drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 struct efx_ef10_filter_table {
  53 /* The RX match field masks supported by this fw & hw, in order of priority */
  54         enum efx_filter_match_flags rx_match_flags[
  55                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  56         unsigned int rx_match_count;
  57
  58         struct {
  59                 unsigned long spec;     /* pointer to spec plus flag bits */
  60 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  61  * used to mark and sweep MAC filters for the device address lists.
  62  */
  63 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  64 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  65 #define EFX_EF10_FILTER_FLAGS           3UL
  66                 u64 handle;             /* firmware handle */
  67         } *entry;
  68         wait_queue_head_t waitq;
  69 /* Shadow of net_device address lists, guarded by mac_lock */
  70 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  71 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  72         struct {
  73                 u8 addr[ETH_ALEN];
  74                 u16 id;
  75         } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
  76           dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  77         int dev_uc_count;               /* negative for PROMISC */
  78         int dev_mc_count;               /* negative for PROMISC/ALLMULTI */
  79 };
  80
  81 /* An arbitrary search limit for the software hash table */
  82 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
  83
  84 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
  85 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
  86
  87 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
  88 {
  89         efx_dword_t reg;
  90
  91         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
  92         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
  93                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
  94 }
  95
  96 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
  97 {
  98         int bar;
  99
 100         bar = efx->type->mem_bar;
 101         return resource_size(&efx->pci_dev->resource[bar]);
 102 }
 103
 104 static bool efx_ef10_is_vf(struct efx_nic *efx)
 105 {
 106         return efx->type->is_vf;
 107 }
 108
 109 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 110 {
 111         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 112         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 113         size_t outlen;
 114         int rc;
 115
 116         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 117                           sizeof(outbuf), &outlen);
 118         if (rc)
 119                 return rc;
 120         if (outlen < sizeof(outbuf))
 121                 return -EIO;
 122
 123         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 124         return 0;
 125 }
 126
 127 #ifdef CONFIG_SFC_SRIOV
 128 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 129 {
 130         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 131         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 132         size_t outlen;
 133         int rc;
 134
 135         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 136                           sizeof(outbuf), &outlen);
 137         if (rc)
 138                 return rc;
 139         if (outlen < sizeof(outbuf))
 140                 return -EIO;
 141
 142         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 143         return 0;
 144 }
 145 #endif
 146
 147 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 148 {
 149         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
 150         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 151         size_t outlen;
 152         int rc;
 153
 154         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 155
 156         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 157                           outbuf, sizeof(outbuf), &outlen);
 158         if (rc)
 159                 return rc;
 160         if (outlen < sizeof(outbuf)) {
 161                 netif_err(efx, drv, efx->net_dev,
 162                           "unable to read datapath firmware capabilities\n");
 163                 return -EIO;
 164         }
 165
 166         nic_data->datapath_caps =
 167                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 168
 169         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 170          */
 171         nic_data->rx_dpcpu_fw_id =
 172                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 173         nic_data->tx_dpcpu_fw_id =
 174                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 175
 176         if (!(nic_data->datapath_caps &
 177               (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
 178                 netif_err(efx, drv, efx->net_dev,
 179                           "current firmware does not support TSO\n");
 180                 return -ENODEV;
 181         }
 182
 183         if (!(nic_data->datapath_caps &
 184               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 185                 netif_err(efx, probe, efx->net_dev,
 186                           "current firmware does not support an RX prefix\n");
 187                 return -ENODEV;
 188         }
 189
 190         return 0;
 191 }
 192
 193 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 194 {
 195         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 196         int rc;
 197
 198         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 199                           outbuf, sizeof(outbuf), NULL);
 200         if (rc)
 201                 return rc;
 202         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 203         return rc > 0 ? rc : -ERANGE;
 204 }
 205
 206 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 207 {
 208         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 209         size_t outlen;
 210         int rc;
 211
 212         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 213
 214         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 215                           outbuf, sizeof(outbuf), &outlen);
 216         if (rc)
 217                 return rc;
 218         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 219                 return -EIO;
 220
 221         ether_addr_copy(mac_address,
 222                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 223         return 0;
 224 }
 225
 226 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 227 {
 228         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 229         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 230         size_t outlen;
 231         int num_addrs, rc;
 232
 233         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 234                        EVB_PORT_ID_ASSIGNED);
 235         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 236                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 237
 238         if (rc)
 239                 return rc;
 240         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 241                 return -EIO;
 242
 243         num_addrs = MCDI_DWORD(outbuf,
 244                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 245
 246         WARN_ON(num_addrs != 1);
 247
 248         ether_addr_copy(mac_address,
 249                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 250
 251         return 0;
 252 }
 253
 254 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 255                                                struct device_attribute *attr,
 256                                                char *buf)
 257 {
 258         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 259
 260         return sprintf(buf, "%d\n",
 261                        ((efx->mcdi->fn_flags) &
 262                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 263                        ? 1 : 0);
 264 }
 265
 266 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 267                                           struct device_attribute *attr,
 268                                           char *buf)
 269 {
 270         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 271
 272         return sprintf(buf, "%d\n",
 273                        ((efx->mcdi->fn_flags) &
 274                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 275                        ? 1 : 0);
 276 }
 277
 278 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 279                    NULL);
 280 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 281
 282 static int efx_ef10_probe(struct efx_nic *efx)
 283 {
 284         struct efx_ef10_nic_data *nic_data;
 285         struct net_device *net_dev = efx->net_dev;
 286         int i, rc;
 287
 288         /* We can have one VI for each 8K region.  However, until we
 289          * use TX option descriptors we need two TX queues per channel.
 290          */
 291         efx->max_channels =
 292                 min_t(unsigned int,
 293                       EFX_MAX_CHANNELS,
 294                       efx_ef10_mem_map_size(efx) /
 295                       (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 296         if (WARN_ON(efx->max_channels == 0))
 297                 return -EIO;
 298
 299         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 300         if (!nic_data)
 301                 return -ENOMEM;
 302         efx->nic_data = nic_data;
 303
 304         /* we assume later that we can copy from this buffer in dwords */
 305         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 306
 307         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 308                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 309         if (rc)
 310                 goto fail1;
 311
 312         /* Get the MC's warm boot count.  In case it's rebooting right
 313          * now, be prepared to retry.
 314          */
 315         i = 0;
 316         for (;;) {
 317                 rc = efx_ef10_get_warm_boot_count(efx);
 318                 if (rc >= 0)
 319                         break;
 320                 if (++i == 5)
 321                         goto fail2;
 322                 ssleep(1);
 323         }
 324         nic_data->warm_boot_count = rc;
 325
 326         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 327
 328         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 329
 330         /* In case we're recovering from a crash (kexec), we want to
 331          * cancel any outstanding request by the previous user of this
 332          * function.  We send a special message using the least
 333          * significant bits of the 'high' (doorbell) register.
 334          */
 335         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 336
 337         rc = efx_mcdi_init(efx);
 338         if (rc)
 339                 goto fail2;
 340
 341         /* Reset (most) configuration for this function */
 342         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 343         if (rc)
 344                 goto fail3;
 345
 346         /* Enable event logging */
 347         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 348         if (rc)
 349                 goto fail3;
 350
 351         rc = device_create_file(&efx->pci_dev->dev,
 352                                 &dev_attr_link_control_flag);
 353         if (rc)
 354                 goto fail3;
 355
 356         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 357         if (rc)
 358                 goto fail4;
 359
 360         rc = efx_ef10_get_pf_index(efx);
 361         if (rc)
 362                 goto fail5;
 363
 364         rc = efx_ef10_init_datapath_caps(efx);
 365         if (rc < 0)
 366                 goto fail5;
 367
 368         efx->rx_packet_len_offset =
 369                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 370
 371         rc = efx_mcdi_port_get_number(efx);
 372         if (rc < 0)
 373                 goto fail5;
 374         efx->port_num = rc;
 375         net_dev->dev_port = rc;
 376
 377         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 378         if (rc)
 379                 goto fail5;
 380
 381         rc = efx_ef10_get_sysclk_freq(efx);
 382         if (rc < 0)
 383                 goto fail5;
 384         efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
 385
 386         /* Check whether firmware supports bug 35388 workaround.
 387          * First try to enable it, then if we get EPERM, just
 388          * ask if it's already enabled
 389          */
 390         rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
 391         if (rc == 0) {
 392                 nic_data->workaround_35388 = true;
 393         } else if (rc == -EPERM) {
 394                 unsigned int enabled;
 395
 396                 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
 397                 if (rc)
 398                         goto fail3;
 399                 nic_data->workaround_35388 = enabled &
 400                         MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
 401         } else if (rc != -ENOSYS && rc != -ENOENT) {
 402                 goto fail5;
 403         }
 404         netif_dbg(efx, probe, efx->net_dev,
 405                   "workaround for bug 35388 is %sabled\n",
 406                   nic_data->workaround_35388 ? "en" : "dis");
 407
 408         rc = efx_mcdi_mon_probe(efx);
 409         if (rc && rc != -EPERM)
 410                 goto fail5;
 411
 412         efx_ptp_probe(efx, NULL);
 413
 414 #ifdef CONFIG_SFC_SRIOV
 415         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 416                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 417                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 418
 419                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 420         } else
 421 #endif
 422                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 423
 424         return 0;
 425
 426 fail5:
 427         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 428 fail4:
 429         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 430 fail3:
 431         efx_mcdi_fini(efx);
 432 fail2:
 433         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 434 fail1:
 435         kfree(nic_data);
 436         efx->nic_data = NULL;
 437         return rc;
 438 }
 439
 440 static int efx_ef10_free_vis(struct efx_nic *efx)
 441 {
 442         MCDI_DECLARE_BUF_ERR(outbuf);
 443         size_t outlen;
 444         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 445                                     outbuf, sizeof(outbuf), &outlen);
 446
 447         /* -EALREADY means nothing to free, so ignore */
 448         if (rc == -EALREADY)
 449                 rc = 0;
 450         if (rc)
 451                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 452                                        rc);
 453         return rc;
 454 }
 455
 456 #ifdef EFX_USE_PIO
 457
 458 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 459 {
 460         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 461         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 462         unsigned int i;
 463         int rc;
 464
 465         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 466
 467         for (i = 0; i < nic_data->n_piobufs; i++) {
 468                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 469                                nic_data->piobuf_handle[i]);
 470                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 471                                   NULL, 0, NULL);
 472                 WARN_ON(rc);
 473         }
 474
 475         nic_data->n_piobufs = 0;
 476 }
 477
 478 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 479 {
 480         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 481         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 482         unsigned int i;
 483         size_t outlen;
 484         int rc = 0;
 485
 486         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 487
 488         for (i = 0; i < n; i++) {
 489                 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 490                                   outbuf, sizeof(outbuf), &outlen);
 491                 if (rc)
 492                         break;
 493                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 494                         rc = -EIO;
 495                         break;
 496                 }
 497                 nic_data->piobuf_handle[i] =
 498                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 499                 netif_dbg(efx, probe, efx->net_dev,
 500                           "allocated PIO buffer %u handle %x\n", i,
 501                           nic_data->piobuf_handle[i]);
 502         }
 503
 504         nic_data->n_piobufs = i;
 505         if (rc)
 506                 efx_ef10_free_piobufs(efx);
 507         return rc;
 508 }
 509
 510 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 511 {
 512         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 513         _MCDI_DECLARE_BUF(inbuf,
 514                           max(MC_CMD_LINK_PIOBUF_IN_LEN,
 515                               MC_CMD_UNLINK_PIOBUF_IN_LEN));
 516         struct efx_channel *channel;
 517         struct efx_tx_queue *tx_queue;
 518         unsigned int offset, index;
 519         int rc;
 520
 521         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 522         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 523
 524         memset(inbuf, 0, sizeof(inbuf));
 525
 526         /* Link a buffer to each VI in the write-combining mapping */
 527         for (index = 0; index < nic_data->n_piobufs; ++index) {
 528                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 529                                nic_data->piobuf_handle[index]);
 530                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 531                                nic_data->pio_write_vi_base + index);
 532                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 533                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 534                                   NULL, 0, NULL);
 535                 if (rc) {
 536                         netif_err(efx, drv, efx->net_dev,
 537                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 538                                   nic_data->pio_write_vi_base + index, index,
 539                                   rc);
 540                         goto fail;
 541                 }
 542                 netif_dbg(efx, probe, efx->net_dev,
 543                           "linked VI %u to PIO buffer %u\n",
 544                           nic_data->pio_write_vi_base + index, index);
 545         }
 546
 547         /* Link a buffer to each TX queue */
 548         efx_for_each_channel(channel, efx) {
 549                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 550                         /* We assign the PIO buffers to queues in
 551                          * reverse order to allow for the following
 552                          * special case.
 553                          */
 554                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 555                                    tx_queue->channel->channel - 1) *
 556                                   efx_piobuf_size);
 557                         index = offset / ER_DZ_TX_PIOBUF_SIZE;
 558                         offset = offset % ER_DZ_TX_PIOBUF_SIZE;
 559
 560                         /* When the host page size is 4K, the first
 561                          * host page in the WC mapping may be within
 562                          * the same VI page as the last TX queue.  We
 563                          * can only link one buffer to each VI.
 564                          */
 565                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 566                                 BUG_ON(index != 0);
 567                                 rc = 0;
 568                         } else {
 569                                 MCDI_SET_DWORD(inbuf,
 570                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 571                                                nic_data->piobuf_handle[index]);
 572                                 MCDI_SET_DWORD(inbuf,
 573                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 574                                                tx_queue->queue);
 575                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 576                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 577                                                   NULL, 0, NULL);
 578                         }
 579
 580                         if (rc) {
 581                                 /* This is non-fatal; the TX path just
 582                                  * won't use PIO for this queue
 583                                  */
 584                                 netif_err(efx, drv, efx->net_dev,
 585                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 586                                           tx_queue->queue, index, rc);
 587                                 tx_queue->piobuf = NULL;
 588                         } else {
 589                                 tx_queue->piobuf =
 590                                         nic_data->pio_write_base +
 591                                         index * EFX_VI_PAGE_SIZE + offset;
 592                                 tx_queue->piobuf_offset = offset;
 593                                 netif_dbg(efx, probe, efx->net_dev,
 594                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 595                                           tx_queue->queue, index,
 596                                           tx_queue->piobuf_offset,
 597                                           tx_queue->piobuf);
 598                         }
 599                 }
 600         }
 601
 602         return 0;
 603
 604 fail:
 605         while (index--) {
 606                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 607                                nic_data->pio_write_vi_base + index);
 608                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 609                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 610                              NULL, 0, NULL);
 611         }
 612         return rc;
 613 }
 614
 615 #else /* !EFX_USE_PIO */
 616
 617 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 618 {
 619         return n == 0 ? 0 : -ENOBUFS;
 620 }
 621
 622 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 623 {
 624         return 0;
 625 }
 626
 627 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 628 {
 629 }
 630
 631 #endif /* EFX_USE_PIO */
 632
 633 static void efx_ef10_remove(struct efx_nic *efx)
 634 {
 635         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 636         int rc;
 637
 638 #ifdef CONFIG_SFC_SRIOV
 639         struct efx_ef10_nic_data *nic_data_pf;
 640         struct pci_dev *pci_dev_pf;
 641         struct efx_nic *efx_pf;
 642         struct ef10_vf *vf;
 643
 644         if (efx->pci_dev->is_virtfn) {
 645                 pci_dev_pf = efx->pci_dev->physfn;
 646                 if (pci_dev_pf) {
 647                         efx_pf = pci_get_drvdata(pci_dev_pf);
 648                         nic_data_pf = efx_pf->nic_data;
 649                         vf = nic_data_pf->vf + nic_data->vf_index;
 650                         vf->efx = NULL;
 651                 } else
 652                         netif_info(efx, drv, efx->net_dev,
 653                                    "Could not get the PF id from VF\n");
 654         }
 655 #endif
 656
 657         efx_ptp_remove(efx);
 658
 659         efx_mcdi_mon_remove(efx);
 660
 661         efx_ef10_rx_free_indir_table(efx);
 662
 663         if (nic_data->wc_membase)
 664                 iounmap(nic_data->wc_membase);
 665
 666         rc = efx_ef10_free_vis(efx);
 667         WARN_ON(rc != 0);
 668
 669         if (!nic_data->must_restore_piobufs)
 670                 efx_ef10_free_piobufs(efx);
 671
 672         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 673         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 674
 675         efx_mcdi_fini(efx);
 676         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 677         kfree(nic_data);
 678 }
 679
 680 static int efx_ef10_probe_pf(struct efx_nic *efx)
 681 {
 682         return efx_ef10_probe(efx);
 683 }
 684
 685 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
 686 {
 687         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
 688
 689         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
 690         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
 691                             NULL, 0, NULL);
 692 }
 693
 694 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
 695 {
 696         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
 697
 698         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
 699         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
 700                             NULL, 0, NULL);
 701 }
 702
 703 int efx_ef10_vport_add_mac(struct efx_nic *efx,
 704                            unsigned int port_id, u8 *mac)
 705 {
 706         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
 707
 708         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
 709         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
 710
 711         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
 712                             sizeof(inbuf), NULL, 0, NULL);
 713 }
 714
 715 int efx_ef10_vport_del_mac(struct efx_nic *efx,
 716                            unsigned int port_id, u8 *mac)
 717 {
 718         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
 719
 720         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
 721         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
 722
 723         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
 724                             sizeof(inbuf), NULL, 0, NULL);
 725 }
 726
 727 #ifdef CONFIG_SFC_SRIOV
 728 static int efx_ef10_probe_vf(struct efx_nic *efx)
 729 {
 730         int rc;
 731         struct pci_dev *pci_dev_pf;
 732
 733         /* If the parent PF has no VF data structure, it doesn't know about this
 734          * VF so fail probe.  The VF needs to be re-created.  This can happen
 735          * if the PF driver is unloaded while the VF is assigned to a guest.
 736          */
 737         pci_dev_pf = efx->pci_dev->physfn;
 738         if (pci_dev_pf) {
 739                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 740                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
 741
 742                 if (!nic_data_pf->vf) {
 743                         netif_info(efx, drv, efx->net_dev,
 744                                    "The VF cannot link to its parent PF; "
 745                                    "please destroy and re-create the VF\n");
 746                         return -EBUSY;
 747                 }
 748         }
 749
 750         rc = efx_ef10_probe(efx);
 751         if (rc)
 752                 return rc;
 753
 754         rc = efx_ef10_get_vf_index(efx);
 755         if (rc)
 756                 goto fail;
 757
 758         if (efx->pci_dev->is_virtfn) {
 759                 if (efx->pci_dev->physfn) {
 760                         struct efx_nic *efx_pf =
 761                                 pci_get_drvdata(efx->pci_dev->physfn);
 762                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
 763                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 764
 765                         nic_data_p->vf[nic_data->vf_index].efx = efx;
 766                         nic_data_p->vf[nic_data->vf_index].pci_dev =
 767                                 efx->pci_dev;
 768                 } else
 769                         netif_info(efx, drv, efx->net_dev,
 770                                    "Could not get the PF id from VF\n");
 771         }
 772
 773         return 0;
 774
 775 fail:
 776         efx_ef10_remove(efx);
 777         return rc;
 778 }
 779 #else
 780 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
 781 {
 782         return 0;
 783 }
 784 #endif
 785
 786 static int efx_ef10_alloc_vis(struct efx_nic *efx,
 787                               unsigned int min_vis, unsigned int max_vis)
 788 {
 789         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
 790         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
 791         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 792         size_t outlen;
 793         int rc;
 794
 795         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
 796         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
 797         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
 798                           outbuf, sizeof(outbuf), &outlen);
 799         if (rc != 0)
 800                 return rc;
 801
 802         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
 803                 return -EIO;
 804
 805         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
 806                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
 807
 808         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
 809         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
 810         return 0;
 811 }
 812
 813 /* Note that the failure path of this function does not free
 814  * resources, as this will be done by efx_ef10_remove().
 815  */
 816 static int efx_ef10_dimension_resources(struct efx_nic *efx)
 817 {
 818         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 819         unsigned int uc_mem_map_size, wc_mem_map_size;
 820         unsigned int min_vis, pio_write_vi_base, max_vis;
 821         void __iomem *membase;
 822         int rc;
 823
 824         min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
 825
 826 #ifdef EFX_USE_PIO
 827         /* Try to allocate PIO buffers if wanted and if the full
 828          * number of PIO buffers would be sufficient to allocate one
 829          * copy-buffer per TX channel.  Failure is non-fatal, as there
 830          * are only a small number of PIO buffers shared between all
 831          * functions of the controller.
 832          */
 833         if (efx_piobuf_size != 0 &&
 834             ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
 835             efx->n_tx_channels) {
 836                 unsigned int n_piobufs =
 837                         DIV_ROUND_UP(efx->n_tx_channels,
 838                                      ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
 839
 840                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
 841                 if (rc)
 842                         netif_err(efx, probe, efx->net_dev,
 843                                   "failed to allocate PIO buffers (%d)\n", rc);
 844                 else
 845                         netif_dbg(efx, probe, efx->net_dev,
 846                                   "allocated %u PIO buffers\n", n_piobufs);
 847         }
 848 #else
 849         nic_data->n_piobufs = 0;
 850 #endif
 851
 852         /* PIO buffers should be mapped with write-combining enabled,
 853          * and we want to make single UC and WC mappings rather than
 854          * several of each (in fact that's the only option if host
 855          * page size is >4K).  So we may allocate some extra VIs just
 856          * for writing PIO buffers through.
 857          *
 858          * The UC mapping contains (min_vis - 1) complete VIs and the
 859          * first half of the next VI.  Then the WC mapping begins with
 860          * the second half of this last VI.
 861          */
 862         uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
 863                                      ER_DZ_TX_PIOBUF);
 864         if (nic_data->n_piobufs) {
 865                 /* pio_write_vi_base rounds down to give the number of complete
 866                  * VIs inside the UC mapping.
 867                  */
 868                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
 869                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
 870                                                nic_data->n_piobufs) *
 871                                               EFX_VI_PAGE_SIZE) -
 872                                    uc_mem_map_size);
 873                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
 874         } else {
 875                 pio_write_vi_base = 0;
 876                 wc_mem_map_size = 0;
 877                 max_vis = min_vis;
 878         }
 879
 880         /* In case the last attached driver failed to free VIs, do it now */
 881         rc = efx_ef10_free_vis(efx);
 882         if (rc != 0)
 883                 return rc;
 884
 885         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
 886         if (rc != 0)
 887                 return rc;
 888
 889         /* If we didn't get enough VIs to map all the PIO buffers, free the
 890          * PIO buffers
 891          */
 892         if (nic_data->n_piobufs &&
 893             nic_data->n_allocated_vis <
 894             pio_write_vi_base + nic_data->n_piobufs) {
 895                 netif_dbg(efx, probe, efx->net_dev,
 896                           "%u VIs are not sufficient to map %u PIO buffers\n",
 897                           nic_data->n_allocated_vis, nic_data->n_piobufs);
 898                 efx_ef10_free_piobufs(efx);
 899         }
 900
 901         /* Shrink the original UC mapping of the memory BAR */
 902         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
 903         if (!membase) {
 904                 netif_err(efx, probe, efx->net_dev,
 905                           "could not shrink memory BAR to %x\n",
 906                           uc_mem_map_size);
 907                 return -ENOMEM;
 908         }
 909         iounmap(efx->membase);
 910         efx->membase = membase;
 911
 912         /* Set up the WC mapping if needed */
 913         if (wc_mem_map_size) {
 914                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
 915                                                   uc_mem_map_size,
 916                                                   wc_mem_map_size);
 917                 if (!nic_data->wc_membase) {
 918                         netif_err(efx, probe, efx->net_dev,
 919                                   "could not allocate WC mapping of size %x\n",
 920                                   wc_mem_map_size);
 921                         return -ENOMEM;
 922                 }
 923                 nic_data->pio_write_vi_base = pio_write_vi_base;
 924                 nic_data->pio_write_base =
 925                         nic_data->wc_membase +
 926                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
 927                          uc_mem_map_size);
 928
 929                 rc = efx_ef10_link_piobufs(efx);
 930                 if (rc)
 931                         efx_ef10_free_piobufs(efx);
 932         }
 933
 934         netif_dbg(efx, probe, efx->net_dev,
 935                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
 936                   &efx->membase_phys, efx->membase, uc_mem_map_size,
 937                   nic_data->wc_membase, wc_mem_map_size);
 938
 939         return 0;
 940 }
 941
 942 static int efx_ef10_init_nic(struct efx_nic *efx)
 943 {
 944         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 945         int rc;
 946
 947         if (nic_data->must_check_datapath_caps) {
 948                 rc = efx_ef10_init_datapath_caps(efx);
 949                 if (rc)
 950                         return rc;
 951                 nic_data->must_check_datapath_caps = false;
 952         }
 953
 954         if (nic_data->must_realloc_vis) {
 955                 /* We cannot let the number of VIs change now */
 956                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
 957                                         nic_data->n_allocated_vis);
 958                 if (rc)
 959                         return rc;
 960                 nic_data->must_realloc_vis = false;
 961         }
 962
 963         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
 964                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
 965                 if (rc == 0) {
 966                         rc = efx_ef10_link_piobufs(efx);
 967                         if (rc)
 968                                 efx_ef10_free_piobufs(efx);
 969                 }
 970
 971                 /* Log an error on failure, but this is non-fatal */
 972                 if (rc)
 973                         netif_err(efx, drv, efx->net_dev,
 974                                   "failed to restore PIO buffers (%d)\n", rc);
 975                 nic_data->must_restore_piobufs = false;
 976         }
 977
 978         /* don't fail init if RSS setup doesn't work */
 979         efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
 980
 981         return 0;
 982 }
 983
 984 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
 985 {
 986         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 987
 988         /* All our allocations have been reset */
 989         nic_data->must_realloc_vis = true;
 990         nic_data->must_restore_filters = true;
 991         nic_data->must_restore_piobufs = true;
 992         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 993 }
 994
 995 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
 996 {
 997         if (reason == RESET_TYPE_MC_FAILURE)
 998                 return RESET_TYPE_DATAPATH;
 999
1000         return efx_mcdi_map_reset_reason(reason);
1001 }
1002
1003 static int efx_ef10_map_reset_flags(u32 *flags)
1004 {
1005         enum {
1006                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1007                                    ETH_RESET_SHARED_SHIFT),
1008                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1009                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1010                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1011                                  ETH_RESET_SHARED_SHIFT)
1012         };
1013
1014         /* We assume for now that our PCI function is permitted to
1015          * reset everything.
1016          */
1017
1018         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1019                 *flags &= ~EF10_RESET_MC;
1020                 return RESET_TYPE_WORLD;
1021         }
1022
1023         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1024                 *flags &= ~EF10_RESET_PORT;
1025                 return RESET_TYPE_ALL;
1026         }
1027
1028         /* no invisible reset implemented */
1029
1030         return -EINVAL;
1031 }
1032
1033 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1034 {
1035         int rc = efx_mcdi_reset(efx, reset_type);
1036
1037         /* If it was a port reset, trigger reallocation of MC resources.
1038          * Note that on an MC reset nothing needs to be done now because we'll
1039          * detect the MC reset later and handle it then.
1040          * For an FLR, we never get an MC reset event, but the MC has reset all
1041          * resources assigned to us, so we have to trigger reallocation now.
1042          */
1043         if ((reset_type == RESET_TYPE_ALL ||
1044              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1045                 efx_ef10_reset_mc_allocations(efx);
1046         return rc;
1047 }
1048
1049 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1050         [EF10_STAT_ ## ext_name] =                              \
1051         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1052 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1053         [EF10_STAT_ ## int_name] =                              \
1054         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1055 #define EF10_OTHER_STAT(ext_name)                               \
1056         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1057 #define GENERIC_SW_STAT(ext_name)                               \
1058         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1059
1060 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1061         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1062         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1063         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1064         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1065         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1066         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1067         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1068         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1069         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1070         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1071         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1072         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1073         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1074         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1075         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1076         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1077         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1078         EF10_OTHER_STAT(port_rx_good_bytes),
1079         EF10_OTHER_STAT(port_rx_bad_bytes),
1080         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1081         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1082         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1083         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1084         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1085         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1086         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1087         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1088         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1089         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1090         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1091         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1092         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1093         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1094         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1095         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1096         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1097         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1098         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1099         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1100         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1101         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1102         GENERIC_SW_STAT(rx_nodesc_trunc),
1103         GENERIC_SW_STAT(rx_noskb_drops),
1104         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1105         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1106         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1107         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1108         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1109         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1110         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1111         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1112         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1113         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1114         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1115         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1116         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1117         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1118         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1119         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1120         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1121         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1122         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1123         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1124         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1125         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1126         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1127         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1128         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1129         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1130         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1131         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1132         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1133         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1134 };
1135
1136 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1137                                (1ULL << EF10_STAT_port_tx_packets) |    \
1138                                (1ULL << EF10_STAT_port_tx_pause) |      \
1139                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1140                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1141                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1142                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1143                                (1ULL <<                                 \
1144                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1145                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1146                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1147                                (1ULL << EF10_STAT_port_rx_packets) |    \
1148                                (1ULL << EF10_STAT_port_rx_good) |       \
1149                                (1ULL << EF10_STAT_port_rx_bad) |        \
1150                                (1ULL << EF10_STAT_port_rx_pause) |      \
1151                                (1ULL << EF10_STAT_port_rx_control) |    \
1152                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1153                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1154                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1155                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1156                                (1ULL << EF10_STAT_port_rx_64) |         \
1157                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1158                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1159                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1160                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1161                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1162                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1163                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1164                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1165                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1166                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1167                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1168                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1169
1170 /* These statistics are only provided by the 10G MAC.  For a 10G/40G
1171  * switchable port we do not expose these because they might not
1172  * include all the packets they should.
1173  */
1174 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1175                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1176                                  (1ULL << EF10_STAT_port_tx_64) |       \
1177                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1178                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1179                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1180                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1181                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1182                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1183
1184 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1185  * switchable port we do expose these because the errors will otherwise
1186  * be silent.
1187  */
1188 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1189                                   (1ULL << EF10_STAT_port_rx_length_error))
1190
1191 /* These statistics are only provided if the firmware supports the
1192  * capability PM_AND_RXDP_COUNTERS.
1193  */
1194 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1195         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1196         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1197         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1198         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1199         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1200         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1201         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1202         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1203         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1204         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1205         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1206         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1207
1208 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1209 {
1210         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1211         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1212         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1213
1214         if (!(efx->mcdi->fn_flags &
1215               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1216                 return 0;
1217
1218         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1219                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1220         else
1221                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1222
1223         if (nic_data->datapath_caps &
1224             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1225                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1226
1227         return raw_mask;
1228 }
1229
1230 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1231 {
1232         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1233         u64 raw_mask[2];
1234
1235         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1236
1237         /* Only show vadaptor stats when EVB capability is present */
1238         if (nic_data->datapath_caps &
1239             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1240                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1241                 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1242         } else {
1243                 raw_mask[1] = 0;
1244         }
1245
1246 #if BITS_PER_LONG == 64
1247         mask[0] = raw_mask[0];
1248         mask[1] = raw_mask[1];
1249 #else
1250         mask[0] = raw_mask[0] & 0xffffffff;
1251         mask[1] = raw_mask[0] >> 32;
1252         mask[2] = raw_mask[1] & 0xffffffff;
1253         mask[3] = raw_mask[1] >> 32;
1254 #endif
1255 }
1256
1257 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1258 {
1259         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1260
1261         efx_ef10_get_stat_mask(efx, mask);
1262         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1263                                       mask, names);
1264 }
1265
1266 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1267                                            struct rtnl_link_stats64 *core_stats)
1268 {
1269         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1270         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1271         u64 *stats = nic_data->stats;
1272         size_t stats_count = 0, index;
1273
1274         efx_ef10_get_stat_mask(efx, mask);
1275
1276         if (full_stats) {
1277                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1278                         if (efx_ef10_stat_desc[index].name) {
1279                                 *full_stats++ = stats[index];
1280                                 ++stats_count;
1281                         }
1282                 }
1283         }
1284
1285         if (!core_stats)
1286                 return stats_count;
1287
1288         if (nic_data->datapath_caps &
1289                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1290                 /* Use vadaptor stats. */
1291                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1292                                          stats[EF10_STAT_rx_multicast] +
1293                                          stats[EF10_STAT_rx_broadcast];
1294                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1295                                          stats[EF10_STAT_tx_multicast] +
1296                                          stats[EF10_STAT_tx_broadcast];
1297                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1298                                        stats[EF10_STAT_rx_multicast_bytes] +
1299                                        stats[EF10_STAT_rx_broadcast_bytes];
1300                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1301                                        stats[EF10_STAT_tx_multicast_bytes] +
1302                                        stats[EF10_STAT_tx_broadcast_bytes];
1303                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1304                                          stats[GENERIC_STAT_rx_noskb_drops];
1305                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1306                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1307                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1308                 core_stats->rx_errors = core_stats->rx_crc_errors;
1309                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1310         } else {
1311                 /* Use port stats. */
1312                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1313                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1314                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1315                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1316                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1317                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1318                                          stats[GENERIC_STAT_rx_noskb_drops];
1319                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1320                 core_stats->rx_length_errors =
1321                                 stats[EF10_STAT_port_rx_gtjumbo] +
1322                                 stats[EF10_STAT_port_rx_length_error];
1323                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1324                 core_stats->rx_frame_errors =
1325                                 stats[EF10_STAT_port_rx_align_error];
1326                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1327                 core_stats->rx_errors = (core_stats->rx_length_errors +
1328                                          core_stats->rx_crc_errors +
1329                                          core_stats->rx_frame_errors);
1330         }
1331
1332         return stats_count;
1333 }
1334
1335 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1336 {
1337         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1338         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1339         __le64 generation_start, generation_end;
1340         u64 *stats = nic_data->stats;
1341         __le64 *dma_stats;
1342
1343         efx_ef10_get_stat_mask(efx, mask);
1344
1345         dma_stats = efx->stats_buffer.addr;
1346         nic_data = efx->nic_data;
1347
1348         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1349         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1350                 return 0;
1351         rmb();
1352         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1353                              stats, efx->stats_buffer.addr, false);
1354         rmb();
1355         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1356         if (generation_end != generation_start)
1357                 return -EAGAIN;
1358
1359         /* Update derived statistics */
1360         efx_nic_fix_nodesc_drop_stat(efx,
1361                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1362         stats[EF10_STAT_port_rx_good_bytes] =
1363                 stats[EF10_STAT_port_rx_bytes] -
1364                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1365         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1366                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1367         efx_update_sw_stats(efx, stats);
1368         return 0;
1369 }
1370
1371
1372 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1373                                        struct rtnl_link_stats64 *core_stats)
1374 {
1375         int retry;
1376
1377         /* If we're unlucky enough to read statistics during the DMA, wait
1378          * up to 10ms for it to finish (typically takes <500us)
1379          */
1380         for (retry = 0; retry < 100; ++retry) {
1381                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1382                         break;
1383                 udelay(100);
1384         }
1385
1386         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1387 }
1388
1389 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1390 {
1391         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1392         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1393         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1394         __le64 generation_start, generation_end;
1395         u64 *stats = nic_data->stats;
1396         u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1397         struct efx_buffer stats_buf;
1398         __le64 *dma_stats;
1399         int rc;
1400
1401         spin_unlock_bh(&efx->stats_lock);
1402
1403         if (in_interrupt()) {
1404                 /* If in atomic context, cannot update stats.  Just update the
1405                  * software stats and return so the caller can continue.
1406                  */
1407                 spin_lock_bh(&efx->stats_lock);
1408                 efx_update_sw_stats(efx, stats);
1409                 return 0;
1410         }
1411
1412         efx_ef10_get_stat_mask(efx, mask);
1413
1414         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1415         if (rc) {
1416                 spin_lock_bh(&efx->stats_lock);
1417                 return rc;
1418         }
1419
1420         dma_stats = stats_buf.addr;
1421         dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1422
1423         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1424         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1425                               MAC_STATS_IN_DMA, 1);
1426         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1427         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1428
1429         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1430                                 NULL, 0, NULL);
1431         spin_lock_bh(&efx->stats_lock);
1432         if (rc) {
1433                 /* Expect ENOENT if DMA queues have not been set up */
1434                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1435                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1436                                                sizeof(inbuf), NULL, 0, rc);
1437                 goto out;
1438         }
1439
1440         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1441         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1442                 WARN_ON_ONCE(1);
1443                 goto out;
1444         }
1445         rmb();
1446         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1447                              stats, stats_buf.addr, false);
1448         rmb();
1449         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1450         if (generation_end != generation_start) {
1451                 rc = -EAGAIN;
1452                 goto out;
1453         }
1454
1455         efx_update_sw_stats(efx, stats);
1456 out:
1457         efx_nic_free_buffer(efx, &stats_buf);
1458         return rc;
1459 }
1460
1461 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1462                                        struct rtnl_link_stats64 *core_stats)
1463 {
1464         if (efx_ef10_try_update_nic_stats_vf(efx))
1465                 return 0;
1466
1467         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1468 }
1469
1470 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1471 {
1472         struct efx_nic *efx = channel->efx;
1473         unsigned int mode, value;
1474         efx_dword_t timer_cmd;
1475
1476         if (channel->irq_moderation) {
1477                 mode = 3;
1478                 value = channel->irq_moderation - 1;
1479         } else {
1480                 mode = 0;
1481                 value = 0;
1482         }
1483
1484         if (EFX_EF10_WORKAROUND_35388(efx)) {
1485                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1486                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1487                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1488                                      ERF_DD_EVQ_IND_TIMER_VAL, value);
1489                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1490                                 channel->channel);
1491         } else {
1492                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1493                                      ERF_DZ_TC_TIMER_VAL, value);
1494                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1495                                 channel->channel);
1496         }
1497 }
1498
1499 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1500                                 struct ethtool_wolinfo *wol) {}
1501
1502 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1503 {
1504         return -EOPNOTSUPP;
1505 }
1506
1507 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1508 {
1509         wol->supported = 0;
1510         wol->wolopts = 0;
1511         memset(&wol->sopass, 0, sizeof(wol->sopass));
1512 }
1513
1514 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1515 {
1516         if (type != 0)
1517                 return -EINVAL;
1518         return 0;
1519 }
1520
1521 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1522                                   const efx_dword_t *hdr, size_t hdr_len,
1523                                   const efx_dword_t *sdu, size_t sdu_len)
1524 {
1525         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1526         u8 *pdu = nic_data->mcdi_buf.addr;
1527
1528         memcpy(pdu, hdr, hdr_len);
1529         memcpy(pdu + hdr_len, sdu, sdu_len);
1530         wmb();
1531
1532         /* The hardware provides 'low' and 'high' (doorbell) registers
1533          * for passing the 64-bit address of an MCDI request to
1534          * firmware.  However the dwords are swapped by firmware.  The
1535          * least significant bits of the doorbell are then 0 for all
1536          * MCDI requests due to alignment.
1537          */
1538         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1539                     ER_DZ_MC_DB_LWRD);
1540         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1541                     ER_DZ_MC_DB_HWRD);
1542 }
1543
1544 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1545 {
1546         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1547         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1548
1549         rmb();
1550         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1551 }
1552
1553 static void
1554 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1555                             size_t offset, size_t outlen)
1556 {
1557         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1558         const u8 *pdu = nic_data->mcdi_buf.addr;
1559
1560         memcpy(outbuf, pdu + offset, outlen);
1561 }
1562
1563 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1564 {
1565         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1566         int rc;
1567
1568         rc = efx_ef10_get_warm_boot_count(efx);
1569         if (rc < 0) {
1570                 /* The firmware is presumably in the process of
1571                  * rebooting.  However, we are supposed to report each
1572                  * reboot just once, so we must only do that once we
1573                  * can read and store the updated warm boot count.
1574                  */
1575                 return 0;
1576         }
1577
1578         if (rc == nic_data->warm_boot_count)
1579                 return 0;
1580
1581         nic_data->warm_boot_count = rc;
1582
1583         /* All our allocations have been reset */
1584         efx_ef10_reset_mc_allocations(efx);
1585
1586         /* Driver-created vswitches and vports must be re-created */
1587         nic_data->must_probe_vswitching = true;
1588         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1589
1590         /* The datapath firmware might have been changed */
1591         nic_data->must_check_datapath_caps = true;
1592
1593         /* MAC statistics have been cleared on the NIC; clear the local
1594          * statistic that we update with efx_update_diff_stat().
1595          */
1596         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1597
1598         return -EIO;
1599 }
1600
1601 /* Handle an MSI interrupt
1602  *
1603  * Handle an MSI hardware interrupt.  This routine schedules event
1604  * queue processing.  No interrupt acknowledgement cycle is necessary.
1605  * Also, we never need to check that the interrupt is for us, since
1606  * MSI interrupts cannot be shared.
1607  */
1608 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1609 {
1610         struct efx_msi_context *context = dev_id;
1611         struct efx_nic *efx = context->efx;
1612
1613         netif_vdbg(efx, intr, efx->net_dev,
1614                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1615
1616         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1617                 /* Note test interrupts */
1618                 if (context->index == efx->irq_level)
1619                         efx->last_irq_cpu = raw_smp_processor_id();
1620
1621                 /* Schedule processing of the channel */
1622                 efx_schedule_channel_irq(efx->channel[context->index]);
1623         }
1624
1625         return IRQ_HANDLED;
1626 }
1627
1628 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1629 {
1630         struct efx_nic *efx = dev_id;
1631         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1632         struct efx_channel *channel;
1633         efx_dword_t reg;
1634         u32 queues;
1635
1636         /* Read the ISR which also ACKs the interrupts */
1637         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1638         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1639
1640         if (queues == 0)
1641                 return IRQ_NONE;
1642
1643         if (likely(soft_enabled)) {
1644                 /* Note test interrupts */
1645                 if (queues & (1U << efx->irq_level))
1646                         efx->last_irq_cpu = raw_smp_processor_id();
1647
1648                 efx_for_each_channel(channel, efx) {
1649                         if (queues & 1)
1650                                 efx_schedule_channel_irq(channel);
1651                         queues >>= 1;
1652                 }
1653         }
1654
1655         netif_vdbg(efx, intr, efx->net_dev,
1656                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1657                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1658
1659         return IRQ_HANDLED;
1660 }
1661
1662 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1663 {
1664         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1665
1666         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1667
1668         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1669         (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1670                             inbuf, sizeof(inbuf), NULL, 0, NULL);
1671 }
1672
1673 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1674 {
1675         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1676                                     (tx_queue->ptr_mask + 1) *
1677                                     sizeof(efx_qword_t),
1678                                     GFP_KERNEL);
1679 }
1680
1681 /* This writes to the TX_DESC_WPTR and also pushes data */
1682 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1683                                          const efx_qword_t *txd)
1684 {
1685         unsigned int write_ptr;
1686         efx_oword_t reg;
1687
1688         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1689         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1690         reg.qword[0] = *txd;
1691         efx_writeo_page(tx_queue->efx, &reg,
1692                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
1693 }
1694
1695 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1696 {
1697         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1698                                                        EFX_BUF_SIZE));
1699         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1700         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1701         struct efx_channel *channel = tx_queue->channel;
1702         struct efx_nic *efx = tx_queue->efx;
1703         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1704         size_t inlen;
1705         dma_addr_t dma_addr;
1706         efx_qword_t *txd;
1707         int rc;
1708         int i;
1709         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
1710
1711         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1712         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1713         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1714         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1715         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1716                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1717                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1718         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1719         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
1720
1721         dma_addr = tx_queue->txd.buf.dma_addr;
1722
1723         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1724                   tx_queue->queue, entries, (u64)dma_addr);
1725
1726         for (i = 0; i < entries; ++i) {
1727                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1728                 dma_addr += EFX_BUF_SIZE;
1729         }
1730
1731         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1732
1733         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1734                           NULL, 0, NULL);
1735         if (rc)
1736                 goto fail;
1737
1738         /* A previous user of this TX queue might have set us up the
1739          * bomb by writing a descriptor to the TX push collector but
1740          * not the doorbell.  (Each collector belongs to a port, not a
1741          * queue or function, so cannot easily be reset.)  We must
1742          * attempt to push a no-op descriptor in its place.
1743          */
1744         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1745         tx_queue->insert_count = 1;
1746         txd = efx_tx_desc(tx_queue, 0);
1747         EFX_POPULATE_QWORD_4(*txd,
1748                              ESF_DZ_TX_DESC_IS_OPT, true,
1749                              ESF_DZ_TX_OPTION_TYPE,
1750                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1751                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1752                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1753         tx_queue->write_count = 1;
1754         wmb();
1755         efx_ef10_push_tx_desc(tx_queue, txd);
1756
1757         return;
1758
1759 fail:
1760         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1761                     tx_queue->queue);
1762 }
1763
1764 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1765 {
1766         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1767         MCDI_DECLARE_BUF_ERR(outbuf);
1768         struct efx_nic *efx = tx_queue->efx;
1769         size_t outlen;
1770         int rc;
1771
1772         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1773                        tx_queue->queue);
1774
1775         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1776                           outbuf, sizeof(outbuf), &outlen);
1777
1778         if (rc && rc != -EALREADY)
1779                 goto fail;
1780
1781         return;
1782
1783 fail:
1784         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1785                                outbuf, outlen, rc);
1786 }
1787
1788 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1789 {
1790         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1791 }
1792
1793 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1794 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1795 {
1796         unsigned int write_ptr;
1797         efx_dword_t reg;
1798
1799         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1800         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1801         efx_writed_page(tx_queue->efx, &reg,
1802                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1803 }
1804
1805 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1806 {
1807         unsigned int old_write_count = tx_queue->write_count;
1808         struct efx_tx_buffer *buffer;
1809         unsigned int write_ptr;
1810         efx_qword_t *txd;
1811
1812         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1813
1814         do {
1815                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1816                 buffer = &tx_queue->buffer[write_ptr];
1817                 txd = efx_tx_desc(tx_queue, write_ptr);
1818                 ++tx_queue->write_count;
1819
1820                 /* Create TX descriptor ring entry */
1821                 if (buffer->flags & EFX_TX_BUF_OPTION) {
1822                         *txd = buffer->option;
1823                 } else {
1824                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1825                         EFX_POPULATE_QWORD_3(
1826                                 *txd,
1827                                 ESF_DZ_TX_KER_CONT,
1828                                 buffer->flags & EFX_TX_BUF_CONT,
1829                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1830                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1831                 }
1832         } while (tx_queue->write_count != tx_queue->insert_count);
1833
1834         wmb(); /* Ensure descriptors are written before they are fetched */
1835
1836         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1837                 txd = efx_tx_desc(tx_queue,
1838                                   old_write_count & tx_queue->ptr_mask);
1839                 efx_ef10_push_tx_desc(tx_queue, txd);
1840                 ++tx_queue->pushes;
1841         } else {
1842                 efx_ef10_notify_tx_desc(tx_queue);
1843         }
1844 }
1845
1846 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1847                                       bool exclusive, unsigned *context_size)
1848 {
1849         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1850         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1851         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1852         size_t outlen;
1853         int rc;
1854         u32 alloc_type = exclusive ?
1855                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1856                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1857         unsigned rss_spread = exclusive ?
1858                                 efx->rss_spread :
1859                                 min(rounddown_pow_of_two(efx->rss_spread),
1860                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1861
1862         if (!exclusive && rss_spread == 1) {
1863                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1864                 if (context_size)
1865                         *context_size = 1;
1866                 return 0;
1867         }
1868
1869         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1870                        nic_data->vport_id);
1871         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1872         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
1873
1874         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1875                 outbuf, sizeof(outbuf), &outlen);
1876         if (rc != 0)
1877                 return rc;
1878
1879         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1880                 return -EIO;
1881
1882         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1883
1884         if (context_size)
1885                 *context_size = rss_spread;
1886
1887         return 0;
1888 }
1889
1890 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1891 {
1892         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1893         int rc;
1894
1895         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1896                        context);
1897
1898         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1899                             NULL, 0, NULL);
1900         WARN_ON(rc != 0);
1901 }
1902
1903 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1904                                        const u32 *rx_indir_table)
1905 {
1906         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1907         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1908         int i, rc;
1909
1910         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1911                        context);
1912         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1913                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1914
1915         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1916                 MCDI_PTR(tablebuf,
1917                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1918                                 (u8) rx_indir_table[i];
1919
1920         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1921                           sizeof(tablebuf), NULL, 0, NULL);
1922         if (rc != 0)
1923                 return rc;
1924
1925         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1926                        context);
1927         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1928                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1929         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1930                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1931                         efx->rx_hash_key[i];
1932
1933         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1934                             sizeof(keybuf), NULL, 0, NULL);
1935 }
1936
1937 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1938 {
1939         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1940
1941         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1942                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1943         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1944 }
1945
1946 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1947                                               unsigned *context_size)
1948 {
1949         u32 new_rx_rss_context;
1950         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1951         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1952                                             false, context_size);
1953
1954         if (rc != 0)
1955                 return rc;
1956
1957         nic_data->rx_rss_context = new_rx_rss_context;
1958         nic_data->rx_rss_context_exclusive = false;
1959         efx_set_default_rx_indir_table(efx);
1960         return 0;
1961 }
1962
1963 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
1964                                                  const u32 *rx_indir_table)
1965 {
1966         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1967         int rc;
1968         u32 new_rx_rss_context;
1969
1970         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
1971             !nic_data->rx_rss_context_exclusive) {
1972                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1973                                                 true, NULL);
1974                 if (rc == -EOPNOTSUPP)
1975                         return rc;
1976                 else if (rc != 0)
1977                         goto fail1;
1978         } else {
1979                 new_rx_rss_context = nic_data->rx_rss_context;
1980         }
1981
1982         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
1983                                          rx_indir_table);
1984         if (rc != 0)
1985                 goto fail2;
1986
1987         if (nic_data->rx_rss_context != new_rx_rss_context)
1988                 efx_ef10_rx_free_indir_table(efx);
1989         nic_data->rx_rss_context = new_rx_rss_context;
1990         nic_data->rx_rss_context_exclusive = true;
1991         if (rx_indir_table != efx->rx_indir_table)
1992                 memcpy(efx->rx_indir_table, rx_indir_table,
1993                        sizeof(efx->rx_indir_table));
1994         return 0;
1995
1996 fail2:
1997         if (new_rx_rss_context != nic_data->rx_rss_context)
1998                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
1999 fail1:
2000         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2001         return rc;
2002 }
2003
2004 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2005                                           const u32 *rx_indir_table)
2006 {
2007         int rc;
2008
2009         if (efx->rss_spread == 1)
2010                 return 0;
2011
2012         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2013
2014         if (rc == -ENOBUFS && !user) {
2015                 unsigned context_size;
2016                 bool mismatch = false;
2017                 size_t i;
2018
2019                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2020                      i++)
2021                         mismatch = rx_indir_table[i] !=
2022                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
2023
2024                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2025                 if (rc == 0) {
2026                         if (context_size != efx->rss_spread)
2027                                 netif_warn(efx, probe, efx->net_dev,
2028                                            "Could not allocate an exclusive RSS"
2029                                            " context; allocated a shared one of"
2030                                            " different size."
2031                                            " Wanted %u, got %u.\n",
2032                                            efx->rss_spread, context_size);
2033                         else if (mismatch)
2034                                 netif_warn(efx, probe, efx->net_dev,
2035                                            "Could not allocate an exclusive RSS"
2036                                            " context; allocated a shared one but"
2037                                            " could not apply custom"
2038                                            " indirection.\n");
2039                         else
2040                                 netif_info(efx, probe, efx->net_dev,
2041                                            "Could not allocate an exclusive RSS"
2042                                            " context; allocated a shared one.\n");
2043                 }
2044         }
2045         return rc;
2046 }
2047
2048 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2049                                           const u32 *rx_indir_table
2050                                           __attribute__ ((unused)))
2051 {
2052         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2053
2054         if (user)
2055                 return -EOPNOTSUPP;
2056         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2057                 return 0;
2058         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2059 }
2060
2061 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2062 {
2063         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2064                                     (rx_queue->ptr_mask + 1) *
2065                                     sizeof(efx_qword_t),
2066                                     GFP_KERNEL);
2067 }
2068
2069 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2070 {
2071         MCDI_DECLARE_BUF(inbuf,
2072                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2073                                                 EFX_BUF_SIZE));
2074         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2075         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2076         struct efx_nic *efx = rx_queue->efx;
2077         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2078         size_t inlen;
2079         dma_addr_t dma_addr;
2080         int rc;
2081         int i;
2082         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2083
2084         rx_queue->scatter_n = 0;
2085         rx_queue->scatter_len = 0;
2086
2087         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2088         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2089         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2090         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2091                        efx_rx_queue_index(rx_queue));
2092         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2093                               INIT_RXQ_IN_FLAG_PREFIX, 1,
2094                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2095         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2096         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2097
2098         dma_addr = rx_queue->rxd.buf.dma_addr;
2099
2100         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2101                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2102
2103         for (i = 0; i < entries; ++i) {
2104                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2105                 dma_addr += EFX_BUF_SIZE;
2106         }
2107
2108         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2109
2110         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2111                           NULL, 0, NULL);
2112         if (rc)
2113                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2114                             efx_rx_queue_index(rx_queue));
2115 }
2116
2117 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2118 {
2119         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2120         MCDI_DECLARE_BUF_ERR(outbuf);
2121         struct efx_nic *efx = rx_queue->efx;
2122         size_t outlen;
2123         int rc;
2124
2125         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2126                        efx_rx_queue_index(rx_queue));
2127
2128         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2129                           outbuf, sizeof(outbuf), &outlen);
2130
2131         if (rc && rc != -EALREADY)
2132                 goto fail;
2133
2134         return;
2135
2136 fail:
2137         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2138                                outbuf, outlen, rc);
2139 }
2140
2141 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2142 {
2143         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2144 }
2145
2146 /* This creates an entry in the RX descriptor queue */
2147 static inline void
2148 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2149 {
2150         struct efx_rx_buffer *rx_buf;
2151         efx_qword_t *rxd;
2152
2153         rxd = efx_rx_desc(rx_queue, index);
2154         rx_buf = efx_rx_buffer(rx_queue, index);
2155         EFX_POPULATE_QWORD_2(*rxd,
2156                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2157                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2158 }
2159
2160 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2161 {
2162         struct efx_nic *efx = rx_queue->efx;
2163         unsigned int write_count;
2164         efx_dword_t reg;
2165
2166         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2167         write_count = rx_queue->added_count & ~7;
2168         if (rx_queue->notified_count == write_count)
2169                 return;
2170
2171         do
2172                 efx_ef10_build_rx_desc(
2173                         rx_queue,
2174                         rx_queue->notified_count & rx_queue->ptr_mask);
2175         while (++rx_queue->notified_count != write_count);
2176
2177         wmb();
2178         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2179                              write_count & rx_queue->ptr_mask);
2180         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2181                         efx_rx_queue_index(rx_queue));
2182 }
2183
2184 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2185
2186 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2187 {
2188         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2189         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2190         efx_qword_t event;
2191
2192         EFX_POPULATE_QWORD_2(event,
2193                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2194                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2195
2196         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2197
2198         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2199          * already swapped the data to little-endian order.
2200          */
2201         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2202                sizeof(efx_qword_t));
2203
2204         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2205                            inbuf, sizeof(inbuf), 0,
2206                            efx_ef10_rx_defer_refill_complete, 0);
2207 }
2208
2209 static void
2210 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2211                                   int rc, efx_dword_t *outbuf,
2212                                   size_t outlen_actual)
2213 {
2214         /* nothing to do */
2215 }
2216
2217 static int efx_ef10_ev_probe(struct efx_channel *channel)
2218 {
2219         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2220                                     (channel->eventq_mask + 1) *
2221                                     sizeof(efx_qword_t),
2222                                     GFP_KERNEL);
2223 }
2224
2225 static int efx_ef10_ev_init(struct efx_channel *channel)
2226 {
2227         MCDI_DECLARE_BUF(inbuf,
2228                          MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2229                                                 EFX_BUF_SIZE));
2230         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2231         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2232         struct efx_nic *efx = channel->efx;
2233         struct efx_ef10_nic_data *nic_data;
2234         bool supports_rx_merge;
2235         size_t inlen, outlen;
2236         dma_addr_t dma_addr;
2237         int rc;
2238         int i;
2239
2240         nic_data = efx->nic_data;
2241         supports_rx_merge =
2242                 !!(nic_data->datapath_caps &
2243                    1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2244
2245         /* Fill event queue with all ones (i.e. empty events) */
2246         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2247
2248         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2249         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2250         /* INIT_EVQ expects index in vector table, not absolute */
2251         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2252         MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2253                               INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2254                               INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2255                               INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2256                               INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2257         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2258                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2259         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2260         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2261         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2262                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2263         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2264
2265         dma_addr = channel->eventq.buf.dma_addr;
2266         for (i = 0; i < entries; ++i) {
2267                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2268                 dma_addr += EFX_BUF_SIZE;
2269         }
2270
2271         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2272
2273         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2274                           outbuf, sizeof(outbuf), &outlen);
2275         /* IRQ return is ignored */
2276         return rc;
2277 }
2278
2279 static void efx_ef10_ev_fini(struct efx_channel *channel)
2280 {
2281         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2282         MCDI_DECLARE_BUF_ERR(outbuf);
2283         struct efx_nic *efx = channel->efx;
2284         size_t outlen;
2285         int rc;
2286
2287         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2288
2289         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2290                           outbuf, sizeof(outbuf), &outlen);
2291
2292         if (rc && rc != -EALREADY)
2293                 goto fail;
2294
2295         return;
2296
2297 fail:
2298         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2299                                outbuf, outlen, rc);
2300 }
2301
2302 static void efx_ef10_ev_remove(struct efx_channel *channel)
2303 {
2304         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2305 }
2306
2307 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2308                                            unsigned int rx_queue_label)
2309 {
2310         struct efx_nic *efx = rx_queue->efx;
2311
2312         netif_info(efx, hw, efx->net_dev,
2313                    "rx event arrived on queue %d labeled as queue %u\n",
2314                    efx_rx_queue_index(rx_queue), rx_queue_label);
2315
2316         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2317 }
2318
2319 static void
2320 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2321                              unsigned int actual, unsigned int expected)
2322 {
2323         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2324         struct efx_nic *efx = rx_queue->efx;
2325
2326         netif_info(efx, hw, efx->net_dev,
2327                    "dropped %d events (index=%d expected=%d)\n",
2328                    dropped, actual, expected);
2329
2330         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2331 }
2332
2333 /* partially received RX was aborted. clean up. */
2334 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2335 {
2336         unsigned int rx_desc_ptr;
2337
2338         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2339                   "scattered RX aborted (dropping %u buffers)\n",
2340                   rx_queue->scatter_n);
2341
2342         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2343
2344         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2345                       0, EFX_RX_PKT_DISCARD);
2346
2347         rx_queue->removed_count += rx_queue->scatter_n;
2348         rx_queue->scatter_n = 0;
2349         rx_queue->scatter_len = 0;
2350         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2351 }
2352
2353 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2354                                     const efx_qword_t *event)
2355 {
2356         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2357         unsigned int n_descs, n_packets, i;
2358         struct efx_nic *efx = channel->efx;
2359         struct efx_rx_queue *rx_queue;
2360         bool rx_cont;
2361         u16 flags = 0;
2362
2363         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2364                 return 0;
2365
2366         /* Basic packet information */
2367         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2368         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2369         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2370         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2371         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2372
2373         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2374                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2375                             EFX_QWORD_FMT "\n",
2376                             EFX_QWORD_VAL(*event));
2377
2378         rx_queue = efx_channel_get_rx_queue(channel);
2379
2380         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2381                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2382
2383         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2384                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2385
2386         if (n_descs != rx_queue->scatter_n + 1) {
2387                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2388
2389                 /* detect rx abort */
2390                 if (unlikely(n_descs == rx_queue->scatter_n)) {
2391                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2392                                 netdev_WARN(efx->net_dev,
2393                                             "invalid RX abort: scatter_n=%u event="
2394                                             EFX_QWORD_FMT "\n",
2395                                             rx_queue->scatter_n,
2396                                             EFX_QWORD_VAL(*event));
2397                         efx_ef10_handle_rx_abort(rx_queue);
2398                         return 0;
2399                 }
2400
2401                 /* Check that RX completion merging is valid, i.e.
2402                  * the current firmware supports it and this is a
2403                  * non-scattered packet.
2404                  */
2405                 if (!(nic_data->datapath_caps &
2406                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2407                     rx_queue->scatter_n != 0 || rx_cont) {
2408                         efx_ef10_handle_rx_bad_lbits(
2409                                 rx_queue, next_ptr_lbits,
2410                                 (rx_queue->removed_count +
2411                                  rx_queue->scatter_n + 1) &
2412                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2413                         return 0;
2414                 }
2415
2416                 /* Merged completion for multiple non-scattered packets */
2417                 rx_queue->scatter_n = 1;
2418                 rx_queue->scatter_len = 0;
2419                 n_packets = n_descs;
2420                 ++channel->n_rx_merge_events;
2421                 channel->n_rx_merge_packets += n_packets;
2422                 flags |= EFX_RX_PKT_PREFIX_LEN;
2423         } else {
2424                 ++rx_queue->scatter_n;
2425                 rx_queue->scatter_len += rx_bytes;
2426                 if (rx_cont)
2427                         return 0;
2428                 n_packets = 1;
2429         }
2430
2431         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2432                 flags |= EFX_RX_PKT_DISCARD;
2433
2434         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2435                 channel->n_rx_ip_hdr_chksum_err += n_packets;
2436         } else if (unlikely(EFX_QWORD_FIELD(*event,
2437                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2438                 channel->n_rx_tcp_udp_chksum_err += n_packets;
2439         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2440                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2441                 flags |= EFX_RX_PKT_CSUMMED;
2442         }
2443
2444         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2445                 flags |= EFX_RX_PKT_TCP;
2446
2447         channel->irq_mod_score += 2 * n_packets;
2448
2449         /* Handle received packet(s) */
2450         for (i = 0; i < n_packets; i++) {
2451                 efx_rx_packet(rx_queue,
2452                               rx_queue->removed_count & rx_queue->ptr_mask,
2453                               rx_queue->scatter_n, rx_queue->scatter_len,
2454                               flags);
2455                 rx_queue->removed_count += rx_queue->scatter_n;
2456         }
2457
2458         rx_queue->scatter_n = 0;
2459         rx_queue->scatter_len = 0;
2460
2461         return n_packets;
2462 }
2463
2464 static int
2465 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2466 {
2467         struct efx_nic *efx = channel->efx;
2468         struct efx_tx_queue *tx_queue;
2469         unsigned int tx_ev_desc_ptr;
2470         unsigned int tx_ev_q_label;
2471         int tx_descs = 0;
2472
2473         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2474                 return 0;
2475
2476         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2477                 return 0;
2478
2479         /* Transmit completion */
2480         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2481         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2482         tx_queue = efx_channel_get_tx_queue(channel,
2483                                             tx_ev_q_label % EFX_TXQ_TYPES);
2484         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2485                     tx_queue->ptr_mask);
2486         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2487
2488         return tx_descs;
2489 }
2490
2491 static void
2492 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2493 {
2494         struct efx_nic *efx = channel->efx;
2495         int subcode;
2496
2497         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2498
2499         switch (subcode) {
2500         case ESE_DZ_DRV_TIMER_EV:
2501         case ESE_DZ_DRV_WAKE_UP_EV:
2502                 break;
2503         case ESE_DZ_DRV_START_UP_EV:
2504                 /* event queue init complete. ok. */
2505                 break;
2506         default:
2507                 netif_err(efx, hw, efx->net_dev,
2508                           "channel %d unknown driver event type %d"
2509                           " (data " EFX_QWORD_FMT ")\n",
2510                           channel->channel, subcode,
2511                           EFX_QWORD_VAL(*event));
2512
2513         }
2514 }
2515
2516 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2517                                                    efx_qword_t *event)
2518 {
2519         struct efx_nic *efx = channel->efx;
2520         u32 subcode;
2521
2522         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2523
2524         switch (subcode) {
2525         case EFX_EF10_TEST:
2526                 channel->event_test_cpu = raw_smp_processor_id();
2527                 break;
2528         case EFX_EF10_REFILL:
2529                 /* The queue must be empty, so we won't receive any rx
2530                  * events, so efx_process_channel() won't refill the
2531                  * queue. Refill it here
2532                  */
2533                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2534                 break;
2535         default:
2536                 netif_err(efx, hw, efx->net_dev,
2537                           "channel %d unknown driver event type %u"
2538                           " (data " EFX_QWORD_FMT ")\n",
2539                           channel->channel, (unsigned) subcode,
2540                           EFX_QWORD_VAL(*event));
2541         }
2542 }
2543
2544 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2545 {
2546         struct efx_nic *efx = channel->efx;
2547         efx_qword_t event, *p_event;
2548         unsigned int read_ptr;
2549         int ev_code;
2550         int tx_descs = 0;
2551         int spent = 0;
2552
2553         if (quota <= 0)
2554                 return spent;
2555
2556         read_ptr = channel->eventq_read_ptr;
2557
2558         for (;;) {
2559                 p_event = efx_event(channel, read_ptr);
2560                 event = *p_event;
2561
2562                 if (!efx_event_present(&event))
2563                         break;
2564
2565                 EFX_SET_QWORD(*p_event);
2566
2567                 ++read_ptr;
2568
2569                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2570
2571                 netif_vdbg(efx, drv, efx->net_dev,
2572                            "processing event on %d " EFX_QWORD_FMT "\n",
2573                            channel->channel, EFX_QWORD_VAL(event));
2574
2575                 switch (ev_code) {
2576                 case ESE_DZ_EV_CODE_MCDI_EV:
2577                         efx_mcdi_process_event(channel, &event);
2578                         break;
2579                 case ESE_DZ_EV_CODE_RX_EV:
2580                         spent += efx_ef10_handle_rx_event(channel, &event);
2581                         if (spent >= quota) {
2582                                 /* XXX can we split a merged event to
2583                                  * avoid going over-quota?
2584                                  */
2585                                 spent = quota;
2586                                 goto out;
2587                         }
2588                         break;
2589                 case ESE_DZ_EV_CODE_TX_EV:
2590                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
2591                         if (tx_descs > efx->txq_entries) {
2592                                 spent = quota;
2593                                 goto out;
2594                         } else if (++spent == quota) {
2595                                 goto out;
2596                         }
2597                         break;
2598                 case ESE_DZ_EV_CODE_DRIVER_EV:
2599                         efx_ef10_handle_driver_event(channel, &event);
2600                         if (++spent == quota)
2601                                 goto out;
2602                         break;
2603                 case EFX_EF10_DRVGEN_EV:
2604                         efx_ef10_handle_driver_generated_event(channel, &event);
2605                         break;
2606                 default:
2607                         netif_err(efx, hw, efx->net_dev,
2608                                   "channel %d unknown event type %d"
2609                                   " (data " EFX_QWORD_FMT ")\n",
2610                                   channel->channel, ev_code,
2611                                   EFX_QWORD_VAL(event));
2612                 }
2613         }
2614
2615 out:
2616         channel->eventq_read_ptr = read_ptr;
2617         return spent;
2618 }
2619
2620 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2621 {
2622         struct efx_nic *efx = channel->efx;
2623         efx_dword_t rptr;
2624
2625         if (EFX_EF10_WORKAROUND_35388(efx)) {
2626                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2627                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2628                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2629                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2630
2631                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2632                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2633                                      ERF_DD_EVQ_IND_RPTR,
2634                                      (channel->eventq_read_ptr &
2635                                       channel->eventq_mask) >>
2636                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
2637                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2638                                 channel->channel);
2639                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2640                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2641                                      ERF_DD_EVQ_IND_RPTR,
2642                                      channel->eventq_read_ptr &
2643                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2644                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2645                                 channel->channel);
2646         } else {
2647                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2648                                      channel->eventq_read_ptr &
2649                                      channel->eventq_mask);
2650                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2651         }
2652 }
2653
2654 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2655 {
2656         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2657         struct efx_nic *efx = channel->efx;
2658         efx_qword_t event;
2659         int rc;
2660
2661         EFX_POPULATE_QWORD_2(event,
2662                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2663                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
2664
2665         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2666
2667         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2668          * already swapped the data to little-endian order.
2669          */
2670         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2671                sizeof(efx_qword_t));
2672
2673         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2674                           NULL, 0, NULL);
2675         if (rc != 0)
2676                 goto fail;
2677
2678         return;
2679
2680 fail:
2681         WARN_ON(true);
2682         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2683 }
2684
2685 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2686 {
2687         if (atomic_dec_and_test(&efx->active_queues))
2688                 wake_up(&efx->flush_wq);
2689
2690         WARN_ON(atomic_read(&efx->active_queues) < 0);
2691 }
2692
2693 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2694 {
2695         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2696         struct efx_channel *channel;
2697         struct efx_tx_queue *tx_queue;
2698         struct efx_rx_queue *rx_queue;
2699         int pending;
2700
2701         /* If the MC has just rebooted, the TX/RX queues will have already been
2702          * torn down, but efx->active_queues needs to be set to zero.
2703          */
2704         if (nic_data->must_realloc_vis) {
2705                 atomic_set(&efx->active_queues, 0);
2706                 return 0;
2707         }
2708
2709         /* Do not attempt to write to the NIC during EEH recovery */
2710         if (efx->state != STATE_RECOVERY) {
2711                 efx_for_each_channel(channel, efx) {
2712                         efx_for_each_channel_rx_queue(rx_queue, channel)
2713                                 efx_ef10_rx_fini(rx_queue);
2714                         efx_for_each_channel_tx_queue(tx_queue, channel)
2715                                 efx_ef10_tx_fini(tx_queue);
2716                 }
2717
2718                 wait_event_timeout(efx->flush_wq,
2719                                    atomic_read(&efx->active_queues) == 0,
2720                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2721                 pending = atomic_read(&efx->active_queues);
2722                 if (pending) {
2723                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2724                                   pending);
2725                         return -ETIMEDOUT;
2726                 }
2727         }
2728
2729         return 0;
2730 }
2731
2732 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2733 {
2734         atomic_set(&efx->active_queues, 0);
2735 }
2736
2737 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2738                                   const struct efx_filter_spec *right)
2739 {
2740         if ((left->match_flags ^ right->match_flags) |
2741             ((left->flags ^ right->flags) &
2742              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2743                 return false;
2744
2745         return memcmp(&left->outer_vid, &right->outer_vid,
2746                       sizeof(struct efx_filter_spec) -
2747                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
2748 }
2749
2750 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2751 {
2752         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2753         return jhash2((const u32 *)&spec->outer_vid,
2754                       (sizeof(struct efx_filter_spec) -
2755                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
2756                       0);
2757         /* XXX should we randomise the initval? */
2758 }
2759
2760 /* Decide whether a filter should be exclusive or else should allow
2761  * delivery to additional recipients.  Currently we decide that
2762  * filters for specific local unicast MAC and IP addresses are
2763  * exclusive.
2764  */
2765 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2766 {
2767         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2768             !is_multicast_ether_addr(spec->loc_mac))
2769                 return true;
2770
2771         if ((spec->match_flags &
2772              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2773             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2774                 if (spec->ether_type == htons(ETH_P_IP) &&
2775                     !ipv4_is_multicast(spec->loc_host[0]))
2776                         return true;
2777                 if (spec->ether_type == htons(ETH_P_IPV6) &&
2778                     ((const u8 *)spec->loc_host)[0] != 0xff)
2779                         return true;
2780         }
2781
2782         return false;
2783 }
2784
2785 static struct efx_filter_spec *
2786 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2787                            unsigned int filter_idx)
2788 {
2789         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2790                                           ~EFX_EF10_FILTER_FLAGS);
2791 }
2792
2793 static unsigned int
2794 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2795                            unsigned int filter_idx)
2796 {
2797         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2798 }
2799
2800 static void
2801 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2802                           unsigned int filter_idx,
2803                           const struct efx_filter_spec *spec,
2804                           unsigned int flags)
2805 {
2806         table->entry[filter_idx].spec = (unsigned long)spec | flags;
2807 }
2808
2809 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2810                                       const struct efx_filter_spec *spec,
2811                                       efx_dword_t *inbuf, u64 handle,
2812                                       bool replacing)
2813 {
2814         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2815
2816         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2817
2818         if (replacing) {
2819                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2820                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
2821                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2822         } else {
2823                 u32 match_fields = 0;
2824
2825                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2826                                efx_ef10_filter_is_exclusive(spec) ?
2827                                MC_CMD_FILTER_OP_IN_OP_INSERT :
2828                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2829
2830                 /* Convert match flags and values.  Unlike almost
2831                  * everything else in MCDI, these fields are in
2832                  * network byte order.
2833                  */
2834                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2835                         match_fields |=
2836                                 is_multicast_ether_addr(spec->loc_mac) ?
2837                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2838                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2839 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
2840                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
2841                         match_fields |=                                      \
2842                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
2843                                 mcdi_field ## _LBN;                          \
2844                         BUILD_BUG_ON(                                        \
2845                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2846                                 sizeof(spec->gen_field));                    \
2847                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2848                                &spec->gen_field, sizeof(spec->gen_field));   \
2849                 }
2850                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2851                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2852                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2853                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2854                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2855                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2856                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2857                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2858                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2859                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2860 #undef COPY_FIELD
2861                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2862                                match_fields);
2863         }
2864
2865         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
2866         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2867                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2868                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2869                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2870         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
2871         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2872                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2873         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2874                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2875                        0 : spec->dmaq_id);
2876         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2877                        (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2878                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2879                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2880         if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2881                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2882                                spec->rss_context !=
2883                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2884                                spec->rss_context : nic_data->rx_rss_context);
2885 }
2886
2887 static int efx_ef10_filter_push(struct efx_nic *efx,
2888                                 const struct efx_filter_spec *spec,
2889                                 u64 *handle, bool replacing)
2890 {
2891         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2892         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2893         int rc;
2894
2895         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2896         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2897                           outbuf, sizeof(outbuf), NULL);
2898         if (rc == 0)
2899                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2900         if (rc == -ENOSPC)
2901                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2902         return rc;
2903 }
2904
2905 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2906                                         enum efx_filter_match_flags match_flags)
2907 {
2908         unsigned int match_pri;
2909
2910         for (match_pri = 0;
2911              match_pri < table->rx_match_count;
2912              match_pri++)
2913                 if (table->rx_match_flags[match_pri] == match_flags)
2914                         return match_pri;
2915
2916         return -EPROTONOSUPPORT;
2917 }
2918
2919 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2920                                   struct efx_filter_spec *spec,
2921                                   bool replace_equal)
2922 {
2923         struct efx_ef10_filter_table *table = efx->filter_state;
2924         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2925         struct efx_filter_spec *saved_spec;
2926         unsigned int match_pri, hash;
2927         unsigned int priv_flags;
2928         bool replacing = false;
2929         int ins_index = -1;
2930         DEFINE_WAIT(wait);
2931         bool is_mc_recip;
2932         s32 rc;
2933
2934         /* For now, only support RX filters */
2935         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2936             EFX_FILTER_FLAG_RX)
2937                 return -EINVAL;
2938
2939         rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2940         if (rc < 0)
2941                 return rc;
2942         match_pri = rc;
2943
2944         hash = efx_ef10_filter_hash(spec);
2945         is_mc_recip = efx_filter_is_mc_recipient(spec);
2946         if (is_mc_recip)
2947                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2948
2949         /* Find any existing filters with the same match tuple or
2950          * else a free slot to insert at.  If any of them are busy,
2951          * we have to wait and retry.
2952          */
2953         for (;;) {
2954                 unsigned int depth = 1;
2955                 unsigned int i;
2956
2957                 spin_lock_bh(&efx->filter_lock);
2958
2959                 for (;;) {
2960                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2961                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2962
2963                         if (!saved_spec) {
2964                                 if (ins_index < 0)
2965                                         ins_index = i;
2966                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2967                                 if (table->entry[i].spec &
2968                                     EFX_EF10_FILTER_FLAG_BUSY)
2969                                         break;
2970                                 if (spec->priority < saved_spec->priority &&
2971                                     spec->priority != EFX_FILTER_PRI_AUTO) {
2972                                         rc = -EPERM;
2973                                         goto out_unlock;
2974                                 }
2975                                 if (!is_mc_recip) {
2976                                         /* This is the only one */
2977                                         if (spec->priority ==
2978                                             saved_spec->priority &&
2979                                             !replace_equal) {
2980                                                 rc = -EEXIST;
2981                                                 goto out_unlock;
2982                                         }
2983                                         ins_index = i;
2984                                         goto found;
2985                                 } else if (spec->priority >
2986                                            saved_spec->priority ||
2987                                            (spec->priority ==
2988                                             saved_spec->priority &&
2989                                             replace_equal)) {
2990                                         if (ins_index < 0)
2991                                                 ins_index = i;
2992                                         else
2993                                                 __set_bit(depth, mc_rem_map);
2994                                 }
2995                         }
2996
2997                         /* Once we reach the maximum search depth, use
2998                          * the first suitable slot or return -EBUSY if
2999                          * there was none
3000                          */
3001                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3002                                 if (ins_index < 0) {
3003                                         rc = -EBUSY;
3004                                         goto out_unlock;
3005                                 }
3006                                 goto found;
3007                         }
3008
3009                         ++depth;
3010                 }
3011
3012                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3013                 spin_unlock_bh(&efx->filter_lock);
3014                 schedule();
3015         }
3016
3017 found:
3018         /* Create a software table entry if necessary, and mark it
3019          * busy.  We might yet fail to insert, but any attempt to
3020          * insert a conflicting filter while we're waiting for the
3021          * firmware must find the busy entry.
3022          */
3023         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3024         if (saved_spec) {
3025                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3026                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3027                         /* Just make sure it won't be removed */
3028                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3029                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3030                         table->entry[ins_index].spec &=
3031                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3032                         rc = ins_index;
3033                         goto out_unlock;
3034                 }
3035                 replacing = true;
3036                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3037         } else {
3038                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3039                 if (!saved_spec) {
3040                         rc = -ENOMEM;
3041                         goto out_unlock;
3042                 }
3043                 *saved_spec = *spec;
3044                 priv_flags = 0;
3045         }
3046         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3047                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3048
3049         /* Mark lower-priority multicast recipients busy prior to removal */
3050         if (is_mc_recip) {
3051                 unsigned int depth, i;
3052
3053                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3054                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3055                         if (test_bit(depth, mc_rem_map))
3056                                 table->entry[i].spec |=
3057                                         EFX_EF10_FILTER_FLAG_BUSY;
3058                 }
3059         }
3060
3061         spin_unlock_bh(&efx->filter_lock);
3062
3063         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3064                                   replacing);
3065
3066         /* Finalise the software table entry */
3067         spin_lock_bh(&efx->filter_lock);
3068         if (rc == 0) {
3069                 if (replacing) {
3070                         /* Update the fields that may differ */
3071                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3072                                 saved_spec->flags |=
3073                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
3074                         saved_spec->priority = spec->priority;
3075                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3076                         saved_spec->flags |= spec->flags;
3077                         saved_spec->rss_context = spec->rss_context;
3078                         saved_spec->dmaq_id = spec->dmaq_id;
3079                 }
3080         } else if (!replacing) {
3081                 kfree(saved_spec);
3082                 saved_spec = NULL;
3083         }
3084         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3085
3086         /* Remove and finalise entries for lower-priority multicast
3087          * recipients
3088          */
3089         if (is_mc_recip) {
3090                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3091                 unsigned int depth, i;
3092
3093                 memset(inbuf, 0, sizeof(inbuf));
3094
3095                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3096                         if (!test_bit(depth, mc_rem_map))
3097                                 continue;
3098
3099                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3100                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3101                         priv_flags = efx_ef10_filter_entry_flags(table, i);
3102
3103                         if (rc == 0) {
3104                                 spin_unlock_bh(&efx->filter_lock);
3105                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3106                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3107                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3108                                                table->entry[i].handle);
3109                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3110                                                   inbuf, sizeof(inbuf),
3111                                                   NULL, 0, NULL);
3112                                 spin_lock_bh(&efx->filter_lock);
3113                         }
3114
3115                         if (rc == 0) {
3116                                 kfree(saved_spec);
3117                                 saved_spec = NULL;
3118                                 priv_flags = 0;
3119                         } else {
3120                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3121                         }
3122                         efx_ef10_filter_set_entry(table, i, saved_spec,
3123                                                   priv_flags);
3124                 }
3125         }
3126
3127         /* If successful, return the inserted filter ID */
3128         if (rc == 0)
3129                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3130
3131         wake_up_all(&table->waitq);
3132 out_unlock:
3133         spin_unlock_bh(&efx->filter_lock);
3134         finish_wait(&table->waitq, &wait);
3135         return rc;
3136 }
3137
3138 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3139 {
3140         /* no need to do anything here on EF10 */
3141 }
3142
3143 /* Remove a filter.
3144  * If !by_index, remove by ID
3145  * If by_index, remove by index
3146  * Filter ID may come from userland and must be range-checked.
3147  */
3148 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3149                                            unsigned int priority_mask,
3150                                            u32 filter_id, bool by_index)
3151 {
3152         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3153         struct efx_ef10_filter_table *table = efx->filter_state;
3154         MCDI_DECLARE_BUF(inbuf,
3155                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3156                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3157         struct efx_filter_spec *spec;
3158         DEFINE_WAIT(wait);
3159         int rc;
3160
3161         /* Find the software table entry and mark it busy.  Don't
3162          * remove it yet; any attempt to update while we're waiting
3163          * for the firmware must find the busy entry.
3164          */
3165         for (;;) {
3166                 spin_lock_bh(&efx->filter_lock);
3167                 if (!(table->entry[filter_idx].spec &
3168                       EFX_EF10_FILTER_FLAG_BUSY))
3169                         break;
3170                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3171                 spin_unlock_bh(&efx->filter_lock);
3172                 schedule();
3173         }
3174
3175         spec = efx_ef10_filter_entry_spec(table, filter_idx);
3176         if (!spec ||
3177             (!by_index &&
3178              efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3179              filter_id / HUNT_FILTER_TBL_ROWS)) {
3180                 rc = -ENOENT;
3181                 goto out_unlock;
3182         }
3183
3184         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3185             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3186                 /* Just remove flags */
3187                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3188                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3189                 rc = 0;
3190                 goto out_unlock;
3191         }
3192
3193         if (!(priority_mask & (1U << spec->priority))) {
3194                 rc = -ENOENT;
3195                 goto out_unlock;
3196         }
3197
3198         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3199         spin_unlock_bh(&efx->filter_lock);
3200
3201         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3202                 /* Reset to an automatic filter */
3203
3204                 struct efx_filter_spec new_spec = *spec;
3205
3206                 new_spec.priority = EFX_FILTER_PRI_AUTO;
3207                 new_spec.flags = (EFX_FILTER_FLAG_RX |
3208                                   EFX_FILTER_FLAG_RX_RSS);
3209                 new_spec.dmaq_id = 0;
3210                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3211                 rc = efx_ef10_filter_push(efx, &new_spec,
3212                                           &table->entry[filter_idx].handle,
3213                                           true);
3214
3215                 spin_lock_bh(&efx->filter_lock);
3216                 if (rc == 0)
3217                         *spec = new_spec;
3218         } else {
3219                 /* Really remove the filter */
3220
3221                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3222                                efx_ef10_filter_is_exclusive(spec) ?
3223                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3224                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3225                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3226                                table->entry[filter_idx].handle);
3227                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3228                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
3229
3230                 spin_lock_bh(&efx->filter_lock);
3231                 if (rc == 0) {
3232                         kfree(spec);
3233                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3234                 }
3235         }
3236
3237         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3238         wake_up_all(&table->waitq);
3239 out_unlock:
3240         spin_unlock_bh(&efx->filter_lock);
3241         finish_wait(&table->waitq, &wait);
3242         return rc;
3243 }
3244
3245 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3246                                        enum efx_filter_priority priority,
3247                                        u32 filter_id)
3248 {
3249         return efx_ef10_filter_remove_internal(efx, 1U << priority,
3250                                                filter_id, false);
3251 }
3252
3253 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3254                                     enum efx_filter_priority priority,
3255                                     u32 filter_id, struct efx_filter_spec *spec)
3256 {
3257         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3258         struct efx_ef10_filter_table *table = efx->filter_state;
3259         const struct efx_filter_spec *saved_spec;
3260         int rc;
3261
3262         spin_lock_bh(&efx->filter_lock);
3263         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3264         if (saved_spec && saved_spec->priority == priority &&
3265             efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3266             filter_id / HUNT_FILTER_TBL_ROWS) {
3267                 *spec = *saved_spec;
3268                 rc = 0;
3269         } else {
3270                 rc = -ENOENT;
3271         }
3272         spin_unlock_bh(&efx->filter_lock);
3273         return rc;
3274 }
3275
3276 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3277                                      enum efx_filter_priority priority)
3278 {
3279         unsigned int priority_mask;
3280         unsigned int i;
3281         int rc;
3282
3283         priority_mask = (((1U << (priority + 1)) - 1) &
3284                          ~(1U << EFX_FILTER_PRI_AUTO));
3285
3286         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3287                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3288                                                      i, true);
3289                 if (rc && rc != -ENOENT)
3290                         return rc;
3291         }
3292
3293         return 0;
3294 }
3295
3296 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3297                                          enum efx_filter_priority priority)
3298 {
3299         struct efx_ef10_filter_table *table = efx->filter_state;
3300         unsigned int filter_idx;
3301         s32 count = 0;
3302
3303         spin_lock_bh(&efx->filter_lock);
3304         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3305                 if (table->entry[filter_idx].spec &&
3306                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3307                     priority)
3308                         ++count;
3309         }
3310         spin_unlock_bh(&efx->filter_lock);
3311         return count;
3312 }
3313
3314 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3315 {
3316         struct efx_ef10_filter_table *table = efx->filter_state;
3317
3318         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3319 }
3320
3321 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3322                                       enum efx_filter_priority priority,
3323                                       u32 *buf, u32 size)
3324 {
3325         struct efx_ef10_filter_table *table = efx->filter_state;
3326         struct efx_filter_spec *spec;
3327         unsigned int filter_idx;
3328         s32 count = 0;
3329
3330         spin_lock_bh(&efx->filter_lock);
3331         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3332                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3333                 if (spec && spec->priority == priority) {
3334                         if (count == size) {
3335                                 count = -EMSGSIZE;
3336                                 break;
3337                         }
3338                         buf[count++] = (efx_ef10_filter_rx_match_pri(
3339                                                 table, spec->match_flags) *
3340                                         HUNT_FILTER_TBL_ROWS +
3341                                         filter_idx);
3342                 }
3343         }
3344         spin_unlock_bh(&efx->filter_lock);
3345         return count;
3346 }
3347
3348 #ifdef CONFIG_RFS_ACCEL
3349
3350 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3351
3352 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3353                                       struct efx_filter_spec *spec)
3354 {
3355         struct efx_ef10_filter_table *table = efx->filter_state;
3356         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3357         struct efx_filter_spec *saved_spec;
3358         unsigned int hash, i, depth = 1;
3359         bool replacing = false;
3360         int ins_index = -1;
3361         u64 cookie;
3362         s32 rc;
3363
3364         /* Must be an RX filter without RSS and not for a multicast
3365          * destination address (RFS only works for connected sockets).
3366          * These restrictions allow us to pass only a tiny amount of
3367          * data through to the completion function.
3368          */
3369         EFX_WARN_ON_PARANOID(spec->flags !=
3370                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3371         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3372         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3373
3374         hash = efx_ef10_filter_hash(spec);
3375
3376         spin_lock_bh(&efx->filter_lock);
3377
3378         /* Find any existing filter with the same match tuple or else
3379          * a free slot to insert at.  If an existing filter is busy,
3380          * we have to give up.
3381          */
3382         for (;;) {
3383                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3384                 saved_spec = efx_ef10_filter_entry_spec(table, i);
3385
3386                 if (!saved_spec) {
3387                         if (ins_index < 0)
3388                                 ins_index = i;
3389                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3390                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3391                                 rc = -EBUSY;
3392                                 goto fail_unlock;
3393                         }
3394                         if (spec->priority < saved_spec->priority) {
3395                                 rc = -EPERM;
3396                                 goto fail_unlock;
3397                         }
3398                         ins_index = i;
3399                         break;
3400                 }
3401
3402                 /* Once we reach the maximum search depth, use the
3403                  * first suitable slot or return -EBUSY if there was
3404                  * none
3405                  */
3406                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3407                         if (ins_index < 0) {
3408                                 rc = -EBUSY;
3409                                 goto fail_unlock;
3410                         }
3411                         break;
3412                 }
3413
3414                 ++depth;
3415         }
3416
3417         /* Create a software table entry if necessary, and mark it
3418          * busy.  We might yet fail to insert, but any attempt to
3419          * insert a conflicting filter while we're waiting for the
3420          * firmware must find the busy entry.
3421          */
3422         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3423         if (saved_spec) {
3424                 replacing = true;
3425         } else {
3426                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3427                 if (!saved_spec) {
3428                         rc = -ENOMEM;
3429                         goto fail_unlock;
3430                 }
3431                 *saved_spec = *spec;
3432         }
3433         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3434                                   EFX_EF10_FILTER_FLAG_BUSY);
3435
3436         spin_unlock_bh(&efx->filter_lock);
3437
3438         /* Pack up the variables needed on completion */
3439         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3440
3441         efx_ef10_filter_push_prep(efx, spec, inbuf,
3442                                   table->entry[ins_index].handle, replacing);
3443         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3444                            MC_CMD_FILTER_OP_OUT_LEN,
3445                            efx_ef10_filter_rfs_insert_complete, cookie);
3446
3447         return ins_index;
3448
3449 fail_unlock:
3450         spin_unlock_bh(&efx->filter_lock);
3451         return rc;
3452 }
3453
3454 static void
3455 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3456                                     int rc, efx_dword_t *outbuf,
3457                                     size_t outlen_actual)
3458 {
3459         struct efx_ef10_filter_table *table = efx->filter_state;
3460         unsigned int ins_index, dmaq_id;
3461         struct efx_filter_spec *spec;
3462         bool replacing;
3463
3464         /* Unpack the cookie */
3465         replacing = cookie >> 31;
3466         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3467         dmaq_id = cookie & 0xffff;
3468
3469         spin_lock_bh(&efx->filter_lock);
3470         spec = efx_ef10_filter_entry_spec(table, ins_index);
3471         if (rc == 0) {
3472                 table->entry[ins_index].handle =
3473                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3474                 if (replacing)
3475                         spec->dmaq_id = dmaq_id;
3476         } else if (!replacing) {
3477                 kfree(spec);
3478                 spec = NULL;
3479         }
3480         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3481         spin_unlock_bh(&efx->filter_lock);
3482
3483         wake_up_all(&table->waitq);
3484 }
3485
3486 static void
3487 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3488                                     unsigned long filter_idx,
3489                                     int rc, efx_dword_t *outbuf,
3490                                     size_t outlen_actual);
3491
3492 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3493                                            unsigned int filter_idx)
3494 {
3495         struct efx_ef10_filter_table *table = efx->filter_state;
3496         struct efx_filter_spec *spec =
3497                 efx_ef10_filter_entry_spec(table, filter_idx);
3498         MCDI_DECLARE_BUF(inbuf,
3499                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3500                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3501
3502         if (!spec ||
3503             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3504             spec->priority != EFX_FILTER_PRI_HINT ||
3505             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3506                                  flow_id, filter_idx))
3507                 return false;
3508
3509         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3510                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
3511         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3512                        table->entry[filter_idx].handle);
3513         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3514                                efx_ef10_filter_rfs_expire_complete, filter_idx))
3515                 return false;
3516
3517         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3518         return true;
3519 }
3520
3521 static void
3522 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3523                                     unsigned long filter_idx,
3524                                     int rc, efx_dword_t *outbuf,
3525                                     size_t outlen_actual)
3526 {
3527         struct efx_ef10_filter_table *table = efx->filter_state;
3528         struct efx_filter_spec *spec =
3529                 efx_ef10_filter_entry_spec(table, filter_idx);
3530
3531         spin_lock_bh(&efx->filter_lock);
3532         if (rc == 0) {
3533                 kfree(spec);
3534                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3535         }
3536         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3537         wake_up_all(&table->waitq);
3538         spin_unlock_bh(&efx->filter_lock);
3539 }
3540
3541 #endif /* CONFIG_RFS_ACCEL */
3542
3543 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3544 {
3545         int match_flags = 0;
3546
3547 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
3548                 u32 old_mcdi_flags = mcdi_flags;                        \
3549                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
3550                                 mcdi_field ## _LBN);                    \
3551                 if (mcdi_flags != old_mcdi_flags)                       \
3552                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
3553         }
3554         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3555         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3556         MAP_FLAG(REM_HOST, SRC_IP);
3557         MAP_FLAG(LOC_HOST, DST_IP);
3558         MAP_FLAG(REM_MAC, SRC_MAC);
3559         MAP_FLAG(REM_PORT, SRC_PORT);
3560         MAP_FLAG(LOC_MAC, DST_MAC);
3561         MAP_FLAG(LOC_PORT, DST_PORT);
3562         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3563         MAP_FLAG(INNER_VID, INNER_VLAN);
3564         MAP_FLAG(OUTER_VID, OUTER_VLAN);
3565         MAP_FLAG(IP_PROTO, IP_PROTO);
3566 #undef MAP_FLAG
3567
3568         /* Did we map them all? */
3569         if (mcdi_flags)
3570                 return -EINVAL;
3571
3572         return match_flags;
3573 }
3574
3575 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3576 {
3577         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3578         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3579         unsigned int pd_match_pri, pd_match_count;
3580         struct efx_ef10_filter_table *table;
3581         size_t outlen;
3582         int rc;
3583
3584         table = kzalloc(sizeof(*table), GFP_KERNEL);
3585         if (!table)
3586                 return -ENOMEM;
3587
3588         /* Find out which RX filter types are supported, and their priorities */
3589         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3590                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3591         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3592                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3593                           &outlen);
3594         if (rc)
3595                 goto fail;
3596         pd_match_count = MCDI_VAR_ARRAY_LEN(
3597                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3598         table->rx_match_count = 0;
3599
3600         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3601                 u32 mcdi_flags =
3602                         MCDI_ARRAY_DWORD(
3603                                 outbuf,
3604                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3605                                 pd_match_pri);
3606                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3607                 if (rc < 0) {
3608                         netif_dbg(efx, probe, efx->net_dev,
3609                                   "%s: fw flags %#x pri %u not supported in driver\n",
3610                                   __func__, mcdi_flags, pd_match_pri);
3611                 } else {
3612                         netif_dbg(efx, probe, efx->net_dev,
3613                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3614                                   __func__, mcdi_flags, pd_match_pri,
3615                                   rc, table->rx_match_count);
3616                         table->rx_match_flags[table->rx_match_count++] = rc;
3617                 }
3618         }
3619
3620         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3621         if (!table->entry) {
3622                 rc = -ENOMEM;
3623                 goto fail;
3624         }
3625
3626         efx->filter_state = table;
3627         init_waitqueue_head(&table->waitq);
3628         return 0;
3629
3630 fail:
3631         kfree(table);
3632         return rc;
3633 }
3634
3635 /* Caller must hold efx->filter_sem for read if race against
3636  * efx_ef10_filter_table_remove() is possible
3637  */
3638 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3639 {
3640         struct efx_ef10_filter_table *table = efx->filter_state;
3641         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3642         struct efx_filter_spec *spec;
3643         unsigned int filter_idx;
3644         bool failed = false;
3645         int rc;
3646
3647         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3648
3649         if (!nic_data->must_restore_filters)
3650                 return;
3651
3652         if (!table)
3653                 return;
3654
3655         spin_lock_bh(&efx->filter_lock);
3656
3657         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3658                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3659                 if (!spec)
3660                         continue;
3661
3662                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3663                 spin_unlock_bh(&efx->filter_lock);
3664
3665                 rc = efx_ef10_filter_push(efx, spec,
3666                                           &table->entry[filter_idx].handle,
3667                                           false);
3668                 if (rc)
3669                         failed = true;
3670
3671                 spin_lock_bh(&efx->filter_lock);
3672                 if (rc) {
3673                         kfree(spec);
3674                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3675                 } else {
3676                         table->entry[filter_idx].spec &=
3677                                 ~EFX_EF10_FILTER_FLAG_BUSY;
3678                 }
3679         }
3680
3681         spin_unlock_bh(&efx->filter_lock);
3682
3683         if (failed)
3684                 netif_err(efx, hw, efx->net_dev,
3685                           "unable to restore all filters\n");
3686         else
3687                 nic_data->must_restore_filters = false;
3688 }
3689
3690 /* Caller must hold efx->filter_sem for write */
3691 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3692 {
3693         struct efx_ef10_filter_table *table = efx->filter_state;
3694         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3695         struct efx_filter_spec *spec;
3696         unsigned int filter_idx;
3697         int rc;
3698
3699         efx->filter_state = NULL;
3700         if (!table)
3701                 return;
3702
3703         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3704                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3705                 if (!spec)
3706                         continue;
3707
3708                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3709                                efx_ef10_filter_is_exclusive(spec) ?
3710                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3711                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3712                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3713                                table->entry[filter_idx].handle);
3714                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3715                                   NULL, 0, NULL);
3716                 if (rc)
3717                         netdev_WARN(efx->net_dev,
3718                                     "filter_idx=%#x handle=%#llx\n",
3719                                     filter_idx,
3720                                     table->entry[filter_idx].handle);
3721                 kfree(spec);
3722         }
3723
3724         vfree(table->entry);
3725         kfree(table);
3726 }
3727
3728 /* Caller must hold efx->filter_sem for read if race against
3729  * efx_ef10_filter_table_remove() is possible
3730  */
3731 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3732 {
3733         struct efx_ef10_filter_table *table = efx->filter_state;
3734         struct net_device *net_dev = efx->net_dev;
3735         struct efx_filter_spec spec;
3736         bool remove_failed = false;
3737         struct netdev_hw_addr *uc;
3738         struct netdev_hw_addr *mc;
3739         unsigned int filter_idx;
3740         int i, n, rc;
3741
3742         if (!efx_dev_registered(efx))
3743                 return;
3744
3745         if (!table)
3746                 return;
3747
3748         /* Mark old filters that may need to be removed */
3749         spin_lock_bh(&efx->filter_lock);
3750         n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
3751         for (i = 0; i < n; i++) {
3752                 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3753                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3754         }
3755         n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
3756         for (i = 0; i < n; i++) {
3757                 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3758                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3759         }
3760         spin_unlock_bh(&efx->filter_lock);
3761
3762         /* Copy/convert the address lists; add the primary station
3763          * address and broadcast address
3764          */
3765         netif_addr_lock_bh(net_dev);
3766         if (net_dev->flags & IFF_PROMISC ||
3767             netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3768                 table->dev_uc_count = -1;
3769         } else {
3770                 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
3771                 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3772                 i = 1;
3773                 netdev_for_each_uc_addr(uc, net_dev) {
3774                         ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3775                         i++;
3776                 }
3777         }
3778         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
3779             netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3780                 table->dev_mc_count = -1;
3781         } else {
3782                 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3783                 eth_broadcast_addr(table->dev_mc_list[0].addr);
3784                 i = 1;
3785                 netdev_for_each_mc_addr(mc, net_dev) {
3786                         ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3787                         i++;
3788                 }
3789         }
3790         netif_addr_unlock_bh(net_dev);
3791
3792         /* Insert/renew unicast filters */
3793         if (table->dev_uc_count >= 0) {
3794                 for (i = 0; i < table->dev_uc_count; i++) {
3795                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3796                                            EFX_FILTER_FLAG_RX_RSS,
3797                                            0);
3798                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3799                                                  table->dev_uc_list[i].addr);
3800                         rc = efx_ef10_filter_insert(efx, &spec, true);
3801                         if (rc < 0) {
3802                                 /* Fall back to unicast-promisc */
3803                                 while (i--)
3804                                         efx_ef10_filter_remove_safe(
3805                                                 efx, EFX_FILTER_PRI_AUTO,
3806                                                 table->dev_uc_list[i].id);
3807                                 table->dev_uc_count = -1;
3808                                 break;
3809                         }
3810                         table->dev_uc_list[i].id = rc;
3811                 }
3812         }
3813         if (table->dev_uc_count < 0) {
3814                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3815                                    EFX_FILTER_FLAG_RX_RSS,
3816                                    0);
3817                 efx_filter_set_uc_def(&spec);
3818                 rc = efx_ef10_filter_insert(efx, &spec, true);
3819                 if (rc < 0) {
3820                         WARN_ON(1);
3821                         table->dev_uc_count = 0;
3822                 } else {
3823                         table->dev_uc_list[0].id = rc;
3824                 }
3825         }
3826
3827         /* Insert/renew multicast filters */
3828         if (table->dev_mc_count >= 0) {
3829                 for (i = 0; i < table->dev_mc_count; i++) {
3830                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3831                                            EFX_FILTER_FLAG_RX_RSS,
3832                                            0);
3833                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3834                                                  table->dev_mc_list[i].addr);
3835                         rc = efx_ef10_filter_insert(efx, &spec, true);
3836                         if (rc < 0) {
3837                                 /* Fall back to multicast-promisc */
3838                                 while (i--)
3839                                         efx_ef10_filter_remove_safe(
3840                                                 efx, EFX_FILTER_PRI_AUTO,
3841                                                 table->dev_mc_list[i].id);
3842                                 table->dev_mc_count = -1;
3843                                 break;
3844                         }
3845                         table->dev_mc_list[i].id = rc;
3846                 }
3847         }
3848         if (table->dev_mc_count < 0) {
3849                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3850                                    EFX_FILTER_FLAG_RX_RSS,
3851                                    0);
3852                 efx_filter_set_mc_def(&spec);
3853                 rc = efx_ef10_filter_insert(efx, &spec, true);
3854                 if (rc < 0) {
3855                         WARN_ON(1);
3856                         table->dev_mc_count = 0;
3857                 } else {
3858                         table->dev_mc_list[0].id = rc;
3859                 }
3860         }
3861
3862         /* Remove filters that weren't renewed.  Since nothing else
3863          * changes the AUTO_OLD flag or removes these filters, we
3864          * don't need to hold the filter_lock while scanning for
3865          * these filters.
3866          */
3867         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3868                 if (ACCESS_ONCE(table->entry[i].spec) &
3869                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
3870                         if (efx_ef10_filter_remove_internal(
3871                                     efx, 1U << EFX_FILTER_PRI_AUTO,
3872                                     i, true) < 0)
3873                                 remove_failed = true;
3874                 }
3875         }
3876         WARN_ON(remove_failed);
3877 }
3878
3879 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
3880 {
3881         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3882         u8 mac_old[ETH_ALEN];
3883         int rc, rc2;
3884
3885         /* Only reconfigure a PF-created vport */
3886         if (is_zero_ether_addr(nic_data->vport_mac))
3887                 return 0;
3888
3889         efx_device_detach_sync(efx);
3890         efx_net_stop(efx->net_dev);
3891         down_write(&efx->filter_sem);
3892         efx_ef10_filter_table_remove(efx);
3893         up_write(&efx->filter_sem);
3894
3895         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
3896         if (rc)
3897                 goto restore_filters;
3898
3899         ether_addr_copy(mac_old, nic_data->vport_mac);
3900         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
3901                                     nic_data->vport_mac);
3902         if (rc)
3903                 goto restore_vadaptor;
3904
3905         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
3906                                     efx->net_dev->dev_addr);
3907         if (!rc) {
3908                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
3909         } else {
3910                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
3911                 if (rc2) {
3912                         /* Failed to add original MAC, so clear vport_mac */
3913                         eth_zero_addr(nic_data->vport_mac);
3914                         goto reset_nic;
3915                 }
3916         }
3917
3918 restore_vadaptor:
3919         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
3920         if (rc2)
3921                 goto reset_nic;
3922 restore_filters:
3923         down_write(&efx->filter_sem);
3924         rc2 = efx_ef10_filter_table_probe(efx);
3925         up_write(&efx->filter_sem);
3926         if (rc2)
3927                 goto reset_nic;
3928
3929         rc2 = efx_net_open(efx->net_dev);
3930         if (rc2)
3931                 goto reset_nic;
3932
3933         netif_device_attach(efx->net_dev);
3934
3935         return rc;
3936
3937 reset_nic:
3938         netif_err(efx, drv, efx->net_dev,
3939                   "Failed to restore when changing MAC address - scheduling reset\n");
3940         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
3941
3942         return rc ? rc : rc2;
3943 }
3944
3945 static int efx_ef10_set_mac_address(struct efx_nic *efx)
3946 {
3947         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
3948         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3949         bool was_enabled = efx->port_enabled;
3950         int rc;
3951
3952         efx_device_detach_sync(efx);
3953         efx_net_stop(efx->net_dev);
3954         down_write(&efx->filter_sem);
3955         efx_ef10_filter_table_remove(efx);
3956
3957         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
3958                         efx->net_dev->dev_addr);
3959         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
3960                        nic_data->vport_id);
3961         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
3962                                 sizeof(inbuf), NULL, 0, NULL);
3963
3964         efx_ef10_filter_table_probe(efx);
3965         up_write(&efx->filter_sem);
3966         if (was_enabled)
3967                 efx_net_open(efx->net_dev);
3968         netif_device_attach(efx->net_dev);
3969
3970 #ifdef CONFIG_SFC_SRIOV
3971         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
3972                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
3973
3974                 if (rc == -EPERM) {
3975                         struct efx_nic *efx_pf;
3976
3977                         /* Switch to PF and change MAC address on vport */
3978                         efx_pf = pci_get_drvdata(pci_dev_pf);
3979
3980                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
3981                                                        nic_data->vf_index,
3982                                                        efx->net_dev->dev_addr);
3983                 } else if (!rc) {
3984                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
3985                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
3986                         unsigned int i;
3987
3988                         /* MAC address successfully changed by VF (with MAC
3989                          * spoofing) so update the parent PF if possible.
3990                          */
3991                         for (i = 0; i < efx_pf->vf_count; ++i) {
3992                                 struct ef10_vf *vf = nic_data->vf + i;
3993
3994                                 if (vf->efx == efx) {
3995                                         ether_addr_copy(vf->mac,
3996                                                         efx->net_dev->dev_addr);
3997                                         return 0;
3998                                 }
3999                         }
4000                 }
4001         } else
4002 #endif
4003         if (rc == -EPERM) {
4004                 netif_err(efx, drv, efx->net_dev,
4005                           "Cannot change MAC address; use sfboot to enable"
4006                           " mac-spoofing on this interface\n");
4007         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4008                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4009                  * fall-back to the method of changing the MAC address on the
4010                  * vport.  This only applies to PFs because such versions of
4011                  * MCFW do not support VFs.
4012                  */
4013                 rc = efx_ef10_vport_set_mac_address(efx);
4014         } else {
4015                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4016                                        sizeof(inbuf), NULL, 0, rc);
4017         }
4018
4019         return rc;
4020 }
4021
4022 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4023 {
4024         efx_ef10_filter_sync_rx_mode(efx);
4025
4026         return efx_mcdi_set_mac(efx);
4027 }
4028
4029 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4030 {
4031         efx_ef10_filter_sync_rx_mode(efx);
4032
4033         return 0;
4034 }
4035
4036 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4037 {
4038         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4039
4040         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4041         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4042                             NULL, 0, NULL);
4043 }
4044
4045 /* MC BISTs follow a different poll mechanism to phy BISTs.
4046  * The BIST is done in the poll handler on the MC, and the MCDI command
4047  * will block until the BIST is done.
4048  */
4049 static int efx_ef10_poll_bist(struct efx_nic *efx)
4050 {
4051         int rc;
4052         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4053         size_t outlen;
4054         u32 result;
4055
4056         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4057                            outbuf, sizeof(outbuf), &outlen);
4058         if (rc != 0)
4059                 return rc;
4060
4061         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4062                 return -EIO;
4063
4064         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4065         switch (result) {
4066         case MC_CMD_POLL_BIST_PASSED:
4067                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4068                 return 0;
4069         case MC_CMD_POLL_BIST_TIMEOUT:
4070                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4071                 return -EIO;
4072         case MC_CMD_POLL_BIST_FAILED:
4073                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4074                 return -EIO;
4075         default:
4076                 netif_err(efx, hw, efx->net_dev,
4077                           "BIST returned unknown result %u", result);
4078                 return -EIO;
4079         }
4080 }
4081
4082 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4083 {
4084         int rc;
4085
4086         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4087
4088         rc = efx_ef10_start_bist(efx, bist_type);
4089         if (rc != 0)
4090                 return rc;
4091
4092         return efx_ef10_poll_bist(efx);
4093 }
4094
4095 static int
4096 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4097 {
4098         int rc, rc2;
4099
4100         efx_reset_down(efx, RESET_TYPE_WORLD);
4101
4102         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4103                           NULL, 0, NULL, 0, NULL);
4104         if (rc != 0)
4105                 goto out;
4106
4107         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4108         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4109
4110         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4111
4112 out:
4113         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4114         return rc ? rc : rc2;
4115 }
4116
4117 #ifdef CONFIG_SFC_MTD
4118
4119 struct efx_ef10_nvram_type_info {
4120         u16 type, type_mask;
4121         u8 port;
4122         const char *name;
4123 };
4124
4125 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4126         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
4127         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
4128         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
4129         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
4130         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
4131         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
4132         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
4133         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
4134         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
4135         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
4136         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
4137 };
4138
4139 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4140                                         struct efx_mcdi_mtd_partition *part,
4141                                         unsigned int type)
4142 {
4143         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4144         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4145         const struct efx_ef10_nvram_type_info *info;
4146         size_t size, erase_size, outlen;
4147         bool protected;
4148         int rc;
4149
4150         for (info = efx_ef10_nvram_types; ; info++) {
4151                 if (info ==
4152                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4153                         return -ENODEV;
4154                 if ((type & ~info->type_mask) == info->type)
4155                         break;
4156         }
4157         if (info->port != efx_port_num(efx))
4158                 return -ENODEV;
4159
4160         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4161         if (rc)
4162                 return rc;
4163         if (protected)
4164                 return -ENODEV; /* hide it */
4165
4166         part->nvram_type = type;
4167
4168         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4169         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4170                           outbuf, sizeof(outbuf), &outlen);
4171         if (rc)
4172                 return rc;
4173         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4174                 return -EIO;
4175         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4176             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4177                 part->fw_subtype = MCDI_DWORD(outbuf,
4178                                               NVRAM_METADATA_OUT_SUBTYPE);
4179
4180         part->common.dev_type_name = "EF10 NVRAM manager";
4181         part->common.type_name = info->name;
4182
4183         part->common.mtd.type = MTD_NORFLASH;
4184         part->common.mtd.flags = MTD_CAP_NORFLASH;
4185         part->common.mtd.size = size;
4186         part->common.mtd.erasesize = erase_size;
4187
4188         return 0;
4189 }
4190
4191 static int efx_ef10_mtd_probe(struct efx_nic *efx)
4192 {
4193         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4194         struct efx_mcdi_mtd_partition *parts;
4195         size_t outlen, n_parts_total, i, n_parts;
4196         unsigned int type;
4197         int rc;
4198
4199         ASSERT_RTNL();
4200
4201         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4202         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4203                           outbuf, sizeof(outbuf), &outlen);
4204         if (rc)
4205                 return rc;
4206         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4207                 return -EIO;
4208
4209         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4210         if (n_parts_total >
4211             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4212                 return -EIO;
4213
4214         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4215         if (!parts)
4216                 return -ENOMEM;
4217
4218         n_parts = 0;
4219         for (i = 0; i < n_parts_total; i++) {
4220                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4221                                         i);
4222                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4223                 if (rc == 0)
4224                         n_parts++;
4225                 else if (rc != -ENODEV)
4226                         goto fail;
4227         }
4228
4229         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4230 fail:
4231         if (rc)
4232                 kfree(parts);
4233         return rc;
4234 }
4235
4236 #endif /* CONFIG_SFC_MTD */
4237
4238 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4239 {
4240         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4241 }
4242
4243 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4244                                             u32 host_time) {}
4245
4246 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4247                                            bool temp)
4248 {
4249         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4250         int rc;
4251
4252         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4253             channel->sync_events_state == SYNC_EVENTS_VALID ||
4254             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4255                 return 0;
4256         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4257
4258         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4259         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4260         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4261                        channel->channel);
4262
4263         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4264                           inbuf, sizeof(inbuf), NULL, 0, NULL);
4265
4266         if (rc != 0)
4267                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4268                                                     SYNC_EVENTS_DISABLED;
4269
4270         return rc;
4271 }
4272
4273 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4274                                             bool temp)
4275 {
4276         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4277         int rc;
4278
4279         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4280             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4281                 return 0;
4282         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4283                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4284                 return 0;
4285         }
4286         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4287                                             SYNC_EVENTS_DISABLED;
4288
4289         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4290         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4291         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4292                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4293         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4294                        channel->channel);
4295
4296         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4297                           inbuf, sizeof(inbuf), NULL, 0, NULL);
4298
4299         return rc;
4300 }
4301
4302 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4303                                            bool temp)
4304 {
4305         int (*set)(struct efx_channel *channel, bool temp);
4306         struct efx_channel *channel;
4307
4308         set = en ?
4309               efx_ef10_rx_enable_timestamping :
4310               efx_ef10_rx_disable_timestamping;
4311
4312         efx_for_each_channel(channel, efx) {
4313                 int rc = set(channel, temp);
4314                 if (en && rc != 0) {
4315                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4316                         return rc;
4317                 }
4318         }
4319
4320         return 0;
4321 }
4322
4323 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4324                                          struct hwtstamp_config *init)
4325 {
4326         return -EOPNOTSUPP;
4327 }
4328
4329 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4330                                       struct hwtstamp_config *init)
4331 {
4332         int rc;
4333
4334         switch (init->rx_filter) {
4335         case HWTSTAMP_FILTER_NONE:
4336                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4337                 /* if TX timestamping is still requested then leave PTP on */
4338                 return efx_ptp_change_mode(efx,
4339                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
4340         case HWTSTAMP_FILTER_ALL:
4341         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4342         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4343         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4344         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4345         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4346         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4347         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4348         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4349         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4350         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4351         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4352         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4353                 init->rx_filter = HWTSTAMP_FILTER_ALL;
4354                 rc = efx_ptp_change_mode(efx, true, 0);
4355                 if (!rc)
4356                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4357                 if (rc)
4358                         efx_ptp_change_mode(efx, false, 0);
4359                 return rc;
4360         default:
4361                 return -ERANGE;
4362         }
4363 }
4364
4365 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
4366         .is_vf = true,
4367         .mem_bar = EFX_MEM_VF_BAR,
4368         .mem_map_size = efx_ef10_mem_map_size,
4369         .probe = efx_ef10_probe_vf,
4370         .remove = efx_ef10_remove,
4371         .dimension_resources = efx_ef10_dimension_resources,
4372         .init = efx_ef10_init_nic,
4373         .fini = efx_port_dummy_op_void,
4374         .map_reset_reason = efx_ef10_map_reset_reason,
4375         .map_reset_flags = efx_ef10_map_reset_flags,
4376         .reset = efx_ef10_reset,
4377         .probe_port = efx_mcdi_port_probe,
4378         .remove_port = efx_mcdi_port_remove,
4379         .fini_dmaq = efx_ef10_fini_dmaq,
4380         .prepare_flr = efx_ef10_prepare_flr,
4381         .finish_flr = efx_port_dummy_op_void,
4382         .describe_stats = efx_ef10_describe_stats,
4383         .update_stats = efx_ef10_update_stats_vf,
4384         .start_stats = efx_port_dummy_op_void,
4385         .pull_stats = efx_port_dummy_op_void,
4386         .stop_stats = efx_port_dummy_op_void,
4387         .set_id_led = efx_mcdi_set_id_led,
4388         .push_irq_moderation = efx_ef10_push_irq_moderation,
4389         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
4390         .check_mac_fault = efx_mcdi_mac_check_fault,
4391         .reconfigure_port = efx_mcdi_port_reconfigure,
4392         .get_wol = efx_ef10_get_wol_vf,
4393         .set_wol = efx_ef10_set_wol_vf,
4394         .resume_wol = efx_port_dummy_op_void,
4395         .mcdi_request = efx_ef10_mcdi_request,
4396         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4397         .mcdi_read_response = efx_ef10_mcdi_read_response,
4398         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4399         .irq_enable_master = efx_port_dummy_op_void,
4400         .irq_test_generate = efx_ef10_irq_test_generate,
4401         .irq_disable_non_ev = efx_port_dummy_op_void,
4402         .irq_handle_msi = efx_ef10_msi_interrupt,
4403         .irq_handle_legacy = efx_ef10_legacy_interrupt,
4404         .tx_probe = efx_ef10_tx_probe,
4405         .tx_init = efx_ef10_tx_init,
4406         .tx_remove = efx_ef10_tx_remove,
4407         .tx_write = efx_ef10_tx_write,
4408         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
4409         .rx_probe = efx_ef10_rx_probe,
4410         .rx_init = efx_ef10_rx_init,
4411         .rx_remove = efx_ef10_rx_remove,
4412         .rx_write = efx_ef10_rx_write,
4413         .rx_defer_refill = efx_ef10_rx_defer_refill,
4414         .ev_probe = efx_ef10_ev_probe,
4415         .ev_init = efx_ef10_ev_init,
4416         .ev_fini = efx_ef10_ev_fini,
4417         .ev_remove = efx_ef10_ev_remove,
4418         .ev_process = efx_ef10_ev_process,
4419         .ev_read_ack = efx_ef10_ev_read_ack,
4420         .ev_test_generate = efx_ef10_ev_test_generate,
4421         .filter_table_probe = efx_ef10_filter_table_probe,
4422         .filter_table_restore = efx_ef10_filter_table_restore,
4423         .filter_table_remove = efx_ef10_filter_table_remove,
4424         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4425         .filter_insert = efx_ef10_filter_insert,
4426         .filter_remove_safe = efx_ef10_filter_remove_safe,
4427         .filter_get_safe = efx_ef10_filter_get_safe,
4428         .filter_clear_rx = efx_ef10_filter_clear_rx,
4429         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4430         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4431         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4432 #ifdef CONFIG_RFS_ACCEL
4433         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4434         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4435 #endif
4436 #ifdef CONFIG_SFC_MTD
4437         .mtd_probe = efx_port_dummy_op_int,
4438 #endif
4439         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4440         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4441 #ifdef CONFIG_SFC_SRIOV
4442         .vswitching_probe = efx_ef10_vswitching_probe_vf,
4443         .vswitching_restore = efx_ef10_vswitching_restore_vf,
4444         .vswitching_remove = efx_ef10_vswitching_remove_vf,
4445         .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
4446 #endif
4447         .get_mac_address = efx_ef10_get_mac_address_vf,
4448         .set_mac_address = efx_ef10_set_mac_address,
4449
4450         .revision = EFX_REV_HUNT_A0,
4451         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4452         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4453         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4454         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4455         .can_rx_scatter = true,
4456         .always_rx_scatter = true,
4457         .max_interrupt_mode = EFX_INT_MODE_MSIX,
4458         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4459         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4460                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
4461         .mcdi_max_ver = 2,
4462         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4463         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4464                             1 << HWTSTAMP_FILTER_ALL,
4465 };
4466
4467 const struct efx_nic_type efx_hunt_a0_nic_type = {
4468         .is_vf = false,
4469         .mem_bar = EFX_MEM_BAR,
4470         .mem_map_size = efx_ef10_mem_map_size,
4471         .probe = efx_ef10_probe_pf,
4472         .remove = efx_ef10_remove,
4473         .dimension_resources = efx_ef10_dimension_resources,
4474         .init = efx_ef10_init_nic,
4475         .fini = efx_port_dummy_op_void,
4476         .map_reset_reason = efx_ef10_map_reset_reason,
4477         .map_reset_flags = efx_ef10_map_reset_flags,
4478         .reset = efx_ef10_reset,
4479         .probe_port = efx_mcdi_port_probe,
4480         .remove_port = efx_mcdi_port_remove,
4481         .fini_dmaq = efx_ef10_fini_dmaq,
4482         .prepare_flr = efx_ef10_prepare_flr,
4483         .finish_flr = efx_port_dummy_op_void,
4484         .describe_stats = efx_ef10_describe_stats,
4485         .update_stats = efx_ef10_update_stats_pf,
4486         .start_stats = efx_mcdi_mac_start_stats,
4487         .pull_stats = efx_mcdi_mac_pull_stats,
4488         .stop_stats = efx_mcdi_mac_stop_stats,
4489         .set_id_led = efx_mcdi_set_id_led,
4490         .push_irq_moderation = efx_ef10_push_irq_moderation,
4491         .reconfigure_mac = efx_ef10_mac_reconfigure,
4492         .check_mac_fault = efx_mcdi_mac_check_fault,
4493         .reconfigure_port = efx_mcdi_port_reconfigure,
4494         .get_wol = efx_ef10_get_wol,
4495         .set_wol = efx_ef10_set_wol,
4496         .resume_wol = efx_port_dummy_op_void,
4497         .test_chip = efx_ef10_test_chip,
4498         .test_nvram = efx_mcdi_nvram_test_all,
4499         .mcdi_request = efx_ef10_mcdi_request,
4500         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4501         .mcdi_read_response = efx_ef10_mcdi_read_response,
4502         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4503         .irq_enable_master = efx_port_dummy_op_void,
4504         .irq_test_generate = efx_ef10_irq_test_generate,
4505         .irq_disable_non_ev = efx_port_dummy_op_void,
4506         .irq_handle_msi = efx_ef10_msi_interrupt,
4507         .irq_handle_legacy = efx_ef10_legacy_interrupt,
4508         .tx_probe = efx_ef10_tx_probe,
4509         .tx_init = efx_ef10_tx_init,
4510         .tx_remove = efx_ef10_tx_remove,
4511         .tx_write = efx_ef10_tx_write,
4512         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
4513         .rx_probe = efx_ef10_rx_probe,
4514         .rx_init = efx_ef10_rx_init,
4515         .rx_remove = efx_ef10_rx_remove,
4516         .rx_write = efx_ef10_rx_write,
4517         .rx_defer_refill = efx_ef10_rx_defer_refill,
4518         .ev_probe = efx_ef10_ev_probe,
4519         .ev_init = efx_ef10_ev_init,
4520         .ev_fini = efx_ef10_ev_fini,
4521         .ev_remove = efx_ef10_ev_remove,
4522         .ev_process = efx_ef10_ev_process,
4523         .ev_read_ack = efx_ef10_ev_read_ack,
4524         .ev_test_generate = efx_ef10_ev_test_generate,
4525         .filter_table_probe = efx_ef10_filter_table_probe,
4526         .filter_table_restore = efx_ef10_filter_table_restore,
4527         .filter_table_remove = efx_ef10_filter_table_remove,
4528         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4529         .filter_insert = efx_ef10_filter_insert,
4530         .filter_remove_safe = efx_ef10_filter_remove_safe,
4531         .filter_get_safe = efx_ef10_filter_get_safe,
4532         .filter_clear_rx = efx_ef10_filter_clear_rx,
4533         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4534         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4535         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4536 #ifdef CONFIG_RFS_ACCEL
4537         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4538         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4539 #endif
4540 #ifdef CONFIG_SFC_MTD
4541         .mtd_probe = efx_ef10_mtd_probe,
4542         .mtd_rename = efx_mcdi_mtd_rename,
4543         .mtd_read = efx_mcdi_mtd_read,
4544         .mtd_erase = efx_mcdi_mtd_erase,
4545         .mtd_write = efx_mcdi_mtd_write,
4546         .mtd_sync = efx_mcdi_mtd_sync,
4547 #endif
4548         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
4549         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4550         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4551 #ifdef CONFIG_SFC_SRIOV
4552         .sriov_configure = efx_ef10_sriov_configure,
4553         .sriov_init = efx_ef10_sriov_init,
4554         .sriov_fini = efx_ef10_sriov_fini,
4555         .sriov_wanted = efx_ef10_sriov_wanted,
4556         .sriov_reset = efx_ef10_sriov_reset,
4557         .sriov_flr = efx_ef10_sriov_flr,
4558         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4559         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4560         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4561         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4562         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
4563         .vswitching_probe = efx_ef10_vswitching_probe_pf,
4564         .vswitching_restore = efx_ef10_vswitching_restore_pf,
4565         .vswitching_remove = efx_ef10_vswitching_remove_pf,
4566 #endif
4567         .get_mac_address = efx_ef10_get_mac_address_pf,
4568         .set_mac_address = efx_ef10_set_mac_address,
4569
4570         .revision = EFX_REV_HUNT_A0,
4571         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4572         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4573         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4574         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4575         .can_rx_scatter = true,
4576         .always_rx_scatter = true,
4577         .max_interrupt_mode = EFX_INT_MODE_MSIX,
4578         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4579         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4580                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
4581         .mcdi_max_ver = 2,
4582         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4583         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4584                             1 << HWTSTAMP_FILTER_ALL,
4585 };