drivers/net/ethernet/sfc/farch.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/pci.h>
  15 #include <linux/module.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/crc32.h>
  18 #include "net_driver.h"
  19 #include "bitfield.h"
  20 #include "efx.h"
  21 #include "nic.h"
  22 #include "farch_regs.h"
  23 #include "io.h"
  24 #include "workarounds.h"
  25
  26 /* Falcon-architecture (SFC4000 and SFC9000-family) support */
  27
  28 /**************************************************************************
  29  *
  30  * Configurable values
  31  *
  32  **************************************************************************
  33  */
  34
  35 /* This is set to 16 for a good reason.  In summary, if larger than
  36  * 16, the descriptor cache holds more than a default socket
  37  * buffer's worth of packets (for UDP we can only have at most one
  38  * socket buffer's worth outstanding).  This combined with the fact
  39  * that we only get 1 TX event per descriptor cache means the NIC
  40  * goes idle.
  41  */
  42 #define TX_DC_ENTRIES 16
  43 #define TX_DC_ENTRIES_ORDER 1
  44
  45 #define RX_DC_ENTRIES 64
  46 #define RX_DC_ENTRIES_ORDER 3
  47
  48 /* If EFX_MAX_INT_ERRORS internal errors occur within
  49  * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
  50  * disable it.
  51  */
  52 #define EFX_INT_ERROR_EXPIRE 3600
  53 #define EFX_MAX_INT_ERRORS 5
  54
  55 /* Depth of RX flush request fifo */
  56 #define EFX_RX_FLUSH_COUNT 4
  57
  58 /* Driver generated events */
  59 #define _EFX_CHANNEL_MAGIC_TEST         0x000101
  60 #define _EFX_CHANNEL_MAGIC_FILL         0x000102
  61 #define _EFX_CHANNEL_MAGIC_RX_DRAIN     0x000103
  62 #define _EFX_CHANNEL_MAGIC_TX_DRAIN     0x000104
  63
  64 #define _EFX_CHANNEL_MAGIC(_code, _data)        ((_code) << 8 | (_data))
  65 #define _EFX_CHANNEL_MAGIC_CODE(_magic)         ((_magic) >> 8)
  66
  67 #define EFX_CHANNEL_MAGIC_TEST(_channel)                                \
  68         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel)
  69 #define EFX_CHANNEL_MAGIC_FILL(_rx_queue)                               \
  70         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL,                     \
  71                            efx_rx_queue_index(_rx_queue))
  72 #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue)                           \
  73         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN,                 \
  74                            efx_rx_queue_index(_rx_queue))
  75 #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue)                           \
  76         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN,                 \
  77                            (_tx_queue)->queue)
  78
  79 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic);
  80
  81 /**************************************************************************
  82  *
  83  * Hardware access
  84  *
  85  **************************************************************************/
  86
  87 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
  88                                      unsigned int index)
  89 {
  90         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
  91                         value, index);
  92 }
  93
  94 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
  95                                      const efx_oword_t *mask)
  96 {
  97         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
  98                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
  99 }
 100
 101 int efx_farch_test_registers(struct efx_nic *efx,
 102                              const struct efx_farch_register_test *regs,
 103                              size_t n_regs)
 104 {
 105         unsigned address = 0, i, j;
 106         efx_oword_t mask, imask, original, reg, buf;
 107
 108         for (i = 0; i < n_regs; ++i) {
 109                 address = regs[i].address;
 110                 mask = imask = regs[i].mask;
 111                 EFX_INVERT_OWORD(imask);
 112
 113                 efx_reado(efx, &original, address);
 114
 115                 /* bit sweep on and off */
 116                 for (j = 0; j < 128; j++) {
 117                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
 118                                 continue;
 119
 120                         /* Test this testable bit can be set in isolation */
 121                         EFX_AND_OWORD(reg, original, mask);
 122                         EFX_SET_OWORD32(reg, j, j, 1);
 123
 124                         efx_writeo(efx, &reg, address);
 125                         efx_reado(efx, &buf, address);
 126
 127                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 128                                 goto fail;
 129
 130                         /* Test this testable bit can be cleared in isolation */
 131                         EFX_OR_OWORD(reg, original, mask);
 132                         EFX_SET_OWORD32(reg, j, j, 0);
 133
 134                         efx_writeo(efx, &reg, address);
 135                         efx_reado(efx, &buf, address);
 136
 137                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 138                                 goto fail;
 139                 }
 140
 141                 efx_writeo(efx, &original, address);
 142         }
 143
 144         return 0;
 145
 146 fail:
 147         netif_err(efx, hw, efx->net_dev,
 148                   "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
 149                   " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
 150                   EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
 151         return -EIO;
 152 }
 153
 154 /**************************************************************************
 155  *
 156  * Special buffer handling
 157  * Special buffers are used for event queues and the TX and RX
 158  * descriptor rings.
 159  *
 160  *************************************************************************/
 161
 162 /*
 163  * Initialise a special buffer
 164  *
 165  * This will define a buffer (previously allocated via
 166  * efx_alloc_special_buffer()) in the buffer table, allowing
 167  * it to be used for event queues, descriptor rings etc.
 168  */
 169 static void
 170 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 171 {
 172         efx_qword_t buf_desc;
 173         unsigned int index;
 174         dma_addr_t dma_addr;
 175         int i;
 176
 177         EFX_BUG_ON_PARANOID(!buffer->buf.addr);
 178
 179         /* Write buffer descriptors to NIC */
 180         for (i = 0; i < buffer->entries; i++) {
 181                 index = buffer->index + i;
 182                 dma_addr = buffer->buf.dma_addr + (i * EFX_BUF_SIZE);
 183                 netif_dbg(efx, probe, efx->net_dev,
 184                           "mapping special buffer %d at %llx\n",
 185                           index, (unsigned long long)dma_addr);
 186                 EFX_POPULATE_QWORD_3(buf_desc,
 187                                      FRF_AZ_BUF_ADR_REGION, 0,
 188                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
 189                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
 190                 efx_write_buf_tbl(efx, &buf_desc, index);
 191         }
 192 }
 193
 194 /* Unmaps a buffer and clears the buffer table entries */
 195 static void
 196 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 197 {
 198         efx_oword_t buf_tbl_upd;
 199         unsigned int start = buffer->index;
 200         unsigned int end = (buffer->index + buffer->entries - 1);
 201
 202         if (!buffer->entries)
 203                 return;
 204
 205         netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
 206                   buffer->index, buffer->index + buffer->entries - 1);
 207
 208         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 209                              FRF_AZ_BUF_UPD_CMD, 0,
 210                              FRF_AZ_BUF_CLR_CMD, 1,
 211                              FRF_AZ_BUF_CLR_END_ID, end,
 212                              FRF_AZ_BUF_CLR_START_ID, start);
 213         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
 214 }
 215
 216 /*
 217  * Allocate a new special buffer
 218  *
 219  * This allocates memory for a new buffer, clears it and allocates a
 220  * new buffer ID range.  It does not write into the buffer table.
 221  *
 222  * This call will allocate 4KB buffers, since 8KB buffers can't be
 223  * used for event queues and descriptor rings.
 224  */
 225 static int efx_alloc_special_buffer(struct efx_nic *efx,
 226                                     struct efx_special_buffer *buffer,
 227                                     unsigned int len)
 228 {
 229         len = ALIGN(len, EFX_BUF_SIZE);
 230
 231         if (efx_nic_alloc_buffer(efx, &buffer->buf, len, GFP_KERNEL))
 232                 return -ENOMEM;
 233         buffer->entries = len / EFX_BUF_SIZE;
 234         BUG_ON(buffer->buf.dma_addr & (EFX_BUF_SIZE - 1));
 235
 236         /* Select new buffer ID */
 237         buffer->index = efx->next_buffer_table;
 238         efx->next_buffer_table += buffer->entries;
 239 #ifdef CONFIG_SFC_SRIOV
 240         BUG_ON(efx_sriov_enabled(efx) &&
 241                efx->vf_buftbl_base < efx->next_buffer_table);
 242 #endif
 243
 244         netif_dbg(efx, probe, efx->net_dev,
 245                   "allocating special buffers %d-%d at %llx+%x "
 246                   "(virt %p phys %llx)\n", buffer->index,
 247                   buffer->index + buffer->entries - 1,
 248                   (u64)buffer->buf.dma_addr, len,
 249                   buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
 250
 251         return 0;
 252 }
 253
 254 static void
 255 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 256 {
 257         if (!buffer->buf.addr)
 258                 return;
 259
 260         netif_dbg(efx, hw, efx->net_dev,
 261                   "deallocating special buffers %d-%d at %llx+%x "
 262                   "(virt %p phys %llx)\n", buffer->index,
 263                   buffer->index + buffer->entries - 1,
 264                   (u64)buffer->buf.dma_addr, buffer->buf.len,
 265                   buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
 266
 267         efx_nic_free_buffer(efx, &buffer->buf);
 268         buffer->entries = 0;
 269 }
 270
 271 /**************************************************************************
 272  *
 273  * TX path
 274  *
 275  **************************************************************************/
 276
 277 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 278 static inline void efx_farch_notify_tx_desc(struct efx_tx_queue *tx_queue)
 279 {
 280         unsigned write_ptr;
 281         efx_dword_t reg;
 282
 283         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 284         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
 285         efx_writed_page(tx_queue->efx, &reg,
 286                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 287 }
 288
 289 /* Write pointer and first descriptor for TX descriptor ring */
 290 static inline void efx_farch_push_tx_desc(struct efx_tx_queue *tx_queue,
 291                                           const efx_qword_t *txd)
 292 {
 293         unsigned write_ptr;
 294         efx_oword_t reg;
 295
 296         BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
 297         BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
 298
 299         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 300         EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
 301                              FRF_AZ_TX_DESC_WPTR, write_ptr);
 302         reg.qword[0] = *txd;
 303         efx_writeo_page(tx_queue->efx, &reg,
 304                         FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
 305 }
 306
 307
 308 /* For each entry inserted into the software descriptor ring, create a
 309  * descriptor in the hardware TX descriptor ring (in host memory), and
 310  * write a doorbell.
 311  */
 312 void efx_farch_tx_write(struct efx_tx_queue *tx_queue)
 313 {
 314         struct efx_tx_buffer *buffer;
 315         efx_qword_t *txd;
 316         unsigned write_ptr;
 317         unsigned old_write_count = tx_queue->write_count;
 318
 319         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 320
 321         do {
 322                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 323                 buffer = &tx_queue->buffer[write_ptr];
 324                 txd = efx_tx_desc(tx_queue, write_ptr);
 325                 ++tx_queue->write_count;
 326
 327                 EFX_BUG_ON_PARANOID(buffer->flags & EFX_TX_BUF_OPTION);
 328
 329                 /* Create TX descriptor ring entry */
 330                 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
 331                 EFX_POPULATE_QWORD_4(*txd,
 332                                      FSF_AZ_TX_KER_CONT,
 333                                      buffer->flags & EFX_TX_BUF_CONT,
 334                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
 335                                      FSF_AZ_TX_KER_BUF_REGION, 0,
 336                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 337         } while (tx_queue->write_count != tx_queue->insert_count);
 338
 339         wmb(); /* Ensure descriptors are written before they are fetched */
 340
 341         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
 342                 txd = efx_tx_desc(tx_queue,
 343                                   old_write_count & tx_queue->ptr_mask);
 344                 efx_farch_push_tx_desc(tx_queue, txd);
 345                 ++tx_queue->pushes;
 346         } else {
 347                 efx_farch_notify_tx_desc(tx_queue);
 348         }
 349 }
 350
 351 /* Allocate hardware resources for a TX queue */
 352 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue)
 353 {
 354         struct efx_nic *efx = tx_queue->efx;
 355         unsigned entries;
 356
 357         entries = tx_queue->ptr_mask + 1;
 358         return efx_alloc_special_buffer(efx, &tx_queue->txd,
 359                                         entries * sizeof(efx_qword_t));
 360 }
 361
 362 void efx_farch_tx_init(struct efx_tx_queue *tx_queue)
 363 {
 364         struct efx_nic *efx = tx_queue->efx;
 365         efx_oword_t reg;
 366
 367         /* Pin TX descriptor ring */
 368         efx_init_special_buffer(efx, &tx_queue->txd);
 369
 370         /* Push TX descriptor ring to card */
 371         EFX_POPULATE_OWORD_10(reg,
 372                               FRF_AZ_TX_DESCQ_EN, 1,
 373                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
 374                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
 375                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 376                               FRF_AZ_TX_DESCQ_EVQ_ID,
 377                               tx_queue->channel->channel,
 378                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
 379                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
 380                               FRF_AZ_TX_DESCQ_SIZE,
 381                               __ffs(tx_queue->txd.entries),
 382                               FRF_AZ_TX_DESCQ_TYPE, 0,
 383                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
 384
 385         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 386                 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
 387                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
 388                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS,
 389                                     !csum);
 390         }
 391
 392         efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
 393                          tx_queue->queue);
 394
 395         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 396                 /* Only 128 bits in this register */
 397                 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
 398
 399                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
 400                 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
 401                         __clear_bit_le(tx_queue->queue, &reg);
 402                 else
 403                         __set_bit_le(tx_queue->queue, &reg);
 404                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
 405         }
 406
 407         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 408                 EFX_POPULATE_OWORD_1(reg,
 409                                      FRF_BZ_TX_PACE,
 410                                      (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
 411                                      FFE_BZ_TX_PACE_OFF :
 412                                      FFE_BZ_TX_PACE_RESERVED);
 413                 efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL,
 414                                  tx_queue->queue);
 415         }
 416 }
 417
 418 static void efx_farch_flush_tx_queue(struct efx_tx_queue *tx_queue)
 419 {
 420         struct efx_nic *efx = tx_queue->efx;
 421         efx_oword_t tx_flush_descq;
 422
 423         WARN_ON(atomic_read(&tx_queue->flush_outstanding));
 424         atomic_set(&tx_queue->flush_outstanding, 1);
 425
 426         EFX_POPULATE_OWORD_2(tx_flush_descq,
 427                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
 428                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
 429         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
 430 }
 431
 432 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue)
 433 {
 434         struct efx_nic *efx = tx_queue->efx;
 435         efx_oword_t tx_desc_ptr;
 436
 437         /* Remove TX descriptor ring from card */
 438         EFX_ZERO_OWORD(tx_desc_ptr);
 439         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 440                          tx_queue->queue);
 441
 442         /* Unpin TX descriptor ring */
 443         efx_fini_special_buffer(efx, &tx_queue->txd);
 444 }
 445
 446 /* Free buffers backing TX queue */
 447 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue)
 448 {
 449         efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 450 }
 451
 452 /**************************************************************************
 453  *
 454  * RX path
 455  *
 456  **************************************************************************/
 457
 458 /* This creates an entry in the RX descriptor queue */
 459 static inline void
 460 efx_farch_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
 461 {
 462         struct efx_rx_buffer *rx_buf;
 463         efx_qword_t *rxd;
 464
 465         rxd = efx_rx_desc(rx_queue, index);
 466         rx_buf = efx_rx_buffer(rx_queue, index);
 467         EFX_POPULATE_QWORD_3(*rxd,
 468                              FSF_AZ_RX_KER_BUF_SIZE,
 469                              rx_buf->len -
 470                              rx_queue->efx->type->rx_buffer_padding,
 471                              FSF_AZ_RX_KER_BUF_REGION, 0,
 472                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
 473 }
 474
 475 /* This writes to the RX_DESC_WPTR register for the specified receive
 476  * descriptor ring.
 477  */
 478 void efx_farch_rx_write(struct efx_rx_queue *rx_queue)
 479 {
 480         struct efx_nic *efx = rx_queue->efx;
 481         efx_dword_t reg;
 482         unsigned write_ptr;
 483
 484         while (rx_queue->notified_count != rx_queue->added_count) {
 485                 efx_farch_build_rx_desc(
 486                         rx_queue,
 487                         rx_queue->notified_count & rx_queue->ptr_mask);
 488                 ++rx_queue->notified_count;
 489         }
 490
 491         wmb();
 492         write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
 493         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
 494         efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
 495                         efx_rx_queue_index(rx_queue));
 496 }
 497
 498 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue)
 499 {
 500         struct efx_nic *efx = rx_queue->efx;
 501         unsigned entries;
 502
 503         entries = rx_queue->ptr_mask + 1;
 504         return efx_alloc_special_buffer(efx, &rx_queue->rxd,
 505                                         entries * sizeof(efx_qword_t));
 506 }
 507
 508 void efx_farch_rx_init(struct efx_rx_queue *rx_queue)
 509 {
 510         efx_oword_t rx_desc_ptr;
 511         struct efx_nic *efx = rx_queue->efx;
 512         bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
 513         bool iscsi_digest_en = is_b0;
 514         bool jumbo_en;
 515
 516         /* For kernel-mode queues in Falcon A1, the JUMBO flag enables
 517          * DMA to continue after a PCIe page boundary (and scattering
 518          * is not possible).  In Falcon B0 and Siena, it enables
 519          * scatter.
 520          */
 521         jumbo_en = !is_b0 || efx->rx_scatter;
 522
 523         netif_dbg(efx, hw, efx->net_dev,
 524                   "RX queue %d ring in special buffers %d-%d\n",
 525                   efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
 526                   rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 527
 528         rx_queue->scatter_n = 0;
 529
 530         /* Pin RX descriptor ring */
 531         efx_init_special_buffer(efx, &rx_queue->rxd);
 532
 533         /* Push RX descriptor ring to card */
 534         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 535                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
 536                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
 537                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 538                               FRF_AZ_RX_DESCQ_EVQ_ID,
 539                               efx_rx_queue_channel(rx_queue)->channel,
 540                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
 541                               FRF_AZ_RX_DESCQ_LABEL,
 542                               efx_rx_queue_index(rx_queue),
 543                               FRF_AZ_RX_DESCQ_SIZE,
 544                               __ffs(rx_queue->rxd.entries),
 545                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 546                               FRF_AZ_RX_DESCQ_JUMBO, jumbo_en,
 547                               FRF_AZ_RX_DESCQ_EN, 1);
 548         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 549                          efx_rx_queue_index(rx_queue));
 550 }
 551
 552 static void efx_farch_flush_rx_queue(struct efx_rx_queue *rx_queue)
 553 {
 554         struct efx_nic *efx = rx_queue->efx;
 555         efx_oword_t rx_flush_descq;
 556
 557         EFX_POPULATE_OWORD_2(rx_flush_descq,
 558                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
 559                              FRF_AZ_RX_FLUSH_DESCQ,
 560                              efx_rx_queue_index(rx_queue));
 561         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
 562 }
 563
 564 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue)
 565 {
 566         efx_oword_t rx_desc_ptr;
 567         struct efx_nic *efx = rx_queue->efx;
 568
 569         /* Remove RX descriptor ring from card */
 570         EFX_ZERO_OWORD(rx_desc_ptr);
 571         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 572                          efx_rx_queue_index(rx_queue));
 573
 574         /* Unpin RX descriptor ring */
 575         efx_fini_special_buffer(efx, &rx_queue->rxd);
 576 }
 577
 578 /* Free buffers backing RX queue */
 579 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue)
 580 {
 581         efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 582 }
 583
 584 /**************************************************************************
 585  *
 586  * Flush handling
 587  *
 588  **************************************************************************/
 589
 590 /* efx_farch_flush_queues() must be woken up when all flushes are completed,
 591  * or more RX flushes can be kicked off.
 592  */
 593 static bool efx_farch_flush_wake(struct efx_nic *efx)
 594 {
 595         /* Ensure that all updates are visible to efx_farch_flush_queues() */
 596         smp_mb();
 597
 598         return (atomic_read(&efx->active_queues) == 0 ||
 599                 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT
 600                  && atomic_read(&efx->rxq_flush_pending) > 0));
 601 }
 602
 603 static bool efx_check_tx_flush_complete(struct efx_nic *efx)
 604 {
 605         bool i = true;
 606         efx_oword_t txd_ptr_tbl;
 607         struct efx_channel *channel;
 608         struct efx_tx_queue *tx_queue;
 609
 610         efx_for_each_channel(channel, efx) {
 611                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 612                         efx_reado_table(efx, &txd_ptr_tbl,
 613                                         FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue);
 614                         if (EFX_OWORD_FIELD(txd_ptr_tbl,
 615                                             FRF_AZ_TX_DESCQ_FLUSH) ||
 616                             EFX_OWORD_FIELD(txd_ptr_tbl,
 617                                             FRF_AZ_TX_DESCQ_EN)) {
 618                                 netif_dbg(efx, hw, efx->net_dev,
 619                                           "flush did not complete on TXQ %d\n",
 620                                           tx_queue->queue);
 621                                 i = false;
 622                         } else if (atomic_cmpxchg(&tx_queue->flush_outstanding,
 623                                                   1, 0)) {
 624                                 /* The flush is complete, but we didn't
 625                                  * receive a flush completion event
 626                                  */
 627                                 netif_dbg(efx, hw, efx->net_dev,
 628                                           "flush complete on TXQ %d, so drain "
 629                                           "the queue\n", tx_queue->queue);
 630                                 /* Don't need to increment active_queues as it
 631                                  * has already been incremented for the queues
 632                                  * which did not drain
 633                                  */
 634                                 efx_farch_magic_event(channel,
 635                                                       EFX_CHANNEL_MAGIC_TX_DRAIN(
 636                                                               tx_queue));
 637                         }
 638                 }
 639         }
 640
 641         return i;
 642 }
 643
 644 /* Flush all the transmit queues, and continue flushing receive queues until
 645  * they're all flushed. Wait for the DRAIN events to be recieved so that there
 646  * are no more RX and TX events left on any channel. */
 647 static int efx_farch_do_flush(struct efx_nic *efx)
 648 {
 649         unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */
 650         struct efx_channel *channel;
 651         struct efx_rx_queue *rx_queue;
 652         struct efx_tx_queue *tx_queue;
 653         int rc = 0;
 654
 655         efx_for_each_channel(channel, efx) {
 656                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 657                         efx_farch_flush_tx_queue(tx_queue);
 658                 }
 659                 efx_for_each_channel_rx_queue(rx_queue, channel) {
 660                         rx_queue->flush_pending = true;
 661                         atomic_inc(&efx->rxq_flush_pending);
 662                 }
 663         }
 664
 665         while (timeout && atomic_read(&efx->active_queues) > 0) {
 666                 /* If SRIOV is enabled, then offload receive queue flushing to
 667                  * the firmware (though we will still have to poll for
 668                  * completion). If that fails, fall back to the old scheme.
 669                  */
 670                 if (efx_sriov_enabled(efx)) {
 671                         rc = efx_mcdi_flush_rxqs(efx);
 672                         if (!rc)
 673                                 goto wait;
 674                 }
 675
 676                 /* The hardware supports four concurrent rx flushes, each of
 677                  * which may need to be retried if there is an outstanding
 678                  * descriptor fetch
 679                  */
 680                 efx_for_each_channel(channel, efx) {
 681                         efx_for_each_channel_rx_queue(rx_queue, channel) {
 682                                 if (atomic_read(&efx->rxq_flush_outstanding) >=
 683                                     EFX_RX_FLUSH_COUNT)
 684                                         break;
 685
 686                                 if (rx_queue->flush_pending) {
 687                                         rx_queue->flush_pending = false;
 688                                         atomic_dec(&efx->rxq_flush_pending);
 689                                         atomic_inc(&efx->rxq_flush_outstanding);
 690                                         efx_farch_flush_rx_queue(rx_queue);
 691                                 }
 692                         }
 693                 }
 694
 695         wait:
 696                 timeout = wait_event_timeout(efx->flush_wq,
 697                                              efx_farch_flush_wake(efx),
 698                                              timeout);
 699         }
 700
 701         if (atomic_read(&efx->active_queues) &&
 702             !efx_check_tx_flush_complete(efx)) {
 703                 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues "
 704                           "(rx %d+%d)\n", atomic_read(&efx->active_queues),
 705                           atomic_read(&efx->rxq_flush_outstanding),
 706                           atomic_read(&efx->rxq_flush_pending));
 707                 rc = -ETIMEDOUT;
 708
 709                 atomic_set(&efx->active_queues, 0);
 710                 atomic_set(&efx->rxq_flush_pending, 0);
 711                 atomic_set(&efx->rxq_flush_outstanding, 0);
 712         }
 713
 714         return rc;
 715 }
 716
 717 int efx_farch_fini_dmaq(struct efx_nic *efx)
 718 {
 719         struct efx_channel *channel;
 720         struct efx_tx_queue *tx_queue;
 721         struct efx_rx_queue *rx_queue;
 722         int rc = 0;
 723
 724         /* Do not attempt to write to the NIC during EEH recovery */
 725         if (efx->state != STATE_RECOVERY) {
 726                 /* Only perform flush if DMA is enabled */
 727                 if (efx->pci_dev->is_busmaster) {
 728                         efx->type->prepare_flush(efx);
 729                         rc = efx_farch_do_flush(efx);
 730                         efx->type->finish_flush(efx);
 731                 }
 732
 733                 efx_for_each_channel(channel, efx) {
 734                         efx_for_each_channel_rx_queue(rx_queue, channel)
 735                                 efx_farch_rx_fini(rx_queue);
 736                         efx_for_each_channel_tx_queue(tx_queue, channel)
 737                                 efx_farch_tx_fini(tx_queue);
 738                 }
 739         }
 740
 741         return rc;
 742 }
 743
 744 /* Reset queue and flush accounting after FLR
 745  *
 746  * One possible cause of FLR recovery is that DMA may be failing (eg. if bus
 747  * mastering was disabled), in which case we don't receive (RXQ) flush
 748  * completion events.  This means that efx->rxq_flush_outstanding remained at 4
 749  * after the FLR; also, efx->active_queues was non-zero (as no flush completion
 750  * events were received, and we didn't go through efx_check_tx_flush_complete())
 751  * If we don't fix this up, on the next call to efx_realloc_channels() we won't
 752  * flush any RX queues because efx->rxq_flush_outstanding is at the limit of 4
 753  * for batched flush requests; and the efx->active_queues gets messed up because
 754  * we keep incrementing for the newly initialised queues, but it never went to
 755  * zero previously.  Then we get a timeout every time we try to restart the
 756  * queues, as it doesn't go back to zero when we should be flushing the queues.
 757  */
 758 void efx_farch_finish_flr(struct efx_nic *efx)
 759 {
 760         atomic_set(&efx->rxq_flush_pending, 0);
 761         atomic_set(&efx->rxq_flush_outstanding, 0);
 762         atomic_set(&efx->active_queues, 0);
 763 }
 764
 765
 766 /**************************************************************************
 767  *
 768  * Event queue processing
 769  * Event queues are processed by per-channel tasklets.
 770  *
 771  **************************************************************************/
 772
 773 /* Update a channel's event queue's read pointer (RPTR) register
 774  *
 775  * This writes the EVQ_RPTR_REG register for the specified channel's
 776  * event queue.
 777  */
 778 void efx_farch_ev_read_ack(struct efx_channel *channel)
 779 {
 780         efx_dword_t reg;
 781         struct efx_nic *efx = channel->efx;
 782
 783         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
 784                              channel->eventq_read_ptr & channel->eventq_mask);
 785
 786         /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size
 787          * of 4 bytes, but it is really 16 bytes just like later revisions.
 788          */
 789         efx_writed(efx, &reg,
 790                    efx->type->evq_rptr_tbl_base +
 791                    FR_BZ_EVQ_RPTR_STEP * channel->channel);
 792 }
 793
 794 /* Use HW to insert a SW defined event */
 795 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
 796                               efx_qword_t *event)
 797 {
 798         efx_oword_t drv_ev_reg;
 799
 800         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
 801                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
 802         drv_ev_reg.u32[0] = event->u32[0];
 803         drv_ev_reg.u32[1] = event->u32[1];
 804         drv_ev_reg.u32[2] = 0;
 805         drv_ev_reg.u32[3] = 0;
 806         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq);
 807         efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV);
 808 }
 809
 810 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic)
 811 {
 812         efx_qword_t event;
 813
 814         EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE,
 815                              FSE_AZ_EV_CODE_DRV_GEN_EV,
 816                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
 817         efx_farch_generate_event(channel->efx, channel->channel, &event);
 818 }
 819
 820 /* Handle a transmit completion event
 821  *
 822  * The NIC batches TX completion events; the message we receive is of
 823  * the form "complete all TX events up to this index".
 824  */
 825 static int
 826 efx_farch_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
 827 {
 828         unsigned int tx_ev_desc_ptr;
 829         unsigned int tx_ev_q_label;
 830         struct efx_tx_queue *tx_queue;
 831         struct efx_nic *efx = channel->efx;
 832         int tx_packets = 0;
 833
 834         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
 835                 return 0;
 836
 837         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
 838                 /* Transmit completion */
 839                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
 840                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 841                 tx_queue = efx_channel_get_tx_queue(
 842                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 843                 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
 844                               tx_queue->ptr_mask);
 845                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 846         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
 847                 /* Rewrite the FIFO write pointer */
 848                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 849                 tx_queue = efx_channel_get_tx_queue(
 850                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 851
 852                 netif_tx_lock(efx->net_dev);
 853                 efx_farch_notify_tx_desc(tx_queue);
 854                 netif_tx_unlock(efx->net_dev);
 855         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR)) {
 856                 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
 857         } else {
 858                 netif_err(efx, tx_err, efx->net_dev,
 859                           "channel %d unexpected TX event "
 860                           EFX_QWORD_FMT"\n", channel->channel,
 861                           EFX_QWORD_VAL(*event));
 862         }
 863
 864         return tx_packets;
 865 }
 866
 867 /* Detect errors included in the rx_evt_pkt_ok bit. */
 868 static u16 efx_farch_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 869                                       const efx_qword_t *event)
 870 {
 871         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 872         struct efx_nic *efx = rx_queue->efx;
 873         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 874         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 875         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 876         bool rx_ev_other_err, rx_ev_pause_frm;
 877         bool rx_ev_hdr_type, rx_ev_mcast_pkt;
 878         unsigned rx_ev_pkt_type;
 879
 880         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 881         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 882         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
 883         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
 884         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 885                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
 886         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 887                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
 888         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 889                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
 890         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
 891         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
 892         rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
 893                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
 894         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
 895
 896         /* Every error apart from tobe_disc and pause_frm */
 897         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 898                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 899                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 900
 901         /* Count errors that are not in MAC stats.  Ignore expected
 902          * checksum errors during self-test. */
 903         if (rx_ev_frm_trunc)
 904                 ++channel->n_rx_frm_trunc;
 905         else if (rx_ev_tobe_disc)
 906                 ++channel->n_rx_tobe_disc;
 907         else if (!efx->loopback_selftest) {
 908                 if (rx_ev_ip_hdr_chksum_err)
 909                         ++channel->n_rx_ip_hdr_chksum_err;
 910                 else if (rx_ev_tcp_udp_chksum_err)
 911                         ++channel->n_rx_tcp_udp_chksum_err;
 912         }
 913
 914         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 915          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 916          * to a FIFO overflow.
 917          */
 918 #ifdef DEBUG
 919         if (rx_ev_other_err && net_ratelimit()) {
 920                 netif_dbg(efx, rx_err, efx->net_dev,
 921                           " RX queue %d unexpected RX event "
 922                           EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 923                           efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
 924                           rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 925                           rx_ev_ip_hdr_chksum_err ?
 926                           " [IP_HDR_CHKSUM_ERR]" : "",
 927                           rx_ev_tcp_udp_chksum_err ?
 928                           " [TCP_UDP_CHKSUM_ERR]" : "",
 929                           rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 930                           rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 931                           rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 932                           rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 933                           rx_ev_pause_frm ? " [PAUSE]" : "");
 934         }
 935 #endif
 936
 937         /* The frame must be discarded if any of these are true. */
 938         return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 939                 rx_ev_tobe_disc | rx_ev_pause_frm) ?
 940                 EFX_RX_PKT_DISCARD : 0;
 941 }
 942
 943 /* Handle receive events that are not in-order. Return true if this
 944  * can be handled as a partial packet discard, false if it's more
 945  * serious.
 946  */
 947 static bool
 948 efx_farch_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
 949 {
 950         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 951         struct efx_nic *efx = rx_queue->efx;
 952         unsigned expected, dropped;
 953
 954         if (rx_queue->scatter_n &&
 955             index == ((rx_queue->removed_count + rx_queue->scatter_n - 1) &
 956                       rx_queue->ptr_mask)) {
 957                 ++channel->n_rx_nodesc_trunc;
 958                 return true;
 959         }
 960
 961         expected = rx_queue->removed_count & rx_queue->ptr_mask;
 962         dropped = (index - expected) & rx_queue->ptr_mask;
 963         netif_info(efx, rx_err, efx->net_dev,
 964                    "dropped %d events (index=%d expected=%d)\n",
 965                    dropped, index, expected);
 966
 967         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 968                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 969         return false;
 970 }
 971
 972 /* Handle a packet received event
 973  *
 974  * The NIC gives a "discard" flag if it's a unicast packet with the
 975  * wrong destination address
 976  * Also "is multicast" and "matches multicast filter" flags can be used to
 977  * discard non-matching multicast packets.
 978  */
 979 static void
 980 efx_farch_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
 981 {
 982         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 983         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 984         unsigned expected_ptr;
 985         bool rx_ev_pkt_ok, rx_ev_sop, rx_ev_cont;
 986         u16 flags;
 987         struct efx_rx_queue *rx_queue;
 988         struct efx_nic *efx = channel->efx;
 989
 990         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
 991                 return;
 992
 993         rx_ev_cont = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT);
 994         rx_ev_sop = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP);
 995         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
 996                 channel->channel);
 997
 998         rx_queue = efx_channel_get_rx_queue(channel);
 999
1000         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
1001         expected_ptr = ((rx_queue->removed_count + rx_queue->scatter_n) &
1002                         rx_queue->ptr_mask);
1003
1004         /* Check for partial drops and other errors */
1005         if (unlikely(rx_ev_desc_ptr != expected_ptr) ||
1006             unlikely(rx_ev_sop != (rx_queue->scatter_n == 0))) {
1007                 if (rx_ev_desc_ptr != expected_ptr &&
1008                     !efx_farch_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr))
1009                         return;
1010
1011                 /* Discard all pending fragments */
1012                 if (rx_queue->scatter_n) {
1013                         efx_rx_packet(
1014                                 rx_queue,
1015                                 rx_queue->removed_count & rx_queue->ptr_mask,
1016                                 rx_queue->scatter_n, 0, EFX_RX_PKT_DISCARD);
1017                         rx_queue->removed_count += rx_queue->scatter_n;
1018                         rx_queue->scatter_n = 0;
1019                 }
1020
1021                 /* Return if there is no new fragment */
1022                 if (rx_ev_desc_ptr != expected_ptr)
1023                         return;
1024
1025                 /* Discard new fragment if not SOP */
1026                 if (!rx_ev_sop) {
1027                         efx_rx_packet(
1028                                 rx_queue,
1029                                 rx_queue->removed_count & rx_queue->ptr_mask,
1030                                 1, 0, EFX_RX_PKT_DISCARD);
1031                         ++rx_queue->removed_count;
1032                         return;
1033                 }
1034         }
1035
1036         ++rx_queue->scatter_n;
1037         if (rx_ev_cont)
1038                 return;
1039
1040         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
1041         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
1042         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
1043
1044         if (likely(rx_ev_pkt_ok)) {
1045                 /* If packet is marked as OK then we can rely on the
1046                  * hardware checksum and classification.
1047                  */
1048                 flags = 0;
1049                 switch (rx_ev_hdr_type) {
1050                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
1051                         flags |= EFX_RX_PKT_TCP;
1052                         /* fall through */
1053                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
1054                         flags |= EFX_RX_PKT_CSUMMED;
1055                         /* fall through */
1056                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
1057                 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
1058                         break;
1059                 }
1060         } else {
1061                 flags = efx_farch_handle_rx_not_ok(rx_queue, event);
1062         }
1063
1064         /* Detect multicast packets that didn't match the filter */
1065         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
1066         if (rx_ev_mcast_pkt) {
1067                 unsigned int rx_ev_mcast_hash_match =
1068                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
1069
1070                 if (unlikely(!rx_ev_mcast_hash_match)) {
1071                         ++channel->n_rx_mcast_mismatch;
1072                         flags |= EFX_RX_PKT_DISCARD;
1073                 }
1074         }
1075
1076         channel->irq_mod_score += 2;
1077
1078         /* Handle received packet */
1079         efx_rx_packet(rx_queue,
1080                       rx_queue->removed_count & rx_queue->ptr_mask,
1081                       rx_queue->scatter_n, rx_ev_byte_cnt, flags);
1082         rx_queue->removed_count += rx_queue->scatter_n;
1083         rx_queue->scatter_n = 0;
1084 }
1085
1086 /* If this flush done event corresponds to a &struct efx_tx_queue, then
1087  * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue
1088  * of all transmit completions.
1089  */
1090 static void
1091 efx_farch_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1092 {
1093         struct efx_tx_queue *tx_queue;
1094         int qid;
1095
1096         qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1097         if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) {
1098                 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES,
1099                                             qid % EFX_TXQ_TYPES);
1100                 if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) {
1101                         efx_farch_magic_event(tx_queue->channel,
1102                                               EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue));
1103                 }
1104         }
1105 }
1106
1107 /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
1108  * was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
1109  * the RX queue back to the mask of RX queues in need of flushing.
1110  */
1111 static void
1112 efx_farch_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1113 {
1114         struct efx_channel *channel;
1115         struct efx_rx_queue *rx_queue;
1116         int qid;
1117         bool failed;
1118
1119         qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1120         failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1121         if (qid >= efx->n_channels)
1122                 return;
1123         channel = efx_get_channel(efx, qid);
1124         if (!efx_channel_has_rx_queue(channel))
1125                 return;
1126         rx_queue = efx_channel_get_rx_queue(channel);
1127
1128         if (failed) {
1129                 netif_info(efx, hw, efx->net_dev,
1130                            "RXQ %d flush retry\n", qid);
1131                 rx_queue->flush_pending = true;
1132                 atomic_inc(&efx->rxq_flush_pending);
1133         } else {
1134                 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1135                                       EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue));
1136         }
1137         atomic_dec(&efx->rxq_flush_outstanding);
1138         if (efx_farch_flush_wake(efx))
1139                 wake_up(&efx->flush_wq);
1140 }
1141
1142 static void
1143 efx_farch_handle_drain_event(struct efx_channel *channel)
1144 {
1145         struct efx_nic *efx = channel->efx;
1146
1147         WARN_ON(atomic_read(&efx->active_queues) == 0);
1148         atomic_dec(&efx->active_queues);
1149         if (efx_farch_flush_wake(efx))
1150                 wake_up(&efx->flush_wq);
1151 }
1152
1153 static void efx_farch_handle_generated_event(struct efx_channel *channel,
1154                                              efx_qword_t *event)
1155 {
1156         struct efx_nic *efx = channel->efx;
1157         struct efx_rx_queue *rx_queue =
1158                 efx_channel_has_rx_queue(channel) ?
1159                 efx_channel_get_rx_queue(channel) : NULL;
1160         unsigned magic, code;
1161
1162         magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
1163         code = _EFX_CHANNEL_MAGIC_CODE(magic);
1164
1165         if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) {
1166                 channel->event_test_cpu = raw_smp_processor_id();
1167         } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) {
1168                 /* The queue must be empty, so we won't receive any rx
1169                  * events, so efx_process_channel() won't refill the
1170                  * queue. Refill it here */
1171                 efx_fast_push_rx_descriptors(rx_queue, true);
1172         } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) {
1173                 efx_farch_handle_drain_event(channel);
1174         } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) {
1175                 efx_farch_handle_drain_event(channel);
1176         } else {
1177                 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
1178                           "generated event "EFX_QWORD_FMT"\n",
1179                           channel->channel, EFX_QWORD_VAL(*event));
1180         }
1181 }
1182
1183 static void
1184 efx_farch_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1185 {
1186         struct efx_nic *efx = channel->efx;
1187         unsigned int ev_sub_code;
1188         unsigned int ev_sub_data;
1189
1190         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
1191         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1192
1193         switch (ev_sub_code) {
1194         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
1195                 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
1196                            channel->channel, ev_sub_data);
1197                 efx_farch_handle_tx_flush_done(efx, event);
1198                 efx_sriov_tx_flush_done(efx, event);
1199                 break;
1200         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
1201                 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
1202                            channel->channel, ev_sub_data);
1203                 efx_farch_handle_rx_flush_done(efx, event);
1204                 efx_sriov_rx_flush_done(efx, event);
1205                 break;
1206         case FSE_AZ_EVQ_INIT_DONE_EV:
1207                 netif_dbg(efx, hw, efx->net_dev,
1208                           "channel %d EVQ %d initialised\n",
1209                           channel->channel, ev_sub_data);
1210                 break;
1211         case FSE_AZ_SRM_UPD_DONE_EV:
1212                 netif_vdbg(efx, hw, efx->net_dev,
1213                            "channel %d SRAM update done\n", channel->channel);
1214                 break;
1215         case FSE_AZ_WAKE_UP_EV:
1216                 netif_vdbg(efx, hw, efx->net_dev,
1217                            "channel %d RXQ %d wakeup event\n",
1218                            channel->channel, ev_sub_data);
1219                 break;
1220         case FSE_AZ_TIMER_EV:
1221                 netif_vdbg(efx, hw, efx->net_dev,
1222                            "channel %d RX queue %d timer expired\n",
1223                            channel->channel, ev_sub_data);
1224                 break;
1225         case FSE_AA_RX_RECOVER_EV:
1226                 netif_err(efx, rx_err, efx->net_dev,
1227                           "channel %d seen DRIVER RX_RESET event. "
1228                         "Resetting.\n", channel->channel);
1229                 atomic_inc(&efx->rx_reset);
1230                 efx_schedule_reset(efx,
1231                                    EFX_WORKAROUND_6555(efx) ?
1232                                    RESET_TYPE_RX_RECOVERY :
1233                                    RESET_TYPE_DISABLE);
1234                 break;
1235         case FSE_BZ_RX_DSC_ERROR_EV:
1236                 if (ev_sub_data < EFX_VI_BASE) {
1237                         netif_err(efx, rx_err, efx->net_dev,
1238                                   "RX DMA Q %d reports descriptor fetch error."
1239                                   " RX Q %d is disabled.\n", ev_sub_data,
1240                                   ev_sub_data);
1241                         efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1242                 } else
1243                         efx_sriov_desc_fetch_err(efx, ev_sub_data);
1244                 break;
1245         case FSE_BZ_TX_DSC_ERROR_EV:
1246                 if (ev_sub_data < EFX_VI_BASE) {
1247                         netif_err(efx, tx_err, efx->net_dev,
1248                                   "TX DMA Q %d reports descriptor fetch error."
1249                                   " TX Q %d is disabled.\n", ev_sub_data,
1250                                   ev_sub_data);
1251                         efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1252                 } else
1253                         efx_sriov_desc_fetch_err(efx, ev_sub_data);
1254                 break;
1255         default:
1256                 netif_vdbg(efx, hw, efx->net_dev,
1257                            "channel %d unknown driver event code %d "
1258                            "data %04x\n", channel->channel, ev_sub_code,
1259                            ev_sub_data);
1260                 break;
1261         }
1262 }
1263
1264 int efx_farch_ev_process(struct efx_channel *channel, int budget)
1265 {
1266         struct efx_nic *efx = channel->efx;
1267         unsigned int read_ptr;
1268         efx_qword_t event, *p_event;
1269         int ev_code;
1270         int tx_packets = 0;
1271         int spent = 0;
1272
1273         if (budget <= 0)
1274                 return spent;
1275
1276         read_ptr = channel->eventq_read_ptr;
1277
1278         for (;;) {
1279                 p_event = efx_event(channel, read_ptr);
1280                 event = *p_event;
1281
1282                 if (!efx_event_present(&event))
1283                         /* End of events */
1284                         break;
1285
1286                 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1287                            "channel %d event is "EFX_QWORD_FMT"\n",
1288                            channel->channel, EFX_QWORD_VAL(event));
1289
1290                 /* Clear this event by marking it all ones */
1291                 EFX_SET_QWORD(*p_event);
1292
1293                 ++read_ptr;
1294
1295                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1296
1297                 switch (ev_code) {
1298                 case FSE_AZ_EV_CODE_RX_EV:
1299                         efx_farch_handle_rx_event(channel, &event);
1300                         if (++spent == budget)
1301                                 goto out;
1302                         break;
1303                 case FSE_AZ_EV_CODE_TX_EV:
1304                         tx_packets += efx_farch_handle_tx_event(channel,
1305                                                                 &event);
1306                         if (tx_packets > efx->txq_entries) {
1307                                 spent = budget;
1308                                 goto out;
1309                         }
1310                         break;
1311                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1312                         efx_farch_handle_generated_event(channel, &event);
1313                         break;
1314                 case FSE_AZ_EV_CODE_DRIVER_EV:
1315                         efx_farch_handle_driver_event(channel, &event);
1316                         break;
1317                 case FSE_CZ_EV_CODE_USER_EV:
1318                         efx_sriov_event(channel, &event);
1319                         break;
1320                 case FSE_CZ_EV_CODE_MCDI_EV:
1321                         efx_mcdi_process_event(channel, &event);
1322                         break;
1323                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1324                         if (efx->type->handle_global_event &&
1325                             efx->type->handle_global_event(channel, &event))
1326                                 break;
1327                         /* else fall through */
1328                 default:
1329                         netif_err(channel->efx, hw, channel->efx->net_dev,
1330                                   "channel %d unknown event type %d (data "
1331                                   EFX_QWORD_FMT ")\n", channel->channel,
1332                                   ev_code, EFX_QWORD_VAL(event));
1333                 }
1334         }
1335
1336 out:
1337         channel->eventq_read_ptr = read_ptr;
1338         return spent;
1339 }
1340
1341 /* Allocate buffer table entries for event queue */
1342 int efx_farch_ev_probe(struct efx_channel *channel)
1343 {
1344         struct efx_nic *efx = channel->efx;
1345         unsigned entries;
1346
1347         entries = channel->eventq_mask + 1;
1348         return efx_alloc_special_buffer(efx, &channel->eventq,
1349                                         entries * sizeof(efx_qword_t));
1350 }
1351
1352 int efx_farch_ev_init(struct efx_channel *channel)
1353 {
1354         efx_oword_t reg;
1355         struct efx_nic *efx = channel->efx;
1356
1357         netif_dbg(efx, hw, efx->net_dev,
1358                   "channel %d event queue in special buffers %d-%d\n",
1359                   channel->channel, channel->eventq.index,
1360                   channel->eventq.index + channel->eventq.entries - 1);
1361
1362         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1363                 EFX_POPULATE_OWORD_3(reg,
1364                                      FRF_CZ_TIMER_Q_EN, 1,
1365                                      FRF_CZ_HOST_NOTIFY_MODE, 0,
1366                                      FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1367                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1368         }
1369
1370         /* Pin event queue buffer */
1371         efx_init_special_buffer(efx, &channel->eventq);
1372
1373         /* Fill event queue with all ones (i.e. empty events) */
1374         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1375
1376         /* Push event queue to card */
1377         EFX_POPULATE_OWORD_3(reg,
1378                              FRF_AZ_EVQ_EN, 1,
1379                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1380                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1381         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1382                          channel->channel);
1383
1384         return 0;
1385 }
1386
1387 void efx_farch_ev_fini(struct efx_channel *channel)
1388 {
1389         efx_oword_t reg;
1390         struct efx_nic *efx = channel->efx;
1391
1392         /* Remove event queue from card */
1393         EFX_ZERO_OWORD(reg);
1394         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1395                          channel->channel);
1396         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1397                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1398
1399         /* Unpin event queue */
1400         efx_fini_special_buffer(efx, &channel->eventq);
1401 }
1402
1403 /* Free buffers backing event queue */
1404 void efx_farch_ev_remove(struct efx_channel *channel)
1405 {
1406         efx_free_special_buffer(channel->efx, &channel->eventq);
1407 }
1408
1409
1410 void efx_farch_ev_test_generate(struct efx_channel *channel)
1411 {
1412         efx_farch_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel));
1413 }
1414
1415 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue)
1416 {
1417         efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1418                               EFX_CHANNEL_MAGIC_FILL(rx_queue));
1419 }
1420
1421 /**************************************************************************
1422  *
1423  * Hardware interrupts
1424  * The hardware interrupt handler does very little work; all the event
1425  * queue processing is carried out by per-channel tasklets.
1426  *
1427  **************************************************************************/
1428
1429 /* Enable/disable/generate interrupts */
1430 static inline void efx_farch_interrupts(struct efx_nic *efx,
1431                                       bool enabled, bool force)
1432 {
1433         efx_oword_t int_en_reg_ker;
1434
1435         EFX_POPULATE_OWORD_3(int_en_reg_ker,
1436                              FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level,
1437                              FRF_AZ_KER_INT_KER, force,
1438                              FRF_AZ_DRV_INT_EN_KER, enabled);
1439         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1440 }
1441
1442 void efx_farch_irq_enable_master(struct efx_nic *efx)
1443 {
1444         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1445         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1446
1447         efx_farch_interrupts(efx, true, false);
1448 }
1449
1450 void efx_farch_irq_disable_master(struct efx_nic *efx)
1451 {
1452         /* Disable interrupts */
1453         efx_farch_interrupts(efx, false, false);
1454 }
1455
1456 /* Generate a test interrupt
1457  * Interrupt must already have been enabled, otherwise nasty things
1458  * may happen.
1459  */
1460 void efx_farch_irq_test_generate(struct efx_nic *efx)
1461 {
1462         efx_farch_interrupts(efx, true, true);
1463 }
1464
1465 /* Process a fatal interrupt
1466  * Disable bus mastering ASAP and schedule a reset
1467  */
1468 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx)
1469 {
1470         struct falcon_nic_data *nic_data = efx->nic_data;
1471         efx_oword_t *int_ker = efx->irq_status.addr;
1472         efx_oword_t fatal_intr;
1473         int error, mem_perr;
1474
1475         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1476         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1477
1478         netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1479                   EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1480                   EFX_OWORD_VAL(fatal_intr),
1481                   error ? "disabling bus mastering" : "no recognised error");
1482
1483         /* If this is a memory parity error dump which blocks are offending */
1484         mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1485                     EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1486         if (mem_perr) {
1487                 efx_oword_t reg;
1488                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1489                 netif_err(efx, hw, efx->net_dev,
1490                           "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1491                           EFX_OWORD_VAL(reg));
1492         }
1493
1494         /* Disable both devices */
1495         pci_clear_master(efx->pci_dev);
1496         if (efx_nic_is_dual_func(efx))
1497                 pci_clear_master(nic_data->pci_dev2);
1498         efx_farch_irq_disable_master(efx);
1499
1500         /* Count errors and reset or disable the NIC accordingly */
1501         if (efx->int_error_count == 0 ||
1502             time_after(jiffies, efx->int_error_expire)) {
1503                 efx->int_error_count = 0;
1504                 efx->int_error_expire =
1505                         jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1506         }
1507         if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1508                 netif_err(efx, hw, efx->net_dev,
1509                           "SYSTEM ERROR - reset scheduled\n");
1510                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1511         } else {
1512                 netif_err(efx, hw, efx->net_dev,
1513                           "SYSTEM ERROR - max number of errors seen."
1514                           "NIC will be disabled\n");
1515                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1516         }
1517
1518         return IRQ_HANDLED;
1519 }
1520
1521 /* Handle a legacy interrupt
1522  * Acknowledges the interrupt and schedule event queue processing.
1523  */
1524 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id)
1525 {
1526         struct efx_nic *efx = dev_id;
1527         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1528         efx_oword_t *int_ker = efx->irq_status.addr;
1529         irqreturn_t result = IRQ_NONE;
1530         struct efx_channel *channel;
1531         efx_dword_t reg;
1532         u32 queues;
1533         int syserr;
1534
1535         /* Read the ISR which also ACKs the interrupts */
1536         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1537         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1538
1539         /* Legacy interrupts are disabled too late by the EEH kernel
1540          * code. Disable them earlier.
1541          * If an EEH error occurred, the read will have returned all ones.
1542          */
1543         if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) &&
1544             !efx->eeh_disabled_legacy_irq) {
1545                 disable_irq_nosync(efx->legacy_irq);
1546                 efx->eeh_disabled_legacy_irq = true;
1547         }
1548
1549         /* Handle non-event-queue sources */
1550         if (queues & (1U << efx->irq_level) && soft_enabled) {
1551                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1552                 if (unlikely(syserr))
1553                         return efx_farch_fatal_interrupt(efx);
1554                 efx->last_irq_cpu = raw_smp_processor_id();
1555         }
1556
1557         if (queues != 0) {
1558                 efx->irq_zero_count = 0;
1559
1560                 /* Schedule processing of any interrupting queues */
1561                 if (likely(soft_enabled)) {
1562                         efx_for_each_channel(channel, efx) {
1563                                 if (queues & 1)
1564                                         efx_schedule_channel_irq(channel);
1565                                 queues >>= 1;
1566                         }
1567                 }
1568                 result = IRQ_HANDLED;
1569
1570         } else {
1571                 efx_qword_t *event;
1572
1573                 /* Legacy ISR read can return zero once (SF bug 15783) */
1574
1575                 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1576                  * because this might be a shared interrupt. */
1577                 if (efx->irq_zero_count++ == 0)
1578                         result = IRQ_HANDLED;
1579
1580                 /* Ensure we schedule or rearm all event queues */
1581                 if (likely(soft_enabled)) {
1582                         efx_for_each_channel(channel, efx) {
1583                                 event = efx_event(channel,
1584                                                   channel->eventq_read_ptr);
1585                                 if (efx_event_present(event))
1586                                         efx_schedule_channel_irq(channel);
1587                                 else
1588                                         efx_farch_ev_read_ack(channel);
1589                         }
1590                 }
1591         }
1592
1593         if (result == IRQ_HANDLED)
1594                 netif_vdbg(efx, intr, efx->net_dev,
1595                            "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1596                            irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1597
1598         return result;
1599 }
1600
1601 /* Handle an MSI interrupt
1602  *
1603  * Handle an MSI hardware interrupt.  This routine schedules event
1604  * queue processing.  No interrupt acknowledgement cycle is necessary.
1605  * Also, we never need to check that the interrupt is for us, since
1606  * MSI interrupts cannot be shared.
1607  */
1608 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id)
1609 {
1610         struct efx_msi_context *context = dev_id;
1611         struct efx_nic *efx = context->efx;
1612         efx_oword_t *int_ker = efx->irq_status.addr;
1613         int syserr;
1614
1615         netif_vdbg(efx, intr, efx->net_dev,
1616                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1617                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1618
1619         if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
1620                 return IRQ_HANDLED;
1621
1622         /* Handle non-event-queue sources */
1623         if (context->index == efx->irq_level) {
1624                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1625                 if (unlikely(syserr))
1626                         return efx_farch_fatal_interrupt(efx);
1627                 efx->last_irq_cpu = raw_smp_processor_id();
1628         }
1629
1630         /* Schedule processing of the channel */
1631         efx_schedule_channel_irq(efx->channel[context->index]);
1632
1633         return IRQ_HANDLED;
1634 }
1635
1636 /* Setup RSS indirection table.
1637  * This maps from the hash value of the packet to RXQ
1638  */
1639 void efx_farch_rx_push_indir_table(struct efx_nic *efx)
1640 {
1641         size_t i = 0;
1642         efx_dword_t dword;
1643
1644         BUG_ON(efx_nic_rev(efx) < EFX_REV_FALCON_B0);
1645
1646         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1647                      FR_BZ_RX_INDIRECTION_TBL_ROWS);
1648
1649         for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1650                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1651                                      efx->rx_indir_table[i]);
1652                 efx_writed(efx, &dword,
1653                            FR_BZ_RX_INDIRECTION_TBL +
1654                            FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1655         }
1656 }
1657
1658 /* Looks at available SRAM resources and works out how many queues we
1659  * can support, and where things like descriptor caches should live.
1660  *
1661  * SRAM is split up as follows:
1662  * 0                          buftbl entries for channels
1663  * efx->vf_buftbl_base        buftbl entries for SR-IOV
1664  * efx->rx_dc_base            RX descriptor caches
1665  * efx->tx_dc_base            TX descriptor caches
1666  */
1667 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1668 {
1669         unsigned vi_count, buftbl_min;
1670
1671         /* Account for the buffer table entries backing the datapath channels
1672          * and the descriptor caches for those channels.
1673          */
1674         buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1675                        efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1676                        efx->n_channels * EFX_MAX_EVQ_SIZE)
1677                       * sizeof(efx_qword_t) / EFX_BUF_SIZE);
1678         vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1679
1680 #ifdef CONFIG_SFC_SRIOV
1681         if (efx_sriov_wanted(efx)) {
1682                 unsigned vi_dc_entries, buftbl_free, entries_per_vf, vf_limit;
1683
1684                 efx->vf_buftbl_base = buftbl_min;
1685
1686                 vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES;
1687                 vi_count = max(vi_count, EFX_VI_BASE);
1688                 buftbl_free = (sram_lim_qw - buftbl_min -
1689                                vi_count * vi_dc_entries);
1690
1691                 entries_per_vf = ((vi_dc_entries + EFX_VF_BUFTBL_PER_VI) *
1692                                   efx_vf_size(efx));
1693                 vf_limit = min(buftbl_free / entries_per_vf,
1694                                (1024U - EFX_VI_BASE) >> efx->vi_scale);
1695
1696                 if (efx->vf_count > vf_limit) {
1697                         netif_err(efx, probe, efx->net_dev,
1698                                   "Reducing VF count from from %d to %d\n",
1699                                   efx->vf_count, vf_limit);
1700                         efx->vf_count = vf_limit;
1701                 }
1702                 vi_count += efx->vf_count * efx_vf_size(efx);
1703         }
1704 #endif
1705
1706         efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1707         efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1708 }
1709
1710 u32 efx_farch_fpga_ver(struct efx_nic *efx)
1711 {
1712         efx_oword_t altera_build;
1713         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1714         return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1715 }
1716
1717 void efx_farch_init_common(struct efx_nic *efx)
1718 {
1719         efx_oword_t temp;
1720
1721         /* Set positions of descriptor caches in SRAM. */
1722         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
1723         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1724         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
1725         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1726
1727         /* Set TX descriptor cache size. */
1728         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1729         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1730         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1731
1732         /* Set RX descriptor cache size.  Set low watermark to size-8, as
1733          * this allows most efficient prefetching.
1734          */
1735         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1736         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1737         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1738         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1739         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1740
1741         /* Program INT_KER address */
1742         EFX_POPULATE_OWORD_2(temp,
1743                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1744                              EFX_INT_MODE_USE_MSI(efx),
1745                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1746         efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1747
1748         if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1749                 /* Use an interrupt level unused by event queues */
1750                 efx->irq_level = 0x1f;
1751         else
1752                 /* Use a valid MSI-X vector */
1753                 efx->irq_level = 0;
1754
1755         /* Enable all the genuinely fatal interrupts.  (They are still
1756          * masked by the overall interrupt mask, controlled by
1757          * falcon_interrupts()).
1758          *
1759          * Note: All other fatal interrupts are enabled
1760          */
1761         EFX_POPULATE_OWORD_3(temp,
1762                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1763                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1764                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1765         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1766                 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1767         EFX_INVERT_OWORD(temp);
1768         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1769
1770         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1771          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1772          */
1773         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1774         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1775         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1776         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1777         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1778         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1779         /* Enable SW_EV to inherit in char driver - assume harmless here */
1780         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1781         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1782         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1783         /* Disable hardware watchdog which can misfire */
1784         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1785         /* Squash TX of packets of 16 bytes or less */
1786         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1787                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1788         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1789
1790         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1791                 EFX_POPULATE_OWORD_4(temp,
1792                                      /* Default values */
1793                                      FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1794                                      FRF_BZ_TX_PACE_SB_AF, 0xb,
1795                                      FRF_BZ_TX_PACE_FB_BASE, 0,
1796                                      /* Allow large pace values in the
1797                                       * fast bin. */
1798                                      FRF_BZ_TX_PACE_BIN_TH,
1799                                      FFE_BZ_TX_PACE_RESERVED);
1800                 efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1801         }
1802 }
1803
1804 /**************************************************************************
1805  *
1806  * Filter tables
1807  *
1808  **************************************************************************
1809  */
1810
1811 /* "Fudge factors" - difference between programmed value and actual depth.
1812  * Due to pipelined implementation we need to program H/W with a value that
1813  * is larger than the hop limit we want.
1814  */
1815 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD 3
1816 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL 1
1817
1818 /* Hard maximum search limit.  Hardware will time-out beyond 200-something.
1819  * We also need to avoid infinite loops in efx_farch_filter_search() when the
1820  * table is full.
1821  */
1822 #define EFX_FARCH_FILTER_CTL_SRCH_MAX 200
1823
1824 /* Don't try very hard to find space for performance hints, as this is
1825  * counter-productive. */
1826 #define EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX 5
1827
1828 enum efx_farch_filter_type {
1829         EFX_FARCH_FILTER_TCP_FULL = 0,
1830         EFX_FARCH_FILTER_TCP_WILD,
1831         EFX_FARCH_FILTER_UDP_FULL,
1832         EFX_FARCH_FILTER_UDP_WILD,
1833         EFX_FARCH_FILTER_MAC_FULL = 4,
1834         EFX_FARCH_FILTER_MAC_WILD,
1835         EFX_FARCH_FILTER_UC_DEF = 8,
1836         EFX_FARCH_FILTER_MC_DEF,
1837         EFX_FARCH_FILTER_TYPE_COUNT,            /* number of specific types */
1838 };
1839
1840 enum efx_farch_filter_table_id {
1841         EFX_FARCH_FILTER_TABLE_RX_IP = 0,
1842         EFX_FARCH_FILTER_TABLE_RX_MAC,
1843         EFX_FARCH_FILTER_TABLE_RX_DEF,
1844         EFX_FARCH_FILTER_TABLE_TX_MAC,
1845         EFX_FARCH_FILTER_TABLE_COUNT,
1846 };
1847
1848 enum efx_farch_filter_index {
1849         EFX_FARCH_FILTER_INDEX_UC_DEF,
1850         EFX_FARCH_FILTER_INDEX_MC_DEF,
1851         EFX_FARCH_FILTER_SIZE_RX_DEF,
1852 };
1853
1854 struct efx_farch_filter_spec {
1855         u8      type:4;
1856         u8      priority:4;
1857         u8      flags;
1858         u16     dmaq_id;
1859         u32     data[3];
1860 };
1861
1862 struct efx_farch_filter_table {
1863         enum efx_farch_filter_table_id id;
1864         u32             offset;         /* address of table relative to BAR */
1865         unsigned        size;           /* number of entries */
1866         unsigned        step;           /* step between entries */
1867         unsigned        used;           /* number currently used */
1868         unsigned long   *used_bitmap;
1869         struct efx_farch_filter_spec *spec;
1870         unsigned        search_limit[EFX_FARCH_FILTER_TYPE_COUNT];
1871 };
1872
1873 struct efx_farch_filter_state {
1874         struct efx_farch_filter_table table[EFX_FARCH_FILTER_TABLE_COUNT];
1875 };
1876
1877 static void
1878 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
1879                                    struct efx_farch_filter_table *table,
1880                                    unsigned int filter_idx);
1881
1882 /* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
1883  * key derived from the n-tuple.  The initial LFSR state is 0xffff. */
1884 static u16 efx_farch_filter_hash(u32 key)
1885 {
1886         u16 tmp;
1887
1888         /* First 16 rounds */
1889         tmp = 0x1fff ^ key >> 16;
1890         tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1891         tmp = tmp ^ tmp >> 9;
1892         /* Last 16 rounds */
1893         tmp = tmp ^ tmp << 13 ^ key;
1894         tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1895         return tmp ^ tmp >> 9;
1896 }
1897
1898 /* To allow for hash collisions, filter search continues at these
1899  * increments from the first possible entry selected by the hash. */
1900 static u16 efx_farch_filter_increment(u32 key)
1901 {
1902         return key * 2 - 1;
1903 }
1904
1905 static enum efx_farch_filter_table_id
1906 efx_farch_filter_spec_table_id(const struct efx_farch_filter_spec *spec)
1907 {
1908         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1909                      (EFX_FARCH_FILTER_TCP_FULL >> 2));
1910         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1911                      (EFX_FARCH_FILTER_TCP_WILD >> 2));
1912         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1913                      (EFX_FARCH_FILTER_UDP_FULL >> 2));
1914         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1915                      (EFX_FARCH_FILTER_UDP_WILD >> 2));
1916         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1917                      (EFX_FARCH_FILTER_MAC_FULL >> 2));
1918         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1919                      (EFX_FARCH_FILTER_MAC_WILD >> 2));
1920         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_TX_MAC !=
1921                      EFX_FARCH_FILTER_TABLE_RX_MAC + 2);
1922         return (spec->type >> 2) + ((spec->flags & EFX_FILTER_FLAG_TX) ? 2 : 0);
1923 }
1924
1925 static void efx_farch_filter_push_rx_config(struct efx_nic *efx)
1926 {
1927         struct efx_farch_filter_state *state = efx->filter_state;
1928         struct efx_farch_filter_table *table;
1929         efx_oword_t filter_ctl;
1930
1931         efx_reado(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1932
1933         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
1934         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_FULL_SRCH_LIMIT,
1935                             table->search_limit[EFX_FARCH_FILTER_TCP_FULL] +
1936                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1937         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_WILD_SRCH_LIMIT,
1938                             table->search_limit[EFX_FARCH_FILTER_TCP_WILD] +
1939                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1940         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_FULL_SRCH_LIMIT,
1941                             table->search_limit[EFX_FARCH_FILTER_UDP_FULL] +
1942                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1943         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_WILD_SRCH_LIMIT,
1944                             table->search_limit[EFX_FARCH_FILTER_UDP_WILD] +
1945                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1946
1947         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
1948         if (table->size) {
1949                 EFX_SET_OWORD_FIELD(
1950                         filter_ctl, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
1951                         table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
1952                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1953                 EFX_SET_OWORD_FIELD(
1954                         filter_ctl, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
1955                         table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
1956                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1957         }
1958
1959         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
1960         if (table->size) {
1961                 EFX_SET_OWORD_FIELD(
1962                         filter_ctl, FRF_CZ_UNICAST_NOMATCH_Q_ID,
1963                         table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].dmaq_id);
1964                 EFX_SET_OWORD_FIELD(
1965                         filter_ctl, FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED,
1966                         !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1967                            EFX_FILTER_FLAG_RX_RSS));
1968                 EFX_SET_OWORD_FIELD(
1969                         filter_ctl, FRF_CZ_MULTICAST_NOMATCH_Q_ID,
1970                         table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].dmaq_id);
1971                 EFX_SET_OWORD_FIELD(
1972                         filter_ctl, FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED,
1973                         !!(table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1974                            EFX_FILTER_FLAG_RX_RSS));
1975
1976                 /* There is a single bit to enable RX scatter for all
1977                  * unmatched packets.  Only set it if scatter is
1978                  * enabled in both filter specs.
1979                  */
1980                 EFX_SET_OWORD_FIELD(
1981                         filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1982                         !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1983                            table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1984                            EFX_FILTER_FLAG_RX_SCATTER));
1985         } else if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1986                 /* We don't expose 'default' filters because unmatched
1987                  * packets always go to the queue number found in the
1988                  * RSS table.  But we still need to set the RX scatter
1989                  * bit here.
1990                  */
1991                 EFX_SET_OWORD_FIELD(
1992                         filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1993                         efx->rx_scatter);
1994         }
1995
1996         efx_writeo(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1997 }
1998
1999 static void efx_farch_filter_push_tx_limits(struct efx_nic *efx)
2000 {
2001         struct efx_farch_filter_state *state = efx->filter_state;
2002         struct efx_farch_filter_table *table;
2003         efx_oword_t tx_cfg;
2004
2005         efx_reado(efx, &tx_cfg, FR_AZ_TX_CFG);
2006
2007         table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2008         if (table->size) {
2009                 EFX_SET_OWORD_FIELD(
2010                         tx_cfg, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
2011                         table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
2012                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
2013                 EFX_SET_OWORD_FIELD(
2014                         tx_cfg, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
2015                         table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
2016                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
2017         }
2018
2019         efx_writeo(efx, &tx_cfg, FR_AZ_TX_CFG);
2020 }
2021
2022 static int
2023 efx_farch_filter_from_gen_spec(struct efx_farch_filter_spec *spec,
2024                                const struct efx_filter_spec *gen_spec)
2025 {
2026         bool is_full = false;
2027
2028         if ((gen_spec->flags & EFX_FILTER_FLAG_RX_RSS) &&
2029             gen_spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT)
2030                 return -EINVAL;
2031
2032         spec->priority = gen_spec->priority;
2033         spec->flags = gen_spec->flags;
2034         spec->dmaq_id = gen_spec->dmaq_id;
2035
2036         switch (gen_spec->match_flags) {
2037         case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2038               EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
2039               EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT):
2040                 is_full = true;
2041                 /* fall through */
2042         case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2043               EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT): {
2044                 __be32 rhost, host1, host2;
2045                 __be16 rport, port1, port2;
2046
2047                 EFX_BUG_ON_PARANOID(!(gen_spec->flags & EFX_FILTER_FLAG_RX));
2048
2049                 if (gen_spec->ether_type != htons(ETH_P_IP))
2050                         return -EPROTONOSUPPORT;
2051                 if (gen_spec->loc_port == 0 ||
2052                     (is_full && gen_spec->rem_port == 0))
2053                         return -EADDRNOTAVAIL;
2054                 switch (gen_spec->ip_proto) {
2055                 case IPPROTO_TCP:
2056                         spec->type = (is_full ? EFX_FARCH_FILTER_TCP_FULL :
2057                                       EFX_FARCH_FILTER_TCP_WILD);
2058                         break;
2059                 case IPPROTO_UDP:
2060                         spec->type = (is_full ? EFX_FARCH_FILTER_UDP_FULL :
2061                                       EFX_FARCH_FILTER_UDP_WILD);
2062                         break;
2063                 default:
2064                         return -EPROTONOSUPPORT;
2065                 }
2066
2067                 /* Filter is constructed in terms of source and destination,
2068                  * with the odd wrinkle that the ports are swapped in a UDP
2069                  * wildcard filter.  We need to convert from local and remote
2070                  * (= zero for wildcard) addresses.
2071                  */
2072                 rhost = is_full ? gen_spec->rem_host[0] : 0;
2073                 rport = is_full ? gen_spec->rem_port : 0;
2074                 host1 = rhost;
2075                 host2 = gen_spec->loc_host[0];
2076                 if (!is_full && gen_spec->ip_proto == IPPROTO_UDP) {
2077                         port1 = gen_spec->loc_port;
2078                         port2 = rport;
2079                 } else {
2080                         port1 = rport;
2081                         port2 = gen_spec->loc_port;
2082                 }
2083                 spec->data[0] = ntohl(host1) << 16 | ntohs(port1);
2084                 spec->data[1] = ntohs(port2) << 16 | ntohl(host1) >> 16;
2085                 spec->data[2] = ntohl(host2);
2086
2087                 break;
2088         }
2089
2090         case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
2091                 is_full = true;
2092                 /* fall through */
2093         case EFX_FILTER_MATCH_LOC_MAC:
2094                 spec->type = (is_full ? EFX_FARCH_FILTER_MAC_FULL :
2095                               EFX_FARCH_FILTER_MAC_WILD);
2096                 spec->data[0] = is_full ? ntohs(gen_spec->outer_vid) : 0;
2097                 spec->data[1] = (gen_spec->loc_mac[2] << 24 |
2098                                  gen_spec->loc_mac[3] << 16 |
2099                                  gen_spec->loc_mac[4] << 8 |
2100                                  gen_spec->loc_mac[5]);
2101                 spec->data[2] = (gen_spec->loc_mac[0] << 8 |
2102                                  gen_spec->loc_mac[1]);
2103                 break;
2104
2105         case EFX_FILTER_MATCH_LOC_MAC_IG:
2106                 spec->type = (is_multicast_ether_addr(gen_spec->loc_mac) ?
2107                               EFX_FARCH_FILTER_MC_DEF :
2108                               EFX_FARCH_FILTER_UC_DEF);
2109                 memset(spec->data, 0, sizeof(spec->data)); /* ensure equality */
2110                 break;
2111
2112         default:
2113                 return -EPROTONOSUPPORT;
2114         }
2115
2116         return 0;
2117 }
2118
2119 static void
2120 efx_farch_filter_to_gen_spec(struct efx_filter_spec *gen_spec,
2121                              const struct efx_farch_filter_spec *spec)
2122 {
2123         bool is_full = false;
2124
2125         /* *gen_spec should be completely initialised, to be consistent
2126          * with efx_filter_init_{rx,tx}() and in case we want to copy
2127          * it back to userland.
2128          */
2129         memset(gen_spec, 0, sizeof(*gen_spec));
2130
2131         gen_spec->priority = spec->priority;
2132         gen_spec->flags = spec->flags;
2133         gen_spec->dmaq_id = spec->dmaq_id;
2134
2135         switch (spec->type) {
2136         case EFX_FARCH_FILTER_TCP_FULL:
2137         case EFX_FARCH_FILTER_UDP_FULL:
2138                 is_full = true;
2139                 /* fall through */
2140         case EFX_FARCH_FILTER_TCP_WILD:
2141         case EFX_FARCH_FILTER_UDP_WILD: {
2142                 __be32 host1, host2;
2143                 __be16 port1, port2;
2144
2145                 gen_spec->match_flags =
2146                         EFX_FILTER_MATCH_ETHER_TYPE |
2147                         EFX_FILTER_MATCH_IP_PROTO |
2148                         EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
2149                 if (is_full)
2150                         gen_spec->match_flags |= (EFX_FILTER_MATCH_REM_HOST |
2151                                                   EFX_FILTER_MATCH_REM_PORT);
2152                 gen_spec->ether_type = htons(ETH_P_IP);
2153                 gen_spec->ip_proto =
2154                         (spec->type == EFX_FARCH_FILTER_TCP_FULL ||
2155                          spec->type == EFX_FARCH_FILTER_TCP_WILD) ?
2156                         IPPROTO_TCP : IPPROTO_UDP;
2157
2158                 host1 = htonl(spec->data[0] >> 16 | spec->data[1] << 16);
2159                 port1 = htons(spec->data[0]);
2160                 host2 = htonl(spec->data[2]);
2161                 port2 = htons(spec->data[1] >> 16);
2162                 if (spec->flags & EFX_FILTER_FLAG_TX) {
2163                         gen_spec->loc_host[0] = host1;
2164                         gen_spec->rem_host[0] = host2;
2165                 } else {
2166                         gen_spec->loc_host[0] = host2;
2167                         gen_spec->rem_host[0] = host1;
2168                 }
2169                 if (!!(gen_spec->flags & EFX_FILTER_FLAG_TX) ^
2170                     (!is_full && gen_spec->ip_proto == IPPROTO_UDP)) {
2171                         gen_spec->loc_port = port1;
2172                         gen_spec->rem_port = port2;
2173                 } else {
2174                         gen_spec->loc_port = port2;
2175                         gen_spec->rem_port = port1;
2176                 }
2177
2178                 break;
2179         }
2180
2181         case EFX_FARCH_FILTER_MAC_FULL:
2182                 is_full = true;
2183                 /* fall through */
2184         case EFX_FARCH_FILTER_MAC_WILD:
2185                 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC;
2186                 if (is_full)
2187                         gen_spec->match_flags |= EFX_FILTER_MATCH_OUTER_VID;
2188                 gen_spec->loc_mac[0] = spec->data[2] >> 8;
2189                 gen_spec->loc_mac[1] = spec->data[2];
2190                 gen_spec->loc_mac[2] = spec->data[1] >> 24;
2191                 gen_spec->loc_mac[3] = spec->data[1] >> 16;
2192                 gen_spec->loc_mac[4] = spec->data[1] >> 8;
2193                 gen_spec->loc_mac[5] = spec->data[1];
2194                 gen_spec->outer_vid = htons(spec->data[0]);
2195                 break;
2196
2197         case EFX_FARCH_FILTER_UC_DEF:
2198         case EFX_FARCH_FILTER_MC_DEF:
2199                 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC_IG;
2200                 gen_spec->loc_mac[0] = spec->type == EFX_FARCH_FILTER_MC_DEF;
2201                 break;
2202
2203         default:
2204                 WARN_ON(1);
2205                 break;
2206         }
2207 }
2208
2209 static void
2210 efx_farch_filter_init_rx_auto(struct efx_nic *efx,
2211                               struct efx_farch_filter_spec *spec)
2212 {
2213         /* If there's only one channel then disable RSS for non VF
2214          * traffic, thereby allowing VFs to use RSS when the PF can't.
2215          */
2216         spec->priority = EFX_FILTER_PRI_AUTO;
2217         spec->flags = (EFX_FILTER_FLAG_RX |
2218                        (efx->n_rx_channels > 1 ? EFX_FILTER_FLAG_RX_RSS : 0) |
2219                        (efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0));
2220         spec->dmaq_id = 0;
2221 }
2222
2223 /* Build a filter entry and return its n-tuple key. */
2224 static u32 efx_farch_filter_build(efx_oword_t *filter,
2225                                   struct efx_farch_filter_spec *spec)
2226 {
2227         u32 data3;
2228
2229         switch (efx_farch_filter_spec_table_id(spec)) {
2230         case EFX_FARCH_FILTER_TABLE_RX_IP: {
2231                 bool is_udp = (spec->type == EFX_FARCH_FILTER_UDP_FULL ||
2232                                spec->type == EFX_FARCH_FILTER_UDP_WILD);
2233                 EFX_POPULATE_OWORD_7(
2234                         *filter,
2235                         FRF_BZ_RSS_EN,
2236                         !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2237                         FRF_BZ_SCATTER_EN,
2238                         !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2239                         FRF_BZ_TCP_UDP, is_udp,
2240                         FRF_BZ_RXQ_ID, spec->dmaq_id,
2241                         EFX_DWORD_2, spec->data[2],
2242                         EFX_DWORD_1, spec->data[1],
2243                         EFX_DWORD_0, spec->data[0]);
2244                 data3 = is_udp;
2245                 break;
2246         }
2247
2248         case EFX_FARCH_FILTER_TABLE_RX_MAC: {
2249                 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2250                 EFX_POPULATE_OWORD_7(
2251                         *filter,
2252                         FRF_CZ_RMFT_RSS_EN,
2253                         !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2254                         FRF_CZ_RMFT_SCATTER_EN,
2255                         !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2256                         FRF_CZ_RMFT_RXQ_ID, spec->dmaq_id,
2257                         FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
2258                         FRF_CZ_RMFT_DEST_MAC_HI, spec->data[2],
2259                         FRF_CZ_RMFT_DEST_MAC_LO, spec->data[1],
2260                         FRF_CZ_RMFT_VLAN_ID, spec->data[0]);
2261                 data3 = is_wild;
2262                 break;
2263         }
2264
2265         case EFX_FARCH_FILTER_TABLE_TX_MAC: {
2266                 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2267                 EFX_POPULATE_OWORD_5(*filter,
2268                                      FRF_CZ_TMFT_TXQ_ID, spec->dmaq_id,
2269                                      FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
2270                                      FRF_CZ_TMFT_SRC_MAC_HI, spec->data[2],
2271                                      FRF_CZ_TMFT_SRC_MAC_LO, spec->data[1],
2272                                      FRF_CZ_TMFT_VLAN_ID, spec->data[0]);
2273                 data3 = is_wild | spec->dmaq_id << 1;
2274                 break;
2275         }
2276
2277         default:
2278                 BUG();
2279         }
2280
2281         return spec->data[0] ^ spec->data[1] ^ spec->data[2] ^ data3;
2282 }
2283
2284 static bool efx_farch_filter_equal(const struct efx_farch_filter_spec *left,
2285                                    const struct efx_farch_filter_spec *right)
2286 {
2287         if (left->type != right->type ||
2288             memcmp(left->data, right->data, sizeof(left->data)))
2289                 return false;
2290
2291         if (left->flags & EFX_FILTER_FLAG_TX &&
2292             left->dmaq_id != right->dmaq_id)
2293                 return false;
2294
2295         return true;
2296 }
2297
2298 /*
2299  * Construct/deconstruct external filter IDs.  At least the RX filter
2300  * IDs must be ordered by matching priority, for RX NFC semantics.
2301  *
2302  * Deconstruction needs to be robust against invalid IDs so that
2303  * efx_filter_remove_id_safe() and efx_filter_get_filter_safe() can
2304  * accept user-provided IDs.
2305  */
2306
2307 #define EFX_FARCH_FILTER_MATCH_PRI_COUNT        5
2308
2309 static const u8 efx_farch_filter_type_match_pri[EFX_FARCH_FILTER_TYPE_COUNT] = {
2310         [EFX_FARCH_FILTER_TCP_FULL]     = 0,
2311         [EFX_FARCH_FILTER_UDP_FULL]     = 0,
2312         [EFX_FARCH_FILTER_TCP_WILD]     = 1,
2313         [EFX_FARCH_FILTER_UDP_WILD]     = 1,
2314         [EFX_FARCH_FILTER_MAC_FULL]     = 2,
2315         [EFX_FARCH_FILTER_MAC_WILD]     = 3,
2316         [EFX_FARCH_FILTER_UC_DEF]       = 4,
2317         [EFX_FARCH_FILTER_MC_DEF]       = 4,
2318 };
2319
2320 static const enum efx_farch_filter_table_id efx_farch_filter_range_table[] = {
2321         EFX_FARCH_FILTER_TABLE_RX_IP,   /* RX match pri 0 */
2322         EFX_FARCH_FILTER_TABLE_RX_IP,
2323         EFX_FARCH_FILTER_TABLE_RX_MAC,
2324         EFX_FARCH_FILTER_TABLE_RX_MAC,
2325         EFX_FARCH_FILTER_TABLE_RX_DEF,  /* RX match pri 4 */
2326         EFX_FARCH_FILTER_TABLE_TX_MAC,  /* TX match pri 0 */
2327         EFX_FARCH_FILTER_TABLE_TX_MAC,  /* TX match pri 1 */
2328 };
2329
2330 #define EFX_FARCH_FILTER_INDEX_WIDTH 13
2331 #define EFX_FARCH_FILTER_INDEX_MASK ((1 << EFX_FARCH_FILTER_INDEX_WIDTH) - 1)
2332
2333 static inline u32
2334 efx_farch_filter_make_id(const struct efx_farch_filter_spec *spec,
2335                          unsigned int index)
2336 {
2337         unsigned int range;
2338
2339         range = efx_farch_filter_type_match_pri[spec->type];
2340         if (!(spec->flags & EFX_FILTER_FLAG_RX))
2341                 range += EFX_FARCH_FILTER_MATCH_PRI_COUNT;
2342
2343         return range << EFX_FARCH_FILTER_INDEX_WIDTH | index;
2344 }
2345
2346 static inline enum efx_farch_filter_table_id
2347 efx_farch_filter_id_table_id(u32 id)
2348 {
2349         unsigned int range = id >> EFX_FARCH_FILTER_INDEX_WIDTH;
2350
2351         if (range < ARRAY_SIZE(efx_farch_filter_range_table))
2352                 return efx_farch_filter_range_table[range];
2353         else
2354                 return EFX_FARCH_FILTER_TABLE_COUNT; /* invalid */
2355 }
2356
2357 static inline unsigned int efx_farch_filter_id_index(u32 id)
2358 {
2359         return id & EFX_FARCH_FILTER_INDEX_MASK;
2360 }
2361
2362 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx)
2363 {
2364         struct efx_farch_filter_state *state = efx->filter_state;
2365         unsigned int range = EFX_FARCH_FILTER_MATCH_PRI_COUNT - 1;
2366         enum efx_farch_filter_table_id table_id;
2367
2368         do {
2369                 table_id = efx_farch_filter_range_table[range];
2370                 if (state->table[table_id].size != 0)
2371                         return range << EFX_FARCH_FILTER_INDEX_WIDTH |
2372                                 state->table[table_id].size;
2373         } while (range--);
2374
2375         return 0;
2376 }
2377
2378 s32 efx_farch_filter_insert(struct efx_nic *efx,
2379                             struct efx_filter_spec *gen_spec,
2380                             bool replace_equal)
2381 {
2382         struct efx_farch_filter_state *state = efx->filter_state;
2383         struct efx_farch_filter_table *table;
2384         struct efx_farch_filter_spec spec;
2385         efx_oword_t filter;
2386         int rep_index, ins_index;
2387         unsigned int depth = 0;
2388         int rc;
2389
2390         rc = efx_farch_filter_from_gen_spec(&spec, gen_spec);
2391         if (rc)
2392                 return rc;
2393
2394         table = &state->table[efx_farch_filter_spec_table_id(&spec)];
2395         if (table->size == 0)
2396                 return -EINVAL;
2397
2398         netif_vdbg(efx, hw, efx->net_dev,
2399                    "%s: type %d search_limit=%d", __func__, spec.type,
2400                    table->search_limit[spec.type]);
2401
2402         if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2403                 /* One filter spec per type */
2404                 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_UC_DEF != 0);
2405                 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_MC_DEF !=
2406                              EFX_FARCH_FILTER_MC_DEF - EFX_FARCH_FILTER_UC_DEF);
2407                 rep_index = spec.type - EFX_FARCH_FILTER_UC_DEF;
2408                 ins_index = rep_index;
2409
2410                 spin_lock_bh(&efx->filter_lock);
2411         } else {
2412                 /* Search concurrently for
2413                  * (1) a filter to be replaced (rep_index): any filter
2414                  *     with the same match values, up to the current
2415                  *     search depth for this type, and
2416                  * (2) the insertion point (ins_index): (1) or any
2417                  *     free slot before it or up to the maximum search
2418                  *     depth for this priority
2419                  * We fail if we cannot find (2).
2420                  *
2421                  * We can stop once either
2422                  * (a) we find (1), in which case we have definitely
2423                  *     found (2) as well; or
2424                  * (b) we have searched exhaustively for (1), and have
2425                  *     either found (2) or searched exhaustively for it
2426                  */
2427                 u32 key = efx_farch_filter_build(&filter, &spec);
2428                 unsigned int hash = efx_farch_filter_hash(key);
2429                 unsigned int incr = efx_farch_filter_increment(key);
2430                 unsigned int max_rep_depth = table->search_limit[spec.type];
2431                 unsigned int max_ins_depth =
2432                         spec.priority <= EFX_FILTER_PRI_HINT ?
2433                         EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX :
2434                         EFX_FARCH_FILTER_CTL_SRCH_MAX;
2435                 unsigned int i = hash & (table->size - 1);
2436
2437                 ins_index = -1;
2438                 depth = 1;
2439
2440                 spin_lock_bh(&efx->filter_lock);
2441
2442                 for (;;) {
2443                         if (!test_bit(i, table->used_bitmap)) {
2444                                 if (ins_index < 0)
2445                                         ins_index = i;
2446                         } else if (efx_farch_filter_equal(&spec,
2447                                                           &table->spec[i])) {
2448                                 /* Case (a) */
2449                                 if (ins_index < 0)
2450                                         ins_index = i;
2451                                 rep_index = i;
2452                                 break;
2453                         }
2454
2455                         if (depth >= max_rep_depth &&
2456                             (ins_index >= 0 || depth >= max_ins_depth)) {
2457                                 /* Case (b) */
2458                                 if (ins_index < 0) {
2459                                         rc = -EBUSY;
2460                                         goto out;
2461                                 }
2462                                 rep_index = -1;
2463                                 break;
2464                         }
2465
2466                         i = (i + incr) & (table->size - 1);
2467                         ++depth;
2468                 }
2469         }
2470
2471         /* If we found a filter to be replaced, check whether we
2472          * should do so
2473          */
2474         if (rep_index >= 0) {
2475                 struct efx_farch_filter_spec *saved_spec =
2476                         &table->spec[rep_index];
2477
2478                 if (spec.priority == saved_spec->priority && !replace_equal) {
2479                         rc = -EEXIST;
2480                         goto out;
2481                 }
2482                 if (spec.priority < saved_spec->priority) {
2483                         rc = -EPERM;
2484                         goto out;
2485                 }
2486                 if (saved_spec->priority == EFX_FILTER_PRI_AUTO ||
2487                     saved_spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO)
2488                         spec.flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2489         }
2490
2491         /* Insert the filter */
2492         if (ins_index != rep_index) {
2493                 __set_bit(ins_index, table->used_bitmap);
2494                 ++table->used;
2495         }
2496         table->spec[ins_index] = spec;
2497
2498         if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2499                 efx_farch_filter_push_rx_config(efx);
2500         } else {
2501                 if (table->search_limit[spec.type] < depth) {
2502                         table->search_limit[spec.type] = depth;
2503                         if (spec.flags & EFX_FILTER_FLAG_TX)
2504                                 efx_farch_filter_push_tx_limits(efx);
2505                         else
2506                                 efx_farch_filter_push_rx_config(efx);
2507                 }
2508
2509                 efx_writeo(efx, &filter,
2510                            table->offset + table->step * ins_index);
2511
2512                 /* If we were able to replace a filter by inserting
2513                  * at a lower depth, clear the replaced filter
2514                  */
2515                 if (ins_index != rep_index && rep_index >= 0)
2516                         efx_farch_filter_table_clear_entry(efx, table,
2517                                                            rep_index);
2518         }
2519
2520         netif_vdbg(efx, hw, efx->net_dev,
2521                    "%s: filter type %d index %d rxq %u set",
2522                    __func__, spec.type, ins_index, spec.dmaq_id);
2523         rc = efx_farch_filter_make_id(&spec, ins_index);
2524
2525 out:
2526         spin_unlock_bh(&efx->filter_lock);
2527         return rc;
2528 }
2529
2530 static void
2531 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
2532                                    struct efx_farch_filter_table *table,
2533                                    unsigned int filter_idx)
2534 {
2535         static efx_oword_t filter;
2536
2537         EFX_WARN_ON_PARANOID(!test_bit(filter_idx, table->used_bitmap));
2538         BUG_ON(table->offset == 0); /* can't clear MAC default filters */
2539
2540         __clear_bit(filter_idx, table->used_bitmap);
2541         --table->used;
2542         memset(&table->spec[filter_idx], 0, sizeof(table->spec[0]));
2543
2544         efx_writeo(efx, &filter, table->offset + table->step * filter_idx);
2545
2546         /* If this filter required a greater search depth than
2547          * any other, the search limit for its type can now be
2548          * decreased.  However, it is hard to determine that
2549          * unless the table has become completely empty - in
2550          * which case, all its search limits can be set to 0.
2551          */
2552         if (unlikely(table->used == 0)) {
2553                 memset(table->search_limit, 0, sizeof(table->search_limit));
2554                 if (table->id == EFX_FARCH_FILTER_TABLE_TX_MAC)
2555                         efx_farch_filter_push_tx_limits(efx);
2556                 else
2557                         efx_farch_filter_push_rx_config(efx);
2558         }
2559 }
2560
2561 static int efx_farch_filter_remove(struct efx_nic *efx,
2562                                    struct efx_farch_filter_table *table,
2563                                    unsigned int filter_idx,
2564                                    enum efx_filter_priority priority)
2565 {
2566         struct efx_farch_filter_spec *spec = &table->spec[filter_idx];
2567
2568         if (!test_bit(filter_idx, table->used_bitmap) ||
2569             spec->priority != priority)
2570                 return -ENOENT;
2571
2572         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2573                 efx_farch_filter_init_rx_auto(efx, spec);
2574                 efx_farch_filter_push_rx_config(efx);
2575         } else {
2576                 efx_farch_filter_table_clear_entry(efx, table, filter_idx);
2577         }
2578
2579         return 0;
2580 }
2581
2582 int efx_farch_filter_remove_safe(struct efx_nic *efx,
2583                                  enum efx_filter_priority priority,
2584                                  u32 filter_id)
2585 {
2586         struct efx_farch_filter_state *state = efx->filter_state;
2587         enum efx_farch_filter_table_id table_id;
2588         struct efx_farch_filter_table *table;
2589         unsigned int filter_idx;
2590         struct efx_farch_filter_spec *spec;
2591         int rc;
2592
2593         table_id = efx_farch_filter_id_table_id(filter_id);
2594         if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2595                 return -ENOENT;
2596         table = &state->table[table_id];
2597
2598         filter_idx = efx_farch_filter_id_index(filter_id);
2599         if (filter_idx >= table->size)
2600                 return -ENOENT;
2601         spec = &table->spec[filter_idx];
2602
2603         spin_lock_bh(&efx->filter_lock);
2604         rc = efx_farch_filter_remove(efx, table, filter_idx, priority);
2605         spin_unlock_bh(&efx->filter_lock);
2606
2607         return rc;
2608 }
2609
2610 int efx_farch_filter_get_safe(struct efx_nic *efx,
2611                               enum efx_filter_priority priority,
2612                               u32 filter_id, struct efx_filter_spec *spec_buf)
2613 {
2614         struct efx_farch_filter_state *state = efx->filter_state;
2615         enum efx_farch_filter_table_id table_id;
2616         struct efx_farch_filter_table *table;
2617         struct efx_farch_filter_spec *spec;
2618         unsigned int filter_idx;
2619         int rc;
2620
2621         table_id = efx_farch_filter_id_table_id(filter_id);
2622         if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2623                 return -ENOENT;
2624         table = &state->table[table_id];
2625
2626         filter_idx = efx_farch_filter_id_index(filter_id);
2627         if (filter_idx >= table->size)
2628                 return -ENOENT;
2629         spec = &table->spec[filter_idx];
2630
2631         spin_lock_bh(&efx->filter_lock);
2632
2633         if (test_bit(filter_idx, table->used_bitmap) &&
2634             spec->priority == priority) {
2635                 efx_farch_filter_to_gen_spec(spec_buf, spec);
2636                 rc = 0;
2637         } else {
2638                 rc = -ENOENT;
2639         }
2640
2641         spin_unlock_bh(&efx->filter_lock);
2642
2643         return rc;
2644 }
2645
2646 static void
2647 efx_farch_filter_table_clear(struct efx_nic *efx,
2648                              enum efx_farch_filter_table_id table_id,
2649                              enum efx_filter_priority priority)
2650 {
2651         struct efx_farch_filter_state *state = efx->filter_state;
2652         struct efx_farch_filter_table *table = &state->table[table_id];
2653         unsigned int filter_idx;
2654
2655         spin_lock_bh(&efx->filter_lock);
2656         for (filter_idx = 0; filter_idx < table->size; ++filter_idx) {
2657                 if (table->spec[filter_idx].priority != EFX_FILTER_PRI_AUTO)
2658                         efx_farch_filter_remove(efx, table,
2659                                                 filter_idx, priority);
2660         }
2661         spin_unlock_bh(&efx->filter_lock);
2662 }
2663
2664 int efx_farch_filter_clear_rx(struct efx_nic *efx,
2665                                enum efx_filter_priority priority)
2666 {
2667         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_IP,
2668                                      priority);
2669         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_MAC,
2670                                      priority);
2671         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_DEF,
2672                                      priority);
2673         return 0;
2674 }
2675
2676 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
2677                                    enum efx_filter_priority priority)
2678 {
2679         struct efx_farch_filter_state *state = efx->filter_state;
2680         enum efx_farch_filter_table_id table_id;
2681         struct efx_farch_filter_table *table;
2682         unsigned int filter_idx;
2683         u32 count = 0;
2684
2685         spin_lock_bh(&efx->filter_lock);
2686
2687         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2688              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2689              table_id++) {
2690                 table = &state->table[table_id];
2691                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2692                         if (test_bit(filter_idx, table->used_bitmap) &&
2693                             table->spec[filter_idx].priority == priority)
2694                                 ++count;
2695                 }
2696         }
2697
2698         spin_unlock_bh(&efx->filter_lock);
2699
2700         return count;
2701 }
2702
2703 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
2704                                 enum efx_filter_priority priority,
2705                                 u32 *buf, u32 size)
2706 {
2707         struct efx_farch_filter_state *state = efx->filter_state;
2708         enum efx_farch_filter_table_id table_id;
2709         struct efx_farch_filter_table *table;
2710         unsigned int filter_idx;
2711         s32 count = 0;
2712
2713         spin_lock_bh(&efx->filter_lock);
2714
2715         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2716              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2717              table_id++) {
2718                 table = &state->table[table_id];
2719                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2720                         if (test_bit(filter_idx, table->used_bitmap) &&
2721                             table->spec[filter_idx].priority == priority) {
2722                                 if (count == size) {
2723                                         count = -EMSGSIZE;
2724                                         goto out;
2725                                 }
2726                                 buf[count++] = efx_farch_filter_make_id(
2727                                         &table->spec[filter_idx], filter_idx);
2728                         }
2729                 }
2730         }
2731 out:
2732         spin_unlock_bh(&efx->filter_lock);
2733
2734         return count;
2735 }
2736
2737 /* Restore filter stater after reset */
2738 void efx_farch_filter_table_restore(struct efx_nic *efx)
2739 {
2740         struct efx_farch_filter_state *state = efx->filter_state;
2741         enum efx_farch_filter_table_id table_id;
2742         struct efx_farch_filter_table *table;
2743         efx_oword_t filter;
2744         unsigned int filter_idx;
2745
2746         spin_lock_bh(&efx->filter_lock);
2747
2748         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2749                 table = &state->table[table_id];
2750
2751                 /* Check whether this is a regular register table */
2752                 if (table->step == 0)
2753                         continue;
2754
2755                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2756                         if (!test_bit(filter_idx, table->used_bitmap))
2757                                 continue;
2758                         efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2759                         efx_writeo(efx, &filter,
2760                                    table->offset + table->step * filter_idx);
2761                 }
2762         }
2763
2764         efx_farch_filter_push_rx_config(efx);
2765         efx_farch_filter_push_tx_limits(efx);
2766
2767         spin_unlock_bh(&efx->filter_lock);
2768 }
2769
2770 void efx_farch_filter_table_remove(struct efx_nic *efx)
2771 {
2772         struct efx_farch_filter_state *state = efx->filter_state;
2773         enum efx_farch_filter_table_id table_id;
2774
2775         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2776                 kfree(state->table[table_id].used_bitmap);
2777                 vfree(state->table[table_id].spec);
2778         }
2779         kfree(state);
2780 }
2781
2782 int efx_farch_filter_table_probe(struct efx_nic *efx)
2783 {
2784         struct efx_farch_filter_state *state;
2785         struct efx_farch_filter_table *table;
2786         unsigned table_id;
2787
2788         state = kzalloc(sizeof(struct efx_farch_filter_state), GFP_KERNEL);
2789         if (!state)
2790                 return -ENOMEM;
2791         efx->filter_state = state;
2792
2793         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2794                 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2795                 table->id = EFX_FARCH_FILTER_TABLE_RX_IP;
2796                 table->offset = FR_BZ_RX_FILTER_TBL0;
2797                 table->size = FR_BZ_RX_FILTER_TBL0_ROWS;
2798                 table->step = FR_BZ_RX_FILTER_TBL0_STEP;
2799         }
2800
2801         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
2802                 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
2803                 table->id = EFX_FARCH_FILTER_TABLE_RX_MAC;
2804                 table->offset = FR_CZ_RX_MAC_FILTER_TBL0;
2805                 table->size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
2806                 table->step = FR_CZ_RX_MAC_FILTER_TBL0_STEP;
2807
2808                 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2809                 table->id = EFX_FARCH_FILTER_TABLE_RX_DEF;
2810                 table->size = EFX_FARCH_FILTER_SIZE_RX_DEF;
2811
2812                 table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2813                 table->id = EFX_FARCH_FILTER_TABLE_TX_MAC;
2814                 table->offset = FR_CZ_TX_MAC_FILTER_TBL0;
2815                 table->size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
2816                 table->step = FR_CZ_TX_MAC_FILTER_TBL0_STEP;
2817         }
2818
2819         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2820                 table = &state->table[table_id];
2821                 if (table->size == 0)
2822                         continue;
2823                 table->used_bitmap = kcalloc(BITS_TO_LONGS(table->size),
2824                                              sizeof(unsigned long),
2825                                              GFP_KERNEL);
2826                 if (!table->used_bitmap)
2827                         goto fail;
2828                 table->spec = vzalloc(table->size * sizeof(*table->spec));
2829                 if (!table->spec)
2830                         goto fail;
2831         }
2832
2833         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2834         if (table->size) {
2835                 /* RX default filters must always exist */
2836                 struct efx_farch_filter_spec *spec;
2837                 unsigned i;
2838
2839                 for (i = 0; i < EFX_FARCH_FILTER_SIZE_RX_DEF; i++) {
2840                         spec = &table->spec[i];
2841                         spec->type = EFX_FARCH_FILTER_UC_DEF + i;
2842                         efx_farch_filter_init_rx_auto(efx, spec);
2843                         __set_bit(i, table->used_bitmap);
2844                 }
2845         }
2846
2847         efx_farch_filter_push_rx_config(efx);
2848
2849         return 0;
2850
2851 fail:
2852         efx_farch_filter_table_remove(efx);
2853         return -ENOMEM;
2854 }
2855
2856 /* Update scatter enable flags for filters pointing to our own RX queues */
2857 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx)
2858 {
2859         struct efx_farch_filter_state *state = efx->filter_state;
2860         enum efx_farch_filter_table_id table_id;
2861         struct efx_farch_filter_table *table;
2862         efx_oword_t filter;
2863         unsigned int filter_idx;
2864
2865         spin_lock_bh(&efx->filter_lock);
2866
2867         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2868              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2869              table_id++) {
2870                 table = &state->table[table_id];
2871
2872                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2873                         if (!test_bit(filter_idx, table->used_bitmap) ||
2874                             table->spec[filter_idx].dmaq_id >=
2875                             efx->n_rx_channels)
2876                                 continue;
2877
2878                         if (efx->rx_scatter)
2879                                 table->spec[filter_idx].flags |=
2880                                         EFX_FILTER_FLAG_RX_SCATTER;
2881                         else
2882                                 table->spec[filter_idx].flags &=
2883                                         ~EFX_FILTER_FLAG_RX_SCATTER;
2884
2885                         if (table_id == EFX_FARCH_FILTER_TABLE_RX_DEF)
2886                                 /* Pushed by efx_farch_filter_push_rx_config() */
2887                                 continue;
2888
2889                         efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2890                         efx_writeo(efx, &filter,
2891                                    table->offset + table->step * filter_idx);
2892                 }
2893         }
2894
2895         efx_farch_filter_push_rx_config(efx);
2896
2897         spin_unlock_bh(&efx->filter_lock);
2898 }
2899
2900 #ifdef CONFIG_RFS_ACCEL
2901
2902 s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
2903                                 struct efx_filter_spec *gen_spec)
2904 {
2905         return efx_farch_filter_insert(efx, gen_spec, true);
2906 }
2907
2908 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2909                                      unsigned int index)
2910 {
2911         struct efx_farch_filter_state *state = efx->filter_state;
2912         struct efx_farch_filter_table *table =
2913                 &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2914
2915         if (test_bit(index, table->used_bitmap) &&
2916             table->spec[index].priority == EFX_FILTER_PRI_HINT &&
2917             rps_may_expire_flow(efx->net_dev, table->spec[index].dmaq_id,
2918                                 flow_id, index)) {
2919                 efx_farch_filter_table_clear_entry(efx, table, index);
2920                 return true;
2921         }
2922
2923         return false;
2924 }
2925
2926 #endif /* CONFIG_RFS_ACCEL */
2927
2928 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx)
2929 {
2930         struct net_device *net_dev = efx->net_dev;
2931         struct netdev_hw_addr *ha;
2932         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2933         u32 crc;
2934         int bit;
2935
2936         netif_addr_lock_bh(net_dev);
2937
2938         efx->unicast_filter = !(net_dev->flags & IFF_PROMISC);
2939
2940         /* Build multicast hash table */
2941         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2942                 memset(mc_hash, 0xff, sizeof(*mc_hash));
2943         } else {
2944                 memset(mc_hash, 0x00, sizeof(*mc_hash));
2945                 netdev_for_each_mc_addr(ha, net_dev) {
2946                         crc = ether_crc_le(ETH_ALEN, ha->addr);
2947                         bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
2948                         __set_bit_le(bit, mc_hash);
2949                 }
2950
2951                 /* Broadcast packets go through the multicast hash filter.
2952                  * ether_crc_le() of the broadcast address is 0xbe2612ff
2953                  * so we always add bit 0xff to the mask.
2954                  */
2955                 __set_bit_le(0xff, mc_hash);
2956         }
2957
2958         netif_addr_unlock_bh(net_dev);
2959 }