drivers/net/ethernet/sfc/farch.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/pci.h>
  15 #include <linux/module.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/crc32.h>
  18 #include "net_driver.h"
  19 #include "bitfield.h"
  20 #include "efx.h"
  21 #include "nic.h"
  22 #include "farch_regs.h"
  23 #include "io.h"
  24 #include "workarounds.h"
  25
  26 /* Falcon-architecture (SFC4000 and SFC9000-family) support */
  27
  28 /**************************************************************************
  29  *
  30  * Configurable values
  31  *
  32  **************************************************************************
  33  */
  34
  35 /* This is set to 16 for a good reason.  In summary, if larger than
  36  * 16, the descriptor cache holds more than a default socket
  37  * buffer's worth of packets (for UDP we can only have at most one
  38  * socket buffer's worth outstanding).  This combined with the fact
  39  * that we only get 1 TX event per descriptor cache means the NIC
  40  * goes idle.
  41  */
  42 #define TX_DC_ENTRIES 16
  43 #define TX_DC_ENTRIES_ORDER 1
  44
  45 #define RX_DC_ENTRIES 64
  46 #define RX_DC_ENTRIES_ORDER 3
  47
  48 /* If EFX_MAX_INT_ERRORS internal errors occur within
  49  * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
  50  * disable it.
  51  */
  52 #define EFX_INT_ERROR_EXPIRE 3600
  53 #define EFX_MAX_INT_ERRORS 5
  54
  55 /* Depth of RX flush request fifo */
  56 #define EFX_RX_FLUSH_COUNT 4
  57
  58 /* Driver generated events */
  59 #define _EFX_CHANNEL_MAGIC_TEST         0x000101
  60 #define _EFX_CHANNEL_MAGIC_FILL         0x000102
  61 #define _EFX_CHANNEL_MAGIC_RX_DRAIN     0x000103
  62 #define _EFX_CHANNEL_MAGIC_TX_DRAIN     0x000104
  63
  64 #define _EFX_CHANNEL_MAGIC(_code, _data)        ((_code) << 8 | (_data))
  65 #define _EFX_CHANNEL_MAGIC_CODE(_magic)         ((_magic) >> 8)
  66
  67 #define EFX_CHANNEL_MAGIC_TEST(_channel)                                \
  68         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel)
  69 #define EFX_CHANNEL_MAGIC_FILL(_rx_queue)                               \
  70         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL,                     \
  71                            efx_rx_queue_index(_rx_queue))
  72 #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue)                           \
  73         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN,                 \
  74                            efx_rx_queue_index(_rx_queue))
  75 #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue)                           \
  76         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN,                 \
  77                            (_tx_queue)->queue)
  78
  79 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic);
  80
  81 /**************************************************************************
  82  *
  83  * Hardware access
  84  *
  85  **************************************************************************/
  86
  87 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
  88                                      unsigned int index)
  89 {
  90         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
  91                         value, index);
  92 }
  93
  94 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
  95                                      const efx_oword_t *mask)
  96 {
  97         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
  98                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
  99 }
 100
 101 int efx_farch_test_registers(struct efx_nic *efx,
 102                              const struct efx_farch_register_test *regs,
 103                              size_t n_regs)
 104 {
 105         unsigned address = 0, i, j;
 106         efx_oword_t mask, imask, original, reg, buf;
 107
 108         for (i = 0; i < n_regs; ++i) {
 109                 address = regs[i].address;
 110                 mask = imask = regs[i].mask;
 111                 EFX_INVERT_OWORD(imask);
 112
 113                 efx_reado(efx, &original, address);
 114
 115                 /* bit sweep on and off */
 116                 for (j = 0; j < 128; j++) {
 117                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
 118                                 continue;
 119
 120                         /* Test this testable bit can be set in isolation */
 121                         EFX_AND_OWORD(reg, original, mask);
 122                         EFX_SET_OWORD32(reg, j, j, 1);
 123
 124                         efx_writeo(efx, &reg, address);
 125                         efx_reado(efx, &buf, address);
 126
 127                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 128                                 goto fail;
 129
 130                         /* Test this testable bit can be cleared in isolation */
 131                         EFX_OR_OWORD(reg, original, mask);
 132                         EFX_SET_OWORD32(reg, j, j, 0);
 133
 134                         efx_writeo(efx, &reg, address);
 135                         efx_reado(efx, &buf, address);
 136
 137                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 138                                 goto fail;
 139                 }
 140
 141                 efx_writeo(efx, &original, address);
 142         }
 143
 144         return 0;
 145
 146 fail:
 147         netif_err(efx, hw, efx->net_dev,
 148                   "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
 149                   " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
 150                   EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
 151         return -EIO;
 152 }
 153
 154 /**************************************************************************
 155  *
 156  * Special buffer handling
 157  * Special buffers are used for event queues and the TX and RX
 158  * descriptor rings.
 159  *
 160  *************************************************************************/
 161
 162 /*
 163  * Initialise a special buffer
 164  *
 165  * This will define a buffer (previously allocated via
 166  * efx_alloc_special_buffer()) in the buffer table, allowing
 167  * it to be used for event queues, descriptor rings etc.
 168  */
 169 static void
 170 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 171 {
 172         efx_qword_t buf_desc;
 173         unsigned int index;
 174         dma_addr_t dma_addr;
 175         int i;
 176
 177         EFX_BUG_ON_PARANOID(!buffer->buf.addr);
 178
 179         /* Write buffer descriptors to NIC */
 180         for (i = 0; i < buffer->entries; i++) {
 181                 index = buffer->index + i;
 182                 dma_addr = buffer->buf.dma_addr + (i * EFX_BUF_SIZE);
 183                 netif_dbg(efx, probe, efx->net_dev,
 184                           "mapping special buffer %d at %llx\n",
 185                           index, (unsigned long long)dma_addr);
 186                 EFX_POPULATE_QWORD_3(buf_desc,
 187                                      FRF_AZ_BUF_ADR_REGION, 0,
 188                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
 189                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
 190                 efx_write_buf_tbl(efx, &buf_desc, index);
 191         }
 192 }
 193
 194 /* Unmaps a buffer and clears the buffer table entries */
 195 static void
 196 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 197 {
 198         efx_oword_t buf_tbl_upd;
 199         unsigned int start = buffer->index;
 200         unsigned int end = (buffer->index + buffer->entries - 1);
 201
 202         if (!buffer->entries)
 203                 return;
 204
 205         netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
 206                   buffer->index, buffer->index + buffer->entries - 1);
 207
 208         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 209                              FRF_AZ_BUF_UPD_CMD, 0,
 210                              FRF_AZ_BUF_CLR_CMD, 1,
 211                              FRF_AZ_BUF_CLR_END_ID, end,
 212                              FRF_AZ_BUF_CLR_START_ID, start);
 213         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
 214 }
 215
 216 /*
 217  * Allocate a new special buffer
 218  *
 219  * This allocates memory for a new buffer, clears it and allocates a
 220  * new buffer ID range.  It does not write into the buffer table.
 221  *
 222  * This call will allocate 4KB buffers, since 8KB buffers can't be
 223  * used for event queues and descriptor rings.
 224  */
 225 static int efx_alloc_special_buffer(struct efx_nic *efx,
 226                                     struct efx_special_buffer *buffer,
 227                                     unsigned int len)
 228 {
 229         len = ALIGN(len, EFX_BUF_SIZE);
 230
 231         if (efx_nic_alloc_buffer(efx, &buffer->buf, len, GFP_KERNEL))
 232                 return -ENOMEM;
 233         buffer->entries = len / EFX_BUF_SIZE;
 234         BUG_ON(buffer->buf.dma_addr & (EFX_BUF_SIZE - 1));
 235
 236         /* Select new buffer ID */
 237         buffer->index = efx->next_buffer_table;
 238         efx->next_buffer_table += buffer->entries;
 239 #ifdef CONFIG_SFC_SRIOV
 240         BUG_ON(efx_sriov_enabled(efx) &&
 241                efx->vf_buftbl_base < efx->next_buffer_table);
 242 #endif
 243
 244         netif_dbg(efx, probe, efx->net_dev,
 245                   "allocating special buffers %d-%d at %llx+%x "
 246                   "(virt %p phys %llx)\n", buffer->index,
 247                   buffer->index + buffer->entries - 1,
 248                   (u64)buffer->buf.dma_addr, len,
 249                   buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
 250
 251         return 0;
 252 }
 253
 254 static void
 255 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 256 {
 257         if (!buffer->buf.addr)
 258                 return;
 259
 260         netif_dbg(efx, hw, efx->net_dev,
 261                   "deallocating special buffers %d-%d at %llx+%x "
 262                   "(virt %p phys %llx)\n", buffer->index,
 263                   buffer->index + buffer->entries - 1,
 264                   (u64)buffer->buf.dma_addr, buffer->buf.len,
 265                   buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
 266
 267         efx_nic_free_buffer(efx, &buffer->buf);
 268         buffer->entries = 0;
 269 }
 270
 271 /**************************************************************************
 272  *
 273  * TX path
 274  *
 275  **************************************************************************/
 276
 277 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 278 static inline void efx_farch_notify_tx_desc(struct efx_tx_queue *tx_queue)
 279 {
 280         unsigned write_ptr;
 281         efx_dword_t reg;
 282
 283         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 284         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
 285         efx_writed_page(tx_queue->efx, &reg,
 286                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 287 }
 288
 289 /* Write pointer and first descriptor for TX descriptor ring */
 290 static inline void efx_farch_push_tx_desc(struct efx_tx_queue *tx_queue,
 291                                           const efx_qword_t *txd)
 292 {
 293         unsigned write_ptr;
 294         efx_oword_t reg;
 295
 296         BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
 297         BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
 298
 299         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 300         EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
 301                              FRF_AZ_TX_DESC_WPTR, write_ptr);
 302         reg.qword[0] = *txd;
 303         efx_writeo_page(tx_queue->efx, &reg,
 304                         FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
 305 }
 306
 307
 308 /* For each entry inserted into the software descriptor ring, create a
 309  * descriptor in the hardware TX descriptor ring (in host memory), and
 310  * write a doorbell.
 311  */
 312 void efx_farch_tx_write(struct efx_tx_queue *tx_queue)
 313 {
 314         struct efx_tx_buffer *buffer;
 315         efx_qword_t *txd;
 316         unsigned write_ptr;
 317         unsigned old_write_count = tx_queue->write_count;
 318
 319         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 320
 321         do {
 322                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 323                 buffer = &tx_queue->buffer[write_ptr];
 324                 txd = efx_tx_desc(tx_queue, write_ptr);
 325                 ++tx_queue->write_count;
 326
 327                 EFX_BUG_ON_PARANOID(buffer->flags & EFX_TX_BUF_OPTION);
 328
 329                 /* Create TX descriptor ring entry */
 330                 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
 331                 EFX_POPULATE_QWORD_4(*txd,
 332                                      FSF_AZ_TX_KER_CONT,
 333                                      buffer->flags & EFX_TX_BUF_CONT,
 334                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
 335                                      FSF_AZ_TX_KER_BUF_REGION, 0,
 336                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 337         } while (tx_queue->write_count != tx_queue->insert_count);
 338
 339         wmb(); /* Ensure descriptors are written before they are fetched */
 340
 341         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
 342                 txd = efx_tx_desc(tx_queue,
 343                                   old_write_count & tx_queue->ptr_mask);
 344                 efx_farch_push_tx_desc(tx_queue, txd);
 345                 ++tx_queue->pushes;
 346         } else {
 347                 efx_farch_notify_tx_desc(tx_queue);
 348         }
 349 }
 350
 351 /* Allocate hardware resources for a TX queue */
 352 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue)
 353 {
 354         struct efx_nic *efx = tx_queue->efx;
 355         unsigned entries;
 356
 357         entries = tx_queue->ptr_mask + 1;
 358         return efx_alloc_special_buffer(efx, &tx_queue->txd,
 359                                         entries * sizeof(efx_qword_t));
 360 }
 361
 362 void efx_farch_tx_init(struct efx_tx_queue *tx_queue)
 363 {
 364         struct efx_nic *efx = tx_queue->efx;
 365         efx_oword_t reg;
 366
 367         /* Pin TX descriptor ring */
 368         efx_init_special_buffer(efx, &tx_queue->txd);
 369
 370         /* Push TX descriptor ring to card */
 371         EFX_POPULATE_OWORD_10(reg,
 372                               FRF_AZ_TX_DESCQ_EN, 1,
 373                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
 374                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
 375                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 376                               FRF_AZ_TX_DESCQ_EVQ_ID,
 377                               tx_queue->channel->channel,
 378                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
 379                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
 380                               FRF_AZ_TX_DESCQ_SIZE,
 381                               __ffs(tx_queue->txd.entries),
 382                               FRF_AZ_TX_DESCQ_TYPE, 0,
 383                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
 384
 385         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 386                 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
 387                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
 388                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS,
 389                                     !csum);
 390         }
 391
 392         efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
 393                          tx_queue->queue);
 394
 395         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 396                 /* Only 128 bits in this register */
 397                 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
 398
 399                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
 400                 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
 401                         __clear_bit_le(tx_queue->queue, &reg);
 402                 else
 403                         __set_bit_le(tx_queue->queue, &reg);
 404                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
 405         }
 406
 407         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 408                 EFX_POPULATE_OWORD_1(reg,
 409                                      FRF_BZ_TX_PACE,
 410                                      (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
 411                                      FFE_BZ_TX_PACE_OFF :
 412                                      FFE_BZ_TX_PACE_RESERVED);
 413                 efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL,
 414                                  tx_queue->queue);
 415         }
 416 }
 417
 418 static void efx_farch_flush_tx_queue(struct efx_tx_queue *tx_queue)
 419 {
 420         struct efx_nic *efx = tx_queue->efx;
 421         efx_oword_t tx_flush_descq;
 422
 423         WARN_ON(atomic_read(&tx_queue->flush_outstanding));
 424         atomic_set(&tx_queue->flush_outstanding, 1);
 425
 426         EFX_POPULATE_OWORD_2(tx_flush_descq,
 427                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
 428                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
 429         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
 430 }
 431
 432 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue)
 433 {
 434         struct efx_nic *efx = tx_queue->efx;
 435         efx_oword_t tx_desc_ptr;
 436
 437         /* Remove TX descriptor ring from card */
 438         EFX_ZERO_OWORD(tx_desc_ptr);
 439         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 440                          tx_queue->queue);
 441
 442         /* Unpin TX descriptor ring */
 443         efx_fini_special_buffer(efx, &tx_queue->txd);
 444 }
 445
 446 /* Free buffers backing TX queue */
 447 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue)
 448 {
 449         efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 450 }
 451
 452 /**************************************************************************
 453  *
 454  * RX path
 455  *
 456  **************************************************************************/
 457
 458 /* This creates an entry in the RX descriptor queue */
 459 static inline void
 460 efx_farch_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
 461 {
 462         struct efx_rx_buffer *rx_buf;
 463         efx_qword_t *rxd;
 464
 465         rxd = efx_rx_desc(rx_queue, index);
 466         rx_buf = efx_rx_buffer(rx_queue, index);
 467         EFX_POPULATE_QWORD_3(*rxd,
 468                              FSF_AZ_RX_KER_BUF_SIZE,
 469                              rx_buf->len -
 470                              rx_queue->efx->type->rx_buffer_padding,
 471                              FSF_AZ_RX_KER_BUF_REGION, 0,
 472                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
 473 }
 474
 475 /* This writes to the RX_DESC_WPTR register for the specified receive
 476  * descriptor ring.
 477  */
 478 void efx_farch_rx_write(struct efx_rx_queue *rx_queue)
 479 {
 480         struct efx_nic *efx = rx_queue->efx;
 481         efx_dword_t reg;
 482         unsigned write_ptr;
 483
 484         while (rx_queue->notified_count != rx_queue->added_count) {
 485                 efx_farch_build_rx_desc(
 486                         rx_queue,
 487                         rx_queue->notified_count & rx_queue->ptr_mask);
 488                 ++rx_queue->notified_count;
 489         }
 490
 491         wmb();
 492         write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
 493         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
 494         efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
 495                         efx_rx_queue_index(rx_queue));
 496 }
 497
 498 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue)
 499 {
 500         struct efx_nic *efx = rx_queue->efx;
 501         unsigned entries;
 502
 503         entries = rx_queue->ptr_mask + 1;
 504         return efx_alloc_special_buffer(efx, &rx_queue->rxd,
 505                                         entries * sizeof(efx_qword_t));
 506 }
 507
 508 void efx_farch_rx_init(struct efx_rx_queue *rx_queue)
 509 {
 510         efx_oword_t rx_desc_ptr;
 511         struct efx_nic *efx = rx_queue->efx;
 512         bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
 513         bool iscsi_digest_en = is_b0;
 514         bool jumbo_en;
 515
 516         /* For kernel-mode queues in Falcon A1, the JUMBO flag enables
 517          * DMA to continue after a PCIe page boundary (and scattering
 518          * is not possible).  In Falcon B0 and Siena, it enables
 519          * scatter.
 520          */
 521         jumbo_en = !is_b0 || efx->rx_scatter;
 522
 523         netif_dbg(efx, hw, efx->net_dev,
 524                   "RX queue %d ring in special buffers %d-%d\n",
 525                   efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
 526                   rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 527
 528         rx_queue->scatter_n = 0;
 529
 530         /* Pin RX descriptor ring */
 531         efx_init_special_buffer(efx, &rx_queue->rxd);
 532
 533         /* Push RX descriptor ring to card */
 534         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 535                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
 536                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
 537                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 538                               FRF_AZ_RX_DESCQ_EVQ_ID,
 539                               efx_rx_queue_channel(rx_queue)->channel,
 540                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
 541                               FRF_AZ_RX_DESCQ_LABEL,
 542                               efx_rx_queue_index(rx_queue),
 543                               FRF_AZ_RX_DESCQ_SIZE,
 544                               __ffs(rx_queue->rxd.entries),
 545                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 546                               FRF_AZ_RX_DESCQ_JUMBO, jumbo_en,
 547                               FRF_AZ_RX_DESCQ_EN, 1);
 548         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 549                          efx_rx_queue_index(rx_queue));
 550 }
 551
 552 static void efx_farch_flush_rx_queue(struct efx_rx_queue *rx_queue)
 553 {
 554         struct efx_nic *efx = rx_queue->efx;
 555         efx_oword_t rx_flush_descq;
 556
 557         EFX_POPULATE_OWORD_2(rx_flush_descq,
 558                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
 559                              FRF_AZ_RX_FLUSH_DESCQ,
 560                              efx_rx_queue_index(rx_queue));
 561         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
 562 }
 563
 564 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue)
 565 {
 566         efx_oword_t rx_desc_ptr;
 567         struct efx_nic *efx = rx_queue->efx;
 568
 569         /* Remove RX descriptor ring from card */
 570         EFX_ZERO_OWORD(rx_desc_ptr);
 571         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 572                          efx_rx_queue_index(rx_queue));
 573
 574         /* Unpin RX descriptor ring */
 575         efx_fini_special_buffer(efx, &rx_queue->rxd);
 576 }
 577
 578 /* Free buffers backing RX queue */
 579 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue)
 580 {
 581         efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 582 }
 583
 584 /**************************************************************************
 585  *
 586  * Flush handling
 587  *
 588  **************************************************************************/
 589
 590 /* efx_farch_flush_queues() must be woken up when all flushes are completed,
 591  * or more RX flushes can be kicked off.
 592  */
 593 static bool efx_farch_flush_wake(struct efx_nic *efx)
 594 {
 595         /* Ensure that all updates are visible to efx_farch_flush_queues() */
 596         smp_mb();
 597
 598         return (atomic_read(&efx->active_queues) == 0 ||
 599                 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT
 600                  && atomic_read(&efx->rxq_flush_pending) > 0));
 601 }
 602
 603 static bool efx_check_tx_flush_complete(struct efx_nic *efx)
 604 {
 605         bool i = true;
 606         efx_oword_t txd_ptr_tbl;
 607         struct efx_channel *channel;
 608         struct efx_tx_queue *tx_queue;
 609
 610         efx_for_each_channel(channel, efx) {
 611                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 612                         efx_reado_table(efx, &txd_ptr_tbl,
 613                                         FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue);
 614                         if (EFX_OWORD_FIELD(txd_ptr_tbl,
 615                                             FRF_AZ_TX_DESCQ_FLUSH) ||
 616                             EFX_OWORD_FIELD(txd_ptr_tbl,
 617                                             FRF_AZ_TX_DESCQ_EN)) {
 618                                 netif_dbg(efx, hw, efx->net_dev,
 619                                           "flush did not complete on TXQ %d\n",
 620                                           tx_queue->queue);
 621                                 i = false;
 622                         } else if (atomic_cmpxchg(&tx_queue->flush_outstanding,
 623                                                   1, 0)) {
 624                                 /* The flush is complete, but we didn't
 625                                  * receive a flush completion event
 626                                  */
 627                                 netif_dbg(efx, hw, efx->net_dev,
 628                                           "flush complete on TXQ %d, so drain "
 629                                           "the queue\n", tx_queue->queue);
 630                                 /* Don't need to increment active_queues as it
 631                                  * has already been incremented for the queues
 632                                  * which did not drain
 633                                  */
 634                                 efx_farch_magic_event(channel,
 635                                                       EFX_CHANNEL_MAGIC_TX_DRAIN(
 636                                                               tx_queue));
 637                         }
 638                 }
 639         }
 640
 641         return i;
 642 }
 643
 644 /* Flush all the transmit queues, and continue flushing receive queues until
 645  * they're all flushed. Wait for the DRAIN events to be recieved so that there
 646  * are no more RX and TX events left on any channel. */
 647 static int efx_farch_do_flush(struct efx_nic *efx)
 648 {
 649         unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */
 650         struct efx_channel *channel;
 651         struct efx_rx_queue *rx_queue;
 652         struct efx_tx_queue *tx_queue;
 653         int rc = 0;
 654
 655         efx_for_each_channel(channel, efx) {
 656                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 657                         efx_farch_flush_tx_queue(tx_queue);
 658                 }
 659                 efx_for_each_channel_rx_queue(rx_queue, channel) {
 660                         rx_queue->flush_pending = true;
 661                         atomic_inc(&efx->rxq_flush_pending);
 662                 }
 663         }
 664
 665         while (timeout && atomic_read(&efx->active_queues) > 0) {
 666                 /* If SRIOV is enabled, then offload receive queue flushing to
 667                  * the firmware (though we will still have to poll for
 668                  * completion). If that fails, fall back to the old scheme.
 669                  */
 670                 if (efx_sriov_enabled(efx)) {
 671                         rc = efx_mcdi_flush_rxqs(efx);
 672                         if (!rc)
 673                                 goto wait;
 674                 }
 675
 676                 /* The hardware supports four concurrent rx flushes, each of
 677                  * which may need to be retried if there is an outstanding
 678                  * descriptor fetch
 679                  */
 680                 efx_for_each_channel(channel, efx) {
 681                         efx_for_each_channel_rx_queue(rx_queue, channel) {
 682                                 if (atomic_read(&efx->rxq_flush_outstanding) >=
 683                                     EFX_RX_FLUSH_COUNT)
 684                                         break;
 685
 686                                 if (rx_queue->flush_pending) {
 687                                         rx_queue->flush_pending = false;
 688                                         atomic_dec(&efx->rxq_flush_pending);
 689                                         atomic_inc(&efx->rxq_flush_outstanding);
 690                                         efx_farch_flush_rx_queue(rx_queue);
 691                                 }
 692                         }
 693                 }
 694
 695         wait:
 696                 timeout = wait_event_timeout(efx->flush_wq,
 697                                              efx_farch_flush_wake(efx),
 698                                              timeout);
 699         }
 700
 701         if (atomic_read(&efx->active_queues) &&
 702             !efx_check_tx_flush_complete(efx)) {
 703                 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues "
 704                           "(rx %d+%d)\n", atomic_read(&efx->active_queues),
 705                           atomic_read(&efx->rxq_flush_outstanding),
 706                           atomic_read(&efx->rxq_flush_pending));
 707                 rc = -ETIMEDOUT;
 708
 709                 atomic_set(&efx->active_queues, 0);
 710                 atomic_set(&efx->rxq_flush_pending, 0);
 711                 atomic_set(&efx->rxq_flush_outstanding, 0);
 712         }
 713
 714         return rc;
 715 }
 716
 717 int efx_farch_fini_dmaq(struct efx_nic *efx)
 718 {
 719         struct efx_channel *channel;
 720         struct efx_tx_queue *tx_queue;
 721         struct efx_rx_queue *rx_queue;
 722         int rc = 0;
 723
 724         /* Do not attempt to write to the NIC during EEH recovery */
 725         if (efx->state != STATE_RECOVERY) {
 726                 /* Only perform flush if DMA is enabled */
 727                 if (efx->pci_dev->is_busmaster) {
 728                         efx->type->prepare_flush(efx);
 729                         rc = efx_farch_do_flush(efx);
 730                         efx->type->finish_flush(efx);
 731                 }
 732
 733                 efx_for_each_channel(channel, efx) {
 734                         efx_for_each_channel_rx_queue(rx_queue, channel)
 735                                 efx_farch_rx_fini(rx_queue);
 736                         efx_for_each_channel_tx_queue(tx_queue, channel)
 737                                 efx_farch_tx_fini(tx_queue);
 738                 }
 739         }
 740
 741         return rc;
 742 }
 743
 744 /**************************************************************************
 745  *
 746  * Event queue processing
 747  * Event queues are processed by per-channel tasklets.
 748  *
 749  **************************************************************************/
 750
 751 /* Update a channel's event queue's read pointer (RPTR) register
 752  *
 753  * This writes the EVQ_RPTR_REG register for the specified channel's
 754  * event queue.
 755  */
 756 void efx_farch_ev_read_ack(struct efx_channel *channel)
 757 {
 758         efx_dword_t reg;
 759         struct efx_nic *efx = channel->efx;
 760
 761         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
 762                              channel->eventq_read_ptr & channel->eventq_mask);
 763
 764         /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size
 765          * of 4 bytes, but it is really 16 bytes just like later revisions.
 766          */
 767         efx_writed(efx, &reg,
 768                    efx->type->evq_rptr_tbl_base +
 769                    FR_BZ_EVQ_RPTR_STEP * channel->channel);
 770 }
 771
 772 /* Use HW to insert a SW defined event */
 773 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
 774                               efx_qword_t *event)
 775 {
 776         efx_oword_t drv_ev_reg;
 777
 778         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
 779                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
 780         drv_ev_reg.u32[0] = event->u32[0];
 781         drv_ev_reg.u32[1] = event->u32[1];
 782         drv_ev_reg.u32[2] = 0;
 783         drv_ev_reg.u32[3] = 0;
 784         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq);
 785         efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV);
 786 }
 787
 788 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic)
 789 {
 790         efx_qword_t event;
 791
 792         EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE,
 793                              FSE_AZ_EV_CODE_DRV_GEN_EV,
 794                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
 795         efx_farch_generate_event(channel->efx, channel->channel, &event);
 796 }
 797
 798 /* Handle a transmit completion event
 799  *
 800  * The NIC batches TX completion events; the message we receive is of
 801  * the form "complete all TX events up to this index".
 802  */
 803 static int
 804 efx_farch_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
 805 {
 806         unsigned int tx_ev_desc_ptr;
 807         unsigned int tx_ev_q_label;
 808         struct efx_tx_queue *tx_queue;
 809         struct efx_nic *efx = channel->efx;
 810         int tx_packets = 0;
 811
 812         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
 813                 return 0;
 814
 815         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
 816                 /* Transmit completion */
 817                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
 818                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 819                 tx_queue = efx_channel_get_tx_queue(
 820                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 821                 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
 822                               tx_queue->ptr_mask);
 823                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 824         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
 825                 /* Rewrite the FIFO write pointer */
 826                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 827                 tx_queue = efx_channel_get_tx_queue(
 828                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 829
 830                 netif_tx_lock(efx->net_dev);
 831                 efx_farch_notify_tx_desc(tx_queue);
 832                 netif_tx_unlock(efx->net_dev);
 833         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR)) {
 834                 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
 835         } else {
 836                 netif_err(efx, tx_err, efx->net_dev,
 837                           "channel %d unexpected TX event "
 838                           EFX_QWORD_FMT"\n", channel->channel,
 839                           EFX_QWORD_VAL(*event));
 840         }
 841
 842         return tx_packets;
 843 }
 844
 845 /* Detect errors included in the rx_evt_pkt_ok bit. */
 846 static u16 efx_farch_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 847                                       const efx_qword_t *event)
 848 {
 849         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 850         struct efx_nic *efx = rx_queue->efx;
 851         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 852         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 853         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 854         bool rx_ev_other_err, rx_ev_pause_frm;
 855         bool rx_ev_hdr_type, rx_ev_mcast_pkt;
 856         unsigned rx_ev_pkt_type;
 857
 858         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 859         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 860         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
 861         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
 862         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 863                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
 864         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 865                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
 866         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 867                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
 868         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
 869         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
 870         rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
 871                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
 872         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
 873
 874         /* Every error apart from tobe_disc and pause_frm */
 875         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 876                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 877                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 878
 879         /* Count errors that are not in MAC stats.  Ignore expected
 880          * checksum errors during self-test. */
 881         if (rx_ev_frm_trunc)
 882                 ++channel->n_rx_frm_trunc;
 883         else if (rx_ev_tobe_disc)
 884                 ++channel->n_rx_tobe_disc;
 885         else if (!efx->loopback_selftest) {
 886                 if (rx_ev_ip_hdr_chksum_err)
 887                         ++channel->n_rx_ip_hdr_chksum_err;
 888                 else if (rx_ev_tcp_udp_chksum_err)
 889                         ++channel->n_rx_tcp_udp_chksum_err;
 890         }
 891
 892         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 893          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 894          * to a FIFO overflow.
 895          */
 896 #ifdef DEBUG
 897         if (rx_ev_other_err && net_ratelimit()) {
 898                 netif_dbg(efx, rx_err, efx->net_dev,
 899                           " RX queue %d unexpected RX event "
 900                           EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 901                           efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
 902                           rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 903                           rx_ev_ip_hdr_chksum_err ?
 904                           " [IP_HDR_CHKSUM_ERR]" : "",
 905                           rx_ev_tcp_udp_chksum_err ?
 906                           " [TCP_UDP_CHKSUM_ERR]" : "",
 907                           rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 908                           rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 909                           rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 910                           rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 911                           rx_ev_pause_frm ? " [PAUSE]" : "");
 912         }
 913 #endif
 914
 915         /* The frame must be discarded if any of these are true. */
 916         return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 917                 rx_ev_tobe_disc | rx_ev_pause_frm) ?
 918                 EFX_RX_PKT_DISCARD : 0;
 919 }
 920
 921 /* Handle receive events that are not in-order. Return true if this
 922  * can be handled as a partial packet discard, false if it's more
 923  * serious.
 924  */
 925 static bool
 926 efx_farch_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
 927 {
 928         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 929         struct efx_nic *efx = rx_queue->efx;
 930         unsigned expected, dropped;
 931
 932         if (rx_queue->scatter_n &&
 933             index == ((rx_queue->removed_count + rx_queue->scatter_n - 1) &
 934                       rx_queue->ptr_mask)) {
 935                 ++channel->n_rx_nodesc_trunc;
 936                 return true;
 937         }
 938
 939         expected = rx_queue->removed_count & rx_queue->ptr_mask;
 940         dropped = (index - expected) & rx_queue->ptr_mask;
 941         netif_info(efx, rx_err, efx->net_dev,
 942                    "dropped %d events (index=%d expected=%d)\n",
 943                    dropped, index, expected);
 944
 945         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 946                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 947         return false;
 948 }
 949
 950 /* Handle a packet received event
 951  *
 952  * The NIC gives a "discard" flag if it's a unicast packet with the
 953  * wrong destination address
 954  * Also "is multicast" and "matches multicast filter" flags can be used to
 955  * discard non-matching multicast packets.
 956  */
 957 static void
 958 efx_farch_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
 959 {
 960         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 961         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 962         unsigned expected_ptr;
 963         bool rx_ev_pkt_ok, rx_ev_sop, rx_ev_cont;
 964         u16 flags;
 965         struct efx_rx_queue *rx_queue;
 966         struct efx_nic *efx = channel->efx;
 967
 968         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
 969                 return;
 970
 971         rx_ev_cont = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT);
 972         rx_ev_sop = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP);
 973         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
 974                 channel->channel);
 975
 976         rx_queue = efx_channel_get_rx_queue(channel);
 977
 978         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
 979         expected_ptr = ((rx_queue->removed_count + rx_queue->scatter_n) &
 980                         rx_queue->ptr_mask);
 981
 982         /* Check for partial drops and other errors */
 983         if (unlikely(rx_ev_desc_ptr != expected_ptr) ||
 984             unlikely(rx_ev_sop != (rx_queue->scatter_n == 0))) {
 985                 if (rx_ev_desc_ptr != expected_ptr &&
 986                     !efx_farch_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr))
 987                         return;
 988
 989                 /* Discard all pending fragments */
 990                 if (rx_queue->scatter_n) {
 991                         efx_rx_packet(
 992                                 rx_queue,
 993                                 rx_queue->removed_count & rx_queue->ptr_mask,
 994                                 rx_queue->scatter_n, 0, EFX_RX_PKT_DISCARD);
 995                         rx_queue->removed_count += rx_queue->scatter_n;
 996                         rx_queue->scatter_n = 0;
 997                 }
 998
 999                 /* Return if there is no new fragment */
1000                 if (rx_ev_desc_ptr != expected_ptr)
1001                         return;
1002
1003                 /* Discard new fragment if not SOP */
1004                 if (!rx_ev_sop) {
1005                         efx_rx_packet(
1006                                 rx_queue,
1007                                 rx_queue->removed_count & rx_queue->ptr_mask,
1008                                 1, 0, EFX_RX_PKT_DISCARD);
1009                         ++rx_queue->removed_count;
1010                         return;
1011                 }
1012         }
1013
1014         ++rx_queue->scatter_n;
1015         if (rx_ev_cont)
1016                 return;
1017
1018         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
1019         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
1020         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
1021
1022         if (likely(rx_ev_pkt_ok)) {
1023                 /* If packet is marked as OK then we can rely on the
1024                  * hardware checksum and classification.
1025                  */
1026                 flags = 0;
1027                 switch (rx_ev_hdr_type) {
1028                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
1029                         flags |= EFX_RX_PKT_TCP;
1030                         /* fall through */
1031                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
1032                         flags |= EFX_RX_PKT_CSUMMED;
1033                         /* fall through */
1034                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
1035                 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
1036                         break;
1037                 }
1038         } else {
1039                 flags = efx_farch_handle_rx_not_ok(rx_queue, event);
1040         }
1041
1042         /* Detect multicast packets that didn't match the filter */
1043         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
1044         if (rx_ev_mcast_pkt) {
1045                 unsigned int rx_ev_mcast_hash_match =
1046                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
1047
1048                 if (unlikely(!rx_ev_mcast_hash_match)) {
1049                         ++channel->n_rx_mcast_mismatch;
1050                         flags |= EFX_RX_PKT_DISCARD;
1051                 }
1052         }
1053
1054         channel->irq_mod_score += 2;
1055
1056         /* Handle received packet */
1057         efx_rx_packet(rx_queue,
1058                       rx_queue->removed_count & rx_queue->ptr_mask,
1059                       rx_queue->scatter_n, rx_ev_byte_cnt, flags);
1060         rx_queue->removed_count += rx_queue->scatter_n;
1061         rx_queue->scatter_n = 0;
1062 }
1063
1064 /* If this flush done event corresponds to a &struct efx_tx_queue, then
1065  * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue
1066  * of all transmit completions.
1067  */
1068 static void
1069 efx_farch_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1070 {
1071         struct efx_tx_queue *tx_queue;
1072         int qid;
1073
1074         qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1075         if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) {
1076                 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES,
1077                                             qid % EFX_TXQ_TYPES);
1078                 if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) {
1079                         efx_farch_magic_event(tx_queue->channel,
1080                                               EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue));
1081                 }
1082         }
1083 }
1084
1085 /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
1086  * was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
1087  * the RX queue back to the mask of RX queues in need of flushing.
1088  */
1089 static void
1090 efx_farch_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1091 {
1092         struct efx_channel *channel;
1093         struct efx_rx_queue *rx_queue;
1094         int qid;
1095         bool failed;
1096
1097         qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1098         failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1099         if (qid >= efx->n_channels)
1100                 return;
1101         channel = efx_get_channel(efx, qid);
1102         if (!efx_channel_has_rx_queue(channel))
1103                 return;
1104         rx_queue = efx_channel_get_rx_queue(channel);
1105
1106         if (failed) {
1107                 netif_info(efx, hw, efx->net_dev,
1108                            "RXQ %d flush retry\n", qid);
1109                 rx_queue->flush_pending = true;
1110                 atomic_inc(&efx->rxq_flush_pending);
1111         } else {
1112                 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1113                                       EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue));
1114         }
1115         atomic_dec(&efx->rxq_flush_outstanding);
1116         if (efx_farch_flush_wake(efx))
1117                 wake_up(&efx->flush_wq);
1118 }
1119
1120 static void
1121 efx_farch_handle_drain_event(struct efx_channel *channel)
1122 {
1123         struct efx_nic *efx = channel->efx;
1124
1125         WARN_ON(atomic_read(&efx->active_queues) == 0);
1126         atomic_dec(&efx->active_queues);
1127         if (efx_farch_flush_wake(efx))
1128                 wake_up(&efx->flush_wq);
1129 }
1130
1131 static void efx_farch_handle_generated_event(struct efx_channel *channel,
1132                                              efx_qword_t *event)
1133 {
1134         struct efx_nic *efx = channel->efx;
1135         struct efx_rx_queue *rx_queue =
1136                 efx_channel_has_rx_queue(channel) ?
1137                 efx_channel_get_rx_queue(channel) : NULL;
1138         unsigned magic, code;
1139
1140         magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
1141         code = _EFX_CHANNEL_MAGIC_CODE(magic);
1142
1143         if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) {
1144                 channel->event_test_cpu = raw_smp_processor_id();
1145         } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) {
1146                 /* The queue must be empty, so we won't receive any rx
1147                  * events, so efx_process_channel() won't refill the
1148                  * queue. Refill it here */
1149                 efx_fast_push_rx_descriptors(rx_queue, true);
1150         } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) {
1151                 efx_farch_handle_drain_event(channel);
1152         } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) {
1153                 efx_farch_handle_drain_event(channel);
1154         } else {
1155                 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
1156                           "generated event "EFX_QWORD_FMT"\n",
1157                           channel->channel, EFX_QWORD_VAL(*event));
1158         }
1159 }
1160
1161 static void
1162 efx_farch_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1163 {
1164         struct efx_nic *efx = channel->efx;
1165         unsigned int ev_sub_code;
1166         unsigned int ev_sub_data;
1167
1168         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
1169         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1170
1171         switch (ev_sub_code) {
1172         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
1173                 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
1174                            channel->channel, ev_sub_data);
1175                 efx_farch_handle_tx_flush_done(efx, event);
1176                 efx_sriov_tx_flush_done(efx, event);
1177                 break;
1178         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
1179                 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
1180                            channel->channel, ev_sub_data);
1181                 efx_farch_handle_rx_flush_done(efx, event);
1182                 efx_sriov_rx_flush_done(efx, event);
1183                 break;
1184         case FSE_AZ_EVQ_INIT_DONE_EV:
1185                 netif_dbg(efx, hw, efx->net_dev,
1186                           "channel %d EVQ %d initialised\n",
1187                           channel->channel, ev_sub_data);
1188                 break;
1189         case FSE_AZ_SRM_UPD_DONE_EV:
1190                 netif_vdbg(efx, hw, efx->net_dev,
1191                            "channel %d SRAM update done\n", channel->channel);
1192                 break;
1193         case FSE_AZ_WAKE_UP_EV:
1194                 netif_vdbg(efx, hw, efx->net_dev,
1195                            "channel %d RXQ %d wakeup event\n",
1196                            channel->channel, ev_sub_data);
1197                 break;
1198         case FSE_AZ_TIMER_EV:
1199                 netif_vdbg(efx, hw, efx->net_dev,
1200                            "channel %d RX queue %d timer expired\n",
1201                            channel->channel, ev_sub_data);
1202                 break;
1203         case FSE_AA_RX_RECOVER_EV:
1204                 netif_err(efx, rx_err, efx->net_dev,
1205                           "channel %d seen DRIVER RX_RESET event. "
1206                         "Resetting.\n", channel->channel);
1207                 atomic_inc(&efx->rx_reset);
1208                 efx_schedule_reset(efx,
1209                                    EFX_WORKAROUND_6555(efx) ?
1210                                    RESET_TYPE_RX_RECOVERY :
1211                                    RESET_TYPE_DISABLE);
1212                 break;
1213         case FSE_BZ_RX_DSC_ERROR_EV:
1214                 if (ev_sub_data < EFX_VI_BASE) {
1215                         netif_err(efx, rx_err, efx->net_dev,
1216                                   "RX DMA Q %d reports descriptor fetch error."
1217                                   " RX Q %d is disabled.\n", ev_sub_data,
1218                                   ev_sub_data);
1219                         efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1220                 } else
1221                         efx_sriov_desc_fetch_err(efx, ev_sub_data);
1222                 break;
1223         case FSE_BZ_TX_DSC_ERROR_EV:
1224                 if (ev_sub_data < EFX_VI_BASE) {
1225                         netif_err(efx, tx_err, efx->net_dev,
1226                                   "TX DMA Q %d reports descriptor fetch error."
1227                                   " TX Q %d is disabled.\n", ev_sub_data,
1228                                   ev_sub_data);
1229                         efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1230                 } else
1231                         efx_sriov_desc_fetch_err(efx, ev_sub_data);
1232                 break;
1233         default:
1234                 netif_vdbg(efx, hw, efx->net_dev,
1235                            "channel %d unknown driver event code %d "
1236                            "data %04x\n", channel->channel, ev_sub_code,
1237                            ev_sub_data);
1238                 break;
1239         }
1240 }
1241
1242 int efx_farch_ev_process(struct efx_channel *channel, int budget)
1243 {
1244         struct efx_nic *efx = channel->efx;
1245         unsigned int read_ptr;
1246         efx_qword_t event, *p_event;
1247         int ev_code;
1248         int tx_packets = 0;
1249         int spent = 0;
1250
1251         if (budget <= 0)
1252                 return spent;
1253
1254         read_ptr = channel->eventq_read_ptr;
1255
1256         for (;;) {
1257                 p_event = efx_event(channel, read_ptr);
1258                 event = *p_event;
1259
1260                 if (!efx_event_present(&event))
1261                         /* End of events */
1262                         break;
1263
1264                 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1265                            "channel %d event is "EFX_QWORD_FMT"\n",
1266                            channel->channel, EFX_QWORD_VAL(event));
1267
1268                 /* Clear this event by marking it all ones */
1269                 EFX_SET_QWORD(*p_event);
1270
1271                 ++read_ptr;
1272
1273                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1274
1275                 switch (ev_code) {
1276                 case FSE_AZ_EV_CODE_RX_EV:
1277                         efx_farch_handle_rx_event(channel, &event);
1278                         if (++spent == budget)
1279                                 goto out;
1280                         break;
1281                 case FSE_AZ_EV_CODE_TX_EV:
1282                         tx_packets += efx_farch_handle_tx_event(channel,
1283                                                                 &event);
1284                         if (tx_packets > efx->txq_entries) {
1285                                 spent = budget;
1286                                 goto out;
1287                         }
1288                         break;
1289                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1290                         efx_farch_handle_generated_event(channel, &event);
1291                         break;
1292                 case FSE_AZ_EV_CODE_DRIVER_EV:
1293                         efx_farch_handle_driver_event(channel, &event);
1294                         break;
1295                 case FSE_CZ_EV_CODE_USER_EV:
1296                         efx_sriov_event(channel, &event);
1297                         break;
1298                 case FSE_CZ_EV_CODE_MCDI_EV:
1299                         efx_mcdi_process_event(channel, &event);
1300                         break;
1301                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1302                         if (efx->type->handle_global_event &&
1303                             efx->type->handle_global_event(channel, &event))
1304                                 break;
1305                         /* else fall through */
1306                 default:
1307                         netif_err(channel->efx, hw, channel->efx->net_dev,
1308                                   "channel %d unknown event type %d (data "
1309                                   EFX_QWORD_FMT ")\n", channel->channel,
1310                                   ev_code, EFX_QWORD_VAL(event));
1311                 }
1312         }
1313
1314 out:
1315         channel->eventq_read_ptr = read_ptr;
1316         return spent;
1317 }
1318
1319 /* Allocate buffer table entries for event queue */
1320 int efx_farch_ev_probe(struct efx_channel *channel)
1321 {
1322         struct efx_nic *efx = channel->efx;
1323         unsigned entries;
1324
1325         entries = channel->eventq_mask + 1;
1326         return efx_alloc_special_buffer(efx, &channel->eventq,
1327                                         entries * sizeof(efx_qword_t));
1328 }
1329
1330 int efx_farch_ev_init(struct efx_channel *channel)
1331 {
1332         efx_oword_t reg;
1333         struct efx_nic *efx = channel->efx;
1334
1335         netif_dbg(efx, hw, efx->net_dev,
1336                   "channel %d event queue in special buffers %d-%d\n",
1337                   channel->channel, channel->eventq.index,
1338                   channel->eventq.index + channel->eventq.entries - 1);
1339
1340         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1341                 EFX_POPULATE_OWORD_3(reg,
1342                                      FRF_CZ_TIMER_Q_EN, 1,
1343                                      FRF_CZ_HOST_NOTIFY_MODE, 0,
1344                                      FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1345                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1346         }
1347
1348         /* Pin event queue buffer */
1349         efx_init_special_buffer(efx, &channel->eventq);
1350
1351         /* Fill event queue with all ones (i.e. empty events) */
1352         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1353
1354         /* Push event queue to card */
1355         EFX_POPULATE_OWORD_3(reg,
1356                              FRF_AZ_EVQ_EN, 1,
1357                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1358                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1359         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1360                          channel->channel);
1361
1362         return 0;
1363 }
1364
1365 void efx_farch_ev_fini(struct efx_channel *channel)
1366 {
1367         efx_oword_t reg;
1368         struct efx_nic *efx = channel->efx;
1369
1370         /* Remove event queue from card */
1371         EFX_ZERO_OWORD(reg);
1372         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1373                          channel->channel);
1374         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1375                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1376
1377         /* Unpin event queue */
1378         efx_fini_special_buffer(efx, &channel->eventq);
1379 }
1380
1381 /* Free buffers backing event queue */
1382 void efx_farch_ev_remove(struct efx_channel *channel)
1383 {
1384         efx_free_special_buffer(channel->efx, &channel->eventq);
1385 }
1386
1387
1388 void efx_farch_ev_test_generate(struct efx_channel *channel)
1389 {
1390         efx_farch_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel));
1391 }
1392
1393 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue)
1394 {
1395         efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1396                               EFX_CHANNEL_MAGIC_FILL(rx_queue));
1397 }
1398
1399 /**************************************************************************
1400  *
1401  * Hardware interrupts
1402  * The hardware interrupt handler does very little work; all the event
1403  * queue processing is carried out by per-channel tasklets.
1404  *
1405  **************************************************************************/
1406
1407 /* Enable/disable/generate interrupts */
1408 static inline void efx_farch_interrupts(struct efx_nic *efx,
1409                                       bool enabled, bool force)
1410 {
1411         efx_oword_t int_en_reg_ker;
1412
1413         EFX_POPULATE_OWORD_3(int_en_reg_ker,
1414                              FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level,
1415                              FRF_AZ_KER_INT_KER, force,
1416                              FRF_AZ_DRV_INT_EN_KER, enabled);
1417         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1418 }
1419
1420 void efx_farch_irq_enable_master(struct efx_nic *efx)
1421 {
1422         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1423         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1424
1425         efx_farch_interrupts(efx, true, false);
1426 }
1427
1428 void efx_farch_irq_disable_master(struct efx_nic *efx)
1429 {
1430         /* Disable interrupts */
1431         efx_farch_interrupts(efx, false, false);
1432 }
1433
1434 /* Generate a test interrupt
1435  * Interrupt must already have been enabled, otherwise nasty things
1436  * may happen.
1437  */
1438 void efx_farch_irq_test_generate(struct efx_nic *efx)
1439 {
1440         efx_farch_interrupts(efx, true, true);
1441 }
1442
1443 /* Process a fatal interrupt
1444  * Disable bus mastering ASAP and schedule a reset
1445  */
1446 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx)
1447 {
1448         struct falcon_nic_data *nic_data = efx->nic_data;
1449         efx_oword_t *int_ker = efx->irq_status.addr;
1450         efx_oword_t fatal_intr;
1451         int error, mem_perr;
1452
1453         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1454         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1455
1456         netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1457                   EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1458                   EFX_OWORD_VAL(fatal_intr),
1459                   error ? "disabling bus mastering" : "no recognised error");
1460
1461         /* If this is a memory parity error dump which blocks are offending */
1462         mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1463                     EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1464         if (mem_perr) {
1465                 efx_oword_t reg;
1466                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1467                 netif_err(efx, hw, efx->net_dev,
1468                           "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1469                           EFX_OWORD_VAL(reg));
1470         }
1471
1472         /* Disable both devices */
1473         pci_clear_master(efx->pci_dev);
1474         if (efx_nic_is_dual_func(efx))
1475                 pci_clear_master(nic_data->pci_dev2);
1476         efx_farch_irq_disable_master(efx);
1477
1478         /* Count errors and reset or disable the NIC accordingly */
1479         if (efx->int_error_count == 0 ||
1480             time_after(jiffies, efx->int_error_expire)) {
1481                 efx->int_error_count = 0;
1482                 efx->int_error_expire =
1483                         jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1484         }
1485         if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1486                 netif_err(efx, hw, efx->net_dev,
1487                           "SYSTEM ERROR - reset scheduled\n");
1488                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1489         } else {
1490                 netif_err(efx, hw, efx->net_dev,
1491                           "SYSTEM ERROR - max number of errors seen."
1492                           "NIC will be disabled\n");
1493                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1494         }
1495
1496         return IRQ_HANDLED;
1497 }
1498
1499 /* Handle a legacy interrupt
1500  * Acknowledges the interrupt and schedule event queue processing.
1501  */
1502 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id)
1503 {
1504         struct efx_nic *efx = dev_id;
1505         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1506         efx_oword_t *int_ker = efx->irq_status.addr;
1507         irqreturn_t result = IRQ_NONE;
1508         struct efx_channel *channel;
1509         efx_dword_t reg;
1510         u32 queues;
1511         int syserr;
1512
1513         /* Read the ISR which also ACKs the interrupts */
1514         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1515         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1516
1517         /* Legacy interrupts are disabled too late by the EEH kernel
1518          * code. Disable them earlier.
1519          * If an EEH error occurred, the read will have returned all ones.
1520          */
1521         if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) &&
1522             !efx->eeh_disabled_legacy_irq) {
1523                 disable_irq_nosync(efx->legacy_irq);
1524                 efx->eeh_disabled_legacy_irq = true;
1525         }
1526
1527         /* Handle non-event-queue sources */
1528         if (queues & (1U << efx->irq_level) && soft_enabled) {
1529                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1530                 if (unlikely(syserr))
1531                         return efx_farch_fatal_interrupt(efx);
1532                 efx->last_irq_cpu = raw_smp_processor_id();
1533         }
1534
1535         if (queues != 0) {
1536                 efx->irq_zero_count = 0;
1537
1538                 /* Schedule processing of any interrupting queues */
1539                 if (likely(soft_enabled)) {
1540                         efx_for_each_channel(channel, efx) {
1541                                 if (queues & 1)
1542                                         efx_schedule_channel_irq(channel);
1543                                 queues >>= 1;
1544                         }
1545                 }
1546                 result = IRQ_HANDLED;
1547
1548         } else {
1549                 efx_qword_t *event;
1550
1551                 /* Legacy ISR read can return zero once (SF bug 15783) */
1552
1553                 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1554                  * because this might be a shared interrupt. */
1555                 if (efx->irq_zero_count++ == 0)
1556                         result = IRQ_HANDLED;
1557
1558                 /* Ensure we schedule or rearm all event queues */
1559                 if (likely(soft_enabled)) {
1560                         efx_for_each_channel(channel, efx) {
1561                                 event = efx_event(channel,
1562                                                   channel->eventq_read_ptr);
1563                                 if (efx_event_present(event))
1564                                         efx_schedule_channel_irq(channel);
1565                                 else
1566                                         efx_farch_ev_read_ack(channel);
1567                         }
1568                 }
1569         }
1570
1571         if (result == IRQ_HANDLED)
1572                 netif_vdbg(efx, intr, efx->net_dev,
1573                            "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1574                            irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1575
1576         return result;
1577 }
1578
1579 /* Handle an MSI interrupt
1580  *
1581  * Handle an MSI hardware interrupt.  This routine schedules event
1582  * queue processing.  No interrupt acknowledgement cycle is necessary.
1583  * Also, we never need to check that the interrupt is for us, since
1584  * MSI interrupts cannot be shared.
1585  */
1586 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id)
1587 {
1588         struct efx_msi_context *context = dev_id;
1589         struct efx_nic *efx = context->efx;
1590         efx_oword_t *int_ker = efx->irq_status.addr;
1591         int syserr;
1592
1593         netif_vdbg(efx, intr, efx->net_dev,
1594                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1595                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1596
1597         if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
1598                 return IRQ_HANDLED;
1599
1600         /* Handle non-event-queue sources */
1601         if (context->index == efx->irq_level) {
1602                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1603                 if (unlikely(syserr))
1604                         return efx_farch_fatal_interrupt(efx);
1605                 efx->last_irq_cpu = raw_smp_processor_id();
1606         }
1607
1608         /* Schedule processing of the channel */
1609         efx_schedule_channel_irq(efx->channel[context->index]);
1610
1611         return IRQ_HANDLED;
1612 }
1613
1614 /* Setup RSS indirection table.
1615  * This maps from the hash value of the packet to RXQ
1616  */
1617 void efx_farch_rx_push_indir_table(struct efx_nic *efx)
1618 {
1619         size_t i = 0;
1620         efx_dword_t dword;
1621
1622         BUG_ON(efx_nic_rev(efx) < EFX_REV_FALCON_B0);
1623
1624         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1625                      FR_BZ_RX_INDIRECTION_TBL_ROWS);
1626
1627         for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1628                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1629                                      efx->rx_indir_table[i]);
1630                 efx_writed(efx, &dword,
1631                            FR_BZ_RX_INDIRECTION_TBL +
1632                            FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1633         }
1634 }
1635
1636 /* Looks at available SRAM resources and works out how many queues we
1637  * can support, and where things like descriptor caches should live.
1638  *
1639  * SRAM is split up as follows:
1640  * 0                          buftbl entries for channels
1641  * efx->vf_buftbl_base        buftbl entries for SR-IOV
1642  * efx->rx_dc_base            RX descriptor caches
1643  * efx->tx_dc_base            TX descriptor caches
1644  */
1645 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1646 {
1647         unsigned vi_count, buftbl_min;
1648
1649         /* Account for the buffer table entries backing the datapath channels
1650          * and the descriptor caches for those channels.
1651          */
1652         buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1653                        efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1654                        efx->n_channels * EFX_MAX_EVQ_SIZE)
1655                       * sizeof(efx_qword_t) / EFX_BUF_SIZE);
1656         vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1657
1658 #ifdef CONFIG_SFC_SRIOV
1659         if (efx_sriov_wanted(efx)) {
1660                 unsigned vi_dc_entries, buftbl_free, entries_per_vf, vf_limit;
1661
1662                 efx->vf_buftbl_base = buftbl_min;
1663
1664                 vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES;
1665                 vi_count = max(vi_count, EFX_VI_BASE);
1666                 buftbl_free = (sram_lim_qw - buftbl_min -
1667                                vi_count * vi_dc_entries);
1668
1669                 entries_per_vf = ((vi_dc_entries + EFX_VF_BUFTBL_PER_VI) *
1670                                   efx_vf_size(efx));
1671                 vf_limit = min(buftbl_free / entries_per_vf,
1672                                (1024U - EFX_VI_BASE) >> efx->vi_scale);
1673
1674                 if (efx->vf_count > vf_limit) {
1675                         netif_err(efx, probe, efx->net_dev,
1676                                   "Reducing VF count from from %d to %d\n",
1677                                   efx->vf_count, vf_limit);
1678                         efx->vf_count = vf_limit;
1679                 }
1680                 vi_count += efx->vf_count * efx_vf_size(efx);
1681         }
1682 #endif
1683
1684         efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1685         efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1686 }
1687
1688 u32 efx_farch_fpga_ver(struct efx_nic *efx)
1689 {
1690         efx_oword_t altera_build;
1691         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1692         return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1693 }
1694
1695 void efx_farch_init_common(struct efx_nic *efx)
1696 {
1697         efx_oword_t temp;
1698
1699         /* Set positions of descriptor caches in SRAM. */
1700         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
1701         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1702         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
1703         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1704
1705         /* Set TX descriptor cache size. */
1706         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1707         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1708         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1709
1710         /* Set RX descriptor cache size.  Set low watermark to size-8, as
1711          * this allows most efficient prefetching.
1712          */
1713         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1714         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1715         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1716         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1717         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1718
1719         /* Program INT_KER address */
1720         EFX_POPULATE_OWORD_2(temp,
1721                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1722                              EFX_INT_MODE_USE_MSI(efx),
1723                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1724         efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1725
1726         if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1727                 /* Use an interrupt level unused by event queues */
1728                 efx->irq_level = 0x1f;
1729         else
1730                 /* Use a valid MSI-X vector */
1731                 efx->irq_level = 0;
1732
1733         /* Enable all the genuinely fatal interrupts.  (They are still
1734          * masked by the overall interrupt mask, controlled by
1735          * falcon_interrupts()).
1736          *
1737          * Note: All other fatal interrupts are enabled
1738          */
1739         EFX_POPULATE_OWORD_3(temp,
1740                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1741                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1742                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1743         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1744                 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1745         EFX_INVERT_OWORD(temp);
1746         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1747
1748         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1749          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1750          */
1751         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1752         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1753         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1754         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1755         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1756         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1757         /* Enable SW_EV to inherit in char driver - assume harmless here */
1758         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1759         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1760         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1761         /* Disable hardware watchdog which can misfire */
1762         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1763         /* Squash TX of packets of 16 bytes or less */
1764         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1765                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1766         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1767
1768         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1769                 EFX_POPULATE_OWORD_4(temp,
1770                                      /* Default values */
1771                                      FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1772                                      FRF_BZ_TX_PACE_SB_AF, 0xb,
1773                                      FRF_BZ_TX_PACE_FB_BASE, 0,
1774                                      /* Allow large pace values in the
1775                                       * fast bin. */
1776                                      FRF_BZ_TX_PACE_BIN_TH,
1777                                      FFE_BZ_TX_PACE_RESERVED);
1778                 efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1779         }
1780 }
1781
1782 /**************************************************************************
1783  *
1784  * Filter tables
1785  *
1786  **************************************************************************
1787  */
1788
1789 /* "Fudge factors" - difference between programmed value and actual depth.
1790  * Due to pipelined implementation we need to program H/W with a value that
1791  * is larger than the hop limit we want.
1792  */
1793 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD 3
1794 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL 1
1795
1796 /* Hard maximum search limit.  Hardware will time-out beyond 200-something.
1797  * We also need to avoid infinite loops in efx_farch_filter_search() when the
1798  * table is full.
1799  */
1800 #define EFX_FARCH_FILTER_CTL_SRCH_MAX 200
1801
1802 /* Don't try very hard to find space for performance hints, as this is
1803  * counter-productive. */
1804 #define EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX 5
1805
1806 enum efx_farch_filter_type {
1807         EFX_FARCH_FILTER_TCP_FULL = 0,
1808         EFX_FARCH_FILTER_TCP_WILD,
1809         EFX_FARCH_FILTER_UDP_FULL,
1810         EFX_FARCH_FILTER_UDP_WILD,
1811         EFX_FARCH_FILTER_MAC_FULL = 4,
1812         EFX_FARCH_FILTER_MAC_WILD,
1813         EFX_FARCH_FILTER_UC_DEF = 8,
1814         EFX_FARCH_FILTER_MC_DEF,
1815         EFX_FARCH_FILTER_TYPE_COUNT,            /* number of specific types */
1816 };
1817
1818 enum efx_farch_filter_table_id {
1819         EFX_FARCH_FILTER_TABLE_RX_IP = 0,
1820         EFX_FARCH_FILTER_TABLE_RX_MAC,
1821         EFX_FARCH_FILTER_TABLE_RX_DEF,
1822         EFX_FARCH_FILTER_TABLE_TX_MAC,
1823         EFX_FARCH_FILTER_TABLE_COUNT,
1824 };
1825
1826 enum efx_farch_filter_index {
1827         EFX_FARCH_FILTER_INDEX_UC_DEF,
1828         EFX_FARCH_FILTER_INDEX_MC_DEF,
1829         EFX_FARCH_FILTER_SIZE_RX_DEF,
1830 };
1831
1832 struct efx_farch_filter_spec {
1833         u8      type:4;
1834         u8      priority:4;
1835         u8      flags;
1836         u16     dmaq_id;
1837         u32     data[3];
1838 };
1839
1840 struct efx_farch_filter_table {
1841         enum efx_farch_filter_table_id id;
1842         u32             offset;         /* address of table relative to BAR */
1843         unsigned        size;           /* number of entries */
1844         unsigned        step;           /* step between entries */
1845         unsigned        used;           /* number currently used */
1846         unsigned long   *used_bitmap;
1847         struct efx_farch_filter_spec *spec;
1848         unsigned        search_limit[EFX_FARCH_FILTER_TYPE_COUNT];
1849 };
1850
1851 struct efx_farch_filter_state {
1852         struct efx_farch_filter_table table[EFX_FARCH_FILTER_TABLE_COUNT];
1853 };
1854
1855 static void
1856 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
1857                                    struct efx_farch_filter_table *table,
1858                                    unsigned int filter_idx);
1859
1860 /* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
1861  * key derived from the n-tuple.  The initial LFSR state is 0xffff. */
1862 static u16 efx_farch_filter_hash(u32 key)
1863 {
1864         u16 tmp;
1865
1866         /* First 16 rounds */
1867         tmp = 0x1fff ^ key >> 16;
1868         tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1869         tmp = tmp ^ tmp >> 9;
1870         /* Last 16 rounds */
1871         tmp = tmp ^ tmp << 13 ^ key;
1872         tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1873         return tmp ^ tmp >> 9;
1874 }
1875
1876 /* To allow for hash collisions, filter search continues at these
1877  * increments from the first possible entry selected by the hash. */
1878 static u16 efx_farch_filter_increment(u32 key)
1879 {
1880         return key * 2 - 1;
1881 }
1882
1883 static enum efx_farch_filter_table_id
1884 efx_farch_filter_spec_table_id(const struct efx_farch_filter_spec *spec)
1885 {
1886         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1887                      (EFX_FARCH_FILTER_TCP_FULL >> 2));
1888         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1889                      (EFX_FARCH_FILTER_TCP_WILD >> 2));
1890         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1891                      (EFX_FARCH_FILTER_UDP_FULL >> 2));
1892         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1893                      (EFX_FARCH_FILTER_UDP_WILD >> 2));
1894         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1895                      (EFX_FARCH_FILTER_MAC_FULL >> 2));
1896         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1897                      (EFX_FARCH_FILTER_MAC_WILD >> 2));
1898         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_TX_MAC !=
1899                      EFX_FARCH_FILTER_TABLE_RX_MAC + 2);
1900         return (spec->type >> 2) + ((spec->flags & EFX_FILTER_FLAG_TX) ? 2 : 0);
1901 }
1902
1903 static void efx_farch_filter_push_rx_config(struct efx_nic *efx)
1904 {
1905         struct efx_farch_filter_state *state = efx->filter_state;
1906         struct efx_farch_filter_table *table;
1907         efx_oword_t filter_ctl;
1908
1909         efx_reado(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1910
1911         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
1912         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_FULL_SRCH_LIMIT,
1913                             table->search_limit[EFX_FARCH_FILTER_TCP_FULL] +
1914                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1915         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_WILD_SRCH_LIMIT,
1916                             table->search_limit[EFX_FARCH_FILTER_TCP_WILD] +
1917                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1918         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_FULL_SRCH_LIMIT,
1919                             table->search_limit[EFX_FARCH_FILTER_UDP_FULL] +
1920                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1921         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_WILD_SRCH_LIMIT,
1922                             table->search_limit[EFX_FARCH_FILTER_UDP_WILD] +
1923                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1924
1925         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
1926         if (table->size) {
1927                 EFX_SET_OWORD_FIELD(
1928                         filter_ctl, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
1929                         table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
1930                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1931                 EFX_SET_OWORD_FIELD(
1932                         filter_ctl, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
1933                         table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
1934                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1935         }
1936
1937         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
1938         if (table->size) {
1939                 EFX_SET_OWORD_FIELD(
1940                         filter_ctl, FRF_CZ_UNICAST_NOMATCH_Q_ID,
1941                         table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].dmaq_id);
1942                 EFX_SET_OWORD_FIELD(
1943                         filter_ctl, FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED,
1944                         !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1945                            EFX_FILTER_FLAG_RX_RSS));
1946                 EFX_SET_OWORD_FIELD(
1947                         filter_ctl, FRF_CZ_MULTICAST_NOMATCH_Q_ID,
1948                         table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].dmaq_id);
1949                 EFX_SET_OWORD_FIELD(
1950                         filter_ctl, FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED,
1951                         !!(table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1952                            EFX_FILTER_FLAG_RX_RSS));
1953
1954                 /* There is a single bit to enable RX scatter for all
1955                  * unmatched packets.  Only set it if scatter is
1956                  * enabled in both filter specs.
1957                  */
1958                 EFX_SET_OWORD_FIELD(
1959                         filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1960                         !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1961                            table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1962                            EFX_FILTER_FLAG_RX_SCATTER));
1963         } else if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1964                 /* We don't expose 'default' filters because unmatched
1965                  * packets always go to the queue number found in the
1966                  * RSS table.  But we still need to set the RX scatter
1967                  * bit here.
1968                  */
1969                 EFX_SET_OWORD_FIELD(
1970                         filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1971                         efx->rx_scatter);
1972         }
1973
1974         efx_writeo(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1975 }
1976
1977 static void efx_farch_filter_push_tx_limits(struct efx_nic *efx)
1978 {
1979         struct efx_farch_filter_state *state = efx->filter_state;
1980         struct efx_farch_filter_table *table;
1981         efx_oword_t tx_cfg;
1982
1983         efx_reado(efx, &tx_cfg, FR_AZ_TX_CFG);
1984
1985         table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
1986         if (table->size) {
1987                 EFX_SET_OWORD_FIELD(
1988                         tx_cfg, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
1989                         table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
1990                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1991                 EFX_SET_OWORD_FIELD(
1992                         tx_cfg, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
1993                         table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
1994                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1995         }
1996
1997         efx_writeo(efx, &tx_cfg, FR_AZ_TX_CFG);
1998 }
1999
2000 static int
2001 efx_farch_filter_from_gen_spec(struct efx_farch_filter_spec *spec,
2002                                const struct efx_filter_spec *gen_spec)
2003 {
2004         bool is_full = false;
2005
2006         if ((gen_spec->flags & EFX_FILTER_FLAG_RX_RSS) &&
2007             gen_spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT)
2008                 return -EINVAL;
2009
2010         spec->priority = gen_spec->priority;
2011         spec->flags = gen_spec->flags;
2012         spec->dmaq_id = gen_spec->dmaq_id;
2013
2014         switch (gen_spec->match_flags) {
2015         case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2016               EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
2017               EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT):
2018                 is_full = true;
2019                 /* fall through */
2020         case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2021               EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT): {
2022                 __be32 rhost, host1, host2;
2023                 __be16 rport, port1, port2;
2024
2025                 EFX_BUG_ON_PARANOID(!(gen_spec->flags & EFX_FILTER_FLAG_RX));
2026
2027                 if (gen_spec->ether_type != htons(ETH_P_IP))
2028                         return -EPROTONOSUPPORT;
2029                 if (gen_spec->loc_port == 0 ||
2030                     (is_full && gen_spec->rem_port == 0))
2031                         return -EADDRNOTAVAIL;
2032                 switch (gen_spec->ip_proto) {
2033                 case IPPROTO_TCP:
2034                         spec->type = (is_full ? EFX_FARCH_FILTER_TCP_FULL :
2035                                       EFX_FARCH_FILTER_TCP_WILD);
2036                         break;
2037                 case IPPROTO_UDP:
2038                         spec->type = (is_full ? EFX_FARCH_FILTER_UDP_FULL :
2039                                       EFX_FARCH_FILTER_UDP_WILD);
2040                         break;
2041                 default:
2042                         return -EPROTONOSUPPORT;
2043                 }
2044
2045                 /* Filter is constructed in terms of source and destination,
2046                  * with the odd wrinkle that the ports are swapped in a UDP
2047                  * wildcard filter.  We need to convert from local and remote
2048                  * (= zero for wildcard) addresses.
2049                  */
2050                 rhost = is_full ? gen_spec->rem_host[0] : 0;
2051                 rport = is_full ? gen_spec->rem_port : 0;
2052                 host1 = rhost;
2053                 host2 = gen_spec->loc_host[0];
2054                 if (!is_full && gen_spec->ip_proto == IPPROTO_UDP) {
2055                         port1 = gen_spec->loc_port;
2056                         port2 = rport;
2057                 } else {
2058                         port1 = rport;
2059                         port2 = gen_spec->loc_port;
2060                 }
2061                 spec->data[0] = ntohl(host1) << 16 | ntohs(port1);
2062                 spec->data[1] = ntohs(port2) << 16 | ntohl(host1) >> 16;
2063                 spec->data[2] = ntohl(host2);
2064
2065                 break;
2066         }
2067
2068         case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
2069                 is_full = true;
2070                 /* fall through */
2071         case EFX_FILTER_MATCH_LOC_MAC:
2072                 spec->type = (is_full ? EFX_FARCH_FILTER_MAC_FULL :
2073                               EFX_FARCH_FILTER_MAC_WILD);
2074                 spec->data[0] = is_full ? ntohs(gen_spec->outer_vid) : 0;
2075                 spec->data[1] = (gen_spec->loc_mac[2] << 24 |
2076                                  gen_spec->loc_mac[3] << 16 |
2077                                  gen_spec->loc_mac[4] << 8 |
2078                                  gen_spec->loc_mac[5]);
2079                 spec->data[2] = (gen_spec->loc_mac[0] << 8 |
2080                                  gen_spec->loc_mac[1]);
2081                 break;
2082
2083         case EFX_FILTER_MATCH_LOC_MAC_IG:
2084                 spec->type = (is_multicast_ether_addr(gen_spec->loc_mac) ?
2085                               EFX_FARCH_FILTER_MC_DEF :
2086                               EFX_FARCH_FILTER_UC_DEF);
2087                 memset(spec->data, 0, sizeof(spec->data)); /* ensure equality */
2088                 break;
2089
2090         default:
2091                 return -EPROTONOSUPPORT;
2092         }
2093
2094         return 0;
2095 }
2096
2097 static void
2098 efx_farch_filter_to_gen_spec(struct efx_filter_spec *gen_spec,
2099                              const struct efx_farch_filter_spec *spec)
2100 {
2101         bool is_full = false;
2102
2103         /* *gen_spec should be completely initialised, to be consistent
2104          * with efx_filter_init_{rx,tx}() and in case we want to copy
2105          * it back to userland.
2106          */
2107         memset(gen_spec, 0, sizeof(*gen_spec));
2108
2109         gen_spec->priority = spec->priority;
2110         gen_spec->flags = spec->flags;
2111         gen_spec->dmaq_id = spec->dmaq_id;
2112
2113         switch (spec->type) {
2114         case EFX_FARCH_FILTER_TCP_FULL:
2115         case EFX_FARCH_FILTER_UDP_FULL:
2116                 is_full = true;
2117                 /* fall through */
2118         case EFX_FARCH_FILTER_TCP_WILD:
2119         case EFX_FARCH_FILTER_UDP_WILD: {
2120                 __be32 host1, host2;
2121                 __be16 port1, port2;
2122
2123                 gen_spec->match_flags =
2124                         EFX_FILTER_MATCH_ETHER_TYPE |
2125                         EFX_FILTER_MATCH_IP_PROTO |
2126                         EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
2127                 if (is_full)
2128                         gen_spec->match_flags |= (EFX_FILTER_MATCH_REM_HOST |
2129                                                   EFX_FILTER_MATCH_REM_PORT);
2130                 gen_spec->ether_type = htons(ETH_P_IP);
2131                 gen_spec->ip_proto =
2132                         (spec->type == EFX_FARCH_FILTER_TCP_FULL ||
2133                          spec->type == EFX_FARCH_FILTER_TCP_WILD) ?
2134                         IPPROTO_TCP : IPPROTO_UDP;
2135
2136                 host1 = htonl(spec->data[0] >> 16 | spec->data[1] << 16);
2137                 port1 = htons(spec->data[0]);
2138                 host2 = htonl(spec->data[2]);
2139                 port2 = htons(spec->data[1] >> 16);
2140                 if (spec->flags & EFX_FILTER_FLAG_TX) {
2141                         gen_spec->loc_host[0] = host1;
2142                         gen_spec->rem_host[0] = host2;
2143                 } else {
2144                         gen_spec->loc_host[0] = host2;
2145                         gen_spec->rem_host[0] = host1;
2146                 }
2147                 if (!!(gen_spec->flags & EFX_FILTER_FLAG_TX) ^
2148                     (!is_full && gen_spec->ip_proto == IPPROTO_UDP)) {
2149                         gen_spec->loc_port = port1;
2150                         gen_spec->rem_port = port2;
2151                 } else {
2152                         gen_spec->loc_port = port2;
2153                         gen_spec->rem_port = port1;
2154                 }
2155
2156                 break;
2157         }
2158
2159         case EFX_FARCH_FILTER_MAC_FULL:
2160                 is_full = true;
2161                 /* fall through */
2162         case EFX_FARCH_FILTER_MAC_WILD:
2163                 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC;
2164                 if (is_full)
2165                         gen_spec->match_flags |= EFX_FILTER_MATCH_OUTER_VID;
2166                 gen_spec->loc_mac[0] = spec->data[2] >> 8;
2167                 gen_spec->loc_mac[1] = spec->data[2];
2168                 gen_spec->loc_mac[2] = spec->data[1] >> 24;
2169                 gen_spec->loc_mac[3] = spec->data[1] >> 16;
2170                 gen_spec->loc_mac[4] = spec->data[1] >> 8;
2171                 gen_spec->loc_mac[5] = spec->data[1];
2172                 gen_spec->outer_vid = htons(spec->data[0]);
2173                 break;
2174
2175         case EFX_FARCH_FILTER_UC_DEF:
2176         case EFX_FARCH_FILTER_MC_DEF:
2177                 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC_IG;
2178                 gen_spec->loc_mac[0] = spec->type == EFX_FARCH_FILTER_MC_DEF;
2179                 break;
2180
2181         default:
2182                 WARN_ON(1);
2183                 break;
2184         }
2185 }
2186
2187 static void
2188 efx_farch_filter_init_rx_auto(struct efx_nic *efx,
2189                               struct efx_farch_filter_spec *spec)
2190 {
2191         /* If there's only one channel then disable RSS for non VF
2192          * traffic, thereby allowing VFs to use RSS when the PF can't.
2193          */
2194         spec->priority = EFX_FILTER_PRI_AUTO;
2195         spec->flags = (EFX_FILTER_FLAG_RX |
2196                        (efx->n_rx_channels > 1 ? EFX_FILTER_FLAG_RX_RSS : 0) |
2197                        (efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0));
2198         spec->dmaq_id = 0;
2199 }
2200
2201 /* Build a filter entry and return its n-tuple key. */
2202 static u32 efx_farch_filter_build(efx_oword_t *filter,
2203                                   struct efx_farch_filter_spec *spec)
2204 {
2205         u32 data3;
2206
2207         switch (efx_farch_filter_spec_table_id(spec)) {
2208         case EFX_FARCH_FILTER_TABLE_RX_IP: {
2209                 bool is_udp = (spec->type == EFX_FARCH_FILTER_UDP_FULL ||
2210                                spec->type == EFX_FARCH_FILTER_UDP_WILD);
2211                 EFX_POPULATE_OWORD_7(
2212                         *filter,
2213                         FRF_BZ_RSS_EN,
2214                         !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2215                         FRF_BZ_SCATTER_EN,
2216                         !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2217                         FRF_BZ_TCP_UDP, is_udp,
2218                         FRF_BZ_RXQ_ID, spec->dmaq_id,
2219                         EFX_DWORD_2, spec->data[2],
2220                         EFX_DWORD_1, spec->data[1],
2221                         EFX_DWORD_0, spec->data[0]);
2222                 data3 = is_udp;
2223                 break;
2224         }
2225
2226         case EFX_FARCH_FILTER_TABLE_RX_MAC: {
2227                 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2228                 EFX_POPULATE_OWORD_7(
2229                         *filter,
2230                         FRF_CZ_RMFT_RSS_EN,
2231                         !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2232                         FRF_CZ_RMFT_SCATTER_EN,
2233                         !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2234                         FRF_CZ_RMFT_RXQ_ID, spec->dmaq_id,
2235                         FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
2236                         FRF_CZ_RMFT_DEST_MAC_HI, spec->data[2],
2237                         FRF_CZ_RMFT_DEST_MAC_LO, spec->data[1],
2238                         FRF_CZ_RMFT_VLAN_ID, spec->data[0]);
2239                 data3 = is_wild;
2240                 break;
2241         }
2242
2243         case EFX_FARCH_FILTER_TABLE_TX_MAC: {
2244                 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2245                 EFX_POPULATE_OWORD_5(*filter,
2246                                      FRF_CZ_TMFT_TXQ_ID, spec->dmaq_id,
2247                                      FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
2248                                      FRF_CZ_TMFT_SRC_MAC_HI, spec->data[2],
2249                                      FRF_CZ_TMFT_SRC_MAC_LO, spec->data[1],
2250                                      FRF_CZ_TMFT_VLAN_ID, spec->data[0]);
2251                 data3 = is_wild | spec->dmaq_id << 1;
2252                 break;
2253         }
2254
2255         default:
2256                 BUG();
2257         }
2258
2259         return spec->data[0] ^ spec->data[1] ^ spec->data[2] ^ data3;
2260 }
2261
2262 static bool efx_farch_filter_equal(const struct efx_farch_filter_spec *left,
2263                                    const struct efx_farch_filter_spec *right)
2264 {
2265         if (left->type != right->type ||
2266             memcmp(left->data, right->data, sizeof(left->data)))
2267                 return false;
2268
2269         if (left->flags & EFX_FILTER_FLAG_TX &&
2270             left->dmaq_id != right->dmaq_id)
2271                 return false;
2272
2273         return true;
2274 }
2275
2276 /*
2277  * Construct/deconstruct external filter IDs.  At least the RX filter
2278  * IDs must be ordered by matching priority, for RX NFC semantics.
2279  *
2280  * Deconstruction needs to be robust against invalid IDs so that
2281  * efx_filter_remove_id_safe() and efx_filter_get_filter_safe() can
2282  * accept user-provided IDs.
2283  */
2284
2285 #define EFX_FARCH_FILTER_MATCH_PRI_COUNT        5
2286
2287 static const u8 efx_farch_filter_type_match_pri[EFX_FARCH_FILTER_TYPE_COUNT] = {
2288         [EFX_FARCH_FILTER_TCP_FULL]     = 0,
2289         [EFX_FARCH_FILTER_UDP_FULL]     = 0,
2290         [EFX_FARCH_FILTER_TCP_WILD]     = 1,
2291         [EFX_FARCH_FILTER_UDP_WILD]     = 1,
2292         [EFX_FARCH_FILTER_MAC_FULL]     = 2,
2293         [EFX_FARCH_FILTER_MAC_WILD]     = 3,
2294         [EFX_FARCH_FILTER_UC_DEF]       = 4,
2295         [EFX_FARCH_FILTER_MC_DEF]       = 4,
2296 };
2297
2298 static const enum efx_farch_filter_table_id efx_farch_filter_range_table[] = {
2299         EFX_FARCH_FILTER_TABLE_RX_IP,   /* RX match pri 0 */
2300         EFX_FARCH_FILTER_TABLE_RX_IP,
2301         EFX_FARCH_FILTER_TABLE_RX_MAC,
2302         EFX_FARCH_FILTER_TABLE_RX_MAC,
2303         EFX_FARCH_FILTER_TABLE_RX_DEF,  /* RX match pri 4 */
2304         EFX_FARCH_FILTER_TABLE_TX_MAC,  /* TX match pri 0 */
2305         EFX_FARCH_FILTER_TABLE_TX_MAC,  /* TX match pri 1 */
2306 };
2307
2308 #define EFX_FARCH_FILTER_INDEX_WIDTH 13
2309 #define EFX_FARCH_FILTER_INDEX_MASK ((1 << EFX_FARCH_FILTER_INDEX_WIDTH) - 1)
2310
2311 static inline u32
2312 efx_farch_filter_make_id(const struct efx_farch_filter_spec *spec,
2313                          unsigned int index)
2314 {
2315         unsigned int range;
2316
2317         range = efx_farch_filter_type_match_pri[spec->type];
2318         if (!(spec->flags & EFX_FILTER_FLAG_RX))
2319                 range += EFX_FARCH_FILTER_MATCH_PRI_COUNT;
2320
2321         return range << EFX_FARCH_FILTER_INDEX_WIDTH | index;
2322 }
2323
2324 static inline enum efx_farch_filter_table_id
2325 efx_farch_filter_id_table_id(u32 id)
2326 {
2327         unsigned int range = id >> EFX_FARCH_FILTER_INDEX_WIDTH;
2328
2329         if (range < ARRAY_SIZE(efx_farch_filter_range_table))
2330                 return efx_farch_filter_range_table[range];
2331         else
2332                 return EFX_FARCH_FILTER_TABLE_COUNT; /* invalid */
2333 }
2334
2335 static inline unsigned int efx_farch_filter_id_index(u32 id)
2336 {
2337         return id & EFX_FARCH_FILTER_INDEX_MASK;
2338 }
2339
2340 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx)
2341 {
2342         struct efx_farch_filter_state *state = efx->filter_state;
2343         unsigned int range = EFX_FARCH_FILTER_MATCH_PRI_COUNT - 1;
2344         enum efx_farch_filter_table_id table_id;
2345
2346         do {
2347                 table_id = efx_farch_filter_range_table[range];
2348                 if (state->table[table_id].size != 0)
2349                         return range << EFX_FARCH_FILTER_INDEX_WIDTH |
2350                                 state->table[table_id].size;
2351         } while (range--);
2352
2353         return 0;
2354 }
2355
2356 s32 efx_farch_filter_insert(struct efx_nic *efx,
2357                             struct efx_filter_spec *gen_spec,
2358                             bool replace_equal)
2359 {
2360         struct efx_farch_filter_state *state = efx->filter_state;
2361         struct efx_farch_filter_table *table;
2362         struct efx_farch_filter_spec spec;
2363         efx_oword_t filter;
2364         int rep_index, ins_index;
2365         unsigned int depth = 0;
2366         int rc;
2367
2368         rc = efx_farch_filter_from_gen_spec(&spec, gen_spec);
2369         if (rc)
2370                 return rc;
2371
2372         table = &state->table[efx_farch_filter_spec_table_id(&spec)];
2373         if (table->size == 0)
2374                 return -EINVAL;
2375
2376         netif_vdbg(efx, hw, efx->net_dev,
2377                    "%s: type %d search_limit=%d", __func__, spec.type,
2378                    table->search_limit[spec.type]);
2379
2380         if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2381                 /* One filter spec per type */
2382                 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_UC_DEF != 0);
2383                 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_MC_DEF !=
2384                              EFX_FARCH_FILTER_MC_DEF - EFX_FARCH_FILTER_UC_DEF);
2385                 rep_index = spec.type - EFX_FARCH_FILTER_UC_DEF;
2386                 ins_index = rep_index;
2387
2388                 spin_lock_bh(&efx->filter_lock);
2389         } else {
2390                 /* Search concurrently for
2391                  * (1) a filter to be replaced (rep_index): any filter
2392                  *     with the same match values, up to the current
2393                  *     search depth for this type, and
2394                  * (2) the insertion point (ins_index): (1) or any
2395                  *     free slot before it or up to the maximum search
2396                  *     depth for this priority
2397                  * We fail if we cannot find (2).
2398                  *
2399                  * We can stop once either
2400                  * (a) we find (1), in which case we have definitely
2401                  *     found (2) as well; or
2402                  * (b) we have searched exhaustively for (1), and have
2403                  *     either found (2) or searched exhaustively for it
2404                  */
2405                 u32 key = efx_farch_filter_build(&filter, &spec);
2406                 unsigned int hash = efx_farch_filter_hash(key);
2407                 unsigned int incr = efx_farch_filter_increment(key);
2408                 unsigned int max_rep_depth = table->search_limit[spec.type];
2409                 unsigned int max_ins_depth =
2410                         spec.priority <= EFX_FILTER_PRI_HINT ?
2411                         EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX :
2412                         EFX_FARCH_FILTER_CTL_SRCH_MAX;
2413                 unsigned int i = hash & (table->size - 1);
2414
2415                 ins_index = -1;
2416                 depth = 1;
2417
2418                 spin_lock_bh(&efx->filter_lock);
2419
2420                 for (;;) {
2421                         if (!test_bit(i, table->used_bitmap)) {
2422                                 if (ins_index < 0)
2423                                         ins_index = i;
2424                         } else if (efx_farch_filter_equal(&spec,
2425                                                           &table->spec[i])) {
2426                                 /* Case (a) */
2427                                 if (ins_index < 0)
2428                                         ins_index = i;
2429                                 rep_index = i;
2430                                 break;
2431                         }
2432
2433                         if (depth >= max_rep_depth &&
2434                             (ins_index >= 0 || depth >= max_ins_depth)) {
2435                                 /* Case (b) */
2436                                 if (ins_index < 0) {
2437                                         rc = -EBUSY;
2438                                         goto out;
2439                                 }
2440                                 rep_index = -1;
2441                                 break;
2442                         }
2443
2444                         i = (i + incr) & (table->size - 1);
2445                         ++depth;
2446                 }
2447         }
2448
2449         /* If we found a filter to be replaced, check whether we
2450          * should do so
2451          */
2452         if (rep_index >= 0) {
2453                 struct efx_farch_filter_spec *saved_spec =
2454                         &table->spec[rep_index];
2455
2456                 if (spec.priority == saved_spec->priority && !replace_equal) {
2457                         rc = -EEXIST;
2458                         goto out;
2459                 }
2460                 if (spec.priority < saved_spec->priority) {
2461                         rc = -EPERM;
2462                         goto out;
2463                 }
2464                 if (saved_spec->priority == EFX_FILTER_PRI_AUTO ||
2465                     saved_spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO)
2466                         spec.flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2467         }
2468
2469         /* Insert the filter */
2470         if (ins_index != rep_index) {
2471                 __set_bit(ins_index, table->used_bitmap);
2472                 ++table->used;
2473         }
2474         table->spec[ins_index] = spec;
2475
2476         if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2477                 efx_farch_filter_push_rx_config(efx);
2478         } else {
2479                 if (table->search_limit[spec.type] < depth) {
2480                         table->search_limit[spec.type] = depth;
2481                         if (spec.flags & EFX_FILTER_FLAG_TX)
2482                                 efx_farch_filter_push_tx_limits(efx);
2483                         else
2484                                 efx_farch_filter_push_rx_config(efx);
2485                 }
2486
2487                 efx_writeo(efx, &filter,
2488                            table->offset + table->step * ins_index);
2489
2490                 /* If we were able to replace a filter by inserting
2491                  * at a lower depth, clear the replaced filter
2492                  */
2493                 if (ins_index != rep_index && rep_index >= 0)
2494                         efx_farch_filter_table_clear_entry(efx, table,
2495                                                            rep_index);
2496         }
2497
2498         netif_vdbg(efx, hw, efx->net_dev,
2499                    "%s: filter type %d index %d rxq %u set",
2500                    __func__, spec.type, ins_index, spec.dmaq_id);
2501         rc = efx_farch_filter_make_id(&spec, ins_index);
2502
2503 out:
2504         spin_unlock_bh(&efx->filter_lock);
2505         return rc;
2506 }
2507
2508 static void
2509 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
2510                                    struct efx_farch_filter_table *table,
2511                                    unsigned int filter_idx)
2512 {
2513         static efx_oword_t filter;
2514
2515         EFX_WARN_ON_PARANOID(!test_bit(filter_idx, table->used_bitmap));
2516         BUG_ON(table->offset == 0); /* can't clear MAC default filters */
2517
2518         __clear_bit(filter_idx, table->used_bitmap);
2519         --table->used;
2520         memset(&table->spec[filter_idx], 0, sizeof(table->spec[0]));
2521
2522         efx_writeo(efx, &filter, table->offset + table->step * filter_idx);
2523
2524         /* If this filter required a greater search depth than
2525          * any other, the search limit for its type can now be
2526          * decreased.  However, it is hard to determine that
2527          * unless the table has become completely empty - in
2528          * which case, all its search limits can be set to 0.
2529          */
2530         if (unlikely(table->used == 0)) {
2531                 memset(table->search_limit, 0, sizeof(table->search_limit));
2532                 if (table->id == EFX_FARCH_FILTER_TABLE_TX_MAC)
2533                         efx_farch_filter_push_tx_limits(efx);
2534                 else
2535                         efx_farch_filter_push_rx_config(efx);
2536         }
2537 }
2538
2539 static int efx_farch_filter_remove(struct efx_nic *efx,
2540                                    struct efx_farch_filter_table *table,
2541                                    unsigned int filter_idx,
2542                                    enum efx_filter_priority priority)
2543 {
2544         struct efx_farch_filter_spec *spec = &table->spec[filter_idx];
2545
2546         if (!test_bit(filter_idx, table->used_bitmap) ||
2547             spec->priority != priority)
2548                 return -ENOENT;
2549
2550         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2551                 efx_farch_filter_init_rx_auto(efx, spec);
2552                 efx_farch_filter_push_rx_config(efx);
2553         } else {
2554                 efx_farch_filter_table_clear_entry(efx, table, filter_idx);
2555         }
2556
2557         return 0;
2558 }
2559
2560 int efx_farch_filter_remove_safe(struct efx_nic *efx,
2561                                  enum efx_filter_priority priority,
2562                                  u32 filter_id)
2563 {
2564         struct efx_farch_filter_state *state = efx->filter_state;
2565         enum efx_farch_filter_table_id table_id;
2566         struct efx_farch_filter_table *table;
2567         unsigned int filter_idx;
2568         struct efx_farch_filter_spec *spec;
2569         int rc;
2570
2571         table_id = efx_farch_filter_id_table_id(filter_id);
2572         if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2573                 return -ENOENT;
2574         table = &state->table[table_id];
2575
2576         filter_idx = efx_farch_filter_id_index(filter_id);
2577         if (filter_idx >= table->size)
2578                 return -ENOENT;
2579         spec = &table->spec[filter_idx];
2580
2581         spin_lock_bh(&efx->filter_lock);
2582         rc = efx_farch_filter_remove(efx, table, filter_idx, priority);
2583         spin_unlock_bh(&efx->filter_lock);
2584
2585         return rc;
2586 }
2587
2588 int efx_farch_filter_get_safe(struct efx_nic *efx,
2589                               enum efx_filter_priority priority,
2590                               u32 filter_id, struct efx_filter_spec *spec_buf)
2591 {
2592         struct efx_farch_filter_state *state = efx->filter_state;
2593         enum efx_farch_filter_table_id table_id;
2594         struct efx_farch_filter_table *table;
2595         struct efx_farch_filter_spec *spec;
2596         unsigned int filter_idx;
2597         int rc;
2598
2599         table_id = efx_farch_filter_id_table_id(filter_id);
2600         if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2601                 return -ENOENT;
2602         table = &state->table[table_id];
2603
2604         filter_idx = efx_farch_filter_id_index(filter_id);
2605         if (filter_idx >= table->size)
2606                 return -ENOENT;
2607         spec = &table->spec[filter_idx];
2608
2609         spin_lock_bh(&efx->filter_lock);
2610
2611         if (test_bit(filter_idx, table->used_bitmap) &&
2612             spec->priority == priority) {
2613                 efx_farch_filter_to_gen_spec(spec_buf, spec);
2614                 rc = 0;
2615         } else {
2616                 rc = -ENOENT;
2617         }
2618
2619         spin_unlock_bh(&efx->filter_lock);
2620
2621         return rc;
2622 }
2623
2624 static void
2625 efx_farch_filter_table_clear(struct efx_nic *efx,
2626                              enum efx_farch_filter_table_id table_id,
2627                              enum efx_filter_priority priority)
2628 {
2629         struct efx_farch_filter_state *state = efx->filter_state;
2630         struct efx_farch_filter_table *table = &state->table[table_id];
2631         unsigned int filter_idx;
2632
2633         spin_lock_bh(&efx->filter_lock);
2634         for (filter_idx = 0; filter_idx < table->size; ++filter_idx) {
2635                 if (table->spec[filter_idx].priority != EFX_FILTER_PRI_AUTO)
2636                         efx_farch_filter_remove(efx, table,
2637                                                 filter_idx, priority);
2638         }
2639         spin_unlock_bh(&efx->filter_lock);
2640 }
2641
2642 int efx_farch_filter_clear_rx(struct efx_nic *efx,
2643                                enum efx_filter_priority priority)
2644 {
2645         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_IP,
2646                                      priority);
2647         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_MAC,
2648                                      priority);
2649         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_DEF,
2650                                      priority);
2651         return 0;
2652 }
2653
2654 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
2655                                    enum efx_filter_priority priority)
2656 {
2657         struct efx_farch_filter_state *state = efx->filter_state;
2658         enum efx_farch_filter_table_id table_id;
2659         struct efx_farch_filter_table *table;
2660         unsigned int filter_idx;
2661         u32 count = 0;
2662
2663         spin_lock_bh(&efx->filter_lock);
2664
2665         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2666              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2667              table_id++) {
2668                 table = &state->table[table_id];
2669                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2670                         if (test_bit(filter_idx, table->used_bitmap) &&
2671                             table->spec[filter_idx].priority == priority)
2672                                 ++count;
2673                 }
2674         }
2675
2676         spin_unlock_bh(&efx->filter_lock);
2677
2678         return count;
2679 }
2680
2681 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
2682                                 enum efx_filter_priority priority,
2683                                 u32 *buf, u32 size)
2684 {
2685         struct efx_farch_filter_state *state = efx->filter_state;
2686         enum efx_farch_filter_table_id table_id;
2687         struct efx_farch_filter_table *table;
2688         unsigned int filter_idx;
2689         s32 count = 0;
2690
2691         spin_lock_bh(&efx->filter_lock);
2692
2693         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2694              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2695              table_id++) {
2696                 table = &state->table[table_id];
2697                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2698                         if (test_bit(filter_idx, table->used_bitmap) &&
2699                             table->spec[filter_idx].priority == priority) {
2700                                 if (count == size) {
2701                                         count = -EMSGSIZE;
2702                                         goto out;
2703                                 }
2704                                 buf[count++] = efx_farch_filter_make_id(
2705                                         &table->spec[filter_idx], filter_idx);
2706                         }
2707                 }
2708         }
2709 out:
2710         spin_unlock_bh(&efx->filter_lock);
2711
2712         return count;
2713 }
2714
2715 /* Restore filter stater after reset */
2716 void efx_farch_filter_table_restore(struct efx_nic *efx)
2717 {
2718         struct efx_farch_filter_state *state = efx->filter_state;
2719         enum efx_farch_filter_table_id table_id;
2720         struct efx_farch_filter_table *table;
2721         efx_oword_t filter;
2722         unsigned int filter_idx;
2723
2724         spin_lock_bh(&efx->filter_lock);
2725
2726         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2727                 table = &state->table[table_id];
2728
2729                 /* Check whether this is a regular register table */
2730                 if (table->step == 0)
2731                         continue;
2732
2733                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2734                         if (!test_bit(filter_idx, table->used_bitmap))
2735                                 continue;
2736                         efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2737                         efx_writeo(efx, &filter,
2738                                    table->offset + table->step * filter_idx);
2739                 }
2740         }
2741
2742         efx_farch_filter_push_rx_config(efx);
2743         efx_farch_filter_push_tx_limits(efx);
2744
2745         spin_unlock_bh(&efx->filter_lock);
2746 }
2747
2748 void efx_farch_filter_table_remove(struct efx_nic *efx)
2749 {
2750         struct efx_farch_filter_state *state = efx->filter_state;
2751         enum efx_farch_filter_table_id table_id;
2752
2753         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2754                 kfree(state->table[table_id].used_bitmap);
2755                 vfree(state->table[table_id].spec);
2756         }
2757         kfree(state);
2758 }
2759
2760 int efx_farch_filter_table_probe(struct efx_nic *efx)
2761 {
2762         struct efx_farch_filter_state *state;
2763         struct efx_farch_filter_table *table;
2764         unsigned table_id;
2765
2766         state = kzalloc(sizeof(struct efx_farch_filter_state), GFP_KERNEL);
2767         if (!state)
2768                 return -ENOMEM;
2769         efx->filter_state = state;
2770
2771         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2772                 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2773                 table->id = EFX_FARCH_FILTER_TABLE_RX_IP;
2774                 table->offset = FR_BZ_RX_FILTER_TBL0;
2775                 table->size = FR_BZ_RX_FILTER_TBL0_ROWS;
2776                 table->step = FR_BZ_RX_FILTER_TBL0_STEP;
2777         }
2778
2779         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
2780                 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
2781                 table->id = EFX_FARCH_FILTER_TABLE_RX_MAC;
2782                 table->offset = FR_CZ_RX_MAC_FILTER_TBL0;
2783                 table->size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
2784                 table->step = FR_CZ_RX_MAC_FILTER_TBL0_STEP;
2785
2786                 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2787                 table->id = EFX_FARCH_FILTER_TABLE_RX_DEF;
2788                 table->size = EFX_FARCH_FILTER_SIZE_RX_DEF;
2789
2790                 table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2791                 table->id = EFX_FARCH_FILTER_TABLE_TX_MAC;
2792                 table->offset = FR_CZ_TX_MAC_FILTER_TBL0;
2793                 table->size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
2794                 table->step = FR_CZ_TX_MAC_FILTER_TBL0_STEP;
2795         }
2796
2797         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2798                 table = &state->table[table_id];
2799                 if (table->size == 0)
2800                         continue;
2801                 table->used_bitmap = kcalloc(BITS_TO_LONGS(table->size),
2802                                              sizeof(unsigned long),
2803                                              GFP_KERNEL);
2804                 if (!table->used_bitmap)
2805                         goto fail;
2806                 table->spec = vzalloc(table->size * sizeof(*table->spec));
2807                 if (!table->spec)
2808                         goto fail;
2809         }
2810
2811         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2812         if (table->size) {
2813                 /* RX default filters must always exist */
2814                 struct efx_farch_filter_spec *spec;
2815                 unsigned i;
2816
2817                 for (i = 0; i < EFX_FARCH_FILTER_SIZE_RX_DEF; i++) {
2818                         spec = &table->spec[i];
2819                         spec->type = EFX_FARCH_FILTER_UC_DEF + i;
2820                         efx_farch_filter_init_rx_auto(efx, spec);
2821                         __set_bit(i, table->used_bitmap);
2822                 }
2823         }
2824
2825         efx_farch_filter_push_rx_config(efx);
2826
2827         return 0;
2828
2829 fail:
2830         efx_farch_filter_table_remove(efx);
2831         return -ENOMEM;
2832 }
2833
2834 /* Update scatter enable flags for filters pointing to our own RX queues */
2835 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx)
2836 {
2837         struct efx_farch_filter_state *state = efx->filter_state;
2838         enum efx_farch_filter_table_id table_id;
2839         struct efx_farch_filter_table *table;
2840         efx_oword_t filter;
2841         unsigned int filter_idx;
2842
2843         spin_lock_bh(&efx->filter_lock);
2844
2845         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2846              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2847              table_id++) {
2848                 table = &state->table[table_id];
2849
2850                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2851                         if (!test_bit(filter_idx, table->used_bitmap) ||
2852                             table->spec[filter_idx].dmaq_id >=
2853                             efx->n_rx_channels)
2854                                 continue;
2855
2856                         if (efx->rx_scatter)
2857                                 table->spec[filter_idx].flags |=
2858                                         EFX_FILTER_FLAG_RX_SCATTER;
2859                         else
2860                                 table->spec[filter_idx].flags &=
2861                                         ~EFX_FILTER_FLAG_RX_SCATTER;
2862
2863                         if (table_id == EFX_FARCH_FILTER_TABLE_RX_DEF)
2864                                 /* Pushed by efx_farch_filter_push_rx_config() */
2865                                 continue;
2866
2867                         efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2868                         efx_writeo(efx, &filter,
2869                                    table->offset + table->step * filter_idx);
2870                 }
2871         }
2872
2873         efx_farch_filter_push_rx_config(efx);
2874
2875         spin_unlock_bh(&efx->filter_lock);
2876 }
2877
2878 #ifdef CONFIG_RFS_ACCEL
2879
2880 s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
2881                                 struct efx_filter_spec *gen_spec)
2882 {
2883         return efx_farch_filter_insert(efx, gen_spec, true);
2884 }
2885
2886 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2887                                      unsigned int index)
2888 {
2889         struct efx_farch_filter_state *state = efx->filter_state;
2890         struct efx_farch_filter_table *table =
2891                 &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2892
2893         if (test_bit(index, table->used_bitmap) &&
2894             table->spec[index].priority == EFX_FILTER_PRI_HINT &&
2895             rps_may_expire_flow(efx->net_dev, table->spec[index].dmaq_id,
2896                                 flow_id, index)) {
2897                 efx_farch_filter_table_clear_entry(efx, table, index);
2898                 return true;
2899         }
2900
2901         return false;
2902 }
2903
2904 #endif /* CONFIG_RFS_ACCEL */
2905
2906 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx)
2907 {
2908         struct net_device *net_dev = efx->net_dev;
2909         struct netdev_hw_addr *ha;
2910         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2911         u32 crc;
2912         int bit;
2913
2914         netif_addr_lock_bh(net_dev);
2915
2916         efx->unicast_filter = !(net_dev->flags & IFF_PROMISC);
2917
2918         /* Build multicast hash table */
2919         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2920                 memset(mc_hash, 0xff, sizeof(*mc_hash));
2921         } else {
2922                 memset(mc_hash, 0x00, sizeof(*mc_hash));
2923                 netdev_for_each_mc_addr(ha, net_dev) {
2924                         crc = ether_crc_le(ETH_ALEN, ha->addr);
2925                         bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
2926                         __set_bit_le(bit, mc_hash);
2927                 }
2928
2929                 /* Broadcast packets go through the multicast hash filter.
2930                  * ether_crc_le() of the broadcast address is 0xbe2612ff
2931                  * so we always add bit 0xff to the mask.
2932                  */
2933                 __set_bit_le(0xff, mc_hash);
2934         }
2935
2936         netif_addr_unlock_bh(net_dev);
2937 }