3 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
5 * Copyright (C) 1996 by Erik Stahlman
6 * Copyright (C) 2001 Standard Microsystems Corporation
7 * Developed by Simple Network Magic Corporation
8 * Copyright (C) 2003 Monta Vista Software, Inc.
9 * Unified SMC91x driver by Nicolas Pitre
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
25 * io = for the base address
27 * nowait = 0 for normal wait states, 1 eliminates additional wait states
30 * Erik Stahlman <erik@vt.edu>
32 * hardware multicast code:
33 * Peter Cammaert <pc@denkart.be>
36 * Daris A Nevil <dnevil@snmc.com>
37 * Nicolas Pitre <nico@fluxnic.net>
38 * Russell King <rmk@arm.linux.org.uk>
41 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
42 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
43 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111
44 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111
45 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111
46 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support
47 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races,
48 * more bus abstraction, big cleanup, etc.
49 * 29/09/03 Russell King - add driver model support
51 * - convert to use generic MII interface
52 * - add link up/down notification
53 * - don't try to handle full negotiation in
55 * - clean up (and fix stack overrun) in PHY
56 * MII read/write functions
57 * 22/09/04 Nicolas Pitre big update (see commit log for details)
59 static const char version[] =
60 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>";
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/sched.h>
71 #include <linux/delay.h>
72 #include <linux/interrupt.h>
73 #include <linux/irq.h>
74 #include <linux/errno.h>
75 #include <linux/ioport.h>
76 #include <linux/crc32.h>
77 #include <linux/platform_device.h>
78 #include <linux/spinlock.h>
79 #include <linux/ethtool.h>
80 #include <linux/mii.h>
81 #include <linux/workqueue.h>
83 #include <linux/of_device.h>
84 #include <linux/of_gpio.h>
86 #include <linux/netdevice.h>
87 #include <linux/etherdevice.h>
88 #include <linux/skbuff.h>
94 #if defined(CONFIG_ASSABET_NEPONSET)
95 #include <mach/neponset.h>
101 static int nowait = SMC_NOWAIT;
102 module_param(nowait, int, 0400);
103 MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
106 * Transmit timeout, default 5 seconds.
108 static int watchdog = 1000;
109 module_param(watchdog, int, 0400);
110 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
112 MODULE_LICENSE("GPL");
113 MODULE_ALIAS("platform:smc91x");
116 * The internal workings of the driver. If you are changing anything
117 * here with the SMC stuff, you should have the datasheet and know
118 * what you are doing.
120 #define CARDNAME "smc91x"
123 * Use power-down feature of the chip
128 * Wait time for memory to be free. This probably shouldn't be
129 * tuned that much, as waiting for this means nothing else happens
132 #define MEMORY_WAIT_TIME 16
135 * The maximum number of processing loops allowed for each call to the
138 #define MAX_IRQ_LOOPS 8
141 * This selects whether TX packets are sent one by one to the SMC91x internal
142 * memory and throttled until transmission completes. This may prevent
143 * RX overruns a litle by keeping much of the memory free for RX packets
144 * but to the expense of reduced TX throughput and increased IRQ overhead.
145 * Note this is not a cure for a too slow data bus or too high IRQ latency.
147 #define THROTTLE_TX_PKTS 0
150 * The MII clock high/low times. 2x this number gives the MII clock period
151 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!)
155 #define DBG(n, dev, fmt, ...) \
157 if (SMC_DEBUG >= (n)) \
158 netdev_dbg(dev, fmt, ##__VA_ARGS__); \
161 #define PRINTK(dev, fmt, ...) \
164 netdev_info(dev, fmt, ##__VA_ARGS__); \
166 netdev_dbg(dev, fmt, ##__VA_ARGS__); \
170 static void PRINT_PKT(u_char *buf, int length)
177 remainder = length % 16;
179 for (i = 0; i < lines ; i ++) {
182 for (cur = 0; cur < 8; cur++) {
186 pr_cont("%02x%02x ", a, b);
191 for (i = 0; i < remainder/2 ; i++) {
195 pr_cont("%02x%02x ", a, b);
200 static inline void PRINT_PKT(u_char *buf, int length) { }
204 /* this enables an interrupt in the interrupt mask register */
205 #define SMC_ENABLE_INT(lp, x) do { \
206 unsigned char mask; \
207 unsigned long smc_enable_flags; \
208 spin_lock_irqsave(&lp->lock, smc_enable_flags); \
209 mask = SMC_GET_INT_MASK(lp); \
211 SMC_SET_INT_MASK(lp, mask); \
212 spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \
215 /* this disables an interrupt from the interrupt mask register */
216 #define SMC_DISABLE_INT(lp, x) do { \
217 unsigned char mask; \
218 unsigned long smc_disable_flags; \
219 spin_lock_irqsave(&lp->lock, smc_disable_flags); \
220 mask = SMC_GET_INT_MASK(lp); \
222 SMC_SET_INT_MASK(lp, mask); \
223 spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \
227 * Wait while MMU is busy. This is usually in the order of a few nanosecs
228 * if at all, but let's avoid deadlocking the system if the hardware
229 * decides to go south.
231 #define SMC_WAIT_MMU_BUSY(lp) do { \
232 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \
233 unsigned long timeout = jiffies + 2; \
234 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \
235 if (time_after(jiffies, timeout)) { \
236 netdev_dbg(dev, "timeout %s line %d\n", \
237 __FILE__, __LINE__); \
247 * this does a soft reset on the device
249 static void smc_reset(struct net_device *dev)
251 struct smc_local *lp = netdev_priv(dev);
252 void __iomem *ioaddr = lp->base;
253 unsigned int ctl, cfg;
254 struct sk_buff *pending_skb;
256 DBG(2, dev, "%s\n", __func__);
258 /* Disable all interrupts, block TX tasklet */
259 spin_lock_irq(&lp->lock);
260 SMC_SELECT_BANK(lp, 2);
261 SMC_SET_INT_MASK(lp, 0);
262 pending_skb = lp->pending_tx_skb;
263 lp->pending_tx_skb = NULL;
264 spin_unlock_irq(&lp->lock);
266 /* free any pending tx skb */
268 dev_kfree_skb(pending_skb);
269 dev->stats.tx_errors++;
270 dev->stats.tx_aborted_errors++;
274 * This resets the registers mostly to defaults, but doesn't
275 * affect EEPROM. That seems unnecessary
277 SMC_SELECT_BANK(lp, 0);
278 SMC_SET_RCR(lp, RCR_SOFTRST);
281 * Setup the Configuration Register
282 * This is necessary because the CONFIG_REG is not affected
285 SMC_SELECT_BANK(lp, 1);
287 cfg = CONFIG_DEFAULT;
290 * Setup for fast accesses if requested. If the card/system
291 * can't handle it then there will be no recovery except for
292 * a hard reset or power cycle
294 if (lp->cfg.flags & SMC91X_NOWAIT)
295 cfg |= CONFIG_NO_WAIT;
298 * Release from possible power-down state
299 * Configuration register is not affected by Soft Reset
301 cfg |= CONFIG_EPH_POWER_EN;
303 SMC_SET_CONFIG(lp, cfg);
305 /* this should pause enough for the chip to be happy */
307 * elaborate? What does the chip _need_? --jgarzik
309 * This seems to be undocumented, but something the original
310 * driver(s) have always done. Suspect undocumented timing
311 * info/determined empirically. --rmk
315 /* Disable transmit and receive functionality */
316 SMC_SELECT_BANK(lp, 0);
317 SMC_SET_RCR(lp, RCR_CLEAR);
318 SMC_SET_TCR(lp, TCR_CLEAR);
320 SMC_SELECT_BANK(lp, 1);
321 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
324 * Set the control register to automatically release successfully
325 * transmitted packets, to make the best use out of our limited
328 if(!THROTTLE_TX_PKTS)
329 ctl |= CTL_AUTO_RELEASE;
331 ctl &= ~CTL_AUTO_RELEASE;
332 SMC_SET_CTL(lp, ctl);
335 SMC_SELECT_BANK(lp, 2);
336 SMC_SET_MMU_CMD(lp, MC_RESET);
337 SMC_WAIT_MMU_BUSY(lp);
341 * Enable Interrupts, Receive, and Transmit
343 static void smc_enable(struct net_device *dev)
345 struct smc_local *lp = netdev_priv(dev);
346 void __iomem *ioaddr = lp->base;
349 DBG(2, dev, "%s\n", __func__);
351 /* see the header file for options in TCR/RCR DEFAULT */
352 SMC_SELECT_BANK(lp, 0);
353 SMC_SET_TCR(lp, lp->tcr_cur_mode);
354 SMC_SET_RCR(lp, lp->rcr_cur_mode);
356 SMC_SELECT_BANK(lp, 1);
357 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
359 /* now, enable interrupts */
360 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
361 if (lp->version >= (CHIP_91100 << 4))
363 SMC_SELECT_BANK(lp, 2);
364 SMC_SET_INT_MASK(lp, mask);
367 * From this point the register bank must _NOT_ be switched away
368 * to something else than bank 2 without proper locking against
369 * races with any tasklet or interrupt handlers until smc_shutdown()
370 * or smc_reset() is called.
375 * this puts the device in an inactive state
377 static void smc_shutdown(struct net_device *dev)
379 struct smc_local *lp = netdev_priv(dev);
380 void __iomem *ioaddr = lp->base;
381 struct sk_buff *pending_skb;
383 DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
385 /* no more interrupts for me */
386 spin_lock_irq(&lp->lock);
387 SMC_SELECT_BANK(lp, 2);
388 SMC_SET_INT_MASK(lp, 0);
389 pending_skb = lp->pending_tx_skb;
390 lp->pending_tx_skb = NULL;
391 spin_unlock_irq(&lp->lock);
393 dev_kfree_skb(pending_skb);
395 /* and tell the card to stay away from that nasty outside world */
396 SMC_SELECT_BANK(lp, 0);
397 SMC_SET_RCR(lp, RCR_CLEAR);
398 SMC_SET_TCR(lp, TCR_CLEAR);
401 /* finally, shut the chip down */
402 SMC_SELECT_BANK(lp, 1);
403 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
408 * This is the procedure to handle the receipt of a packet.
410 static inline void smc_rcv(struct net_device *dev)
412 struct smc_local *lp = netdev_priv(dev);
413 void __iomem *ioaddr = lp->base;
414 unsigned int packet_number, status, packet_len;
416 DBG(3, dev, "%s\n", __func__);
418 packet_number = SMC_GET_RXFIFO(lp);
419 if (unlikely(packet_number & RXFIFO_REMPTY)) {
420 PRINTK(dev, "smc_rcv with nothing on FIFO.\n");
424 /* read from start of packet */
425 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
427 /* First two words are status and packet length */
428 SMC_GET_PKT_HDR(lp, status, packet_len);
429 packet_len &= 0x07ff; /* mask off top bits */
430 DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
431 packet_number, status, packet_len, packet_len);
434 if (unlikely(packet_len < 6 || status & RS_ERRORS)) {
435 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) {
436 /* accept VLAN packets */
437 status &= ~RS_TOOLONG;
440 if (packet_len < 6) {
441 /* bloody hardware */
442 netdev_err(dev, "fubar (rxlen %u status %x\n",
444 status |= RS_TOOSHORT;
446 SMC_WAIT_MMU_BUSY(lp);
447 SMC_SET_MMU_CMD(lp, MC_RELEASE);
448 dev->stats.rx_errors++;
449 if (status & RS_ALGNERR)
450 dev->stats.rx_frame_errors++;
451 if (status & (RS_TOOSHORT | RS_TOOLONG))
452 dev->stats.rx_length_errors++;
453 if (status & RS_BADCRC)
454 dev->stats.rx_crc_errors++;
458 unsigned int data_len;
460 /* set multicast stats */
461 if (status & RS_MULTICAST)
462 dev->stats.multicast++;
465 * Actual payload is packet_len - 6 (or 5 if odd byte).
466 * We want skb_reserve(2) and the final ctrl word
467 * (2 bytes, possibly containing the payload odd byte).
468 * Furthermore, we add 2 bytes to allow rounding up to
469 * multiple of 4 bytes on 32 bit buses.
470 * Hence packet_len - 6 + 2 + 2 + 2.
472 skb = netdev_alloc_skb(dev, packet_len);
473 if (unlikely(skb == NULL)) {
474 SMC_WAIT_MMU_BUSY(lp);
475 SMC_SET_MMU_CMD(lp, MC_RELEASE);
476 dev->stats.rx_dropped++;
480 /* Align IP header to 32 bits */
483 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */
484 if (lp->version == 0x90)
485 status |= RS_ODDFRAME;
488 * If odd length: packet_len - 5,
489 * otherwise packet_len - 6.
490 * With the trailing ctrl byte it's packet_len - 4.
492 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
493 data = skb_put(skb, data_len);
494 SMC_PULL_DATA(lp, data, packet_len - 4);
496 SMC_WAIT_MMU_BUSY(lp);
497 SMC_SET_MMU_CMD(lp, MC_RELEASE);
499 PRINT_PKT(data, packet_len - 4);
501 skb->protocol = eth_type_trans(skb, dev);
503 dev->stats.rx_packets++;
504 dev->stats.rx_bytes += data_len;
510 * On SMP we have the following problem:
512 * A = smc_hardware_send_pkt()
513 * B = smc_hard_start_xmit()
514 * C = smc_interrupt()
516 * A and B can never be executed simultaneously. However, at least on UP,
517 * it is possible (and even desirable) for C to interrupt execution of
518 * A or B in order to have better RX reliability and avoid overruns.
519 * C, just like A and B, must have exclusive access to the chip and
520 * each of them must lock against any other concurrent access.
521 * Unfortunately this is not possible to have C suspend execution of A or
522 * B taking place on another CPU. On UP this is no an issue since A and B
523 * are run from softirq context and C from hard IRQ context, and there is
524 * no other CPU where concurrent access can happen.
525 * If ever there is a way to force at least B and C to always be executed
526 * on the same CPU then we could use read/write locks to protect against
527 * any other concurrent access and C would always interrupt B. But life
528 * isn't that easy in a SMP world...
530 #define smc_special_trylock(lock, flags) \
533 local_irq_save(flags); \
534 __ret = spin_trylock(lock); \
536 local_irq_restore(flags); \
539 #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags)
540 #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags)
542 #define smc_special_trylock(lock, flags) (flags == flags)
543 #define smc_special_lock(lock, flags) do { flags = 0; } while (0)
544 #define smc_special_unlock(lock, flags) do { flags = 0; } while (0)
548 * This is called to actually send a packet to the chip.
550 static void smc_hardware_send_pkt(unsigned long data)
552 struct net_device *dev = (struct net_device *)data;
553 struct smc_local *lp = netdev_priv(dev);
554 void __iomem *ioaddr = lp->base;
556 unsigned int packet_no, len;
560 DBG(3, dev, "%s\n", __func__);
562 if (!smc_special_trylock(&lp->lock, flags)) {
563 netif_stop_queue(dev);
564 tasklet_schedule(&lp->tx_task);
568 skb = lp->pending_tx_skb;
569 if (unlikely(!skb)) {
570 smc_special_unlock(&lp->lock, flags);
573 lp->pending_tx_skb = NULL;
575 packet_no = SMC_GET_AR(lp);
576 if (unlikely(packet_no & AR_FAILED)) {
577 netdev_err(dev, "Memory allocation failed.\n");
578 dev->stats.tx_errors++;
579 dev->stats.tx_fifo_errors++;
580 smc_special_unlock(&lp->lock, flags);
584 /* point to the beginning of the packet */
585 SMC_SET_PN(lp, packet_no);
586 SMC_SET_PTR(lp, PTR_AUTOINC);
590 DBG(2, dev, "TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n",
591 packet_no, len, len, buf);
595 * Send the packet length (+6 for status words, length, and ctl.
596 * The card will pad to 64 bytes with zeroes if packet is too small.
598 SMC_PUT_PKT_HDR(lp, 0, len + 6);
600 /* send the actual data */
601 SMC_PUSH_DATA(lp, buf, len & ~1);
603 /* Send final ctl word with the last byte if there is one */
604 SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp));
607 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
608 * have the effect of having at most one packet queued for TX
609 * in the chip's memory at all time.
611 * If THROTTLE_TX_PKTS is not set then the queue is stopped only
612 * when memory allocation (MC_ALLOC) does not succeed right away.
614 if (THROTTLE_TX_PKTS)
615 netif_stop_queue(dev);
617 /* queue the packet for TX */
618 SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
619 smc_special_unlock(&lp->lock, flags);
621 dev->trans_start = jiffies;
622 dev->stats.tx_packets++;
623 dev->stats.tx_bytes += len;
625 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
627 done: if (!THROTTLE_TX_PKTS)
628 netif_wake_queue(dev);
630 dev_consume_skb_any(skb);
634 * Since I am not sure if I will have enough room in the chip's ram
635 * to store the packet, I call this routine which either sends it
636 * now, or set the card to generates an interrupt when ready
639 static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
641 struct smc_local *lp = netdev_priv(dev);
642 void __iomem *ioaddr = lp->base;
643 unsigned int numPages, poll_count, status;
646 DBG(3, dev, "%s\n", __func__);
648 BUG_ON(lp->pending_tx_skb != NULL);
651 * The MMU wants the number of pages to be the number of 256 bytes
652 * 'pages', minus 1 (since a packet can't ever have 0 pages :))
654 * The 91C111 ignores the size bits, but earlier models don't.
656 * Pkt size for allocating is data length +6 (for additional status
657 * words, length and ctl)
659 * If odd size then last byte is included in ctl word.
661 numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
662 if (unlikely(numPages > 7)) {
663 netdev_warn(dev, "Far too big packet error.\n");
664 dev->stats.tx_errors++;
665 dev->stats.tx_dropped++;
666 dev_kfree_skb_any(skb);
670 smc_special_lock(&lp->lock, flags);
672 /* now, try to allocate the memory */
673 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
676 * Poll the chip for a short amount of time in case the
677 * allocation succeeds quickly.
679 poll_count = MEMORY_WAIT_TIME;
681 status = SMC_GET_INT(lp);
682 if (status & IM_ALLOC_INT) {
683 SMC_ACK_INT(lp, IM_ALLOC_INT);
686 } while (--poll_count);
688 smc_special_unlock(&lp->lock, flags);
690 lp->pending_tx_skb = skb;
692 /* oh well, wait until the chip finds memory later */
693 netif_stop_queue(dev);
694 DBG(2, dev, "TX memory allocation deferred.\n");
695 SMC_ENABLE_INT(lp, IM_ALLOC_INT);
698 * Allocation succeeded: push packet to the chip's own memory
701 smc_hardware_send_pkt((unsigned long)dev);
708 * This handles a TX interrupt, which is only called when:
709 * - a TX error occurred, or
710 * - CTL_AUTO_RELEASE is not set and TX of a packet completed.
712 static void smc_tx(struct net_device *dev)
714 struct smc_local *lp = netdev_priv(dev);
715 void __iomem *ioaddr = lp->base;
716 unsigned int saved_packet, packet_no, tx_status, pkt_len;
718 DBG(3, dev, "%s\n", __func__);
720 /* If the TX FIFO is empty then nothing to do */
721 packet_no = SMC_GET_TXFIFO(lp);
722 if (unlikely(packet_no & TXFIFO_TEMPTY)) {
723 PRINTK(dev, "smc_tx with nothing on FIFO.\n");
727 /* select packet to read from */
728 saved_packet = SMC_GET_PN(lp);
729 SMC_SET_PN(lp, packet_no);
731 /* read the first word (status word) from this packet */
732 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
733 SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
734 DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n",
735 tx_status, packet_no);
737 if (!(tx_status & ES_TX_SUC))
738 dev->stats.tx_errors++;
740 if (tx_status & ES_LOSTCARR)
741 dev->stats.tx_carrier_errors++;
743 if (tx_status & (ES_LATCOL | ES_16COL)) {
744 PRINTK(dev, "%s occurred on last xmit\n",
745 (tx_status & ES_LATCOL) ?
746 "late collision" : "too many collisions");
747 dev->stats.tx_window_errors++;
748 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
749 netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n");
753 /* kill the packet */
754 SMC_WAIT_MMU_BUSY(lp);
755 SMC_SET_MMU_CMD(lp, MC_FREEPKT);
757 /* Don't restore Packet Number Reg until busy bit is cleared */
758 SMC_WAIT_MMU_BUSY(lp);
759 SMC_SET_PN(lp, saved_packet);
761 /* re-enable transmit */
762 SMC_SELECT_BANK(lp, 0);
763 SMC_SET_TCR(lp, lp->tcr_cur_mode);
764 SMC_SELECT_BANK(lp, 2);
768 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
770 static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
772 struct smc_local *lp = netdev_priv(dev);
773 void __iomem *ioaddr = lp->base;
774 unsigned int mii_reg, mask;
776 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
779 for (mask = 1 << (bits - 1); mask; mask >>= 1) {
785 SMC_SET_MII(lp, mii_reg);
787 SMC_SET_MII(lp, mii_reg | MII_MCLK);
792 static unsigned int smc_mii_in(struct net_device *dev, int bits)
794 struct smc_local *lp = netdev_priv(dev);
795 void __iomem *ioaddr = lp->base;
796 unsigned int mii_reg, mask, val;
798 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
799 SMC_SET_MII(lp, mii_reg);
801 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
802 if (SMC_GET_MII(lp) & MII_MDI)
805 SMC_SET_MII(lp, mii_reg);
807 SMC_SET_MII(lp, mii_reg | MII_MCLK);
815 * Reads a register from the MII Management serial interface
817 static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
819 struct smc_local *lp = netdev_priv(dev);
820 void __iomem *ioaddr = lp->base;
821 unsigned int phydata;
823 SMC_SELECT_BANK(lp, 3);
826 smc_mii_out(dev, 0xffffffff, 32);
828 /* Start code (01) + read (10) + phyaddr + phyreg */
829 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
831 /* Turnaround (2bits) + phydata */
832 phydata = smc_mii_in(dev, 18);
834 /* Return to idle state */
835 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
837 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
838 __func__, phyaddr, phyreg, phydata);
840 SMC_SELECT_BANK(lp, 2);
845 * Writes a register to the MII Management serial interface
847 static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
850 struct smc_local *lp = netdev_priv(dev);
851 void __iomem *ioaddr = lp->base;
853 SMC_SELECT_BANK(lp, 3);
856 smc_mii_out(dev, 0xffffffff, 32);
858 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */
859 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
861 /* Return to idle state */
862 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
864 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
865 __func__, phyaddr, phyreg, phydata);
867 SMC_SELECT_BANK(lp, 2);
871 * Finds and reports the PHY address
873 static void smc_phy_detect(struct net_device *dev)
875 struct smc_local *lp = netdev_priv(dev);
878 DBG(2, dev, "%s\n", __func__);
883 * Scan all 32 PHY addresses if necessary, starting at
884 * PHY#1 to PHY#31, and then PHY#0 last.
886 for (phyaddr = 1; phyaddr < 33; ++phyaddr) {
887 unsigned int id1, id2;
889 /* Read the PHY identifiers */
890 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1);
891 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2);
893 DBG(3, dev, "phy_id1=0x%x, phy_id2=0x%x\n",
896 /* Make sure it is a valid identifier */
897 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
898 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) {
899 /* Save the PHY's address */
900 lp->mii.phy_id = phyaddr & 31;
901 lp->phy_type = id1 << 16 | id2;
908 * Sets the PHY to a configuration as determined by the user
910 static int smc_phy_fixed(struct net_device *dev)
912 struct smc_local *lp = netdev_priv(dev);
913 void __iomem *ioaddr = lp->base;
914 int phyaddr = lp->mii.phy_id;
917 DBG(3, dev, "%s\n", __func__);
919 /* Enter Link Disable state */
920 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
921 cfg1 |= PHY_CFG1_LNKDIS;
922 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
925 * Set our fixed capabilities
926 * Disable auto-negotiation
931 bmcr |= BMCR_FULLDPLX;
933 if (lp->ctl_rspeed == 100)
934 bmcr |= BMCR_SPEED100;
936 /* Write our capabilities to the phy control register */
937 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
939 /* Re-Configure the Receive/Phy Control register */
940 SMC_SELECT_BANK(lp, 0);
941 SMC_SET_RPC(lp, lp->rpc_cur_mode);
942 SMC_SELECT_BANK(lp, 2);
948 * smc_phy_reset - reset the phy
952 * Issue a software reset for the specified PHY and
953 * wait up to 100ms for the reset to complete. We should
954 * not access the PHY for 50ms after issuing the reset.
956 * The time to wait appears to be dependent on the PHY.
958 * Must be called with lp->lock locked.
960 static int smc_phy_reset(struct net_device *dev, int phy)
962 struct smc_local *lp = netdev_priv(dev);
966 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
968 for (timeout = 2; timeout; timeout--) {
969 spin_unlock_irq(&lp->lock);
971 spin_lock_irq(&lp->lock);
973 bmcr = smc_phy_read(dev, phy, MII_BMCR);
974 if (!(bmcr & BMCR_RESET))
978 return bmcr & BMCR_RESET;
982 * smc_phy_powerdown - powerdown phy
985 * Power down the specified PHY
987 static void smc_phy_powerdown(struct net_device *dev)
989 struct smc_local *lp = netdev_priv(dev);
991 int phy = lp->mii.phy_id;
993 if (lp->phy_type == 0)
996 /* We need to ensure that no calls to smc_phy_configure are
999 cancel_work_sync(&lp->phy_configure);
1001 bmcr = smc_phy_read(dev, phy, MII_BMCR);
1002 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
1006 * smc_phy_check_media - check the media status and adjust TCR
1008 * @init: set true for initialisation
1010 * Select duplex mode depending on negotiation state. This
1011 * also updates our carrier state.
1013 static void smc_phy_check_media(struct net_device *dev, int init)
1015 struct smc_local *lp = netdev_priv(dev);
1016 void __iomem *ioaddr = lp->base;
1018 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
1019 /* duplex state has changed */
1020 if (lp->mii.full_duplex) {
1021 lp->tcr_cur_mode |= TCR_SWFDUP;
1023 lp->tcr_cur_mode &= ~TCR_SWFDUP;
1026 SMC_SELECT_BANK(lp, 0);
1027 SMC_SET_TCR(lp, lp->tcr_cur_mode);
1032 * Configures the specified PHY through the MII management interface
1033 * using Autonegotiation.
1034 * Calls smc_phy_fixed() if the user has requested a certain config.
1035 * If RPC ANEG bit is set, the media selection is dependent purely on
1036 * the selection by the MII (either in the MII BMCR reg or the result
1037 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
1038 * is controlled by the RPC SPEED and RPC DPLX bits.
1040 static void smc_phy_configure(struct work_struct *work)
1042 struct smc_local *lp =
1043 container_of(work, struct smc_local, phy_configure);
1044 struct net_device *dev = lp->dev;
1045 void __iomem *ioaddr = lp->base;
1046 int phyaddr = lp->mii.phy_id;
1047 int my_phy_caps; /* My PHY capabilities */
1048 int my_ad_caps; /* My Advertised capabilities */
1051 DBG(3, dev, "smc_program_phy()\n");
1053 spin_lock_irq(&lp->lock);
1056 * We should not be called if phy_type is zero.
1058 if (lp->phy_type == 0)
1059 goto smc_phy_configure_exit;
1061 if (smc_phy_reset(dev, phyaddr)) {
1062 netdev_info(dev, "PHY reset timed out\n");
1063 goto smc_phy_configure_exit;
1067 * Enable PHY Interrupts (for register 18)
1068 * Interrupts listed here are disabled
1070 smc_phy_write(dev, phyaddr, PHY_MASK_REG,
1071 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
1072 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
1073 PHY_INT_SPDDET | PHY_INT_DPLXDET);
1075 /* Configure the Receive/Phy Control register */
1076 SMC_SELECT_BANK(lp, 0);
1077 SMC_SET_RPC(lp, lp->rpc_cur_mode);
1079 /* If the user requested no auto neg, then go set his request */
1080 if (lp->mii.force_media) {
1082 goto smc_phy_configure_exit;
1085 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
1086 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
1088 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
1089 netdev_info(dev, "Auto negotiation NOT supported\n");
1091 goto smc_phy_configure_exit;
1094 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */
1096 if (my_phy_caps & BMSR_100BASE4)
1097 my_ad_caps |= ADVERTISE_100BASE4;
1098 if (my_phy_caps & BMSR_100FULL)
1099 my_ad_caps |= ADVERTISE_100FULL;
1100 if (my_phy_caps & BMSR_100HALF)
1101 my_ad_caps |= ADVERTISE_100HALF;
1102 if (my_phy_caps & BMSR_10FULL)
1103 my_ad_caps |= ADVERTISE_10FULL;
1104 if (my_phy_caps & BMSR_10HALF)
1105 my_ad_caps |= ADVERTISE_10HALF;
1107 /* Disable capabilities not selected by our user */
1108 if (lp->ctl_rspeed != 100)
1109 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
1111 if (!lp->ctl_rfduplx)
1112 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1114 /* Update our Auto-Neg Advertisement Register */
1115 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps);
1116 lp->mii.advertising = my_ad_caps;
1119 * Read the register back. Without this, it appears that when
1120 * auto-negotiation is restarted, sometimes it isn't ready and
1121 * the link does not come up.
1123 status = smc_phy_read(dev, phyaddr, MII_ADVERTISE);
1125 DBG(2, dev, "phy caps=%x\n", my_phy_caps);
1126 DBG(2, dev, "phy advertised caps=%x\n", my_ad_caps);
1128 /* Restart auto-negotiation process in order to advertise my caps */
1129 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1131 smc_phy_check_media(dev, 1);
1133 smc_phy_configure_exit:
1134 SMC_SELECT_BANK(lp, 2);
1135 spin_unlock_irq(&lp->lock);
1141 * Purpose: Handle interrupts relating to PHY register 18. This is
1142 * called from the "hard" interrupt handler under our private spinlock.
1144 static void smc_phy_interrupt(struct net_device *dev)
1146 struct smc_local *lp = netdev_priv(dev);
1147 int phyaddr = lp->mii.phy_id;
1150 DBG(2, dev, "%s\n", __func__);
1152 if (lp->phy_type == 0)
1156 smc_phy_check_media(dev, 0);
1158 /* Read PHY Register 18, Status Output */
1159 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG);
1160 if ((phy18 & PHY_INT_INT) == 0)
1165 /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1167 static void smc_10bt_check_media(struct net_device *dev, int init)
1169 struct smc_local *lp = netdev_priv(dev);
1170 void __iomem *ioaddr = lp->base;
1171 unsigned int old_carrier, new_carrier;
1173 old_carrier = netif_carrier_ok(dev) ? 1 : 0;
1175 SMC_SELECT_BANK(lp, 0);
1176 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
1177 SMC_SELECT_BANK(lp, 2);
1179 if (init || (old_carrier != new_carrier)) {
1181 netif_carrier_off(dev);
1183 netif_carrier_on(dev);
1185 if (netif_msg_link(lp))
1186 netdev_info(dev, "link %s\n",
1187 new_carrier ? "up" : "down");
1191 static void smc_eph_interrupt(struct net_device *dev)
1193 struct smc_local *lp = netdev_priv(dev);
1194 void __iomem *ioaddr = lp->base;
1197 smc_10bt_check_media(dev, 0);
1199 SMC_SELECT_BANK(lp, 1);
1200 ctl = SMC_GET_CTL(lp);
1201 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
1202 SMC_SET_CTL(lp, ctl);
1203 SMC_SELECT_BANK(lp, 2);
1207 * This is the main routine of the driver, to handle the device when
1208 * it needs some attention.
1210 static irqreturn_t smc_interrupt(int irq, void *dev_id)
1212 struct net_device *dev = dev_id;
1213 struct smc_local *lp = netdev_priv(dev);
1214 void __iomem *ioaddr = lp->base;
1215 int status, mask, timeout, card_stats;
1218 DBG(3, dev, "%s\n", __func__);
1220 spin_lock(&lp->lock);
1222 /* A preamble may be used when there is a potential race
1223 * between the interruptible transmit functions and this
1225 SMC_INTERRUPT_PREAMBLE;
1227 saved_pointer = SMC_GET_PTR(lp);
1228 mask = SMC_GET_INT_MASK(lp);
1229 SMC_SET_INT_MASK(lp, 0);
1231 /* set a timeout value, so I don't stay here forever */
1232 timeout = MAX_IRQ_LOOPS;
1235 status = SMC_GET_INT(lp);
1237 DBG(2, dev, "INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
1239 ({ int meminfo; SMC_SELECT_BANK(lp, 0);
1240 meminfo = SMC_GET_MIR(lp);
1241 SMC_SELECT_BANK(lp, 2); meminfo; }),
1248 if (status & IM_TX_INT) {
1249 /* do this before RX as it will free memory quickly */
1250 DBG(3, dev, "TX int\n");
1252 SMC_ACK_INT(lp, IM_TX_INT);
1253 if (THROTTLE_TX_PKTS)
1254 netif_wake_queue(dev);
1255 } else if (status & IM_RCV_INT) {
1256 DBG(3, dev, "RX irq\n");
1258 } else if (status & IM_ALLOC_INT) {
1259 DBG(3, dev, "Allocation irq\n");
1260 tasklet_hi_schedule(&lp->tx_task);
1261 mask &= ~IM_ALLOC_INT;
1262 } else if (status & IM_TX_EMPTY_INT) {
1263 DBG(3, dev, "TX empty\n");
1264 mask &= ~IM_TX_EMPTY_INT;
1267 SMC_SELECT_BANK(lp, 0);
1268 card_stats = SMC_GET_COUNTER(lp);
1269 SMC_SELECT_BANK(lp, 2);
1271 /* single collisions */
1272 dev->stats.collisions += card_stats & 0xF;
1275 /* multiple collisions */
1276 dev->stats.collisions += card_stats & 0xF;
1277 } else if (status & IM_RX_OVRN_INT) {
1278 DBG(1, dev, "RX overrun (EPH_ST 0x%04x)\n",
1279 ({ int eph_st; SMC_SELECT_BANK(lp, 0);
1280 eph_st = SMC_GET_EPH_STATUS(lp);
1281 SMC_SELECT_BANK(lp, 2); eph_st; }));
1282 SMC_ACK_INT(lp, IM_RX_OVRN_INT);
1283 dev->stats.rx_errors++;
1284 dev->stats.rx_fifo_errors++;
1285 } else if (status & IM_EPH_INT) {
1286 smc_eph_interrupt(dev);
1287 } else if (status & IM_MDINT) {
1288 SMC_ACK_INT(lp, IM_MDINT);
1289 smc_phy_interrupt(dev);
1290 } else if (status & IM_ERCV_INT) {
1291 SMC_ACK_INT(lp, IM_ERCV_INT);
1292 PRINTK(dev, "UNSUPPORTED: ERCV INTERRUPT\n");
1294 } while (--timeout);
1296 /* restore register states */
1297 SMC_SET_PTR(lp, saved_pointer);
1298 SMC_SET_INT_MASK(lp, mask);
1299 spin_unlock(&lp->lock);
1301 #ifndef CONFIG_NET_POLL_CONTROLLER
1302 if (timeout == MAX_IRQ_LOOPS)
1303 PRINTK(dev, "spurious interrupt (mask = 0x%02x)\n",
1306 DBG(3, dev, "Interrupt done (%d loops)\n",
1307 MAX_IRQ_LOOPS - timeout);
1310 * We return IRQ_HANDLED unconditionally here even if there was
1311 * nothing to do. There is a possibility that a packet might
1312 * get enqueued into the chip right after TX_EMPTY_INT is raised
1313 * but just before the CPU acknowledges the IRQ.
1314 * Better take an unneeded IRQ in some occasions than complexifying
1315 * the code for all cases.
1320 #ifdef CONFIG_NET_POLL_CONTROLLER
1322 * Polling receive - used by netconsole and other diagnostic tools
1323 * to allow network i/o with interrupts disabled.
1325 static void smc_poll_controller(struct net_device *dev)
1327 disable_irq(dev->irq);
1328 smc_interrupt(dev->irq, dev);
1329 enable_irq(dev->irq);
1333 /* Our watchdog timed out. Called by the networking layer */
1334 static void smc_timeout(struct net_device *dev)
1336 struct smc_local *lp = netdev_priv(dev);
1337 void __iomem *ioaddr = lp->base;
1338 int status, mask, eph_st, meminfo, fifo;
1340 DBG(2, dev, "%s\n", __func__);
1342 spin_lock_irq(&lp->lock);
1343 status = SMC_GET_INT(lp);
1344 mask = SMC_GET_INT_MASK(lp);
1345 fifo = SMC_GET_FIFO(lp);
1346 SMC_SELECT_BANK(lp, 0);
1347 eph_st = SMC_GET_EPH_STATUS(lp);
1348 meminfo = SMC_GET_MIR(lp);
1349 SMC_SELECT_BANK(lp, 2);
1350 spin_unlock_irq(&lp->lock);
1351 PRINTK(dev, "TX timeout (INT 0x%02x INTMASK 0x%02x MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
1352 status, mask, meminfo, fifo, eph_st);
1358 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1359 * smc_phy_configure() calls msleep() which calls schedule_timeout()
1360 * which calls schedule(). Hence we use a work queue.
1362 if (lp->phy_type != 0)
1363 schedule_work(&lp->phy_configure);
1365 /* We can accept TX packets again */
1366 dev->trans_start = jiffies; /* prevent tx timeout */
1367 netif_wake_queue(dev);
1371 * This routine will, depending on the values passed to it,
1372 * either make it accept multicast packets, go into
1373 * promiscuous mode (for TCPDUMP and cousins) or accept
1374 * a select set of multicast packets
1376 static void smc_set_multicast_list(struct net_device *dev)
1378 struct smc_local *lp = netdev_priv(dev);
1379 void __iomem *ioaddr = lp->base;
1380 unsigned char multicast_table[8];
1381 int update_multicast = 0;
1383 DBG(2, dev, "%s\n", __func__);
1385 if (dev->flags & IFF_PROMISC) {
1386 DBG(2, dev, "RCR_PRMS\n");
1387 lp->rcr_cur_mode |= RCR_PRMS;
1390 /* BUG? I never disable promiscuous mode if multicasting was turned on.
1391 Now, I turn off promiscuous mode, but I don't do anything to multicasting
1392 when promiscuous mode is turned on.
1396 * Here, I am setting this to accept all multicast packets.
1397 * I don't need to zero the multicast table, because the flag is
1398 * checked before the table is
1400 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
1401 DBG(2, dev, "RCR_ALMUL\n");
1402 lp->rcr_cur_mode |= RCR_ALMUL;
1406 * This sets the internal hardware table to filter out unwanted
1407 * multicast packets before they take up memory.
1409 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1410 * address are the offset into the table. If that bit is 1, then the
1411 * multicast packet is accepted. Otherwise, it's dropped silently.
1413 * To use the 6 bits as an offset into the table, the high 3 bits are
1414 * the number of the 8 bit register, while the low 3 bits are the bit
1415 * within that register.
1417 else if (!netdev_mc_empty(dev)) {
1418 struct netdev_hw_addr *ha;
1420 /* table for flipping the order of 3 bits */
1421 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7};
1423 /* start with a table of all zeros: reject all */
1424 memset(multicast_table, 0, sizeof(multicast_table));
1426 netdev_for_each_mc_addr(ha, dev) {
1429 /* only use the low order bits */
1430 position = crc32_le(~0, ha->addr, 6) & 0x3f;
1432 /* do some messy swapping to put the bit in the right spot */
1433 multicast_table[invert3[position&7]] |=
1434 (1<<invert3[(position>>3)&7]);
1437 /* be sure I get rid of flags I might have set */
1438 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1440 /* now, the table can be loaded into the chipset */
1441 update_multicast = 1;
1443 DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n");
1444 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1447 * since I'm disabling all multicast entirely, I need to
1448 * clear the multicast list
1450 memset(multicast_table, 0, sizeof(multicast_table));
1451 update_multicast = 1;
1454 spin_lock_irq(&lp->lock);
1455 SMC_SELECT_BANK(lp, 0);
1456 SMC_SET_RCR(lp, lp->rcr_cur_mode);
1457 if (update_multicast) {
1458 SMC_SELECT_BANK(lp, 3);
1459 SMC_SET_MCAST(lp, multicast_table);
1461 SMC_SELECT_BANK(lp, 2);
1462 spin_unlock_irq(&lp->lock);
1467 * Open and Initialize the board
1469 * Set up everything, reset the card, etc..
1472 smc_open(struct net_device *dev)
1474 struct smc_local *lp = netdev_priv(dev);
1476 DBG(2, dev, "%s\n", __func__);
1478 /* Setup the default Register Modes */
1479 lp->tcr_cur_mode = TCR_DEFAULT;
1480 lp->rcr_cur_mode = RCR_DEFAULT;
1481 lp->rpc_cur_mode = RPC_DEFAULT |
1482 lp->cfg.leda << RPC_LSXA_SHFT |
1483 lp->cfg.ledb << RPC_LSXB_SHFT;
1486 * If we are not using a MII interface, we need to
1487 * monitor our own carrier signal to detect faults.
1489 if (lp->phy_type == 0)
1490 lp->tcr_cur_mode |= TCR_MON_CSN;
1492 /* reset the hardware */
1496 /* Configure the PHY, initialize the link state */
1497 if (lp->phy_type != 0)
1498 smc_phy_configure(&lp->phy_configure);
1500 spin_lock_irq(&lp->lock);
1501 smc_10bt_check_media(dev, 1);
1502 spin_unlock_irq(&lp->lock);
1505 netif_start_queue(dev);
1512 * this makes the board clean up everything that it can
1513 * and not talk to the outside world. Caused by
1514 * an 'ifconfig ethX down'
1516 static int smc_close(struct net_device *dev)
1518 struct smc_local *lp = netdev_priv(dev);
1520 DBG(2, dev, "%s\n", __func__);
1522 netif_stop_queue(dev);
1523 netif_carrier_off(dev);
1525 /* clear everything */
1527 tasklet_kill(&lp->tx_task);
1528 smc_phy_powerdown(dev);
1536 smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1538 struct smc_local *lp = netdev_priv(dev);
1544 if (lp->phy_type != 0) {
1545 spin_lock_irq(&lp->lock);
1546 ret = mii_ethtool_gset(&lp->mii, cmd);
1547 spin_unlock_irq(&lp->lock);
1549 cmd->supported = SUPPORTED_10baseT_Half |
1550 SUPPORTED_10baseT_Full |
1551 SUPPORTED_TP | SUPPORTED_AUI;
1553 if (lp->ctl_rspeed == 10)
1554 ethtool_cmd_speed_set(cmd, SPEED_10);
1555 else if (lp->ctl_rspeed == 100)
1556 ethtool_cmd_speed_set(cmd, SPEED_100);
1558 cmd->autoneg = AUTONEG_DISABLE;
1559 cmd->transceiver = XCVR_INTERNAL;
1561 cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF;
1570 smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1572 struct smc_local *lp = netdev_priv(dev);
1575 if (lp->phy_type != 0) {
1576 spin_lock_irq(&lp->lock);
1577 ret = mii_ethtool_sset(&lp->mii, cmd);
1578 spin_unlock_irq(&lp->lock);
1580 if (cmd->autoneg != AUTONEG_DISABLE ||
1581 cmd->speed != SPEED_10 ||
1582 (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
1583 (cmd->port != PORT_TP && cmd->port != PORT_AUI))
1586 // lp->port = cmd->port;
1587 lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
1589 // if (netif_running(dev))
1590 // smc_set_port(dev);
1599 smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1601 strlcpy(info->driver, CARDNAME, sizeof(info->driver));
1602 strlcpy(info->version, version, sizeof(info->version));
1603 strlcpy(info->bus_info, dev_name(dev->dev.parent),
1604 sizeof(info->bus_info));
1607 static int smc_ethtool_nwayreset(struct net_device *dev)
1609 struct smc_local *lp = netdev_priv(dev);
1612 if (lp->phy_type != 0) {
1613 spin_lock_irq(&lp->lock);
1614 ret = mii_nway_restart(&lp->mii);
1615 spin_unlock_irq(&lp->lock);
1621 static u32 smc_ethtool_getmsglevel(struct net_device *dev)
1623 struct smc_local *lp = netdev_priv(dev);
1624 return lp->msg_enable;
1627 static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level)
1629 struct smc_local *lp = netdev_priv(dev);
1630 lp->msg_enable = level;
1633 static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word)
1636 struct smc_local *lp = netdev_priv(dev);
1637 void __iomem *ioaddr = lp->base;
1639 spin_lock_irq(&lp->lock);
1640 /* load word into GP register */
1641 SMC_SELECT_BANK(lp, 1);
1642 SMC_SET_GP(lp, word);
1643 /* set the address to put the data in EEPROM */
1644 SMC_SELECT_BANK(lp, 2);
1645 SMC_SET_PTR(lp, addr);
1646 /* tell it to write */
1647 SMC_SELECT_BANK(lp, 1);
1648 ctl = SMC_GET_CTL(lp);
1649 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE));
1650 /* wait for it to finish */
1653 } while (SMC_GET_CTL(lp) & CTL_STORE);
1655 SMC_SET_CTL(lp, ctl);
1656 SMC_SELECT_BANK(lp, 2);
1657 spin_unlock_irq(&lp->lock);
1661 static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word)
1664 struct smc_local *lp = netdev_priv(dev);
1665 void __iomem *ioaddr = lp->base;
1667 spin_lock_irq(&lp->lock);
1668 /* set the EEPROM address to get the data from */
1669 SMC_SELECT_BANK(lp, 2);
1670 SMC_SET_PTR(lp, addr | PTR_READ);
1671 /* tell it to load */
1672 SMC_SELECT_BANK(lp, 1);
1673 SMC_SET_GP(lp, 0xffff); /* init to known */
1674 ctl = SMC_GET_CTL(lp);
1675 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD));
1676 /* wait for it to finish */
1679 } while (SMC_GET_CTL(lp) & CTL_RELOAD);
1680 /* read word from GP register */
1681 *word = SMC_GET_GP(lp);
1683 SMC_SET_CTL(lp, ctl);
1684 SMC_SELECT_BANK(lp, 2);
1685 spin_unlock_irq(&lp->lock);
1689 static int smc_ethtool_geteeprom_len(struct net_device *dev)
1694 static int smc_ethtool_geteeprom(struct net_device *dev,
1695 struct ethtool_eeprom *eeprom, u8 *data)
1700 DBG(1, dev, "Reading %d bytes at %d(0x%x)\n",
1701 eeprom->len, eeprom->offset, eeprom->offset);
1702 imax = smc_ethtool_geteeprom_len(dev);
1703 for (i = 0; i < eeprom->len; i += 2) {
1706 int offset = i + eeprom->offset;
1709 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf);
1712 DBG(2, dev, "Read 0x%x from 0x%x\n", wbuf, offset >> 1);
1713 data[i] = (wbuf >> 8) & 0xff;
1714 data[i+1] = wbuf & 0xff;
1719 static int smc_ethtool_seteeprom(struct net_device *dev,
1720 struct ethtool_eeprom *eeprom, u8 *data)
1725 DBG(1, dev, "Writing %d bytes to %d(0x%x)\n",
1726 eeprom->len, eeprom->offset, eeprom->offset);
1727 imax = smc_ethtool_geteeprom_len(dev);
1728 for (i = 0; i < eeprom->len; i += 2) {
1731 int offset = i + eeprom->offset;
1734 wbuf = (data[i] << 8) | data[i + 1];
1735 DBG(2, dev, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1);
1736 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf);
1744 static const struct ethtool_ops smc_ethtool_ops = {
1745 .get_settings = smc_ethtool_getsettings,
1746 .set_settings = smc_ethtool_setsettings,
1747 .get_drvinfo = smc_ethtool_getdrvinfo,
1749 .get_msglevel = smc_ethtool_getmsglevel,
1750 .set_msglevel = smc_ethtool_setmsglevel,
1751 .nway_reset = smc_ethtool_nwayreset,
1752 .get_link = ethtool_op_get_link,
1753 .get_eeprom_len = smc_ethtool_geteeprom_len,
1754 .get_eeprom = smc_ethtool_geteeprom,
1755 .set_eeprom = smc_ethtool_seteeprom,
1758 static const struct net_device_ops smc_netdev_ops = {
1759 .ndo_open = smc_open,
1760 .ndo_stop = smc_close,
1761 .ndo_start_xmit = smc_hard_start_xmit,
1762 .ndo_tx_timeout = smc_timeout,
1763 .ndo_set_rx_mode = smc_set_multicast_list,
1764 .ndo_change_mtu = eth_change_mtu,
1765 .ndo_validate_addr = eth_validate_addr,
1766 .ndo_set_mac_address = eth_mac_addr,
1767 #ifdef CONFIG_NET_POLL_CONTROLLER
1768 .ndo_poll_controller = smc_poll_controller,
1775 * This routine has a simple purpose -- make the SMC chip generate an
1776 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1779 * does this still work?
1781 * I just deleted auto_irq.c, since it was never built...
1784 static int smc_findirq(struct smc_local *lp)
1786 void __iomem *ioaddr = lp->base;
1788 unsigned long cookie;
1790 DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__);
1792 cookie = probe_irq_on();
1795 * What I try to do here is trigger an ALLOC_INT. This is done
1796 * by allocating a small chunk of memory, which will give an interrupt
1799 /* enable ALLOCation interrupts ONLY */
1800 SMC_SELECT_BANK(lp, 2);
1801 SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
1804 * Allocate 512 bytes of memory. Note that the chip was just
1805 * reset so all the memory is available
1807 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
1810 * Wait until positive that the interrupt has been generated
1815 int_status = SMC_GET_INT(lp);
1816 if (int_status & IM_ALLOC_INT)
1817 break; /* got the interrupt */
1818 } while (--timeout);
1821 * there is really nothing that I can do here if timeout fails,
1822 * as autoirq_report will return a 0 anyway, which is what I
1823 * want in this case. Plus, the clean up is needed in both
1827 /* and disable all interrupts again */
1828 SMC_SET_INT_MASK(lp, 0);
1830 /* and return what I found */
1831 return probe_irq_off(cookie);
1835 * Function: smc_probe(unsigned long ioaddr)
1838 * Tests to see if a given ioaddr points to an SMC91x chip.
1839 * Returns a 0 on success
1842 * (1) see if the high byte of BANK_SELECT is 0x33
1843 * (2) compare the ioaddr with the base register's address
1844 * (3) see if I recognize the chip ID in the appropriate register
1846 * Here I do typical initialization tasks.
1848 * o Initialize the structure if needed
1849 * o print out my vanity message if not done so already
1850 * o print out what type of hardware is detected
1851 * o print out the ethernet address
1853 * o set up my private data
1854 * o configure the dev structure with my subroutines
1855 * o actually GRAB the irq.
1858 static int smc_probe(struct net_device *dev, void __iomem *ioaddr,
1859 unsigned long irq_flags)
1861 struct smc_local *lp = netdev_priv(dev);
1863 unsigned int val, revision_register;
1864 const char *version_string;
1866 DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
1868 /* First, see if the high byte is 0x33 */
1869 val = SMC_CURRENT_BANK(lp);
1870 DBG(2, dev, "%s: bank signature probe returned 0x%04x\n",
1872 if ((val & 0xFF00) != 0x3300) {
1873 if ((val & 0xFF) == 0x33) {
1875 "%s: Detected possible byte-swapped interface at IOADDR %p\n",
1883 * The above MIGHT indicate a device, but I need to write to
1884 * further test this.
1886 SMC_SELECT_BANK(lp, 0);
1887 val = SMC_CURRENT_BANK(lp);
1888 if ((val & 0xFF00) != 0x3300) {
1894 * well, we've already written once, so hopefully another
1895 * time won't hurt. This time, I need to switch the bank
1896 * register to bank 1, so I can access the base address
1899 SMC_SELECT_BANK(lp, 1);
1900 val = SMC_GET_BASE(lp);
1901 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
1902 if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
1903 netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n",
1904 CARDNAME, ioaddr, val);
1908 * check if the revision register is something that I
1909 * recognize. These might need to be added to later,
1910 * as future revisions could be added.
1912 SMC_SELECT_BANK(lp, 3);
1913 revision_register = SMC_GET_REV(lp);
1914 DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
1915 version_string = chip_ids[ (revision_register >> 4) & 0xF];
1916 if (!version_string || (revision_register & 0xff00) != 0x3300) {
1917 /* I don't recognize this chip, so... */
1918 netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n",
1919 CARDNAME, ioaddr, revision_register);
1925 /* At this point I'll assume that the chip is an SMC91x. */
1926 pr_info_once("%s\n", version);
1928 /* fill in some of the fields */
1929 dev->base_addr = (unsigned long)ioaddr;
1931 lp->version = revision_register & 0xff;
1932 spin_lock_init(&lp->lock);
1934 /* Get the MAC address */
1935 SMC_SELECT_BANK(lp, 1);
1936 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1938 /* now, reset the chip, and put it into a known state */
1942 * If dev->irq is 0, then the device has to be banged on to see
1945 * This banging doesn't always detect the IRQ, for unknown reasons.
1946 * a workaround is to reset the chip and try again.
1948 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1949 * be what is requested on the command line. I don't do that, mostly
1950 * because the card that I have uses a non-standard method of accessing
1951 * the IRQs, and because this _should_ work in most configurations.
1953 * Specifying an IRQ is done with the assumption that the user knows
1954 * what (s)he is doing. No checking is done!!!!
1961 dev->irq = smc_findirq(lp);
1964 /* kick the card and try again */
1968 if (dev->irq == 0) {
1969 netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n");
1973 dev->irq = irq_canonicalize(dev->irq);
1975 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1976 dev->netdev_ops = &smc_netdev_ops;
1977 dev->ethtool_ops = &smc_ethtool_ops;
1979 tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev);
1980 INIT_WORK(&lp->phy_configure, smc_phy_configure);
1982 lp->mii.phy_id_mask = 0x1f;
1983 lp->mii.reg_num_mask = 0x1f;
1984 lp->mii.force_media = 0;
1985 lp->mii.full_duplex = 0;
1987 lp->mii.mdio_read = smc_phy_read;
1988 lp->mii.mdio_write = smc_phy_write;
1991 * Locate the phy, if any.
1993 if (lp->version >= (CHIP_91100 << 4))
1994 smc_phy_detect(dev);
1996 /* then shut everything down to save power */
1998 smc_phy_powerdown(dev);
2000 /* Set default parameters */
2001 lp->msg_enable = NETIF_MSG_LINK;
2002 lp->ctl_rfduplx = 0;
2003 lp->ctl_rspeed = 10;
2005 if (lp->version >= (CHIP_91100 << 4)) {
2006 lp->ctl_rfduplx = 1;
2007 lp->ctl_rspeed = 100;
2011 retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev);
2015 #ifdef CONFIG_ARCH_PXA
2016 # ifdef SMC_USE_PXA_DMA
2017 lp->cfg.flags |= SMC91X_USE_DMA;
2019 if (lp->cfg.flags & SMC91X_USE_DMA) {
2020 int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW,
2021 smc_pxa_dma_irq, NULL);
2027 retval = register_netdev(dev);
2029 /* now, print out the card info, in a short format.. */
2030 netdev_info(dev, "%s (rev %d) at %p IRQ %d",
2031 version_string, revision_register & 0x0f,
2032 lp->base, dev->irq);
2034 if (dev->dma != (unsigned char)-1)
2035 pr_cont(" DMA %d", dev->dma);
2038 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "",
2039 THROTTLE_TX_PKTS ? " [throttle_tx]" : "");
2041 if (!is_valid_ether_addr(dev->dev_addr)) {
2042 netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n");
2044 /* Print the Ethernet address */
2045 netdev_info(dev, "Ethernet addr: %pM\n",
2049 if (lp->phy_type == 0) {
2050 PRINTK(dev, "No PHY found\n");
2051 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) {
2052 PRINTK(dev, "PHY LAN83C183 (LAN91C111 Internal)\n");
2053 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) {
2054 PRINTK(dev, "PHY LAN83C180\n");
2059 #ifdef CONFIG_ARCH_PXA
2060 if (retval && dev->dma != (unsigned char)-1)
2061 pxa_free_dma(dev->dma);
2066 static int smc_enable_device(struct platform_device *pdev)
2068 struct net_device *ndev = platform_get_drvdata(pdev);
2069 struct smc_local *lp = netdev_priv(ndev);
2070 unsigned long flags;
2071 unsigned char ecor, ecsr;
2073 struct resource * res;
2075 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2080 * Map the attribute space. This is overkill, but clean.
2082 addr = ioremap(res->start, ATTRIB_SIZE);
2087 * Reset the device. We must disable IRQs around this
2088 * since a reset causes the IRQ line become active.
2090 local_irq_save(flags);
2091 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
2092 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
2093 readb(addr + (ECOR << SMC_IO_SHIFT));
2096 * Wait 100us for the chip to reset.
2101 * The device will ignore all writes to the enable bit while
2102 * reset is asserted, even if the reset bit is cleared in the
2103 * same write. Must clear reset first, then enable the device.
2105 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
2106 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
2109 * Set the appropriate byte/word mode.
2111 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
2114 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
2115 local_irq_restore(flags);
2120 * Wait for the chip to wake up. We could poll the control
2121 * register in the main register space, but that isn't mapped
2122 * yet. We know this is going to take 750us.
2129 static int smc_request_attrib(struct platform_device *pdev,
2130 struct net_device *ndev)
2132 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2133 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2138 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME))
2144 static void smc_release_attrib(struct platform_device *pdev,
2145 struct net_device *ndev)
2147 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2148 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2151 release_mem_region(res->start, ATTRIB_SIZE);
2154 static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev)
2156 if (SMC_CAN_USE_DATACS) {
2157 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2158 struct smc_local *lp = netdev_priv(ndev);
2163 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) {
2164 netdev_info(ndev, "%s: failed to request datacs memory region.\n",
2169 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT);
2173 static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev)
2175 if (SMC_CAN_USE_DATACS) {
2176 struct smc_local *lp = netdev_priv(ndev);
2177 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2180 iounmap(lp->datacs);
2185 release_mem_region(res->start, SMC_DATA_EXTENT);
2189 #if IS_BUILTIN(CONFIG_OF)
2190 static const struct of_device_id smc91x_match[] = {
2191 { .compatible = "smsc,lan91c94", },
2192 { .compatible = "smsc,lan91c111", },
2195 MODULE_DEVICE_TABLE(of, smc91x_match);
2198 * of_try_set_control_gpio - configure a gpio if it exists
2200 static int try_toggle_control_gpio(struct device *dev,
2201 struct gpio_desc **desc,
2202 const char *name, int index,
2203 int value, unsigned int nsdelay)
2205 struct gpio_desc *gpio = *desc;
2208 gpio = devm_gpiod_get_index(dev, name, index);
2210 if (PTR_ERR(gpio) == -ENOENT) {
2215 return PTR_ERR(gpio);
2217 res = gpiod_direction_output(gpio, !value);
2219 dev_err(dev, "unable to toggle gpio %s: %i\n", name, res);
2220 devm_gpiod_put(dev, gpio);
2225 usleep_range(nsdelay, 2 * nsdelay);
2226 gpiod_set_value_cansleep(gpio, value);
2236 * dev->base_addr == 0, try to find all possible locations
2237 * dev->base_addr > 0x1ff, this is the address to check
2238 * dev->base_addr == <anything else>, return failure code
2241 * 0 --> there is a device
2242 * anything else, error
2244 static int smc_drv_probe(struct platform_device *pdev)
2246 struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev);
2247 const struct of_device_id *match = NULL;
2248 struct smc_local *lp;
2249 struct net_device *ndev;
2250 struct resource *res;
2251 unsigned int __iomem *addr;
2252 unsigned long irq_flags = SMC_IRQ_FLAGS;
2253 unsigned long irq_resflags;
2256 ndev = alloc_etherdev(sizeof(struct smc_local));
2261 SET_NETDEV_DEV(ndev, &pdev->dev);
2263 /* get configuration from platform data, only allow use of
2264 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
2267 lp = netdev_priv(ndev);
2271 memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2272 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
2275 #if IS_BUILTIN(CONFIG_OF)
2276 match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev);
2278 struct device_node *np = pdev->dev.of_node;
2281 /* Optional pwrdwn GPIO configured? */
2282 ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio,
2283 "power", 0, 0, 100);
2288 * Optional reset GPIO configured? Minimum 100 ns reset needed
2289 * according to LAN91C96 datasheet page 14.
2291 ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio,
2292 "reset", 0, 0, 100);
2297 * Need to wait for optional EEPROM to load, max 750 us according
2298 * to LAN91C96 datasheet page 55.
2301 usleep_range(750, 1000);
2303 /* Combination of IO widths supported, default to 16-bit */
2304 if (!of_property_read_u32(np, "reg-io-width", &val)) {
2306 lp->cfg.flags |= SMC91X_USE_8BIT;
2307 if ((val == 0) || (val & 2))
2308 lp->cfg.flags |= SMC91X_USE_16BIT;
2310 lp->cfg.flags |= SMC91X_USE_32BIT;
2312 lp->cfg.flags |= SMC91X_USE_16BIT;
2317 if (!pd && !match) {
2318 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0;
2319 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0;
2320 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0;
2321 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
2324 if (!lp->cfg.leda && !lp->cfg.ledb) {
2325 lp->cfg.leda = RPC_LSA_DEFAULT;
2326 lp->cfg.ledb = RPC_LSB_DEFAULT;
2329 ndev->dma = (unsigned char)-1;
2331 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2333 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2336 goto out_free_netdev;
2340 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
2342 goto out_free_netdev;
2345 ndev->irq = platform_get_irq(pdev, 0);
2346 if (ndev->irq <= 0) {
2348 goto out_release_io;
2351 * If this platform does not specify any special irqflags, or if
2352 * the resource supplies a trigger, override the irqflags with
2353 * the trigger flags from the resource.
2355 irq_resflags = irqd_get_trigger_type(irq_get_irq_data(ndev->irq));
2356 if (irq_flags == -1 || irq_resflags & IRQF_TRIGGER_MASK)
2357 irq_flags = irq_resflags & IRQF_TRIGGER_MASK;
2359 ret = smc_request_attrib(pdev, ndev);
2361 goto out_release_io;
2362 #if defined(CONFIG_ASSABET_NEPONSET)
2363 if (machine_is_assabet() && machine_has_neponset())
2364 neponset_ncr_set(NCR_ENET_OSC_EN);
2366 platform_set_drvdata(pdev, ndev);
2367 ret = smc_enable_device(pdev);
2369 goto out_release_attrib;
2371 addr = ioremap(res->start, SMC_IO_EXTENT);
2374 goto out_release_attrib;
2377 #ifdef CONFIG_ARCH_PXA
2379 struct smc_local *lp = netdev_priv(ndev);
2380 lp->device = &pdev->dev;
2381 lp->physaddr = res->start;
2385 ret = smc_probe(ndev, addr, irq_flags);
2389 smc_request_datacs(pdev, ndev);
2396 smc_release_attrib(pdev, ndev);
2398 release_mem_region(res->start, SMC_IO_EXTENT);
2402 pr_info("%s: not found (%d).\n", CARDNAME, ret);
2407 static int smc_drv_remove(struct platform_device *pdev)
2409 struct net_device *ndev = platform_get_drvdata(pdev);
2410 struct smc_local *lp = netdev_priv(ndev);
2411 struct resource *res;
2413 unregister_netdev(ndev);
2415 free_irq(ndev->irq, ndev);
2417 #ifdef CONFIG_ARCH_PXA
2418 if (ndev->dma != (unsigned char)-1)
2419 pxa_free_dma(ndev->dma);
2423 smc_release_datacs(pdev,ndev);
2424 smc_release_attrib(pdev,ndev);
2426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2428 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2429 release_mem_region(res->start, SMC_IO_EXTENT);
2436 static int smc_drv_suspend(struct device *dev)
2438 struct platform_device *pdev = to_platform_device(dev);
2439 struct net_device *ndev = platform_get_drvdata(pdev);
2442 if (netif_running(ndev)) {
2443 netif_device_detach(ndev);
2445 smc_phy_powerdown(ndev);
2451 static int smc_drv_resume(struct device *dev)
2453 struct platform_device *pdev = to_platform_device(dev);
2454 struct net_device *ndev = platform_get_drvdata(pdev);
2457 struct smc_local *lp = netdev_priv(ndev);
2458 smc_enable_device(pdev);
2459 if (netif_running(ndev)) {
2462 if (lp->phy_type != 0)
2463 smc_phy_configure(&lp->phy_configure);
2464 netif_device_attach(ndev);
2470 static struct dev_pm_ops smc_drv_pm_ops = {
2471 .suspend = smc_drv_suspend,
2472 .resume = smc_drv_resume,
2475 static struct platform_driver smc_driver = {
2476 .probe = smc_drv_probe,
2477 .remove = smc_drv_remove,
2480 .pm = &smc_drv_pm_ops,
2481 .of_match_table = of_match_ptr(smc91x_match),
2485 module_platform_driver(smc_driver);