1 /*******************************************************************************
2 Copyright (C) 2007-2009 STMicroelectronics Ltd
4 This program is free software; you can redistribute it and/or modify it
5 under the terms and conditions of the GNU General Public License,
6 version 2, as published by the Free Software Foundation.
8 This program is distributed in the hope it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 You should have received a copy of the GNU General Public License along with
14 this program; if not, write to the Free Software Foundation, Inc.,
15 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 The full GNU General Public License is included in this distribution in
18 the file called "COPYING".
20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 *******************************************************************************/
25 #include "dwmac_dma.h"
27 #define GMAC_HI_REG_AE 0x80000000
29 int dwmac_dma_reset(void __iomem *ioaddr)
31 u32 value = readl(ioaddr + DMA_BUS_MODE);
35 value |= DMA_BUS_MODE_SFT_RESET;
36 writel(value, ioaddr + DMA_BUS_MODE);
39 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
50 /* CSR1 enables the transmit DMA to check for new descriptor */
51 void dwmac_enable_dma_transmission(void __iomem *ioaddr)
53 writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
56 void dwmac_enable_dma_irq(void __iomem *ioaddr)
58 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
61 void dwmac_disable_dma_irq(void __iomem *ioaddr)
63 writel(0, ioaddr + DMA_INTR_ENA);
66 void dwmac_dma_start_tx(void __iomem *ioaddr)
68 u32 value = readl(ioaddr + DMA_CONTROL);
69 value |= DMA_CONTROL_ST;
70 writel(value, ioaddr + DMA_CONTROL);
73 void dwmac_dma_stop_tx(void __iomem *ioaddr)
75 u32 value = readl(ioaddr + DMA_CONTROL);
76 value &= ~DMA_CONTROL_ST;
77 writel(value, ioaddr + DMA_CONTROL);
80 void dwmac_dma_start_rx(void __iomem *ioaddr)
82 u32 value = readl(ioaddr + DMA_CONTROL);
83 value |= DMA_CONTROL_SR;
84 writel(value, ioaddr + DMA_CONTROL);
87 void dwmac_dma_stop_rx(void __iomem *ioaddr)
89 u32 value = readl(ioaddr + DMA_CONTROL);
90 value &= ~DMA_CONTROL_SR;
91 writel(value, ioaddr + DMA_CONTROL);
94 #ifdef DWMAC_DMA_DEBUG
95 static void show_tx_process_state(unsigned int status)
98 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
102 pr_debug("- TX (Stopped): Reset or Stop command\n");
105 pr_debug("- TX (Running):Fetching the Tx desc\n");
108 pr_debug("- TX (Running): Waiting for end of tx\n");
111 pr_debug("- TX (Running): Reading the data "
112 "and queuing the data into the Tx buf\n");
115 pr_debug("- TX (Suspended): Tx Buff Underflow "
116 "or an unavailable Transmit descriptor\n");
119 pr_debug("- TX (Running): Closing Tx descriptor\n");
126 static void show_rx_process_state(unsigned int status)
129 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
133 pr_debug("- RX (Stopped): Reset or Stop command\n");
136 pr_debug("- RX (Running): Fetching the Rx desc\n");
139 pr_debug("- RX (Running):Checking for end of pkt\n");
142 pr_debug("- RX (Running): Waiting for Rx pkt\n");
145 pr_debug("- RX (Suspended): Unavailable Rx buf\n");
148 pr_debug("- RX (Running): Closing Rx descriptor\n");
151 pr_debug("- RX(Running): Flushing the current frame"
152 " from the Rx buf\n");
155 pr_debug("- RX (Running): Queuing the Rx frame"
156 " from the Rx buf into memory\n");
164 int dwmac_dma_interrupt(void __iomem *ioaddr,
165 struct stmmac_extra_stats *x)
168 /* read the status register (CSR5) */
169 u32 intr_status = readl(ioaddr + DMA_STATUS);
171 #ifdef DWMAC_DMA_DEBUG
172 /* Enable it to monitor DMA rx/tx status in case of critical problems */
173 pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status);
174 show_tx_process_state(intr_status);
175 show_rx_process_state(intr_status);
177 /* ABNORMAL interrupts */
178 if (unlikely(intr_status & DMA_STATUS_AIS)) {
179 if (unlikely(intr_status & DMA_STATUS_UNF)) {
180 ret = tx_hard_error_bump_tc;
181 x->tx_undeflow_irq++;
183 if (unlikely(intr_status & DMA_STATUS_TJT))
186 if (unlikely(intr_status & DMA_STATUS_OVF))
187 x->rx_overflow_irq++;
189 if (unlikely(intr_status & DMA_STATUS_RU))
190 x->rx_buf_unav_irq++;
191 if (unlikely(intr_status & DMA_STATUS_RPS))
192 x->rx_process_stopped_irq++;
193 if (unlikely(intr_status & DMA_STATUS_RWT))
194 x->rx_watchdog_irq++;
195 if (unlikely(intr_status & DMA_STATUS_ETI))
197 if (unlikely(intr_status & DMA_STATUS_TPS)) {
198 x->tx_process_stopped_irq++;
201 if (unlikely(intr_status & DMA_STATUS_FBI)) {
202 x->fatal_bus_error_irq++;
206 /* TX/RX NORMAL interrupts */
207 if (likely(intr_status & DMA_STATUS_NIS)) {
209 if (likely(intr_status & DMA_STATUS_RI)) {
210 u32 value = readl(ioaddr + DMA_INTR_ENA);
211 /* to schedule NAPI on real RIE event. */
212 if (likely(value & DMA_INTR_ENA_RIE)) {
213 x->rx_normal_irq_n++;
217 if (likely(intr_status & DMA_STATUS_TI)) {
218 x->tx_normal_irq_n++;
221 if (unlikely(intr_status & DMA_STATUS_ERI))
224 /* Optional hardware blocks, interrupts should be disabled */
225 if (unlikely(intr_status &
226 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
227 pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
229 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
230 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
235 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
237 u32 csr6 = readl(ioaddr + DMA_CONTROL);
238 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
240 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
243 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
244 unsigned int high, unsigned int low)
248 data = (addr[5] << 8) | addr[4];
249 /* For MAC Addr registers se have to set the Address Enable (AE)
250 * bit that has no effect on the High Reg 0 where the bit 31 (MO)
253 writel(data | GMAC_HI_REG_AE, ioaddr + high);
254 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
255 writel(data, ioaddr + low);
258 /* Enable disable MAC RX/TX */
259 void stmmac_set_mac(void __iomem *ioaddr, bool enable)
261 u32 value = readl(ioaddr + MAC_CTRL_REG);
264 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
266 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
268 writel(value, ioaddr + MAC_CTRL_REG);
271 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
272 unsigned int high, unsigned int low)
274 unsigned int hi_addr, lo_addr;
276 /* Read the MAC address from the hardware */
277 hi_addr = readl(ioaddr + high);
278 lo_addr = readl(ioaddr + low);
280 /* Extract the MAC address from the high and low words */
281 addr[0] = lo_addr & 0xff;
282 addr[1] = (lo_addr >> 8) & 0xff;
283 addr[2] = (lo_addr >> 16) & 0xff;
284 addr[3] = (lo_addr >> 24) & 0xff;
285 addr[4] = hi_addr & 0xff;
286 addr[5] = (hi_addr >> 8) & 0xff;