drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_STMMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif /* CONFIG_STMMAC_DEBUG_FS */
  50 #include <linux/net_tstamp.h>
  51 #include "stmmac_ptp.h"
  52 #include "stmmac.h"
  53
  54 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  55 #define JUMBO_LEN       9000
  56
  57 /* Module parameters */
  58 #define TX_TIMEO        5000
  59 static int watchdog = TX_TIMEO;
  60 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  61 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  62
  63 static int debug = -1;
  64 module_param(debug, int, S_IRUGO | S_IWUSR);
  65 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  66
  67 static int phyaddr = -1;
  68 module_param(phyaddr, int, S_IRUGO);
  69 MODULE_PARM_DESC(phyaddr, "Physical device address");
  70
  71 #define DMA_TX_SIZE 256
  72 static int dma_txsize = DMA_TX_SIZE;
  73 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  74 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  75
  76 #define DMA_RX_SIZE 256
  77 static int dma_rxsize = DMA_RX_SIZE;
  78 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
  79 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
  80
  81 static int flow_ctrl = FLOW_OFF;
  82 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  83 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  84
  85 static int pause = PAUSE_TIME;
  86 module_param(pause, int, S_IRUGO | S_IWUSR);
  87 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  88
  89 #define TC_DEFAULT 64
  90 static int tc = TC_DEFAULT;
  91 module_param(tc, int, S_IRUGO | S_IWUSR);
  92 MODULE_PARM_DESC(tc, "DMA threshold control value");
  93
  94 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
  95 static int buf_sz = DMA_BUFFER_SIZE;
  96 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  97 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  98
  99 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 100                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 101                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 102
 103 #define STMMAC_DEFAULT_LPI_TIMER        1000
 104 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 105 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 106 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 107 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 108
 109 /* By default the driver will use the ring mode to manage tx and rx descriptors
 110  * but passing this value so user can force to use the chain instead of the ring
 111  */
 112 static unsigned int chain_mode;
 113 module_param(chain_mode, int, S_IRUGO);
 114 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 115
 116 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 117
 118 #ifdef CONFIG_STMMAC_DEBUG_FS
 119 static int stmmac_init_fs(struct net_device *dev);
 120 static void stmmac_exit_fs(void);
 121 #endif
 122
 123 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 124
 125 /**
 126  * stmmac_verify_args - verify the driver parameters.
 127  * Description: it verifies if some wrong parameter is passed to the driver.
 128  * Note that wrong parameters are replaced with the default values.
 129  */
 130 static void stmmac_verify_args(void)
 131 {
 132         if (unlikely(watchdog < 0))
 133                 watchdog = TX_TIMEO;
 134         if (unlikely(dma_rxsize < 0))
 135                 dma_rxsize = DMA_RX_SIZE;
 136         if (unlikely(dma_txsize < 0))
 137                 dma_txsize = DMA_TX_SIZE;
 138         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 139                 buf_sz = DMA_BUFFER_SIZE;
 140         if (unlikely(flow_ctrl > 1))
 141                 flow_ctrl = FLOW_AUTO;
 142         else if (likely(flow_ctrl < 0))
 143                 flow_ctrl = FLOW_OFF;
 144         if (unlikely((pause < 0) || (pause > 0xffff)))
 145                 pause = PAUSE_TIME;
 146         if (eee_timer < 0)
 147                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 148 }
 149
 150 /**
 151  * stmmac_clk_csr_set - dynamically set the MDC clock
 152  * @priv: driver private structure
 153  * Description: this is to dynamically set the MDC clock according to the csr
 154  * clock input.
 155  * Note:
 156  *      If a specific clk_csr value is passed from the platform
 157  *      this means that the CSR Clock Range selection cannot be
 158  *      changed at run-time and it is fixed (as reported in the driver
 159  *      documentation). Viceversa the driver will try to set the MDC
 160  *      clock dynamically according to the actual clock input.
 161  */
 162 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 163 {
 164         u32 clk_rate;
 165
 166         clk_rate = clk_get_rate(priv->stmmac_clk);
 167
 168         /* Platform provided default clk_csr would be assumed valid
 169          * for all other cases except for the below mentioned ones.
 170          * For values higher than the IEEE 802.3 specified frequency
 171          * we can not estimate the proper divider as it is not known
 172          * the frequency of clk_csr_i. So we do not change the default
 173          * divider.
 174          */
 175         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 176                 if (clk_rate < CSR_F_35M)
 177                         priv->clk_csr = STMMAC_CSR_20_35M;
 178                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 179                         priv->clk_csr = STMMAC_CSR_35_60M;
 180                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 181                         priv->clk_csr = STMMAC_CSR_60_100M;
 182                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 183                         priv->clk_csr = STMMAC_CSR_100_150M;
 184                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 185                         priv->clk_csr = STMMAC_CSR_150_250M;
 186                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 187                         priv->clk_csr = STMMAC_CSR_250_300M;
 188         }
 189 }
 190
 191 static void print_pkt(unsigned char *buf, int len)
 192 {
 193         int j;
 194         pr_debug("len = %d byte, buf addr: 0x%p", len, buf);
 195         for (j = 0; j < len; j++) {
 196                 if ((j % 16) == 0)
 197                         pr_debug("\n %03x:", j);
 198                 pr_debug(" %02x", buf[j]);
 199         }
 200         pr_debug("\n");
 201 }
 202
 203 /* minimum number of free TX descriptors required to wake up TX process */
 204 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 205
 206 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 207 {
 208         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 209 }
 210
 211 /**
 212  * stmmac_hw_fix_mac_speed: callback for speed selection
 213  * @priv: driver private structure
 214  * Description: on some platforms (e.g. ST), some HW system configuraton
 215  * registers have to be set according to the link speed negotiated.
 216  */
 217 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 218 {
 219         struct phy_device *phydev = priv->phydev;
 220
 221         if (likely(priv->plat->fix_mac_speed))
 222                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 223 }
 224
 225 /**
 226  * stmmac_enable_eee_mode: Check and enter in LPI mode
 227  * @priv: driver private structure
 228  * Description: this function is to verify and enter in LPI mode for EEE.
 229  */
 230 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 231 {
 232         /* Check and enter in LPI mode */
 233         if ((priv->dirty_tx == priv->cur_tx) &&
 234             (priv->tx_path_in_lpi_mode == false))
 235                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 236 }
 237
 238 /**
 239  * stmmac_disable_eee_mode: disable/exit from EEE
 240  * @priv: driver private structure
 241  * Description: this function is to exit and disable EEE in case of
 242  * LPI state is true. This is called by the xmit.
 243  */
 244 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 245 {
 246         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 247         del_timer_sync(&priv->eee_ctrl_timer);
 248         priv->tx_path_in_lpi_mode = false;
 249 }
 250
 251 /**
 252  * stmmac_eee_ctrl_timer: EEE TX SW timer.
 253  * @arg : data hook
 254  * Description:
 255  *  if there is no data transfer and if we are not in LPI state,
 256  *  then MAC Transmitter can be moved to LPI state.
 257  */
 258 static void stmmac_eee_ctrl_timer(unsigned long arg)
 259 {
 260         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 261
 262         stmmac_enable_eee_mode(priv);
 263         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 264 }
 265
 266 /**
 267  * stmmac_eee_init: init EEE
 268  * @priv: driver private structure
 269  * Description:
 270  *  If the EEE support has been enabled while configuring the driver,
 271  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 272  *  phy can also manage EEE, so enable the LPI state and start the timer
 273  *  to verify if the tx path can enter in LPI state.
 274  */
 275 bool stmmac_eee_init(struct stmmac_priv *priv)
 276 {
 277         bool ret = false;
 278
 279         /* Using PCS we cannot dial with the phy registers at this stage
 280          * so we do not support extra feature like EEE.
 281          */
 282         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 283             (priv->pcs == STMMAC_PCS_RTBI))
 284                 goto out;
 285
 286         /* MAC core supports the EEE feature. */
 287         if (priv->dma_cap.eee) {
 288                 /* Check if the PHY supports EEE */
 289                 if (phy_init_eee(priv->phydev, 1))
 290                         goto out;
 291
 292                 if (!priv->eee_active) {
 293                         priv->eee_active = 1;
 294                         init_timer(&priv->eee_ctrl_timer);
 295                         priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 296                         priv->eee_ctrl_timer.data = (unsigned long)priv;
 297                         priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
 298                         add_timer(&priv->eee_ctrl_timer);
 299
 300                         priv->hw->mac->set_eee_timer(priv->ioaddr,
 301                                                      STMMAC_DEFAULT_LIT_LS,
 302                                                      priv->tx_lpi_timer);
 303                 } else
 304                         /* Set HW EEE according to the speed */
 305                         priv->hw->mac->set_eee_pls(priv->ioaddr,
 306                                                    priv->phydev->link);
 307
 308                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 309
 310                 ret = true;
 311         }
 312 out:
 313         return ret;
 314 }
 315
 316 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
 317  * @priv: driver private structure
 318  * @entry : descriptor index to be used.
 319  * @skb : the socket buffer
 320  * Description :
 321  * This function will read timestamp from the descriptor & pass it to stack.
 322  * and also perform some sanity checks.
 323  */
 324 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 325                                    unsigned int entry, struct sk_buff *skb)
 326 {
 327         struct skb_shared_hwtstamps shhwtstamp;
 328         u64 ns;
 329         void *desc = NULL;
 330
 331         if (!priv->hwts_tx_en)
 332                 return;
 333
 334         /* exit if skb doesn't support hw tstamp */
 335         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 336                 return;
 337
 338         if (priv->adv_ts)
 339                 desc = (priv->dma_etx + entry);
 340         else
 341                 desc = (priv->dma_tx + entry);
 342
 343         /* check tx tstamp status */
 344         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 345                 return;
 346
 347         /* get the valid tstamp */
 348         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 349
 350         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 351         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 352         /* pass tstamp to stack */
 353         skb_tstamp_tx(skb, &shhwtstamp);
 354
 355         return;
 356 }
 357
 358 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
 359  * @priv: driver private structure
 360  * @entry : descriptor index to be used.
 361  * @skb : the socket buffer
 362  * Description :
 363  * This function will read received packet's timestamp from the descriptor
 364  * and pass it to stack. It also perform some sanity checks.
 365  */
 366 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 367                                    unsigned int entry, struct sk_buff *skb)
 368 {
 369         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 370         u64 ns;
 371         void *desc = NULL;
 372
 373         if (!priv->hwts_rx_en)
 374                 return;
 375
 376         if (priv->adv_ts)
 377                 desc = (priv->dma_erx + entry);
 378         else
 379                 desc = (priv->dma_rx + entry);
 380
 381         /* exit if rx tstamp is not valid */
 382         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 383                 return;
 384
 385         /* get valid tstamp */
 386         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 387         shhwtstamp = skb_hwtstamps(skb);
 388         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 389         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 390 }
 391
 392 /**
 393  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 394  *  @dev: device pointer.
 395  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 396  *  a proprietary structure used to pass information to the driver.
 397  *  Description:
 398  *  This function configures the MAC to enable/disable both outgoing(TX)
 399  *  and incoming(RX) packets time stamping based on user input.
 400  *  Return Value:
 401  *  0 on success and an appropriate -ve integer on failure.
 402  */
 403 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 404 {
 405         struct stmmac_priv *priv = netdev_priv(dev);
 406         struct hwtstamp_config config;
 407         struct timespec now;
 408         u64 temp = 0;
 409         u32 ptp_v2 = 0;
 410         u32 tstamp_all = 0;
 411         u32 ptp_over_ipv4_udp = 0;
 412         u32 ptp_over_ipv6_udp = 0;
 413         u32 ptp_over_ethernet = 0;
 414         u32 snap_type_sel = 0;
 415         u32 ts_master_en = 0;
 416         u32 ts_event_en = 0;
 417         u32 value = 0;
 418
 419         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 420                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 421                 priv->hwts_tx_en = 0;
 422                 priv->hwts_rx_en = 0;
 423
 424                 return -EOPNOTSUPP;
 425         }
 426
 427         if (copy_from_user(&config, ifr->ifr_data,
 428                            sizeof(struct hwtstamp_config)))
 429                 return -EFAULT;
 430
 431         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 432                  __func__, config.flags, config.tx_type, config.rx_filter);
 433
 434         /* reserved for future extensions */
 435         if (config.flags)
 436                 return -EINVAL;
 437
 438         if (config.tx_type != HWTSTAMP_TX_OFF &&
 439             config.tx_type != HWTSTAMP_TX_ON)
 440                 return -ERANGE;
 441
 442         if (priv->adv_ts) {
 443                 switch (config.rx_filter) {
 444                 case HWTSTAMP_FILTER_NONE:
 445                         /* time stamp no incoming packet at all */
 446                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 447                         break;
 448
 449                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 450                         /* PTP v1, UDP, any kind of event packet */
 451                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 452                         /* take time stamp for all event messages */
 453                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 454
 455                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 456                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 457                         break;
 458
 459                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 460                         /* PTP v1, UDP, Sync packet */
 461                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 462                         /* take time stamp for SYNC messages only */
 463                         ts_event_en = PTP_TCR_TSEVNTENA;
 464
 465                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 466                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 467                         break;
 468
 469                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 470                         /* PTP v1, UDP, Delay_req packet */
 471                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 472                         /* take time stamp for Delay_Req messages only */
 473                         ts_master_en = PTP_TCR_TSMSTRENA;
 474                         ts_event_en = PTP_TCR_TSEVNTENA;
 475
 476                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 477                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 478                         break;
 479
 480                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 481                         /* PTP v2, UDP, any kind of event packet */
 482                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 483                         ptp_v2 = PTP_TCR_TSVER2ENA;
 484                         /* take time stamp for all event messages */
 485                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 486
 487                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 488                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 489                         break;
 490
 491                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 492                         /* PTP v2, UDP, Sync packet */
 493                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 494                         ptp_v2 = PTP_TCR_TSVER2ENA;
 495                         /* take time stamp for SYNC messages only */
 496                         ts_event_en = PTP_TCR_TSEVNTENA;
 497
 498                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 499                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 500                         break;
 501
 502                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 503                         /* PTP v2, UDP, Delay_req packet */
 504                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 505                         ptp_v2 = PTP_TCR_TSVER2ENA;
 506                         /* take time stamp for Delay_Req messages only */
 507                         ts_master_en = PTP_TCR_TSMSTRENA;
 508                         ts_event_en = PTP_TCR_TSEVNTENA;
 509
 510                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 511                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 512                         break;
 513
 514                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 515                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 516                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 517                         ptp_v2 = PTP_TCR_TSVER2ENA;
 518                         /* take time stamp for all event messages */
 519                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 520
 521                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 522                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 523                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 524                         break;
 525
 526                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 527                         /* PTP v2/802.AS1, any layer, Sync packet */
 528                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 529                         ptp_v2 = PTP_TCR_TSVER2ENA;
 530                         /* take time stamp for SYNC messages only */
 531                         ts_event_en = PTP_TCR_TSEVNTENA;
 532
 533                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 534                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 535                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 536                         break;
 537
 538                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 539                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 540                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 541                         ptp_v2 = PTP_TCR_TSVER2ENA;
 542                         /* take time stamp for Delay_Req messages only */
 543                         ts_master_en = PTP_TCR_TSMSTRENA;
 544                         ts_event_en = PTP_TCR_TSEVNTENA;
 545
 546                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 547                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 548                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 549                         break;
 550
 551                 case HWTSTAMP_FILTER_ALL:
 552                         /* time stamp any incoming packet */
 553                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 554                         tstamp_all = PTP_TCR_TSENALL;
 555                         break;
 556
 557                 default:
 558                         return -ERANGE;
 559                 }
 560         } else {
 561                 switch (config.rx_filter) {
 562                 case HWTSTAMP_FILTER_NONE:
 563                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 564                         break;
 565                 default:
 566                         /* PTP v1, UDP, any kind of event packet */
 567                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 568                         break;
 569                 }
 570         }
 571         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 572         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 573
 574         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 575                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 576         else {
 577                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 578                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 579                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 580                          ts_master_en | snap_type_sel);
 581
 582                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 583
 584                 /* program Sub Second Increment reg */
 585                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 586
 587                 /* calculate default added value:
 588                  * formula is :
 589                  * addend = (2^32)/freq_div_ratio;
 590                  * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
 591                  * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
 592                  * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
 593                  *       achive 20ns accuracy.
 594                  *
 595                  * 2^x * y == (y << x), hence
 596                  * 2^32 * 50000000 ==> (50000000 << 32)
 597                  */
 598                 temp = (u64) (50000000ULL << 32);
 599                 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
 600                 priv->hw->ptp->config_addend(priv->ioaddr,
 601                                              priv->default_addend);
 602
 603                 /* initialize system time */
 604                 getnstimeofday(&now);
 605                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 606                                             now.tv_nsec);
 607         }
 608
 609         return copy_to_user(ifr->ifr_data, &config,
 610                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 611 }
 612
 613 /**
 614  * stmmac_init_ptp: init PTP
 615  * @priv: driver private structure
 616  * Description: this is to verify if the HW supports the PTPv1 or v2.
 617  * This is done by looking at the HW cap. register.
 618  * Also it registers the ptp driver.
 619  */
 620 static int stmmac_init_ptp(struct stmmac_priv *priv)
 621 {
 622         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 623                 return -EOPNOTSUPP;
 624
 625         priv->adv_ts = 0;
 626         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 627                 priv->adv_ts = 1;
 628
 629         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 630                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 631
 632         if (netif_msg_hw(priv) && priv->adv_ts)
 633                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 634
 635         priv->hw->ptp = &stmmac_ptp;
 636         priv->hwts_tx_en = 0;
 637         priv->hwts_rx_en = 0;
 638
 639         return stmmac_ptp_register(priv);
 640 }
 641
 642 static void stmmac_release_ptp(struct stmmac_priv *priv)
 643 {
 644         stmmac_ptp_unregister(priv);
 645 }
 646
 647 /**
 648  * stmmac_adjust_link
 649  * @dev: net device structure
 650  * Description: it adjusts the link parameters.
 651  */
 652 static void stmmac_adjust_link(struct net_device *dev)
 653 {
 654         struct stmmac_priv *priv = netdev_priv(dev);
 655         struct phy_device *phydev = priv->phydev;
 656         unsigned long flags;
 657         int new_state = 0;
 658         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 659
 660         if (phydev == NULL)
 661                 return;
 662
 663         spin_lock_irqsave(&priv->lock, flags);
 664
 665         if (phydev->link) {
 666                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 667
 668                 /* Now we make sure that we can be in full duplex mode.
 669                  * If not, we operate in half-duplex mode. */
 670                 if (phydev->duplex != priv->oldduplex) {
 671                         new_state = 1;
 672                         if (!(phydev->duplex))
 673                                 ctrl &= ~priv->hw->link.duplex;
 674                         else
 675                                 ctrl |= priv->hw->link.duplex;
 676                         priv->oldduplex = phydev->duplex;
 677                 }
 678                 /* Flow Control operation */
 679                 if (phydev->pause)
 680                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 681                                                  fc, pause_time);
 682
 683                 if (phydev->speed != priv->speed) {
 684                         new_state = 1;
 685                         switch (phydev->speed) {
 686                         case 1000:
 687                                 if (likely(priv->plat->has_gmac))
 688                                         ctrl &= ~priv->hw->link.port;
 689                                 stmmac_hw_fix_mac_speed(priv);
 690                                 break;
 691                         case 100:
 692                         case 10:
 693                                 if (priv->plat->has_gmac) {
 694                                         ctrl |= priv->hw->link.port;
 695                                         if (phydev->speed == SPEED_100) {
 696                                                 ctrl |= priv->hw->link.speed;
 697                                         } else {
 698                                                 ctrl &= ~(priv->hw->link.speed);
 699                                         }
 700                                 } else {
 701                                         ctrl &= ~priv->hw->link.port;
 702                                 }
 703                                 stmmac_hw_fix_mac_speed(priv);
 704                                 break;
 705                         default:
 706                                 if (netif_msg_link(priv))
 707                                         pr_warn("%s: Speed (%d) not 10/100\n",
 708                                                 dev->name, phydev->speed);
 709                                 break;
 710                         }
 711
 712                         priv->speed = phydev->speed;
 713                 }
 714
 715                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 716
 717                 if (!priv->oldlink) {
 718                         new_state = 1;
 719                         priv->oldlink = 1;
 720                 }
 721         } else if (priv->oldlink) {
 722                 new_state = 1;
 723                 priv->oldlink = 0;
 724                 priv->speed = 0;
 725                 priv->oldduplex = -1;
 726         }
 727
 728         if (new_state && netif_msg_link(priv))
 729                 phy_print_status(phydev);
 730
 731         /* At this stage, it could be needed to setup the EEE or adjust some
 732          * MAC related HW registers.
 733          */
 734         priv->eee_enabled = stmmac_eee_init(priv);
 735
 736         spin_unlock_irqrestore(&priv->lock, flags);
 737 }
 738
 739 /**
 740  * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
 741  * @priv: driver private structure
 742  * Description: this is to verify if the HW supports the PCS.
 743  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 744  * configured for the TBI, RTBI, or SGMII PHY interface.
 745  */
 746 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 747 {
 748         int interface = priv->plat->interface;
 749
 750         if (priv->dma_cap.pcs) {
 751                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 752                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 753                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 754                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 755                         pr_debug("STMMAC: PCS RGMII support enable\n");
 756                         priv->pcs = STMMAC_PCS_RGMII;
 757                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 758                         pr_debug("STMMAC: PCS SGMII support enable\n");
 759                         priv->pcs = STMMAC_PCS_SGMII;
 760                 }
 761         }
 762 }
 763
 764 /**
 765  * stmmac_init_phy - PHY initialization
 766  * @dev: net device structure
 767  * Description: it initializes the driver's PHY state, and attaches the PHY
 768  * to the mac driver.
 769  *  Return value:
 770  *  0 on success
 771  */
 772 static int stmmac_init_phy(struct net_device *dev)
 773 {
 774         struct stmmac_priv *priv = netdev_priv(dev);
 775         struct phy_device *phydev;
 776         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 777         char bus_id[MII_BUS_ID_SIZE];
 778         int interface = priv->plat->interface;
 779         int max_speed = priv->plat->max_speed;
 780         priv->oldlink = 0;
 781         priv->speed = 0;
 782         priv->oldduplex = -1;
 783
 784         if (priv->plat->phy_bus_name)
 785                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 786                          priv->plat->phy_bus_name, priv->plat->bus_id);
 787         else
 788                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 789                          priv->plat->bus_id);
 790
 791         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 792                  priv->plat->phy_addr);
 793         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 794
 795         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 796
 797         if (IS_ERR(phydev)) {
 798                 pr_err("%s: Could not attach to PHY\n", dev->name);
 799                 return PTR_ERR(phydev);
 800         }
 801
 802         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 803         if ((interface == PHY_INTERFACE_MODE_MII) ||
 804             (interface == PHY_INTERFACE_MODE_RMII) ||
 805                 (max_speed < 1000 &&  max_speed > 0))
 806                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 807                                          SUPPORTED_1000baseT_Full);
 808
 809         /*
 810          * Broken HW is sometimes missing the pull-up resistor on the
 811          * MDIO line, which results in reads to non-existent devices returning
 812          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 813          * device as well.
 814          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 815          */
 816         if (phydev->phy_id == 0) {
 817                 phy_disconnect(phydev);
 818                 return -ENODEV;
 819         }
 820         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 821                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 822
 823         priv->phydev = phydev;
 824
 825         return 0;
 826 }
 827
 828 /**
 829  * stmmac_display_ring: display ring
 830  * @head: pointer to the head of the ring passed.
 831  * @size: size of the ring.
 832  * @extend_desc: to verify if extended descriptors are used.
 833  * Description: display the control/status and buffer descriptors.
 834  */
 835 static void stmmac_display_ring(void *head, int size, int extend_desc)
 836 {
 837         int i;
 838         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 839         struct dma_desc *p = (struct dma_desc *)head;
 840
 841         for (i = 0; i < size; i++) {
 842                 u64 x;
 843                 if (extend_desc) {
 844                         x = *(u64 *) ep;
 845                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 846                                 i, (unsigned int)virt_to_phys(ep),
 847                                 (unsigned int)x, (unsigned int)(x >> 32),
 848                                 ep->basic.des2, ep->basic.des3);
 849                         ep++;
 850                 } else {
 851                         x = *(u64 *) p;
 852                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 853                                 i, (unsigned int)virt_to_phys(p),
 854                                 (unsigned int)x, (unsigned int)(x >> 32),
 855                                 p->des2, p->des3);
 856                         p++;
 857                 }
 858                 pr_info("\n");
 859         }
 860 }
 861
 862 static void stmmac_display_rings(struct stmmac_priv *priv)
 863 {
 864         unsigned int txsize = priv->dma_tx_size;
 865         unsigned int rxsize = priv->dma_rx_size;
 866
 867         if (priv->extend_desc) {
 868                 pr_info("Extended RX descriptor ring:\n");
 869                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 870                 pr_info("Extended TX descriptor ring:\n");
 871                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 872         } else {
 873                 pr_info("RX descriptor ring:\n");
 874                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 875                 pr_info("TX descriptor ring:\n");
 876                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 877         }
 878 }
 879
 880 static int stmmac_set_bfsize(int mtu, int bufsize)
 881 {
 882         int ret = bufsize;
 883
 884         if (mtu >= BUF_SIZE_4KiB)
 885                 ret = BUF_SIZE_8KiB;
 886         else if (mtu >= BUF_SIZE_2KiB)
 887                 ret = BUF_SIZE_4KiB;
 888         else if (mtu >= DMA_BUFFER_SIZE)
 889                 ret = BUF_SIZE_2KiB;
 890         else
 891                 ret = DMA_BUFFER_SIZE;
 892
 893         return ret;
 894 }
 895
 896 /**
 897  * stmmac_clear_descriptors: clear descriptors
 898  * @priv: driver private structure
 899  * Description: this function is called to clear the tx and rx descriptors
 900  * in case of both basic and extended descriptors are used.
 901  */
 902 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 903 {
 904         int i;
 905         unsigned int txsize = priv->dma_tx_size;
 906         unsigned int rxsize = priv->dma_rx_size;
 907
 908         /* Clear the Rx/Tx descriptors */
 909         for (i = 0; i < rxsize; i++)
 910                 if (priv->extend_desc)
 911                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 912                                                      priv->use_riwt, priv->mode,
 913                                                      (i == rxsize - 1));
 914                 else
 915                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 916                                                      priv->use_riwt, priv->mode,
 917                                                      (i == rxsize - 1));
 918         for (i = 0; i < txsize; i++)
 919                 if (priv->extend_desc)
 920                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 921                                                      priv->mode,
 922                                                      (i == txsize - 1));
 923                 else
 924                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 925                                                      priv->mode,
 926                                                      (i == txsize - 1));
 927 }
 928
 929 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 930                                   int i)
 931 {
 932         struct sk_buff *skb;
 933
 934         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 935                                  GFP_KERNEL);
 936         if (!skb) {
 937                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 938                 return -ENOMEM;
 939         }
 940         skb_reserve(skb, NET_IP_ALIGN);
 941         priv->rx_skbuff[i] = skb;
 942         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 943                                                 priv->dma_buf_sz,
 944                                                 DMA_FROM_DEVICE);
 945         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 946                 pr_err("%s: DMA mapping error\n", __func__);
 947                 dev_kfree_skb_any(skb);
 948                 return -EINVAL;
 949         }
 950
 951         p->des2 = priv->rx_skbuff_dma[i];
 952
 953         if ((priv->mode == STMMAC_RING_MODE) &&
 954             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 955                 priv->hw->ring->init_desc3(p);
 956
 957         return 0;
 958 }
 959
 960 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
 961 {
 962         if (priv->rx_skbuff[i]) {
 963                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 964                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
 965                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 966         }
 967         priv->rx_skbuff[i] = NULL;
 968 }
 969
 970 /**
 971  * init_dma_desc_rings - init the RX/TX descriptor rings
 972  * @dev: net device structure
 973  * Description:  this function initializes the DMA RX/TX descriptors
 974  * and allocates the socket buffers. It suppors the chained and ring
 975  * modes.
 976  */
 977 static int init_dma_desc_rings(struct net_device *dev)
 978 {
 979         int i;
 980         struct stmmac_priv *priv = netdev_priv(dev);
 981         unsigned int txsize = priv->dma_tx_size;
 982         unsigned int rxsize = priv->dma_rx_size;
 983         unsigned int bfsize = 0;
 984         int ret = -ENOMEM;
 985
 986         /* Set the max buffer size according to the DESC mode
 987          * and the MTU. Note that RING mode allows 16KiB bsize.
 988          */
 989         if (priv->mode == STMMAC_RING_MODE)
 990                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 991
 992         if (bfsize < BUF_SIZE_16KiB)
 993                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 994
 995         if (netif_msg_probe(priv))
 996                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
 997                          txsize, rxsize, bfsize);
 998
 999         if (netif_msg_probe(priv)) {
1000                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1001                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1002
1003                 /* RX INITIALIZATION */
1004                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1005         }
1006         for (i = 0; i < rxsize; i++) {
1007                 struct dma_desc *p;
1008                 if (priv->extend_desc)
1009                         p = &((priv->dma_erx + i)->basic);
1010                 else
1011                         p = priv->dma_rx + i;
1012
1013                 ret = stmmac_init_rx_buffers(priv, p, i);
1014                 if (ret)
1015                         goto err_init_rx_buffers;
1016
1017                 if (netif_msg_probe(priv))
1018                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1019                                  priv->rx_skbuff[i]->data,
1020                                  (unsigned int)priv->rx_skbuff_dma[i]);
1021         }
1022         priv->cur_rx = 0;
1023         priv->dirty_rx = (unsigned int)(i - rxsize);
1024         priv->dma_buf_sz = bfsize;
1025         buf_sz = bfsize;
1026
1027         /* Setup the chained descriptor addresses */
1028         if (priv->mode == STMMAC_CHAIN_MODE) {
1029                 if (priv->extend_desc) {
1030                         priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1031                                               rxsize, 1);
1032                         priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1033                                               txsize, 1);
1034                 } else {
1035                         priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1036                                               rxsize, 0);
1037                         priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1038                                               txsize, 0);
1039                 }
1040         }
1041
1042         /* TX INITIALIZATION */
1043         for (i = 0; i < txsize; i++) {
1044                 struct dma_desc *p;
1045                 if (priv->extend_desc)
1046                         p = &((priv->dma_etx + i)->basic);
1047                 else
1048                         p = priv->dma_tx + i;
1049                 p->des2 = 0;
1050                 priv->tx_skbuff_dma[i] = 0;
1051                 priv->tx_skbuff[i] = NULL;
1052         }
1053
1054         priv->dirty_tx = 0;
1055         priv->cur_tx = 0;
1056
1057         stmmac_clear_descriptors(priv);
1058
1059         if (netif_msg_hw(priv))
1060                 stmmac_display_rings(priv);
1061
1062         return 0;
1063 err_init_rx_buffers:
1064         while (--i >= 0)
1065                 stmmac_free_rx_buffers(priv, i);
1066         return ret;
1067 }
1068
1069 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1070 {
1071         int i;
1072
1073         for (i = 0; i < priv->dma_rx_size; i++)
1074                 stmmac_free_rx_buffers(priv, i);
1075 }
1076
1077 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1078 {
1079         int i;
1080
1081         for (i = 0; i < priv->dma_tx_size; i++) {
1082                 if (priv->tx_skbuff[i] != NULL) {
1083                         struct dma_desc *p;
1084                         if (priv->extend_desc)
1085                                 p = &((priv->dma_etx + i)->basic);
1086                         else
1087                                 p = priv->dma_tx + i;
1088
1089                         if (priv->tx_skbuff_dma[i])
1090                                 dma_unmap_single(priv->device,
1091                                                  priv->tx_skbuff_dma[i],
1092                                                  priv->hw->desc->get_tx_len(p),
1093                                                  DMA_TO_DEVICE);
1094                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1095                         priv->tx_skbuff[i] = NULL;
1096                         priv->tx_skbuff_dma[i] = 0;
1097                 }
1098         }
1099 }
1100
1101 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1102 {
1103         unsigned int txsize = priv->dma_tx_size;
1104         unsigned int rxsize = priv->dma_rx_size;
1105         int ret = -ENOMEM;
1106
1107         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1108                                             GFP_KERNEL);
1109         if (!priv->rx_skbuff_dma)
1110                 return -ENOMEM;
1111
1112         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1113                                         GFP_KERNEL);
1114         if (!priv->rx_skbuff)
1115                 goto err_rx_skbuff;
1116
1117         priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1118                                             GFP_KERNEL);
1119         if (!priv->tx_skbuff_dma)
1120                 goto err_tx_skbuff_dma;
1121
1122         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1123                                         GFP_KERNEL);
1124         if (!priv->tx_skbuff)
1125                 goto err_tx_skbuff;
1126
1127         if (priv->extend_desc) {
1128                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1129                                                    sizeof(struct
1130                                                           dma_extended_desc),
1131                                                    &priv->dma_rx_phy,
1132                                                    GFP_KERNEL);
1133                 if (!priv->dma_erx)
1134                         goto err_dma;
1135
1136                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1137                                                    sizeof(struct
1138                                                           dma_extended_desc),
1139                                                    &priv->dma_tx_phy,
1140                                                    GFP_KERNEL);
1141                 if (!priv->dma_etx) {
1142                         dma_free_coherent(priv->device, priv->dma_rx_size *
1143                                         sizeof(struct dma_extended_desc),
1144                                         priv->dma_erx, priv->dma_rx_phy);
1145                         goto err_dma;
1146                 }
1147         } else {
1148                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1149                                                   sizeof(struct dma_desc),
1150                                                   &priv->dma_rx_phy,
1151                                                   GFP_KERNEL);
1152                 if (!priv->dma_rx)
1153                         goto err_dma;
1154
1155                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1156                                                   sizeof(struct dma_desc),
1157                                                   &priv->dma_tx_phy,
1158                                                   GFP_KERNEL);
1159                 if (!priv->dma_tx) {
1160                         dma_free_coherent(priv->device, priv->dma_rx_size *
1161                                         sizeof(struct dma_desc),
1162                                         priv->dma_rx, priv->dma_rx_phy);
1163                         goto err_dma;
1164                 }
1165         }
1166
1167         return 0;
1168
1169 err_dma:
1170         kfree(priv->tx_skbuff);
1171 err_tx_skbuff:
1172         kfree(priv->tx_skbuff_dma);
1173 err_tx_skbuff_dma:
1174         kfree(priv->rx_skbuff);
1175 err_rx_skbuff:
1176         kfree(priv->rx_skbuff_dma);
1177         return ret;
1178 }
1179
1180 static void free_dma_desc_resources(struct stmmac_priv *priv)
1181 {
1182         /* Release the DMA TX/RX socket buffers */
1183         dma_free_rx_skbufs(priv);
1184         dma_free_tx_skbufs(priv);
1185
1186         /* Free DMA regions of consistent memory previously allocated */
1187         if (!priv->extend_desc) {
1188                 dma_free_coherent(priv->device,
1189                                   priv->dma_tx_size * sizeof(struct dma_desc),
1190                                   priv->dma_tx, priv->dma_tx_phy);
1191                 dma_free_coherent(priv->device,
1192                                   priv->dma_rx_size * sizeof(struct dma_desc),
1193                                   priv->dma_rx, priv->dma_rx_phy);
1194         } else {
1195                 dma_free_coherent(priv->device, priv->dma_tx_size *
1196                                   sizeof(struct dma_extended_desc),
1197                                   priv->dma_etx, priv->dma_tx_phy);
1198                 dma_free_coherent(priv->device, priv->dma_rx_size *
1199                                   sizeof(struct dma_extended_desc),
1200                                   priv->dma_erx, priv->dma_rx_phy);
1201         }
1202         kfree(priv->rx_skbuff_dma);
1203         kfree(priv->rx_skbuff);
1204         kfree(priv->tx_skbuff_dma);
1205         kfree(priv->tx_skbuff);
1206 }
1207
1208 /**
1209  *  stmmac_dma_operation_mode - HW DMA operation mode
1210  *  @priv: driver private structure
1211  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1212  *  or Store-And-Forward capability.
1213  */
1214 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1215 {
1216         if (priv->plat->force_thresh_dma_mode)
1217                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1218         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1219                 /*
1220                  * In case of GMAC, SF mode can be enabled
1221                  * to perform the TX COE in HW. This depends on:
1222                  * 1) TX COE if actually supported
1223                  * 2) There is no bugged Jumbo frame support
1224                  *    that needs to not insert csum in the TDES.
1225                  */
1226                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1227                 tc = SF_DMA_MODE;
1228         } else
1229                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1230 }
1231
1232 /**
1233  * stmmac_tx_clean:
1234  * @priv: driver private structure
1235  * Description: it reclaims resources after transmission completes.
1236  */
1237 static void stmmac_tx_clean(struct stmmac_priv *priv)
1238 {
1239         unsigned int txsize = priv->dma_tx_size;
1240
1241         spin_lock(&priv->tx_lock);
1242
1243         priv->xstats.tx_clean++;
1244
1245         while (priv->dirty_tx != priv->cur_tx) {
1246                 int last;
1247                 unsigned int entry = priv->dirty_tx % txsize;
1248                 struct sk_buff *skb = priv->tx_skbuff[entry];
1249                 struct dma_desc *p;
1250
1251                 if (priv->extend_desc)
1252                         p = (struct dma_desc *)(priv->dma_etx + entry);
1253                 else
1254                         p = priv->dma_tx + entry;
1255
1256                 /* Check if the descriptor is owned by the DMA. */
1257                 if (priv->hw->desc->get_tx_owner(p))
1258                         break;
1259
1260                 /* Verify tx error by looking at the last segment. */
1261                 last = priv->hw->desc->get_tx_ls(p);
1262                 if (likely(last)) {
1263                         int tx_error =
1264                             priv->hw->desc->tx_status(&priv->dev->stats,
1265                                                       &priv->xstats, p,
1266                                                       priv->ioaddr);
1267                         if (likely(tx_error == 0)) {
1268                                 priv->dev->stats.tx_packets++;
1269                                 priv->xstats.tx_pkt_n++;
1270                         } else
1271                                 priv->dev->stats.tx_errors++;
1272
1273                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1274                 }
1275                 if (netif_msg_tx_done(priv))
1276                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1277                                  priv->cur_tx, priv->dirty_tx);
1278
1279                 if (likely(priv->tx_skbuff_dma[entry])) {
1280                         dma_unmap_single(priv->device,
1281                                          priv->tx_skbuff_dma[entry],
1282                                          priv->hw->desc->get_tx_len(p),
1283                                          DMA_TO_DEVICE);
1284                         priv->tx_skbuff_dma[entry] = 0;
1285                 }
1286                 priv->hw->ring->clean_desc3(priv, p);
1287
1288                 if (likely(skb != NULL)) {
1289                         dev_kfree_skb(skb);
1290                         priv->tx_skbuff[entry] = NULL;
1291                 }
1292
1293                 priv->hw->desc->release_tx_desc(p, priv->mode);
1294
1295                 priv->dirty_tx++;
1296         }
1297         if (unlikely(netif_queue_stopped(priv->dev) &&
1298                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1299                 netif_tx_lock(priv->dev);
1300                 if (netif_queue_stopped(priv->dev) &&
1301                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1302                         if (netif_msg_tx_done(priv))
1303                                 pr_debug("%s: restart transmit\n", __func__);
1304                         netif_wake_queue(priv->dev);
1305                 }
1306                 netif_tx_unlock(priv->dev);
1307         }
1308
1309         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1310                 stmmac_enable_eee_mode(priv);
1311                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1312         }
1313         spin_unlock(&priv->tx_lock);
1314 }
1315
1316 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1317 {
1318         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1319 }
1320
1321 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1322 {
1323         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1324 }
1325
1326 /**
1327  * stmmac_tx_err: irq tx error mng function
1328  * @priv: driver private structure
1329  * Description: it cleans the descriptors and restarts the transmission
1330  * in case of errors.
1331  */
1332 static void stmmac_tx_err(struct stmmac_priv *priv)
1333 {
1334         int i;
1335         int txsize = priv->dma_tx_size;
1336         netif_stop_queue(priv->dev);
1337
1338         priv->hw->dma->stop_tx(priv->ioaddr);
1339         dma_free_tx_skbufs(priv);
1340         for (i = 0; i < txsize; i++)
1341                 if (priv->extend_desc)
1342                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1343                                                      priv->mode,
1344                                                      (i == txsize - 1));
1345                 else
1346                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1347                                                      priv->mode,
1348                                                      (i == txsize - 1));
1349         priv->dirty_tx = 0;
1350         priv->cur_tx = 0;
1351         priv->hw->dma->start_tx(priv->ioaddr);
1352
1353         priv->dev->stats.tx_errors++;
1354         netif_wake_queue(priv->dev);
1355 }
1356
1357 /**
1358  * stmmac_dma_interrupt: DMA ISR
1359  * @priv: driver private structure
1360  * Description: this is the DMA ISR. It is called by the main ISR.
1361  * It calls the dwmac dma routine to understand which type of interrupt
1362  * happened. In case of there is a Normal interrupt and either TX or RX
1363  * interrupt happened so the NAPI is scheduled.
1364  */
1365 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1366 {
1367         int status;
1368
1369         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1370         if (likely((status & handle_rx)) || (status & handle_tx)) {
1371                 if (likely(napi_schedule_prep(&priv->napi))) {
1372                         stmmac_disable_dma_irq(priv);
1373                         __napi_schedule(&priv->napi);
1374                 }
1375         }
1376         if (unlikely(status & tx_hard_error_bump_tc)) {
1377                 /* Try to bump up the dma threshold on this failure */
1378                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1379                         tc += 64;
1380                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1381                         priv->xstats.threshold = tc;
1382                 }
1383         } else if (unlikely(status == tx_hard_error))
1384                 stmmac_tx_err(priv);
1385 }
1386
1387 /**
1388  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1389  * @priv: driver private structure
1390  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1391  */
1392 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1393 {
1394         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1395             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1396
1397         dwmac_mmc_intr_all_mask(priv->ioaddr);
1398
1399         if (priv->dma_cap.rmon) {
1400                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1401                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1402         } else
1403                 pr_info(" No MAC Management Counters available\n");
1404 }
1405
1406 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1407 {
1408         u32 hwid = priv->hw->synopsys_uid;
1409
1410         /* Check Synopsys Id (not available on old chips) */
1411         if (likely(hwid)) {
1412                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1413                 u32 synid = (hwid & 0x000000ff);
1414
1415                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1416                         uid, synid);
1417
1418                 return synid;
1419         }
1420         return 0;
1421 }
1422
1423 /**
1424  * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1425  * @priv: driver private structure
1426  * Description: select the Enhanced/Alternate or Normal descriptors.
1427  * In case of Enhanced/Alternate, it looks at the extended descriptors are
1428  * supported by the HW cap. register.
1429  */
1430 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1431 {
1432         if (priv->plat->enh_desc) {
1433                 pr_info(" Enhanced/Alternate descriptors\n");
1434
1435                 /* GMAC older than 3.50 has no extended descriptors */
1436                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1437                         pr_info("\tEnabled extended descriptors\n");
1438                         priv->extend_desc = 1;
1439                 } else
1440                         pr_warn("Extended descriptors not supported\n");
1441
1442                 priv->hw->desc = &enh_desc_ops;
1443         } else {
1444                 pr_info(" Normal descriptors\n");
1445                 priv->hw->desc = &ndesc_ops;
1446         }
1447 }
1448
1449 /**
1450  * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1451  * @priv: driver private structure
1452  * Description:
1453  *  new GMAC chip generations have a new register to indicate the
1454  *  presence of the optional feature/functions.
1455  *  This can be also used to override the value passed through the
1456  *  platform and necessary for old MAC10/100 and GMAC chips.
1457  */
1458 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1459 {
1460         u32 hw_cap = 0;
1461
1462         if (priv->hw->dma->get_hw_feature) {
1463                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1464
1465                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1466                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1467                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1468                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1469                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1470                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1471                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1472                 priv->dma_cap.pmt_remote_wake_up =
1473                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1474                 priv->dma_cap.pmt_magic_frame =
1475                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1476                 /* MMC */
1477                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1478                 /* IEEE 1588-2002 */
1479                 priv->dma_cap.time_stamp =
1480                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1481                 /* IEEE 1588-2008 */
1482                 priv->dma_cap.atime_stamp =
1483                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1484                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1485                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1486                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1487                 /* TX and RX csum */
1488                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1489                 priv->dma_cap.rx_coe_type1 =
1490                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1491                 priv->dma_cap.rx_coe_type2 =
1492                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1493                 priv->dma_cap.rxfifo_over_2048 =
1494                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1495                 /* TX and RX number of channels */
1496                 priv->dma_cap.number_rx_channel =
1497                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1498                 priv->dma_cap.number_tx_channel =
1499                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1500                 /* Alternate (enhanced) DESC mode */
1501                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1502         }
1503
1504         return hw_cap;
1505 }
1506
1507 /**
1508  * stmmac_check_ether_addr: check if the MAC addr is valid
1509  * @priv: driver private structure
1510  * Description:
1511  * it is to verify if the MAC address is valid, in case of failures it
1512  * generates a random MAC address
1513  */
1514 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1515 {
1516         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1517                 priv->hw->mac->get_umac_addr((void __iomem *)
1518                                              priv->dev->base_addr,
1519                                              priv->dev->dev_addr, 0);
1520                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1521                         eth_hw_addr_random(priv->dev);
1522         }
1523         pr_warn("%s: device MAC address %pM\n", priv->dev->name,
1524                 priv->dev->dev_addr);
1525 }
1526
1527 /**
1528  * stmmac_init_dma_engine: DMA init.
1529  * @priv: driver private structure
1530  * Description:
1531  * It inits the DMA invoking the specific MAC/GMAC callback.
1532  * Some DMA parameters can be passed from the platform;
1533  * in case of these are not passed a default is kept for the MAC or GMAC.
1534  */
1535 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1536 {
1537         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1538         int mixed_burst = 0;
1539         int atds = 0;
1540
1541         if (priv->plat->dma_cfg) {
1542                 pbl = priv->plat->dma_cfg->pbl;
1543                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1544                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1545                 burst_len = priv->plat->dma_cfg->burst_len;
1546         }
1547
1548         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1549                 atds = 1;
1550
1551         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1552                                    burst_len, priv->dma_tx_phy,
1553                                    priv->dma_rx_phy, atds);
1554 }
1555
1556 /**
1557  * stmmac_tx_timer: mitigation sw timer for tx.
1558  * @data: data pointer
1559  * Description:
1560  * This is the timer handler to directly invoke the stmmac_tx_clean.
1561  */
1562 static void stmmac_tx_timer(unsigned long data)
1563 {
1564         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1565
1566         stmmac_tx_clean(priv);
1567 }
1568
1569 /**
1570  * stmmac_init_tx_coalesce: init tx mitigation options.
1571  * @priv: driver private structure
1572  * Description:
1573  * This inits the transmit coalesce parameters: i.e. timer rate,
1574  * timer handler and default threshold used for enabling the
1575  * interrupt on completion bit.
1576  */
1577 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1578 {
1579         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1580         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1581         init_timer(&priv->txtimer);
1582         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1583         priv->txtimer.data = (unsigned long)priv;
1584         priv->txtimer.function = stmmac_tx_timer;
1585         add_timer(&priv->txtimer);
1586 }
1587
1588 /**
1589  * stmmac_hw_setup: setup mac in a usable state.
1590  *  @dev : pointer to the device structure.
1591  *  Description:
1592  *  This function sets up the ip in a usable state.
1593  *  Return value:
1594  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1595  *  file on failure.
1596  */
1597 static int stmmac_hw_setup(struct net_device *dev)
1598 {
1599         struct stmmac_priv *priv = netdev_priv(dev);
1600         int ret;
1601
1602         ret = init_dma_desc_rings(dev);
1603         if (ret < 0) {
1604                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1605                 return ret;
1606         }
1607         /* DMA initialization and SW reset */
1608         ret = stmmac_init_dma_engine(priv);
1609         if (ret < 0) {
1610                 pr_err("%s: DMA engine initialization failed\n", __func__);
1611                 return ret;
1612         }
1613
1614         /* Copy the MAC addr into the HW  */
1615         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1616
1617         /* If required, perform hw setup of the bus. */
1618         if (priv->plat->bus_setup)
1619                 priv->plat->bus_setup(priv->ioaddr);
1620
1621         /* Initialize the MAC Core */
1622         priv->hw->mac->core_init(priv->ioaddr);
1623
1624         /* Enable the MAC Rx/Tx */
1625         stmmac_set_mac(priv->ioaddr, true);
1626
1627         /* Set the HW DMA mode and the COE */
1628         stmmac_dma_operation_mode(priv);
1629
1630         stmmac_mmc_setup(priv);
1631
1632         ret = stmmac_init_ptp(priv);
1633         if (ret)
1634                 pr_warn("%s: failed PTP initialisation\n", __func__);
1635
1636 #ifdef CONFIG_STMMAC_DEBUG_FS
1637         ret = stmmac_init_fs(dev);
1638         if (ret < 0)
1639                 pr_warn("%s: failed debugFS registration\n", __func__);
1640 #endif
1641         /* Start the ball rolling... */
1642         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1643         priv->hw->dma->start_tx(priv->ioaddr);
1644         priv->hw->dma->start_rx(priv->ioaddr);
1645
1646         /* Dump DMA/MAC registers */
1647         if (netif_msg_hw(priv)) {
1648                 priv->hw->mac->dump_regs(priv->ioaddr);
1649                 priv->hw->dma->dump_regs(priv->ioaddr);
1650         }
1651         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1652
1653         priv->eee_enabled = stmmac_eee_init(priv);
1654
1655         stmmac_init_tx_coalesce(priv);
1656
1657         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1658                 priv->rx_riwt = MAX_DMA_RIWT;
1659                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1660         }
1661
1662         if (priv->pcs && priv->hw->mac->ctrl_ane)
1663                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1664
1665         return 0;
1666 }
1667
1668 /**
1669  *  stmmac_open - open entry point of the driver
1670  *  @dev : pointer to the device structure.
1671  *  Description:
1672  *  This function is the open entry point of the driver.
1673  *  Return value:
1674  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1675  *  file on failure.
1676  */
1677 static int stmmac_open(struct net_device *dev)
1678 {
1679         struct stmmac_priv *priv = netdev_priv(dev);
1680         int ret;
1681
1682         clk_prepare_enable(priv->stmmac_clk);
1683
1684         stmmac_check_ether_addr(priv);
1685
1686         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1687             priv->pcs != STMMAC_PCS_RTBI) {
1688                 ret = stmmac_init_phy(dev);
1689                 if (ret) {
1690                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1691                                __func__, ret);
1692                         goto phy_error;
1693                 }
1694         }
1695
1696         /* Extra statistics */
1697         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1698         priv->xstats.threshold = tc;
1699
1700         /* Create and initialize the TX/RX descriptors chains. */
1701         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1702         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1703         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1704
1705         alloc_dma_desc_resources(priv);
1706         if (ret < 0) {
1707                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1708                 goto dma_desc_error;
1709         }
1710
1711         ret = stmmac_hw_setup(dev);
1712         if (ret < 0) {
1713                 pr_err("%s: Hw setup failed\n", __func__);
1714                 goto init_error;
1715         }
1716
1717         if (priv->phydev)
1718                 phy_start(priv->phydev);
1719
1720         /* Request the IRQ lines */
1721         ret = request_irq(dev->irq, stmmac_interrupt,
1722                           IRQF_SHARED, dev->name, dev);
1723         if (unlikely(ret < 0)) {
1724                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1725                        __func__, dev->irq, ret);
1726                 goto init_error;
1727         }
1728
1729         /* Request the Wake IRQ in case of another line is used for WoL */
1730         if (priv->wol_irq != dev->irq) {
1731                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1732                                   IRQF_SHARED, dev->name, dev);
1733                 if (unlikely(ret < 0)) {
1734                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1735                                __func__, priv->wol_irq, ret);
1736                         goto wolirq_error;
1737                 }
1738         }
1739
1740         /* Request the IRQ lines */
1741         if (priv->lpi_irq != -ENXIO) {
1742                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1743                                   dev->name, dev);
1744                 if (unlikely(ret < 0)) {
1745                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1746                                __func__, priv->lpi_irq, ret);
1747                         goto lpiirq_error;
1748                 }
1749         }
1750
1751         napi_enable(&priv->napi);
1752         netif_start_queue(dev);
1753
1754         return 0;
1755
1756 lpiirq_error:
1757         if (priv->wol_irq != dev->irq)
1758                 free_irq(priv->wol_irq, dev);
1759 wolirq_error:
1760         free_irq(dev->irq, dev);
1761
1762 init_error:
1763         free_dma_desc_resources(priv);
1764 dma_desc_error:
1765         if (priv->phydev)
1766                 phy_disconnect(priv->phydev);
1767 phy_error:
1768         clk_disable_unprepare(priv->stmmac_clk);
1769
1770         return ret;
1771 }
1772
1773 /**
1774  *  stmmac_release - close entry point of the driver
1775  *  @dev : device pointer.
1776  *  Description:
1777  *  This is the stop entry point of the driver.
1778  */
1779 static int stmmac_release(struct net_device *dev)
1780 {
1781         struct stmmac_priv *priv = netdev_priv(dev);
1782
1783         if (priv->eee_enabled)
1784                 del_timer_sync(&priv->eee_ctrl_timer);
1785
1786         /* Stop and disconnect the PHY */
1787         if (priv->phydev) {
1788                 phy_stop(priv->phydev);
1789                 phy_disconnect(priv->phydev);
1790                 priv->phydev = NULL;
1791         }
1792
1793         netif_stop_queue(dev);
1794
1795         napi_disable(&priv->napi);
1796
1797         del_timer_sync(&priv->txtimer);
1798
1799         /* Free the IRQ lines */
1800         free_irq(dev->irq, dev);
1801         if (priv->wol_irq != dev->irq)
1802                 free_irq(priv->wol_irq, dev);
1803         if (priv->lpi_irq != -ENXIO)
1804                 free_irq(priv->lpi_irq, dev);
1805
1806         /* Stop TX/RX DMA and clear the descriptors */
1807         priv->hw->dma->stop_tx(priv->ioaddr);
1808         priv->hw->dma->stop_rx(priv->ioaddr);
1809
1810         /* Release and free the Rx/Tx resources */
1811         free_dma_desc_resources(priv);
1812
1813         /* Disable the MAC Rx/Tx */
1814         stmmac_set_mac(priv->ioaddr, false);
1815
1816         netif_carrier_off(dev);
1817
1818 #ifdef CONFIG_STMMAC_DEBUG_FS
1819         stmmac_exit_fs();
1820 #endif
1821         clk_disable_unprepare(priv->stmmac_clk);
1822
1823         stmmac_release_ptp(priv);
1824
1825         return 0;
1826 }
1827
1828 /**
1829  *  stmmac_xmit: Tx entry point of the driver
1830  *  @skb : the socket buffer
1831  *  @dev : device pointer
1832  *  Description : this is the tx entry point of the driver.
1833  *  It programs the chain or the ring and supports oversized frames
1834  *  and SG feature.
1835  */
1836 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1837 {
1838         struct stmmac_priv *priv = netdev_priv(dev);
1839         unsigned int txsize = priv->dma_tx_size;
1840         unsigned int entry;
1841         int i, csum_insertion = 0, is_jumbo = 0;
1842         int nfrags = skb_shinfo(skb)->nr_frags;
1843         struct dma_desc *desc, *first;
1844         unsigned int nopaged_len = skb_headlen(skb);
1845
1846         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1847                 if (!netif_queue_stopped(dev)) {
1848                         netif_stop_queue(dev);
1849                         /* This is a hard error, log it. */
1850                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1851                 }
1852                 return NETDEV_TX_BUSY;
1853         }
1854
1855         spin_lock(&priv->tx_lock);
1856
1857         if (priv->tx_path_in_lpi_mode)
1858                 stmmac_disable_eee_mode(priv);
1859
1860         entry = priv->cur_tx % txsize;
1861
1862         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1863
1864         if (priv->extend_desc)
1865                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1866         else
1867                 desc = priv->dma_tx + entry;
1868
1869         first = desc;
1870
1871         priv->tx_skbuff[entry] = skb;
1872
1873         /* To program the descriptors according to the size of the frame */
1874         if (priv->mode == STMMAC_RING_MODE) {
1875                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1876                                                         priv->plat->enh_desc);
1877                 if (unlikely(is_jumbo))
1878                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1879                                                           csum_insertion);
1880         } else {
1881                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1882                                                          priv->plat->enh_desc);
1883                 if (unlikely(is_jumbo))
1884                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1885                                                            csum_insertion);
1886         }
1887         if (likely(!is_jumbo)) {
1888                 desc->des2 = dma_map_single(priv->device, skb->data,
1889                                             nopaged_len, DMA_TO_DEVICE);
1890                 priv->tx_skbuff_dma[entry] = desc->des2;
1891                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1892                                                 csum_insertion, priv->mode);
1893         } else
1894                 desc = first;
1895
1896         for (i = 0; i < nfrags; i++) {
1897                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1898                 int len = skb_frag_size(frag);
1899
1900                 entry = (++priv->cur_tx) % txsize;
1901                 if (priv->extend_desc)
1902                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1903                 else
1904                         desc = priv->dma_tx + entry;
1905
1906                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1907                                               DMA_TO_DEVICE);
1908                 priv->tx_skbuff_dma[entry] = desc->des2;
1909                 priv->tx_skbuff[entry] = NULL;
1910                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1911                                                 priv->mode);
1912                 wmb();
1913                 priv->hw->desc->set_tx_owner(desc);
1914                 wmb();
1915         }
1916
1917         /* Finalize the latest segment. */
1918         priv->hw->desc->close_tx_desc(desc);
1919
1920         wmb();
1921         /* According to the coalesce parameter the IC bit for the latest
1922          * segment could be reset and the timer re-started to invoke the
1923          * stmmac_tx function. This approach takes care about the fragments.
1924          */
1925         priv->tx_count_frames += nfrags + 1;
1926         if (priv->tx_coal_frames > priv->tx_count_frames) {
1927                 priv->hw->desc->clear_tx_ic(desc);
1928                 priv->xstats.tx_reset_ic_bit++;
1929                 mod_timer(&priv->txtimer,
1930                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1931         } else
1932                 priv->tx_count_frames = 0;
1933
1934         /* To avoid raise condition */
1935         priv->hw->desc->set_tx_owner(first);
1936         wmb();
1937
1938         priv->cur_tx++;
1939
1940         if (netif_msg_pktdata(priv)) {
1941                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1942                         __func__, (priv->cur_tx % txsize),
1943                         (priv->dirty_tx % txsize), entry, first, nfrags);
1944
1945                 if (priv->extend_desc)
1946                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1947                 else
1948                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1949
1950                 pr_debug(">>> frame to be transmitted: ");
1951                 print_pkt(skb->data, skb->len);
1952         }
1953         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1954                 if (netif_msg_hw(priv))
1955                         pr_debug("%s: stop transmitted packets\n", __func__);
1956                 netif_stop_queue(dev);
1957         }
1958
1959         dev->stats.tx_bytes += skb->len;
1960
1961         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1962                      priv->hwts_tx_en)) {
1963                 /* declare that device is doing timestamping */
1964                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1965                 priv->hw->desc->enable_tx_timestamp(first);
1966         }
1967
1968         if (!priv->hwts_tx_en)
1969                 skb_tx_timestamp(skb);
1970
1971         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1972
1973         spin_unlock(&priv->tx_lock);
1974
1975         return NETDEV_TX_OK;
1976 }
1977
1978 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
1979 {
1980         struct ethhdr *ehdr;
1981         u16 vlanid;
1982
1983         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
1984             NETIF_F_HW_VLAN_CTAG_RX &&
1985             !__vlan_get_tag(skb, &vlanid)) {
1986                 /* pop the vlan tag */
1987                 ehdr = (struct ethhdr *)skb->data;
1988                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
1989                 skb_pull(skb, VLAN_HLEN);
1990                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
1991         }
1992 }
1993
1994
1995 /**
1996  * stmmac_rx_refill: refill used skb preallocated buffers
1997  * @priv: driver private structure
1998  * Description : this is to reallocate the skb for the reception process
1999  * that is based on zero-copy.
2000  */
2001 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2002 {
2003         unsigned int rxsize = priv->dma_rx_size;
2004         int bfsize = priv->dma_buf_sz;
2005
2006         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2007                 unsigned int entry = priv->dirty_rx % rxsize;
2008                 struct dma_desc *p;
2009
2010                 if (priv->extend_desc)
2011                         p = (struct dma_desc *)(priv->dma_erx + entry);
2012                 else
2013                         p = priv->dma_rx + entry;
2014
2015                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2016                         struct sk_buff *skb;
2017
2018                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2019
2020                         if (unlikely(skb == NULL))
2021                                 break;
2022
2023                         priv->rx_skbuff[entry] = skb;
2024                         priv->rx_skbuff_dma[entry] =
2025                             dma_map_single(priv->device, skb->data, bfsize,
2026                                            DMA_FROM_DEVICE);
2027
2028                         p->des2 = priv->rx_skbuff_dma[entry];
2029
2030                         priv->hw->ring->refill_desc3(priv, p);
2031
2032                         if (netif_msg_rx_status(priv))
2033                                 pr_debug("\trefill entry #%d\n", entry);
2034                 }
2035                 wmb();
2036                 priv->hw->desc->set_rx_owner(p);
2037                 wmb();
2038         }
2039 }
2040
2041 /**
2042  * stmmac_rx_refill: refill used skb preallocated buffers
2043  * @priv: driver private structure
2044  * @limit: napi bugget.
2045  * Description :  this the function called by the napi poll method.
2046  * It gets all the frames inside the ring.
2047  */
2048 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2049 {
2050         unsigned int rxsize = priv->dma_rx_size;
2051         unsigned int entry = priv->cur_rx % rxsize;
2052         unsigned int next_entry;
2053         unsigned int count = 0;
2054         int coe = priv->plat->rx_coe;
2055
2056         if (netif_msg_rx_status(priv)) {
2057                 pr_debug("%s: descriptor ring:\n", __func__);
2058                 if (priv->extend_desc)
2059                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2060                 else
2061                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2062         }
2063         while (count < limit) {
2064                 int status;
2065                 struct dma_desc *p;
2066
2067                 if (priv->extend_desc)
2068                         p = (struct dma_desc *)(priv->dma_erx + entry);
2069                 else
2070                         p = priv->dma_rx + entry;
2071
2072                 if (priv->hw->desc->get_rx_owner(p))
2073                         break;
2074
2075                 count++;
2076
2077                 next_entry = (++priv->cur_rx) % rxsize;
2078                 if (priv->extend_desc)
2079                         prefetch(priv->dma_erx + next_entry);
2080                 else
2081                         prefetch(priv->dma_rx + next_entry);
2082
2083                 /* read the status of the incoming frame */
2084                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2085                                                    &priv->xstats, p);
2086                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2087                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2088                                                            &priv->xstats,
2089                                                            priv->dma_erx +
2090                                                            entry);
2091                 if (unlikely(status == discard_frame)) {
2092                         priv->dev->stats.rx_errors++;
2093                         if (priv->hwts_rx_en && !priv->extend_desc) {
2094                                 /* DESC2 & DESC3 will be overwitten by device
2095                                  * with timestamp value, hence reinitialize
2096                                  * them in stmmac_rx_refill() function so that
2097                                  * device can reuse it.
2098                                  */
2099                                 priv->rx_skbuff[entry] = NULL;
2100                                 dma_unmap_single(priv->device,
2101                                                  priv->rx_skbuff_dma[entry],
2102                                                  priv->dma_buf_sz,
2103                                                  DMA_FROM_DEVICE);
2104                         }
2105                 } else {
2106                         struct sk_buff *skb;
2107                         int frame_len;
2108
2109                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2110
2111                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2112                          * Type frames (LLC/LLC-SNAP)
2113                          */
2114                         if (unlikely(status != llc_snap))
2115                                 frame_len -= ETH_FCS_LEN;
2116
2117                         if (netif_msg_rx_status(priv)) {
2118                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2119                                          p, entry, p->des2);
2120                                 if (frame_len > ETH_FRAME_LEN)
2121                                         pr_debug("\tframe size %d, COE: %d\n",
2122                                                  frame_len, status);
2123                         }
2124                         skb = priv->rx_skbuff[entry];
2125                         if (unlikely(!skb)) {
2126                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2127                                        priv->dev->name);
2128                                 priv->dev->stats.rx_dropped++;
2129                                 break;
2130                         }
2131                         prefetch(skb->data - NET_IP_ALIGN);
2132                         priv->rx_skbuff[entry] = NULL;
2133
2134                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2135
2136                         skb_put(skb, frame_len);
2137                         dma_unmap_single(priv->device,
2138                                          priv->rx_skbuff_dma[entry],
2139                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2140
2141                         if (netif_msg_pktdata(priv)) {
2142                                 pr_debug("frame received (%dbytes)", frame_len);
2143                                 print_pkt(skb->data, frame_len);
2144                         }
2145
2146                         stmmac_rx_vlan(priv->dev, skb);
2147
2148                         skb->protocol = eth_type_trans(skb, priv->dev);
2149
2150                         if (unlikely(!coe))
2151                                 skb_checksum_none_assert(skb);
2152                         else
2153                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2154
2155                         napi_gro_receive(&priv->napi, skb);
2156
2157                         priv->dev->stats.rx_packets++;
2158                         priv->dev->stats.rx_bytes += frame_len;
2159                 }
2160                 entry = next_entry;
2161         }
2162
2163         stmmac_rx_refill(priv);
2164
2165         priv->xstats.rx_pkt_n += count;
2166
2167         return count;
2168 }
2169
2170 /**
2171  *  stmmac_poll - stmmac poll method (NAPI)
2172  *  @napi : pointer to the napi structure.
2173  *  @budget : maximum number of packets that the current CPU can receive from
2174  *            all interfaces.
2175  *  Description :
2176  *  To look at the incoming frames and clear the tx resources.
2177  */
2178 static int stmmac_poll(struct napi_struct *napi, int budget)
2179 {
2180         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2181         int work_done = 0;
2182
2183         priv->xstats.napi_poll++;
2184         stmmac_tx_clean(priv);
2185
2186         work_done = stmmac_rx(priv, budget);
2187         if (work_done < budget) {
2188                 napi_complete(napi);
2189                 stmmac_enable_dma_irq(priv);
2190         }
2191         return work_done;
2192 }
2193
2194 /**
2195  *  stmmac_tx_timeout
2196  *  @dev : Pointer to net device structure
2197  *  Description: this function is called when a packet transmission fails to
2198  *   complete within a reasonable time. The driver will mark the error in the
2199  *   netdev structure and arrange for the device to be reset to a sane state
2200  *   in order to transmit a new packet.
2201  */
2202 static void stmmac_tx_timeout(struct net_device *dev)
2203 {
2204         struct stmmac_priv *priv = netdev_priv(dev);
2205
2206         /* Clear Tx resources and restart transmitting again */
2207         stmmac_tx_err(priv);
2208 }
2209
2210 /* Configuration changes (passed on by ifconfig) */
2211 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2212 {
2213         if (dev->flags & IFF_UP)        /* can't act on a running interface */
2214                 return -EBUSY;
2215
2216         /* Don't allow changing the I/O address */
2217         if (map->base_addr != dev->base_addr) {
2218                 pr_warn("%s: can't change I/O address\n", dev->name);
2219                 return -EOPNOTSUPP;
2220         }
2221
2222         /* Don't allow changing the IRQ */
2223         if (map->irq != dev->irq) {
2224                 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
2225                 return -EOPNOTSUPP;
2226         }
2227
2228         return 0;
2229 }
2230
2231 /**
2232  *  stmmac_set_rx_mode - entry point for multicast addressing
2233  *  @dev : pointer to the device structure
2234  *  Description:
2235  *  This function is a driver entry point which gets called by the kernel
2236  *  whenever multicast addresses must be enabled/disabled.
2237  *  Return value:
2238  *  void.
2239  */
2240 static void stmmac_set_rx_mode(struct net_device *dev)
2241 {
2242         struct stmmac_priv *priv = netdev_priv(dev);
2243
2244         spin_lock(&priv->lock);
2245         priv->hw->mac->set_filter(dev, priv->synopsys_id);
2246         spin_unlock(&priv->lock);
2247 }
2248
2249 /**
2250  *  stmmac_change_mtu - entry point to change MTU size for the device.
2251  *  @dev : device pointer.
2252  *  @new_mtu : the new MTU size for the device.
2253  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2254  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2255  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2256  *  Return value:
2257  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2258  *  file on failure.
2259  */
2260 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2261 {
2262         struct stmmac_priv *priv = netdev_priv(dev);
2263         int max_mtu;
2264
2265         if (netif_running(dev)) {
2266                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2267                 return -EBUSY;
2268         }
2269
2270         if (priv->plat->enh_desc)
2271                 max_mtu = JUMBO_LEN;
2272         else
2273                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2274
2275         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2276                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2277                 return -EINVAL;
2278         }
2279
2280         dev->mtu = new_mtu;
2281         netdev_update_features(dev);
2282
2283         return 0;
2284 }
2285
2286 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2287                                              netdev_features_t features)
2288 {
2289         struct stmmac_priv *priv = netdev_priv(dev);
2290
2291         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2292                 features &= ~NETIF_F_RXCSUM;
2293         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2294                 features &= ~NETIF_F_IPV6_CSUM;
2295         if (!priv->plat->tx_coe)
2296                 features &= ~NETIF_F_ALL_CSUM;
2297
2298         /* Some GMAC devices have a bugged Jumbo frame support that
2299          * needs to have the Tx COE disabled for oversized frames
2300          * (due to limited buffer sizes). In this case we disable
2301          * the TX csum insertionin the TDES and not use SF.
2302          */
2303         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2304                 features &= ~NETIF_F_ALL_CSUM;
2305
2306         return features;
2307 }
2308
2309 /**
2310  *  stmmac_interrupt - main ISR
2311  *  @irq: interrupt number.
2312  *  @dev_id: to pass the net device pointer.
2313  *  Description: this is the main driver interrupt service routine.
2314  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2315  *  interrupts.
2316  */
2317 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2318 {
2319         struct net_device *dev = (struct net_device *)dev_id;
2320         struct stmmac_priv *priv = netdev_priv(dev);
2321
2322         if (unlikely(!dev)) {
2323                 pr_err("%s: invalid dev pointer\n", __func__);
2324                 return IRQ_NONE;
2325         }
2326
2327         /* To handle GMAC own interrupts */
2328         if (priv->plat->has_gmac) {
2329                 int status = priv->hw->mac->host_irq_status((void __iomem *)
2330                                                             dev->base_addr,
2331                                                             &priv->xstats);
2332                 if (unlikely(status)) {
2333                         /* For LPI we need to save the tx status */
2334                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2335                                 priv->tx_path_in_lpi_mode = true;
2336                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2337                                 priv->tx_path_in_lpi_mode = false;
2338                 }
2339         }
2340
2341         /* To handle DMA interrupts */
2342         stmmac_dma_interrupt(priv);
2343
2344         return IRQ_HANDLED;
2345 }
2346
2347 #ifdef CONFIG_NET_POLL_CONTROLLER
2348 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2349  * to allow network I/O with interrupts disabled.
2350  */
2351 static void stmmac_poll_controller(struct net_device *dev)
2352 {
2353         disable_irq(dev->irq);
2354         stmmac_interrupt(dev->irq, dev);
2355         enable_irq(dev->irq);
2356 }
2357 #endif
2358
2359 /**
2360  *  stmmac_ioctl - Entry point for the Ioctl
2361  *  @dev: Device pointer.
2362  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2363  *  a proprietary structure used to pass information to the driver.
2364  *  @cmd: IOCTL command
2365  *  Description:
2366  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2367  */
2368 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2369 {
2370         struct stmmac_priv *priv = netdev_priv(dev);
2371         int ret = -EOPNOTSUPP;
2372
2373         if (!netif_running(dev))
2374                 return -EINVAL;
2375
2376         switch (cmd) {
2377         case SIOCGMIIPHY:
2378         case SIOCGMIIREG:
2379         case SIOCSMIIREG:
2380                 if (!priv->phydev)
2381                         return -EINVAL;
2382                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2383                 break;
2384         case SIOCSHWTSTAMP:
2385                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2386                 break;
2387         default:
2388                 break;
2389         }
2390
2391         return ret;
2392 }
2393
2394 #ifdef CONFIG_STMMAC_DEBUG_FS
2395 static struct dentry *stmmac_fs_dir;
2396 static struct dentry *stmmac_rings_status;
2397 static struct dentry *stmmac_dma_cap;
2398
2399 static void sysfs_display_ring(void *head, int size, int extend_desc,
2400                                struct seq_file *seq)
2401 {
2402         int i;
2403         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2404         struct dma_desc *p = (struct dma_desc *)head;
2405
2406         for (i = 0; i < size; i++) {
2407                 u64 x;
2408                 if (extend_desc) {
2409                         x = *(u64 *) ep;
2410                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2411                                    i, (unsigned int)virt_to_phys(ep),
2412                                    (unsigned int)x, (unsigned int)(x >> 32),
2413                                    ep->basic.des2, ep->basic.des3);
2414                         ep++;
2415                 } else {
2416                         x = *(u64 *) p;
2417                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2418                                    i, (unsigned int)virt_to_phys(ep),
2419                                    (unsigned int)x, (unsigned int)(x >> 32),
2420                                    p->des2, p->des3);
2421                         p++;
2422                 }
2423                 seq_printf(seq, "\n");
2424         }
2425 }
2426
2427 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2428 {
2429         struct net_device *dev = seq->private;
2430         struct stmmac_priv *priv = netdev_priv(dev);
2431         unsigned int txsize = priv->dma_tx_size;
2432         unsigned int rxsize = priv->dma_rx_size;
2433
2434         if (priv->extend_desc) {
2435                 seq_printf(seq, "Extended RX descriptor ring:\n");
2436                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2437                 seq_printf(seq, "Extended TX descriptor ring:\n");
2438                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2439         } else {
2440                 seq_printf(seq, "RX descriptor ring:\n");
2441                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2442                 seq_printf(seq, "TX descriptor ring:\n");
2443                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2444         }
2445
2446         return 0;
2447 }
2448
2449 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2450 {
2451         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2452 }
2453
2454 static const struct file_operations stmmac_rings_status_fops = {
2455         .owner = THIS_MODULE,
2456         .open = stmmac_sysfs_ring_open,
2457         .read = seq_read,
2458         .llseek = seq_lseek,
2459         .release = single_release,
2460 };
2461
2462 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2463 {
2464         struct net_device *dev = seq->private;
2465         struct stmmac_priv *priv = netdev_priv(dev);
2466
2467         if (!priv->hw_cap_support) {
2468                 seq_printf(seq, "DMA HW features not supported\n");
2469                 return 0;
2470         }
2471
2472         seq_printf(seq, "==============================\n");
2473         seq_printf(seq, "\tDMA HW features\n");
2474         seq_printf(seq, "==============================\n");
2475
2476         seq_printf(seq, "\t10/100 Mbps %s\n",
2477                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2478         seq_printf(seq, "\t1000 Mbps %s\n",
2479                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2480         seq_printf(seq, "\tHalf duple %s\n",
2481                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2482         seq_printf(seq, "\tHash Filter: %s\n",
2483                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2484         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2485                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2486         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2487                    (priv->dma_cap.pcs) ? "Y" : "N");
2488         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2489                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2490         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2491                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2492         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2493                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2494         seq_printf(seq, "\tRMON module: %s\n",
2495                    (priv->dma_cap.rmon) ? "Y" : "N");
2496         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2497                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2498         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2499                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2500         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2501                    (priv->dma_cap.eee) ? "Y" : "N");
2502         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2503         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2504                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2505         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2506                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2507         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2508                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2509         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2510                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2511         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2512                    priv->dma_cap.number_rx_channel);
2513         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2514                    priv->dma_cap.number_tx_channel);
2515         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2516                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2517
2518         return 0;
2519 }
2520
2521 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2522 {
2523         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2524 }
2525
2526 static const struct file_operations stmmac_dma_cap_fops = {
2527         .owner = THIS_MODULE,
2528         .open = stmmac_sysfs_dma_cap_open,
2529         .read = seq_read,
2530         .llseek = seq_lseek,
2531         .release = single_release,
2532 };
2533
2534 static int stmmac_init_fs(struct net_device *dev)
2535 {
2536         /* Create debugfs entries */
2537         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2538
2539         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2540                 pr_err("ERROR %s, debugfs create directory failed\n",
2541                        STMMAC_RESOURCE_NAME);
2542
2543                 return -ENOMEM;
2544         }
2545
2546         /* Entry to report DMA RX/TX rings */
2547         stmmac_rings_status = debugfs_create_file("descriptors_status",
2548                                                   S_IRUGO, stmmac_fs_dir, dev,
2549                                                   &stmmac_rings_status_fops);
2550
2551         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2552                 pr_info("ERROR creating stmmac ring debugfs file\n");
2553                 debugfs_remove(stmmac_fs_dir);
2554
2555                 return -ENOMEM;
2556         }
2557
2558         /* Entry to report the DMA HW features */
2559         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2560                                              dev, &stmmac_dma_cap_fops);
2561
2562         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2563                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2564                 debugfs_remove(stmmac_rings_status);
2565                 debugfs_remove(stmmac_fs_dir);
2566
2567                 return -ENOMEM;
2568         }
2569
2570         return 0;
2571 }
2572
2573 static void stmmac_exit_fs(void)
2574 {
2575         debugfs_remove(stmmac_rings_status);
2576         debugfs_remove(stmmac_dma_cap);
2577         debugfs_remove(stmmac_fs_dir);
2578 }
2579 #endif /* CONFIG_STMMAC_DEBUG_FS */
2580
2581 static const struct net_device_ops stmmac_netdev_ops = {
2582         .ndo_open = stmmac_open,
2583         .ndo_start_xmit = stmmac_xmit,
2584         .ndo_stop = stmmac_release,
2585         .ndo_change_mtu = stmmac_change_mtu,
2586         .ndo_fix_features = stmmac_fix_features,
2587         .ndo_set_rx_mode = stmmac_set_rx_mode,
2588         .ndo_tx_timeout = stmmac_tx_timeout,
2589         .ndo_do_ioctl = stmmac_ioctl,
2590         .ndo_set_config = stmmac_config,
2591 #ifdef CONFIG_NET_POLL_CONTROLLER
2592         .ndo_poll_controller = stmmac_poll_controller,
2593 #endif
2594         .ndo_set_mac_address = eth_mac_addr,
2595 };
2596
2597 /**
2598  *  stmmac_hw_init - Init the MAC device
2599  *  @priv: driver private structure
2600  *  Description: this function detects which MAC device
2601  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2602  *  (if supported) and sets the driver's features (for example
2603  *  to use the ring or chaine mode or support the normal/enh
2604  *  descriptor structure).
2605  */
2606 static int stmmac_hw_init(struct stmmac_priv *priv)
2607 {
2608         int ret;
2609         struct mac_device_info *mac;
2610
2611         /* Identify the MAC HW device */
2612         if (priv->plat->has_gmac) {
2613                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2614                 mac = dwmac1000_setup(priv->ioaddr);
2615         } else {
2616                 mac = dwmac100_setup(priv->ioaddr);
2617         }
2618         if (!mac)
2619                 return -ENOMEM;
2620
2621         priv->hw = mac;
2622
2623         /* Get and dump the chip ID */
2624         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2625
2626         /* To use the chained or ring mode */
2627         if (chain_mode) {
2628                 priv->hw->chain = &chain_mode_ops;
2629                 pr_info(" Chain mode enabled\n");
2630                 priv->mode = STMMAC_CHAIN_MODE;
2631         } else {
2632                 priv->hw->ring = &ring_mode_ops;
2633                 pr_info(" Ring mode enabled\n");
2634                 priv->mode = STMMAC_RING_MODE;
2635         }
2636
2637         /* Get the HW capability (new GMAC newer than 3.50a) */
2638         priv->hw_cap_support = stmmac_get_hw_features(priv);
2639         if (priv->hw_cap_support) {
2640                 pr_info(" DMA HW capability register supported");
2641
2642                 /* We can override some gmac/dma configuration fields: e.g.
2643                  * enh_desc, tx_coe (e.g. that are passed through the
2644                  * platform) with the values from the HW capability
2645                  * register (if supported).
2646                  */
2647                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2648                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2649
2650                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2651
2652                 if (priv->dma_cap.rx_coe_type2)
2653                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2654                 else if (priv->dma_cap.rx_coe_type1)
2655                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2656
2657         } else
2658                 pr_info(" No HW DMA feature register supported");
2659
2660         /* To use alternate (extended) or normal descriptor structures */
2661         stmmac_selec_desc_mode(priv);
2662
2663         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2664         if (!ret) {
2665                 pr_warn(" RX IPC Checksum Offload not configured.\n");
2666                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2667         }
2668
2669         if (priv->plat->rx_coe)
2670                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2671                         priv->plat->rx_coe);
2672         if (priv->plat->tx_coe)
2673                 pr_info(" TX Checksum insertion supported\n");
2674
2675         if (priv->plat->pmt) {
2676                 pr_info(" Wake-Up On Lan supported\n");
2677                 device_set_wakeup_capable(priv->device, 1);
2678         }
2679
2680         return 0;
2681 }
2682
2683 /**
2684  * stmmac_dvr_probe
2685  * @device: device pointer
2686  * @plat_dat: platform data pointer
2687  * @addr: iobase memory address
2688  * Description: this is the main probe function used to
2689  * call the alloc_etherdev, allocate the priv structure.
2690  */
2691 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2692                                      struct plat_stmmacenet_data *plat_dat,
2693                                      void __iomem *addr)
2694 {
2695         int ret = 0;
2696         struct net_device *ndev = NULL;
2697         struct stmmac_priv *priv;
2698
2699         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2700         if (!ndev)
2701                 return NULL;
2702
2703         SET_NETDEV_DEV(ndev, device);
2704
2705         priv = netdev_priv(ndev);
2706         priv->device = device;
2707         priv->dev = ndev;
2708
2709         ether_setup(ndev);
2710
2711         stmmac_set_ethtool_ops(ndev);
2712         priv->pause = pause;
2713         priv->plat = plat_dat;
2714         priv->ioaddr = addr;
2715         priv->dev->base_addr = (unsigned long)addr;
2716
2717         /* Verify driver arguments */
2718         stmmac_verify_args();
2719
2720         /* Override with kernel parameters if supplied XXX CRS XXX
2721          * this needs to have multiple instances
2722          */
2723         if ((phyaddr >= 0) && (phyaddr <= 31))
2724                 priv->plat->phy_addr = phyaddr;
2725
2726         /* Init MAC and get the capabilities */
2727         ret = stmmac_hw_init(priv);
2728         if (ret)
2729                 goto error_free_netdev;
2730
2731         ndev->netdev_ops = &stmmac_netdev_ops;
2732
2733         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2734                             NETIF_F_RXCSUM;
2735         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2736         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2737 #ifdef STMMAC_VLAN_TAG_USED
2738         /* Both mac100 and gmac support receive VLAN tag detection */
2739         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2740 #endif
2741         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2742
2743         if (flow_ctrl)
2744                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2745
2746         /* Rx Watchdog is available in the COREs newer than the 3.40.
2747          * In some case, for example on bugged HW this feature
2748          * has to be disable and this can be done by passing the
2749          * riwt_off field from the platform.
2750          */
2751         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2752                 priv->use_riwt = 1;
2753                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2754         }
2755
2756         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2757
2758         spin_lock_init(&priv->lock);
2759         spin_lock_init(&priv->tx_lock);
2760
2761         ret = register_netdev(ndev);
2762         if (ret) {
2763                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2764                 goto error_netdev_register;
2765         }
2766
2767         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2768         if (IS_ERR(priv->stmmac_clk)) {
2769                 pr_warn("%s: warning: cannot get CSR clock\n", __func__);
2770                 goto error_clk_get;
2771         }
2772
2773         /* If a specific clk_csr value is passed from the platform
2774          * this means that the CSR Clock Range selection cannot be
2775          * changed at run-time and it is fixed. Viceversa the driver'll try to
2776          * set the MDC clock dynamically according to the csr actual
2777          * clock input.
2778          */
2779         if (!priv->plat->clk_csr)
2780                 stmmac_clk_csr_set(priv);
2781         else
2782                 priv->clk_csr = priv->plat->clk_csr;
2783
2784         stmmac_check_pcs_mode(priv);
2785
2786         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2787             priv->pcs != STMMAC_PCS_RTBI) {
2788                 /* MDIO bus Registration */
2789                 ret = stmmac_mdio_register(ndev);
2790                 if (ret < 0) {
2791                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2792                                  __func__, priv->plat->bus_id);
2793                         goto error_mdio_register;
2794                 }
2795         }
2796
2797         return priv;
2798
2799 error_mdio_register:
2800         clk_put(priv->stmmac_clk);
2801 error_clk_get:
2802         unregister_netdev(ndev);
2803 error_netdev_register:
2804         netif_napi_del(&priv->napi);
2805 error_free_netdev:
2806         free_netdev(ndev);
2807
2808         return NULL;
2809 }
2810
2811 /**
2812  * stmmac_dvr_remove
2813  * @ndev: net device pointer
2814  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2815  * changes the link status, releases the DMA descriptor rings.
2816  */
2817 int stmmac_dvr_remove(struct net_device *ndev)
2818 {
2819         struct stmmac_priv *priv = netdev_priv(ndev);
2820
2821         pr_info("%s:\n\tremoving driver", __func__);
2822
2823         priv->hw->dma->stop_rx(priv->ioaddr);
2824         priv->hw->dma->stop_tx(priv->ioaddr);
2825
2826         stmmac_set_mac(priv->ioaddr, false);
2827         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2828             priv->pcs != STMMAC_PCS_RTBI)
2829                 stmmac_mdio_unregister(ndev);
2830         netif_carrier_off(ndev);
2831         unregister_netdev(ndev);
2832         free_netdev(ndev);
2833
2834         return 0;
2835 }
2836
2837 #ifdef CONFIG_PM
2838 int stmmac_suspend(struct net_device *ndev)
2839 {
2840         struct stmmac_priv *priv = netdev_priv(ndev);
2841         unsigned long flags;
2842
2843         if (!ndev || !netif_running(ndev))
2844                 return 0;
2845
2846         if (priv->phydev)
2847                 phy_stop(priv->phydev);
2848
2849         spin_lock_irqsave(&priv->lock, flags);
2850
2851         netif_device_detach(ndev);
2852         netif_stop_queue(ndev);
2853
2854         napi_disable(&priv->napi);
2855
2856         /* Stop TX/RX DMA */
2857         priv->hw->dma->stop_tx(priv->ioaddr);
2858         priv->hw->dma->stop_rx(priv->ioaddr);
2859
2860         stmmac_clear_descriptors(priv);
2861
2862         /* Enable Power down mode by programming the PMT regs */
2863         if (device_may_wakeup(priv->device))
2864                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2865         else {
2866                 stmmac_set_mac(priv->ioaddr, false);
2867                 /* Disable clock in case of PWM is off */
2868                 clk_disable_unprepare(priv->stmmac_clk);
2869         }
2870         spin_unlock_irqrestore(&priv->lock, flags);
2871         return 0;
2872 }
2873
2874 int stmmac_resume(struct net_device *ndev)
2875 {
2876         struct stmmac_priv *priv = netdev_priv(ndev);
2877         unsigned long flags;
2878
2879         if (!netif_running(ndev))
2880                 return 0;
2881
2882         spin_lock_irqsave(&priv->lock, flags);
2883
2884         /* Power Down bit, into the PM register, is cleared
2885          * automatically as soon as a magic packet or a Wake-up frame
2886          * is received. Anyway, it's better to manually clear
2887          * this bit because it can generate problems while resuming
2888          * from another devices (e.g. serial console).
2889          */
2890         if (device_may_wakeup(priv->device)) {
2891                 priv->hw->mac->pmt(priv->ioaddr, 0);
2892         } else {
2893                 /* enable the clk prevously disabled */
2894                 clk_prepare_enable(priv->stmmac_clk);
2895                 /* reset the phy so that it's ready */
2896                 if (priv->mii)
2897                         stmmac_mdio_reset(priv->mii);
2898         }
2899
2900         netif_device_attach(ndev);
2901
2902         stmmac_hw_setup(ndev);
2903
2904         napi_enable(&priv->napi);
2905
2906         netif_start_queue(ndev);
2907
2908         spin_unlock_irqrestore(&priv->lock, flags);
2909
2910         if (priv->phydev)
2911                 phy_start(priv->phydev);
2912
2913         return 0;
2914 }
2915
2916 int stmmac_freeze(struct net_device *ndev)
2917 {
2918         if (!ndev || !netif_running(ndev))
2919                 return 0;
2920
2921         return stmmac_release(ndev);
2922 }
2923
2924 int stmmac_restore(struct net_device *ndev)
2925 {
2926         if (!ndev || !netif_running(ndev))
2927                 return 0;
2928
2929         return stmmac_open(ndev);
2930 }
2931 #endif /* CONFIG_PM */
2932
2933 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2934  * depending on the configuration selected.
2935  */
2936 static int __init stmmac_init(void)
2937 {
2938         int ret;
2939
2940         ret = stmmac_register_platform();
2941         if (ret)
2942                 goto err;
2943         ret = stmmac_register_pci();
2944         if (ret)
2945                 goto err_pci;
2946         return 0;
2947 err_pci:
2948         stmmac_unregister_platform();
2949 err:
2950         pr_err("stmmac: driver registration failed\n");
2951         return ret;
2952 }
2953
2954 static void __exit stmmac_exit(void)
2955 {
2956         stmmac_unregister_platform();
2957         stmmac_unregister_pci();
2958 }
2959
2960 module_init(stmmac_init);
2961 module_exit(stmmac_exit);
2962
2963 #ifndef MODULE
2964 static int __init stmmac_cmdline_opt(char *str)
2965 {
2966         char *opt;
2967
2968         if (!str || !*str)
2969                 return -EINVAL;
2970         while ((opt = strsep(&str, ",")) != NULL) {
2971                 if (!strncmp(opt, "debug:", 6)) {
2972                         if (kstrtoint(opt + 6, 0, &debug))
2973                                 goto err;
2974                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2975                         if (kstrtoint(opt + 8, 0, &phyaddr))
2976                                 goto err;
2977                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2978                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2979                                 goto err;
2980                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2981                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2982                                 goto err;
2983                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2984                         if (kstrtoint(opt + 7, 0, &buf_sz))
2985                                 goto err;
2986                 } else if (!strncmp(opt, "tc:", 3)) {
2987                         if (kstrtoint(opt + 3, 0, &tc))
2988                                 goto err;
2989                 } else if (!strncmp(opt, "watchdog:", 9)) {
2990                         if (kstrtoint(opt + 9, 0, &watchdog))
2991                                 goto err;
2992                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2993                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2994                                 goto err;
2995                 } else if (!strncmp(opt, "pause:", 6)) {
2996                         if (kstrtoint(opt + 6, 0, &pause))
2997                                 goto err;
2998                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2999                         if (kstrtoint(opt + 10, 0, &eee_timer))
3000                                 goto err;
3001                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3002                         if (kstrtoint(opt + 11, 0, &chain_mode))
3003                                 goto err;
3004                 }
3005         }
3006         return 0;
3007
3008 err:
3009         pr_err("%s: ERROR broken module parameter conversion", __func__);
3010         return -EINVAL;
3011 }
3012
3013 __setup("stmmaceth=", stmmac_cmdline_opt);
3014 #endif /* MODULE */
3015
3016 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3017 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3018 MODULE_LICENSE("GPL");