drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55 #include <linux/of_mdio.h>
  56
  57 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  58
  59 /* Module parameters */
  60 #define TX_TIMEO        5000
  61 static int watchdog = TX_TIMEO;
  62 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  63 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  64
  65 static int debug = -1;
  66 module_param(debug, int, S_IRUGO | S_IWUSR);
  67 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  68
  69 static int phyaddr = -1;
  70 module_param(phyaddr, int, S_IRUGO);
  71 MODULE_PARM_DESC(phyaddr, "Physical device address");
  72
  73 #define DMA_TX_SIZE 256
  74 static int dma_txsize = DMA_TX_SIZE;
  75 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  76 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  77
  78 #define DMA_RX_SIZE 256
  79 static int dma_rxsize = DMA_RX_SIZE;
  80 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
  81 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
  82
  83 static int flow_ctrl = FLOW_OFF;
  84 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  86
  87 static int pause = PAUSE_TIME;
  88 module_param(pause, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  90
  91 #define TC_DEFAULT 64
  92 static int tc = TC_DEFAULT;
  93 module_param(tc, int, S_IRUGO | S_IWUSR);
  94 MODULE_PARM_DESC(tc, "DMA threshold control value");
  95
  96 #define DEFAULT_BUFSIZE 1536
  97 static int buf_sz = DEFAULT_BUFSIZE;
  98 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  99 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 100
 101 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 102                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 103                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 104
 105 #define STMMAC_DEFAULT_LPI_TIMER        1000
 106 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 107 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 108 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 109 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 110
 111 /* By default the driver will use the ring mode to manage tx and rx descriptors
 112  * but passing this value so user can force to use the chain instead of the ring
 113  */
 114 static unsigned int chain_mode;
 115 module_param(chain_mode, int, S_IRUGO);
 116 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 117
 118 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 119
 120 #ifdef CONFIG_DEBUG_FS
 121 static int stmmac_init_fs(struct net_device *dev);
 122 static void stmmac_exit_fs(struct net_device *dev);
 123 #endif
 124
 125 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 126
 127 /**
 128  * stmmac_verify_args - verify the driver parameters.
 129  * Description: it checks the driver parameters and set a default in case of
 130  * errors.
 131  */
 132 static void stmmac_verify_args(void)
 133 {
 134         if (unlikely(watchdog < 0))
 135                 watchdog = TX_TIMEO;
 136         if (unlikely(dma_rxsize < 0))
 137                 dma_rxsize = DMA_RX_SIZE;
 138         if (unlikely(dma_txsize < 0))
 139                 dma_txsize = DMA_TX_SIZE;
 140         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 141                 buf_sz = DEFAULT_BUFSIZE;
 142         if (unlikely(flow_ctrl > 1))
 143                 flow_ctrl = FLOW_AUTO;
 144         else if (likely(flow_ctrl < 0))
 145                 flow_ctrl = FLOW_OFF;
 146         if (unlikely((pause < 0) || (pause > 0xffff)))
 147                 pause = PAUSE_TIME;
 148         if (eee_timer < 0)
 149                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 150 }
 151
 152 /**
 153  * stmmac_clk_csr_set - dynamically set the MDC clock
 154  * @priv: driver private structure
 155  * Description: this is to dynamically set the MDC clock according to the csr
 156  * clock input.
 157  * Note:
 158  *      If a specific clk_csr value is passed from the platform
 159  *      this means that the CSR Clock Range selection cannot be
 160  *      changed at run-time and it is fixed (as reported in the driver
 161  *      documentation). Viceversa the driver will try to set the MDC
 162  *      clock dynamically according to the actual clock input.
 163  */
 164 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 165 {
 166         u32 clk_rate;
 167
 168         clk_rate = clk_get_rate(priv->stmmac_clk);
 169
 170         /* Platform provided default clk_csr would be assumed valid
 171          * for all other cases except for the below mentioned ones.
 172          * For values higher than the IEEE 802.3 specified frequency
 173          * we can not estimate the proper divider as it is not known
 174          * the frequency of clk_csr_i. So we do not change the default
 175          * divider.
 176          */
 177         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 178                 if (clk_rate < CSR_F_35M)
 179                         priv->clk_csr = STMMAC_CSR_20_35M;
 180                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 181                         priv->clk_csr = STMMAC_CSR_35_60M;
 182                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 183                         priv->clk_csr = STMMAC_CSR_60_100M;
 184                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 185                         priv->clk_csr = STMMAC_CSR_100_150M;
 186                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 187                         priv->clk_csr = STMMAC_CSR_150_250M;
 188                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 189                         priv->clk_csr = STMMAC_CSR_250_300M;
 190         }
 191 }
 192
 193 static void print_pkt(unsigned char *buf, int len)
 194 {
 195         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 196         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 197 }
 198
 199 /* minimum number of free TX descriptors required to wake up TX process */
 200 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 201
 202 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 203 {
 204         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 205 }
 206
 207 /**
 208  * stmmac_hw_fix_mac_speed - callback for speed selection
 209  * @priv: driver private structure
 210  * Description: on some platforms (e.g. ST), some HW system configuraton
 211  * registers have to be set according to the link speed negotiated.
 212  */
 213 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 214 {
 215         struct phy_device *phydev = priv->phydev;
 216
 217         if (likely(priv->plat->fix_mac_speed))
 218                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 219 }
 220
 221 /**
 222  * stmmac_enable_eee_mode - check and enter in LPI mode
 223  * @priv: driver private structure
 224  * Description: this function is to verify and enter in LPI mode in case of
 225  * EEE.
 226  */
 227 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 228 {
 229         /* Check and enter in LPI mode */
 230         if ((priv->dirty_tx == priv->cur_tx) &&
 231             (priv->tx_path_in_lpi_mode == false))
 232                 priv->hw->mac->set_eee_mode(priv->hw);
 233 }
 234
 235 /**
 236  * stmmac_disable_eee_mode - disable and exit from LPI mode
 237  * @priv: driver private structure
 238  * Description: this function is to exit and disable EEE in case of
 239  * LPI state is true. This is called by the xmit.
 240  */
 241 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 242 {
 243         priv->hw->mac->reset_eee_mode(priv->hw);
 244         del_timer_sync(&priv->eee_ctrl_timer);
 245         priv->tx_path_in_lpi_mode = false;
 246 }
 247
 248 /**
 249  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 250  * @arg : data hook
 251  * Description:
 252  *  if there is no data transfer and if we are not in LPI state,
 253  *  then MAC Transmitter can be moved to LPI state.
 254  */
 255 static void stmmac_eee_ctrl_timer(unsigned long arg)
 256 {
 257         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 258
 259         stmmac_enable_eee_mode(priv);
 260         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 261 }
 262
 263 /**
 264  * stmmac_eee_init - init EEE
 265  * @priv: driver private structure
 266  * Description:
 267  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 268  *  can also manage EEE, this function enable the LPI state and start related
 269  *  timer.
 270  */
 271 bool stmmac_eee_init(struct stmmac_priv *priv)
 272 {
 273         char *phy_bus_name = priv->plat->phy_bus_name;
 274         unsigned long flags;
 275         bool ret = false;
 276
 277         /* Using PCS we cannot dial with the phy registers at this stage
 278          * so we do not support extra feature like EEE.
 279          */
 280         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 281             (priv->pcs == STMMAC_PCS_RTBI))
 282                 goto out;
 283
 284         /* Never init EEE in case of a switch is attached */
 285         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
 286                 goto out;
 287
 288         /* MAC core supports the EEE feature. */
 289         if (priv->dma_cap.eee) {
 290                 int tx_lpi_timer = priv->tx_lpi_timer;
 291
 292                 /* Check if the PHY supports EEE */
 293                 if (phy_init_eee(priv->phydev, 1)) {
 294                         /* To manage at run-time if the EEE cannot be supported
 295                          * anymore (for example because the lp caps have been
 296                          * changed).
 297                          * In that case the driver disable own timers.
 298                          */
 299                         spin_lock_irqsave(&priv->lock, flags);
 300                         if (priv->eee_active) {
 301                                 pr_debug("stmmac: disable EEE\n");
 302                                 del_timer_sync(&priv->eee_ctrl_timer);
 303                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 304                                                              tx_lpi_timer);
 305                         }
 306                         priv->eee_active = 0;
 307                         spin_unlock_irqrestore(&priv->lock, flags);
 308                         goto out;
 309                 }
 310                 /* Activate the EEE and start timers */
 311                 spin_lock_irqsave(&priv->lock, flags);
 312                 if (!priv->eee_active) {
 313                         priv->eee_active = 1;
 314                         setup_timer(&priv->eee_ctrl_timer,
 315                                     stmmac_eee_ctrl_timer,
 316                                     (unsigned long)priv);
 317                         mod_timer(&priv->eee_ctrl_timer,
 318                                   STMMAC_LPI_T(eee_timer));
 319
 320                         priv->hw->mac->set_eee_timer(priv->hw,
 321                                                      STMMAC_DEFAULT_LIT_LS,
 322                                                      tx_lpi_timer);
 323                 }
 324                 /* Set HW EEE according to the speed */
 325                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 326
 327                 ret = true;
 328                 spin_unlock_irqrestore(&priv->lock, flags);
 329
 330                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 331         }
 332 out:
 333         return ret;
 334 }
 335
 336 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 337  * @priv: driver private structure
 338  * @entry : descriptor index to be used.
 339  * @skb : the socket buffer
 340  * Description :
 341  * This function will read timestamp from the descriptor & pass it to stack.
 342  * and also perform some sanity checks.
 343  */
 344 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 345                                    unsigned int entry, struct sk_buff *skb)
 346 {
 347         struct skb_shared_hwtstamps shhwtstamp;
 348         u64 ns;
 349         void *desc = NULL;
 350
 351         if (!priv->hwts_tx_en)
 352                 return;
 353
 354         /* exit if skb doesn't support hw tstamp */
 355         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 356                 return;
 357
 358         if (priv->adv_ts)
 359                 desc = (priv->dma_etx + entry);
 360         else
 361                 desc = (priv->dma_tx + entry);
 362
 363         /* check tx tstamp status */
 364         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 365                 return;
 366
 367         /* get the valid tstamp */
 368         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 369
 370         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 371         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 372         /* pass tstamp to stack */
 373         skb_tstamp_tx(skb, &shhwtstamp);
 374
 375         return;
 376 }
 377
 378 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 379  * @priv: driver private structure
 380  * @entry : descriptor index to be used.
 381  * @skb : the socket buffer
 382  * Description :
 383  * This function will read received packet's timestamp from the descriptor
 384  * and pass it to stack. It also perform some sanity checks.
 385  */
 386 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 387                                    unsigned int entry, struct sk_buff *skb)
 388 {
 389         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 390         u64 ns;
 391         void *desc = NULL;
 392
 393         if (!priv->hwts_rx_en)
 394                 return;
 395
 396         if (priv->adv_ts)
 397                 desc = (priv->dma_erx + entry);
 398         else
 399                 desc = (priv->dma_rx + entry);
 400
 401         /* exit if rx tstamp is not valid */
 402         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 403                 return;
 404
 405         /* get valid tstamp */
 406         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 407         shhwtstamp = skb_hwtstamps(skb);
 408         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 409         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 410 }
 411
 412 /**
 413  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 414  *  @dev: device pointer.
 415  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 416  *  a proprietary structure used to pass information to the driver.
 417  *  Description:
 418  *  This function configures the MAC to enable/disable both outgoing(TX)
 419  *  and incoming(RX) packets time stamping based on user input.
 420  *  Return Value:
 421  *  0 on success and an appropriate -ve integer on failure.
 422  */
 423 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 424 {
 425         struct stmmac_priv *priv = netdev_priv(dev);
 426         struct hwtstamp_config config;
 427         struct timespec now;
 428         u64 temp = 0;
 429         u32 ptp_v2 = 0;
 430         u32 tstamp_all = 0;
 431         u32 ptp_over_ipv4_udp = 0;
 432         u32 ptp_over_ipv6_udp = 0;
 433         u32 ptp_over_ethernet = 0;
 434         u32 snap_type_sel = 0;
 435         u32 ts_master_en = 0;
 436         u32 ts_event_en = 0;
 437         u32 value = 0;
 438
 439         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 440                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 441                 priv->hwts_tx_en = 0;
 442                 priv->hwts_rx_en = 0;
 443
 444                 return -EOPNOTSUPP;
 445         }
 446
 447         if (copy_from_user(&config, ifr->ifr_data,
 448                            sizeof(struct hwtstamp_config)))
 449                 return -EFAULT;
 450
 451         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 452                  __func__, config.flags, config.tx_type, config.rx_filter);
 453
 454         /* reserved for future extensions */
 455         if (config.flags)
 456                 return -EINVAL;
 457
 458         if (config.tx_type != HWTSTAMP_TX_OFF &&
 459             config.tx_type != HWTSTAMP_TX_ON)
 460                 return -ERANGE;
 461
 462         if (priv->adv_ts) {
 463                 switch (config.rx_filter) {
 464                 case HWTSTAMP_FILTER_NONE:
 465                         /* time stamp no incoming packet at all */
 466                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 467                         break;
 468
 469                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 470                         /* PTP v1, UDP, any kind of event packet */
 471                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 472                         /* take time stamp for all event messages */
 473                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 474
 475                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 476                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 477                         break;
 478
 479                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 480                         /* PTP v1, UDP, Sync packet */
 481                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 482                         /* take time stamp for SYNC messages only */
 483                         ts_event_en = PTP_TCR_TSEVNTENA;
 484
 485                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 486                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 487                         break;
 488
 489                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 490                         /* PTP v1, UDP, Delay_req packet */
 491                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 492                         /* take time stamp for Delay_Req messages only */
 493                         ts_master_en = PTP_TCR_TSMSTRENA;
 494                         ts_event_en = PTP_TCR_TSEVNTENA;
 495
 496                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 497                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 498                         break;
 499
 500                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 501                         /* PTP v2, UDP, any kind of event packet */
 502                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 503                         ptp_v2 = PTP_TCR_TSVER2ENA;
 504                         /* take time stamp for all event messages */
 505                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 506
 507                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 508                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 509                         break;
 510
 511                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 512                         /* PTP v2, UDP, Sync packet */
 513                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 514                         ptp_v2 = PTP_TCR_TSVER2ENA;
 515                         /* take time stamp for SYNC messages only */
 516                         ts_event_en = PTP_TCR_TSEVNTENA;
 517
 518                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 519                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 520                         break;
 521
 522                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 523                         /* PTP v2, UDP, Delay_req packet */
 524                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 525                         ptp_v2 = PTP_TCR_TSVER2ENA;
 526                         /* take time stamp for Delay_Req messages only */
 527                         ts_master_en = PTP_TCR_TSMSTRENA;
 528                         ts_event_en = PTP_TCR_TSEVNTENA;
 529
 530                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 531                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 532                         break;
 533
 534                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 535                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 536                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 537                         ptp_v2 = PTP_TCR_TSVER2ENA;
 538                         /* take time stamp for all event messages */
 539                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 540
 541                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 542                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 543                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 544                         break;
 545
 546                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 547                         /* PTP v2/802.AS1, any layer, Sync packet */
 548                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 549                         ptp_v2 = PTP_TCR_TSVER2ENA;
 550                         /* take time stamp for SYNC messages only */
 551                         ts_event_en = PTP_TCR_TSEVNTENA;
 552
 553                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 554                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 555                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 556                         break;
 557
 558                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 559                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 560                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 561                         ptp_v2 = PTP_TCR_TSVER2ENA;
 562                         /* take time stamp for Delay_Req messages only */
 563                         ts_master_en = PTP_TCR_TSMSTRENA;
 564                         ts_event_en = PTP_TCR_TSEVNTENA;
 565
 566                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 567                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 568                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 569                         break;
 570
 571                 case HWTSTAMP_FILTER_ALL:
 572                         /* time stamp any incoming packet */
 573                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 574                         tstamp_all = PTP_TCR_TSENALL;
 575                         break;
 576
 577                 default:
 578                         return -ERANGE;
 579                 }
 580         } else {
 581                 switch (config.rx_filter) {
 582                 case HWTSTAMP_FILTER_NONE:
 583                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 584                         break;
 585                 default:
 586                         /* PTP v1, UDP, any kind of event packet */
 587                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 588                         break;
 589                 }
 590         }
 591         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 592         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 593
 594         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 595                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 596         else {
 597                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 598                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 599                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 600                          ts_master_en | snap_type_sel);
 601
 602                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 603
 604                 /* program Sub Second Increment reg */
 605                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 606
 607                 /* calculate default added value:
 608                  * formula is :
 609                  * addend = (2^32)/freq_div_ratio;
 610                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
 611                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
 612                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
 613                  *       achieve 20ns accuracy.
 614                  *
 615                  * 2^x * y == (y << x), hence
 616                  * 2^32 * 50000000 ==> (50000000 << 32)
 617                  */
 618                 temp = (u64) (50000000ULL << 32);
 619                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 620                 priv->hw->ptp->config_addend(priv->ioaddr,
 621                                              priv->default_addend);
 622
 623                 /* initialize system time */
 624                 getnstimeofday(&now);
 625                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 626                                             now.tv_nsec);
 627         }
 628
 629         return copy_to_user(ifr->ifr_data, &config,
 630                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 631 }
 632
 633 /**
 634  * stmmac_init_ptp - init PTP
 635  * @priv: driver private structure
 636  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 637  * This is done by looking at the HW cap. register.
 638  * This function also registers the ptp driver.
 639  */
 640 static int stmmac_init_ptp(struct stmmac_priv *priv)
 641 {
 642         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 643                 return -EOPNOTSUPP;
 644
 645         /* Fall-back to main clock in case of no PTP ref is passed */
 646         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 647         if (IS_ERR(priv->clk_ptp_ref)) {
 648                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 649                 priv->clk_ptp_ref = NULL;
 650         } else {
 651                 clk_prepare_enable(priv->clk_ptp_ref);
 652                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 653         }
 654
 655         priv->adv_ts = 0;
 656         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 657                 priv->adv_ts = 1;
 658
 659         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 660                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 661
 662         if (netif_msg_hw(priv) && priv->adv_ts)
 663                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 664
 665         priv->hw->ptp = &stmmac_ptp;
 666         priv->hwts_tx_en = 0;
 667         priv->hwts_rx_en = 0;
 668
 669         return stmmac_ptp_register(priv);
 670 }
 671
 672 static void stmmac_release_ptp(struct stmmac_priv *priv)
 673 {
 674         if (priv->clk_ptp_ref)
 675                 clk_disable_unprepare(priv->clk_ptp_ref);
 676         stmmac_ptp_unregister(priv);
 677 }
 678
 679 /**
 680  * stmmac_adjust_link - adjusts the link parameters
 681  * @dev: net device structure
 682  * Description: this is the helper called by the physical abstraction layer
 683  * drivers to communicate the phy link status. According the speed and duplex
 684  * this driver can invoke registered glue-logic as well.
 685  * It also invoke the eee initialization because it could happen when switch
 686  * on different networks (that are eee capable).
 687  */
 688 static void stmmac_adjust_link(struct net_device *dev)
 689 {
 690         struct stmmac_priv *priv = netdev_priv(dev);
 691         struct phy_device *phydev = priv->phydev;
 692         unsigned long flags;
 693         int new_state = 0;
 694         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 695
 696         if (phydev == NULL)
 697                 return;
 698
 699         spin_lock_irqsave(&priv->lock, flags);
 700
 701         if (phydev->link) {
 702                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 703
 704                 /* Now we make sure that we can be in full duplex mode.
 705                  * If not, we operate in half-duplex mode. */
 706                 if (phydev->duplex != priv->oldduplex) {
 707                         new_state = 1;
 708                         if (!(phydev->duplex))
 709                                 ctrl &= ~priv->hw->link.duplex;
 710                         else
 711                                 ctrl |= priv->hw->link.duplex;
 712                         priv->oldduplex = phydev->duplex;
 713                 }
 714                 /* Flow Control operation */
 715                 if (phydev->pause)
 716                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 717                                                  fc, pause_time);
 718
 719                 if (phydev->speed != priv->speed) {
 720                         new_state = 1;
 721                         switch (phydev->speed) {
 722                         case 1000:
 723                                 if (likely(priv->plat->has_gmac))
 724                                         ctrl &= ~priv->hw->link.port;
 725                                 stmmac_hw_fix_mac_speed(priv);
 726                                 break;
 727                         case 100:
 728                         case 10:
 729                                 if (priv->plat->has_gmac) {
 730                                         ctrl |= priv->hw->link.port;
 731                                         if (phydev->speed == SPEED_100) {
 732                                                 ctrl |= priv->hw->link.speed;
 733                                         } else {
 734                                                 ctrl &= ~(priv->hw->link.speed);
 735                                         }
 736                                 } else {
 737                                         ctrl &= ~priv->hw->link.port;
 738                                 }
 739                                 stmmac_hw_fix_mac_speed(priv);
 740                                 break;
 741                         default:
 742                                 if (netif_msg_link(priv))
 743                                         pr_warn("%s: Speed (%d) not 10/100\n",
 744                                                 dev->name, phydev->speed);
 745                                 break;
 746                         }
 747
 748                         priv->speed = phydev->speed;
 749                 }
 750
 751                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 752
 753                 if (!priv->oldlink) {
 754                         new_state = 1;
 755                         priv->oldlink = 1;
 756                 }
 757         } else if (priv->oldlink) {
 758                 new_state = 1;
 759                 priv->oldlink = 0;
 760                 priv->speed = 0;
 761                 priv->oldduplex = -1;
 762         }
 763
 764         if (new_state && netif_msg_link(priv))
 765                 phy_print_status(phydev);
 766
 767         spin_unlock_irqrestore(&priv->lock, flags);
 768
 769         /* At this stage, it could be needed to setup the EEE or adjust some
 770          * MAC related HW registers.
 771          */
 772         priv->eee_enabled = stmmac_eee_init(priv);
 773 }
 774
 775 /**
 776  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 777  * @priv: driver private structure
 778  * Description: this is to verify if the HW supports the PCS.
 779  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 780  * configured for the TBI, RTBI, or SGMII PHY interface.
 781  */
 782 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 783 {
 784         int interface = priv->plat->interface;
 785
 786         if (priv->dma_cap.pcs) {
 787                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 788                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 789                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 790                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 791                         pr_debug("STMMAC: PCS RGMII support enable\n");
 792                         priv->pcs = STMMAC_PCS_RGMII;
 793                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 794                         pr_debug("STMMAC: PCS SGMII support enable\n");
 795                         priv->pcs = STMMAC_PCS_SGMII;
 796                 }
 797         }
 798 }
 799
 800 /**
 801  * stmmac_init_phy - PHY initialization
 802  * @dev: net device structure
 803  * Description: it initializes the driver's PHY state, and attaches the PHY
 804  * to the mac driver.
 805  *  Return value:
 806  *  0 on success
 807  */
 808 static int stmmac_init_phy(struct net_device *dev)
 809 {
 810         struct stmmac_priv *priv = netdev_priv(dev);
 811         struct phy_device *phydev;
 812         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 813         char bus_id[MII_BUS_ID_SIZE];
 814         int interface = priv->plat->interface;
 815         int max_speed = priv->plat->max_speed;
 816         priv->oldlink = 0;
 817         priv->speed = 0;
 818         priv->oldduplex = -1;
 819
 820         if (priv->plat->phy_node) {
 821                 phydev = of_phy_connect(dev, priv->plat->phy_node,
 822                                         &stmmac_adjust_link, 0, interface);
 823         } else {
 824                 if (priv->plat->phy_bus_name)
 825                         snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 826                                  priv->plat->phy_bus_name, priv->plat->bus_id);
 827                 else
 828                         snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 829                                  priv->plat->bus_id);
 830
 831                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 832                          priv->plat->phy_addr);
 833                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
 834                          phy_id_fmt);
 835
 836                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
 837                                      interface);
 838         }
 839
 840         if (IS_ERR(phydev)) {
 841                 pr_err("%s: Could not attach to PHY\n", dev->name);
 842                 return PTR_ERR(phydev);
 843         }
 844
 845         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 846         if ((interface == PHY_INTERFACE_MODE_MII) ||
 847             (interface == PHY_INTERFACE_MODE_RMII) ||
 848                 (max_speed < 1000 && max_speed > 0))
 849                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 850                                          SUPPORTED_1000baseT_Full);
 851
 852         /*
 853          * Broken HW is sometimes missing the pull-up resistor on the
 854          * MDIO line, which results in reads to non-existent devices returning
 855          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 856          * device as well.
 857          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 858          */
 859         if (!priv->plat->phy_node && phydev->phy_id == 0) {
 860                 phy_disconnect(phydev);
 861                 return -ENODEV;
 862         }
 863         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 864                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 865
 866         priv->phydev = phydev;
 867
 868         return 0;
 869 }
 870
 871 /**
 872  * stmmac_display_ring - display ring
 873  * @head: pointer to the head of the ring passed.
 874  * @size: size of the ring.
 875  * @extend_desc: to verify if extended descriptors are used.
 876  * Description: display the control/status and buffer descriptors.
 877  */
 878 static void stmmac_display_ring(void *head, int size, int extend_desc)
 879 {
 880         int i;
 881         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 882         struct dma_desc *p = (struct dma_desc *)head;
 883
 884         for (i = 0; i < size; i++) {
 885                 u64 x;
 886                 if (extend_desc) {
 887                         x = *(u64 *) ep;
 888                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 889                                 i, (unsigned int)virt_to_phys(ep),
 890                                 (unsigned int)x, (unsigned int)(x >> 32),
 891                                 ep->basic.des2, ep->basic.des3);
 892                         ep++;
 893                 } else {
 894                         x = *(u64 *) p;
 895                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 896                                 i, (unsigned int)virt_to_phys(p),
 897                                 (unsigned int)x, (unsigned int)(x >> 32),
 898                                 p->des2, p->des3);
 899                         p++;
 900                 }
 901                 pr_info("\n");
 902         }
 903 }
 904
 905 static void stmmac_display_rings(struct stmmac_priv *priv)
 906 {
 907         unsigned int txsize = priv->dma_tx_size;
 908         unsigned int rxsize = priv->dma_rx_size;
 909
 910         if (priv->extend_desc) {
 911                 pr_info("Extended RX descriptor ring:\n");
 912                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 913                 pr_info("Extended TX descriptor ring:\n");
 914                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 915         } else {
 916                 pr_info("RX descriptor ring:\n");
 917                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 918                 pr_info("TX descriptor ring:\n");
 919                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 920         }
 921 }
 922
 923 static int stmmac_set_bfsize(int mtu, int bufsize)
 924 {
 925         int ret = bufsize;
 926
 927         if (mtu >= BUF_SIZE_4KiB)
 928                 ret = BUF_SIZE_8KiB;
 929         else if (mtu >= BUF_SIZE_2KiB)
 930                 ret = BUF_SIZE_4KiB;
 931         else if (mtu > DEFAULT_BUFSIZE)
 932                 ret = BUF_SIZE_2KiB;
 933         else
 934                 ret = DEFAULT_BUFSIZE;
 935
 936         return ret;
 937 }
 938
 939 /**
 940  * stmmac_clear_descriptors - clear descriptors
 941  * @priv: driver private structure
 942  * Description: this function is called to clear the tx and rx descriptors
 943  * in case of both basic and extended descriptors are used.
 944  */
 945 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 946 {
 947         int i;
 948         unsigned int txsize = priv->dma_tx_size;
 949         unsigned int rxsize = priv->dma_rx_size;
 950
 951         /* Clear the Rx/Tx descriptors */
 952         for (i = 0; i < rxsize; i++)
 953                 if (priv->extend_desc)
 954                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 955                                                      priv->use_riwt, priv->mode,
 956                                                      (i == rxsize - 1));
 957                 else
 958                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 959                                                      priv->use_riwt, priv->mode,
 960                                                      (i == rxsize - 1));
 961         for (i = 0; i < txsize; i++)
 962                 if (priv->extend_desc)
 963                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 964                                                      priv->mode,
 965                                                      (i == txsize - 1));
 966                 else
 967                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 968                                                      priv->mode,
 969                                                      (i == txsize - 1));
 970 }
 971
 972 /**
 973  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 974  * @priv: driver private structure
 975  * @p: descriptor pointer
 976  * @i: descriptor index
 977  * @flags: gfp flag.
 978  * Description: this function is called to allocate a receive buffer, perform
 979  * the DMA mapping and init the descriptor.
 980  */
 981 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 982                                   int i, gfp_t flags)
 983 {
 984         struct sk_buff *skb;
 985
 986         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
 987         if (!skb) {
 988                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 989                 return -ENOMEM;
 990         }
 991         priv->rx_skbuff[i] = skb;
 992         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 993                                                 priv->dma_buf_sz,
 994                                                 DMA_FROM_DEVICE);
 995         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 996                 pr_err("%s: DMA mapping error\n", __func__);
 997                 dev_kfree_skb_any(skb);
 998                 return -EINVAL;
 999         }
1000
1001         p->des2 = priv->rx_skbuff_dma[i];
1002
1003         if ((priv->hw->mode->init_desc3) &&
1004             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1005                 priv->hw->mode->init_desc3(p);
1006
1007         return 0;
1008 }
1009
1010 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1011 {
1012         if (priv->rx_skbuff[i]) {
1013                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1014                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1015                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1016         }
1017         priv->rx_skbuff[i] = NULL;
1018 }
1019
1020 /**
1021  * init_dma_desc_rings - init the RX/TX descriptor rings
1022  * @dev: net device structure
1023  * @flags: gfp flag.
1024  * Description: this function initializes the DMA RX/TX descriptors
1025  * and allocates the socket buffers. It suppors the chained and ring
1026  * modes.
1027  */
1028 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1029 {
1030         int i;
1031         struct stmmac_priv *priv = netdev_priv(dev);
1032         unsigned int txsize = priv->dma_tx_size;
1033         unsigned int rxsize = priv->dma_rx_size;
1034         unsigned int bfsize = 0;
1035         int ret = -ENOMEM;
1036
1037         if (priv->hw->mode->set_16kib_bfsize)
1038                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1039
1040         if (bfsize < BUF_SIZE_16KiB)
1041                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1042
1043         priv->dma_buf_sz = bfsize;
1044
1045         if (netif_msg_probe(priv))
1046                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1047                          txsize, rxsize, bfsize);
1048
1049         if (netif_msg_probe(priv)) {
1050                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1051                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1052
1053                 /* RX INITIALIZATION */
1054                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1055         }
1056         for (i = 0; i < rxsize; i++) {
1057                 struct dma_desc *p;
1058                 if (priv->extend_desc)
1059                         p = &((priv->dma_erx + i)->basic);
1060                 else
1061                         p = priv->dma_rx + i;
1062
1063                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1064                 if (ret)
1065                         goto err_init_rx_buffers;
1066
1067                 if (netif_msg_probe(priv))
1068                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1069                                  priv->rx_skbuff[i]->data,
1070                                  (unsigned int)priv->rx_skbuff_dma[i]);
1071         }
1072         priv->cur_rx = 0;
1073         priv->dirty_rx = (unsigned int)(i - rxsize);
1074         buf_sz = bfsize;
1075
1076         /* Setup the chained descriptor addresses */
1077         if (priv->mode == STMMAC_CHAIN_MODE) {
1078                 if (priv->extend_desc) {
1079                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1080                                              rxsize, 1);
1081                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1082                                              txsize, 1);
1083                 } else {
1084                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1085                                              rxsize, 0);
1086                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1087                                              txsize, 0);
1088                 }
1089         }
1090
1091         /* TX INITIALIZATION */
1092         for (i = 0; i < txsize; i++) {
1093                 struct dma_desc *p;
1094                 if (priv->extend_desc)
1095                         p = &((priv->dma_etx + i)->basic);
1096                 else
1097                         p = priv->dma_tx + i;
1098                 p->des2 = 0;
1099                 priv->tx_skbuff_dma[i].buf = 0;
1100                 priv->tx_skbuff_dma[i].map_as_page = false;
1101                 priv->tx_skbuff[i] = NULL;
1102         }
1103
1104         priv->dirty_tx = 0;
1105         priv->cur_tx = 0;
1106         netdev_reset_queue(priv->dev);
1107
1108         stmmac_clear_descriptors(priv);
1109
1110         if (netif_msg_hw(priv))
1111                 stmmac_display_rings(priv);
1112
1113         return 0;
1114 err_init_rx_buffers:
1115         while (--i >= 0)
1116                 stmmac_free_rx_buffers(priv, i);
1117         return ret;
1118 }
1119
1120 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1121 {
1122         int i;
1123
1124         for (i = 0; i < priv->dma_rx_size; i++)
1125                 stmmac_free_rx_buffers(priv, i);
1126 }
1127
1128 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1129 {
1130         int i;
1131
1132         for (i = 0; i < priv->dma_tx_size; i++) {
1133                 struct dma_desc *p;
1134
1135                 if (priv->extend_desc)
1136                         p = &((priv->dma_etx + i)->basic);
1137                 else
1138                         p = priv->dma_tx + i;
1139
1140                 if (priv->tx_skbuff_dma[i].buf) {
1141                         if (priv->tx_skbuff_dma[i].map_as_page)
1142                                 dma_unmap_page(priv->device,
1143                                                priv->tx_skbuff_dma[i].buf,
1144                                                priv->hw->desc->get_tx_len(p),
1145                                                DMA_TO_DEVICE);
1146                         else
1147                                 dma_unmap_single(priv->device,
1148                                                  priv->tx_skbuff_dma[i].buf,
1149                                                  priv->hw->desc->get_tx_len(p),
1150                                                  DMA_TO_DEVICE);
1151                 }
1152
1153                 if (priv->tx_skbuff[i] != NULL) {
1154                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1155                         priv->tx_skbuff[i] = NULL;
1156                         priv->tx_skbuff_dma[i].buf = 0;
1157                         priv->tx_skbuff_dma[i].map_as_page = false;
1158                 }
1159         }
1160 }
1161
1162 /**
1163  * alloc_dma_desc_resources - alloc TX/RX resources.
1164  * @priv: private structure
1165  * Description: according to which descriptor can be used (extend or basic)
1166  * this function allocates the resources for TX and RX paths. In case of
1167  * reception, for example, it pre-allocated the RX socket buffer in order to
1168  * allow zero-copy mechanism.
1169  */
1170 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1171 {
1172         unsigned int txsize = priv->dma_tx_size;
1173         unsigned int rxsize = priv->dma_rx_size;
1174         int ret = -ENOMEM;
1175
1176         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1177                                             GFP_KERNEL);
1178         if (!priv->rx_skbuff_dma)
1179                 return -ENOMEM;
1180
1181         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1182                                         GFP_KERNEL);
1183         if (!priv->rx_skbuff)
1184                 goto err_rx_skbuff;
1185
1186         priv->tx_skbuff_dma = kmalloc_array(txsize,
1187                                             sizeof(*priv->tx_skbuff_dma),
1188                                             GFP_KERNEL);
1189         if (!priv->tx_skbuff_dma)
1190                 goto err_tx_skbuff_dma;
1191
1192         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1193                                         GFP_KERNEL);
1194         if (!priv->tx_skbuff)
1195                 goto err_tx_skbuff;
1196
1197         if (priv->extend_desc) {
1198                 priv->dma_erx = dma_zalloc_coherent(priv->device, rxsize *
1199                                                     sizeof(struct
1200                                                            dma_extended_desc),
1201                                                     &priv->dma_rx_phy,
1202                                                     GFP_KERNEL);
1203                 if (!priv->dma_erx)
1204                         goto err_dma;
1205
1206                 priv->dma_etx = dma_zalloc_coherent(priv->device, txsize *
1207                                                     sizeof(struct
1208                                                            dma_extended_desc),
1209                                                     &priv->dma_tx_phy,
1210                                                     GFP_KERNEL);
1211                 if (!priv->dma_etx) {
1212                         dma_free_coherent(priv->device, priv->dma_rx_size *
1213                                           sizeof(struct dma_extended_desc),
1214                                           priv->dma_erx, priv->dma_rx_phy);
1215                         goto err_dma;
1216                 }
1217         } else {
1218                 priv->dma_rx = dma_zalloc_coherent(priv->device, rxsize *
1219                                                    sizeof(struct dma_desc),
1220                                                    &priv->dma_rx_phy,
1221                                                    GFP_KERNEL);
1222                 if (!priv->dma_rx)
1223                         goto err_dma;
1224
1225                 priv->dma_tx = dma_zalloc_coherent(priv->device, txsize *
1226                                                    sizeof(struct dma_desc),
1227                                                    &priv->dma_tx_phy,
1228                                                    GFP_KERNEL);
1229                 if (!priv->dma_tx) {
1230                         dma_free_coherent(priv->device, priv->dma_rx_size *
1231                                           sizeof(struct dma_desc),
1232                                           priv->dma_rx, priv->dma_rx_phy);
1233                         goto err_dma;
1234                 }
1235         }
1236
1237         return 0;
1238
1239 err_dma:
1240         kfree(priv->tx_skbuff);
1241 err_tx_skbuff:
1242         kfree(priv->tx_skbuff_dma);
1243 err_tx_skbuff_dma:
1244         kfree(priv->rx_skbuff);
1245 err_rx_skbuff:
1246         kfree(priv->rx_skbuff_dma);
1247         return ret;
1248 }
1249
1250 static void free_dma_desc_resources(struct stmmac_priv *priv)
1251 {
1252         /* Release the DMA TX/RX socket buffers */
1253         dma_free_rx_skbufs(priv);
1254         dma_free_tx_skbufs(priv);
1255
1256         /* Free DMA regions of consistent memory previously allocated */
1257         if (!priv->extend_desc) {
1258                 dma_free_coherent(priv->device,
1259                                   priv->dma_tx_size * sizeof(struct dma_desc),
1260                                   priv->dma_tx, priv->dma_tx_phy);
1261                 dma_free_coherent(priv->device,
1262                                   priv->dma_rx_size * sizeof(struct dma_desc),
1263                                   priv->dma_rx, priv->dma_rx_phy);
1264         } else {
1265                 dma_free_coherent(priv->device, priv->dma_tx_size *
1266                                   sizeof(struct dma_extended_desc),
1267                                   priv->dma_etx, priv->dma_tx_phy);
1268                 dma_free_coherent(priv->device, priv->dma_rx_size *
1269                                   sizeof(struct dma_extended_desc),
1270                                   priv->dma_erx, priv->dma_rx_phy);
1271         }
1272         kfree(priv->rx_skbuff_dma);
1273         kfree(priv->rx_skbuff);
1274         kfree(priv->tx_skbuff_dma);
1275         kfree(priv->tx_skbuff);
1276 }
1277
1278 /**
1279  *  stmmac_dma_operation_mode - HW DMA operation mode
1280  *  @priv: driver private structure
1281  *  Description: it is used for configuring the DMA operation mode register in
1282  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1283  */
1284 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1285 {
1286         int rxfifosz = priv->plat->rx_fifo_size;
1287
1288         if (priv->plat->force_thresh_dma_mode)
1289                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1290         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1291                 /*
1292                  * In case of GMAC, SF mode can be enabled
1293                  * to perform the TX COE in HW. This depends on:
1294                  * 1) TX COE if actually supported
1295                  * 2) There is no bugged Jumbo frame support
1296                  *    that needs to not insert csum in the TDES.
1297                  */
1298                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1299                                         rxfifosz);
1300                 priv->xstats.threshold = SF_DMA_MODE;
1301         } else
1302                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1303                                         rxfifosz);
1304 }
1305
1306 /**
1307  * stmmac_tx_clean - to manage the transmission completion
1308  * @priv: driver private structure
1309  * Description: it reclaims the transmit resources after transmission completes.
1310  */
1311 static void stmmac_tx_clean(struct stmmac_priv *priv)
1312 {
1313         unsigned int txsize = priv->dma_tx_size;
1314         unsigned int bytes_compl = 0, pkts_compl = 0;
1315
1316         spin_lock(&priv->tx_lock);
1317
1318         priv->xstats.tx_clean++;
1319
1320         while (priv->dirty_tx != priv->cur_tx) {
1321                 int last;
1322                 unsigned int entry = priv->dirty_tx % txsize;
1323                 struct sk_buff *skb = priv->tx_skbuff[entry];
1324                 struct dma_desc *p;
1325
1326                 if (priv->extend_desc)
1327                         p = (struct dma_desc *)(priv->dma_etx + entry);
1328                 else
1329                         p = priv->dma_tx + entry;
1330
1331                 /* Check if the descriptor is owned by the DMA. */
1332                 if (priv->hw->desc->get_tx_owner(p))
1333                         break;
1334
1335                 /* Verify tx error by looking at the last segment. */
1336                 last = priv->hw->desc->get_tx_ls(p);
1337                 if (likely(last)) {
1338                         int tx_error =
1339                             priv->hw->desc->tx_status(&priv->dev->stats,
1340                                                       &priv->xstats, p,
1341                                                       priv->ioaddr);
1342                         if (likely(tx_error == 0)) {
1343                                 priv->dev->stats.tx_packets++;
1344                                 priv->xstats.tx_pkt_n++;
1345                         } else
1346                                 priv->dev->stats.tx_errors++;
1347
1348                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1349                 }
1350                 if (netif_msg_tx_done(priv))
1351                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1352                                  priv->cur_tx, priv->dirty_tx);
1353
1354                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1355                         if (priv->tx_skbuff_dma[entry].map_as_page)
1356                                 dma_unmap_page(priv->device,
1357                                                priv->tx_skbuff_dma[entry].buf,
1358                                                priv->hw->desc->get_tx_len(p),
1359                                                DMA_TO_DEVICE);
1360                         else
1361                                 dma_unmap_single(priv->device,
1362                                                  priv->tx_skbuff_dma[entry].buf,
1363                                                  priv->hw->desc->get_tx_len(p),
1364                                                  DMA_TO_DEVICE);
1365                         priv->tx_skbuff_dma[entry].buf = 0;
1366                         priv->tx_skbuff_dma[entry].map_as_page = false;
1367                 }
1368                 priv->hw->mode->clean_desc3(priv, p);
1369
1370                 if (likely(skb != NULL)) {
1371                         pkts_compl++;
1372                         bytes_compl += skb->len;
1373                         dev_consume_skb_any(skb);
1374                         priv->tx_skbuff[entry] = NULL;
1375                 }
1376
1377                 priv->hw->desc->release_tx_desc(p, priv->mode);
1378
1379                 priv->dirty_tx++;
1380         }
1381
1382         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1383
1384         if (unlikely(netif_queue_stopped(priv->dev) &&
1385                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1386                 netif_tx_lock(priv->dev);
1387                 if (netif_queue_stopped(priv->dev) &&
1388                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1389                         if (netif_msg_tx_done(priv))
1390                                 pr_debug("%s: restart transmit\n", __func__);
1391                         netif_wake_queue(priv->dev);
1392                 }
1393                 netif_tx_unlock(priv->dev);
1394         }
1395
1396         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1397                 stmmac_enable_eee_mode(priv);
1398                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1399         }
1400         spin_unlock(&priv->tx_lock);
1401 }
1402
1403 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1404 {
1405         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1406 }
1407
1408 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1409 {
1410         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1411 }
1412
1413 /**
1414  * stmmac_tx_err - to manage the tx error
1415  * @priv: driver private structure
1416  * Description: it cleans the descriptors and restarts the transmission
1417  * in case of transmission errors.
1418  */
1419 static void stmmac_tx_err(struct stmmac_priv *priv)
1420 {
1421         int i;
1422         int txsize = priv->dma_tx_size;
1423         netif_stop_queue(priv->dev);
1424
1425         priv->hw->dma->stop_tx(priv->ioaddr);
1426         dma_free_tx_skbufs(priv);
1427         for (i = 0; i < txsize; i++)
1428                 if (priv->extend_desc)
1429                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1430                                                      priv->mode,
1431                                                      (i == txsize - 1));
1432                 else
1433                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1434                                                      priv->mode,
1435                                                      (i == txsize - 1));
1436         priv->dirty_tx = 0;
1437         priv->cur_tx = 0;
1438         netdev_reset_queue(priv->dev);
1439         priv->hw->dma->start_tx(priv->ioaddr);
1440
1441         priv->dev->stats.tx_errors++;
1442         netif_wake_queue(priv->dev);
1443 }
1444
1445 /**
1446  * stmmac_dma_interrupt - DMA ISR
1447  * @priv: driver private structure
1448  * Description: this is the DMA ISR. It is called by the main ISR.
1449  * It calls the dwmac dma routine and schedule poll method in case of some
1450  * work can be done.
1451  */
1452 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1453 {
1454         int status;
1455         int rxfifosz = priv->plat->rx_fifo_size;
1456
1457         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1458         if (likely((status & handle_rx)) || (status & handle_tx)) {
1459                 if (likely(napi_schedule_prep(&priv->napi))) {
1460                         stmmac_disable_dma_irq(priv);
1461                         __napi_schedule(&priv->napi);
1462                 }
1463         }
1464         if (unlikely(status & tx_hard_error_bump_tc)) {
1465                 /* Try to bump up the dma threshold on this failure */
1466                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1467                     (tc <= 256)) {
1468                         tc += 64;
1469                         if (priv->plat->force_thresh_dma_mode)
1470                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1471                                                         rxfifosz);
1472                         else
1473                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1474                                                         SF_DMA_MODE, rxfifosz);
1475                         priv->xstats.threshold = tc;
1476                 }
1477         } else if (unlikely(status == tx_hard_error))
1478                 stmmac_tx_err(priv);
1479 }
1480
1481 /**
1482  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1483  * @priv: driver private structure
1484  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1485  */
1486 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1487 {
1488         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1489             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1490
1491         dwmac_mmc_intr_all_mask(priv->ioaddr);
1492
1493         if (priv->dma_cap.rmon) {
1494                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1495                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1496         } else
1497                 pr_info(" No MAC Management Counters available\n");
1498 }
1499
1500 /**
1501  * stmmac_get_synopsys_id - return the SYINID.
1502  * @priv: driver private structure
1503  * Description: this simple function is to decode and return the SYINID
1504  * starting from the HW core register.
1505  */
1506 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1507 {
1508         u32 hwid = priv->hw->synopsys_uid;
1509
1510         /* Check Synopsys Id (not available on old chips) */
1511         if (likely(hwid)) {
1512                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1513                 u32 synid = (hwid & 0x000000ff);
1514
1515                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1516                         uid, synid);
1517
1518                 return synid;
1519         }
1520         return 0;
1521 }
1522
1523 /**
1524  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1525  * @priv: driver private structure
1526  * Description: select the Enhanced/Alternate or Normal descriptors.
1527  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1528  * supported by the HW capability register.
1529  */
1530 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1531 {
1532         if (priv->plat->enh_desc) {
1533                 pr_info(" Enhanced/Alternate descriptors\n");
1534
1535                 /* GMAC older than 3.50 has no extended descriptors */
1536                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1537                         pr_info("\tEnabled extended descriptors\n");
1538                         priv->extend_desc = 1;
1539                 } else
1540                         pr_warn("Extended descriptors not supported\n");
1541
1542                 priv->hw->desc = &enh_desc_ops;
1543         } else {
1544                 pr_info(" Normal descriptors\n");
1545                 priv->hw->desc = &ndesc_ops;
1546         }
1547 }
1548
1549 /**
1550  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1551  * @priv: driver private structure
1552  * Description:
1553  *  new GMAC chip generations have a new register to indicate the
1554  *  presence of the optional feature/functions.
1555  *  This can be also used to override the value passed through the
1556  *  platform and necessary for old MAC10/100 and GMAC chips.
1557  */
1558 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1559 {
1560         u32 hw_cap = 0;
1561
1562         if (priv->hw->dma->get_hw_feature) {
1563                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1564
1565                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1566                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1567                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1568                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1569                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1570                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1571                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1572                 priv->dma_cap.pmt_remote_wake_up =
1573                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1574                 priv->dma_cap.pmt_magic_frame =
1575                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1576                 /* MMC */
1577                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1578                 /* IEEE 1588-2002 */
1579                 priv->dma_cap.time_stamp =
1580                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1581                 /* IEEE 1588-2008 */
1582                 priv->dma_cap.atime_stamp =
1583                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1584                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1585                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1586                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1587                 /* TX and RX csum */
1588                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1589                 priv->dma_cap.rx_coe_type1 =
1590                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1591                 priv->dma_cap.rx_coe_type2 =
1592                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1593                 priv->dma_cap.rxfifo_over_2048 =
1594                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1595                 /* TX and RX number of channels */
1596                 priv->dma_cap.number_rx_channel =
1597                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1598                 priv->dma_cap.number_tx_channel =
1599                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1600                 /* Alternate (enhanced) DESC mode */
1601                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1602         }
1603
1604         return hw_cap;
1605 }
1606
1607 /**
1608  * stmmac_check_ether_addr - check if the MAC addr is valid
1609  * @priv: driver private structure
1610  * Description:
1611  * it is to verify if the MAC address is valid, in case of failures it
1612  * generates a random MAC address
1613  */
1614 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1615 {
1616         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1617                 priv->hw->mac->get_umac_addr(priv->hw,
1618                                              priv->dev->dev_addr, 0);
1619                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1620                         eth_hw_addr_random(priv->dev);
1621                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1622                         priv->dev->dev_addr);
1623         }
1624 }
1625
1626 /**
1627  * stmmac_init_dma_engine - DMA init.
1628  * @priv: driver private structure
1629  * Description:
1630  * It inits the DMA invoking the specific MAC/GMAC callback.
1631  * Some DMA parameters can be passed from the platform;
1632  * in case of these are not passed a default is kept for the MAC or GMAC.
1633  */
1634 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1635 {
1636         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1637         int mixed_burst = 0;
1638         int atds = 0;
1639
1640         if (priv->plat->dma_cfg) {
1641                 pbl = priv->plat->dma_cfg->pbl;
1642                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1643                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1644                 burst_len = priv->plat->dma_cfg->burst_len;
1645         }
1646
1647         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1648                 atds = 1;
1649
1650         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1651                                    burst_len, priv->dma_tx_phy,
1652                                    priv->dma_rx_phy, atds);
1653 }
1654
1655 /**
1656  * stmmac_tx_timer - mitigation sw timer for tx.
1657  * @data: data pointer
1658  * Description:
1659  * This is the timer handler to directly invoke the stmmac_tx_clean.
1660  */
1661 static void stmmac_tx_timer(unsigned long data)
1662 {
1663         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1664
1665         stmmac_tx_clean(priv);
1666 }
1667
1668 /**
1669  * stmmac_init_tx_coalesce - init tx mitigation options.
1670  * @priv: driver private structure
1671  * Description:
1672  * This inits the transmit coalesce parameters: i.e. timer rate,
1673  * timer handler and default threshold used for enabling the
1674  * interrupt on completion bit.
1675  */
1676 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1677 {
1678         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1679         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1680         init_timer(&priv->txtimer);
1681         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1682         priv->txtimer.data = (unsigned long)priv;
1683         priv->txtimer.function = stmmac_tx_timer;
1684         add_timer(&priv->txtimer);
1685 }
1686
1687 /**
1688  * stmmac_hw_setup - setup mac in a usable state.
1689  *  @dev : pointer to the device structure.
1690  *  Description:
1691  *  this is the main function to setup the HW in a usable state because the
1692  *  dma engine is reset, the core registers are configured (e.g. AXI,
1693  *  Checksum features, timers). The DMA is ready to start receiving and
1694  *  transmitting.
1695  *  Return value:
1696  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1697  *  file on failure.
1698  */
1699 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1700 {
1701         struct stmmac_priv *priv = netdev_priv(dev);
1702         int ret;
1703
1704         /* DMA initialization and SW reset */
1705         ret = stmmac_init_dma_engine(priv);
1706         if (ret < 0) {
1707                 pr_err("%s: DMA engine initialization failed\n", __func__);
1708                 return ret;
1709         }
1710
1711         /* Copy the MAC addr into the HW  */
1712         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1713
1714         /* If required, perform hw setup of the bus. */
1715         if (priv->plat->bus_setup)
1716                 priv->plat->bus_setup(priv->ioaddr);
1717
1718         /* Initialize the MAC Core */
1719         priv->hw->mac->core_init(priv->hw, dev->mtu);
1720
1721         ret = priv->hw->mac->rx_ipc(priv->hw);
1722         if (!ret) {
1723                 pr_warn(" RX IPC Checksum Offload disabled\n");
1724                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1725                 priv->hw->rx_csum = 0;
1726         }
1727
1728         /* Enable the MAC Rx/Tx */
1729         stmmac_set_mac(priv->ioaddr, true);
1730
1731         /* Set the HW DMA mode and the COE */
1732         stmmac_dma_operation_mode(priv);
1733
1734         stmmac_mmc_setup(priv);
1735
1736         if (init_ptp) {
1737                 ret = stmmac_init_ptp(priv);
1738                 if (ret && ret != -EOPNOTSUPP)
1739                         pr_warn("%s: failed PTP initialisation\n", __func__);
1740         }
1741
1742 #ifdef CONFIG_DEBUG_FS
1743         ret = stmmac_init_fs(dev);
1744         if (ret < 0)
1745                 pr_warn("%s: failed debugFS registration\n", __func__);
1746 #endif
1747         /* Start the ball rolling... */
1748         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1749         priv->hw->dma->start_tx(priv->ioaddr);
1750         priv->hw->dma->start_rx(priv->ioaddr);
1751
1752         /* Dump DMA/MAC registers */
1753         if (netif_msg_hw(priv)) {
1754                 priv->hw->mac->dump_regs(priv->hw);
1755                 priv->hw->dma->dump_regs(priv->ioaddr);
1756         }
1757         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1758
1759         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1760                 priv->rx_riwt = MAX_DMA_RIWT;
1761                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1762         }
1763
1764         if (priv->pcs && priv->hw->mac->ctrl_ane)
1765                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1766
1767         return 0;
1768 }
1769
1770 /**
1771  *  stmmac_open - open entry point of the driver
1772  *  @dev : pointer to the device structure.
1773  *  Description:
1774  *  This function is the open entry point of the driver.
1775  *  Return value:
1776  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1777  *  file on failure.
1778  */
1779 static int stmmac_open(struct net_device *dev)
1780 {
1781         struct stmmac_priv *priv = netdev_priv(dev);
1782         int ret;
1783
1784         stmmac_check_ether_addr(priv);
1785
1786         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1787             priv->pcs != STMMAC_PCS_RTBI) {
1788                 ret = stmmac_init_phy(dev);
1789                 if (ret) {
1790                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1791                                __func__, ret);
1792                         return ret;
1793                 }
1794         }
1795
1796         /* Extra statistics */
1797         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1798         priv->xstats.threshold = tc;
1799
1800         /* Create and initialize the TX/RX descriptors chains. */
1801         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1802         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1803         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1804
1805         ret = alloc_dma_desc_resources(priv);
1806         if (ret < 0) {
1807                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1808                 goto dma_desc_error;
1809         }
1810
1811         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1812         if (ret < 0) {
1813                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1814                 goto init_error;
1815         }
1816
1817         ret = stmmac_hw_setup(dev, true);
1818         if (ret < 0) {
1819                 pr_err("%s: Hw setup failed\n", __func__);
1820                 goto init_error;
1821         }
1822
1823         stmmac_init_tx_coalesce(priv);
1824
1825         if (priv->phydev)
1826                 phy_start(priv->phydev);
1827
1828         /* Request the IRQ lines */
1829         ret = request_irq(dev->irq, stmmac_interrupt,
1830                           IRQF_SHARED, dev->name, dev);
1831         if (unlikely(ret < 0)) {
1832                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1833                        __func__, dev->irq, ret);
1834                 goto init_error;
1835         }
1836
1837         /* Request the Wake IRQ in case of another line is used for WoL */
1838         if (priv->wol_irq != dev->irq) {
1839                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1840                                   IRQF_SHARED, dev->name, dev);
1841                 if (unlikely(ret < 0)) {
1842                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1843                                __func__, priv->wol_irq, ret);
1844                         goto wolirq_error;
1845                 }
1846         }
1847
1848         /* Request the IRQ lines */
1849         if (priv->lpi_irq > 0) {
1850                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1851                                   dev->name, dev);
1852                 if (unlikely(ret < 0)) {
1853                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1854                                __func__, priv->lpi_irq, ret);
1855                         goto lpiirq_error;
1856                 }
1857         }
1858
1859         napi_enable(&priv->napi);
1860         netif_start_queue(dev);
1861
1862         return 0;
1863
1864 lpiirq_error:
1865         if (priv->wol_irq != dev->irq)
1866                 free_irq(priv->wol_irq, dev);
1867 wolirq_error:
1868         free_irq(dev->irq, dev);
1869
1870 init_error:
1871         free_dma_desc_resources(priv);
1872 dma_desc_error:
1873         if (priv->phydev)
1874                 phy_disconnect(priv->phydev);
1875
1876         return ret;
1877 }
1878
1879 /**
1880  *  stmmac_release - close entry point of the driver
1881  *  @dev : device pointer.
1882  *  Description:
1883  *  This is the stop entry point of the driver.
1884  */
1885 static int stmmac_release(struct net_device *dev)
1886 {
1887         struct stmmac_priv *priv = netdev_priv(dev);
1888
1889         if (priv->eee_enabled)
1890                 del_timer_sync(&priv->eee_ctrl_timer);
1891
1892         /* Stop and disconnect the PHY */
1893         if (priv->phydev) {
1894                 phy_stop(priv->phydev);
1895                 phy_disconnect(priv->phydev);
1896                 priv->phydev = NULL;
1897         }
1898
1899         netif_stop_queue(dev);
1900
1901         napi_disable(&priv->napi);
1902
1903         del_timer_sync(&priv->txtimer);
1904
1905         /* Free the IRQ lines */
1906         free_irq(dev->irq, dev);
1907         if (priv->wol_irq != dev->irq)
1908                 free_irq(priv->wol_irq, dev);
1909         if (priv->lpi_irq > 0)
1910                 free_irq(priv->lpi_irq, dev);
1911
1912         /* Stop TX/RX DMA and clear the descriptors */
1913         priv->hw->dma->stop_tx(priv->ioaddr);
1914         priv->hw->dma->stop_rx(priv->ioaddr);
1915
1916         /* Release and free the Rx/Tx resources */
1917         free_dma_desc_resources(priv);
1918
1919         /* Disable the MAC Rx/Tx */
1920         stmmac_set_mac(priv->ioaddr, false);
1921
1922         netif_carrier_off(dev);
1923
1924 #ifdef CONFIG_DEBUG_FS
1925         stmmac_exit_fs(dev);
1926 #endif
1927
1928         stmmac_release_ptp(priv);
1929
1930         return 0;
1931 }
1932
1933 /**
1934  *  stmmac_xmit - Tx entry point of the driver
1935  *  @skb : the socket buffer
1936  *  @dev : device pointer
1937  *  Description : this is the tx entry point of the driver.
1938  *  It programs the chain or the ring and supports oversized frames
1939  *  and SG feature.
1940  */
1941 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1942 {
1943         struct stmmac_priv *priv = netdev_priv(dev);
1944         unsigned int txsize = priv->dma_tx_size;
1945         unsigned int entry;
1946         int i, csum_insertion = 0, is_jumbo = 0;
1947         int nfrags = skb_shinfo(skb)->nr_frags;
1948         struct dma_desc *desc, *first;
1949         unsigned int nopaged_len = skb_headlen(skb);
1950         unsigned int enh_desc = priv->plat->enh_desc;
1951
1952         spin_lock(&priv->tx_lock);
1953
1954         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1955                 spin_unlock(&priv->tx_lock);
1956                 if (!netif_queue_stopped(dev)) {
1957                         netif_stop_queue(dev);
1958                         /* This is a hard error, log it. */
1959                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1960                 }
1961                 return NETDEV_TX_BUSY;
1962         }
1963
1964         if (priv->tx_path_in_lpi_mode)
1965                 stmmac_disable_eee_mode(priv);
1966
1967         entry = priv->cur_tx % txsize;
1968
1969         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1970
1971         if (priv->extend_desc)
1972                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1973         else
1974                 desc = priv->dma_tx + entry;
1975
1976         first = desc;
1977
1978         /* To program the descriptors according to the size of the frame */
1979         if (enh_desc)
1980                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1981
1982         if (likely(!is_jumbo)) {
1983                 desc->des2 = dma_map_single(priv->device, skb->data,
1984                                             nopaged_len, DMA_TO_DEVICE);
1985                 if (dma_mapping_error(priv->device, desc->des2))
1986                         goto dma_map_err;
1987                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1988                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1989                                                 csum_insertion, priv->mode);
1990         } else {
1991                 desc = first;
1992                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1993                 if (unlikely(entry < 0))
1994                         goto dma_map_err;
1995         }
1996
1997         for (i = 0; i < nfrags; i++) {
1998                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1999                 int len = skb_frag_size(frag);
2000
2001                 priv->tx_skbuff[entry] = NULL;
2002                 entry = (++priv->cur_tx) % txsize;
2003                 if (priv->extend_desc)
2004                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2005                 else
2006                         desc = priv->dma_tx + entry;
2007
2008                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2009                                               DMA_TO_DEVICE);
2010                 if (dma_mapping_error(priv->device, desc->des2))
2011                         goto dma_map_err; /* should reuse desc w/o issues */
2012
2013                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2014                 priv->tx_skbuff_dma[entry].map_as_page = true;
2015                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2016                                                 priv->mode);
2017                 wmb();
2018                 priv->hw->desc->set_tx_owner(desc);
2019                 wmb();
2020         }
2021
2022         priv->tx_skbuff[entry] = skb;
2023
2024         /* Finalize the latest segment. */
2025         priv->hw->desc->close_tx_desc(desc);
2026
2027         wmb();
2028         /* According to the coalesce parameter the IC bit for the latest
2029          * segment could be reset and the timer re-started to invoke the
2030          * stmmac_tx function. This approach takes care about the fragments.
2031          */
2032         priv->tx_count_frames += nfrags + 1;
2033         if (priv->tx_coal_frames > priv->tx_count_frames) {
2034                 priv->hw->desc->clear_tx_ic(desc);
2035                 priv->xstats.tx_reset_ic_bit++;
2036                 mod_timer(&priv->txtimer,
2037                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2038         } else
2039                 priv->tx_count_frames = 0;
2040
2041         /* To avoid raise condition */
2042         priv->hw->desc->set_tx_owner(first);
2043         wmb();
2044
2045         priv->cur_tx++;
2046
2047         if (netif_msg_pktdata(priv)) {
2048                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2049                         __func__, (priv->cur_tx % txsize),
2050                         (priv->dirty_tx % txsize), entry, first, nfrags);
2051
2052                 if (priv->extend_desc)
2053                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2054                 else
2055                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2056
2057                 pr_debug(">>> frame to be transmitted: ");
2058                 print_pkt(skb->data, skb->len);
2059         }
2060         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2061                 if (netif_msg_hw(priv))
2062                         pr_debug("%s: stop transmitted packets\n", __func__);
2063                 netif_stop_queue(dev);
2064         }
2065
2066         dev->stats.tx_bytes += skb->len;
2067
2068         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2069                      priv->hwts_tx_en)) {
2070                 /* declare that device is doing timestamping */
2071                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2072                 priv->hw->desc->enable_tx_timestamp(first);
2073         }
2074
2075         if (!priv->hwts_tx_en)
2076                 skb_tx_timestamp(skb);
2077
2078         netdev_sent_queue(dev, skb->len);
2079         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2080
2081         spin_unlock(&priv->tx_lock);
2082         return NETDEV_TX_OK;
2083
2084 dma_map_err:
2085         spin_unlock(&priv->tx_lock);
2086         dev_err(priv->device, "Tx dma map failed\n");
2087         dev_kfree_skb(skb);
2088         priv->dev->stats.tx_dropped++;
2089         return NETDEV_TX_OK;
2090 }
2091
2092 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2093 {
2094         struct ethhdr *ehdr;
2095         u16 vlanid;
2096
2097         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2098             NETIF_F_HW_VLAN_CTAG_RX &&
2099             !__vlan_get_tag(skb, &vlanid)) {
2100                 /* pop the vlan tag */
2101                 ehdr = (struct ethhdr *)skb->data;
2102                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2103                 skb_pull(skb, VLAN_HLEN);
2104                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2105         }
2106 }
2107
2108
2109 /**
2110  * stmmac_rx_refill - refill used skb preallocated buffers
2111  * @priv: driver private structure
2112  * Description : this is to reallocate the skb for the reception process
2113  * that is based on zero-copy.
2114  */
2115 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2116 {
2117         unsigned int rxsize = priv->dma_rx_size;
2118         int bfsize = priv->dma_buf_sz;
2119
2120         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2121                 unsigned int entry = priv->dirty_rx % rxsize;
2122                 struct dma_desc *p;
2123
2124                 if (priv->extend_desc)
2125                         p = (struct dma_desc *)(priv->dma_erx + entry);
2126                 else
2127                         p = priv->dma_rx + entry;
2128
2129                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2130                         struct sk_buff *skb;
2131
2132                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2133
2134                         if (unlikely(skb == NULL))
2135                                 break;
2136
2137                         priv->rx_skbuff[entry] = skb;
2138                         priv->rx_skbuff_dma[entry] =
2139                             dma_map_single(priv->device, skb->data, bfsize,
2140                                            DMA_FROM_DEVICE);
2141                         if (dma_mapping_error(priv->device,
2142                                               priv->rx_skbuff_dma[entry])) {
2143                                 dev_err(priv->device, "Rx dma map failed\n");
2144                                 dev_kfree_skb(skb);
2145                                 break;
2146                         }
2147                         p->des2 = priv->rx_skbuff_dma[entry];
2148
2149                         priv->hw->mode->refill_desc3(priv, p);
2150
2151                         if (netif_msg_rx_status(priv))
2152                                 pr_debug("\trefill entry #%d\n", entry);
2153                 }
2154                 wmb();
2155                 priv->hw->desc->set_rx_owner(p);
2156                 wmb();
2157         }
2158 }
2159
2160 /**
2161  * stmmac_rx - manage the receive process
2162  * @priv: driver private structure
2163  * @limit: napi bugget.
2164  * Description :  this the function called by the napi poll method.
2165  * It gets all the frames inside the ring.
2166  */
2167 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2168 {
2169         unsigned int rxsize = priv->dma_rx_size;
2170         unsigned int entry = priv->cur_rx % rxsize;
2171         unsigned int next_entry;
2172         unsigned int count = 0;
2173         int coe = priv->hw->rx_csum;
2174
2175         if (netif_msg_rx_status(priv)) {
2176                 pr_debug("%s: descriptor ring:\n", __func__);
2177                 if (priv->extend_desc)
2178                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2179                 else
2180                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2181         }
2182         while (count < limit) {
2183                 int status;
2184                 struct dma_desc *p;
2185
2186                 if (priv->extend_desc)
2187                         p = (struct dma_desc *)(priv->dma_erx + entry);
2188                 else
2189                         p = priv->dma_rx + entry;
2190
2191                 if (priv->hw->desc->get_rx_owner(p))
2192                         break;
2193
2194                 count++;
2195
2196                 next_entry = (++priv->cur_rx) % rxsize;
2197                 if (priv->extend_desc)
2198                         prefetch(priv->dma_erx + next_entry);
2199                 else
2200                         prefetch(priv->dma_rx + next_entry);
2201
2202                 /* read the status of the incoming frame */
2203                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2204                                                    &priv->xstats, p);
2205                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2206                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2207                                                            &priv->xstats,
2208                                                            priv->dma_erx +
2209                                                            entry);
2210                 if (unlikely(status == discard_frame)) {
2211                         priv->dev->stats.rx_errors++;
2212                         if (priv->hwts_rx_en && !priv->extend_desc) {
2213                                 /* DESC2 & DESC3 will be overwitten by device
2214                                  * with timestamp value, hence reinitialize
2215                                  * them in stmmac_rx_refill() function so that
2216                                  * device can reuse it.
2217                                  */
2218                                 priv->rx_skbuff[entry] = NULL;
2219                                 dma_unmap_single(priv->device,
2220                                                  priv->rx_skbuff_dma[entry],
2221                                                  priv->dma_buf_sz,
2222                                                  DMA_FROM_DEVICE);
2223                         }
2224                 } else {
2225                         struct sk_buff *skb;
2226                         int frame_len;
2227
2228                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2229
2230                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2231                          * Type frames (LLC/LLC-SNAP)
2232                          */
2233                         if (unlikely(status != llc_snap))
2234                                 frame_len -= ETH_FCS_LEN;
2235
2236                         if (netif_msg_rx_status(priv)) {
2237                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2238                                          p, entry, p->des2);
2239                                 if (frame_len > ETH_FRAME_LEN)
2240                                         pr_debug("\tframe size %d, COE: %d\n",
2241                                                  frame_len, status);
2242                         }
2243                         skb = priv->rx_skbuff[entry];
2244                         if (unlikely(!skb)) {
2245                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2246                                        priv->dev->name);
2247                                 priv->dev->stats.rx_dropped++;
2248                                 break;
2249                         }
2250                         prefetch(skb->data - NET_IP_ALIGN);
2251                         priv->rx_skbuff[entry] = NULL;
2252
2253                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2254
2255                         skb_put(skb, frame_len);
2256                         dma_unmap_single(priv->device,
2257                                          priv->rx_skbuff_dma[entry],
2258                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2259
2260                         if (netif_msg_pktdata(priv)) {
2261                                 pr_debug("frame received (%dbytes)", frame_len);
2262                                 print_pkt(skb->data, frame_len);
2263                         }
2264
2265                         stmmac_rx_vlan(priv->dev, skb);
2266
2267                         skb->protocol = eth_type_trans(skb, priv->dev);
2268
2269                         if (unlikely(!coe))
2270                                 skb_checksum_none_assert(skb);
2271                         else
2272                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2273
2274                         napi_gro_receive(&priv->napi, skb);
2275
2276                         priv->dev->stats.rx_packets++;
2277                         priv->dev->stats.rx_bytes += frame_len;
2278                 }
2279                 entry = next_entry;
2280         }
2281
2282         stmmac_rx_refill(priv);
2283
2284         priv->xstats.rx_pkt_n += count;
2285
2286         return count;
2287 }
2288
2289 /**
2290  *  stmmac_poll - stmmac poll method (NAPI)
2291  *  @napi : pointer to the napi structure.
2292  *  @budget : maximum number of packets that the current CPU can receive from
2293  *            all interfaces.
2294  *  Description :
2295  *  To look at the incoming frames and clear the tx resources.
2296  */
2297 static int stmmac_poll(struct napi_struct *napi, int budget)
2298 {
2299         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2300         int work_done = 0;
2301
2302         priv->xstats.napi_poll++;
2303         stmmac_tx_clean(priv);
2304
2305         work_done = stmmac_rx(priv, budget);
2306         if (work_done < budget) {
2307                 napi_complete(napi);
2308                 stmmac_enable_dma_irq(priv);
2309         }
2310         return work_done;
2311 }
2312
2313 /**
2314  *  stmmac_tx_timeout
2315  *  @dev : Pointer to net device structure
2316  *  Description: this function is called when a packet transmission fails to
2317  *   complete within a reasonable time. The driver will mark the error in the
2318  *   netdev structure and arrange for the device to be reset to a sane state
2319  *   in order to transmit a new packet.
2320  */
2321 static void stmmac_tx_timeout(struct net_device *dev)
2322 {
2323         struct stmmac_priv *priv = netdev_priv(dev);
2324
2325         /* Clear Tx resources and restart transmitting again */
2326         stmmac_tx_err(priv);
2327 }
2328
2329 /**
2330  *  stmmac_set_rx_mode - entry point for multicast addressing
2331  *  @dev : pointer to the device structure
2332  *  Description:
2333  *  This function is a driver entry point which gets called by the kernel
2334  *  whenever multicast addresses must be enabled/disabled.
2335  *  Return value:
2336  *  void.
2337  */
2338 static void stmmac_set_rx_mode(struct net_device *dev)
2339 {
2340         struct stmmac_priv *priv = netdev_priv(dev);
2341
2342         priv->hw->mac->set_filter(priv->hw, dev);
2343 }
2344
2345 /**
2346  *  stmmac_change_mtu - entry point to change MTU size for the device.
2347  *  @dev : device pointer.
2348  *  @new_mtu : the new MTU size for the device.
2349  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2350  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2351  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2352  *  Return value:
2353  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2354  *  file on failure.
2355  */
2356 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2357 {
2358         struct stmmac_priv *priv = netdev_priv(dev);
2359         int max_mtu;
2360
2361         if (netif_running(dev)) {
2362                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2363                 return -EBUSY;
2364         }
2365
2366         if (priv->plat->enh_desc)
2367                 max_mtu = JUMBO_LEN;
2368         else
2369                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2370
2371         if (priv->plat->maxmtu < max_mtu)
2372                 max_mtu = priv->plat->maxmtu;
2373
2374         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2375                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2376                 return -EINVAL;
2377         }
2378
2379         dev->mtu = new_mtu;
2380         netdev_update_features(dev);
2381
2382         return 0;
2383 }
2384
2385 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2386                                              netdev_features_t features)
2387 {
2388         struct stmmac_priv *priv = netdev_priv(dev);
2389
2390         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2391                 features &= ~NETIF_F_RXCSUM;
2392
2393         if (!priv->plat->tx_coe)
2394                 features &= ~NETIF_F_ALL_CSUM;
2395
2396         /* Some GMAC devices have a bugged Jumbo frame support that
2397          * needs to have the Tx COE disabled for oversized frames
2398          * (due to limited buffer sizes). In this case we disable
2399          * the TX csum insertionin the TDES and not use SF.
2400          */
2401         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2402                 features &= ~NETIF_F_ALL_CSUM;
2403
2404         return features;
2405 }
2406
2407 static int stmmac_set_features(struct net_device *netdev,
2408                                netdev_features_t features)
2409 {
2410         struct stmmac_priv *priv = netdev_priv(netdev);
2411
2412         /* Keep the COE Type in case of csum is supporting */
2413         if (features & NETIF_F_RXCSUM)
2414                 priv->hw->rx_csum = priv->plat->rx_coe;
2415         else
2416                 priv->hw->rx_csum = 0;
2417         /* No check needed because rx_coe has been set before and it will be
2418          * fixed in case of issue.
2419          */
2420         priv->hw->mac->rx_ipc(priv->hw);
2421
2422         return 0;
2423 }
2424
2425 /**
2426  *  stmmac_interrupt - main ISR
2427  *  @irq: interrupt number.
2428  *  @dev_id: to pass the net device pointer.
2429  *  Description: this is the main driver interrupt service routine.
2430  *  It can call:
2431  *  o DMA service routine (to manage incoming frame reception and transmission
2432  *    status)
2433  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2434  *    interrupts.
2435  */
2436 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2437 {
2438         struct net_device *dev = (struct net_device *)dev_id;
2439         struct stmmac_priv *priv = netdev_priv(dev);
2440
2441         if (priv->irq_wake)
2442                 pm_wakeup_event(priv->device, 0);
2443
2444         if (unlikely(!dev)) {
2445                 pr_err("%s: invalid dev pointer\n", __func__);
2446                 return IRQ_NONE;
2447         }
2448
2449         /* To handle GMAC own interrupts */
2450         if (priv->plat->has_gmac) {
2451                 int status = priv->hw->mac->host_irq_status(priv->hw,
2452                                                             &priv->xstats);
2453                 if (unlikely(status)) {
2454                         /* For LPI we need to save the tx status */
2455                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2456                                 priv->tx_path_in_lpi_mode = true;
2457                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2458                                 priv->tx_path_in_lpi_mode = false;
2459                 }
2460         }
2461
2462         /* To handle DMA interrupts */
2463         stmmac_dma_interrupt(priv);
2464
2465         return IRQ_HANDLED;
2466 }
2467
2468 #ifdef CONFIG_NET_POLL_CONTROLLER
2469 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2470  * to allow network I/O with interrupts disabled.
2471  */
2472 static void stmmac_poll_controller(struct net_device *dev)
2473 {
2474         disable_irq(dev->irq);
2475         stmmac_interrupt(dev->irq, dev);
2476         enable_irq(dev->irq);
2477 }
2478 #endif
2479
2480 /**
2481  *  stmmac_ioctl - Entry point for the Ioctl
2482  *  @dev: Device pointer.
2483  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2484  *  a proprietary structure used to pass information to the driver.
2485  *  @cmd: IOCTL command
2486  *  Description:
2487  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2488  */
2489 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2490 {
2491         struct stmmac_priv *priv = netdev_priv(dev);
2492         int ret = -EOPNOTSUPP;
2493
2494         if (!netif_running(dev))
2495                 return -EINVAL;
2496
2497         switch (cmd) {
2498         case SIOCGMIIPHY:
2499         case SIOCGMIIREG:
2500         case SIOCSMIIREG:
2501                 if (!priv->phydev)
2502                         return -EINVAL;
2503                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2504                 break;
2505         case SIOCSHWTSTAMP:
2506                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2507                 break;
2508         default:
2509                 break;
2510         }
2511
2512         return ret;
2513 }
2514
2515 #ifdef CONFIG_DEBUG_FS
2516 static struct dentry *stmmac_fs_dir;
2517
2518 static void sysfs_display_ring(void *head, int size, int extend_desc,
2519                                struct seq_file *seq)
2520 {
2521         int i;
2522         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2523         struct dma_desc *p = (struct dma_desc *)head;
2524
2525         for (i = 0; i < size; i++) {
2526                 u64 x;
2527                 if (extend_desc) {
2528                         x = *(u64 *) ep;
2529                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2530                                    i, (unsigned int)virt_to_phys(ep),
2531                                    (unsigned int)x, (unsigned int)(x >> 32),
2532                                    ep->basic.des2, ep->basic.des3);
2533                         ep++;
2534                 } else {
2535                         x = *(u64 *) p;
2536                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2537                                    i, (unsigned int)virt_to_phys(ep),
2538                                    (unsigned int)x, (unsigned int)(x >> 32),
2539                                    p->des2, p->des3);
2540                         p++;
2541                 }
2542                 seq_printf(seq, "\n");
2543         }
2544 }
2545
2546 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2547 {
2548         struct net_device *dev = seq->private;
2549         struct stmmac_priv *priv = netdev_priv(dev);
2550         unsigned int txsize = priv->dma_tx_size;
2551         unsigned int rxsize = priv->dma_rx_size;
2552
2553         if (priv->extend_desc) {
2554                 seq_printf(seq, "Extended RX descriptor ring:\n");
2555                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2556                 seq_printf(seq, "Extended TX descriptor ring:\n");
2557                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2558         } else {
2559                 seq_printf(seq, "RX descriptor ring:\n");
2560                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2561                 seq_printf(seq, "TX descriptor ring:\n");
2562                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2563         }
2564
2565         return 0;
2566 }
2567
2568 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2569 {
2570         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2571 }
2572
2573 static const struct file_operations stmmac_rings_status_fops = {
2574         .owner = THIS_MODULE,
2575         .open = stmmac_sysfs_ring_open,
2576         .read = seq_read,
2577         .llseek = seq_lseek,
2578         .release = single_release,
2579 };
2580
2581 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2582 {
2583         struct net_device *dev = seq->private;
2584         struct stmmac_priv *priv = netdev_priv(dev);
2585
2586         if (!priv->hw_cap_support) {
2587                 seq_printf(seq, "DMA HW features not supported\n");
2588                 return 0;
2589         }
2590
2591         seq_printf(seq, "==============================\n");
2592         seq_printf(seq, "\tDMA HW features\n");
2593         seq_printf(seq, "==============================\n");
2594
2595         seq_printf(seq, "\t10/100 Mbps %s\n",
2596                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2597         seq_printf(seq, "\t1000 Mbps %s\n",
2598                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2599         seq_printf(seq, "\tHalf duple %s\n",
2600                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2601         seq_printf(seq, "\tHash Filter: %s\n",
2602                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2603         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2604                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2605         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2606                    (priv->dma_cap.pcs) ? "Y" : "N");
2607         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2608                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2609         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2610                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2611         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2612                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2613         seq_printf(seq, "\tRMON module: %s\n",
2614                    (priv->dma_cap.rmon) ? "Y" : "N");
2615         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2616                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2617         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2618                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2619         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2620                    (priv->dma_cap.eee) ? "Y" : "N");
2621         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2622         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2623                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2624         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2625                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2626         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2627                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2628         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2629                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2630         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2631                    priv->dma_cap.number_rx_channel);
2632         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2633                    priv->dma_cap.number_tx_channel);
2634         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2635                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2636
2637         return 0;
2638 }
2639
2640 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2641 {
2642         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2643 }
2644
2645 static const struct file_operations stmmac_dma_cap_fops = {
2646         .owner = THIS_MODULE,
2647         .open = stmmac_sysfs_dma_cap_open,
2648         .read = seq_read,
2649         .llseek = seq_lseek,
2650         .release = single_release,
2651 };
2652
2653 static int stmmac_init_fs(struct net_device *dev)
2654 {
2655         struct stmmac_priv *priv = netdev_priv(dev);
2656
2657         /* Create per netdev entries */
2658         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2659
2660         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2661                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2662                        STMMAC_RESOURCE_NAME, dev->name);
2663
2664                 return -ENOMEM;
2665         }
2666
2667         /* Entry to report DMA RX/TX rings */
2668         priv->dbgfs_rings_status =
2669                 debugfs_create_file("descriptors_status", S_IRUGO,
2670                                     priv->dbgfs_dir, dev,
2671                                     &stmmac_rings_status_fops);
2672
2673         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2674                 pr_info("ERROR creating stmmac ring debugfs file\n");
2675                 debugfs_remove_recursive(priv->dbgfs_dir);
2676
2677                 return -ENOMEM;
2678         }
2679
2680         /* Entry to report the DMA HW features */
2681         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2682                                             priv->dbgfs_dir,
2683                                             dev, &stmmac_dma_cap_fops);
2684
2685         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2686                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2687                 debugfs_remove_recursive(priv->dbgfs_dir);
2688
2689                 return -ENOMEM;
2690         }
2691
2692         return 0;
2693 }
2694
2695 static void stmmac_exit_fs(struct net_device *dev)
2696 {
2697         struct stmmac_priv *priv = netdev_priv(dev);
2698
2699         debugfs_remove_recursive(priv->dbgfs_dir);
2700 }
2701 #endif /* CONFIG_DEBUG_FS */
2702
2703 static const struct net_device_ops stmmac_netdev_ops = {
2704         .ndo_open = stmmac_open,
2705         .ndo_start_xmit = stmmac_xmit,
2706         .ndo_stop = stmmac_release,
2707         .ndo_change_mtu = stmmac_change_mtu,
2708         .ndo_fix_features = stmmac_fix_features,
2709         .ndo_set_features = stmmac_set_features,
2710         .ndo_set_rx_mode = stmmac_set_rx_mode,
2711         .ndo_tx_timeout = stmmac_tx_timeout,
2712         .ndo_do_ioctl = stmmac_ioctl,
2713 #ifdef CONFIG_NET_POLL_CONTROLLER
2714         .ndo_poll_controller = stmmac_poll_controller,
2715 #endif
2716         .ndo_set_mac_address = eth_mac_addr,
2717 };
2718
2719 /**
2720  *  stmmac_hw_init - Init the MAC device
2721  *  @priv: driver private structure
2722  *  Description: this function is to configure the MAC device according to
2723  *  some platform parameters or the HW capability register. It prepares the
2724  *  driver to use either ring or chain modes and to setup either enhanced or
2725  *  normal descriptors.
2726  */
2727 static int stmmac_hw_init(struct stmmac_priv *priv)
2728 {
2729         struct mac_device_info *mac;
2730
2731         /* Identify the MAC HW device */
2732         if (priv->plat->has_gmac) {
2733                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2734                 mac = dwmac1000_setup(priv->ioaddr,
2735                                       priv->plat->multicast_filter_bins,
2736                                       priv->plat->unicast_filter_entries);
2737         } else {
2738                 mac = dwmac100_setup(priv->ioaddr);
2739         }
2740         if (!mac)
2741                 return -ENOMEM;
2742
2743         priv->hw = mac;
2744
2745         /* Get and dump the chip ID */
2746         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2747
2748         /* To use the chained or ring mode */
2749         if (chain_mode) {
2750                 priv->hw->mode = &chain_mode_ops;
2751                 pr_info(" Chain mode enabled\n");
2752                 priv->mode = STMMAC_CHAIN_MODE;
2753         } else {
2754                 priv->hw->mode = &ring_mode_ops;
2755                 pr_info(" Ring mode enabled\n");
2756                 priv->mode = STMMAC_RING_MODE;
2757         }
2758
2759         /* Get the HW capability (new GMAC newer than 3.50a) */
2760         priv->hw_cap_support = stmmac_get_hw_features(priv);
2761         if (priv->hw_cap_support) {
2762                 pr_info(" DMA HW capability register supported");
2763
2764                 /* We can override some gmac/dma configuration fields: e.g.
2765                  * enh_desc, tx_coe (e.g. that are passed through the
2766                  * platform) with the values from the HW capability
2767                  * register (if supported).
2768                  */
2769                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2770                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2771
2772                 /* TXCOE doesn't work in thresh DMA mode */
2773                 if (priv->plat->force_thresh_dma_mode)
2774                         priv->plat->tx_coe = 0;
2775                 else
2776                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
2777
2778                 if (priv->dma_cap.rx_coe_type2)
2779                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2780                 else if (priv->dma_cap.rx_coe_type1)
2781                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2782
2783         } else
2784                 pr_info(" No HW DMA feature register supported");
2785
2786         /* To use alternate (extended) or normal descriptor structures */
2787         stmmac_selec_desc_mode(priv);
2788
2789         if (priv->plat->rx_coe) {
2790                 priv->hw->rx_csum = priv->plat->rx_coe;
2791                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2792                         priv->plat->rx_coe);
2793         }
2794         if (priv->plat->tx_coe)
2795                 pr_info(" TX Checksum insertion supported\n");
2796
2797         if (priv->plat->pmt) {
2798                 pr_info(" Wake-Up On Lan supported\n");
2799                 device_set_wakeup_capable(priv->device, 1);
2800         }
2801
2802         return 0;
2803 }
2804
2805 /**
2806  * stmmac_dvr_probe
2807  * @device: device pointer
2808  * @plat_dat: platform data pointer
2809  * @res: stmmac resource pointer
2810  * Description: this is the main probe function used to
2811  * call the alloc_etherdev, allocate the priv structure.
2812  * Return:
2813  * returns 0 on success, otherwise errno.
2814  */
2815 int stmmac_dvr_probe(struct device *device,
2816                      struct plat_stmmacenet_data *plat_dat,
2817                      struct stmmac_resources *res)
2818 {
2819         int ret = 0;
2820         struct net_device *ndev = NULL;
2821         struct stmmac_priv *priv;
2822
2823         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2824         if (!ndev)
2825                 return -ENOMEM;
2826
2827         SET_NETDEV_DEV(ndev, device);
2828
2829         priv = netdev_priv(ndev);
2830         priv->device = device;
2831         priv->dev = ndev;
2832
2833         stmmac_set_ethtool_ops(ndev);
2834         priv->pause = pause;
2835         priv->plat = plat_dat;
2836         priv->ioaddr = res->addr;
2837         priv->dev->base_addr = (unsigned long)res->addr;
2838
2839         priv->dev->irq = res->irq;
2840         priv->wol_irq = res->wol_irq;
2841         priv->lpi_irq = res->lpi_irq;
2842
2843         if (res->mac)
2844                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2845
2846         dev_set_drvdata(device, priv->dev);
2847
2848         /* Verify driver arguments */
2849         stmmac_verify_args();
2850
2851         /* Override with kernel parameters if supplied XXX CRS XXX
2852          * this needs to have multiple instances
2853          */
2854         if ((phyaddr >= 0) && (phyaddr <= 31))
2855                 priv->plat->phy_addr = phyaddr;
2856
2857         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2858         if (IS_ERR(priv->stmmac_clk)) {
2859                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2860                          __func__);
2861                 /* If failed to obtain stmmac_clk and specific clk_csr value
2862                  * is NOT passed from the platform, probe fail.
2863                  */
2864                 if (!priv->plat->clk_csr) {
2865                         ret = PTR_ERR(priv->stmmac_clk);
2866                         goto error_clk_get;
2867                 } else {
2868                         priv->stmmac_clk = NULL;
2869                 }
2870         }
2871         clk_prepare_enable(priv->stmmac_clk);
2872
2873         priv->pclk = devm_clk_get(priv->device, "pclk");
2874         if (IS_ERR(priv->pclk)) {
2875                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2876                         ret = -EPROBE_DEFER;
2877                         goto error_pclk_get;
2878                 }
2879                 priv->pclk = NULL;
2880         }
2881         clk_prepare_enable(priv->pclk);
2882
2883         priv->stmmac_rst = devm_reset_control_get(priv->device,
2884                                                   STMMAC_RESOURCE_NAME);
2885         if (IS_ERR(priv->stmmac_rst)) {
2886                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2887                         ret = -EPROBE_DEFER;
2888                         goto error_hw_init;
2889                 }
2890                 dev_info(priv->device, "no reset control found\n");
2891                 priv->stmmac_rst = NULL;
2892         }
2893         if (priv->stmmac_rst)
2894                 reset_control_deassert(priv->stmmac_rst);
2895
2896         /* Init MAC and get the capabilities */
2897         ret = stmmac_hw_init(priv);
2898         if (ret)
2899                 goto error_hw_init;
2900
2901         ndev->netdev_ops = &stmmac_netdev_ops;
2902
2903         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2904                             NETIF_F_RXCSUM;
2905         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2906         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2907 #ifdef STMMAC_VLAN_TAG_USED
2908         /* Both mac100 and gmac support receive VLAN tag detection */
2909         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2910 #endif
2911         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2912
2913         if (flow_ctrl)
2914                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2915
2916         /* Rx Watchdog is available in the COREs newer than the 3.40.
2917          * In some case, for example on bugged HW this feature
2918          * has to be disable and this can be done by passing the
2919          * riwt_off field from the platform.
2920          */
2921         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2922                 priv->use_riwt = 1;
2923                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2924         }
2925
2926         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2927
2928         spin_lock_init(&priv->lock);
2929         spin_lock_init(&priv->tx_lock);
2930
2931         ret = register_netdev(ndev);
2932         if (ret) {
2933                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2934                 goto error_netdev_register;
2935         }
2936
2937         /* If a specific clk_csr value is passed from the platform
2938          * this means that the CSR Clock Range selection cannot be
2939          * changed at run-time and it is fixed. Viceversa the driver'll try to
2940          * set the MDC clock dynamically according to the csr actual
2941          * clock input.
2942          */
2943         if (!priv->plat->clk_csr)
2944                 stmmac_clk_csr_set(priv);
2945         else
2946                 priv->clk_csr = priv->plat->clk_csr;
2947
2948         stmmac_check_pcs_mode(priv);
2949
2950         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2951             priv->pcs != STMMAC_PCS_RTBI) {
2952                 /* MDIO bus Registration */
2953                 ret = stmmac_mdio_register(ndev);
2954                 if (ret < 0) {
2955                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2956                                  __func__, priv->plat->bus_id);
2957                         goto error_mdio_register;
2958                 }
2959         }
2960
2961         return 0;
2962
2963 error_mdio_register:
2964         unregister_netdev(ndev);
2965 error_netdev_register:
2966         netif_napi_del(&priv->napi);
2967 error_hw_init:
2968         clk_disable_unprepare(priv->pclk);
2969 error_pclk_get:
2970         clk_disable_unprepare(priv->stmmac_clk);
2971 error_clk_get:
2972         free_netdev(ndev);
2973
2974         return ret;
2975 }
2976 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2977
2978 /**
2979  * stmmac_dvr_remove
2980  * @ndev: net device pointer
2981  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2982  * changes the link status, releases the DMA descriptor rings.
2983  */
2984 int stmmac_dvr_remove(struct net_device *ndev)
2985 {
2986         struct stmmac_priv *priv = netdev_priv(ndev);
2987
2988         pr_info("%s:\n\tremoving driver", __func__);
2989
2990         priv->hw->dma->stop_rx(priv->ioaddr);
2991         priv->hw->dma->stop_tx(priv->ioaddr);
2992
2993         stmmac_set_mac(priv->ioaddr, false);
2994         netif_carrier_off(ndev);
2995         unregister_netdev(ndev);
2996         if (priv->stmmac_rst)
2997                 reset_control_assert(priv->stmmac_rst);
2998         clk_disable_unprepare(priv->pclk);
2999         clk_disable_unprepare(priv->stmmac_clk);
3000         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3001             priv->pcs != STMMAC_PCS_RTBI)
3002                 stmmac_mdio_unregister(ndev);
3003         free_netdev(ndev);
3004
3005         return 0;
3006 }
3007 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3008
3009 /**
3010  * stmmac_suspend - suspend callback
3011  * @ndev: net device pointer
3012  * Description: this is the function to suspend the device and it is called
3013  * by the platform driver to stop the network queue, release the resources,
3014  * program the PMT register (for WoL), clean and release driver resources.
3015  */
3016 int stmmac_suspend(struct net_device *ndev)
3017 {
3018         struct stmmac_priv *priv = netdev_priv(ndev);
3019         unsigned long flags;
3020
3021         if (!ndev || !netif_running(ndev))
3022                 return 0;
3023
3024         if (priv->phydev)
3025                 phy_stop(priv->phydev);
3026
3027         spin_lock_irqsave(&priv->lock, flags);
3028
3029         netif_device_detach(ndev);
3030         netif_stop_queue(ndev);
3031
3032         napi_disable(&priv->napi);
3033
3034         /* Stop TX/RX DMA */
3035         priv->hw->dma->stop_tx(priv->ioaddr);
3036         priv->hw->dma->stop_rx(priv->ioaddr);
3037
3038         stmmac_clear_descriptors(priv);
3039
3040         /* Enable Power down mode by programming the PMT regs */
3041         if (device_may_wakeup(priv->device)) {
3042                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3043                 priv->irq_wake = 1;
3044         } else {
3045                 stmmac_set_mac(priv->ioaddr, false);
3046                 pinctrl_pm_select_sleep_state(priv->device);
3047                 /* Disable clock in case of PWM is off */
3048                 clk_disable(priv->pclk);
3049                 clk_disable(priv->stmmac_clk);
3050         }
3051         spin_unlock_irqrestore(&priv->lock, flags);
3052
3053         priv->oldlink = 0;
3054         priv->speed = 0;
3055         priv->oldduplex = -1;
3056         return 0;
3057 }
3058 EXPORT_SYMBOL_GPL(stmmac_suspend);
3059
3060 /**
3061  * stmmac_resume - resume callback
3062  * @ndev: net device pointer
3063  * Description: when resume this function is invoked to setup the DMA and CORE
3064  * in a usable state.
3065  */
3066 int stmmac_resume(struct net_device *ndev)
3067 {
3068         struct stmmac_priv *priv = netdev_priv(ndev);
3069         unsigned long flags;
3070
3071         if (!netif_running(ndev))
3072                 return 0;
3073
3074         spin_lock_irqsave(&priv->lock, flags);
3075
3076         /* Power Down bit, into the PM register, is cleared
3077          * automatically as soon as a magic packet or a Wake-up frame
3078          * is received. Anyway, it's better to manually clear
3079          * this bit because it can generate problems while resuming
3080          * from another devices (e.g. serial console).
3081          */
3082         if (device_may_wakeup(priv->device)) {
3083                 priv->hw->mac->pmt(priv->hw, 0);
3084                 priv->irq_wake = 0;
3085         } else {
3086                 pinctrl_pm_select_default_state(priv->device);
3087                 /* enable the clk prevously disabled */
3088                 clk_enable(priv->stmmac_clk);
3089                 clk_enable(priv->pclk);
3090                 /* reset the phy so that it's ready */
3091                 if (priv->mii)
3092                         stmmac_mdio_reset(priv->mii);
3093         }
3094
3095         netif_device_attach(ndev);
3096
3097         init_dma_desc_rings(ndev, GFP_ATOMIC);
3098         stmmac_hw_setup(ndev, false);
3099         stmmac_init_tx_coalesce(priv);
3100
3101         napi_enable(&priv->napi);
3102
3103         netif_start_queue(ndev);
3104
3105         spin_unlock_irqrestore(&priv->lock, flags);
3106
3107         if (priv->phydev)
3108                 phy_start(priv->phydev);
3109
3110         return 0;
3111 }
3112 EXPORT_SYMBOL_GPL(stmmac_resume);
3113
3114 #ifndef MODULE
3115 static int __init stmmac_cmdline_opt(char *str)
3116 {
3117         char *opt;
3118
3119         if (!str || !*str)
3120                 return -EINVAL;
3121         while ((opt = strsep(&str, ",")) != NULL) {
3122                 if (!strncmp(opt, "debug:", 6)) {
3123                         if (kstrtoint(opt + 6, 0, &debug))
3124                                 goto err;
3125                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3126                         if (kstrtoint(opt + 8, 0, &phyaddr))
3127                                 goto err;
3128                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3129                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3130                                 goto err;
3131                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3132                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3133                                 goto err;
3134                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3135                         if (kstrtoint(opt + 7, 0, &buf_sz))
3136                                 goto err;
3137                 } else if (!strncmp(opt, "tc:", 3)) {
3138                         if (kstrtoint(opt + 3, 0, &tc))
3139                                 goto err;
3140                 } else if (!strncmp(opt, "watchdog:", 9)) {
3141                         if (kstrtoint(opt + 9, 0, &watchdog))
3142                                 goto err;
3143                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3144                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3145                                 goto err;
3146                 } else if (!strncmp(opt, "pause:", 6)) {
3147                         if (kstrtoint(opt + 6, 0, &pause))
3148                                 goto err;
3149                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3150                         if (kstrtoint(opt + 10, 0, &eee_timer))
3151                                 goto err;
3152                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3153                         if (kstrtoint(opt + 11, 0, &chain_mode))
3154                                 goto err;
3155                 }
3156         }
3157         return 0;
3158
3159 err:
3160         pr_err("%s: ERROR broken module parameter conversion", __func__);
3161         return -EINVAL;
3162 }
3163
3164 __setup("stmmaceth=", stmmac_cmdline_opt);
3165 #endif /* MODULE */
3166
3167 static int __init stmmac_init(void)
3168 {
3169 #ifdef CONFIG_DEBUG_FS
3170         /* Create debugfs main directory if it doesn't exist yet */
3171         if (!stmmac_fs_dir) {
3172                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3173
3174                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3175                         pr_err("ERROR %s, debugfs create directory failed\n",
3176                                STMMAC_RESOURCE_NAME);
3177
3178                         return -ENOMEM;
3179                 }
3180         }
3181 #endif
3182
3183         return 0;
3184 }
3185
3186 static void __exit stmmac_exit(void)
3187 {
3188 #ifdef CONFIG_DEBUG_FS
3189         debugfs_remove_recursive(stmmac_fs_dir);
3190 #endif
3191 }
3192
3193 module_init(stmmac_init)
3194 module_exit(stmmac_exit)
3195
3196 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3197 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3198 MODULE_LICENSE("GPL");