drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_STMMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif
  50 #include <linux/net_tstamp.h>
  51 #include "stmmac_ptp.h"
  52 #include "stmmac.h"
  53
  54 #undef STMMAC_DEBUG
  55 /*#define STMMAC_DEBUG*/
  56 #ifdef STMMAC_DEBUG
  57 #define DBG(nlevel, klevel, fmt, args...) \
  58                 ((void)(netif_msg_##nlevel(priv) && \
  59                 printk(KERN_##klevel fmt, ## args)))
  60 #else
  61 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  62 #endif
  63
  64 #undef STMMAC_RX_DEBUG
  65 /*#define STMMAC_RX_DEBUG*/
  66 #ifdef STMMAC_RX_DEBUG
  67 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  68 #else
  69 #define RX_DBG(fmt, args...)  do { } while (0)
  70 #endif
  71
  72 #undef STMMAC_XMIT_DEBUG
  73 /*#define STMMAC_XMIT_DEBUG*/
  74 #ifdef STMMAC_XMIT_DEBUG
  75 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  76 #else
  77 #define TX_DBG(fmt, args...)  do { } while (0)
  78 #endif
  79
  80 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  81 #define JUMBO_LEN       9000
  82
  83 /* Module parameters */
  84 #define TX_TIMEO 5000 /* default 5 seconds */
  85 static int watchdog = TX_TIMEO;
  86 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  87 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  88
  89 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  90 module_param(debug, int, S_IRUGO | S_IWUSR);
  91 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  92
  93 int phyaddr = -1;
  94 module_param(phyaddr, int, S_IRUGO);
  95 MODULE_PARM_DESC(phyaddr, "Physical device address");
  96
  97 #define DMA_TX_SIZE 256
  98 static int dma_txsize = DMA_TX_SIZE;
  99 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 100 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 101
 102 #define DMA_RX_SIZE 256
 103 static int dma_rxsize = DMA_RX_SIZE;
 104 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 106
 107 static int flow_ctrl = FLOW_OFF;
 108 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 109 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 110
 111 static int pause = PAUSE_TIME;
 112 module_param(pause, int, S_IRUGO | S_IWUSR);
 113 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 114
 115 #define TC_DEFAULT 64
 116 static int tc = TC_DEFAULT;
 117 module_param(tc, int, S_IRUGO | S_IWUSR);
 118 MODULE_PARM_DESC(tc, "DMA threshold control value");
 119
 120 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 121 static int buf_sz = DMA_BUFFER_SIZE;
 122 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 123 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 124
 125 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 126                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 127                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 128
 129 #define STMMAC_DEFAULT_LPI_TIMER        1000
 130 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 131 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 132 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 133 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
 134
 135 /* By default the driver will use the ring mode to manage tx and rx descriptors
 136  * but passing this value so user can force to use the chain instead of the ring
 137  */
 138 static unsigned int chain_mode;
 139 module_param(chain_mode, int, S_IRUGO);
 140 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 141
 142 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 143
 144 #ifdef CONFIG_STMMAC_DEBUG_FS
 145 static int stmmac_init_fs(struct net_device *dev);
 146 static void stmmac_exit_fs(void);
 147 #endif
 148
 149 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 150
 151 /**
 152  * stmmac_verify_args - verify the driver parameters.
 153  * Description: it verifies if some wrong parameter is passed to the driver.
 154  * Note that wrong parameters are replaced with the default values.
 155  */
 156 static void stmmac_verify_args(void)
 157 {
 158         if (unlikely(watchdog < 0))
 159                 watchdog = TX_TIMEO;
 160         if (unlikely(dma_rxsize < 0))
 161                 dma_rxsize = DMA_RX_SIZE;
 162         if (unlikely(dma_txsize < 0))
 163                 dma_txsize = DMA_TX_SIZE;
 164         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 165                 buf_sz = DMA_BUFFER_SIZE;
 166         if (unlikely(flow_ctrl > 1))
 167                 flow_ctrl = FLOW_AUTO;
 168         else if (likely(flow_ctrl < 0))
 169                 flow_ctrl = FLOW_OFF;
 170         if (unlikely((pause < 0) || (pause > 0xffff)))
 171                 pause = PAUSE_TIME;
 172         if (eee_timer < 0)
 173                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 174 }
 175
 176 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 177 {
 178         u32 clk_rate;
 179
 180         clk_rate = clk_get_rate(priv->stmmac_clk);
 181
 182         /* Platform provided default clk_csr would be assumed valid
 183          * for all other cases except for the below mentioned ones. */
 184         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 185                 if (clk_rate < CSR_F_35M)
 186                         priv->clk_csr = STMMAC_CSR_20_35M;
 187                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 188                         priv->clk_csr = STMMAC_CSR_35_60M;
 189                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 190                         priv->clk_csr = STMMAC_CSR_60_100M;
 191                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 192                         priv->clk_csr = STMMAC_CSR_100_150M;
 193                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 194                         priv->clk_csr = STMMAC_CSR_150_250M;
 195                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 196                         priv->clk_csr = STMMAC_CSR_250_300M;
 197         } /* For values higher than the IEEE 802.3 specified frequency
 198            * we can not estimate the proper divider as it is not known
 199            * the frequency of clk_csr_i. So we do not change the default
 200            * divider. */
 201 }
 202
 203 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 204 static void print_pkt(unsigned char *buf, int len)
 205 {
 206         int j;
 207         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 208         for (j = 0; j < len; j++) {
 209                 if ((j % 16) == 0)
 210                         pr_info("\n %03x:", j);
 211                 pr_info(" %02x", buf[j]);
 212         }
 213         pr_info("\n");
 214 }
 215 #endif
 216
 217 /* minimum number of free TX descriptors required to wake up TX process */
 218 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 219
 220 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 221 {
 222         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 223 }
 224
 225 /* On some ST platforms, some HW system configuraton registers have to be
 226  * set according to the link speed negotiated.
 227  */
 228 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 229 {
 230         struct phy_device *phydev = priv->phydev;
 231
 232         if (likely(priv->plat->fix_mac_speed))
 233                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
 234                                           phydev->speed);
 235 }
 236
 237 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 238 {
 239         /* Check and enter in LPI mode */
 240         if ((priv->dirty_tx == priv->cur_tx) &&
 241             (priv->tx_path_in_lpi_mode == false))
 242                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 243 }
 244
 245 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 246 {
 247         /* Exit and disable EEE in case of we are are in LPI state. */
 248         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 249         del_timer_sync(&priv->eee_ctrl_timer);
 250         priv->tx_path_in_lpi_mode = false;
 251 }
 252
 253 /**
 254  * stmmac_eee_ctrl_timer
 255  * @arg : data hook
 256  * Description:
 257  *  If there is no data transfer and if we are not in LPI state,
 258  *  then MAC Transmitter can be moved to LPI state.
 259  */
 260 static void stmmac_eee_ctrl_timer(unsigned long arg)
 261 {
 262         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 263
 264         stmmac_enable_eee_mode(priv);
 265         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 266 }
 267
 268 /**
 269  * stmmac_eee_init
 270  * @priv: private device pointer
 271  * Description:
 272  *  If the EEE support has been enabled while configuring the driver,
 273  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 274  *  phy can also manage EEE, so enable the LPI state and start the timer
 275  *  to verify if the tx path can enter in LPI state.
 276  */
 277 bool stmmac_eee_init(struct stmmac_priv *priv)
 278 {
 279         bool ret = false;
 280
 281         /* MAC core supports the EEE feature. */
 282         if (priv->dma_cap.eee) {
 283                 /* Check if the PHY supports EEE */
 284                 if (phy_init_eee(priv->phydev, 1))
 285                         goto out;
 286
 287                 priv->eee_active = 1;
 288                 init_timer(&priv->eee_ctrl_timer);
 289                 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 290                 priv->eee_ctrl_timer.data = (unsigned long)priv;
 291                 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
 292                 add_timer(&priv->eee_ctrl_timer);
 293
 294                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 295                                              STMMAC_DEFAULT_LIT_LS_TIMER,
 296                                              priv->tx_lpi_timer);
 297
 298                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 299
 300                 ret = true;
 301         }
 302 out:
 303         return ret;
 304 }
 305
 306 static void stmmac_eee_adjust(struct stmmac_priv *priv)
 307 {
 308         /* When the EEE has been already initialised we have to
 309          * modify the PLS bit in the LPI ctrl & status reg according
 310          * to the PHY link status. For this reason.
 311          */
 312         if (priv->eee_enabled)
 313                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 314 }
 315
 316 /* stmmac_get_tx_hwtstamp:
 317  * @priv : pointer to private device structure.
 318  * @entry : descriptor index to be used.
 319  * @skb : the socket buffer
 320  * Description :
 321  * This function will read timestamp from the descriptor & pass it to stack.
 322  * and also perform some sanity checks.
 323  */
 324 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 325                                    unsigned int entry,
 326                                    struct sk_buff *skb)
 327 {
 328         struct skb_shared_hwtstamps shhwtstamp;
 329         u64 ns;
 330         void *desc = NULL;
 331
 332         if (!priv->hwts_tx_en)
 333                 return;
 334
 335         /* if skb doesn't support hw tstamp */
 336         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 337                 return;
 338
 339         if (priv->adv_ts)
 340                 desc = (priv->dma_etx + entry);
 341         else
 342                 desc = (priv->dma_tx + entry);
 343
 344         /* check tx tstamp status */
 345         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 346                 return;
 347
 348         /* get the valid tstamp */
 349         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 350
 351         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 352         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 353         /* pass tstamp to stack */
 354         skb_tstamp_tx(skb, &shhwtstamp);
 355
 356         return;
 357 }
 358
 359 /* stmmac_get_rx_hwtstamp:
 360  * @priv : pointer to private device structure.
 361  * @entry : descriptor index to be used.
 362  * @skb : the socket buffer
 363  * Description :
 364  * This function will read received packet's timestamp from the descriptor
 365  * and pass it to stack. It also perform some sanity checks.
 366  */
 367 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 368                                    unsigned int entry,
 369                                    struct sk_buff *skb)
 370 {
 371         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 372         u64 ns;
 373         void *desc = NULL;
 374
 375         if (!priv->hwts_rx_en)
 376                 return;
 377
 378         if (priv->adv_ts)
 379                 desc = (priv->dma_erx + entry);
 380         else
 381                 desc = (priv->dma_rx + entry);
 382
 383         /* if rx tstamp is not valid */
 384         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 385                 return;
 386
 387         /* get valid tstamp */
 388         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 389         shhwtstamp = skb_hwtstamps(skb);
 390         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 391         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 392 }
 393
 394 /**
 395  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 396  *  @dev: device pointer.
 397  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 398  *  a proprietary structure used to pass information to the driver.
 399  *  Description:
 400  *  This function configures the MAC to enable/disable both outgoing(TX)
 401  *  and incoming(RX) packets time stamping based on user input.
 402  *  Return Value:
 403  *  0 on success and an appropriate -ve integer on failure.
 404  */
 405 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 406 {
 407         struct stmmac_priv *priv = netdev_priv(dev);
 408         struct hwtstamp_config config;
 409         struct timespec now;
 410         u64 temp = 0;
 411         u32 ptp_v2 = 0;
 412         u32 tstamp_all = 0;
 413         u32 ptp_over_ipv4_udp = 0;
 414         u32 ptp_over_ipv6_udp = 0;
 415         u32 ptp_over_ethernet = 0;
 416         u32 snap_type_sel = 0;
 417         u32 ts_master_en = 0;
 418         u32 ts_event_en = 0;
 419         u32 value = 0;
 420
 421         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 422                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 423                 priv->hwts_tx_en = 0;
 424                 priv->hwts_rx_en = 0;
 425
 426                 return -EOPNOTSUPP;
 427         }
 428
 429         if (copy_from_user(&config, ifr->ifr_data,
 430                 sizeof(struct hwtstamp_config)))
 431                 return -EFAULT;
 432
 433         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 434                  __func__, config.flags, config.tx_type, config.rx_filter);
 435
 436         /* reserved for future extensions */
 437         if (config.flags)
 438                 return -EINVAL;
 439
 440         switch (config.tx_type) {
 441         case HWTSTAMP_TX_OFF:
 442                 priv->hwts_tx_en = 0;
 443                 break;
 444         case HWTSTAMP_TX_ON:
 445                 priv->hwts_tx_en = 1;
 446                 break;
 447         default:
 448                 return -ERANGE;
 449         }
 450
 451         if (priv->adv_ts) {
 452                 switch (config.rx_filter) {
 453                 /* time stamp no incoming packet at all */
 454                 case HWTSTAMP_FILTER_NONE:
 455                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 456                         break;
 457
 458                 /* PTP v1, UDP, any kind of event packet */
 459                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 460                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 461                         /* take time stamp for all event messages */
 462                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 463
 464                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 465                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 466                         break;
 467
 468                 /* PTP v1, UDP, Sync packet */
 469                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 470                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 471                         /* take time stamp for SYNC messages only */
 472                         ts_event_en = PTP_TCR_TSEVNTENA;
 473
 474                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 475                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 476                         break;
 477
 478                 /* PTP v1, UDP, Delay_req packet */
 479                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 480                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 481                         /* take time stamp for Delay_Req messages only */
 482                         ts_master_en = PTP_TCR_TSMSTRENA;
 483                         ts_event_en = PTP_TCR_TSEVNTENA;
 484
 485                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 486                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 487                         break;
 488
 489                 /* PTP v2, UDP, any kind of event packet */
 490                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 491                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 492                         ptp_v2 = PTP_TCR_TSVER2ENA;
 493                         /* take time stamp for all event messages */
 494                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 495
 496                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 497                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 498                         break;
 499
 500                 /* PTP v2, UDP, Sync packet */
 501                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 502                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 503                         ptp_v2 = PTP_TCR_TSVER2ENA;
 504                         /* take time stamp for SYNC messages only */
 505                         ts_event_en = PTP_TCR_TSEVNTENA;
 506
 507                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 508                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 509                         break;
 510
 511                 /* PTP v2, UDP, Delay_req packet */
 512                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 513                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 514                         ptp_v2 = PTP_TCR_TSVER2ENA;
 515                         /* take time stamp for Delay_Req messages only */
 516                         ts_master_en = PTP_TCR_TSMSTRENA;
 517                         ts_event_en = PTP_TCR_TSEVNTENA;
 518
 519                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 520                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 521                         break;
 522
 523                 /* PTP v2/802.AS1, any layer, any kind of event packet */
 524                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 525                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 526                         ptp_v2 = PTP_TCR_TSVER2ENA;
 527                         /* take time stamp for all event messages */
 528                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 529
 530                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 531                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 532                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 533                         break;
 534
 535                 /* PTP v2/802.AS1, any layer, Sync packet */
 536                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 537                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 538                         ptp_v2 = PTP_TCR_TSVER2ENA;
 539                         /* take time stamp for SYNC messages only */
 540                         ts_event_en = PTP_TCR_TSEVNTENA;
 541
 542                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 543                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 544                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 545                         break;
 546
 547                 /* PTP v2/802.AS1, any layer, Delay_req packet */
 548                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 549                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 550                         ptp_v2 = PTP_TCR_TSVER2ENA;
 551                         /* take time stamp for Delay_Req messages only */
 552                         ts_master_en = PTP_TCR_TSMSTRENA;
 553                         ts_event_en = PTP_TCR_TSEVNTENA;
 554
 555                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 556                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 557                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 558                         break;
 559
 560                 /* time stamp any incoming packet */
 561                 case HWTSTAMP_FILTER_ALL:
 562                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 563                         tstamp_all = PTP_TCR_TSENALL;
 564                         break;
 565
 566                 default:
 567                         return -ERANGE;
 568                 }
 569         } else {
 570                 switch (config.rx_filter) {
 571                 case HWTSTAMP_FILTER_NONE:
 572                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 573                         break;
 574                 default:
 575                         /* PTP v1, UDP, any kind of event packet */
 576                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 577                         break;
 578                 }
 579         }
 580         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 581
 582         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 583                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 584         else {
 585                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 586                         tstamp_all | ptp_v2 | ptp_over_ethernet |
 587                         ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 588                         ts_master_en | snap_type_sel);
 589
 590                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 591
 592                 /* program Sub Second Increment reg */
 593                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 594
 595                 /* calculate default added value:
 596                  * formula is :
 597                  * addend = (2^32)/freq_div_ratio;
 598                  * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
 599                  * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
 600                  * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
 601                  *       achive 20ns accuracy.
 602                  *
 603                  * 2^x * y == (y << x), hence
 604                  * 2^32 * 50000000 ==> (50000000 << 32)
 605                  */
 606                 temp = (u64)(50000000ULL << 32);
 607                 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
 608                 priv->hw->ptp->config_addend(priv->ioaddr,
 609                                              priv->default_addend);
 610
 611                 /* initialize system time */
 612                 getnstimeofday(&now);
 613                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 614                                             now.tv_nsec);
 615         }
 616
 617         return copy_to_user(ifr->ifr_data, &config,
 618                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 619 }
 620
 621 static int stmmac_init_ptp(struct stmmac_priv *priv)
 622 {
 623         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 624                 return -EOPNOTSUPP;
 625
 626         if (netif_msg_hw(priv)) {
 627                 if (priv->dma_cap.time_stamp) {
 628                         pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 629                         priv->adv_ts = 0;
 630                 }
 631                 if (priv->dma_cap.atime_stamp && priv->extend_desc) {
 632                         pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 633                         priv->adv_ts = 1;
 634                 }
 635         }
 636
 637         priv->hw->ptp = &stmmac_ptp;
 638         priv->hwts_tx_en = 0;
 639         priv->hwts_rx_en = 0;
 640
 641         return stmmac_ptp_register(priv);
 642 }
 643
 644 static void stmmac_release_ptp(struct stmmac_priv *priv)
 645 {
 646         stmmac_ptp_unregister(priv);
 647 }
 648
 649 /**
 650  * stmmac_adjust_link
 651  * @dev: net device structure
 652  * Description: it adjusts the link parameters.
 653  */
 654 static void stmmac_adjust_link(struct net_device *dev)
 655 {
 656         struct stmmac_priv *priv = netdev_priv(dev);
 657         struct phy_device *phydev = priv->phydev;
 658         unsigned long flags;
 659         int new_state = 0;
 660         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 661
 662         if (phydev == NULL)
 663                 return;
 664
 665         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 666             phydev->addr, phydev->link);
 667
 668         spin_lock_irqsave(&priv->lock, flags);
 669
 670         if (phydev->link) {
 671                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 672
 673                 /* Now we make sure that we can be in full duplex mode.
 674                  * If not, we operate in half-duplex mode. */
 675                 if (phydev->duplex != priv->oldduplex) {
 676                         new_state = 1;
 677                         if (!(phydev->duplex))
 678                                 ctrl &= ~priv->hw->link.duplex;
 679                         else
 680                                 ctrl |= priv->hw->link.duplex;
 681                         priv->oldduplex = phydev->duplex;
 682                 }
 683                 /* Flow Control operation */
 684                 if (phydev->pause)
 685                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 686                                                  fc, pause_time);
 687
 688                 if (phydev->speed != priv->speed) {
 689                         new_state = 1;
 690                         switch (phydev->speed) {
 691                         case 1000:
 692                                 if (likely(priv->plat->has_gmac))
 693                                         ctrl &= ~priv->hw->link.port;
 694                                         stmmac_hw_fix_mac_speed(priv);
 695                                 break;
 696                         case 100:
 697                         case 10:
 698                                 if (priv->plat->has_gmac) {
 699                                         ctrl |= priv->hw->link.port;
 700                                         if (phydev->speed == SPEED_100) {
 701                                                 ctrl |= priv->hw->link.speed;
 702                                         } else {
 703                                                 ctrl &= ~(priv->hw->link.speed);
 704                                         }
 705                                 } else {
 706                                         ctrl &= ~priv->hw->link.port;
 707                                 }
 708                                 stmmac_hw_fix_mac_speed(priv);
 709                                 break;
 710                         default:
 711                                 if (netif_msg_link(priv))
 712                                         pr_warning("%s: Speed (%d) is not 10"
 713                                        " or 100!\n", dev->name, phydev->speed);
 714                                 break;
 715                         }
 716
 717                         priv->speed = phydev->speed;
 718                 }
 719
 720                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 721
 722                 if (!priv->oldlink) {
 723                         new_state = 1;
 724                         priv->oldlink = 1;
 725                 }
 726         } else if (priv->oldlink) {
 727                 new_state = 1;
 728                 priv->oldlink = 0;
 729                 priv->speed = 0;
 730                 priv->oldduplex = -1;
 731         }
 732
 733         if (new_state && netif_msg_link(priv))
 734                 phy_print_status(phydev);
 735
 736         stmmac_eee_adjust(priv);
 737
 738         spin_unlock_irqrestore(&priv->lock, flags);
 739
 740         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 741 }
 742
 743 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 744 {
 745         int interface = priv->plat->interface;
 746
 747         if (priv->dma_cap.pcs) {
 748                 if ((interface & PHY_INTERFACE_MODE_RGMII) ||
 749                     (interface & PHY_INTERFACE_MODE_RGMII_ID) ||
 750                     (interface & PHY_INTERFACE_MODE_RGMII_RXID) ||
 751                     (interface & PHY_INTERFACE_MODE_RGMII_TXID)) {
 752                         pr_debug("STMMAC: PCS RGMII support enable\n");
 753                         priv->pcs = STMMAC_PCS_RGMII;
 754                 } else if (interface & PHY_INTERFACE_MODE_SGMII) {
 755                         pr_debug("STMMAC: PCS SGMII support enable\n");
 756                         priv->pcs = STMMAC_PCS_SGMII;
 757                 }
 758         }
 759 }
 760
 761 /**
 762  * stmmac_init_phy - PHY initialization
 763  * @dev: net device structure
 764  * Description: it initializes the driver's PHY state, and attaches the PHY
 765  * to the mac driver.
 766  *  Return value:
 767  *  0 on success
 768  */
 769 static int stmmac_init_phy(struct net_device *dev)
 770 {
 771         struct stmmac_priv *priv = netdev_priv(dev);
 772         struct phy_device *phydev;
 773         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 774         char bus_id[MII_BUS_ID_SIZE];
 775         int interface = priv->plat->interface;
 776         priv->oldlink = 0;
 777         priv->speed = 0;
 778         priv->oldduplex = -1;
 779
 780         if (priv->plat->phy_bus_name)
 781                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 782                                 priv->plat->phy_bus_name, priv->plat->bus_id);
 783         else
 784                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 785                                 priv->plat->bus_id);
 786
 787         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 788                  priv->plat->phy_addr);
 789         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 790
 791         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 792
 793         if (IS_ERR(phydev)) {
 794                 pr_err("%s: Could not attach to PHY\n", dev->name);
 795                 return PTR_ERR(phydev);
 796         }
 797
 798         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 799         if ((interface == PHY_INTERFACE_MODE_MII) ||
 800             (interface == PHY_INTERFACE_MODE_RMII))
 801                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 802                                          SUPPORTED_1000baseT_Full);
 803
 804         /*
 805          * Broken HW is sometimes missing the pull-up resistor on the
 806          * MDIO line, which results in reads to non-existent devices returning
 807          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 808          * device as well.
 809          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 810          */
 811         if (phydev->phy_id == 0) {
 812                 phy_disconnect(phydev);
 813                 return -ENODEV;
 814         }
 815         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 816                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 817
 818         priv->phydev = phydev;
 819
 820         return 0;
 821 }
 822
 823 /**
 824  * stmmac_display_ring
 825  * @p: pointer to the ring.
 826  * @size: size of the ring.
 827  * Description: display the control/status and buffer descriptors.
 828  */
 829 static void stmmac_display_ring(void *head, int size, int extend_desc)
 830 {
 831         int i;
 832         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
 833         struct dma_desc *p = (struct dma_desc *) head;
 834
 835         for (i = 0; i < size; i++) {
 836                 u64 x;
 837                 if (extend_desc) {
 838                         x = *(u64 *) ep;
 839                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 840                                 i, (unsigned int) virt_to_phys(ep),
 841                                 (unsigned int) x, (unsigned int) (x >> 32),
 842                                 ep->basic.des2, ep->basic.des3);
 843                         ep++;
 844                 } else {
 845                         x = *(u64 *) p;
 846                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 847                                 i, (unsigned int) virt_to_phys(p),
 848                                 (unsigned int) x, (unsigned int) (x >> 32),
 849                                 p->des2, p->des3);
 850                         p++;
 851                 }
 852                 pr_info("\n");
 853         }
 854 }
 855
 856 static void stmmac_display_rings(struct stmmac_priv *priv)
 857 {
 858         unsigned int txsize = priv->dma_tx_size;
 859         unsigned int rxsize = priv->dma_rx_size;
 860
 861         if (priv->extend_desc) {
 862                 pr_info("Extended RX descriptor ring:\n");
 863                 stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
 864                 pr_info("Extended TX descriptor ring:\n");
 865                 stmmac_display_ring((void *) priv->dma_etx, txsize, 1);
 866         } else {
 867                 pr_info("RX descriptor ring:\n");
 868                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 869                 pr_info("TX descriptor ring:\n");
 870                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 871         }
 872 }
 873
 874 static int stmmac_set_bfsize(int mtu, int bufsize)
 875 {
 876         int ret = bufsize;
 877
 878         if (mtu >= BUF_SIZE_4KiB)
 879                 ret = BUF_SIZE_8KiB;
 880         else if (mtu >= BUF_SIZE_2KiB)
 881                 ret = BUF_SIZE_4KiB;
 882         else if (mtu >= DMA_BUFFER_SIZE)
 883                 ret = BUF_SIZE_2KiB;
 884         else
 885                 ret = DMA_BUFFER_SIZE;
 886
 887         return ret;
 888 }
 889
 890 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 891 {
 892         int i;
 893         unsigned int txsize = priv->dma_tx_size;
 894         unsigned int rxsize = priv->dma_rx_size;
 895
 896         /* Clear the Rx/Tx descriptors */
 897         for (i = 0; i < rxsize; i++)
 898                 if (priv->extend_desc)
 899                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 900                                                      priv->use_riwt, priv->mode,
 901                                                      (i == rxsize - 1));
 902                 else
 903                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 904                                                      priv->use_riwt, priv->mode,
 905                                                      (i == rxsize - 1));
 906         for (i = 0; i < txsize; i++)
 907                 if (priv->extend_desc)
 908                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 909                                                      priv->mode,
 910                                                      (i == txsize - 1));
 911                 else
 912                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 913                                                      priv->mode,
 914                                                      (i == txsize - 1));
 915 }
 916
 917 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 918                                   int i)
 919 {
 920         struct sk_buff *skb;
 921
 922         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 923                                  GFP_KERNEL);
 924         if (unlikely(skb == NULL)) {
 925                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 926                 return 1;
 927         }
 928         skb_reserve(skb, NET_IP_ALIGN);
 929         priv->rx_skbuff[i] = skb;
 930         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 931                                                 priv->dma_buf_sz,
 932                                                 DMA_FROM_DEVICE);
 933
 934         p->des2 = priv->rx_skbuff_dma[i];
 935
 936         if ((priv->mode == STMMAC_RING_MODE) &&
 937             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 938                 priv->hw->ring->init_desc3(p);
 939
 940         return 0;
 941 }
 942
 943 /**
 944  * init_dma_desc_rings - init the RX/TX descriptor rings
 945  * @dev: net device structure
 946  * Description:  this function initializes the DMA RX/TX descriptors
 947  * and allocates the socket buffers. It suppors the chained and ring
 948  * modes.
 949  */
 950 static void init_dma_desc_rings(struct net_device *dev)
 951 {
 952         int i;
 953         struct stmmac_priv *priv = netdev_priv(dev);
 954         unsigned int txsize = priv->dma_tx_size;
 955         unsigned int rxsize = priv->dma_rx_size;
 956         unsigned int bfsize = 0;
 957
 958         /* Set the max buffer size according to the DESC mode
 959          * and the MTU. Note that RING mode allows 16KiB bsize. */
 960         if (priv->mode == STMMAC_RING_MODE)
 961                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 962
 963         if (bfsize < BUF_SIZE_16KiB)
 964                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 965
 966         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 967             txsize, rxsize, bfsize);
 968
 969         if (priv->extend_desc) {
 970                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
 971                                                    sizeof(struct
 972                                                           dma_extended_desc),
 973                                                    &priv->dma_rx_phy,
 974                                                    GFP_KERNEL);
 975                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
 976                                                    sizeof(struct
 977                                                           dma_extended_desc),
 978                                                    &priv->dma_tx_phy,
 979                                                    GFP_KERNEL);
 980                 if ((!priv->dma_erx) || (!priv->dma_etx))
 981                         return;
 982         } else {
 983                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
 984                                                   sizeof(struct dma_desc),
 985                                                   &priv->dma_rx_phy,
 986                                                   GFP_KERNEL);
 987                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
 988                                                   sizeof(struct dma_desc),
 989                                                   &priv->dma_tx_phy,
 990                                                   GFP_KERNEL);
 991                 if ((!priv->dma_rx) || (!priv->dma_tx))
 992                         return;
 993         }
 994
 995         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
 996                                             GFP_KERNEL);
 997         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
 998                                         GFP_KERNEL);
 999         priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1000                                         GFP_KERNEL);
1001         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1002                                         GFP_KERNEL);
1003         if (netif_msg_drv(priv))
1004                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1005                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1006
1007         /* RX INITIALIZATION */
1008         DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
1009         for (i = 0; i < rxsize; i++) {
1010                 struct dma_desc *p;
1011                 if (priv->extend_desc)
1012                         p = &((priv->dma_erx + i)->basic);
1013                 else
1014                         p = priv->dma_rx + i;
1015
1016                 if (stmmac_init_rx_buffers(priv, p, i))
1017                         break;
1018
1019                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1020                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
1021         }
1022         priv->cur_rx = 0;
1023         priv->dirty_rx = (unsigned int)(i - rxsize);
1024         priv->dma_buf_sz = bfsize;
1025         buf_sz = bfsize;
1026
1027         /* Setup the chained descriptor addresses */
1028         if (priv->mode == STMMAC_CHAIN_MODE) {
1029                 if (priv->extend_desc) {
1030                         priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1031                                               rxsize, 1);
1032                         priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1033                                               txsize, 1);
1034                 } else {
1035                         priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1036                                               rxsize, 0);
1037                         priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1038                                               txsize, 0);
1039                 }
1040         }
1041
1042         /* TX INITIALIZATION */
1043         for (i = 0; i < txsize; i++) {
1044                 struct dma_desc *p;
1045                 if (priv->extend_desc)
1046                         p = &((priv->dma_etx + i)->basic);
1047                 else
1048                         p = priv->dma_tx + i;
1049                 p->des2 = 0;
1050                 priv->tx_skbuff_dma[i] = 0;
1051                 priv->tx_skbuff[i] = NULL;
1052         }
1053
1054         priv->dirty_tx = 0;
1055         priv->cur_tx = 0;
1056
1057         stmmac_clear_descriptors(priv);
1058
1059         if (netif_msg_hw(priv))
1060                 stmmac_display_rings(priv);
1061 }
1062
1063 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1064 {
1065         int i;
1066
1067         for (i = 0; i < priv->dma_rx_size; i++) {
1068                 if (priv->rx_skbuff[i]) {
1069                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1070                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1071                         dev_kfree_skb_any(priv->rx_skbuff[i]);
1072                 }
1073                 priv->rx_skbuff[i] = NULL;
1074         }
1075 }
1076
1077 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1078 {
1079         int i;
1080
1081         for (i = 0; i < priv->dma_tx_size; i++) {
1082                 if (priv->tx_skbuff[i] != NULL) {
1083                         struct dma_desc *p;
1084                         if (priv->extend_desc)
1085                                 p = &((priv->dma_etx + i)->basic);
1086                         else
1087                                 p = priv->dma_tx + i;
1088
1089                         if (priv->tx_skbuff_dma[i])
1090                                 dma_unmap_single(priv->device,
1091                                                  priv->tx_skbuff_dma[i],
1092                                                  priv->hw->desc->get_tx_len(p),
1093                                                  DMA_TO_DEVICE);
1094                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1095                         priv->tx_skbuff[i] = NULL;
1096                         priv->tx_skbuff_dma[i] = 0;
1097                 }
1098         }
1099 }
1100
1101 static void free_dma_desc_resources(struct stmmac_priv *priv)
1102 {
1103         /* Release the DMA TX/RX socket buffers */
1104         dma_free_rx_skbufs(priv);
1105         dma_free_tx_skbufs(priv);
1106
1107         /* Free the region of consistent memory previously allocated for
1108          * the DMA */
1109         if (!priv->extend_desc) {
1110                 dma_free_coherent(priv->device,
1111                                   priv->dma_tx_size * sizeof(struct dma_desc),
1112                                   priv->dma_tx, priv->dma_tx_phy);
1113                 dma_free_coherent(priv->device,
1114                                   priv->dma_rx_size * sizeof(struct dma_desc),
1115                                   priv->dma_rx, priv->dma_rx_phy);
1116         } else {
1117                 dma_free_coherent(priv->device, priv->dma_tx_size *
1118                                   sizeof(struct dma_extended_desc),
1119                                   priv->dma_etx, priv->dma_tx_phy);
1120                 dma_free_coherent(priv->device, priv->dma_rx_size *
1121                                   sizeof(struct dma_extended_desc),
1122                                   priv->dma_erx, priv->dma_rx_phy);
1123         }
1124         kfree(priv->rx_skbuff_dma);
1125         kfree(priv->rx_skbuff);
1126         kfree(priv->tx_skbuff_dma);
1127         kfree(priv->tx_skbuff);
1128 }
1129
1130 /**
1131  *  stmmac_dma_operation_mode - HW DMA operation mode
1132  *  @priv : pointer to the private device structure.
1133  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1134  *  or Store-And-Forward capability.
1135  */
1136 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1137 {
1138         if (likely(priv->plat->force_sf_dma_mode ||
1139                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
1140                 /*
1141                  * In case of GMAC, SF mode can be enabled
1142                  * to perform the TX COE in HW. This depends on:
1143                  * 1) TX COE if actually supported
1144                  * 2) There is no bugged Jumbo frame support
1145                  *    that needs to not insert csum in the TDES.
1146                  */
1147                 priv->hw->dma->dma_mode(priv->ioaddr,
1148                                         SF_DMA_MODE, SF_DMA_MODE);
1149                 tc = SF_DMA_MODE;
1150         } else
1151                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1152 }
1153
1154 /**
1155  * stmmac_tx_clean:
1156  * @priv: private data pointer
1157  * Description: it reclaims resources after transmission completes.
1158  */
1159 static void stmmac_tx_clean(struct stmmac_priv *priv)
1160 {
1161         unsigned int txsize = priv->dma_tx_size;
1162
1163         spin_lock(&priv->tx_lock);
1164
1165         priv->xstats.tx_clean++;
1166
1167         while (priv->dirty_tx != priv->cur_tx) {
1168                 int last;
1169                 unsigned int entry = priv->dirty_tx % txsize;
1170                 struct sk_buff *skb = priv->tx_skbuff[entry];
1171                 struct dma_desc *p;
1172
1173                 if (priv->extend_desc)
1174                         p = (struct dma_desc *) (priv->dma_etx + entry);
1175                 else
1176                         p = priv->dma_tx + entry;
1177
1178                 /* Check if the descriptor is owned by the DMA. */
1179                 if (priv->hw->desc->get_tx_owner(p))
1180                         break;
1181
1182                 /* Verify tx error by looking at the last segment. */
1183                 last = priv->hw->desc->get_tx_ls(p);
1184                 if (likely(last)) {
1185                         int tx_error =
1186                                 priv->hw->desc->tx_status(&priv->dev->stats,
1187                                                           &priv->xstats, p,
1188                                                           priv->ioaddr);
1189                         if (likely(tx_error == 0)) {
1190                                 priv->dev->stats.tx_packets++;
1191                                 priv->xstats.tx_pkt_n++;
1192                         } else
1193                                 priv->dev->stats.tx_errors++;
1194
1195                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1196                 }
1197                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
1198                         priv->cur_tx, priv->dirty_tx);
1199
1200                 if (likely(priv->tx_skbuff_dma[entry])) {
1201                         dma_unmap_single(priv->device,
1202                                          priv->tx_skbuff_dma[entry],
1203                                          priv->hw->desc->get_tx_len(p),
1204                                          DMA_TO_DEVICE);
1205                         priv->tx_skbuff_dma[entry] = 0;
1206                 }
1207                 priv->hw->ring->clean_desc3(priv, p);
1208
1209                 if (likely(skb != NULL)) {
1210                         dev_kfree_skb(skb);
1211                         priv->tx_skbuff[entry] = NULL;
1212                 }
1213
1214                 priv->hw->desc->release_tx_desc(p, priv->mode);
1215
1216                 priv->dirty_tx++;
1217         }
1218         if (unlikely(netif_queue_stopped(priv->dev) &&
1219                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1220                 netif_tx_lock(priv->dev);
1221                 if (netif_queue_stopped(priv->dev) &&
1222                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1223                         TX_DBG("%s: restart transmit\n", __func__);
1224                         netif_wake_queue(priv->dev);
1225                 }
1226                 netif_tx_unlock(priv->dev);
1227         }
1228
1229         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1230                 stmmac_enable_eee_mode(priv);
1231                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
1232         }
1233         spin_unlock(&priv->tx_lock);
1234 }
1235
1236 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1237 {
1238         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1239 }
1240
1241 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1242 {
1243         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1244 }
1245
1246
1247 /**
1248  * stmmac_tx_err:
1249  * @priv: pointer to the private device structure
1250  * Description: it cleans the descriptors and restarts the transmission
1251  * in case of errors.
1252  */
1253 static void stmmac_tx_err(struct stmmac_priv *priv)
1254 {
1255         int i;
1256         int txsize = priv->dma_tx_size;
1257         netif_stop_queue(priv->dev);
1258
1259         priv->hw->dma->stop_tx(priv->ioaddr);
1260         dma_free_tx_skbufs(priv);
1261         for (i = 0; i < txsize; i++)
1262                 if (priv->extend_desc)
1263                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1264                                                      priv->mode,
1265                                                      (i == txsize - 1));
1266                 else
1267                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1268                                                      priv->mode,
1269                                                      (i == txsize - 1));
1270         priv->dirty_tx = 0;
1271         priv->cur_tx = 0;
1272         priv->hw->dma->start_tx(priv->ioaddr);
1273
1274         priv->dev->stats.tx_errors++;
1275         netif_wake_queue(priv->dev);
1276 }
1277
1278 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1279 {
1280         int status;
1281
1282         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1283         if (likely((status & handle_rx)) || (status & handle_tx)) {
1284                 if (likely(napi_schedule_prep(&priv->napi))) {
1285                         stmmac_disable_dma_irq(priv);
1286                         __napi_schedule(&priv->napi);
1287                 }
1288         }
1289         if (unlikely(status & tx_hard_error_bump_tc)) {
1290                 /* Try to bump up the dma threshold on this failure */
1291                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1292                         tc += 64;
1293                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1294                         priv->xstats.threshold = tc;
1295                 }
1296         } else if (unlikely(status == tx_hard_error))
1297                 stmmac_tx_err(priv);
1298 }
1299
1300 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1301 {
1302         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1303                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1304
1305         /* Mask MMC irq, counters are managed in SW and registers
1306          * are cleared on each READ eventually. */
1307         dwmac_mmc_intr_all_mask(priv->ioaddr);
1308
1309         if (priv->dma_cap.rmon) {
1310                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1311                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1312         } else
1313                 pr_info(" No MAC Management Counters available\n");
1314 }
1315
1316 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1317 {
1318         u32 hwid = priv->hw->synopsys_uid;
1319
1320         /* Only check valid Synopsys Id because old MAC chips
1321          * have no HW registers where get the ID */
1322         if (likely(hwid)) {
1323                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1324                 u32 synid = (hwid & 0x000000ff);
1325
1326                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1327                         uid, synid);
1328
1329                 return synid;
1330         }
1331         return 0;
1332 }
1333
1334 /**
1335  * stmmac_selec_desc_mode
1336  * @priv : private structure
1337  * Description: select the Enhanced/Alternate or Normal descriptors
1338  */
1339 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1340 {
1341         if (priv->plat->enh_desc) {
1342                 pr_info(" Enhanced/Alternate descriptors\n");
1343
1344                 /* GMAC older than 3.50 has no extended descriptors */
1345                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1346                         pr_info("\tEnabled extended descriptors\n");
1347                         priv->extend_desc = 1;
1348                 } else
1349                         pr_warn("Extended descriptors not supported\n");
1350
1351                 priv->hw->desc = &enh_desc_ops;
1352         } else {
1353                 pr_info(" Normal descriptors\n");
1354                 priv->hw->desc = &ndesc_ops;
1355         }
1356 }
1357
1358 /**
1359  * stmmac_get_hw_features
1360  * @priv : private device pointer
1361  * Description:
1362  *  new GMAC chip generations have a new register to indicate the
1363  *  presence of the optional feature/functions.
1364  *  This can be also used to override the value passed through the
1365  *  platform and necessary for old MAC10/100 and GMAC chips.
1366  */
1367 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1368 {
1369         u32 hw_cap = 0;
1370
1371         if (priv->hw->dma->get_hw_feature) {
1372                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1373
1374                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1375                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1376                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1377                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1378                 priv->dma_cap.multi_addr =
1379                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
1380                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1381                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1382                 priv->dma_cap.pmt_remote_wake_up =
1383                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1384                 priv->dma_cap.pmt_magic_frame =
1385                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1386                 /* MMC */
1387                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1388                 /* IEEE 1588-2002*/
1389                 priv->dma_cap.time_stamp =
1390                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1391                 /* IEEE 1588-2008*/
1392                 priv->dma_cap.atime_stamp =
1393                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1394                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1395                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1396                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1397                 /* TX and RX csum */
1398                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1399                 priv->dma_cap.rx_coe_type1 =
1400                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1401                 priv->dma_cap.rx_coe_type2 =
1402                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1403                 priv->dma_cap.rxfifo_over_2048 =
1404                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1405                 /* TX and RX number of channels */
1406                 priv->dma_cap.number_rx_channel =
1407                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1408                 priv->dma_cap.number_tx_channel =
1409                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1410                 /* Alternate (enhanced) DESC mode*/
1411                 priv->dma_cap.enh_desc =
1412                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1413         }
1414
1415         return hw_cap;
1416 }
1417
1418 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1419 {
1420         /* verify if the MAC address is valid, in case of failures it
1421          * generates a random MAC address */
1422         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1423                 priv->hw->mac->get_umac_addr((void __iomem *)
1424                                              priv->dev->base_addr,
1425                                              priv->dev->dev_addr, 0);
1426                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
1427                         eth_hw_addr_random(priv->dev);
1428         }
1429         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
1430                                                    priv->dev->dev_addr);
1431 }
1432
1433 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1434 {
1435         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1436         int mixed_burst = 0;
1437         int atds = 0;
1438
1439         /* Some DMA parameters can be passed from the platform;
1440          * in case of these are not passed we keep a default
1441          * (good for all the chips) and init the DMA! */
1442         if (priv->plat->dma_cfg) {
1443                 pbl = priv->plat->dma_cfg->pbl;
1444                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1445                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1446                 burst_len = priv->plat->dma_cfg->burst_len;
1447         }
1448
1449         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1450                 atds = 1;
1451
1452         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1453                                    burst_len, priv->dma_tx_phy,
1454                                    priv->dma_rx_phy, atds);
1455 }
1456
1457 /**
1458  * stmmac_tx_timer:
1459  * @data: data pointer
1460  * Description:
1461  * This is the timer handler to directly invoke the stmmac_tx_clean.
1462  */
1463 static void stmmac_tx_timer(unsigned long data)
1464 {
1465         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1466
1467         stmmac_tx_clean(priv);
1468 }
1469
1470 /**
1471  * stmmac_tx_timer:
1472  * @priv: private data structure
1473  * Description:
1474  * This inits the transmit coalesce parameters: i.e. timer rate,
1475  * timer handler and default threshold used for enabling the
1476  * interrupt on completion bit.
1477  */
1478 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1479 {
1480         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1481         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1482         init_timer(&priv->txtimer);
1483         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1484         priv->txtimer.data = (unsigned long)priv;
1485         priv->txtimer.function = stmmac_tx_timer;
1486         add_timer(&priv->txtimer);
1487 }
1488
1489 /**
1490  *  stmmac_open - open entry point of the driver
1491  *  @dev : pointer to the device structure.
1492  *  Description:
1493  *  This function is the open entry point of the driver.
1494  *  Return value:
1495  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1496  *  file on failure.
1497  */
1498 static int stmmac_open(struct net_device *dev)
1499 {
1500         struct stmmac_priv *priv = netdev_priv(dev);
1501         int ret;
1502
1503         clk_prepare_enable(priv->stmmac_clk);
1504
1505         stmmac_check_ether_addr(priv);
1506
1507         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1508             priv->pcs != STMMAC_PCS_RTBI) {
1509                 ret = stmmac_init_phy(dev);
1510                 if (ret) {
1511                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1512                                __func__, ret);
1513                         goto open_error;
1514                 }
1515         }
1516
1517         /* Create and initialize the TX/RX descriptors chains. */
1518         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1519         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1520         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1521         init_dma_desc_rings(dev);
1522
1523         /* DMA initialization and SW reset */
1524         ret = stmmac_init_dma_engine(priv);
1525         if (ret < 0) {
1526                 pr_err("%s: DMA initialization failed\n", __func__);
1527                 goto open_error;
1528         }
1529
1530         /* Copy the MAC addr into the HW  */
1531         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1532
1533         /* If required, perform hw setup of the bus. */
1534         if (priv->plat->bus_setup)
1535                 priv->plat->bus_setup(priv->ioaddr);
1536
1537         /* Initialize the MAC Core */
1538         priv->hw->mac->core_init(priv->ioaddr);
1539
1540         /* Request the IRQ lines */
1541         ret = request_irq(dev->irq, stmmac_interrupt,
1542                          IRQF_SHARED, dev->name, dev);
1543         if (unlikely(ret < 0)) {
1544                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1545                        __func__, dev->irq, ret);
1546                 goto open_error;
1547         }
1548
1549         /* Request the Wake IRQ in case of another line is used for WoL */
1550         if (priv->wol_irq != dev->irq) {
1551                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1552                                   IRQF_SHARED, dev->name, dev);
1553                 if (unlikely(ret < 0)) {
1554                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1555                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1556                         goto open_error_wolirq;
1557                 }
1558         }
1559
1560         /* Request the IRQ lines */
1561         if (priv->lpi_irq != -ENXIO) {
1562                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1563                                   dev->name, dev);
1564                 if (unlikely(ret < 0)) {
1565                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1566                                __func__, priv->lpi_irq, ret);
1567                         goto open_error_lpiirq;
1568                 }
1569         }
1570
1571         /* Enable the MAC Rx/Tx */
1572         stmmac_set_mac(priv->ioaddr, true);
1573
1574         /* Set the HW DMA mode and the COE */
1575         stmmac_dma_operation_mode(priv);
1576
1577         /* Extra statistics */
1578         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1579         priv->xstats.threshold = tc;
1580
1581         stmmac_mmc_setup(priv);
1582
1583         ret = stmmac_init_ptp(priv);
1584         if (ret)
1585                 pr_warn("%s: failed PTP initialisation\n", __func__);
1586
1587 #ifdef CONFIG_STMMAC_DEBUG_FS
1588         ret = stmmac_init_fs(dev);
1589         if (ret < 0)
1590                 pr_warning("%s: failed debugFS registration\n", __func__);
1591 #endif
1592         /* Start the ball rolling... */
1593         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1594         priv->hw->dma->start_tx(priv->ioaddr);
1595         priv->hw->dma->start_rx(priv->ioaddr);
1596
1597         /* Dump DMA/MAC registers */
1598         if (netif_msg_hw(priv)) {
1599                 priv->hw->mac->dump_regs(priv->ioaddr);
1600                 priv->hw->dma->dump_regs(priv->ioaddr);
1601         }
1602
1603         if (priv->phydev)
1604                 phy_start(priv->phydev);
1605
1606         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1607
1608         /* Using PCS we cannot dial with the phy registers at this stage
1609          * so we do not support extra feature like EEE.
1610          */
1611         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1612             priv->pcs != STMMAC_PCS_RTBI)
1613                 priv->eee_enabled = stmmac_eee_init(priv);
1614
1615         stmmac_init_tx_coalesce(priv);
1616
1617         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1618                 priv->rx_riwt = MAX_DMA_RIWT;
1619                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1620         }
1621
1622         if (priv->pcs && priv->hw->mac->ctrl_ane)
1623                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1624
1625         napi_enable(&priv->napi);
1626         netif_start_queue(dev);
1627
1628         return 0;
1629
1630 open_error_lpiirq:
1631         if (priv->wol_irq != dev->irq)
1632                 free_irq(priv->wol_irq, dev);
1633
1634 open_error_wolirq:
1635         free_irq(dev->irq, dev);
1636
1637 open_error:
1638         if (priv->phydev)
1639                 phy_disconnect(priv->phydev);
1640
1641         clk_disable_unprepare(priv->stmmac_clk);
1642
1643         return ret;
1644 }
1645
1646 /**
1647  *  stmmac_release - close entry point of the driver
1648  *  @dev : device pointer.
1649  *  Description:
1650  *  This is the stop entry point of the driver.
1651  */
1652 static int stmmac_release(struct net_device *dev)
1653 {
1654         struct stmmac_priv *priv = netdev_priv(dev);
1655
1656         if (priv->eee_enabled)
1657                 del_timer_sync(&priv->eee_ctrl_timer);
1658
1659         /* Stop and disconnect the PHY */
1660         if (priv->phydev) {
1661                 phy_stop(priv->phydev);
1662                 phy_disconnect(priv->phydev);
1663                 priv->phydev = NULL;
1664         }
1665
1666         netif_stop_queue(dev);
1667
1668         napi_disable(&priv->napi);
1669
1670         del_timer_sync(&priv->txtimer);
1671
1672         /* Free the IRQ lines */
1673         free_irq(dev->irq, dev);
1674         if (priv->wol_irq != dev->irq)
1675                 free_irq(priv->wol_irq, dev);
1676         if (priv->lpi_irq != -ENXIO)
1677                 free_irq(priv->lpi_irq, dev);
1678
1679         /* Stop TX/RX DMA and clear the descriptors */
1680         priv->hw->dma->stop_tx(priv->ioaddr);
1681         priv->hw->dma->stop_rx(priv->ioaddr);
1682
1683         /* Release and free the Rx/Tx resources */
1684         free_dma_desc_resources(priv);
1685
1686         /* Disable the MAC Rx/Tx */
1687         stmmac_set_mac(priv->ioaddr, false);
1688
1689         netif_carrier_off(dev);
1690
1691 #ifdef CONFIG_STMMAC_DEBUG_FS
1692         stmmac_exit_fs();
1693 #endif
1694         clk_disable_unprepare(priv->stmmac_clk);
1695
1696         stmmac_release_ptp(priv);
1697
1698         return 0;
1699 }
1700
1701 /**
1702  *  stmmac_xmit:
1703  *  @skb : the socket buffer
1704  *  @dev : device pointer
1705  *  Description : Tx entry point of the driver.
1706  */
1707 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1708 {
1709         struct stmmac_priv *priv = netdev_priv(dev);
1710         unsigned int txsize = priv->dma_tx_size;
1711         unsigned int entry;
1712         int i, csum_insertion = 0, is_jumbo = 0;
1713         int nfrags = skb_shinfo(skb)->nr_frags;
1714         struct dma_desc *desc, *first;
1715         unsigned int nopaged_len = skb_headlen(skb);
1716
1717         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1718                 if (!netif_queue_stopped(dev)) {
1719                         netif_stop_queue(dev);
1720                         /* This is a hard error, log it. */
1721                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1722                                 __func__);
1723                 }
1724                 return NETDEV_TX_BUSY;
1725         }
1726
1727         spin_lock(&priv->tx_lock);
1728
1729         if (priv->tx_path_in_lpi_mode)
1730                 stmmac_disable_eee_mode(priv);
1731
1732         entry = priv->cur_tx % txsize;
1733
1734 #ifdef STMMAC_XMIT_DEBUG
1735         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1736                 pr_debug("stmmac xmit: [entry %d]\n"
1737                          "\tskb addr %p - len: %d - nopaged_len: %d\n"
1738                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1739                          "\ttx_count_frames %d\n", entry,
1740                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1741                          !skb_is_gso(skb) ? "isn't" : "is",
1742                          priv->tx_count_frames);
1743 #endif
1744
1745         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1746
1747         if (priv->extend_desc)
1748                 desc = (struct dma_desc *) (priv->dma_etx + entry);
1749         else
1750                 desc = priv->dma_tx + entry;
1751
1752         first = desc;
1753
1754 #ifdef STMMAC_XMIT_DEBUG
1755         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1756                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1757                          "\t\tn_frags: %d, ip_summed: %d\n",
1758                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1759 #endif
1760         priv->tx_skbuff[entry] = skb;
1761
1762         /* To program the descriptors according to the size of the frame */
1763         if (priv->mode == STMMAC_RING_MODE) {
1764                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1765                                                         priv->plat->enh_desc);
1766                 if (unlikely(is_jumbo))
1767                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1768                                                           csum_insertion);
1769         } else {
1770                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1771                                                         priv->plat->enh_desc);
1772                 if (unlikely(is_jumbo))
1773                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1774                                                            csum_insertion);
1775         }
1776         if (likely(!is_jumbo)) {
1777                 desc->des2 = dma_map_single(priv->device, skb->data,
1778                                         nopaged_len, DMA_TO_DEVICE);
1779                 priv->tx_skbuff_dma[entry] = desc->des2;
1780                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1781                                                 csum_insertion, priv->mode);
1782         } else
1783                 desc = first;
1784
1785         for (i = 0; i < nfrags; i++) {
1786                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1787                 int len = skb_frag_size(frag);
1788
1789                 entry = (++priv->cur_tx) % txsize;
1790                 if (priv->extend_desc)
1791                         desc = (struct dma_desc *) (priv->dma_etx + entry);
1792                 else
1793                         desc = priv->dma_tx + entry;
1794
1795                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1796                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1797                                               DMA_TO_DEVICE);
1798                 priv->tx_skbuff_dma[entry] = desc->des2;
1799                 priv->tx_skbuff[entry] = NULL;
1800                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1801                                                 priv->mode);
1802                 wmb();
1803                 priv->hw->desc->set_tx_owner(desc);
1804                 wmb();
1805         }
1806
1807         /* Finalize the latest segment. */
1808         priv->hw->desc->close_tx_desc(desc);
1809
1810         wmb();
1811         /* According to the coalesce parameter the IC bit for the latest
1812          * segment could be reset and the timer re-started to invoke the
1813          * stmmac_tx function. This approach takes care about the fragments.
1814          */
1815         priv->tx_count_frames += nfrags + 1;
1816         if (priv->tx_coal_frames > priv->tx_count_frames) {
1817                 priv->hw->desc->clear_tx_ic(desc);
1818                 priv->xstats.tx_reset_ic_bit++;
1819                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1820                        priv->tx_count_frames);
1821                 mod_timer(&priv->txtimer,
1822                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1823         } else
1824                 priv->tx_count_frames = 0;
1825
1826         /* To avoid raise condition */
1827         priv->hw->desc->set_tx_owner(first);
1828         wmb();
1829
1830         priv->cur_tx++;
1831
1832 #ifdef STMMAC_XMIT_DEBUG
1833         if (netif_msg_pktdata(priv)) {
1834                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1835                        "first=%p, nfrags=%d\n",
1836                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1837                        entry, first, nfrags);
1838                 if (priv->extend_desc)
1839                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1840                 else
1841                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1842
1843                 pr_info(">>> frame to be transmitted: ");
1844                 print_pkt(skb->data, skb->len);
1845         }
1846 #endif
1847         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1848                 TX_DBG("%s: stop transmitted packets\n", __func__);
1849                 netif_stop_queue(dev);
1850         }
1851
1852         dev->stats.tx_bytes += skb->len;
1853
1854         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1855                      priv->hwts_tx_en)) {
1856                 /* declare that device is doing timestamping */
1857                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1858                 priv->hw->desc->enable_tx_timestamp(first);
1859         }
1860
1861         if (!priv->hwts_tx_en)
1862                 skb_tx_timestamp(skb);
1863
1864         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1865
1866         spin_unlock(&priv->tx_lock);
1867
1868         return NETDEV_TX_OK;
1869 }
1870
1871 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1872 {
1873         unsigned int rxsize = priv->dma_rx_size;
1874         int bfsize = priv->dma_buf_sz;
1875
1876         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1877                 unsigned int entry = priv->dirty_rx % rxsize;
1878                 struct dma_desc *p;
1879
1880                 if (priv->extend_desc)
1881                         p = (struct dma_desc *) (priv->dma_erx + entry);
1882                 else
1883                         p = priv->dma_rx + entry;
1884
1885                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1886                         struct sk_buff *skb;
1887
1888                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1889
1890                         if (unlikely(skb == NULL))
1891                                 break;
1892
1893                         priv->rx_skbuff[entry] = skb;
1894                         priv->rx_skbuff_dma[entry] =
1895                             dma_map_single(priv->device, skb->data, bfsize,
1896                                            DMA_FROM_DEVICE);
1897
1898                         p->des2 = priv->rx_skbuff_dma[entry];
1899
1900                         priv->hw->ring->refill_desc3(priv, p);
1901
1902                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1903                 }
1904                 wmb();
1905                 priv->hw->desc->set_rx_owner(p);
1906                 wmb();
1907         }
1908 }
1909
1910 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1911 {
1912         unsigned int rxsize = priv->dma_rx_size;
1913         unsigned int entry = priv->cur_rx % rxsize;
1914         unsigned int next_entry;
1915         unsigned int count = 0;
1916
1917 #ifdef STMMAC_RX_DEBUG
1918         if (netif_msg_hw(priv)) {
1919                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1920                 if (priv->extend_desc)
1921                         stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
1922                 else
1923                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
1924         }
1925 #endif
1926         while (count < limit) {
1927                 int status;
1928                 struct dma_desc *p, *p_next;
1929
1930                 if (priv->extend_desc)
1931                         p = (struct dma_desc *) (priv->dma_erx + entry);
1932                 else
1933                         p = priv->dma_rx + entry ;
1934
1935                 if (priv->hw->desc->get_rx_owner(p))
1936                         break;
1937
1938                 count++;
1939
1940                 next_entry = (++priv->cur_rx) % rxsize;
1941                 if (priv->extend_desc)
1942                         p_next = (struct dma_desc *) (priv->dma_erx +
1943                                                       next_entry);
1944                 else
1945                         p_next = priv->dma_rx + next_entry;
1946
1947                 prefetch(p_next);
1948
1949                 /* read the status of the incoming frame */
1950                 status = priv->hw->desc->rx_status(&priv->dev->stats,
1951                                                    &priv->xstats, p);
1952                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
1953                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
1954                                                            &priv->xstats,
1955                                                            priv->dma_erx +
1956                                                            entry);
1957                 if (unlikely(status == discard_frame)) {
1958                         priv->dev->stats.rx_errors++;
1959                         if (priv->hwts_rx_en && !priv->extend_desc) {
1960                                 /* DESC2 & DESC3 will be overwitten by device
1961                                  * with timestamp value, hence reinitialize
1962                                  * them in stmmac_rx_refill() function so that
1963                                  * device can reuse it.
1964                                  */
1965                                 priv->rx_skbuff[entry] = NULL;
1966                                 dma_unmap_single(priv->device,
1967                                         priv->rx_skbuff_dma[entry],
1968                                         priv->dma_buf_sz, DMA_FROM_DEVICE);
1969                         }
1970                 } else {
1971                         struct sk_buff *skb;
1972                         int frame_len;
1973
1974                         frame_len = priv->hw->desc->get_rx_frame_len(p,
1975                                         priv->plat->rx_coe);
1976                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1977                          * Type frames (LLC/LLC-SNAP) */
1978                         if (unlikely(status != llc_snap))
1979                                 frame_len -= ETH_FCS_LEN;
1980 #ifdef STMMAC_RX_DEBUG
1981                         if (frame_len > ETH_FRAME_LEN)
1982                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1983                                         frame_len, status);
1984
1985                         if (netif_msg_hw(priv))
1986                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1987                                         p, entry, p->des2);
1988 #endif
1989                         skb = priv->rx_skbuff[entry];
1990                         if (unlikely(!skb)) {
1991                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1992                                         priv->dev->name);
1993                                 priv->dev->stats.rx_dropped++;
1994                                 break;
1995                         }
1996                         prefetch(skb->data - NET_IP_ALIGN);
1997                         priv->rx_skbuff[entry] = NULL;
1998
1999                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2000
2001                         skb_put(skb, frame_len);
2002                         dma_unmap_single(priv->device,
2003                                          priv->rx_skbuff_dma[entry],
2004                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2005 #ifdef STMMAC_RX_DEBUG
2006                         if (netif_msg_pktdata(priv)) {
2007                                 pr_info(" frame received (%dbytes)", frame_len);
2008                                 print_pkt(skb->data, frame_len);
2009                         }
2010 #endif
2011                         skb->protocol = eth_type_trans(skb, priv->dev);
2012
2013                         if (unlikely(!priv->plat->rx_coe))
2014                                 skb_checksum_none_assert(skb);
2015                         else
2016                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2017
2018                         napi_gro_receive(&priv->napi, skb);
2019
2020                         priv->dev->stats.rx_packets++;
2021                         priv->dev->stats.rx_bytes += frame_len;
2022                 }
2023                 entry = next_entry;
2024         }
2025
2026         stmmac_rx_refill(priv);
2027
2028         priv->xstats.rx_pkt_n += count;
2029
2030         return count;
2031 }
2032
2033 /**
2034  *  stmmac_poll - stmmac poll method (NAPI)
2035  *  @napi : pointer to the napi structure.
2036  *  @budget : maximum number of packets that the current CPU can receive from
2037  *            all interfaces.
2038  *  Description :
2039  *  To look at the incoming frames and clear the tx resources.
2040  */
2041 static int stmmac_poll(struct napi_struct *napi, int budget)
2042 {
2043         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2044         int work_done = 0;
2045
2046         priv->xstats.napi_poll++;
2047         stmmac_tx_clean(priv);
2048
2049         work_done = stmmac_rx(priv, budget);
2050         if (work_done < budget) {
2051                 napi_complete(napi);
2052                 stmmac_enable_dma_irq(priv);
2053         }
2054         return work_done;
2055 }
2056
2057 /**
2058  *  stmmac_tx_timeout
2059  *  @dev : Pointer to net device structure
2060  *  Description: this function is called when a packet transmission fails to
2061  *   complete within a reasonable time. The driver will mark the error in the
2062  *   netdev structure and arrange for the device to be reset to a sane state
2063  *   in order to transmit a new packet.
2064  */
2065 static void stmmac_tx_timeout(struct net_device *dev)
2066 {
2067         struct stmmac_priv *priv = netdev_priv(dev);
2068
2069         /* Clear Tx resources and restart transmitting again */
2070         stmmac_tx_err(priv);
2071 }
2072
2073 /* Configuration changes (passed on by ifconfig) */
2074 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2075 {
2076         if (dev->flags & IFF_UP)        /* can't act on a running interface */
2077                 return -EBUSY;
2078
2079         /* Don't allow changing the I/O address */
2080         if (map->base_addr != dev->base_addr) {
2081                 pr_warning("%s: can't change I/O address\n", dev->name);
2082                 return -EOPNOTSUPP;
2083         }
2084
2085         /* Don't allow changing the IRQ */
2086         if (map->irq != dev->irq) {
2087                 pr_warning("%s: can't change IRQ number %d\n",
2088                        dev->name, dev->irq);
2089                 return -EOPNOTSUPP;
2090         }
2091
2092         /* ignore other fields */
2093         return 0;
2094 }
2095
2096 /**
2097  *  stmmac_set_rx_mode - entry point for multicast addressing
2098  *  @dev : pointer to the device structure
2099  *  Description:
2100  *  This function is a driver entry point which gets called by the kernel
2101  *  whenever multicast addresses must be enabled/disabled.
2102  *  Return value:
2103  *  void.
2104  */
2105 static void stmmac_set_rx_mode(struct net_device *dev)
2106 {
2107         struct stmmac_priv *priv = netdev_priv(dev);
2108
2109         spin_lock(&priv->lock);
2110         priv->hw->mac->set_filter(dev, priv->synopsys_id);
2111         spin_unlock(&priv->lock);
2112 }
2113
2114 /**
2115  *  stmmac_change_mtu - entry point to change MTU size for the device.
2116  *  @dev : device pointer.
2117  *  @new_mtu : the new MTU size for the device.
2118  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2119  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2120  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2121  *  Return value:
2122  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2123  *  file on failure.
2124  */
2125 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2126 {
2127         struct stmmac_priv *priv = netdev_priv(dev);
2128         int max_mtu;
2129
2130         if (netif_running(dev)) {
2131                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2132                 return -EBUSY;
2133         }
2134
2135         if (priv->plat->enh_desc)
2136                 max_mtu = JUMBO_LEN;
2137         else
2138                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2139
2140         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2141                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2142                 return -EINVAL;
2143         }
2144
2145         dev->mtu = new_mtu;
2146         netdev_update_features(dev);
2147
2148         return 0;
2149 }
2150
2151 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2152         netdev_features_t features)
2153 {
2154         struct stmmac_priv *priv = netdev_priv(dev);
2155
2156         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2157                 features &= ~NETIF_F_RXCSUM;
2158         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2159                 features &= ~NETIF_F_IPV6_CSUM;
2160         if (!priv->plat->tx_coe)
2161                 features &= ~NETIF_F_ALL_CSUM;
2162
2163         /* Some GMAC devices have a bugged Jumbo frame support that
2164          * needs to have the Tx COE disabled for oversized frames
2165          * (due to limited buffer sizes). In this case we disable
2166          * the TX csum insertionin the TDES and not use SF. */
2167         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2168                 features &= ~NETIF_F_ALL_CSUM;
2169
2170         return features;
2171 }
2172
2173 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2174 {
2175         struct net_device *dev = (struct net_device *)dev_id;
2176         struct stmmac_priv *priv = netdev_priv(dev);
2177
2178         if (unlikely(!dev)) {
2179                 pr_err("%s: invalid dev pointer\n", __func__);
2180                 return IRQ_NONE;
2181         }
2182
2183         /* To handle GMAC own interrupts */
2184         if (priv->plat->has_gmac) {
2185                 int status = priv->hw->mac->host_irq_status((void __iomem *)
2186                                                             dev->base_addr,
2187                                                             &priv->xstats);
2188                 if (unlikely(status)) {
2189                         /* For LPI we need to save the tx status */
2190                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2191                                 priv->tx_path_in_lpi_mode = true;
2192                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2193                                 priv->tx_path_in_lpi_mode = false;
2194                 }
2195         }
2196
2197         /* To handle DMA interrupts */
2198         stmmac_dma_interrupt(priv);
2199
2200         return IRQ_HANDLED;
2201 }
2202
2203 #ifdef CONFIG_NET_POLL_CONTROLLER
2204 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2205  * to allow network I/O with interrupts disabled. */
2206 static void stmmac_poll_controller(struct net_device *dev)
2207 {
2208         disable_irq(dev->irq);
2209         stmmac_interrupt(dev->irq, dev);
2210         enable_irq(dev->irq);
2211 }
2212 #endif
2213
2214 /**
2215  *  stmmac_ioctl - Entry point for the Ioctl
2216  *  @dev: Device pointer.
2217  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2218  *  a proprietary structure used to pass information to the driver.
2219  *  @cmd: IOCTL command
2220  *  Description:
2221  *  Currently it supports just the phy_mii_ioctl(...) and HW time stamping.
2222  */
2223 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2224 {
2225         struct stmmac_priv *priv = netdev_priv(dev);
2226         int ret = -EOPNOTSUPP;
2227
2228         if (!netif_running(dev))
2229                 return -EINVAL;
2230
2231         switch (cmd) {
2232         case SIOCGMIIPHY:
2233         case SIOCGMIIREG:
2234         case SIOCSMIIREG:
2235                 if (!priv->phydev)
2236                         return -EINVAL;
2237                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2238                 break;
2239         case SIOCSHWTSTAMP:
2240                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2241                 break;
2242         default:
2243                 break;
2244         }
2245
2246         return ret;
2247 }
2248
2249 #ifdef CONFIG_STMMAC_DEBUG_FS
2250 static struct dentry *stmmac_fs_dir;
2251 static struct dentry *stmmac_rings_status;
2252 static struct dentry *stmmac_dma_cap;
2253
2254 static void sysfs_display_ring(void *head, int size, int extend_desc,
2255                                 struct seq_file *seq)
2256 {
2257         int i;
2258         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
2259         struct dma_desc *p = (struct dma_desc *) head;
2260
2261         for (i = 0; i < size; i++) {
2262                 u64 x;
2263                 if (extend_desc) {
2264                         x = *(u64 *) ep;
2265                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2266                                    i, (unsigned int) virt_to_phys(ep),
2267                                    (unsigned int) x, (unsigned int) (x >> 32),
2268                                    ep->basic.des2, ep->basic.des3);
2269                         ep++;
2270                 } else {
2271                         x = *(u64 *) p;
2272                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2273                                    i, (unsigned int) virt_to_phys(ep),
2274                                    (unsigned int) x, (unsigned int) (x >> 32),
2275                                    p->des2, p->des3);
2276                         p++;
2277                 }
2278                 seq_printf(seq, "\n");
2279         }
2280 }
2281
2282 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2283 {
2284         struct net_device *dev = seq->private;
2285         struct stmmac_priv *priv = netdev_priv(dev);
2286         unsigned int txsize = priv->dma_tx_size;
2287         unsigned int rxsize = priv->dma_rx_size;
2288
2289         if (priv->extend_desc) {
2290                 seq_printf(seq, "Extended RX descriptor ring:\n");
2291                 sysfs_display_ring((void *) priv->dma_erx, rxsize, 1, seq);
2292                 seq_printf(seq, "Extended TX descriptor ring:\n");
2293                 sysfs_display_ring((void *) priv->dma_etx, txsize, 1, seq);
2294         } else {
2295                 seq_printf(seq, "RX descriptor ring:\n");
2296                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2297                 seq_printf(seq, "TX descriptor ring:\n");
2298                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2299         }
2300
2301         return 0;
2302 }
2303
2304 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2305 {
2306         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2307 }
2308
2309 static const struct file_operations stmmac_rings_status_fops = {
2310         .owner = THIS_MODULE,
2311         .open = stmmac_sysfs_ring_open,
2312         .read = seq_read,
2313         .llseek = seq_lseek,
2314         .release = single_release,
2315 };
2316
2317 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2318 {
2319         struct net_device *dev = seq->private;
2320         struct stmmac_priv *priv = netdev_priv(dev);
2321
2322         if (!priv->hw_cap_support) {
2323                 seq_printf(seq, "DMA HW features not supported\n");
2324                 return 0;
2325         }
2326
2327         seq_printf(seq, "==============================\n");
2328         seq_printf(seq, "\tDMA HW features\n");
2329         seq_printf(seq, "==============================\n");
2330
2331         seq_printf(seq, "\t10/100 Mbps %s\n",
2332                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2333         seq_printf(seq, "\t1000 Mbps %s\n",
2334                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2335         seq_printf(seq, "\tHalf duple %s\n",
2336                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2337         seq_printf(seq, "\tHash Filter: %s\n",
2338                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2339         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2340                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2341         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2342                    (priv->dma_cap.pcs) ? "Y" : "N");
2343         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2344                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2345         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2346                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2347         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2348                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2349         seq_printf(seq, "\tRMON module: %s\n",
2350                    (priv->dma_cap.rmon) ? "Y" : "N");
2351         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2352                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2353         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2354                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2355         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2356                    (priv->dma_cap.eee) ? "Y" : "N");
2357         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2358         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2359                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2360         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2361                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2362         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2363                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2364         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2365                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2366         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2367                    priv->dma_cap.number_rx_channel);
2368         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2369                    priv->dma_cap.number_tx_channel);
2370         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2371                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2372
2373         return 0;
2374 }
2375
2376 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2377 {
2378         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2379 }
2380
2381 static const struct file_operations stmmac_dma_cap_fops = {
2382         .owner = THIS_MODULE,
2383         .open = stmmac_sysfs_dma_cap_open,
2384         .read = seq_read,
2385         .llseek = seq_lseek,
2386         .release = single_release,
2387 };
2388
2389 static int stmmac_init_fs(struct net_device *dev)
2390 {
2391         /* Create debugfs entries */
2392         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2393
2394         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2395                 pr_err("ERROR %s, debugfs create directory failed\n",
2396                        STMMAC_RESOURCE_NAME);
2397
2398                 return -ENOMEM;
2399         }
2400
2401         /* Entry to report DMA RX/TX rings */
2402         stmmac_rings_status = debugfs_create_file("descriptors_status",
2403                                            S_IRUGO, stmmac_fs_dir, dev,
2404                                            &stmmac_rings_status_fops);
2405
2406         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2407                 pr_info("ERROR creating stmmac ring debugfs file\n");
2408                 debugfs_remove(stmmac_fs_dir);
2409
2410                 return -ENOMEM;
2411         }
2412
2413         /* Entry to report the DMA HW features */
2414         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2415                                              dev, &stmmac_dma_cap_fops);
2416
2417         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2418                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2419                 debugfs_remove(stmmac_rings_status);
2420                 debugfs_remove(stmmac_fs_dir);
2421
2422                 return -ENOMEM;
2423         }
2424
2425         return 0;
2426 }
2427
2428 static void stmmac_exit_fs(void)
2429 {
2430         debugfs_remove(stmmac_rings_status);
2431         debugfs_remove(stmmac_dma_cap);
2432         debugfs_remove(stmmac_fs_dir);
2433 }
2434 #endif /* CONFIG_STMMAC_DEBUG_FS */
2435
2436 static const struct net_device_ops stmmac_netdev_ops = {
2437         .ndo_open = stmmac_open,
2438         .ndo_start_xmit = stmmac_xmit,
2439         .ndo_stop = stmmac_release,
2440         .ndo_change_mtu = stmmac_change_mtu,
2441         .ndo_fix_features = stmmac_fix_features,
2442         .ndo_set_rx_mode = stmmac_set_rx_mode,
2443         .ndo_tx_timeout = stmmac_tx_timeout,
2444         .ndo_do_ioctl = stmmac_ioctl,
2445         .ndo_set_config = stmmac_config,
2446 #ifdef CONFIG_NET_POLL_CONTROLLER
2447         .ndo_poll_controller = stmmac_poll_controller,
2448 #endif
2449         .ndo_set_mac_address = eth_mac_addr,
2450 };
2451
2452 /**
2453  *  stmmac_hw_init - Init the MAC device
2454  *  @priv : pointer to the private device structure.
2455  *  Description: this function detects which MAC device
2456  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2457  *  (if supported) and sets the driver's features (for example
2458  *  to use the ring or chaine mode or support the normal/enh
2459  *  descriptor structure).
2460  */
2461 static int stmmac_hw_init(struct stmmac_priv *priv)
2462 {
2463         int ret;
2464         struct mac_device_info *mac;
2465
2466         /* Identify the MAC HW device */
2467         if (priv->plat->has_gmac) {
2468                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2469                 mac = dwmac1000_setup(priv->ioaddr);
2470         } else {
2471                 mac = dwmac100_setup(priv->ioaddr);
2472         }
2473         if (!mac)
2474                 return -ENOMEM;
2475
2476         priv->hw = mac;
2477
2478         /* Get and dump the chip ID */
2479         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2480
2481         /* To use alternate (extended) or normal descriptor structures */
2482         stmmac_selec_desc_mode(priv);
2483
2484         /* To use the chained or ring mode */
2485         if (chain_mode) {
2486                 priv->hw->chain = &chain_mode_ops;
2487                 pr_info(" Chain mode enabled\n");
2488                 priv->mode = STMMAC_CHAIN_MODE;
2489         } else {
2490                 priv->hw->ring = &ring_mode_ops;
2491                 pr_info(" Ring mode enabled\n");
2492                 priv->mode = STMMAC_RING_MODE;
2493         }
2494
2495         /* Get the HW capability (new GMAC newer than 3.50a) */
2496         priv->hw_cap_support = stmmac_get_hw_features(priv);
2497         if (priv->hw_cap_support) {
2498                 pr_info(" DMA HW capability register supported");
2499
2500                 /* We can override some gmac/dma configuration fields: e.g.
2501                  * enh_desc, tx_coe (e.g. that are passed through the
2502                  * platform) with the values from the HW capability
2503                  * register (if supported).
2504                  */
2505                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2506                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2507
2508                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2509
2510                 if (priv->dma_cap.rx_coe_type2)
2511                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2512                 else if (priv->dma_cap.rx_coe_type1)
2513                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2514
2515         } else
2516                 pr_info(" No HW DMA feature register supported");
2517
2518         /* Enable the IPC (Checksum Offload) and check if the feature has been
2519          * enabled during the core configuration. */
2520         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2521         if (!ret) {
2522                 pr_warning(" RX IPC Checksum Offload not configured.\n");
2523                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2524         }
2525
2526         if (priv->plat->rx_coe)
2527                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2528                         priv->plat->rx_coe);
2529         if (priv->plat->tx_coe)
2530                 pr_info(" TX Checksum insertion supported\n");
2531
2532         if (priv->plat->pmt) {
2533                 pr_info(" Wake-Up On Lan supported\n");
2534                 device_set_wakeup_capable(priv->device, 1);
2535         }
2536
2537         return 0;
2538 }
2539
2540 /**
2541  * stmmac_dvr_probe
2542  * @device: device pointer
2543  * @plat_dat: platform data pointer
2544  * @addr: iobase memory address
2545  * Description: this is the main probe function used to
2546  * call the alloc_etherdev, allocate the priv structure.
2547  */
2548 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2549                                      struct plat_stmmacenet_data *plat_dat,
2550                                      void __iomem *addr)
2551 {
2552         int ret = 0;
2553         struct net_device *ndev = NULL;
2554         struct stmmac_priv *priv;
2555
2556         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2557         if (!ndev)
2558                 return NULL;
2559
2560         SET_NETDEV_DEV(ndev, device);
2561
2562         priv = netdev_priv(ndev);
2563         priv->device = device;
2564         priv->dev = ndev;
2565
2566         ether_setup(ndev);
2567
2568         stmmac_set_ethtool_ops(ndev);
2569         priv->pause = pause;
2570         priv->plat = plat_dat;
2571         priv->ioaddr = addr;
2572         priv->dev->base_addr = (unsigned long)addr;
2573
2574         /* Verify driver arguments */
2575         stmmac_verify_args();
2576
2577         /* Override with kernel parameters if supplied XXX CRS XXX
2578          * this needs to have multiple instances */
2579         if ((phyaddr >= 0) && (phyaddr <= 31))
2580                 priv->plat->phy_addr = phyaddr;
2581
2582         /* Init MAC and get the capabilities */
2583         ret = stmmac_hw_init(priv);
2584         if (ret)
2585                 goto error_free_netdev;
2586
2587         ndev->netdev_ops = &stmmac_netdev_ops;
2588
2589         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2590                             NETIF_F_RXCSUM;
2591         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2592         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2593 #ifdef STMMAC_VLAN_TAG_USED
2594         /* Both mac100 and gmac support receive VLAN tag detection */
2595         ndev->features |= NETIF_F_HW_VLAN_RX;
2596 #endif
2597         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2598
2599         if (flow_ctrl)
2600                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2601
2602         /* Rx Watchdog is available in the COREs newer than the 3.40.
2603          * In some case, for example on bugged HW this feature
2604          * has to be disable and this can be done by passing the
2605          * riwt_off field from the platform.
2606          */
2607         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2608                 priv->use_riwt = 1;
2609                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2610         }
2611
2612         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2613
2614         spin_lock_init(&priv->lock);
2615         spin_lock_init(&priv->tx_lock);
2616
2617         ret = register_netdev(ndev);
2618         if (ret) {
2619                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2620                 goto error_netdev_register;
2621         }
2622
2623         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2624         if (IS_ERR(priv->stmmac_clk)) {
2625                 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2626                 goto error_clk_get;
2627         }
2628
2629         /* If a specific clk_csr value is passed from the platform
2630          * this means that the CSR Clock Range selection cannot be
2631          * changed at run-time and it is fixed. Viceversa the driver'll try to
2632          * set the MDC clock dynamically according to the csr actual
2633          * clock input.
2634          */
2635         if (!priv->plat->clk_csr)
2636                 stmmac_clk_csr_set(priv);
2637         else
2638                 priv->clk_csr = priv->plat->clk_csr;
2639
2640         stmmac_check_pcs_mode(priv);
2641
2642         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2643             priv->pcs != STMMAC_PCS_RTBI) {
2644                 /* MDIO bus Registration */
2645                 ret = stmmac_mdio_register(ndev);
2646                 if (ret < 0) {
2647                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2648                                  __func__, priv->plat->bus_id);
2649                         goto error_mdio_register;
2650                 }
2651         }
2652
2653         return priv;
2654
2655 error_mdio_register:
2656         clk_put(priv->stmmac_clk);
2657 error_clk_get:
2658         unregister_netdev(ndev);
2659 error_netdev_register:
2660         netif_napi_del(&priv->napi);
2661 error_free_netdev:
2662         free_netdev(ndev);
2663
2664         return NULL;
2665 }
2666
2667 /**
2668  * stmmac_dvr_remove
2669  * @ndev: net device pointer
2670  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2671  * changes the link status, releases the DMA descriptor rings.
2672  */
2673 int stmmac_dvr_remove(struct net_device *ndev)
2674 {
2675         struct stmmac_priv *priv = netdev_priv(ndev);
2676
2677         pr_info("%s:\n\tremoving driver", __func__);
2678
2679         priv->hw->dma->stop_rx(priv->ioaddr);
2680         priv->hw->dma->stop_tx(priv->ioaddr);
2681
2682         stmmac_set_mac(priv->ioaddr, false);
2683         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2684             priv->pcs != STMMAC_PCS_RTBI)
2685                 stmmac_mdio_unregister(ndev);
2686         netif_carrier_off(ndev);
2687         unregister_netdev(ndev);
2688         free_netdev(ndev);
2689
2690         return 0;
2691 }
2692
2693 #ifdef CONFIG_PM
2694 int stmmac_suspend(struct net_device *ndev)
2695 {
2696         struct stmmac_priv *priv = netdev_priv(ndev);
2697         unsigned long flags;
2698
2699         if (!ndev || !netif_running(ndev))
2700                 return 0;
2701
2702         if (priv->phydev)
2703                 phy_stop(priv->phydev);
2704
2705         spin_lock_irqsave(&priv->lock, flags);
2706
2707         netif_device_detach(ndev);
2708         netif_stop_queue(ndev);
2709
2710         napi_disable(&priv->napi);
2711
2712         /* Stop TX/RX DMA */
2713         priv->hw->dma->stop_tx(priv->ioaddr);
2714         priv->hw->dma->stop_rx(priv->ioaddr);
2715
2716         stmmac_clear_descriptors(priv);
2717
2718         /* Enable Power down mode by programming the PMT regs */
2719         if (device_may_wakeup(priv->device))
2720                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2721         else {
2722                 stmmac_set_mac(priv->ioaddr, false);
2723                 /* Disable clock in case of PWM is off */
2724                 clk_disable_unprepare(priv->stmmac_clk);
2725         }
2726         spin_unlock_irqrestore(&priv->lock, flags);
2727         return 0;
2728 }
2729
2730 int stmmac_resume(struct net_device *ndev)
2731 {
2732         struct stmmac_priv *priv = netdev_priv(ndev);
2733         unsigned long flags;
2734
2735         if (!netif_running(ndev))
2736                 return 0;
2737
2738         spin_lock_irqsave(&priv->lock, flags);
2739
2740         /* Power Down bit, into the PM register, is cleared
2741          * automatically as soon as a magic packet or a Wake-up frame
2742          * is received. Anyway, it's better to manually clear
2743          * this bit because it can generate problems while resuming
2744          * from another devices (e.g. serial console). */
2745         if (device_may_wakeup(priv->device))
2746                 priv->hw->mac->pmt(priv->ioaddr, 0);
2747         else
2748                 /* enable the clk prevously disabled */
2749                 clk_prepare_enable(priv->stmmac_clk);
2750
2751         netif_device_attach(ndev);
2752
2753         /* Enable the MAC and DMA */
2754         stmmac_set_mac(priv->ioaddr, true);
2755         priv->hw->dma->start_tx(priv->ioaddr);
2756         priv->hw->dma->start_rx(priv->ioaddr);
2757
2758         napi_enable(&priv->napi);
2759
2760         netif_start_queue(ndev);
2761
2762         spin_unlock_irqrestore(&priv->lock, flags);
2763
2764         if (priv->phydev)
2765                 phy_start(priv->phydev);
2766
2767         return 0;
2768 }
2769
2770 int stmmac_freeze(struct net_device *ndev)
2771 {
2772         if (!ndev || !netif_running(ndev))
2773                 return 0;
2774
2775         return stmmac_release(ndev);
2776 }
2777
2778 int stmmac_restore(struct net_device *ndev)
2779 {
2780         if (!ndev || !netif_running(ndev))
2781                 return 0;
2782
2783         return stmmac_open(ndev);
2784 }
2785 #endif /* CONFIG_PM */
2786
2787 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2788  * depending on the configuration selected.
2789  */
2790 static int __init stmmac_init(void)
2791 {
2792         int ret;
2793
2794         ret = stmmac_register_platform();
2795         if (ret)
2796                 goto err;
2797         ret = stmmac_register_pci();
2798         if (ret)
2799                 goto err_pci;
2800         return 0;
2801 err_pci:
2802         stmmac_unregister_platform();
2803 err:
2804         pr_err("stmmac: driver registration failed\n");
2805         return ret;
2806 }
2807
2808 static void __exit stmmac_exit(void)
2809 {
2810         stmmac_unregister_platform();
2811         stmmac_unregister_pci();
2812 }
2813
2814 module_init(stmmac_init);
2815 module_exit(stmmac_exit);
2816
2817 #ifndef MODULE
2818 static int __init stmmac_cmdline_opt(char *str)
2819 {
2820         char *opt;
2821
2822         if (!str || !*str)
2823                 return -EINVAL;
2824         while ((opt = strsep(&str, ",")) != NULL) {
2825                 if (!strncmp(opt, "debug:", 6)) {
2826                         if (kstrtoint(opt + 6, 0, &debug))
2827                                 goto err;
2828                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2829                         if (kstrtoint(opt + 8, 0, &phyaddr))
2830                                 goto err;
2831                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2832                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2833                                 goto err;
2834                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2835                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2836                                 goto err;
2837                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2838                         if (kstrtoint(opt + 7, 0, &buf_sz))
2839                                 goto err;
2840                 } else if (!strncmp(opt, "tc:", 3)) {
2841                         if (kstrtoint(opt + 3, 0, &tc))
2842                                 goto err;
2843                 } else if (!strncmp(opt, "watchdog:", 9)) {
2844                         if (kstrtoint(opt + 9, 0, &watchdog))
2845                                 goto err;
2846                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2847                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2848                                 goto err;
2849                 } else if (!strncmp(opt, "pause:", 6)) {
2850                         if (kstrtoint(opt + 6, 0, &pause))
2851                                 goto err;
2852                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2853                         if (kstrtoint(opt + 10, 0, &eee_timer))
2854                                 goto err;
2855                 } else if (!strncmp(opt, "chain_mode:", 11)) {
2856                         if (kstrtoint(opt + 11, 0, &chain_mode))
2857                                 goto err;
2858                 }
2859         }
2860         return 0;
2861
2862 err:
2863         pr_err("%s: ERROR broken module parameter conversion", __func__);
2864         return -EINVAL;
2865 }
2866
2867 __setup("stmmaceth=", stmmac_cmdline_opt);
2868 #endif
2869
2870 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2871 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2872 MODULE_LICENSE("GPL");