drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_STMMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif
  50 #include "stmmac.h"
  51
  52 #undef STMMAC_DEBUG
  53 /*#define STMMAC_DEBUG*/
  54 #ifdef STMMAC_DEBUG
  55 #define DBG(nlevel, klevel, fmt, args...) \
  56                 ((void)(netif_msg_##nlevel(priv) && \
  57                 printk(KERN_##klevel fmt, ## args)))
  58 #else
  59 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  60 #endif
  61
  62 #undef STMMAC_RX_DEBUG
  63 /*#define STMMAC_RX_DEBUG*/
  64 #ifdef STMMAC_RX_DEBUG
  65 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  66 #else
  67 #define RX_DBG(fmt, args...)  do { } while (0)
  68 #endif
  69
  70 #undef STMMAC_XMIT_DEBUG
  71 /*#define STMMAC_XMIT_DEBUG*/
  72 #ifdef STMMAC_XMIT_DEBUG
  73 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  74 #else
  75 #define TX_DBG(fmt, args...)  do { } while (0)
  76 #endif
  77
  78 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  79 #define JUMBO_LEN       9000
  80
  81 /* Module parameters */
  82 #define TX_TIMEO 5000 /* default 5 seconds */
  83 static int watchdog = TX_TIMEO;
  84 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  85 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  86
  87 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  88 module_param(debug, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  90
  91 int phyaddr = -1;
  92 module_param(phyaddr, int, S_IRUGO);
  93 MODULE_PARM_DESC(phyaddr, "Physical device address");
  94
  95 #define DMA_TX_SIZE 256
  96 static int dma_txsize = DMA_TX_SIZE;
  97 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  99
 100 #define DMA_RX_SIZE 256
 101 static int dma_rxsize = DMA_RX_SIZE;
 102 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 103 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 104
 105 static int flow_ctrl = FLOW_OFF;
 106 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 107 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 108
 109 static int pause = PAUSE_TIME;
 110 module_param(pause, int, S_IRUGO | S_IWUSR);
 111 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 112
 113 #define TC_DEFAULT 64
 114 static int tc = TC_DEFAULT;
 115 module_param(tc, int, S_IRUGO | S_IWUSR);
 116 MODULE_PARM_DESC(tc, "DMA threshold control value");
 117
 118 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 119 static int buf_sz = DMA_BUFFER_SIZE;
 120 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 121 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 122
 123 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 124                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 125                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 126
 127 #define STMMAC_DEFAULT_LPI_TIMER        1000
 128 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 129 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 130 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 131 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
 132
 133 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 134
 135 #ifdef CONFIG_STMMAC_DEBUG_FS
 136 static int stmmac_init_fs(struct net_device *dev);
 137 static void stmmac_exit_fs(void);
 138 #endif
 139
 140 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 141
 142 /**
 143  * stmmac_verify_args - verify the driver parameters.
 144  * Description: it verifies if some wrong parameter is passed to the driver.
 145  * Note that wrong parameters are replaced with the default values.
 146  */
 147 static void stmmac_verify_args(void)
 148 {
 149         if (unlikely(watchdog < 0))
 150                 watchdog = TX_TIMEO;
 151         if (unlikely(dma_rxsize < 0))
 152                 dma_rxsize = DMA_RX_SIZE;
 153         if (unlikely(dma_txsize < 0))
 154                 dma_txsize = DMA_TX_SIZE;
 155         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 156                 buf_sz = DMA_BUFFER_SIZE;
 157         if (unlikely(flow_ctrl > 1))
 158                 flow_ctrl = FLOW_AUTO;
 159         else if (likely(flow_ctrl < 0))
 160                 flow_ctrl = FLOW_OFF;
 161         if (unlikely((pause < 0) || (pause > 0xffff)))
 162                 pause = PAUSE_TIME;
 163         if (eee_timer < 0)
 164                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 165 }
 166
 167 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 168 {
 169         u32 clk_rate;
 170
 171         clk_rate = clk_get_rate(priv->stmmac_clk);
 172
 173         /* Platform provided default clk_csr would be assumed valid
 174          * for all other cases except for the below mentioned ones. */
 175         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 176                 if (clk_rate < CSR_F_35M)
 177                         priv->clk_csr = STMMAC_CSR_20_35M;
 178                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 179                         priv->clk_csr = STMMAC_CSR_35_60M;
 180                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 181                         priv->clk_csr = STMMAC_CSR_60_100M;
 182                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 183                         priv->clk_csr = STMMAC_CSR_100_150M;
 184                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 185                         priv->clk_csr = STMMAC_CSR_150_250M;
 186                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 187                         priv->clk_csr = STMMAC_CSR_250_300M;
 188         } /* For values higher than the IEEE 802.3 specified frequency
 189            * we can not estimate the proper divider as it is not known
 190            * the frequency of clk_csr_i. So we do not change the default
 191            * divider. */
 192 }
 193
 194 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 195 static void print_pkt(unsigned char *buf, int len)
 196 {
 197         int j;
 198         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 199         for (j = 0; j < len; j++) {
 200                 if ((j % 16) == 0)
 201                         pr_info("\n %03x:", j);
 202                 pr_info(" %02x", buf[j]);
 203         }
 204         pr_info("\n");
 205 }
 206 #endif
 207
 208 /* minimum number of free TX descriptors required to wake up TX process */
 209 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 210
 211 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 212 {
 213         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 214 }
 215
 216 /* On some ST platforms, some HW system configuraton registers have to be
 217  * set according to the link speed negotiated.
 218  */
 219 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 220 {
 221         struct phy_device *phydev = priv->phydev;
 222
 223         if (likely(priv->plat->fix_mac_speed))
 224                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
 225                                           phydev->speed);
 226 }
 227
 228 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 229 {
 230         /* Check and enter in LPI mode */
 231         if ((priv->dirty_tx == priv->cur_tx) &&
 232             (priv->tx_path_in_lpi_mode == false))
 233                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 234 }
 235
 236 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 237 {
 238         /* Exit and disable EEE in case of we are are in LPI state. */
 239         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 240         del_timer_sync(&priv->eee_ctrl_timer);
 241         priv->tx_path_in_lpi_mode = false;
 242 }
 243
 244 /**
 245  * stmmac_eee_ctrl_timer
 246  * @arg : data hook
 247  * Description:
 248  *  If there is no data transfer and if we are not in LPI state,
 249  *  then MAC Transmitter can be moved to LPI state.
 250  */
 251 static void stmmac_eee_ctrl_timer(unsigned long arg)
 252 {
 253         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 254
 255         stmmac_enable_eee_mode(priv);
 256         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 257 }
 258
 259 /**
 260  * stmmac_eee_init
 261  * @priv: private device pointer
 262  * Description:
 263  *  If the EEE support has been enabled while configuring the driver,
 264  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 265  *  phy can also manage EEE, so enable the LPI state and start the timer
 266  *  to verify if the tx path can enter in LPI state.
 267  */
 268 bool stmmac_eee_init(struct stmmac_priv *priv)
 269 {
 270         bool ret = false;
 271
 272         /* MAC core supports the EEE feature. */
 273         if (priv->dma_cap.eee) {
 274                 /* Check if the PHY supports EEE */
 275                 if (phy_init_eee(priv->phydev, 1))
 276                         goto out;
 277
 278                 priv->eee_active = 1;
 279                 init_timer(&priv->eee_ctrl_timer);
 280                 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 281                 priv->eee_ctrl_timer.data = (unsigned long)priv;
 282                 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
 283                 add_timer(&priv->eee_ctrl_timer);
 284
 285                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 286                                              STMMAC_DEFAULT_LIT_LS_TIMER,
 287                                              priv->tx_lpi_timer);
 288
 289                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 290
 291                 ret = true;
 292         }
 293 out:
 294         return ret;
 295 }
 296
 297 static void stmmac_eee_adjust(struct stmmac_priv *priv)
 298 {
 299         /* When the EEE has been already initialised we have to
 300          * modify the PLS bit in the LPI ctrl & status reg according
 301          * to the PHY link status. For this reason.
 302          */
 303         if (priv->eee_enabled)
 304                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 305 }
 306
 307 /**
 308  * stmmac_adjust_link
 309  * @dev: net device structure
 310  * Description: it adjusts the link parameters.
 311  */
 312 static void stmmac_adjust_link(struct net_device *dev)
 313 {
 314         struct stmmac_priv *priv = netdev_priv(dev);
 315         struct phy_device *phydev = priv->phydev;
 316         unsigned long flags;
 317         int new_state = 0;
 318         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 319
 320         if (phydev == NULL)
 321                 return;
 322
 323         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 324             phydev->addr, phydev->link);
 325
 326         spin_lock_irqsave(&priv->lock, flags);
 327
 328         if (phydev->link) {
 329                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 330
 331                 /* Now we make sure that we can be in full duplex mode.
 332                  * If not, we operate in half-duplex mode. */
 333                 if (phydev->duplex != priv->oldduplex) {
 334                         new_state = 1;
 335                         if (!(phydev->duplex))
 336                                 ctrl &= ~priv->hw->link.duplex;
 337                         else
 338                                 ctrl |= priv->hw->link.duplex;
 339                         priv->oldduplex = phydev->duplex;
 340                 }
 341                 /* Flow Control operation */
 342                 if (phydev->pause)
 343                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 344                                                  fc, pause_time);
 345
 346                 if (phydev->speed != priv->speed) {
 347                         new_state = 1;
 348                         switch (phydev->speed) {
 349                         case 1000:
 350                                 if (likely(priv->plat->has_gmac))
 351                                         ctrl &= ~priv->hw->link.port;
 352                                         stmmac_hw_fix_mac_speed(priv);
 353                                 break;
 354                         case 100:
 355                         case 10:
 356                                 if (priv->plat->has_gmac) {
 357                                         ctrl |= priv->hw->link.port;
 358                                         if (phydev->speed == SPEED_100) {
 359                                                 ctrl |= priv->hw->link.speed;
 360                                         } else {
 361                                                 ctrl &= ~(priv->hw->link.speed);
 362                                         }
 363                                 } else {
 364                                         ctrl &= ~priv->hw->link.port;
 365                                 }
 366                                 stmmac_hw_fix_mac_speed(priv);
 367                                 break;
 368                         default:
 369                                 if (netif_msg_link(priv))
 370                                         pr_warning("%s: Speed (%d) is not 10"
 371                                        " or 100!\n", dev->name, phydev->speed);
 372                                 break;
 373                         }
 374
 375                         priv->speed = phydev->speed;
 376                 }
 377
 378                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 379
 380                 if (!priv->oldlink) {
 381                         new_state = 1;
 382                         priv->oldlink = 1;
 383                 }
 384         } else if (priv->oldlink) {
 385                 new_state = 1;
 386                 priv->oldlink = 0;
 387                 priv->speed = 0;
 388                 priv->oldduplex = -1;
 389         }
 390
 391         if (new_state && netif_msg_link(priv))
 392                 phy_print_status(phydev);
 393
 394         stmmac_eee_adjust(priv);
 395
 396         spin_unlock_irqrestore(&priv->lock, flags);
 397
 398         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 399 }
 400
 401 /**
 402  * stmmac_init_phy - PHY initialization
 403  * @dev: net device structure
 404  * Description: it initializes the driver's PHY state, and attaches the PHY
 405  * to the mac driver.
 406  *  Return value:
 407  *  0 on success
 408  */
 409 static int stmmac_init_phy(struct net_device *dev)
 410 {
 411         struct stmmac_priv *priv = netdev_priv(dev);
 412         struct phy_device *phydev;
 413         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 414         char bus_id[MII_BUS_ID_SIZE];
 415         int interface = priv->plat->interface;
 416         priv->oldlink = 0;
 417         priv->speed = 0;
 418         priv->oldduplex = -1;
 419
 420         if (priv->plat->phy_bus_name)
 421                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 422                                 priv->plat->phy_bus_name, priv->plat->bus_id);
 423         else
 424                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 425                                 priv->plat->bus_id);
 426
 427         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 428                  priv->plat->phy_addr);
 429         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 430
 431         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 432
 433         if (IS_ERR(phydev)) {
 434                 pr_err("%s: Could not attach to PHY\n", dev->name);
 435                 return PTR_ERR(phydev);
 436         }
 437
 438         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 439         if ((interface == PHY_INTERFACE_MODE_MII) ||
 440             (interface == PHY_INTERFACE_MODE_RMII))
 441                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 442                                          SUPPORTED_1000baseT_Full);
 443
 444         /*
 445          * Broken HW is sometimes missing the pull-up resistor on the
 446          * MDIO line, which results in reads to non-existent devices returning
 447          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 448          * device as well.
 449          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 450          */
 451         if (phydev->phy_id == 0) {
 452                 phy_disconnect(phydev);
 453                 return -ENODEV;
 454         }
 455         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 456                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 457
 458         priv->phydev = phydev;
 459
 460         return 0;
 461 }
 462
 463 /**
 464  * display_ring
 465  * @p: pointer to the ring.
 466  * @size: size of the ring.
 467  * Description: display all the descriptors within the ring.
 468  */
 469 static void display_ring(struct dma_desc *p, int size)
 470 {
 471         struct tmp_s {
 472                 u64 a;
 473                 unsigned int b;
 474                 unsigned int c;
 475         };
 476         int i;
 477         for (i = 0; i < size; i++) {
 478                 struct tmp_s *x = (struct tmp_s *)(p + i);
 479                 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
 480                        i, (unsigned int)virt_to_phys(&p[i]),
 481                        (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
 482                        x->b, x->c);
 483                 pr_info("\n");
 484         }
 485 }
 486
 487 static int stmmac_set_bfsize(int mtu, int bufsize)
 488 {
 489         int ret = bufsize;
 490
 491         if (mtu >= BUF_SIZE_4KiB)
 492                 ret = BUF_SIZE_8KiB;
 493         else if (mtu >= BUF_SIZE_2KiB)
 494                 ret = BUF_SIZE_4KiB;
 495         else if (mtu >= DMA_BUFFER_SIZE)
 496                 ret = BUF_SIZE_2KiB;
 497         else
 498                 ret = DMA_BUFFER_SIZE;
 499
 500         return ret;
 501 }
 502
 503 /**
 504  * init_dma_desc_rings - init the RX/TX descriptor rings
 505  * @dev: net device structure
 506  * Description:  this function initializes the DMA RX/TX descriptors
 507  * and allocates the socket buffers. It suppors the chained and ring
 508  * modes.
 509  */
 510 static void init_dma_desc_rings(struct net_device *dev)
 511 {
 512         int i;
 513         struct stmmac_priv *priv = netdev_priv(dev);
 514         struct sk_buff *skb;
 515         unsigned int txsize = priv->dma_tx_size;
 516         unsigned int rxsize = priv->dma_rx_size;
 517         unsigned int bfsize;
 518         int dis_ic = 0;
 519         int des3_as_data_buf = 0;
 520
 521         /* Set the max buffer size according to the DESC mode
 522          * and the MTU. Note that RING mode allows 16KiB bsize. */
 523         bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 524
 525         if (bfsize == BUF_SIZE_16KiB)
 526                 des3_as_data_buf = 1;
 527         else
 528                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 529
 530         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 531             txsize, rxsize, bfsize);
 532
 533         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
 534                                             GFP_KERNEL);
 535         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
 536                                         GFP_KERNEL);
 537         priv->dma_rx = dma_alloc_coherent(priv->device,
 538                                           rxsize * sizeof(struct dma_desc),
 539                                           &priv->dma_rx_phy, GFP_KERNEL);
 540         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
 541                                         GFP_KERNEL);
 542         priv->dma_tx = dma_alloc_coherent(priv->device,
 543                                           txsize * sizeof(struct dma_desc),
 544                                           &priv->dma_tx_phy, GFP_KERNEL);
 545
 546         if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL))
 547                 return;
 548
 549         DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
 550             "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
 551             dev->name, priv->dma_rx, priv->dma_tx,
 552             (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
 553
 554         /* RX INITIALIZATION */
 555         DBG(probe, INFO, "stmmac: SKB addresses:\n"
 556                          "skb\t\tskb data\tdma data\n");
 557
 558         for (i = 0; i < rxsize; i++) {
 559                 struct dma_desc *p = priv->dma_rx + i;
 560
 561                 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
 562                                          GFP_KERNEL);
 563                 if (unlikely(skb == NULL)) {
 564                         pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 565                         break;
 566                 }
 567                 skb_reserve(skb, NET_IP_ALIGN);
 568                 priv->rx_skbuff[i] = skb;
 569                 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 570                                                 bfsize, DMA_FROM_DEVICE);
 571
 572                 p->des2 = priv->rx_skbuff_dma[i];
 573
 574                 priv->hw->ring->init_desc3(des3_as_data_buf, p);
 575
 576                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
 577                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
 578         }
 579         priv->cur_rx = 0;
 580         priv->dirty_rx = (unsigned int)(i - rxsize);
 581         priv->dma_buf_sz = bfsize;
 582         buf_sz = bfsize;
 583
 584         /* TX INITIALIZATION */
 585         for (i = 0; i < txsize; i++) {
 586                 priv->tx_skbuff[i] = NULL;
 587                 priv->dma_tx[i].des2 = 0;
 588         }
 589
 590         /* In case of Chained mode this sets the des3 to the next
 591          * element in the chain */
 592         priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
 593         priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
 594
 595         priv->dirty_tx = 0;
 596         priv->cur_tx = 0;
 597
 598         if (priv->use_riwt)
 599                 dis_ic = 1;
 600         /* Clear the Rx/Tx descriptors */
 601         priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
 602         priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
 603
 604         if (netif_msg_hw(priv)) {
 605                 pr_info("RX descriptor ring:\n");
 606                 display_ring(priv->dma_rx, rxsize);
 607                 pr_info("TX descriptor ring:\n");
 608                 display_ring(priv->dma_tx, txsize);
 609         }
 610 }
 611
 612 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
 613 {
 614         int i;
 615
 616         for (i = 0; i < priv->dma_rx_size; i++) {
 617                 if (priv->rx_skbuff[i]) {
 618                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 619                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
 620                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 621                 }
 622                 priv->rx_skbuff[i] = NULL;
 623         }
 624 }
 625
 626 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
 627 {
 628         int i;
 629
 630         for (i = 0; i < priv->dma_tx_size; i++) {
 631                 if (priv->tx_skbuff[i] != NULL) {
 632                         struct dma_desc *p = priv->dma_tx + i;
 633                         if (p->des2)
 634                                 dma_unmap_single(priv->device, p->des2,
 635                                                  priv->hw->desc->get_tx_len(p),
 636                                                  DMA_TO_DEVICE);
 637                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 638                         priv->tx_skbuff[i] = NULL;
 639                 }
 640         }
 641 }
 642
 643 static void free_dma_desc_resources(struct stmmac_priv *priv)
 644 {
 645         /* Release the DMA TX/RX socket buffers */
 646         dma_free_rx_skbufs(priv);
 647         dma_free_tx_skbufs(priv);
 648
 649         /* Free the region of consistent memory previously allocated for
 650          * the DMA */
 651         dma_free_coherent(priv->device,
 652                           priv->dma_tx_size * sizeof(struct dma_desc),
 653                           priv->dma_tx, priv->dma_tx_phy);
 654         dma_free_coherent(priv->device,
 655                           priv->dma_rx_size * sizeof(struct dma_desc),
 656                           priv->dma_rx, priv->dma_rx_phy);
 657         kfree(priv->rx_skbuff_dma);
 658         kfree(priv->rx_skbuff);
 659         kfree(priv->tx_skbuff);
 660 }
 661
 662 /**
 663  *  stmmac_dma_operation_mode - HW DMA operation mode
 664  *  @priv : pointer to the private device structure.
 665  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
 666  *  or Store-And-Forward capability.
 667  */
 668 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 669 {
 670         if (likely(priv->plat->force_sf_dma_mode ||
 671                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
 672                 /*
 673                  * In case of GMAC, SF mode can be enabled
 674                  * to perform the TX COE in HW. This depends on:
 675                  * 1) TX COE if actually supported
 676                  * 2) There is no bugged Jumbo frame support
 677                  *    that needs to not insert csum in the TDES.
 678                  */
 679                 priv->hw->dma->dma_mode(priv->ioaddr,
 680                                         SF_DMA_MODE, SF_DMA_MODE);
 681                 tc = SF_DMA_MODE;
 682         } else
 683                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 684 }
 685
 686 /**
 687  * stmmac_tx_clean:
 688  * @priv: private data pointer
 689  * Description: it reclaims resources after transmission completes.
 690  */
 691 static void stmmac_tx_clean(struct stmmac_priv *priv)
 692 {
 693         unsigned int txsize = priv->dma_tx_size;
 694
 695         spin_lock(&priv->tx_lock);
 696
 697         priv->xstats.tx_clean++;
 698
 699         while (priv->dirty_tx != priv->cur_tx) {
 700                 int last;
 701                 unsigned int entry = priv->dirty_tx % txsize;
 702                 struct sk_buff *skb = priv->tx_skbuff[entry];
 703                 struct dma_desc *p = priv->dma_tx + entry;
 704
 705                 /* Check if the descriptor is owned by the DMA. */
 706                 if (priv->hw->desc->get_tx_owner(p))
 707                         break;
 708
 709                 /* Verify tx error by looking at the last segment */
 710                 last = priv->hw->desc->get_tx_ls(p);
 711                 if (likely(last)) {
 712                         int tx_error =
 713                                 priv->hw->desc->tx_status(&priv->dev->stats,
 714                                                           &priv->xstats, p,
 715                                                           priv->ioaddr);
 716                         if (likely(tx_error == 0)) {
 717                                 priv->dev->stats.tx_packets++;
 718                                 priv->xstats.tx_pkt_n++;
 719                         } else
 720                                 priv->dev->stats.tx_errors++;
 721                 }
 722                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
 723                         priv->cur_tx, priv->dirty_tx);
 724
 725                 if (likely(p->des2))
 726                         dma_unmap_single(priv->device, p->des2,
 727                                          priv->hw->desc->get_tx_len(p),
 728                                          DMA_TO_DEVICE);
 729                 priv->hw->ring->clean_desc3(p);
 730
 731                 if (likely(skb != NULL)) {
 732                         dev_kfree_skb(skb);
 733                         priv->tx_skbuff[entry] = NULL;
 734                 }
 735
 736                 priv->hw->desc->release_tx_desc(p);
 737
 738                 priv->dirty_tx++;
 739         }
 740         if (unlikely(netif_queue_stopped(priv->dev) &&
 741                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
 742                 netif_tx_lock(priv->dev);
 743                 if (netif_queue_stopped(priv->dev) &&
 744                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
 745                         TX_DBG("%s: restart transmit\n", __func__);
 746                         netif_wake_queue(priv->dev);
 747                 }
 748                 netif_tx_unlock(priv->dev);
 749         }
 750
 751         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
 752                 stmmac_enable_eee_mode(priv);
 753                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 754         }
 755         spin_unlock(&priv->tx_lock);
 756 }
 757
 758 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
 759 {
 760         priv->hw->dma->enable_dma_irq(priv->ioaddr);
 761 }
 762
 763 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
 764 {
 765         priv->hw->dma->disable_dma_irq(priv->ioaddr);
 766 }
 767
 768
 769 /**
 770  * stmmac_tx_err:
 771  * @priv: pointer to the private device structure
 772  * Description: it cleans the descriptors and restarts the transmission
 773  * in case of errors.
 774  */
 775 static void stmmac_tx_err(struct stmmac_priv *priv)
 776 {
 777         netif_stop_queue(priv->dev);
 778
 779         priv->hw->dma->stop_tx(priv->ioaddr);
 780         dma_free_tx_skbufs(priv);
 781         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
 782         priv->dirty_tx = 0;
 783         priv->cur_tx = 0;
 784         priv->hw->dma->start_tx(priv->ioaddr);
 785
 786         priv->dev->stats.tx_errors++;
 787         netif_wake_queue(priv->dev);
 788 }
 789
 790 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
 791 {
 792         int status;
 793
 794         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
 795         if (likely((status & handle_rx)) || (status & handle_tx)) {
 796                 if (likely(napi_schedule_prep(&priv->napi))) {
 797                         stmmac_disable_dma_irq(priv);
 798                         __napi_schedule(&priv->napi);
 799                 }
 800         }
 801         if (unlikely(status & tx_hard_error_bump_tc)) {
 802                 /* Try to bump up the dma threshold on this failure */
 803                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
 804                         tc += 64;
 805                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 806                         priv->xstats.threshold = tc;
 807                 }
 808         } else if (unlikely(status == tx_hard_error))
 809                 stmmac_tx_err(priv);
 810 }
 811
 812 static void stmmac_mmc_setup(struct stmmac_priv *priv)
 813 {
 814         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
 815                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
 816
 817         /* Mask MMC irq, counters are managed in SW and registers
 818          * are cleared on each READ eventually. */
 819         dwmac_mmc_intr_all_mask(priv->ioaddr);
 820
 821         if (priv->dma_cap.rmon) {
 822                 dwmac_mmc_ctrl(priv->ioaddr, mode);
 823                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
 824         } else
 825                 pr_info(" No MAC Management Counters available\n");
 826 }
 827
 828 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
 829 {
 830         u32 hwid = priv->hw->synopsys_uid;
 831
 832         /* Only check valid Synopsys Id because old MAC chips
 833          * have no HW registers where get the ID */
 834         if (likely(hwid)) {
 835                 u32 uid = ((hwid & 0x0000ff00) >> 8);
 836                 u32 synid = (hwid & 0x000000ff);
 837
 838                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
 839                         uid, synid);
 840
 841                 return synid;
 842         }
 843         return 0;
 844 }
 845
 846 /**
 847  * stmmac_selec_desc_mode
 848  * @priv : private structure
 849  * Description: select the Enhanced/Alternate or Normal descriptors
 850  */
 851 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
 852 {
 853         if (priv->plat->enh_desc) {
 854                 pr_info(" Enhanced/Alternate descriptors\n");
 855                 priv->hw->desc = &enh_desc_ops;
 856         } else {
 857                 pr_info(" Normal descriptors\n");
 858                 priv->hw->desc = &ndesc_ops;
 859         }
 860 }
 861
 862 /**
 863  * stmmac_get_hw_features
 864  * @priv : private device pointer
 865  * Description:
 866  *  new GMAC chip generations have a new register to indicate the
 867  *  presence of the optional feature/functions.
 868  *  This can be also used to override the value passed through the
 869  *  platform and necessary for old MAC10/100 and GMAC chips.
 870  */
 871 static int stmmac_get_hw_features(struct stmmac_priv *priv)
 872 {
 873         u32 hw_cap = 0;
 874
 875         if (priv->hw->dma->get_hw_feature) {
 876                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
 877
 878                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
 879                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
 880                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
 881                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
 882                 priv->dma_cap.multi_addr =
 883                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
 884                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
 885                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
 886                 priv->dma_cap.pmt_remote_wake_up =
 887                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
 888                 priv->dma_cap.pmt_magic_frame =
 889                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
 890                 /* MMC */
 891                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
 892                 /* IEEE 1588-2002*/
 893                 priv->dma_cap.time_stamp =
 894                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
 895                 /* IEEE 1588-2008*/
 896                 priv->dma_cap.atime_stamp =
 897                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
 898                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
 899                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
 900                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
 901                 /* TX and RX csum */
 902                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
 903                 priv->dma_cap.rx_coe_type1 =
 904                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
 905                 priv->dma_cap.rx_coe_type2 =
 906                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
 907                 priv->dma_cap.rxfifo_over_2048 =
 908                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
 909                 /* TX and RX number of channels */
 910                 priv->dma_cap.number_rx_channel =
 911                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
 912                 priv->dma_cap.number_tx_channel =
 913                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
 914                 /* Alternate (enhanced) DESC mode*/
 915                 priv->dma_cap.enh_desc =
 916                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
 917         }
 918
 919         return hw_cap;
 920 }
 921
 922 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
 923 {
 924         /* verify if the MAC address is valid, in case of failures it
 925          * generates a random MAC address */
 926         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
 927                 priv->hw->mac->get_umac_addr((void __iomem *)
 928                                              priv->dev->base_addr,
 929                                              priv->dev->dev_addr, 0);
 930                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
 931                         eth_hw_addr_random(priv->dev);
 932         }
 933         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
 934                                                    priv->dev->dev_addr);
 935 }
 936
 937 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
 938 {
 939         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
 940         int mixed_burst = 0;
 941
 942         /* Some DMA parameters can be passed from the platform;
 943          * in case of these are not passed we keep a default
 944          * (good for all the chips) and init the DMA! */
 945         if (priv->plat->dma_cfg) {
 946                 pbl = priv->plat->dma_cfg->pbl;
 947                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
 948                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
 949                 burst_len = priv->plat->dma_cfg->burst_len;
 950         }
 951
 952         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
 953                                    burst_len, priv->dma_tx_phy,
 954                                    priv->dma_rx_phy);
 955 }
 956
 957 /**
 958  * stmmac_tx_timer:
 959  * @data: data pointer
 960  * Description:
 961  * This is the timer handler to directly invoke the stmmac_tx_clean.
 962  */
 963 static void stmmac_tx_timer(unsigned long data)
 964 {
 965         struct stmmac_priv *priv = (struct stmmac_priv *)data;
 966
 967         stmmac_tx_clean(priv);
 968 }
 969
 970 /**
 971  * stmmac_tx_timer:
 972  * @priv: private data structure
 973  * Description:
 974  * This inits the transmit coalesce parameters: i.e. timer rate,
 975  * timer handler and default threshold used for enabling the
 976  * interrupt on completion bit.
 977  */
 978 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
 979 {
 980         priv->tx_coal_frames = STMMAC_TX_FRAMES;
 981         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
 982         init_timer(&priv->txtimer);
 983         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
 984         priv->txtimer.data = (unsigned long)priv;
 985         priv->txtimer.function = stmmac_tx_timer;
 986         add_timer(&priv->txtimer);
 987 }
 988
 989 /**
 990  *  stmmac_open - open entry point of the driver
 991  *  @dev : pointer to the device structure.
 992  *  Description:
 993  *  This function is the open entry point of the driver.
 994  *  Return value:
 995  *  0 on success and an appropriate (-)ve integer as defined in errno.h
 996  *  file on failure.
 997  */
 998 static int stmmac_open(struct net_device *dev)
 999 {
1000         struct stmmac_priv *priv = netdev_priv(dev);
1001         int ret;
1002
1003         clk_prepare_enable(priv->stmmac_clk);
1004
1005         stmmac_check_ether_addr(priv);
1006
1007         ret = stmmac_init_phy(dev);
1008         if (unlikely(ret)) {
1009                 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
1010                 goto open_error;
1011         }
1012
1013         /* Create and initialize the TX/RX descriptors chains. */
1014         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1015         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1016         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1017         init_dma_desc_rings(dev);
1018
1019         /* DMA initialization and SW reset */
1020         ret = stmmac_init_dma_engine(priv);
1021         if (ret < 0) {
1022                 pr_err("%s: DMA initialization failed\n", __func__);
1023                 goto open_error;
1024         }
1025
1026         /* Copy the MAC addr into the HW  */
1027         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1028
1029         /* If required, perform hw setup of the bus. */
1030         if (priv->plat->bus_setup)
1031                 priv->plat->bus_setup(priv->ioaddr);
1032
1033         /* Initialize the MAC Core */
1034         priv->hw->mac->core_init(priv->ioaddr);
1035
1036         /* Request the IRQ lines */
1037         ret = request_irq(dev->irq, stmmac_interrupt,
1038                          IRQF_SHARED, dev->name, dev);
1039         if (unlikely(ret < 0)) {
1040                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1041                        __func__, dev->irq, ret);
1042                 goto open_error;
1043         }
1044
1045         /* Request the Wake IRQ in case of another line is used for WoL */
1046         if (priv->wol_irq != dev->irq) {
1047                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1048                                   IRQF_SHARED, dev->name, dev);
1049                 if (unlikely(ret < 0)) {
1050                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1051                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1052                         goto open_error_wolirq;
1053                 }
1054         }
1055
1056         /* Request the IRQ lines */
1057         if (priv->lpi_irq != -ENXIO) {
1058                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1059                                   dev->name, dev);
1060                 if (unlikely(ret < 0)) {
1061                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1062                                __func__, priv->lpi_irq, ret);
1063                         goto open_error_lpiirq;
1064                 }
1065         }
1066
1067         /* Enable the MAC Rx/Tx */
1068         stmmac_set_mac(priv->ioaddr, true);
1069
1070         /* Set the HW DMA mode and the COE */
1071         stmmac_dma_operation_mode(priv);
1072
1073         /* Extra statistics */
1074         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1075         priv->xstats.threshold = tc;
1076
1077         stmmac_mmc_setup(priv);
1078
1079 #ifdef CONFIG_STMMAC_DEBUG_FS
1080         ret = stmmac_init_fs(dev);
1081         if (ret < 0)
1082                 pr_warning("%s: failed debugFS registration\n", __func__);
1083 #endif
1084         /* Start the ball rolling... */
1085         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1086         priv->hw->dma->start_tx(priv->ioaddr);
1087         priv->hw->dma->start_rx(priv->ioaddr);
1088
1089         /* Dump DMA/MAC registers */
1090         if (netif_msg_hw(priv)) {
1091                 priv->hw->mac->dump_regs(priv->ioaddr);
1092                 priv->hw->dma->dump_regs(priv->ioaddr);
1093         }
1094
1095         if (priv->phydev)
1096                 phy_start(priv->phydev);
1097
1098         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1099         priv->eee_enabled = stmmac_eee_init(priv);
1100
1101         stmmac_init_tx_coalesce(priv);
1102
1103         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1104                 priv->rx_riwt = MAX_DMA_RIWT;
1105                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1106         }
1107
1108         napi_enable(&priv->napi);
1109         netif_start_queue(dev);
1110
1111         return 0;
1112
1113 open_error_lpiirq:
1114         if (priv->wol_irq != dev->irq)
1115                 free_irq(priv->wol_irq, dev);
1116
1117 open_error_wolirq:
1118         free_irq(dev->irq, dev);
1119
1120 open_error:
1121         if (priv->phydev)
1122                 phy_disconnect(priv->phydev);
1123
1124         clk_disable_unprepare(priv->stmmac_clk);
1125
1126         return ret;
1127 }
1128
1129 /**
1130  *  stmmac_release - close entry point of the driver
1131  *  @dev : device pointer.
1132  *  Description:
1133  *  This is the stop entry point of the driver.
1134  */
1135 static int stmmac_release(struct net_device *dev)
1136 {
1137         struct stmmac_priv *priv = netdev_priv(dev);
1138
1139         if (priv->eee_enabled)
1140                 del_timer_sync(&priv->eee_ctrl_timer);
1141
1142         /* Stop and disconnect the PHY */
1143         if (priv->phydev) {
1144                 phy_stop(priv->phydev);
1145                 phy_disconnect(priv->phydev);
1146                 priv->phydev = NULL;
1147         }
1148
1149         netif_stop_queue(dev);
1150
1151         napi_disable(&priv->napi);
1152
1153         del_timer_sync(&priv->txtimer);
1154
1155         /* Free the IRQ lines */
1156         free_irq(dev->irq, dev);
1157         if (priv->wol_irq != dev->irq)
1158                 free_irq(priv->wol_irq, dev);
1159         if (priv->lpi_irq != -ENXIO)
1160                 free_irq(priv->lpi_irq, dev);
1161
1162         /* Stop TX/RX DMA and clear the descriptors */
1163         priv->hw->dma->stop_tx(priv->ioaddr);
1164         priv->hw->dma->stop_rx(priv->ioaddr);
1165
1166         /* Release and free the Rx/Tx resources */
1167         free_dma_desc_resources(priv);
1168
1169         /* Disable the MAC Rx/Tx */
1170         stmmac_set_mac(priv->ioaddr, false);
1171
1172         netif_carrier_off(dev);
1173
1174 #ifdef CONFIG_STMMAC_DEBUG_FS
1175         stmmac_exit_fs();
1176 #endif
1177         clk_disable_unprepare(priv->stmmac_clk);
1178
1179         return 0;
1180 }
1181
1182 /**
1183  *  stmmac_xmit:
1184  *  @skb : the socket buffer
1185  *  @dev : device pointer
1186  *  Description : Tx entry point of the driver.
1187  */
1188 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1189 {
1190         struct stmmac_priv *priv = netdev_priv(dev);
1191         unsigned int txsize = priv->dma_tx_size;
1192         unsigned int entry;
1193         int i, csum_insertion = 0;
1194         int nfrags = skb_shinfo(skb)->nr_frags;
1195         struct dma_desc *desc, *first;
1196         unsigned int nopaged_len = skb_headlen(skb);
1197
1198         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1199                 if (!netif_queue_stopped(dev)) {
1200                         netif_stop_queue(dev);
1201                         /* This is a hard error, log it. */
1202                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1203                                 __func__);
1204                 }
1205                 return NETDEV_TX_BUSY;
1206         }
1207
1208         spin_lock(&priv->tx_lock);
1209
1210         if (priv->tx_path_in_lpi_mode)
1211                 stmmac_disable_eee_mode(priv);
1212
1213         entry = priv->cur_tx % txsize;
1214
1215 #ifdef STMMAC_XMIT_DEBUG
1216         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1217                 pr_debug("stmmac xmit: [entry %d]\n"
1218                          "\tskb addr %p - len: %d - nopaged_len: %d\n"
1219                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1220                          "\ttx_count_frames %d\n", entry,
1221                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1222                          !skb_is_gso(skb) ? "isn't" : "is",
1223                          priv->tx_count_frames);
1224 #endif
1225
1226         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1227
1228         desc = priv->dma_tx + entry;
1229         first = desc;
1230
1231 #ifdef STMMAC_XMIT_DEBUG
1232         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1233                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1234                          "\t\tn_frags: %d, ip_summed: %d\n",
1235                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1236 #endif
1237         priv->tx_skbuff[entry] = skb;
1238
1239         if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1240                 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
1241                 desc = priv->dma_tx + entry;
1242         } else {
1243                 desc->des2 = dma_map_single(priv->device, skb->data,
1244                                         nopaged_len, DMA_TO_DEVICE);
1245                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1246                                                 csum_insertion);
1247         }
1248
1249         for (i = 0; i < nfrags; i++) {
1250                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1251                 int len = skb_frag_size(frag);
1252
1253                 entry = (++priv->cur_tx) % txsize;
1254                 desc = priv->dma_tx + entry;
1255
1256                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1257                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1258                                               DMA_TO_DEVICE);
1259                 priv->tx_skbuff[entry] = NULL;
1260                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1261                 wmb();
1262                 priv->hw->desc->set_tx_owner(desc);
1263                 wmb();
1264         }
1265
1266         /* Finalize the latest segment. */
1267         priv->hw->desc->close_tx_desc(desc);
1268
1269         wmb();
1270         /* According to the coalesce parameter the IC bit for the latest
1271          * segment could be reset and the timer re-started to invoke the
1272          * stmmac_tx function. This approach takes care about the fragments.
1273          */
1274         priv->tx_count_frames += nfrags + 1;
1275         if (priv->tx_coal_frames > priv->tx_count_frames) {
1276                 priv->hw->desc->clear_tx_ic(desc);
1277                 priv->xstats.tx_reset_ic_bit++;
1278                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1279                        priv->tx_count_frames);
1280                 mod_timer(&priv->txtimer,
1281                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1282         } else
1283                 priv->tx_count_frames = 0;
1284
1285         /* To avoid raise condition */
1286         priv->hw->desc->set_tx_owner(first);
1287         wmb();
1288
1289         priv->cur_tx++;
1290
1291 #ifdef STMMAC_XMIT_DEBUG
1292         if (netif_msg_pktdata(priv)) {
1293                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1294                        "first=%p, nfrags=%d\n",
1295                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1296                        entry, first, nfrags);
1297                 display_ring(priv->dma_tx, txsize);
1298                 pr_info(">>> frame to be transmitted: ");
1299                 print_pkt(skb->data, skb->len);
1300         }
1301 #endif
1302         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1303                 TX_DBG("%s: stop transmitted packets\n", __func__);
1304                 netif_stop_queue(dev);
1305         }
1306
1307         dev->stats.tx_bytes += skb->len;
1308
1309         skb_tx_timestamp(skb);
1310
1311         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1312
1313         spin_unlock(&priv->tx_lock);
1314
1315         return NETDEV_TX_OK;
1316 }
1317
1318 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1319 {
1320         unsigned int rxsize = priv->dma_rx_size;
1321         int bfsize = priv->dma_buf_sz;
1322         struct dma_desc *p = priv->dma_rx;
1323
1324         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1325                 unsigned int entry = priv->dirty_rx % rxsize;
1326                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1327                         struct sk_buff *skb;
1328
1329                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1330
1331                         if (unlikely(skb == NULL))
1332                                 break;
1333
1334                         priv->rx_skbuff[entry] = skb;
1335                         priv->rx_skbuff_dma[entry] =
1336                             dma_map_single(priv->device, skb->data, bfsize,
1337                                            DMA_FROM_DEVICE);
1338
1339                         (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1340
1341                         if (unlikely(priv->plat->has_gmac))
1342                                 priv->hw->ring->refill_desc3(bfsize, p + entry);
1343
1344                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1345                 }
1346                 wmb();
1347                 priv->hw->desc->set_rx_owner(p + entry);
1348                 wmb();
1349         }
1350 }
1351
1352 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1353 {
1354         unsigned int rxsize = priv->dma_rx_size;
1355         unsigned int entry = priv->cur_rx % rxsize;
1356         unsigned int next_entry;
1357         unsigned int count = 0;
1358         struct dma_desc *p = priv->dma_rx + entry;
1359         struct dma_desc *p_next;
1360
1361 #ifdef STMMAC_RX_DEBUG
1362         if (netif_msg_hw(priv)) {
1363                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1364                 display_ring(priv->dma_rx, rxsize);
1365         }
1366 #endif
1367         while (!priv->hw->desc->get_rx_owner(p)) {
1368                 int status;
1369
1370                 if (count >= limit)
1371                         break;
1372
1373                 count++;
1374
1375                 next_entry = (++priv->cur_rx) % rxsize;
1376                 p_next = priv->dma_rx + next_entry;
1377                 prefetch(p_next);
1378
1379                 /* read the status of the incoming frame */
1380                 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1381                                                     &priv->xstats, p));
1382                 if (unlikely(status == discard_frame))
1383                         priv->dev->stats.rx_errors++;
1384                 else {
1385                         struct sk_buff *skb;
1386                         int frame_len;
1387
1388                         frame_len = priv->hw->desc->get_rx_frame_len(p,
1389                                         priv->plat->rx_coe);
1390                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1391                          * Type frames (LLC/LLC-SNAP) */
1392                         if (unlikely(status != llc_snap))
1393                                 frame_len -= ETH_FCS_LEN;
1394 #ifdef STMMAC_RX_DEBUG
1395                         if (frame_len > ETH_FRAME_LEN)
1396                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1397                                         frame_len, status);
1398
1399                         if (netif_msg_hw(priv))
1400                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1401                                         p, entry, p->des2);
1402 #endif
1403                         skb = priv->rx_skbuff[entry];
1404                         if (unlikely(!skb)) {
1405                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1406                                         priv->dev->name);
1407                                 priv->dev->stats.rx_dropped++;
1408                                 break;
1409                         }
1410                         prefetch(skb->data - NET_IP_ALIGN);
1411                         priv->rx_skbuff[entry] = NULL;
1412
1413                         skb_put(skb, frame_len);
1414                         dma_unmap_single(priv->device,
1415                                          priv->rx_skbuff_dma[entry],
1416                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1417 #ifdef STMMAC_RX_DEBUG
1418                         if (netif_msg_pktdata(priv)) {
1419                                 pr_info(" frame received (%dbytes)", frame_len);
1420                                 print_pkt(skb->data, frame_len);
1421                         }
1422 #endif
1423                         skb->protocol = eth_type_trans(skb, priv->dev);
1424
1425                         if (unlikely(!priv->plat->rx_coe))
1426                                 skb_checksum_none_assert(skb);
1427                         else
1428                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1429
1430                         napi_gro_receive(&priv->napi, skb);
1431
1432                         priv->dev->stats.rx_packets++;
1433                         priv->dev->stats.rx_bytes += frame_len;
1434                 }
1435                 entry = next_entry;
1436                 p = p_next;     /* use prefetched values */
1437         }
1438
1439         stmmac_rx_refill(priv);
1440
1441         priv->xstats.rx_pkt_n += count;
1442
1443         return count;
1444 }
1445
1446 /**
1447  *  stmmac_poll - stmmac poll method (NAPI)
1448  *  @napi : pointer to the napi structure.
1449  *  @budget : maximum number of packets that the current CPU can receive from
1450  *            all interfaces.
1451  *  Description :
1452  *  To look at the incoming frames and clear the tx resources.
1453  */
1454 static int stmmac_poll(struct napi_struct *napi, int budget)
1455 {
1456         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1457         int work_done = 0;
1458
1459         priv->xstats.napi_poll++;
1460         stmmac_tx_clean(priv);
1461
1462         work_done = stmmac_rx(priv, budget);
1463         if (work_done < budget) {
1464                 napi_complete(napi);
1465                 stmmac_enable_dma_irq(priv);
1466         }
1467         return work_done;
1468 }
1469
1470 /**
1471  *  stmmac_tx_timeout
1472  *  @dev : Pointer to net device structure
1473  *  Description: this function is called when a packet transmission fails to
1474  *   complete within a reasonable time. The driver will mark the error in the
1475  *   netdev structure and arrange for the device to be reset to a sane state
1476  *   in order to transmit a new packet.
1477  */
1478 static void stmmac_tx_timeout(struct net_device *dev)
1479 {
1480         struct stmmac_priv *priv = netdev_priv(dev);
1481
1482         /* Clear Tx resources and restart transmitting again */
1483         stmmac_tx_err(priv);
1484 }
1485
1486 /* Configuration changes (passed on by ifconfig) */
1487 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1488 {
1489         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1490                 return -EBUSY;
1491
1492         /* Don't allow changing the I/O address */
1493         if (map->base_addr != dev->base_addr) {
1494                 pr_warning("%s: can't change I/O address\n", dev->name);
1495                 return -EOPNOTSUPP;
1496         }
1497
1498         /* Don't allow changing the IRQ */
1499         if (map->irq != dev->irq) {
1500                 pr_warning("%s: can't change IRQ number %d\n",
1501                        dev->name, dev->irq);
1502                 return -EOPNOTSUPP;
1503         }
1504
1505         /* ignore other fields */
1506         return 0;
1507 }
1508
1509 /**
1510  *  stmmac_set_rx_mode - entry point for multicast addressing
1511  *  @dev : pointer to the device structure
1512  *  Description:
1513  *  This function is a driver entry point which gets called by the kernel
1514  *  whenever multicast addresses must be enabled/disabled.
1515  *  Return value:
1516  *  void.
1517  */
1518 static void stmmac_set_rx_mode(struct net_device *dev)
1519 {
1520         struct stmmac_priv *priv = netdev_priv(dev);
1521
1522         spin_lock(&priv->lock);
1523         priv->hw->mac->set_filter(dev, priv->synopsys_id);
1524         spin_unlock(&priv->lock);
1525 }
1526
1527 /**
1528  *  stmmac_change_mtu - entry point to change MTU size for the device.
1529  *  @dev : device pointer.
1530  *  @new_mtu : the new MTU size for the device.
1531  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1532  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1533  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1534  *  Return value:
1535  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1536  *  file on failure.
1537  */
1538 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1539 {
1540         struct stmmac_priv *priv = netdev_priv(dev);
1541         int max_mtu;
1542
1543         if (netif_running(dev)) {
1544                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1545                 return -EBUSY;
1546         }
1547
1548         if (priv->plat->enh_desc)
1549                 max_mtu = JUMBO_LEN;
1550         else
1551                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1552
1553         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1554                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1555                 return -EINVAL;
1556         }
1557
1558         dev->mtu = new_mtu;
1559         netdev_update_features(dev);
1560
1561         return 0;
1562 }
1563
1564 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1565         netdev_features_t features)
1566 {
1567         struct stmmac_priv *priv = netdev_priv(dev);
1568
1569         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
1570                 features &= ~NETIF_F_RXCSUM;
1571         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
1572                 features &= ~NETIF_F_IPV6_CSUM;
1573         if (!priv->plat->tx_coe)
1574                 features &= ~NETIF_F_ALL_CSUM;
1575
1576         /* Some GMAC devices have a bugged Jumbo frame support that
1577          * needs to have the Tx COE disabled for oversized frames
1578          * (due to limited buffer sizes). In this case we disable
1579          * the TX csum insertionin the TDES and not use SF. */
1580         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1581                 features &= ~NETIF_F_ALL_CSUM;
1582
1583         return features;
1584 }
1585
1586 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1587 {
1588         struct net_device *dev = (struct net_device *)dev_id;
1589         struct stmmac_priv *priv = netdev_priv(dev);
1590
1591         if (unlikely(!dev)) {
1592                 pr_err("%s: invalid dev pointer\n", __func__);
1593                 return IRQ_NONE;
1594         }
1595
1596         /* To handle GMAC own interrupts */
1597         if (priv->plat->has_gmac) {
1598                 int status = priv->hw->mac->host_irq_status((void __iomem *)
1599                                                             dev->base_addr);
1600                 if (unlikely(status)) {
1601                         if (status & core_mmc_tx_irq)
1602                                 priv->xstats.mmc_tx_irq_n++;
1603                         if (status & core_mmc_rx_irq)
1604                                 priv->xstats.mmc_rx_irq_n++;
1605                         if (status & core_mmc_rx_csum_offload_irq)
1606                                 priv->xstats.mmc_rx_csum_offload_irq_n++;
1607                         if (status & core_irq_receive_pmt_irq)
1608                                 priv->xstats.irq_receive_pmt_irq_n++;
1609
1610                         /* For LPI we need to save the tx status */
1611                         if (status & core_irq_tx_path_in_lpi_mode) {
1612                                 priv->xstats.irq_tx_path_in_lpi_mode_n++;
1613                                 priv->tx_path_in_lpi_mode = true;
1614                         }
1615                         if (status & core_irq_tx_path_exit_lpi_mode) {
1616                                 priv->xstats.irq_tx_path_exit_lpi_mode_n++;
1617                                 priv->tx_path_in_lpi_mode = false;
1618                         }
1619                         if (status & core_irq_rx_path_in_lpi_mode)
1620                                 priv->xstats.irq_rx_path_in_lpi_mode_n++;
1621                         if (status & core_irq_rx_path_exit_lpi_mode)
1622                                 priv->xstats.irq_rx_path_exit_lpi_mode_n++;
1623                 }
1624         }
1625
1626         /* To handle DMA interrupts */
1627         stmmac_dma_interrupt(priv);
1628
1629         return IRQ_HANDLED;
1630 }
1631
1632 #ifdef CONFIG_NET_POLL_CONTROLLER
1633 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1634  * to allow network I/O with interrupts disabled. */
1635 static void stmmac_poll_controller(struct net_device *dev)
1636 {
1637         disable_irq(dev->irq);
1638         stmmac_interrupt(dev->irq, dev);
1639         enable_irq(dev->irq);
1640 }
1641 #endif
1642
1643 /**
1644  *  stmmac_ioctl - Entry point for the Ioctl
1645  *  @dev: Device pointer.
1646  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1647  *  a proprietary structure used to pass information to the driver.
1648  *  @cmd: IOCTL command
1649  *  Description:
1650  *  Currently there are no special functionality supported in IOCTL, just the
1651  *  phy_mii_ioctl(...) can be invoked.
1652  */
1653 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1654 {
1655         struct stmmac_priv *priv = netdev_priv(dev);
1656         int ret;
1657
1658         if (!netif_running(dev))
1659                 return -EINVAL;
1660
1661         if (!priv->phydev)
1662                 return -EINVAL;
1663
1664         ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1665
1666         return ret;
1667 }
1668
1669 #ifdef CONFIG_STMMAC_DEBUG_FS
1670 static struct dentry *stmmac_fs_dir;
1671 static struct dentry *stmmac_rings_status;
1672 static struct dentry *stmmac_dma_cap;
1673
1674 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1675 {
1676         struct tmp_s {
1677                 u64 a;
1678                 unsigned int b;
1679                 unsigned int c;
1680         };
1681         int i;
1682         struct net_device *dev = seq->private;
1683         struct stmmac_priv *priv = netdev_priv(dev);
1684
1685         seq_printf(seq, "=======================\n");
1686         seq_printf(seq, " RX descriptor ring\n");
1687         seq_printf(seq, "=======================\n");
1688
1689         for (i = 0; i < priv->dma_rx_size; i++) {
1690                 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1691                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1692                            i, (unsigned int)(x->a),
1693                            (unsigned int)((x->a) >> 32), x->b, x->c);
1694                 seq_printf(seq, "\n");
1695         }
1696
1697         seq_printf(seq, "\n");
1698         seq_printf(seq, "=======================\n");
1699         seq_printf(seq, "  TX descriptor ring\n");
1700         seq_printf(seq, "=======================\n");
1701
1702         for (i = 0; i < priv->dma_tx_size; i++) {
1703                 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1704                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1705                            i, (unsigned int)(x->a),
1706                            (unsigned int)((x->a) >> 32), x->b, x->c);
1707                 seq_printf(seq, "\n");
1708         }
1709
1710         return 0;
1711 }
1712
1713 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1714 {
1715         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1716 }
1717
1718 static const struct file_operations stmmac_rings_status_fops = {
1719         .owner = THIS_MODULE,
1720         .open = stmmac_sysfs_ring_open,
1721         .read = seq_read,
1722         .llseek = seq_lseek,
1723         .release = single_release,
1724 };
1725
1726 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1727 {
1728         struct net_device *dev = seq->private;
1729         struct stmmac_priv *priv = netdev_priv(dev);
1730
1731         if (!priv->hw_cap_support) {
1732                 seq_printf(seq, "DMA HW features not supported\n");
1733                 return 0;
1734         }
1735
1736         seq_printf(seq, "==============================\n");
1737         seq_printf(seq, "\tDMA HW features\n");
1738         seq_printf(seq, "==============================\n");
1739
1740         seq_printf(seq, "\t10/100 Mbps %s\n",
1741                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1742         seq_printf(seq, "\t1000 Mbps %s\n",
1743                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
1744         seq_printf(seq, "\tHalf duple %s\n",
1745                    (priv->dma_cap.half_duplex) ? "Y" : "N");
1746         seq_printf(seq, "\tHash Filter: %s\n",
1747                    (priv->dma_cap.hash_filter) ? "Y" : "N");
1748         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1749                    (priv->dma_cap.multi_addr) ? "Y" : "N");
1750         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1751                    (priv->dma_cap.pcs) ? "Y" : "N");
1752         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1753                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
1754         seq_printf(seq, "\tPMT Remote wake up: %s\n",
1755                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1756         seq_printf(seq, "\tPMT Magic Frame: %s\n",
1757                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1758         seq_printf(seq, "\tRMON module: %s\n",
1759                    (priv->dma_cap.rmon) ? "Y" : "N");
1760         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1761                    (priv->dma_cap.time_stamp) ? "Y" : "N");
1762         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1763                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
1764         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1765                    (priv->dma_cap.eee) ? "Y" : "N");
1766         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1767         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1768                    (priv->dma_cap.tx_coe) ? "Y" : "N");
1769         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1770                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1771         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1772                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1773         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1774                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1775         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1776                    priv->dma_cap.number_rx_channel);
1777         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1778                    priv->dma_cap.number_tx_channel);
1779         seq_printf(seq, "\tEnhanced descriptors: %s\n",
1780                    (priv->dma_cap.enh_desc) ? "Y" : "N");
1781
1782         return 0;
1783 }
1784
1785 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1786 {
1787         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1788 }
1789
1790 static const struct file_operations stmmac_dma_cap_fops = {
1791         .owner = THIS_MODULE,
1792         .open = stmmac_sysfs_dma_cap_open,
1793         .read = seq_read,
1794         .llseek = seq_lseek,
1795         .release = single_release,
1796 };
1797
1798 static int stmmac_init_fs(struct net_device *dev)
1799 {
1800         /* Create debugfs entries */
1801         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1802
1803         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1804                 pr_err("ERROR %s, debugfs create directory failed\n",
1805                        STMMAC_RESOURCE_NAME);
1806
1807                 return -ENOMEM;
1808         }
1809
1810         /* Entry to report DMA RX/TX rings */
1811         stmmac_rings_status = debugfs_create_file("descriptors_status",
1812                                            S_IRUGO, stmmac_fs_dir, dev,
1813                                            &stmmac_rings_status_fops);
1814
1815         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1816                 pr_info("ERROR creating stmmac ring debugfs file\n");
1817                 debugfs_remove(stmmac_fs_dir);
1818
1819                 return -ENOMEM;
1820         }
1821
1822         /* Entry to report the DMA HW features */
1823         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1824                                              dev, &stmmac_dma_cap_fops);
1825
1826         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1827                 pr_info("ERROR creating stmmac MMC debugfs file\n");
1828                 debugfs_remove(stmmac_rings_status);
1829                 debugfs_remove(stmmac_fs_dir);
1830
1831                 return -ENOMEM;
1832         }
1833
1834         return 0;
1835 }
1836
1837 static void stmmac_exit_fs(void)
1838 {
1839         debugfs_remove(stmmac_rings_status);
1840         debugfs_remove(stmmac_dma_cap);
1841         debugfs_remove(stmmac_fs_dir);
1842 }
1843 #endif /* CONFIG_STMMAC_DEBUG_FS */
1844
1845 static const struct net_device_ops stmmac_netdev_ops = {
1846         .ndo_open = stmmac_open,
1847         .ndo_start_xmit = stmmac_xmit,
1848         .ndo_stop = stmmac_release,
1849         .ndo_change_mtu = stmmac_change_mtu,
1850         .ndo_fix_features = stmmac_fix_features,
1851         .ndo_set_rx_mode = stmmac_set_rx_mode,
1852         .ndo_tx_timeout = stmmac_tx_timeout,
1853         .ndo_do_ioctl = stmmac_ioctl,
1854         .ndo_set_config = stmmac_config,
1855 #ifdef CONFIG_NET_POLL_CONTROLLER
1856         .ndo_poll_controller = stmmac_poll_controller,
1857 #endif
1858         .ndo_set_mac_address = eth_mac_addr,
1859 };
1860
1861 /**
1862  *  stmmac_hw_init - Init the MAC device
1863  *  @priv : pointer to the private device structure.
1864  *  Description: this function detects which MAC device
1865  *  (GMAC/MAC10-100) has to attached, checks the HW capability
1866  *  (if supported) and sets the driver's features (for example
1867  *  to use the ring or chaine mode or support the normal/enh
1868  *  descriptor structure).
1869  */
1870 static int stmmac_hw_init(struct stmmac_priv *priv)
1871 {
1872         int ret = 0;
1873         struct mac_device_info *mac;
1874
1875         /* Identify the MAC HW device */
1876         if (priv->plat->has_gmac) {
1877                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1878                 mac = dwmac1000_setup(priv->ioaddr);
1879         } else {
1880                 mac = dwmac100_setup(priv->ioaddr);
1881         }
1882         if (!mac)
1883                 return -ENOMEM;
1884
1885         priv->hw = mac;
1886
1887         /* To use the chained or ring mode */
1888         priv->hw->ring = &ring_mode_ops;
1889
1890         /* Get and dump the chip ID */
1891         priv->synopsys_id = stmmac_get_synopsys_id(priv);
1892
1893         /* Get the HW capability (new GMAC newer than 3.50a) */
1894         priv->hw_cap_support = stmmac_get_hw_features(priv);
1895         if (priv->hw_cap_support) {
1896                 pr_info(" DMA HW capability register supported");
1897
1898                 /* We can override some gmac/dma configuration fields: e.g.
1899                  * enh_desc, tx_coe (e.g. that are passed through the
1900                  * platform) with the values from the HW capability
1901                  * register (if supported).
1902                  */
1903                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
1904                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
1905
1906                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
1907
1908                 if (priv->dma_cap.rx_coe_type2)
1909                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
1910                 else if (priv->dma_cap.rx_coe_type1)
1911                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
1912
1913         } else
1914                 pr_info(" No HW DMA feature register supported");
1915
1916         /* Select the enhnaced/normal descriptor structures */
1917         stmmac_selec_desc_mode(priv);
1918
1919         /* Enable the IPC (Checksum Offload) and check if the feature has been
1920          * enabled during the core configuration. */
1921         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
1922         if (!ret) {
1923                 pr_warning(" RX IPC Checksum Offload not configured.\n");
1924                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1925         }
1926
1927         if (priv->plat->rx_coe)
1928                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
1929                         priv->plat->rx_coe);
1930         if (priv->plat->tx_coe)
1931                 pr_info(" TX Checksum insertion supported\n");
1932
1933         if (priv->plat->pmt) {
1934                 pr_info(" Wake-Up On Lan supported\n");
1935                 device_set_wakeup_capable(priv->device, 1);
1936         }
1937
1938         return ret;
1939 }
1940
1941 /**
1942  * stmmac_dvr_probe
1943  * @device: device pointer
1944  * @plat_dat: platform data pointer
1945  * @addr: iobase memory address
1946  * Description: this is the main probe function used to
1947  * call the alloc_etherdev, allocate the priv structure.
1948  */
1949 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
1950                                      struct plat_stmmacenet_data *plat_dat,
1951                                      void __iomem *addr)
1952 {
1953         int ret = 0;
1954         struct net_device *ndev = NULL;
1955         struct stmmac_priv *priv;
1956
1957         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1958         if (!ndev)
1959                 return NULL;
1960
1961         SET_NETDEV_DEV(ndev, device);
1962
1963         priv = netdev_priv(ndev);
1964         priv->device = device;
1965         priv->dev = ndev;
1966
1967         ether_setup(ndev);
1968
1969         stmmac_set_ethtool_ops(ndev);
1970         priv->pause = pause;
1971         priv->plat = plat_dat;
1972         priv->ioaddr = addr;
1973         priv->dev->base_addr = (unsigned long)addr;
1974
1975         /* Verify driver arguments */
1976         stmmac_verify_args();
1977
1978         /* Override with kernel parameters if supplied XXX CRS XXX
1979          * this needs to have multiple instances */
1980         if ((phyaddr >= 0) && (phyaddr <= 31))
1981                 priv->plat->phy_addr = phyaddr;
1982
1983         /* Init MAC and get the capabilities */
1984         stmmac_hw_init(priv);
1985
1986         ndev->netdev_ops = &stmmac_netdev_ops;
1987
1988         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1989                             NETIF_F_RXCSUM;
1990         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1991         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1992 #ifdef STMMAC_VLAN_TAG_USED
1993         /* Both mac100 and gmac support receive VLAN tag detection */
1994         ndev->features |= NETIF_F_HW_VLAN_RX;
1995 #endif
1996         priv->msg_enable = netif_msg_init(debug, default_msg_level);
1997
1998         if (flow_ctrl)
1999                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2000
2001         /* Rx Watchdog is available in the COREs newer than the 3.40.
2002          * In some case, for example on bugged HW this feature
2003          * has to be disable and this can be done by passing the
2004          * riwt_off field from the platform.
2005          */
2006         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2007                 priv->use_riwt = 1;
2008                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2009         }
2010
2011         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2012
2013         spin_lock_init(&priv->lock);
2014         spin_lock_init(&priv->tx_lock);
2015
2016         ret = register_netdev(ndev);
2017         if (ret) {
2018                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2019                 goto error_netdev_register;
2020         }
2021
2022         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2023         if (IS_ERR(priv->stmmac_clk)) {
2024                 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2025                 goto error_clk_get;
2026         }
2027
2028         /* If a specific clk_csr value is passed from the platform
2029          * this means that the CSR Clock Range selection cannot be
2030          * changed at run-time and it is fixed. Viceversa the driver'll try to
2031          * set the MDC clock dynamically according to the csr actual
2032          * clock input.
2033          */
2034         if (!priv->plat->clk_csr)
2035                 stmmac_clk_csr_set(priv);
2036         else
2037                 priv->clk_csr = priv->plat->clk_csr;
2038
2039         /* MDIO bus Registration */
2040         ret = stmmac_mdio_register(ndev);
2041         if (ret < 0) {
2042                 pr_debug("%s: MDIO bus (id: %d) registration failed",
2043                          __func__, priv->plat->bus_id);
2044                 goto error_mdio_register;
2045         }
2046
2047         return priv;
2048
2049 error_mdio_register:
2050         clk_put(priv->stmmac_clk);
2051 error_clk_get:
2052         unregister_netdev(ndev);
2053 error_netdev_register:
2054         netif_napi_del(&priv->napi);
2055         free_netdev(ndev);
2056
2057         return NULL;
2058 }
2059
2060 /**
2061  * stmmac_dvr_remove
2062  * @ndev: net device pointer
2063  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2064  * changes the link status, releases the DMA descriptor rings.
2065  */
2066 int stmmac_dvr_remove(struct net_device *ndev)
2067 {
2068         struct stmmac_priv *priv = netdev_priv(ndev);
2069
2070         pr_info("%s:\n\tremoving driver", __func__);
2071
2072         priv->hw->dma->stop_rx(priv->ioaddr);
2073         priv->hw->dma->stop_tx(priv->ioaddr);
2074
2075         stmmac_set_mac(priv->ioaddr, false);
2076         stmmac_mdio_unregister(ndev);
2077         netif_carrier_off(ndev);
2078         unregister_netdev(ndev);
2079         free_netdev(ndev);
2080
2081         return 0;
2082 }
2083
2084 #ifdef CONFIG_PM
2085 int stmmac_suspend(struct net_device *ndev)
2086 {
2087         struct stmmac_priv *priv = netdev_priv(ndev);
2088         int dis_ic = 0;
2089         unsigned long flags;
2090
2091         if (!ndev || !netif_running(ndev))
2092                 return 0;
2093
2094         if (priv->phydev)
2095                 phy_stop(priv->phydev);
2096
2097         spin_lock_irqsave(&priv->lock, flags);
2098
2099         netif_device_detach(ndev);
2100         netif_stop_queue(ndev);
2101
2102         if (priv->use_riwt)
2103                 dis_ic = 1;
2104
2105         napi_disable(&priv->napi);
2106
2107         /* Stop TX/RX DMA */
2108         priv->hw->dma->stop_tx(priv->ioaddr);
2109         priv->hw->dma->stop_rx(priv->ioaddr);
2110         /* Clear the Rx/Tx descriptors */
2111         priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2112                                      dis_ic);
2113         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2114
2115         /* Enable Power down mode by programming the PMT regs */
2116         if (device_may_wakeup(priv->device))
2117                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2118         else {
2119                 stmmac_set_mac(priv->ioaddr, false);
2120                 /* Disable clock in case of PWM is off */
2121                 clk_disable_unprepare(priv->stmmac_clk);
2122         }
2123         spin_unlock_irqrestore(&priv->lock, flags);
2124         return 0;
2125 }
2126
2127 int stmmac_resume(struct net_device *ndev)
2128 {
2129         struct stmmac_priv *priv = netdev_priv(ndev);
2130         unsigned long flags;
2131
2132         if (!netif_running(ndev))
2133                 return 0;
2134
2135         spin_lock_irqsave(&priv->lock, flags);
2136
2137         /* Power Down bit, into the PM register, is cleared
2138          * automatically as soon as a magic packet or a Wake-up frame
2139          * is received. Anyway, it's better to manually clear
2140          * this bit because it can generate problems while resuming
2141          * from another devices (e.g. serial console). */
2142         if (device_may_wakeup(priv->device))
2143                 priv->hw->mac->pmt(priv->ioaddr, 0);
2144         else
2145                 /* enable the clk prevously disabled */
2146                 clk_prepare_enable(priv->stmmac_clk);
2147
2148         netif_device_attach(ndev);
2149
2150         /* Enable the MAC and DMA */
2151         stmmac_set_mac(priv->ioaddr, true);
2152         priv->hw->dma->start_tx(priv->ioaddr);
2153         priv->hw->dma->start_rx(priv->ioaddr);
2154
2155         napi_enable(&priv->napi);
2156
2157         netif_start_queue(ndev);
2158
2159         spin_unlock_irqrestore(&priv->lock, flags);
2160
2161         if (priv->phydev)
2162                 phy_start(priv->phydev);
2163
2164         return 0;
2165 }
2166
2167 int stmmac_freeze(struct net_device *ndev)
2168 {
2169         if (!ndev || !netif_running(ndev))
2170                 return 0;
2171
2172         return stmmac_release(ndev);
2173 }
2174
2175 int stmmac_restore(struct net_device *ndev)
2176 {
2177         if (!ndev || !netif_running(ndev))
2178                 return 0;
2179
2180         return stmmac_open(ndev);
2181 }
2182 #endif /* CONFIG_PM */
2183
2184 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2185  * depending on the configuration selected.
2186  */
2187 static int __init stmmac_init(void)
2188 {
2189         int ret;
2190
2191         ret = stmmac_register_platform();
2192         if (ret)
2193                 goto err;
2194         ret = stmmac_register_pci();
2195         if (ret)
2196                 goto err_pci;
2197         return 0;
2198 err_pci:
2199         stmmac_unregister_platform();
2200 err:
2201         pr_err("stmmac: driver registration failed\n");
2202         return ret;
2203 }
2204
2205 static void __exit stmmac_exit(void)
2206 {
2207         stmmac_unregister_platform();
2208         stmmac_unregister_pci();
2209 }
2210
2211 module_init(stmmac_init);
2212 module_exit(stmmac_exit);
2213
2214 #ifndef MODULE
2215 static int __init stmmac_cmdline_opt(char *str)
2216 {
2217         char *opt;
2218
2219         if (!str || !*str)
2220                 return -EINVAL;
2221         while ((opt = strsep(&str, ",")) != NULL) {
2222                 if (!strncmp(opt, "debug:", 6)) {
2223                         if (kstrtoint(opt + 6, 0, &debug))
2224                                 goto err;
2225                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2226                         if (kstrtoint(opt + 8, 0, &phyaddr))
2227                                 goto err;
2228                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2229                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2230                                 goto err;
2231                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2232                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2233                                 goto err;
2234                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2235                         if (kstrtoint(opt + 7, 0, &buf_sz))
2236                                 goto err;
2237                 } else if (!strncmp(opt, "tc:", 3)) {
2238                         if (kstrtoint(opt + 3, 0, &tc))
2239                                 goto err;
2240                 } else if (!strncmp(opt, "watchdog:", 9)) {
2241                         if (kstrtoint(opt + 9, 0, &watchdog))
2242                                 goto err;
2243                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2244                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2245                                 goto err;
2246                 } else if (!strncmp(opt, "pause:", 6)) {
2247                         if (kstrtoint(opt + 6, 0, &pause))
2248                                 goto err;
2249                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2250                         if (kstrtoint(opt + 10, 0, &eee_timer))
2251                                 goto err;
2252                 }
2253         }
2254         return 0;
2255
2256 err:
2257         pr_err("%s: ERROR broken module parameter conversion", __func__);
2258         return -EINVAL;
2259 }
2260
2261 __setup("stmmaceth=", stmmac_cmdline_opt);
2262 #endif
2263
2264 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2265 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2266 MODULE_LICENSE("GPL");