drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_STMMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif
  50 #include "stmmac.h"
  51
  52 #undef STMMAC_DEBUG
  53 /*#define STMMAC_DEBUG*/
  54 #ifdef STMMAC_DEBUG
  55 #define DBG(nlevel, klevel, fmt, args...) \
  56                 ((void)(netif_msg_##nlevel(priv) && \
  57                 printk(KERN_##klevel fmt, ## args)))
  58 #else
  59 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  60 #endif
  61
  62 #undef STMMAC_RX_DEBUG
  63 /*#define STMMAC_RX_DEBUG*/
  64 #ifdef STMMAC_RX_DEBUG
  65 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  66 #else
  67 #define RX_DBG(fmt, args...)  do { } while (0)
  68 #endif
  69
  70 #undef STMMAC_XMIT_DEBUG
  71 /*#define STMMAC_XMIT_DEBUG*/
  72 #ifdef STMMAC_XMIT_DEBUG
  73 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  74 #else
  75 #define TX_DBG(fmt, args...)  do { } while (0)
  76 #endif
  77
  78 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  79 #define JUMBO_LEN       9000
  80
  81 /* Module parameters */
  82 #define TX_TIMEO 5000 /* default 5 seconds */
  83 static int watchdog = TX_TIMEO;
  84 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  85 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  86
  87 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  88 module_param(debug, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  90
  91 int phyaddr = -1;
  92 module_param(phyaddr, int, S_IRUGO);
  93 MODULE_PARM_DESC(phyaddr, "Physical device address");
  94
  95 #define DMA_TX_SIZE 256
  96 static int dma_txsize = DMA_TX_SIZE;
  97 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  99
 100 #define DMA_RX_SIZE 256
 101 static int dma_rxsize = DMA_RX_SIZE;
 102 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 103 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 104
 105 static int flow_ctrl = FLOW_OFF;
 106 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 107 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 108
 109 static int pause = PAUSE_TIME;
 110 module_param(pause, int, S_IRUGO | S_IWUSR);
 111 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 112
 113 #define TC_DEFAULT 64
 114 static int tc = TC_DEFAULT;
 115 module_param(tc, int, S_IRUGO | S_IWUSR);
 116 MODULE_PARM_DESC(tc, "DMA threshold control value");
 117
 118 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 119 static int buf_sz = DMA_BUFFER_SIZE;
 120 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 121 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 122
 123 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 124                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 125                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 126
 127 #define STMMAC_DEFAULT_LPI_TIMER        1000
 128 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 129 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 130 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 131 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
 132
 133 /* By default the driver will use the ring mode to manage tx and rx descriptors
 134  * but passing this value so user can force to use the chain instead of the ring
 135  */
 136 static unsigned int chain_mode;
 137 module_param(chain_mode, int, S_IRUGO);
 138 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 139
 140 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 141
 142 #ifdef CONFIG_STMMAC_DEBUG_FS
 143 static int stmmac_init_fs(struct net_device *dev);
 144 static void stmmac_exit_fs(void);
 145 #endif
 146
 147 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 148
 149 /**
 150  * stmmac_verify_args - verify the driver parameters.
 151  * Description: it verifies if some wrong parameter is passed to the driver.
 152  * Note that wrong parameters are replaced with the default values.
 153  */
 154 static void stmmac_verify_args(void)
 155 {
 156         if (unlikely(watchdog < 0))
 157                 watchdog = TX_TIMEO;
 158         if (unlikely(dma_rxsize < 0))
 159                 dma_rxsize = DMA_RX_SIZE;
 160         if (unlikely(dma_txsize < 0))
 161                 dma_txsize = DMA_TX_SIZE;
 162         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 163                 buf_sz = DMA_BUFFER_SIZE;
 164         if (unlikely(flow_ctrl > 1))
 165                 flow_ctrl = FLOW_AUTO;
 166         else if (likely(flow_ctrl < 0))
 167                 flow_ctrl = FLOW_OFF;
 168         if (unlikely((pause < 0) || (pause > 0xffff)))
 169                 pause = PAUSE_TIME;
 170         if (eee_timer < 0)
 171                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 172 }
 173
 174 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 175 {
 176         u32 clk_rate;
 177
 178         clk_rate = clk_get_rate(priv->stmmac_clk);
 179
 180         /* Platform provided default clk_csr would be assumed valid
 181          * for all other cases except for the below mentioned ones. */
 182         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 183                 if (clk_rate < CSR_F_35M)
 184                         priv->clk_csr = STMMAC_CSR_20_35M;
 185                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 186                         priv->clk_csr = STMMAC_CSR_35_60M;
 187                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 188                         priv->clk_csr = STMMAC_CSR_60_100M;
 189                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 190                         priv->clk_csr = STMMAC_CSR_100_150M;
 191                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 192                         priv->clk_csr = STMMAC_CSR_150_250M;
 193                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 194                         priv->clk_csr = STMMAC_CSR_250_300M;
 195         } /* For values higher than the IEEE 802.3 specified frequency
 196            * we can not estimate the proper divider as it is not known
 197            * the frequency of clk_csr_i. So we do not change the default
 198            * divider. */
 199 }
 200
 201 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 202 static void print_pkt(unsigned char *buf, int len)
 203 {
 204         int j;
 205         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 206         for (j = 0; j < len; j++) {
 207                 if ((j % 16) == 0)
 208                         pr_info("\n %03x:", j);
 209                 pr_info(" %02x", buf[j]);
 210         }
 211         pr_info("\n");
 212 }
 213 #endif
 214
 215 /* minimum number of free TX descriptors required to wake up TX process */
 216 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 217
 218 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 219 {
 220         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 221 }
 222
 223 /* On some ST platforms, some HW system configuraton registers have to be
 224  * set according to the link speed negotiated.
 225  */
 226 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 227 {
 228         struct phy_device *phydev = priv->phydev;
 229
 230         if (likely(priv->plat->fix_mac_speed))
 231                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
 232                                           phydev->speed);
 233 }
 234
 235 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 236 {
 237         /* Check and enter in LPI mode */
 238         if ((priv->dirty_tx == priv->cur_tx) &&
 239             (priv->tx_path_in_lpi_mode == false))
 240                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 241 }
 242
 243 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 244 {
 245         /* Exit and disable EEE in case of we are are in LPI state. */
 246         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 247         del_timer_sync(&priv->eee_ctrl_timer);
 248         priv->tx_path_in_lpi_mode = false;
 249 }
 250
 251 /**
 252  * stmmac_eee_ctrl_timer
 253  * @arg : data hook
 254  * Description:
 255  *  If there is no data transfer and if we are not in LPI state,
 256  *  then MAC Transmitter can be moved to LPI state.
 257  */
 258 static void stmmac_eee_ctrl_timer(unsigned long arg)
 259 {
 260         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 261
 262         stmmac_enable_eee_mode(priv);
 263         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 264 }
 265
 266 /**
 267  * stmmac_eee_init
 268  * @priv: private device pointer
 269  * Description:
 270  *  If the EEE support has been enabled while configuring the driver,
 271  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 272  *  phy can also manage EEE, so enable the LPI state and start the timer
 273  *  to verify if the tx path can enter in LPI state.
 274  */
 275 bool stmmac_eee_init(struct stmmac_priv *priv)
 276 {
 277         bool ret = false;
 278
 279         /* MAC core supports the EEE feature. */
 280         if (priv->dma_cap.eee) {
 281                 /* Check if the PHY supports EEE */
 282                 if (phy_init_eee(priv->phydev, 1))
 283                         goto out;
 284
 285                 priv->eee_active = 1;
 286                 init_timer(&priv->eee_ctrl_timer);
 287                 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 288                 priv->eee_ctrl_timer.data = (unsigned long)priv;
 289                 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
 290                 add_timer(&priv->eee_ctrl_timer);
 291
 292                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 293                                              STMMAC_DEFAULT_LIT_LS_TIMER,
 294                                              priv->tx_lpi_timer);
 295
 296                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 297
 298                 ret = true;
 299         }
 300 out:
 301         return ret;
 302 }
 303
 304 static void stmmac_eee_adjust(struct stmmac_priv *priv)
 305 {
 306         /* When the EEE has been already initialised we have to
 307          * modify the PLS bit in the LPI ctrl & status reg according
 308          * to the PHY link status. For this reason.
 309          */
 310         if (priv->eee_enabled)
 311                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 312 }
 313
 314 /**
 315  * stmmac_adjust_link
 316  * @dev: net device structure
 317  * Description: it adjusts the link parameters.
 318  */
 319 static void stmmac_adjust_link(struct net_device *dev)
 320 {
 321         struct stmmac_priv *priv = netdev_priv(dev);
 322         struct phy_device *phydev = priv->phydev;
 323         unsigned long flags;
 324         int new_state = 0;
 325         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 326
 327         if (phydev == NULL)
 328                 return;
 329
 330         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 331             phydev->addr, phydev->link);
 332
 333         spin_lock_irqsave(&priv->lock, flags);
 334
 335         if (phydev->link) {
 336                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 337
 338                 /* Now we make sure that we can be in full duplex mode.
 339                  * If not, we operate in half-duplex mode. */
 340                 if (phydev->duplex != priv->oldduplex) {
 341                         new_state = 1;
 342                         if (!(phydev->duplex))
 343                                 ctrl &= ~priv->hw->link.duplex;
 344                         else
 345                                 ctrl |= priv->hw->link.duplex;
 346                         priv->oldduplex = phydev->duplex;
 347                 }
 348                 /* Flow Control operation */
 349                 if (phydev->pause)
 350                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 351                                                  fc, pause_time);
 352
 353                 if (phydev->speed != priv->speed) {
 354                         new_state = 1;
 355                         switch (phydev->speed) {
 356                         case 1000:
 357                                 if (likely(priv->plat->has_gmac))
 358                                         ctrl &= ~priv->hw->link.port;
 359                                         stmmac_hw_fix_mac_speed(priv);
 360                                 break;
 361                         case 100:
 362                         case 10:
 363                                 if (priv->plat->has_gmac) {
 364                                         ctrl |= priv->hw->link.port;
 365                                         if (phydev->speed == SPEED_100) {
 366                                                 ctrl |= priv->hw->link.speed;
 367                                         } else {
 368                                                 ctrl &= ~(priv->hw->link.speed);
 369                                         }
 370                                 } else {
 371                                         ctrl &= ~priv->hw->link.port;
 372                                 }
 373                                 stmmac_hw_fix_mac_speed(priv);
 374                                 break;
 375                         default:
 376                                 if (netif_msg_link(priv))
 377                                         pr_warning("%s: Speed (%d) is not 10"
 378                                        " or 100!\n", dev->name, phydev->speed);
 379                                 break;
 380                         }
 381
 382                         priv->speed = phydev->speed;
 383                 }
 384
 385                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 386
 387                 if (!priv->oldlink) {
 388                         new_state = 1;
 389                         priv->oldlink = 1;
 390                 }
 391         } else if (priv->oldlink) {
 392                 new_state = 1;
 393                 priv->oldlink = 0;
 394                 priv->speed = 0;
 395                 priv->oldduplex = -1;
 396         }
 397
 398         if (new_state && netif_msg_link(priv))
 399                 phy_print_status(phydev);
 400
 401         stmmac_eee_adjust(priv);
 402
 403         spin_unlock_irqrestore(&priv->lock, flags);
 404
 405         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 406 }
 407
 408 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 409 {
 410         int interface = priv->plat->interface;
 411
 412         if (priv->dma_cap.pcs) {
 413                 if ((interface & PHY_INTERFACE_MODE_RGMII) ||
 414                     (interface & PHY_INTERFACE_MODE_RGMII_ID) ||
 415                     (interface & PHY_INTERFACE_MODE_RGMII_RXID) ||
 416                     (interface & PHY_INTERFACE_MODE_RGMII_TXID)) {
 417                         pr_debug("STMMAC: PCS RGMII support enable\n");
 418                         priv->pcs = STMMAC_PCS_RGMII;
 419                 } else if (interface & PHY_INTERFACE_MODE_SGMII) {
 420                         pr_debug("STMMAC: PCS SGMII support enable\n");
 421                         priv->pcs = STMMAC_PCS_SGMII;
 422                 }
 423         }
 424 }
 425
 426 /**
 427  * stmmac_init_phy - PHY initialization
 428  * @dev: net device structure
 429  * Description: it initializes the driver's PHY state, and attaches the PHY
 430  * to the mac driver.
 431  *  Return value:
 432  *  0 on success
 433  */
 434 static int stmmac_init_phy(struct net_device *dev)
 435 {
 436         struct stmmac_priv *priv = netdev_priv(dev);
 437         struct phy_device *phydev;
 438         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 439         char bus_id[MII_BUS_ID_SIZE];
 440         int interface = priv->plat->interface;
 441         priv->oldlink = 0;
 442         priv->speed = 0;
 443         priv->oldduplex = -1;
 444
 445         if (priv->plat->phy_bus_name)
 446                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 447                                 priv->plat->phy_bus_name, priv->plat->bus_id);
 448         else
 449                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 450                                 priv->plat->bus_id);
 451
 452         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 453                  priv->plat->phy_addr);
 454         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 455
 456         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 457
 458         if (IS_ERR(phydev)) {
 459                 pr_err("%s: Could not attach to PHY\n", dev->name);
 460                 return PTR_ERR(phydev);
 461         }
 462
 463         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 464         if ((interface == PHY_INTERFACE_MODE_MII) ||
 465             (interface == PHY_INTERFACE_MODE_RMII))
 466                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 467                                          SUPPORTED_1000baseT_Full);
 468
 469         /*
 470          * Broken HW is sometimes missing the pull-up resistor on the
 471          * MDIO line, which results in reads to non-existent devices returning
 472          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 473          * device as well.
 474          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 475          */
 476         if (phydev->phy_id == 0) {
 477                 phy_disconnect(phydev);
 478                 return -ENODEV;
 479         }
 480         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 481                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 482
 483         priv->phydev = phydev;
 484
 485         return 0;
 486 }
 487
 488 /**
 489  * stmmac_display_ring
 490  * @p: pointer to the ring.
 491  * @size: size of the ring.
 492  * Description: display the control/status and buffer descriptors.
 493  */
 494 static void stmmac_display_ring(void *head, int size, int extend_desc)
 495 {
 496         int i;
 497         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
 498         struct dma_desc *p = (struct dma_desc *) head;
 499
 500         for (i = 0; i < size; i++) {
 501                 u64 x;
 502                 if (extend_desc) {
 503                         x = *(u64 *) ep;
 504                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 505                                 i, (unsigned int) virt_to_phys(ep),
 506                                 (unsigned int) x, (unsigned int) (x >> 32),
 507                                 ep->basic.des2, ep->basic.des3);
 508                         ep++;
 509                 } else {
 510                         x = *(u64 *) p;
 511                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 512                                 i, (unsigned int) virt_to_phys(p),
 513                                 (unsigned int) x, (unsigned int) (x >> 32),
 514                                 p->des2, p->des3);
 515                         p++;
 516                 }
 517                 pr_info("\n");
 518         }
 519 }
 520
 521 static void stmmac_display_rings(struct stmmac_priv *priv)
 522 {
 523         unsigned int txsize = priv->dma_tx_size;
 524         unsigned int rxsize = priv->dma_rx_size;
 525
 526         if (priv->extend_desc) {
 527                 pr_info("Extended RX descriptor ring:\n");
 528                 stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
 529                 pr_info("Extended TX descriptor ring:\n");
 530                 stmmac_display_ring((void *) priv->dma_etx, txsize, 1);
 531         } else {
 532                 pr_info("RX descriptor ring:\n");
 533                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 534                 pr_info("TX descriptor ring:\n");
 535                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 536         }
 537 }
 538
 539 static int stmmac_set_bfsize(int mtu, int bufsize)
 540 {
 541         int ret = bufsize;
 542
 543         if (mtu >= BUF_SIZE_4KiB)
 544                 ret = BUF_SIZE_8KiB;
 545         else if (mtu >= BUF_SIZE_2KiB)
 546                 ret = BUF_SIZE_4KiB;
 547         else if (mtu >= DMA_BUFFER_SIZE)
 548                 ret = BUF_SIZE_2KiB;
 549         else
 550                 ret = DMA_BUFFER_SIZE;
 551
 552         return ret;
 553 }
 554
 555 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 556 {
 557         int i;
 558         unsigned int txsize = priv->dma_tx_size;
 559         unsigned int rxsize = priv->dma_rx_size;
 560
 561         /* Clear the Rx/Tx descriptors */
 562         for (i = 0; i < rxsize; i++)
 563                 if (priv->extend_desc)
 564                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 565                                                      priv->use_riwt, priv->mode,
 566                                                      (i == rxsize - 1));
 567                 else
 568                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 569                                                      priv->use_riwt, priv->mode,
 570                                                      (i == rxsize - 1));
 571         for (i = 0; i < txsize; i++)
 572                 if (priv->extend_desc)
 573                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 574                                                      priv->mode,
 575                                                      (i == txsize - 1));
 576                 else
 577                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 578                                                      priv->mode,
 579                                                      (i == txsize - 1));
 580 }
 581
 582 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 583                                   int i)
 584 {
 585         struct sk_buff *skb;
 586
 587         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 588                                  GFP_KERNEL);
 589         if (unlikely(skb == NULL)) {
 590                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 591                 return 1;
 592         }
 593         skb_reserve(skb, NET_IP_ALIGN);
 594         priv->rx_skbuff[i] = skb;
 595         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 596                                                 priv->dma_buf_sz,
 597                                                 DMA_FROM_DEVICE);
 598
 599         p->des2 = priv->rx_skbuff_dma[i];
 600
 601         if ((priv->mode == STMMAC_RING_MODE) &&
 602             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 603                 priv->hw->ring->init_desc3(p);
 604
 605         return 0;
 606 }
 607
 608 /**
 609  * init_dma_desc_rings - init the RX/TX descriptor rings
 610  * @dev: net device structure
 611  * Description:  this function initializes the DMA RX/TX descriptors
 612  * and allocates the socket buffers. It suppors the chained and ring
 613  * modes.
 614  */
 615 static void init_dma_desc_rings(struct net_device *dev)
 616 {
 617         int i;
 618         struct stmmac_priv *priv = netdev_priv(dev);
 619         unsigned int txsize = priv->dma_tx_size;
 620         unsigned int rxsize = priv->dma_rx_size;
 621         unsigned int bfsize = 0;
 622
 623         /* Set the max buffer size according to the DESC mode
 624          * and the MTU. Note that RING mode allows 16KiB bsize. */
 625         if (priv->mode == STMMAC_RING_MODE)
 626                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 627
 628         if (bfsize < BUF_SIZE_16KiB)
 629                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 630
 631         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 632             txsize, rxsize, bfsize);
 633
 634         if (priv->extend_desc) {
 635                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
 636                                                    sizeof(struct
 637                                                           dma_extended_desc),
 638                                                    &priv->dma_rx_phy,
 639                                                    GFP_KERNEL);
 640                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
 641                                                    sizeof(struct
 642                                                           dma_extended_desc),
 643                                                    &priv->dma_tx_phy,
 644                                                    GFP_KERNEL);
 645                 if ((!priv->dma_erx) || (!priv->dma_etx))
 646                         return;
 647         } else {
 648                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
 649                                                   sizeof(struct dma_desc),
 650                                                   &priv->dma_rx_phy,
 651                                                   GFP_KERNEL);
 652                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
 653                                                   sizeof(struct dma_desc),
 654                                                   &priv->dma_tx_phy,
 655                                                   GFP_KERNEL);
 656                 if ((!priv->dma_rx) || (!priv->dma_tx))
 657                         return;
 658         }
 659
 660         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
 661                                             GFP_KERNEL);
 662         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
 663                                         GFP_KERNEL);
 664         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
 665                                         GFP_KERNEL);
 666         if (netif_msg_drv(priv))
 667                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
 668                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
 669
 670         /* RX INITIALIZATION */
 671         DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
 672         for (i = 0; i < rxsize; i++) {
 673                 struct dma_desc *p;
 674                 if (priv->extend_desc)
 675                         p = &((priv->dma_erx + i)->basic);
 676                 else
 677                         p = priv->dma_rx + i;
 678
 679                 if (stmmac_init_rx_buffers(priv, p, i))
 680                         break;
 681
 682                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
 683                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
 684         }
 685         priv->cur_rx = 0;
 686         priv->dirty_rx = (unsigned int)(i - rxsize);
 687         priv->dma_buf_sz = bfsize;
 688         buf_sz = bfsize;
 689
 690         /* Setup the chained descriptor addresses */
 691         if (priv->mode == STMMAC_CHAIN_MODE) {
 692                 if (priv->extend_desc) {
 693                         priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
 694                                               rxsize, 1);
 695                         priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
 696                                               txsize, 1);
 697                 } else {
 698                         priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
 699                                               rxsize, 0);
 700                         priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
 701                                               txsize, 0);
 702                 }
 703         }
 704
 705         /* TX INITIALIZATION */
 706         for (i = 0; i < txsize; i++) {
 707                 struct dma_desc *p;
 708                 if (priv->extend_desc)
 709                         p = &((priv->dma_etx + i)->basic);
 710                 else
 711                         p = priv->dma_tx + i;
 712                 p->des2 = 0;
 713                 priv->tx_skbuff[i] = NULL;
 714         }
 715
 716         priv->dirty_tx = 0;
 717         priv->cur_tx = 0;
 718
 719         stmmac_clear_descriptors(priv);
 720
 721         if (netif_msg_hw(priv))
 722                 stmmac_display_rings(priv);
 723 }
 724
 725 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
 726 {
 727         int i;
 728
 729         for (i = 0; i < priv->dma_rx_size; i++) {
 730                 if (priv->rx_skbuff[i]) {
 731                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 732                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
 733                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 734                 }
 735                 priv->rx_skbuff[i] = NULL;
 736         }
 737 }
 738
 739 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
 740 {
 741         int i;
 742
 743         for (i = 0; i < priv->dma_tx_size; i++) {
 744                 if (priv->tx_skbuff[i] != NULL) {
 745                         struct dma_desc *p;
 746                         if (priv->extend_desc)
 747                                 p = &((priv->dma_etx + i)->basic);
 748                         else
 749                                 p = priv->dma_tx + i;
 750
 751                         if (p->des2)
 752                                 dma_unmap_single(priv->device, p->des2,
 753                                                  priv->hw->desc->get_tx_len(p),
 754                                                  DMA_TO_DEVICE);
 755                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 756                         priv->tx_skbuff[i] = NULL;
 757                 }
 758         }
 759 }
 760
 761 static void free_dma_desc_resources(struct stmmac_priv *priv)
 762 {
 763         /* Release the DMA TX/RX socket buffers */
 764         dma_free_rx_skbufs(priv);
 765         dma_free_tx_skbufs(priv);
 766
 767         /* Free the region of consistent memory previously allocated for
 768          * the DMA */
 769         if (!priv->extend_desc) {
 770                 dma_free_coherent(priv->device,
 771                                   priv->dma_tx_size * sizeof(struct dma_desc),
 772                                   priv->dma_tx, priv->dma_tx_phy);
 773                 dma_free_coherent(priv->device,
 774                                   priv->dma_rx_size * sizeof(struct dma_desc),
 775                                   priv->dma_rx, priv->dma_rx_phy);
 776         } else {
 777                 dma_free_coherent(priv->device, priv->dma_tx_size *
 778                                   sizeof(struct dma_extended_desc),
 779                                   priv->dma_etx, priv->dma_tx_phy);
 780                 dma_free_coherent(priv->device, priv->dma_rx_size *
 781                                   sizeof(struct dma_extended_desc),
 782                                   priv->dma_erx, priv->dma_rx_phy);
 783         }
 784         kfree(priv->rx_skbuff_dma);
 785         kfree(priv->rx_skbuff);
 786         kfree(priv->tx_skbuff);
 787 }
 788
 789 /**
 790  *  stmmac_dma_operation_mode - HW DMA operation mode
 791  *  @priv : pointer to the private device structure.
 792  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
 793  *  or Store-And-Forward capability.
 794  */
 795 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 796 {
 797         if (likely(priv->plat->force_sf_dma_mode ||
 798                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
 799                 /*
 800                  * In case of GMAC, SF mode can be enabled
 801                  * to perform the TX COE in HW. This depends on:
 802                  * 1) TX COE if actually supported
 803                  * 2) There is no bugged Jumbo frame support
 804                  *    that needs to not insert csum in the TDES.
 805                  */
 806                 priv->hw->dma->dma_mode(priv->ioaddr,
 807                                         SF_DMA_MODE, SF_DMA_MODE);
 808                 tc = SF_DMA_MODE;
 809         } else
 810                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 811 }
 812
 813 /**
 814  * stmmac_tx_clean:
 815  * @priv: private data pointer
 816  * Description: it reclaims resources after transmission completes.
 817  */
 818 static void stmmac_tx_clean(struct stmmac_priv *priv)
 819 {
 820         unsigned int txsize = priv->dma_tx_size;
 821
 822         spin_lock(&priv->tx_lock);
 823
 824         priv->xstats.tx_clean++;
 825
 826         while (priv->dirty_tx != priv->cur_tx) {
 827                 int last;
 828                 unsigned int entry = priv->dirty_tx % txsize;
 829                 struct sk_buff *skb = priv->tx_skbuff[entry];
 830                 struct dma_desc *p;
 831
 832                 if (priv->extend_desc)
 833                         p = (struct dma_desc *) (priv->dma_etx + entry);
 834                 else
 835                         p = priv->dma_tx + entry;
 836
 837                 /* Check if the descriptor is owned by the DMA. */
 838                 if (priv->hw->desc->get_tx_owner(p))
 839                         break;
 840
 841                 /* Verify tx error by looking at the last segment. */
 842                 last = priv->hw->desc->get_tx_ls(p);
 843                 if (likely(last)) {
 844                         int tx_error =
 845                                 priv->hw->desc->tx_status(&priv->dev->stats,
 846                                                           &priv->xstats, p,
 847                                                           priv->ioaddr);
 848                         if (likely(tx_error == 0)) {
 849                                 priv->dev->stats.tx_packets++;
 850                                 priv->xstats.tx_pkt_n++;
 851                         } else
 852                                 priv->dev->stats.tx_errors++;
 853                 }
 854                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
 855                         priv->cur_tx, priv->dirty_tx);
 856
 857                 if (likely(p->des2))
 858                         dma_unmap_single(priv->device, p->des2,
 859                                          priv->hw->desc->get_tx_len(p),
 860                                          DMA_TO_DEVICE);
 861                 if (priv->mode == STMMAC_RING_MODE)
 862                         priv->hw->ring->clean_desc3(p);
 863
 864                 if (likely(skb != NULL)) {
 865                         dev_kfree_skb(skb);
 866                         priv->tx_skbuff[entry] = NULL;
 867                 }
 868
 869                 priv->hw->desc->release_tx_desc(p, priv->mode);
 870
 871                 priv->dirty_tx++;
 872         }
 873         if (unlikely(netif_queue_stopped(priv->dev) &&
 874                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
 875                 netif_tx_lock(priv->dev);
 876                 if (netif_queue_stopped(priv->dev) &&
 877                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
 878                         TX_DBG("%s: restart transmit\n", __func__);
 879                         netif_wake_queue(priv->dev);
 880                 }
 881                 netif_tx_unlock(priv->dev);
 882         }
 883
 884         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
 885                 stmmac_enable_eee_mode(priv);
 886                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 887         }
 888         spin_unlock(&priv->tx_lock);
 889 }
 890
 891 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
 892 {
 893         priv->hw->dma->enable_dma_irq(priv->ioaddr);
 894 }
 895
 896 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
 897 {
 898         priv->hw->dma->disable_dma_irq(priv->ioaddr);
 899 }
 900
 901
 902 /**
 903  * stmmac_tx_err:
 904  * @priv: pointer to the private device structure
 905  * Description: it cleans the descriptors and restarts the transmission
 906  * in case of errors.
 907  */
 908 static void stmmac_tx_err(struct stmmac_priv *priv)
 909 {
 910         int i;
 911         int txsize = priv->dma_tx_size;
 912         netif_stop_queue(priv->dev);
 913
 914         priv->hw->dma->stop_tx(priv->ioaddr);
 915         dma_free_tx_skbufs(priv);
 916         for (i = 0; i < txsize; i++)
 917                 if (priv->extend_desc)
 918                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 919                                                      priv->mode,
 920                                                      (i == txsize - 1));
 921                 else
 922                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 923                                                      priv->mode,
 924                                                      (i == txsize - 1));
 925         priv->dirty_tx = 0;
 926         priv->cur_tx = 0;
 927         priv->hw->dma->start_tx(priv->ioaddr);
 928
 929         priv->dev->stats.tx_errors++;
 930         netif_wake_queue(priv->dev);
 931 }
 932
 933 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
 934 {
 935         int status;
 936
 937         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
 938         if (likely((status & handle_rx)) || (status & handle_tx)) {
 939                 if (likely(napi_schedule_prep(&priv->napi))) {
 940                         stmmac_disable_dma_irq(priv);
 941                         __napi_schedule(&priv->napi);
 942                 }
 943         }
 944         if (unlikely(status & tx_hard_error_bump_tc)) {
 945                 /* Try to bump up the dma threshold on this failure */
 946                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
 947                         tc += 64;
 948                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 949                         priv->xstats.threshold = tc;
 950                 }
 951         } else if (unlikely(status == tx_hard_error))
 952                 stmmac_tx_err(priv);
 953 }
 954
 955 static void stmmac_mmc_setup(struct stmmac_priv *priv)
 956 {
 957         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
 958                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
 959
 960         /* Mask MMC irq, counters are managed in SW and registers
 961          * are cleared on each READ eventually. */
 962         dwmac_mmc_intr_all_mask(priv->ioaddr);
 963
 964         if (priv->dma_cap.rmon) {
 965                 dwmac_mmc_ctrl(priv->ioaddr, mode);
 966                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
 967         } else
 968                 pr_info(" No MAC Management Counters available\n");
 969 }
 970
 971 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
 972 {
 973         u32 hwid = priv->hw->synopsys_uid;
 974
 975         /* Only check valid Synopsys Id because old MAC chips
 976          * have no HW registers where get the ID */
 977         if (likely(hwid)) {
 978                 u32 uid = ((hwid & 0x0000ff00) >> 8);
 979                 u32 synid = (hwid & 0x000000ff);
 980
 981                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
 982                         uid, synid);
 983
 984                 return synid;
 985         }
 986         return 0;
 987 }
 988
 989 /**
 990  * stmmac_selec_desc_mode
 991  * @priv : private structure
 992  * Description: select the Enhanced/Alternate or Normal descriptors
 993  */
 994 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
 995 {
 996         if (priv->plat->enh_desc) {
 997                 pr_info(" Enhanced/Alternate descriptors\n");
 998
 999                 /* GMAC older than 3.50 has no extended descriptors */
1000                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1001                         pr_info("\tEnabled extended descriptors\n");
1002                         priv->extend_desc = 1;
1003                 } else
1004                         pr_warn("Extended descriptors not supported\n");
1005
1006                 priv->hw->desc = &enh_desc_ops;
1007         } else {
1008                 pr_info(" Normal descriptors\n");
1009                 priv->hw->desc = &ndesc_ops;
1010         }
1011 }
1012
1013 /**
1014  * stmmac_get_hw_features
1015  * @priv : private device pointer
1016  * Description:
1017  *  new GMAC chip generations have a new register to indicate the
1018  *  presence of the optional feature/functions.
1019  *  This can be also used to override the value passed through the
1020  *  platform and necessary for old MAC10/100 and GMAC chips.
1021  */
1022 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1023 {
1024         u32 hw_cap = 0;
1025
1026         if (priv->hw->dma->get_hw_feature) {
1027                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1028
1029                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1030                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1031                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1032                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1033                 priv->dma_cap.multi_addr =
1034                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
1035                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1036                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1037                 priv->dma_cap.pmt_remote_wake_up =
1038                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1039                 priv->dma_cap.pmt_magic_frame =
1040                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1041                 /* MMC */
1042                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1043                 /* IEEE 1588-2002*/
1044                 priv->dma_cap.time_stamp =
1045                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1046                 /* IEEE 1588-2008*/
1047                 priv->dma_cap.atime_stamp =
1048                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1049                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1050                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1051                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1052                 /* TX and RX csum */
1053                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1054                 priv->dma_cap.rx_coe_type1 =
1055                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1056                 priv->dma_cap.rx_coe_type2 =
1057                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1058                 priv->dma_cap.rxfifo_over_2048 =
1059                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1060                 /* TX and RX number of channels */
1061                 priv->dma_cap.number_rx_channel =
1062                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1063                 priv->dma_cap.number_tx_channel =
1064                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1065                 /* Alternate (enhanced) DESC mode*/
1066                 priv->dma_cap.enh_desc =
1067                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1068         }
1069
1070         return hw_cap;
1071 }
1072
1073 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1074 {
1075         /* verify if the MAC address is valid, in case of failures it
1076          * generates a random MAC address */
1077         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1078                 priv->hw->mac->get_umac_addr((void __iomem *)
1079                                              priv->dev->base_addr,
1080                                              priv->dev->dev_addr, 0);
1081                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
1082                         eth_hw_addr_random(priv->dev);
1083         }
1084         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
1085                                                    priv->dev->dev_addr);
1086 }
1087
1088 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1089 {
1090         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1091         int mixed_burst = 0;
1092         int atds = 0;
1093
1094         /* Some DMA parameters can be passed from the platform;
1095          * in case of these are not passed we keep a default
1096          * (good for all the chips) and init the DMA! */
1097         if (priv->plat->dma_cfg) {
1098                 pbl = priv->plat->dma_cfg->pbl;
1099                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1100                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1101                 burst_len = priv->plat->dma_cfg->burst_len;
1102         }
1103
1104         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1105                 atds = 1;
1106
1107         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1108                                    burst_len, priv->dma_tx_phy,
1109                                    priv->dma_rx_phy, atds);
1110 }
1111
1112 /**
1113  * stmmac_tx_timer:
1114  * @data: data pointer
1115  * Description:
1116  * This is the timer handler to directly invoke the stmmac_tx_clean.
1117  */
1118 static void stmmac_tx_timer(unsigned long data)
1119 {
1120         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1121
1122         stmmac_tx_clean(priv);
1123 }
1124
1125 /**
1126  * stmmac_tx_timer:
1127  * @priv: private data structure
1128  * Description:
1129  * This inits the transmit coalesce parameters: i.e. timer rate,
1130  * timer handler and default threshold used for enabling the
1131  * interrupt on completion bit.
1132  */
1133 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1134 {
1135         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1136         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1137         init_timer(&priv->txtimer);
1138         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1139         priv->txtimer.data = (unsigned long)priv;
1140         priv->txtimer.function = stmmac_tx_timer;
1141         add_timer(&priv->txtimer);
1142 }
1143
1144 /**
1145  *  stmmac_open - open entry point of the driver
1146  *  @dev : pointer to the device structure.
1147  *  Description:
1148  *  This function is the open entry point of the driver.
1149  *  Return value:
1150  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1151  *  file on failure.
1152  */
1153 static int stmmac_open(struct net_device *dev)
1154 {
1155         struct stmmac_priv *priv = netdev_priv(dev);
1156         int ret;
1157
1158         clk_prepare_enable(priv->stmmac_clk);
1159
1160         stmmac_check_ether_addr(priv);
1161
1162         if (!priv->pcs) {
1163                 ret = stmmac_init_phy(dev);
1164                 if (ret) {
1165                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1166                                __func__, ret);
1167                         goto open_error;
1168                 }
1169         }
1170
1171         /* Create and initialize the TX/RX descriptors chains. */
1172         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1173         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1174         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1175         init_dma_desc_rings(dev);
1176
1177         /* DMA initialization and SW reset */
1178         ret = stmmac_init_dma_engine(priv);
1179         if (ret < 0) {
1180                 pr_err("%s: DMA initialization failed\n", __func__);
1181                 goto open_error;
1182         }
1183
1184         /* Copy the MAC addr into the HW  */
1185         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1186
1187         /* If required, perform hw setup of the bus. */
1188         if (priv->plat->bus_setup)
1189                 priv->plat->bus_setup(priv->ioaddr);
1190
1191         /* Initialize the MAC Core */
1192         priv->hw->mac->core_init(priv->ioaddr);
1193
1194         /* Request the IRQ lines */
1195         ret = request_irq(dev->irq, stmmac_interrupt,
1196                          IRQF_SHARED, dev->name, dev);
1197         if (unlikely(ret < 0)) {
1198                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1199                        __func__, dev->irq, ret);
1200                 goto open_error;
1201         }
1202
1203         /* Request the Wake IRQ in case of another line is used for WoL */
1204         if (priv->wol_irq != dev->irq) {
1205                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1206                                   IRQF_SHARED, dev->name, dev);
1207                 if (unlikely(ret < 0)) {
1208                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1209                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1210                         goto open_error_wolirq;
1211                 }
1212         }
1213
1214         /* Request the IRQ lines */
1215         if (priv->lpi_irq != -ENXIO) {
1216                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1217                                   dev->name, dev);
1218                 if (unlikely(ret < 0)) {
1219                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1220                                __func__, priv->lpi_irq, ret);
1221                         goto open_error_lpiirq;
1222                 }
1223         }
1224
1225         /* Enable the MAC Rx/Tx */
1226         stmmac_set_mac(priv->ioaddr, true);
1227
1228         /* Set the HW DMA mode and the COE */
1229         stmmac_dma_operation_mode(priv);
1230
1231         /* Extra statistics */
1232         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1233         priv->xstats.threshold = tc;
1234
1235         stmmac_mmc_setup(priv);
1236
1237 #ifdef CONFIG_STMMAC_DEBUG_FS
1238         ret = stmmac_init_fs(dev);
1239         if (ret < 0)
1240                 pr_warning("%s: failed debugFS registration\n", __func__);
1241 #endif
1242         /* Start the ball rolling... */
1243         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1244         priv->hw->dma->start_tx(priv->ioaddr);
1245         priv->hw->dma->start_rx(priv->ioaddr);
1246
1247         /* Dump DMA/MAC registers */
1248         if (netif_msg_hw(priv)) {
1249                 priv->hw->mac->dump_regs(priv->ioaddr);
1250                 priv->hw->dma->dump_regs(priv->ioaddr);
1251         }
1252
1253         if (priv->phydev)
1254                 phy_start(priv->phydev);
1255
1256         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1257
1258         /* Using PCS we cannot dial with the phy registers at this stage
1259          * so we do not support extra feature like EEE.
1260          */
1261         if (!priv->pcs)
1262                 priv->eee_enabled = stmmac_eee_init(priv);
1263
1264         stmmac_init_tx_coalesce(priv);
1265
1266         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1267                 priv->rx_riwt = MAX_DMA_RIWT;
1268                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1269         }
1270
1271         if (priv->pcs && priv->hw->mac->ctrl_ane)
1272                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1273
1274         napi_enable(&priv->napi);
1275         netif_start_queue(dev);
1276
1277         return 0;
1278
1279 open_error_lpiirq:
1280         if (priv->wol_irq != dev->irq)
1281                 free_irq(priv->wol_irq, dev);
1282
1283 open_error_wolirq:
1284         free_irq(dev->irq, dev);
1285
1286 open_error:
1287         if (priv->phydev)
1288                 phy_disconnect(priv->phydev);
1289
1290         clk_disable_unprepare(priv->stmmac_clk);
1291
1292         return ret;
1293 }
1294
1295 /**
1296  *  stmmac_release - close entry point of the driver
1297  *  @dev : device pointer.
1298  *  Description:
1299  *  This is the stop entry point of the driver.
1300  */
1301 static int stmmac_release(struct net_device *dev)
1302 {
1303         struct stmmac_priv *priv = netdev_priv(dev);
1304
1305         if (priv->eee_enabled)
1306                 del_timer_sync(&priv->eee_ctrl_timer);
1307
1308         /* Stop and disconnect the PHY */
1309         if (priv->phydev) {
1310                 phy_stop(priv->phydev);
1311                 phy_disconnect(priv->phydev);
1312                 priv->phydev = NULL;
1313         }
1314
1315         netif_stop_queue(dev);
1316
1317         napi_disable(&priv->napi);
1318
1319         del_timer_sync(&priv->txtimer);
1320
1321         /* Free the IRQ lines */
1322         free_irq(dev->irq, dev);
1323         if (priv->wol_irq != dev->irq)
1324                 free_irq(priv->wol_irq, dev);
1325         if (priv->lpi_irq != -ENXIO)
1326                 free_irq(priv->lpi_irq, dev);
1327
1328         /* Stop TX/RX DMA and clear the descriptors */
1329         priv->hw->dma->stop_tx(priv->ioaddr);
1330         priv->hw->dma->stop_rx(priv->ioaddr);
1331
1332         /* Release and free the Rx/Tx resources */
1333         free_dma_desc_resources(priv);
1334
1335         /* Disable the MAC Rx/Tx */
1336         stmmac_set_mac(priv->ioaddr, false);
1337
1338         netif_carrier_off(dev);
1339
1340 #ifdef CONFIG_STMMAC_DEBUG_FS
1341         stmmac_exit_fs();
1342 #endif
1343         clk_disable_unprepare(priv->stmmac_clk);
1344
1345         return 0;
1346 }
1347
1348 /**
1349  *  stmmac_xmit:
1350  *  @skb : the socket buffer
1351  *  @dev : device pointer
1352  *  Description : Tx entry point of the driver.
1353  */
1354 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1355 {
1356         struct stmmac_priv *priv = netdev_priv(dev);
1357         unsigned int txsize = priv->dma_tx_size;
1358         unsigned int entry;
1359         int i, csum_insertion = 0, is_jumbo = 0;
1360         int nfrags = skb_shinfo(skb)->nr_frags;
1361         struct dma_desc *desc, *first;
1362         unsigned int nopaged_len = skb_headlen(skb);
1363
1364         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1365                 if (!netif_queue_stopped(dev)) {
1366                         netif_stop_queue(dev);
1367                         /* This is a hard error, log it. */
1368                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1369                                 __func__);
1370                 }
1371                 return NETDEV_TX_BUSY;
1372         }
1373
1374         spin_lock(&priv->tx_lock);
1375
1376         if (priv->tx_path_in_lpi_mode)
1377                 stmmac_disable_eee_mode(priv);
1378
1379         entry = priv->cur_tx % txsize;
1380
1381 #ifdef STMMAC_XMIT_DEBUG
1382         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1383                 pr_debug("stmmac xmit: [entry %d]\n"
1384                          "\tskb addr %p - len: %d - nopaged_len: %d\n"
1385                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1386                          "\ttx_count_frames %d\n", entry,
1387                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1388                          !skb_is_gso(skb) ? "isn't" : "is",
1389                          priv->tx_count_frames);
1390 #endif
1391
1392         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1393
1394         if (priv->extend_desc)
1395                 desc = (struct dma_desc *) (priv->dma_etx + entry);
1396         else
1397                 desc = priv->dma_tx + entry;
1398
1399         first = desc;
1400
1401 #ifdef STMMAC_XMIT_DEBUG
1402         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1403                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1404                          "\t\tn_frags: %d, ip_summed: %d\n",
1405                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1406 #endif
1407         priv->tx_skbuff[entry] = skb;
1408
1409         /* To program the descriptors according to the size of the frame */
1410         if (priv->mode == STMMAC_RING_MODE) {
1411                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1412                                                         priv->plat->enh_desc);
1413                 if (unlikely(is_jumbo))
1414                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1415                                                           csum_insertion);
1416         } else {
1417                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1418                                                         priv->plat->enh_desc);
1419                 if (unlikely(is_jumbo))
1420                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1421                                                            csum_insertion);
1422         }
1423         if (likely(!is_jumbo)) {
1424                 desc->des2 = dma_map_single(priv->device, skb->data,
1425                                         nopaged_len, DMA_TO_DEVICE);
1426                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1427                                                 csum_insertion, priv->mode);
1428         } else
1429                 desc = first;
1430
1431         for (i = 0; i < nfrags; i++) {
1432                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1433                 int len = skb_frag_size(frag);
1434
1435                 entry = (++priv->cur_tx) % txsize;
1436                 if (priv->extend_desc)
1437                         desc = (struct dma_desc *) (priv->dma_etx + entry);
1438                 else
1439                         desc = priv->dma_tx + entry;
1440
1441                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1442                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1443                                               DMA_TO_DEVICE);
1444                 priv->tx_skbuff[entry] = NULL;
1445                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1446                                                 priv->mode);
1447                 wmb();
1448                 priv->hw->desc->set_tx_owner(desc);
1449                 wmb();
1450         }
1451
1452         /* Finalize the latest segment. */
1453         priv->hw->desc->close_tx_desc(desc);
1454
1455         wmb();
1456         /* According to the coalesce parameter the IC bit for the latest
1457          * segment could be reset and the timer re-started to invoke the
1458          * stmmac_tx function. This approach takes care about the fragments.
1459          */
1460         priv->tx_count_frames += nfrags + 1;
1461         if (priv->tx_coal_frames > priv->tx_count_frames) {
1462                 priv->hw->desc->clear_tx_ic(desc);
1463                 priv->xstats.tx_reset_ic_bit++;
1464                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1465                        priv->tx_count_frames);
1466                 mod_timer(&priv->txtimer,
1467                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1468         } else
1469                 priv->tx_count_frames = 0;
1470
1471         /* To avoid raise condition */
1472         priv->hw->desc->set_tx_owner(first);
1473         wmb();
1474
1475         priv->cur_tx++;
1476
1477 #ifdef STMMAC_XMIT_DEBUG
1478         if (netif_msg_pktdata(priv)) {
1479                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1480                        "first=%p, nfrags=%d\n",
1481                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1482                        entry, first, nfrags);
1483                 if (priv->extend_desc)
1484                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1485                 else
1486                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1487
1488                 pr_info(">>> frame to be transmitted: ");
1489                 print_pkt(skb->data, skb->len);
1490         }
1491 #endif
1492         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1493                 TX_DBG("%s: stop transmitted packets\n", __func__);
1494                 netif_stop_queue(dev);
1495         }
1496
1497         dev->stats.tx_bytes += skb->len;
1498
1499         skb_tx_timestamp(skb);
1500
1501         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1502
1503         spin_unlock(&priv->tx_lock);
1504
1505         return NETDEV_TX_OK;
1506 }
1507
1508 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1509 {
1510         unsigned int rxsize = priv->dma_rx_size;
1511         int bfsize = priv->dma_buf_sz;
1512
1513         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1514                 unsigned int entry = priv->dirty_rx % rxsize;
1515                 struct dma_desc *p;
1516
1517                 if (priv->extend_desc)
1518                         p = (struct dma_desc *) (priv->dma_erx + entry);
1519                 else
1520                         p = priv->dma_rx + entry;
1521
1522                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1523                         struct sk_buff *skb;
1524
1525                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1526
1527                         if (unlikely(skb == NULL))
1528                                 break;
1529
1530                         priv->rx_skbuff[entry] = skb;
1531                         priv->rx_skbuff_dma[entry] =
1532                             dma_map_single(priv->device, skb->data, bfsize,
1533                                            DMA_FROM_DEVICE);
1534
1535                         p->des2 = priv->rx_skbuff_dma[entry];
1536
1537                         if (unlikely((priv->mode == STMMAC_RING_MODE) &&
1538                                      (priv->plat->has_gmac)))
1539                                 priv->hw->ring->refill_desc3(bfsize, p);
1540
1541                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1542                 }
1543                 wmb();
1544                 priv->hw->desc->set_rx_owner(p);
1545                 wmb();
1546         }
1547 }
1548
1549 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1550 {
1551         unsigned int rxsize = priv->dma_rx_size;
1552         unsigned int entry = priv->cur_rx % rxsize;
1553         unsigned int next_entry;
1554         unsigned int count = 0;
1555
1556 #ifdef STMMAC_RX_DEBUG
1557         if (netif_msg_hw(priv)) {
1558                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1559                 if (priv->extend_desc)
1560                         stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
1561                 else
1562                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
1563         }
1564 #endif
1565         while (count < limit) {
1566                 int status;
1567                 struct dma_desc *p, *p_next;
1568
1569                 if (priv->extend_desc)
1570                         p = (struct dma_desc *) (priv->dma_erx + entry);
1571                 else
1572                         p = priv->dma_rx + entry ;
1573
1574                 if (priv->hw->desc->get_rx_owner(p))
1575                         break;
1576
1577                 count++;
1578
1579                 next_entry = (++priv->cur_rx) % rxsize;
1580                 if (priv->extend_desc)
1581                         p_next = (struct dma_desc *) (priv->dma_erx +
1582                                                       next_entry);
1583                 else
1584                         p_next = priv->dma_rx + next_entry;
1585
1586                 prefetch(p_next);
1587
1588                 /* read the status of the incoming frame */
1589                 status = priv->hw->desc->rx_status(&priv->dev->stats,
1590                                                    &priv->xstats, p);
1591                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
1592                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
1593                                                            &priv->xstats,
1594                                                            priv->dma_erx +
1595                                                            entry);
1596                 if (unlikely(status == discard_frame))
1597                         priv->dev->stats.rx_errors++;
1598                 else {
1599                         struct sk_buff *skb;
1600                         int frame_len;
1601
1602                         frame_len = priv->hw->desc->get_rx_frame_len(p,
1603                                         priv->plat->rx_coe);
1604                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1605                          * Type frames (LLC/LLC-SNAP) */
1606                         if (unlikely(status != llc_snap))
1607                                 frame_len -= ETH_FCS_LEN;
1608 #ifdef STMMAC_RX_DEBUG
1609                         if (frame_len > ETH_FRAME_LEN)
1610                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1611                                         frame_len, status);
1612
1613                         if (netif_msg_hw(priv))
1614                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1615                                         p, entry, p->des2);
1616 #endif
1617                         skb = priv->rx_skbuff[entry];
1618                         if (unlikely(!skb)) {
1619                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1620                                         priv->dev->name);
1621                                 priv->dev->stats.rx_dropped++;
1622                                 break;
1623                         }
1624                         prefetch(skb->data - NET_IP_ALIGN);
1625                         priv->rx_skbuff[entry] = NULL;
1626
1627                         skb_put(skb, frame_len);
1628                         dma_unmap_single(priv->device,
1629                                          priv->rx_skbuff_dma[entry],
1630                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1631 #ifdef STMMAC_RX_DEBUG
1632                         if (netif_msg_pktdata(priv)) {
1633                                 pr_info(" frame received (%dbytes)", frame_len);
1634                                 print_pkt(skb->data, frame_len);
1635                         }
1636 #endif
1637                         skb->protocol = eth_type_trans(skb, priv->dev);
1638
1639                         if (unlikely(!priv->plat->rx_coe))
1640                                 skb_checksum_none_assert(skb);
1641                         else
1642                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1643
1644                         napi_gro_receive(&priv->napi, skb);
1645
1646                         priv->dev->stats.rx_packets++;
1647                         priv->dev->stats.rx_bytes += frame_len;
1648                 }
1649                 entry = next_entry;
1650         }
1651
1652         stmmac_rx_refill(priv);
1653
1654         priv->xstats.rx_pkt_n += count;
1655
1656         return count;
1657 }
1658
1659 /**
1660  *  stmmac_poll - stmmac poll method (NAPI)
1661  *  @napi : pointer to the napi structure.
1662  *  @budget : maximum number of packets that the current CPU can receive from
1663  *            all interfaces.
1664  *  Description :
1665  *  To look at the incoming frames and clear the tx resources.
1666  */
1667 static int stmmac_poll(struct napi_struct *napi, int budget)
1668 {
1669         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1670         int work_done = 0;
1671
1672         priv->xstats.napi_poll++;
1673         stmmac_tx_clean(priv);
1674
1675         work_done = stmmac_rx(priv, budget);
1676         if (work_done < budget) {
1677                 napi_complete(napi);
1678                 stmmac_enable_dma_irq(priv);
1679         }
1680         return work_done;
1681 }
1682
1683 /**
1684  *  stmmac_tx_timeout
1685  *  @dev : Pointer to net device structure
1686  *  Description: this function is called when a packet transmission fails to
1687  *   complete within a reasonable time. The driver will mark the error in the
1688  *   netdev structure and arrange for the device to be reset to a sane state
1689  *   in order to transmit a new packet.
1690  */
1691 static void stmmac_tx_timeout(struct net_device *dev)
1692 {
1693         struct stmmac_priv *priv = netdev_priv(dev);
1694
1695         /* Clear Tx resources and restart transmitting again */
1696         stmmac_tx_err(priv);
1697 }
1698
1699 /* Configuration changes (passed on by ifconfig) */
1700 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1701 {
1702         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1703                 return -EBUSY;
1704
1705         /* Don't allow changing the I/O address */
1706         if (map->base_addr != dev->base_addr) {
1707                 pr_warning("%s: can't change I/O address\n", dev->name);
1708                 return -EOPNOTSUPP;
1709         }
1710
1711         /* Don't allow changing the IRQ */
1712         if (map->irq != dev->irq) {
1713                 pr_warning("%s: can't change IRQ number %d\n",
1714                        dev->name, dev->irq);
1715                 return -EOPNOTSUPP;
1716         }
1717
1718         /* ignore other fields */
1719         return 0;
1720 }
1721
1722 /**
1723  *  stmmac_set_rx_mode - entry point for multicast addressing
1724  *  @dev : pointer to the device structure
1725  *  Description:
1726  *  This function is a driver entry point which gets called by the kernel
1727  *  whenever multicast addresses must be enabled/disabled.
1728  *  Return value:
1729  *  void.
1730  */
1731 static void stmmac_set_rx_mode(struct net_device *dev)
1732 {
1733         struct stmmac_priv *priv = netdev_priv(dev);
1734
1735         spin_lock(&priv->lock);
1736         priv->hw->mac->set_filter(dev, priv->synopsys_id);
1737         spin_unlock(&priv->lock);
1738 }
1739
1740 /**
1741  *  stmmac_change_mtu - entry point to change MTU size for the device.
1742  *  @dev : device pointer.
1743  *  @new_mtu : the new MTU size for the device.
1744  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1745  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1746  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1747  *  Return value:
1748  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1749  *  file on failure.
1750  */
1751 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1752 {
1753         struct stmmac_priv *priv = netdev_priv(dev);
1754         int max_mtu;
1755
1756         if (netif_running(dev)) {
1757                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1758                 return -EBUSY;
1759         }
1760
1761         if (priv->plat->enh_desc)
1762                 max_mtu = JUMBO_LEN;
1763         else
1764                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1765
1766         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1767                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1768                 return -EINVAL;
1769         }
1770
1771         dev->mtu = new_mtu;
1772         netdev_update_features(dev);
1773
1774         return 0;
1775 }
1776
1777 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1778         netdev_features_t features)
1779 {
1780         struct stmmac_priv *priv = netdev_priv(dev);
1781
1782         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
1783                 features &= ~NETIF_F_RXCSUM;
1784         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
1785                 features &= ~NETIF_F_IPV6_CSUM;
1786         if (!priv->plat->tx_coe)
1787                 features &= ~NETIF_F_ALL_CSUM;
1788
1789         /* Some GMAC devices have a bugged Jumbo frame support that
1790          * needs to have the Tx COE disabled for oversized frames
1791          * (due to limited buffer sizes). In this case we disable
1792          * the TX csum insertionin the TDES and not use SF. */
1793         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1794                 features &= ~NETIF_F_ALL_CSUM;
1795
1796         return features;
1797 }
1798
1799 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1800 {
1801         struct net_device *dev = (struct net_device *)dev_id;
1802         struct stmmac_priv *priv = netdev_priv(dev);
1803
1804         if (unlikely(!dev)) {
1805                 pr_err("%s: invalid dev pointer\n", __func__);
1806                 return IRQ_NONE;
1807         }
1808
1809         /* To handle GMAC own interrupts */
1810         if (priv->plat->has_gmac) {
1811                 int status = priv->hw->mac->host_irq_status((void __iomem *)
1812                                                             dev->base_addr,
1813                                                             &priv->xstats);
1814                 if (unlikely(status)) {
1815                         /* For LPI we need to save the tx status */
1816                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
1817                                 priv->tx_path_in_lpi_mode = true;
1818                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
1819                                 priv->tx_path_in_lpi_mode = false;
1820                 }
1821         }
1822
1823         /* To handle DMA interrupts */
1824         stmmac_dma_interrupt(priv);
1825
1826         return IRQ_HANDLED;
1827 }
1828
1829 #ifdef CONFIG_NET_POLL_CONTROLLER
1830 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1831  * to allow network I/O with interrupts disabled. */
1832 static void stmmac_poll_controller(struct net_device *dev)
1833 {
1834         disable_irq(dev->irq);
1835         stmmac_interrupt(dev->irq, dev);
1836         enable_irq(dev->irq);
1837 }
1838 #endif
1839
1840 /**
1841  *  stmmac_ioctl - Entry point for the Ioctl
1842  *  @dev: Device pointer.
1843  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1844  *  a proprietary structure used to pass information to the driver.
1845  *  @cmd: IOCTL command
1846  *  Description:
1847  *  Currently there are no special functionality supported in IOCTL, just the
1848  *  phy_mii_ioctl(...) can be invoked.
1849  */
1850 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1851 {
1852         struct stmmac_priv *priv = netdev_priv(dev);
1853         int ret;
1854
1855         if (!netif_running(dev))
1856                 return -EINVAL;
1857
1858         if (!priv->phydev)
1859                 return -EINVAL;
1860
1861         ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1862
1863         return ret;
1864 }
1865
1866 #ifdef CONFIG_STMMAC_DEBUG_FS
1867 static struct dentry *stmmac_fs_dir;
1868 static struct dentry *stmmac_rings_status;
1869 static struct dentry *stmmac_dma_cap;
1870
1871 static void sysfs_display_ring(void *head, int size, int extend_desc,
1872                                 struct seq_file *seq)
1873 {
1874         int i;
1875         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
1876         struct dma_desc *p = (struct dma_desc *) head;
1877
1878         for (i = 0; i < size; i++) {
1879                 u64 x;
1880                 if (extend_desc) {
1881                         x = *(u64 *) ep;
1882                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
1883                                    i, (unsigned int) virt_to_phys(ep),
1884                                    (unsigned int) x, (unsigned int) (x >> 32),
1885                                    ep->basic.des2, ep->basic.des3);
1886                         ep++;
1887                 } else {
1888                         x = *(u64 *) p;
1889                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
1890                                    i, (unsigned int) virt_to_phys(ep),
1891                                    (unsigned int) x, (unsigned int) (x >> 32),
1892                                    p->des2, p->des3);
1893                         p++;
1894                 }
1895                 seq_printf(seq, "\n");
1896         }
1897 }
1898
1899 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1900 {
1901         struct net_device *dev = seq->private;
1902         struct stmmac_priv *priv = netdev_priv(dev);
1903         unsigned int txsize = priv->dma_tx_size;
1904         unsigned int rxsize = priv->dma_rx_size;
1905
1906         if (priv->extend_desc) {
1907                 seq_printf(seq, "Extended RX descriptor ring:\n");
1908                 sysfs_display_ring((void *) priv->dma_erx, rxsize, 1, seq);
1909                 seq_printf(seq, "Extended TX descriptor ring:\n");
1910                 sysfs_display_ring((void *) priv->dma_etx, txsize, 1, seq);
1911         } else {
1912                 seq_printf(seq, "RX descriptor ring:\n");
1913                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
1914                 seq_printf(seq, "TX descriptor ring:\n");
1915                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
1916         }
1917
1918         return 0;
1919 }
1920
1921 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1922 {
1923         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1924 }
1925
1926 static const struct file_operations stmmac_rings_status_fops = {
1927         .owner = THIS_MODULE,
1928         .open = stmmac_sysfs_ring_open,
1929         .read = seq_read,
1930         .llseek = seq_lseek,
1931         .release = single_release,
1932 };
1933
1934 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1935 {
1936         struct net_device *dev = seq->private;
1937         struct stmmac_priv *priv = netdev_priv(dev);
1938
1939         if (!priv->hw_cap_support) {
1940                 seq_printf(seq, "DMA HW features not supported\n");
1941                 return 0;
1942         }
1943
1944         seq_printf(seq, "==============================\n");
1945         seq_printf(seq, "\tDMA HW features\n");
1946         seq_printf(seq, "==============================\n");
1947
1948         seq_printf(seq, "\t10/100 Mbps %s\n",
1949                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1950         seq_printf(seq, "\t1000 Mbps %s\n",
1951                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
1952         seq_printf(seq, "\tHalf duple %s\n",
1953                    (priv->dma_cap.half_duplex) ? "Y" : "N");
1954         seq_printf(seq, "\tHash Filter: %s\n",
1955                    (priv->dma_cap.hash_filter) ? "Y" : "N");
1956         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1957                    (priv->dma_cap.multi_addr) ? "Y" : "N");
1958         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1959                    (priv->dma_cap.pcs) ? "Y" : "N");
1960         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1961                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
1962         seq_printf(seq, "\tPMT Remote wake up: %s\n",
1963                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1964         seq_printf(seq, "\tPMT Magic Frame: %s\n",
1965                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1966         seq_printf(seq, "\tRMON module: %s\n",
1967                    (priv->dma_cap.rmon) ? "Y" : "N");
1968         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1969                    (priv->dma_cap.time_stamp) ? "Y" : "N");
1970         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1971                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
1972         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1973                    (priv->dma_cap.eee) ? "Y" : "N");
1974         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1975         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1976                    (priv->dma_cap.tx_coe) ? "Y" : "N");
1977         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1978                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1979         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1980                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1981         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1982                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1983         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1984                    priv->dma_cap.number_rx_channel);
1985         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1986                    priv->dma_cap.number_tx_channel);
1987         seq_printf(seq, "\tEnhanced descriptors: %s\n",
1988                    (priv->dma_cap.enh_desc) ? "Y" : "N");
1989
1990         return 0;
1991 }
1992
1993 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1994 {
1995         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1996 }
1997
1998 static const struct file_operations stmmac_dma_cap_fops = {
1999         .owner = THIS_MODULE,
2000         .open = stmmac_sysfs_dma_cap_open,
2001         .read = seq_read,
2002         .llseek = seq_lseek,
2003         .release = single_release,
2004 };
2005
2006 static int stmmac_init_fs(struct net_device *dev)
2007 {
2008         /* Create debugfs entries */
2009         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2010
2011         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2012                 pr_err("ERROR %s, debugfs create directory failed\n",
2013                        STMMAC_RESOURCE_NAME);
2014
2015                 return -ENOMEM;
2016         }
2017
2018         /* Entry to report DMA RX/TX rings */
2019         stmmac_rings_status = debugfs_create_file("descriptors_status",
2020                                            S_IRUGO, stmmac_fs_dir, dev,
2021                                            &stmmac_rings_status_fops);
2022
2023         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2024                 pr_info("ERROR creating stmmac ring debugfs file\n");
2025                 debugfs_remove(stmmac_fs_dir);
2026
2027                 return -ENOMEM;
2028         }
2029
2030         /* Entry to report the DMA HW features */
2031         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2032                                              dev, &stmmac_dma_cap_fops);
2033
2034         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2035                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2036                 debugfs_remove(stmmac_rings_status);
2037                 debugfs_remove(stmmac_fs_dir);
2038
2039                 return -ENOMEM;
2040         }
2041
2042         return 0;
2043 }
2044
2045 static void stmmac_exit_fs(void)
2046 {
2047         debugfs_remove(stmmac_rings_status);
2048         debugfs_remove(stmmac_dma_cap);
2049         debugfs_remove(stmmac_fs_dir);
2050 }
2051 #endif /* CONFIG_STMMAC_DEBUG_FS */
2052
2053 static const struct net_device_ops stmmac_netdev_ops = {
2054         .ndo_open = stmmac_open,
2055         .ndo_start_xmit = stmmac_xmit,
2056         .ndo_stop = stmmac_release,
2057         .ndo_change_mtu = stmmac_change_mtu,
2058         .ndo_fix_features = stmmac_fix_features,
2059         .ndo_set_rx_mode = stmmac_set_rx_mode,
2060         .ndo_tx_timeout = stmmac_tx_timeout,
2061         .ndo_do_ioctl = stmmac_ioctl,
2062         .ndo_set_config = stmmac_config,
2063 #ifdef CONFIG_NET_POLL_CONTROLLER
2064         .ndo_poll_controller = stmmac_poll_controller,
2065 #endif
2066         .ndo_set_mac_address = eth_mac_addr,
2067 };
2068
2069 /**
2070  *  stmmac_hw_init - Init the MAC device
2071  *  @priv : pointer to the private device structure.
2072  *  Description: this function detects which MAC device
2073  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2074  *  (if supported) and sets the driver's features (for example
2075  *  to use the ring or chaine mode or support the normal/enh
2076  *  descriptor structure).
2077  */
2078 static int stmmac_hw_init(struct stmmac_priv *priv)
2079 {
2080         int ret;
2081         struct mac_device_info *mac;
2082
2083         /* Identify the MAC HW device */
2084         if (priv->plat->has_gmac) {
2085                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2086                 mac = dwmac1000_setup(priv->ioaddr);
2087         } else {
2088                 mac = dwmac100_setup(priv->ioaddr);
2089         }
2090         if (!mac)
2091                 return -ENOMEM;
2092
2093         priv->hw = mac;
2094
2095         /* Get and dump the chip ID */
2096         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2097
2098         /* To use alternate (extended) or normal descriptor structures */
2099         stmmac_selec_desc_mode(priv);
2100
2101         /* To use the chained or ring mode */
2102         if (chain_mode) {
2103                 priv->hw->chain = &chain_mode_ops;
2104                 pr_info(" Chain mode enabled\n");
2105                 priv->mode = STMMAC_CHAIN_MODE;
2106         } else {
2107                 priv->hw->ring = &ring_mode_ops;
2108                 pr_info(" Ring mode enabled\n");
2109                 priv->mode = STMMAC_RING_MODE;
2110         }
2111
2112         /* Get the HW capability (new GMAC newer than 3.50a) */
2113         priv->hw_cap_support = stmmac_get_hw_features(priv);
2114         if (priv->hw_cap_support) {
2115                 pr_info(" DMA HW capability register supported");
2116
2117                 /* We can override some gmac/dma configuration fields: e.g.
2118                  * enh_desc, tx_coe (e.g. that are passed through the
2119                  * platform) with the values from the HW capability
2120                  * register (if supported).
2121                  */
2122                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2123                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2124
2125                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2126
2127                 if (priv->dma_cap.rx_coe_type2)
2128                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2129                 else if (priv->dma_cap.rx_coe_type1)
2130                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2131
2132         } else
2133                 pr_info(" No HW DMA feature register supported");
2134
2135         /* Enable the IPC (Checksum Offload) and check if the feature has been
2136          * enabled during the core configuration. */
2137         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2138         if (!ret) {
2139                 pr_warning(" RX IPC Checksum Offload not configured.\n");
2140                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2141         }
2142
2143         if (priv->plat->rx_coe)
2144                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2145                         priv->plat->rx_coe);
2146         if (priv->plat->tx_coe)
2147                 pr_info(" TX Checksum insertion supported\n");
2148
2149         if (priv->plat->pmt) {
2150                 pr_info(" Wake-Up On Lan supported\n");
2151                 device_set_wakeup_capable(priv->device, 1);
2152         }
2153
2154         return 0;
2155 }
2156
2157 /**
2158  * stmmac_dvr_probe
2159  * @device: device pointer
2160  * @plat_dat: platform data pointer
2161  * @addr: iobase memory address
2162  * Description: this is the main probe function used to
2163  * call the alloc_etherdev, allocate the priv structure.
2164  */
2165 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2166                                      struct plat_stmmacenet_data *plat_dat,
2167                                      void __iomem *addr)
2168 {
2169         int ret = 0;
2170         struct net_device *ndev = NULL;
2171         struct stmmac_priv *priv;
2172
2173         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2174         if (!ndev)
2175                 return NULL;
2176
2177         SET_NETDEV_DEV(ndev, device);
2178
2179         priv = netdev_priv(ndev);
2180         priv->device = device;
2181         priv->dev = ndev;
2182
2183         ether_setup(ndev);
2184
2185         stmmac_set_ethtool_ops(ndev);
2186         priv->pause = pause;
2187         priv->plat = plat_dat;
2188         priv->ioaddr = addr;
2189         priv->dev->base_addr = (unsigned long)addr;
2190
2191         /* Verify driver arguments */
2192         stmmac_verify_args();
2193
2194         /* Override with kernel parameters if supplied XXX CRS XXX
2195          * this needs to have multiple instances */
2196         if ((phyaddr >= 0) && (phyaddr <= 31))
2197                 priv->plat->phy_addr = phyaddr;
2198
2199         /* Init MAC and get the capabilities */
2200         ret = stmmac_hw_init(priv);
2201         if (ret)
2202                 goto error_free_netdev;
2203
2204         ndev->netdev_ops = &stmmac_netdev_ops;
2205
2206         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2207                             NETIF_F_RXCSUM;
2208         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2209         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2210 #ifdef STMMAC_VLAN_TAG_USED
2211         /* Both mac100 and gmac support receive VLAN tag detection */
2212         ndev->features |= NETIF_F_HW_VLAN_RX;
2213 #endif
2214         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2215
2216         if (flow_ctrl)
2217                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2218
2219         /* Rx Watchdog is available in the COREs newer than the 3.40.
2220          * In some case, for example on bugged HW this feature
2221          * has to be disable and this can be done by passing the
2222          * riwt_off field from the platform.
2223          */
2224         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2225                 priv->use_riwt = 1;
2226                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2227         }
2228
2229         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2230
2231         spin_lock_init(&priv->lock);
2232         spin_lock_init(&priv->tx_lock);
2233
2234         ret = register_netdev(ndev);
2235         if (ret) {
2236                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2237                 goto error_netdev_register;
2238         }
2239
2240         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2241         if (IS_ERR(priv->stmmac_clk)) {
2242                 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2243                 goto error_clk_get;
2244         }
2245
2246         /* If a specific clk_csr value is passed from the platform
2247          * this means that the CSR Clock Range selection cannot be
2248          * changed at run-time and it is fixed. Viceversa the driver'll try to
2249          * set the MDC clock dynamically according to the csr actual
2250          * clock input.
2251          */
2252         if (!priv->plat->clk_csr)
2253                 stmmac_clk_csr_set(priv);
2254         else
2255                 priv->clk_csr = priv->plat->clk_csr;
2256
2257         stmmac_check_pcs_mode(priv);
2258
2259         if (!priv->pcs) {
2260                 /* MDIO bus Registration */
2261                 ret = stmmac_mdio_register(ndev);
2262                 if (ret < 0) {
2263                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2264                                  __func__, priv->plat->bus_id);
2265                         goto error_mdio_register;
2266                 }
2267         }
2268
2269         return priv;
2270
2271 error_mdio_register:
2272         clk_put(priv->stmmac_clk);
2273 error_clk_get:
2274         unregister_netdev(ndev);
2275 error_netdev_register:
2276         netif_napi_del(&priv->napi);
2277 error_free_netdev:
2278         free_netdev(ndev);
2279
2280         return NULL;
2281 }
2282
2283 /**
2284  * stmmac_dvr_remove
2285  * @ndev: net device pointer
2286  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2287  * changes the link status, releases the DMA descriptor rings.
2288  */
2289 int stmmac_dvr_remove(struct net_device *ndev)
2290 {
2291         struct stmmac_priv *priv = netdev_priv(ndev);
2292
2293         pr_info("%s:\n\tremoving driver", __func__);
2294
2295         priv->hw->dma->stop_rx(priv->ioaddr);
2296         priv->hw->dma->stop_tx(priv->ioaddr);
2297
2298         stmmac_set_mac(priv->ioaddr, false);
2299         if (!priv->pcs)
2300                 stmmac_mdio_unregister(ndev);
2301         netif_carrier_off(ndev);
2302         unregister_netdev(ndev);
2303         free_netdev(ndev);
2304
2305         return 0;
2306 }
2307
2308 #ifdef CONFIG_PM
2309 int stmmac_suspend(struct net_device *ndev)
2310 {
2311         struct stmmac_priv *priv = netdev_priv(ndev);
2312         unsigned long flags;
2313
2314         if (!ndev || !netif_running(ndev))
2315                 return 0;
2316
2317         if (priv->phydev)
2318                 phy_stop(priv->phydev);
2319
2320         spin_lock_irqsave(&priv->lock, flags);
2321
2322         netif_device_detach(ndev);
2323         netif_stop_queue(ndev);
2324
2325         napi_disable(&priv->napi);
2326
2327         /* Stop TX/RX DMA */
2328         priv->hw->dma->stop_tx(priv->ioaddr);
2329         priv->hw->dma->stop_rx(priv->ioaddr);
2330
2331         stmmac_clear_descriptors(priv);
2332
2333         /* Enable Power down mode by programming the PMT regs */
2334         if (device_may_wakeup(priv->device))
2335                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2336         else {
2337                 stmmac_set_mac(priv->ioaddr, false);
2338                 /* Disable clock in case of PWM is off */
2339                 clk_disable_unprepare(priv->stmmac_clk);
2340         }
2341         spin_unlock_irqrestore(&priv->lock, flags);
2342         return 0;
2343 }
2344
2345 int stmmac_resume(struct net_device *ndev)
2346 {
2347         struct stmmac_priv *priv = netdev_priv(ndev);
2348         unsigned long flags;
2349
2350         if (!netif_running(ndev))
2351                 return 0;
2352
2353         spin_lock_irqsave(&priv->lock, flags);
2354
2355         /* Power Down bit, into the PM register, is cleared
2356          * automatically as soon as a magic packet or a Wake-up frame
2357          * is received. Anyway, it's better to manually clear
2358          * this bit because it can generate problems while resuming
2359          * from another devices (e.g. serial console). */
2360         if (device_may_wakeup(priv->device))
2361                 priv->hw->mac->pmt(priv->ioaddr, 0);
2362         else
2363                 /* enable the clk prevously disabled */
2364                 clk_prepare_enable(priv->stmmac_clk);
2365
2366         netif_device_attach(ndev);
2367
2368         /* Enable the MAC and DMA */
2369         stmmac_set_mac(priv->ioaddr, true);
2370         priv->hw->dma->start_tx(priv->ioaddr);
2371         priv->hw->dma->start_rx(priv->ioaddr);
2372
2373         napi_enable(&priv->napi);
2374
2375         netif_start_queue(ndev);
2376
2377         spin_unlock_irqrestore(&priv->lock, flags);
2378
2379         if (priv->phydev)
2380                 phy_start(priv->phydev);
2381
2382         return 0;
2383 }
2384
2385 int stmmac_freeze(struct net_device *ndev)
2386 {
2387         if (!ndev || !netif_running(ndev))
2388                 return 0;
2389
2390         return stmmac_release(ndev);
2391 }
2392
2393 int stmmac_restore(struct net_device *ndev)
2394 {
2395         if (!ndev || !netif_running(ndev))
2396                 return 0;
2397
2398         return stmmac_open(ndev);
2399 }
2400 #endif /* CONFIG_PM */
2401
2402 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2403  * depending on the configuration selected.
2404  */
2405 static int __init stmmac_init(void)
2406 {
2407         int ret;
2408
2409         ret = stmmac_register_platform();
2410         if (ret)
2411                 goto err;
2412         ret = stmmac_register_pci();
2413         if (ret)
2414                 goto err_pci;
2415         return 0;
2416 err_pci:
2417         stmmac_unregister_platform();
2418 err:
2419         pr_err("stmmac: driver registration failed\n");
2420         return ret;
2421 }
2422
2423 static void __exit stmmac_exit(void)
2424 {
2425         stmmac_unregister_platform();
2426         stmmac_unregister_pci();
2427 }
2428
2429 module_init(stmmac_init);
2430 module_exit(stmmac_exit);
2431
2432 #ifndef MODULE
2433 static int __init stmmac_cmdline_opt(char *str)
2434 {
2435         char *opt;
2436
2437         if (!str || !*str)
2438                 return -EINVAL;
2439         while ((opt = strsep(&str, ",")) != NULL) {
2440                 if (!strncmp(opt, "debug:", 6)) {
2441                         if (kstrtoint(opt + 6, 0, &debug))
2442                                 goto err;
2443                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2444                         if (kstrtoint(opt + 8, 0, &phyaddr))
2445                                 goto err;
2446                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2447                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2448                                 goto err;
2449                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2450                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2451                                 goto err;
2452                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2453                         if (kstrtoint(opt + 7, 0, &buf_sz))
2454                                 goto err;
2455                 } else if (!strncmp(opt, "tc:", 3)) {
2456                         if (kstrtoint(opt + 3, 0, &tc))
2457                                 goto err;
2458                 } else if (!strncmp(opt, "watchdog:", 9)) {
2459                         if (kstrtoint(opt + 9, 0, &watchdog))
2460                                 goto err;
2461                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2462                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2463                                 goto err;
2464                 } else if (!strncmp(opt, "pause:", 6)) {
2465                         if (kstrtoint(opt + 6, 0, &pause))
2466                                 goto err;
2467                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2468                         if (kstrtoint(opt + 10, 0, &eee_timer))
2469                                 goto err;
2470                 } else if (!strncmp(opt, "chain_mode:", 11)) {
2471                         if (kstrtoint(opt + 11, 0, &chain_mode))
2472                                 goto err;
2473                 }
2474         }
2475         return 0;
2476
2477 err:
2478         pr_err("%s: ERROR broken module parameter conversion", __func__);
2479         return -EINVAL;
2480 }
2481
2482 __setup("stmmaceth=", stmmac_cmdline_opt);
2483 #endif
2484
2485 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2486 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2487 MODULE_LICENSE("GPL");