drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include "cpsw.h"
  40 #include "cpsw_ale.h"
  41 #include "cpts.h"
  42 #include "davinci_cpdma.h"
  43
  44 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  45                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  46                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  47                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  48                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  49                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  50                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  51                          NETIF_MSG_RX_STATUS)
  52
  53 #define cpsw_info(priv, type, format, ...)              \
  54 do {                                                            \
  55         if (netif_msg_##type(priv) && net_ratelimit())          \
  56                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  57 } while (0)
  58
  59 #define cpsw_err(priv, type, format, ...)               \
  60 do {                                                            \
  61         if (netif_msg_##type(priv) && net_ratelimit())          \
  62                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  63 } while (0)
  64
  65 #define cpsw_dbg(priv, type, format, ...)               \
  66 do {                                                            \
  67         if (netif_msg_##type(priv) && net_ratelimit())          \
  68                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  69 } while (0)
  70
  71 #define cpsw_notice(priv, type, format, ...)            \
  72 do {                                                            \
  73         if (netif_msg_##type(priv) && net_ratelimit())          \
  74                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  75 } while (0)
  76
  77 #define ALE_ALL_PORTS           0x7
  78
  79 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  80 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  81 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  82
  83 #define CPSW_VERSION_1          0x19010a
  84 #define CPSW_VERSION_2          0x19010c
  85 #define CPSW_VERSION_3          0x19010f
  86 #define CPSW_VERSION_4          0x190112
  87
  88 #define HOST_PORT_NUM           0
  89 #define SLIVER_SIZE             0x40
  90
  91 #define CPSW1_HOST_PORT_OFFSET  0x028
  92 #define CPSW1_SLAVE_OFFSET      0x050
  93 #define CPSW1_SLAVE_SIZE        0x040
  94 #define CPSW1_CPDMA_OFFSET      0x100
  95 #define CPSW1_STATERAM_OFFSET   0x200
  96 #define CPSW1_HW_STATS          0x400
  97 #define CPSW1_CPTS_OFFSET       0x500
  98 #define CPSW1_ALE_OFFSET        0x600
  99 #define CPSW1_SLIVER_OFFSET     0x700
 100
 101 #define CPSW2_HOST_PORT_OFFSET  0x108
 102 #define CPSW2_SLAVE_OFFSET      0x200
 103 #define CPSW2_SLAVE_SIZE        0x100
 104 #define CPSW2_CPDMA_OFFSET      0x800
 105 #define CPSW2_HW_STATS          0x900
 106 #define CPSW2_STATERAM_OFFSET   0xa00
 107 #define CPSW2_CPTS_OFFSET       0xc00
 108 #define CPSW2_ALE_OFFSET        0xd00
 109 #define CPSW2_SLIVER_OFFSET     0xd80
 110 #define CPSW2_BD_OFFSET         0x2000
 111
 112 #define CPDMA_RXTHRESH          0x0c0
 113 #define CPDMA_RXFREE            0x0e0
 114 #define CPDMA_TXHDP             0x00
 115 #define CPDMA_RXHDP             0x20
 116 #define CPDMA_TXCP              0x40
 117 #define CPDMA_RXCP              0x60
 118
 119 #define CPSW_POLL_WEIGHT        64
 120 #define CPSW_MIN_PACKET_SIZE    60
 121 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 122
 123 #define RX_PRIORITY_MAPPING     0x76543210
 124 #define TX_PRIORITY_MAPPING     0x33221100
 125 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 126
 127 #define CPSW_VLAN_AWARE         BIT(1)
 128 #define CPSW_ALE_VLAN_AWARE     1
 129
 130 #define CPSW_FIFO_NORMAL_MODE           (0 << 15)
 131 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 15)
 132 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 15)
 133
 134 #define CPSW_INTPACEEN          (0x3f << 16)
 135 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 136 #define CPSW_CMINTMAX_CNT       63
 137 #define CPSW_CMINTMIN_CNT       2
 138 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 139 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 140
 141 #define cpsw_enable_irq(priv)   \
 142         do {                    \
 143                 u32 i;          \
 144                 for (i = 0; i < priv->num_irqs; i++) \
 145                         enable_irq(priv->irqs_table[i]); \
 146         } while (0)
 147 #define cpsw_disable_irq(priv)  \
 148         do {                    \
 149                 u32 i;          \
 150                 for (i = 0; i < priv->num_irqs; i++) \
 151                         disable_irq_nosync(priv->irqs_table[i]); \
 152         } while (0)
 153
 154 #define cpsw_slave_index(priv)                          \
 155                 ((priv->data.dual_emac) ? priv->emac_port :     \
 156                 priv->data.active_slave)
 157
 158 static int debug_level;
 159 module_param(debug_level, int, 0);
 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 161
 162 static int ale_ageout = 10;
 163 module_param(ale_ageout, int, 0);
 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 165
 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 167 module_param(rx_packet_max, int, 0);
 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 169
 170 struct cpsw_wr_regs {
 171         u32     id_ver;
 172         u32     soft_reset;
 173         u32     control;
 174         u32     int_control;
 175         u32     rx_thresh_en;
 176         u32     rx_en;
 177         u32     tx_en;
 178         u32     misc_en;
 179         u32     mem_allign1[8];
 180         u32     rx_thresh_stat;
 181         u32     rx_stat;
 182         u32     tx_stat;
 183         u32     misc_stat;
 184         u32     mem_allign2[8];
 185         u32     rx_imax;
 186         u32     tx_imax;
 187
 188 };
 189
 190 struct cpsw_ss_regs {
 191         u32     id_ver;
 192         u32     control;
 193         u32     soft_reset;
 194         u32     stat_port_en;
 195         u32     ptype;
 196         u32     soft_idle;
 197         u32     thru_rate;
 198         u32     gap_thresh;
 199         u32     tx_start_wds;
 200         u32     flow_control;
 201         u32     vlan_ltype;
 202         u32     ts_ltype;
 203         u32     dlr_ltype;
 204 };
 205
 206 /* CPSW_PORT_V1 */
 207 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 208 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 209 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 210 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 211 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 212 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 213 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 214 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 215
 216 /* CPSW_PORT_V2 */
 217 #define CPSW2_CONTROL       0x00 /* Control Register */
 218 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 219 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 220 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 221 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 222 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 223 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 224
 225 /* CPSW_PORT_V1 and V2 */
 226 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 227 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 228 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 229
 230 /* CPSW_PORT_V2 only */
 231 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 235 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 236 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 237 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 238 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 239
 240 /* Bit definitions for the CPSW2_CONTROL register */
 241 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 242 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 243 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 244 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 245 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 246 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 247 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 248 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 249 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 250 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 251 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 252 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 253 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 254 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 255 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 256 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 257 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 258
 259 #define CTRL_V2_TS_BITS \
 260         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 261          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 262
 263 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 264 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 265 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 266
 267
 268 #define CTRL_V3_TS_BITS \
 269         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 270          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 271          TS_LTYPE1_EN)
 272
 273 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 274 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 275 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 276
 277 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 278 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 279 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 280 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 281 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 282
 283 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 284 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 285
 286 /* Bit definitions for the CPSW1_TS_CTL register */
 287 #define CPSW_V1_TS_RX_EN                BIT(0)
 288 #define CPSW_V1_TS_TX_EN                BIT(4)
 289 #define CPSW_V1_MSG_TYPE_OFS            16
 290
 291 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 292 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 293
 294 struct cpsw_host_regs {
 295         u32     max_blks;
 296         u32     blk_cnt;
 297         u32     tx_in_ctl;
 298         u32     port_vlan;
 299         u32     tx_pri_map;
 300         u32     cpdma_tx_pri_map;
 301         u32     cpdma_rx_chan_map;
 302 };
 303
 304 struct cpsw_sliver_regs {
 305         u32     id_ver;
 306         u32     mac_control;
 307         u32     mac_status;
 308         u32     soft_reset;
 309         u32     rx_maxlen;
 310         u32     __reserved_0;
 311         u32     rx_pause;
 312         u32     tx_pause;
 313         u32     __reserved_1;
 314         u32     rx_pri_map;
 315 };
 316
 317 struct cpsw_hw_stats {
 318         u32     rxgoodframes;
 319         u32     rxbroadcastframes;
 320         u32     rxmulticastframes;
 321         u32     rxpauseframes;
 322         u32     rxcrcerrors;
 323         u32     rxaligncodeerrors;
 324         u32     rxoversizedframes;
 325         u32     rxjabberframes;
 326         u32     rxundersizedframes;
 327         u32     rxfragments;
 328         u32     __pad_0[2];
 329         u32     rxoctets;
 330         u32     txgoodframes;
 331         u32     txbroadcastframes;
 332         u32     txmulticastframes;
 333         u32     txpauseframes;
 334         u32     txdeferredframes;
 335         u32     txcollisionframes;
 336         u32     txsinglecollframes;
 337         u32     txmultcollframes;
 338         u32     txexcessivecollisions;
 339         u32     txlatecollisions;
 340         u32     txunderrun;
 341         u32     txcarriersenseerrors;
 342         u32     txoctets;
 343         u32     octetframes64;
 344         u32     octetframes65t127;
 345         u32     octetframes128t255;
 346         u32     octetframes256t511;
 347         u32     octetframes512t1023;
 348         u32     octetframes1024tup;
 349         u32     netoctets;
 350         u32     rxsofoverruns;
 351         u32     rxmofoverruns;
 352         u32     rxdmaoverruns;
 353 };
 354
 355 struct cpsw_slave {
 356         void __iomem                    *regs;
 357         struct cpsw_sliver_regs __iomem *sliver;
 358         int                             slave_num;
 359         u32                             mac_control;
 360         struct cpsw_slave_data          *data;
 361         struct phy_device               *phy;
 362         struct net_device               *ndev;
 363         u32                             port_vlan;
 364         u32                             open_stat;
 365 };
 366
 367 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 368 {
 369         return __raw_readl(slave->regs + offset);
 370 }
 371
 372 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 373 {
 374         __raw_writel(val, slave->regs + offset);
 375 }
 376
 377 struct cpsw_priv {
 378         spinlock_t                      lock;
 379         struct platform_device          *pdev;
 380         struct net_device               *ndev;
 381         struct napi_struct              napi;
 382         struct device                   *dev;
 383         struct cpsw_platform_data       data;
 384         struct cpsw_ss_regs __iomem     *regs;
 385         struct cpsw_wr_regs __iomem     *wr_regs;
 386         u8 __iomem                      *hw_stats;
 387         struct cpsw_host_regs __iomem   *host_port_regs;
 388         u32                             msg_enable;
 389         u32                             version;
 390         u32                             coal_intvl;
 391         u32                             bus_freq_mhz;
 392         int                             rx_packet_max;
 393         int                             host_port;
 394         struct clk                      *clk;
 395         u8                              mac_addr[ETH_ALEN];
 396         struct cpsw_slave               *slaves;
 397         struct cpdma_ctlr               *dma;
 398         struct cpdma_chan               *txch, *rxch;
 399         struct cpsw_ale                 *ale;
 400         /* snapshot of IRQ numbers */
 401         u32 irqs_table[4];
 402         u32 num_irqs;
 403         bool irq_enabled;
 404         struct cpts *cpts;
 405         u32 emac_port;
 406 };
 407
 408 struct cpsw_stats {
 409         char stat_string[ETH_GSTRING_LEN];
 410         int type;
 411         int sizeof_stat;
 412         int stat_offset;
 413 };
 414
 415 enum {
 416         CPSW_STATS,
 417         CPDMA_RX_STATS,
 418         CPDMA_TX_STATS,
 419 };
 420
 421 #define CPSW_STAT(m)            CPSW_STATS,                             \
 422                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 423                                 offsetof(struct cpsw_hw_stats, m)
 424 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 425                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 426                                 offsetof(struct cpdma_chan_stats, m)
 427 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 428                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 429                                 offsetof(struct cpdma_chan_stats, m)
 430
 431 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 432         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 433         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 434         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 435         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 436         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 437         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 438         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 439         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 440         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 441         { "Rx Fragments", CPSW_STAT(rxfragments) },
 442         { "Rx Octets", CPSW_STAT(rxoctets) },
 443         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 444         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 445         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 446         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 447         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 448         { "Collisions", CPSW_STAT(txcollisionframes) },
 449         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 450         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 451         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 452         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 453         { "Tx Underrun", CPSW_STAT(txunderrun) },
 454         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 455         { "Tx Octets", CPSW_STAT(txoctets) },
 456         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 457         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 458         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 459         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 460         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 461         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 462         { "Net Octets", CPSW_STAT(netoctets) },
 463         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 464         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 465         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 466         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 467         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 468         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 469         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 470         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 471         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 472         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 473         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 474         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 475         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 476         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 477         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 478         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 479         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 480         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 481         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 482         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 483         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 484         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 485         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 486         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 487         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 488         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 489         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 490         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 491         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 492 };
 493
 494 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 495
 496 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 497 #define for_each_slave(priv, func, arg...)                              \
 498         do {                                                            \
 499                 struct cpsw_slave *slave;                               \
 500                 int n;                                                  \
 501                 if (priv->data.dual_emac)                               \
 502                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 503                 else                                                    \
 504                         for (n = (priv)->data.slaves,                   \
 505                                         slave = (priv)->slaves;         \
 506                                         n; n--)                         \
 507                                 (func)(slave++, ##arg);                 \
 508         } while (0)
 509 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 510         (priv->slaves[__slave_no__].ndev)
 511 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 512         ((priv->slaves[__slave_no__].ndev) ?                            \
 513                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 514
 515 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 516         do {                                                            \
 517                 if (!priv->data.dual_emac)                              \
 518                         break;                                          \
 519                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 520                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 521                         priv = netdev_priv(ndev);                       \
 522                         skb->dev = ndev;                                \
 523                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 524                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 525                         priv = netdev_priv(ndev);                       \
 526                         skb->dev = ndev;                                \
 527                 }                                                       \
 528         } while (0)
 529 #define cpsw_add_mcast(priv, addr)                                      \
 530         do {                                                            \
 531                 if (priv->data.dual_emac) {                             \
 532                         struct cpsw_slave *slave = priv->slaves +       \
 533                                                 priv->emac_port;        \
 534                         int slave_port = cpsw_get_slave_port(priv,      \
 535                                                 slave->slave_num);      \
 536                         cpsw_ale_add_mcast(priv->ale, addr,             \
 537                                 1 << slave_port | 1 << priv->host_port, \
 538                                 ALE_VLAN, slave->port_vlan, 0);         \
 539                 } else {                                                \
 540                         cpsw_ale_add_mcast(priv->ale, addr,             \
 541                                 ALE_ALL_PORTS << priv->host_port,       \
 542                                 0, 0, 0);                               \
 543                 }                                                       \
 544         } while (0)
 545
 546 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 547 {
 548         if (priv->host_port == 0)
 549                 return slave_num + 1;
 550         else
 551                 return slave_num;
 552 }
 553
 554 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 555 {
 556         struct cpsw_priv *priv = netdev_priv(ndev);
 557         struct cpsw_ale *ale = priv->ale;
 558         int i;
 559
 560         if (priv->data.dual_emac) {
 561                 bool flag = false;
 562
 563                 /* Enabling promiscuous mode for one interface will be
 564                  * common for both the interface as the interface shares
 565                  * the same hardware resource.
 566                  */
 567                 for (i = 0; i < priv->data.slaves; i++)
 568                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 569                                 flag = true;
 570
 571                 if (!enable && flag) {
 572                         enable = true;
 573                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 574                 }
 575
 576                 if (enable) {
 577                         /* Enable Bypass */
 578                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 579
 580                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 581                 } else {
 582                         /* Disable Bypass */
 583                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 584                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 585                 }
 586         } else {
 587                 if (enable) {
 588                         unsigned long timeout = jiffies + HZ;
 589
 590                         /* Disable Learn for all ports */
 591                         for (i = 0; i < priv->data.slaves; i++) {
 592                                 cpsw_ale_control_set(ale, i,
 593                                                      ALE_PORT_NOLEARN, 1);
 594                                 cpsw_ale_control_set(ale, i,
 595                                                      ALE_PORT_NO_SA_UPDATE, 1);
 596                         }
 597
 598                         /* Clear All Untouched entries */
 599                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 600                         do {
 601                                 cpu_relax();
 602                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 603                                         break;
 604                         } while (time_after(timeout, jiffies));
 605                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 606
 607                         /* Clear all mcast from ALE */
 608                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 609                                                  priv->host_port);
 610
 611                         /* Flood All Unicast Packets to Host port */
 612                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 613                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 614                 } else {
 615                         /* Flood All Unicast Packets to Host port */
 616                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 617
 618                         /* Enable Learn for all ports */
 619                         for (i = 0; i < priv->data.slaves; i++) {
 620                                 cpsw_ale_control_set(ale, i,
 621                                                      ALE_PORT_NOLEARN, 0);
 622                                 cpsw_ale_control_set(ale, i,
 623                                                      ALE_PORT_NO_SA_UPDATE, 0);
 624                         }
 625                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 626                 }
 627         }
 628 }
 629
 630 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 631 {
 632         struct cpsw_priv *priv = netdev_priv(ndev);
 633
 634         if (ndev->flags & IFF_PROMISC) {
 635                 /* Enable promiscuous mode */
 636                 cpsw_set_promiscious(ndev, true);
 637                 return;
 638         } else {
 639                 /* Disable promiscuous mode */
 640                 cpsw_set_promiscious(ndev, false);
 641         }
 642
 643         /* Clear all mcast from ALE */
 644         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
 645
 646         if (!netdev_mc_empty(ndev)) {
 647                 struct netdev_hw_addr *ha;
 648
 649                 /* program multicast address list into ALE register */
 650                 netdev_for_each_mc_addr(ha, ndev) {
 651                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 652                 }
 653         }
 654 }
 655
 656 static void cpsw_intr_enable(struct cpsw_priv *priv)
 657 {
 658         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 659         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 660
 661         cpdma_ctlr_int_ctrl(priv->dma, true);
 662         return;
 663 }
 664
 665 static void cpsw_intr_disable(struct cpsw_priv *priv)
 666 {
 667         __raw_writel(0, &priv->wr_regs->tx_en);
 668         __raw_writel(0, &priv->wr_regs->rx_en);
 669
 670         cpdma_ctlr_int_ctrl(priv->dma, false);
 671         return;
 672 }
 673
 674 static void cpsw_tx_handler(void *token, int len, int status)
 675 {
 676         struct sk_buff          *skb = token;
 677         struct net_device       *ndev = skb->dev;
 678         struct cpsw_priv        *priv = netdev_priv(ndev);
 679
 680         /* Check whether the queue is stopped due to stalled tx dma, if the
 681          * queue is stopped then start the queue as we have free desc for tx
 682          */
 683         if (unlikely(netif_queue_stopped(ndev)))
 684                 netif_wake_queue(ndev);
 685         cpts_tx_timestamp(priv->cpts, skb);
 686         ndev->stats.tx_packets++;
 687         ndev->stats.tx_bytes += len;
 688         dev_kfree_skb_any(skb);
 689 }
 690
 691 static void cpsw_rx_handler(void *token, int len, int status)
 692 {
 693         struct sk_buff          *skb = token;
 694         struct sk_buff          *new_skb;
 695         struct net_device       *ndev = skb->dev;
 696         struct cpsw_priv        *priv = netdev_priv(ndev);
 697         int                     ret = 0;
 698
 699         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 700
 701         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 702                 /* the interface is going down, skbs are purged */
 703                 dev_kfree_skb_any(skb);
 704                 return;
 705         }
 706
 707         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 708         if (new_skb) {
 709                 skb_put(skb, len);
 710                 cpts_rx_timestamp(priv->cpts, skb);
 711                 skb->protocol = eth_type_trans(skb, ndev);
 712                 netif_receive_skb(skb);
 713                 ndev->stats.rx_bytes += len;
 714                 ndev->stats.rx_packets++;
 715         } else {
 716                 ndev->stats.rx_dropped++;
 717                 new_skb = skb;
 718         }
 719
 720         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 721                         skb_tailroom(new_skb), 0);
 722         if (WARN_ON(ret < 0))
 723                 dev_kfree_skb_any(new_skb);
 724 }
 725
 726 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 727 {
 728         struct cpsw_priv *priv = dev_id;
 729
 730         cpsw_intr_disable(priv);
 731         if (priv->irq_enabled == true) {
 732                 cpsw_disable_irq(priv);
 733                 priv->irq_enabled = false;
 734         }
 735
 736         if (netif_running(priv->ndev)) {
 737                 napi_schedule(&priv->napi);
 738                 return IRQ_HANDLED;
 739         }
 740
 741         priv = cpsw_get_slave_priv(priv, 1);
 742         if (!priv)
 743                 return IRQ_NONE;
 744
 745         if (netif_running(priv->ndev)) {
 746                 napi_schedule(&priv->napi);
 747                 return IRQ_HANDLED;
 748         }
 749         return IRQ_NONE;
 750 }
 751
 752 static int cpsw_poll(struct napi_struct *napi, int budget)
 753 {
 754         struct cpsw_priv        *priv = napi_to_priv(napi);
 755         int                     num_tx, num_rx;
 756
 757         num_tx = cpdma_chan_process(priv->txch, 128);
 758         if (num_tx)
 759                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 760
 761         num_rx = cpdma_chan_process(priv->rxch, budget);
 762         if (num_rx < budget) {
 763                 struct cpsw_priv *prim_cpsw;
 764
 765                 napi_complete(napi);
 766                 cpsw_intr_enable(priv);
 767                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 768                 prim_cpsw = cpsw_get_slave_priv(priv, 0);
 769                 if (prim_cpsw->irq_enabled == false) {
 770                         prim_cpsw->irq_enabled = true;
 771                         cpsw_enable_irq(priv);
 772                 }
 773         }
 774
 775         if (num_rx || num_tx)
 776                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 777                          num_rx, num_tx);
 778
 779         return num_rx;
 780 }
 781
 782 static inline void soft_reset(const char *module, void __iomem *reg)
 783 {
 784         unsigned long timeout = jiffies + HZ;
 785
 786         __raw_writel(1, reg);
 787         do {
 788                 cpu_relax();
 789         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 790
 791         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 792 }
 793
 794 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 795                          ((mac)[2] << 16) | ((mac)[3] << 24))
 796 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 797
 798 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 799                                struct cpsw_priv *priv)
 800 {
 801         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 802         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 803 }
 804
 805 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 806                               struct cpsw_priv *priv, bool *link)
 807 {
 808         struct phy_device       *phy = slave->phy;
 809         u32                     mac_control = 0;
 810         u32                     slave_port;
 811
 812         if (!phy)
 813                 return;
 814
 815         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 816
 817         if (phy->link) {
 818                 mac_control = priv->data.mac_control;
 819
 820                 /* enable forwarding */
 821                 cpsw_ale_control_set(priv->ale, slave_port,
 822                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 823
 824                 if (phy->speed == 1000)
 825                         mac_control |= BIT(7);  /* GIGABITEN    */
 826                 if (phy->duplex)
 827                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 828
 829                 /* set speed_in input in case RMII mode is used in 100Mbps */
 830                 if (phy->speed == 100)
 831                         mac_control |= BIT(15);
 832                 else if (phy->speed == 10)
 833                         mac_control |= BIT(18); /* In Band mode */
 834
 835                 *link = true;
 836         } else {
 837                 mac_control = 0;
 838                 /* disable forwarding */
 839                 cpsw_ale_control_set(priv->ale, slave_port,
 840                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 841         }
 842
 843         if (mac_control != slave->mac_control) {
 844                 phy_print_status(phy);
 845                 __raw_writel(mac_control, &slave->sliver->mac_control);
 846         }
 847
 848         slave->mac_control = mac_control;
 849 }
 850
 851 static void cpsw_adjust_link(struct net_device *ndev)
 852 {
 853         struct cpsw_priv        *priv = netdev_priv(ndev);
 854         bool                    link = false;
 855
 856         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 857
 858         if (link) {
 859                 netif_carrier_on(ndev);
 860                 if (netif_running(ndev))
 861                         netif_wake_queue(ndev);
 862         } else {
 863                 netif_carrier_off(ndev);
 864                 netif_stop_queue(ndev);
 865         }
 866 }
 867
 868 static int cpsw_get_coalesce(struct net_device *ndev,
 869                                 struct ethtool_coalesce *coal)
 870 {
 871         struct cpsw_priv *priv = netdev_priv(ndev);
 872
 873         coal->rx_coalesce_usecs = priv->coal_intvl;
 874         return 0;
 875 }
 876
 877 static int cpsw_set_coalesce(struct net_device *ndev,
 878                                 struct ethtool_coalesce *coal)
 879 {
 880         struct cpsw_priv *priv = netdev_priv(ndev);
 881         u32 int_ctrl;
 882         u32 num_interrupts = 0;
 883         u32 prescale = 0;
 884         u32 addnl_dvdr = 1;
 885         u32 coal_intvl = 0;
 886
 887         coal_intvl = coal->rx_coalesce_usecs;
 888
 889         int_ctrl =  readl(&priv->wr_regs->int_control);
 890         prescale = priv->bus_freq_mhz * 4;
 891
 892         if (!coal->rx_coalesce_usecs) {
 893                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 894                 goto update_return;
 895         }
 896
 897         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 898                 coal_intvl = CPSW_CMINTMIN_INTVL;
 899
 900         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 901                 /* Interrupt pacer works with 4us Pulse, we can
 902                  * throttle further by dilating the 4us pulse.
 903                  */
 904                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 905
 906                 if (addnl_dvdr > 1) {
 907                         prescale *= addnl_dvdr;
 908                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 909                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 910                                                 * addnl_dvdr);
 911                 } else {
 912                         addnl_dvdr = 1;
 913                         coal_intvl = CPSW_CMINTMAX_INTVL;
 914                 }
 915         }
 916
 917         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 918         writel(num_interrupts, &priv->wr_regs->rx_imax);
 919         writel(num_interrupts, &priv->wr_regs->tx_imax);
 920
 921         int_ctrl |= CPSW_INTPACEEN;
 922         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 923         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 924
 925 update_return:
 926         writel(int_ctrl, &priv->wr_regs->int_control);
 927
 928         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 929         if (priv->data.dual_emac) {
 930                 int i;
 931
 932                 for (i = 0; i < priv->data.slaves; i++) {
 933                         priv = netdev_priv(priv->slaves[i].ndev);
 934                         priv->coal_intvl = coal_intvl;
 935                 }
 936         } else {
 937                 priv->coal_intvl = coal_intvl;
 938         }
 939
 940         return 0;
 941 }
 942
 943 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 944 {
 945         switch (sset) {
 946         case ETH_SS_STATS:
 947                 return CPSW_STATS_LEN;
 948         default:
 949                 return -EOPNOTSUPP;
 950         }
 951 }
 952
 953 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
 954 {
 955         u8 *p = data;
 956         int i;
 957
 958         switch (stringset) {
 959         case ETH_SS_STATS:
 960                 for (i = 0; i < CPSW_STATS_LEN; i++) {
 961                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
 962                                ETH_GSTRING_LEN);
 963                         p += ETH_GSTRING_LEN;
 964                 }
 965                 break;
 966         }
 967 }
 968
 969 static void cpsw_get_ethtool_stats(struct net_device *ndev,
 970                                     struct ethtool_stats *stats, u64 *data)
 971 {
 972         struct cpsw_priv *priv = netdev_priv(ndev);
 973         struct cpdma_chan_stats rx_stats;
 974         struct cpdma_chan_stats tx_stats;
 975         u32 val;
 976         u8 *p;
 977         int i;
 978
 979         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
 980         cpdma_chan_get_stats(priv->rxch, &rx_stats);
 981         cpdma_chan_get_stats(priv->txch, &tx_stats);
 982
 983         for (i = 0; i < CPSW_STATS_LEN; i++) {
 984                 switch (cpsw_gstrings_stats[i].type) {
 985                 case CPSW_STATS:
 986                         val = readl(priv->hw_stats +
 987                                     cpsw_gstrings_stats[i].stat_offset);
 988                         data[i] = val;
 989                         break;
 990
 991                 case CPDMA_RX_STATS:
 992                         p = (u8 *)&rx_stats +
 993                                 cpsw_gstrings_stats[i].stat_offset;
 994                         data[i] = *(u32 *)p;
 995                         break;
 996
 997                 case CPDMA_TX_STATS:
 998                         p = (u8 *)&tx_stats +
 999                                 cpsw_gstrings_stats[i].stat_offset;
1000                         data[i] = *(u32 *)p;
1001                         break;
1002                 }
1003         }
1004 }
1005
1006 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1007 {
1008         u32 i;
1009         u32 usage_count = 0;
1010
1011         if (!priv->data.dual_emac)
1012                 return 0;
1013
1014         for (i = 0; i < priv->data.slaves; i++)
1015                 if (priv->slaves[i].open_stat)
1016                         usage_count++;
1017
1018         return usage_count;
1019 }
1020
1021 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1022                         struct cpsw_priv *priv, struct sk_buff *skb)
1023 {
1024         if (!priv->data.dual_emac)
1025                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1026                                   skb->len, 0);
1027
1028         if (ndev == cpsw_get_slave_ndev(priv, 0))
1029                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1030                                   skb->len, 1);
1031         else
1032                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1033                                   skb->len, 2);
1034 }
1035
1036 static inline void cpsw_add_dual_emac_def_ale_entries(
1037                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1038                 u32 slave_port)
1039 {
1040         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1041
1042         if (priv->version == CPSW_VERSION_1)
1043                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1044         else
1045                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1046         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1047                           port_mask, port_mask, 0);
1048         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1049                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1050         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1051                 priv->host_port, ALE_VLAN, slave->port_vlan);
1052 }
1053
1054 static void soft_reset_slave(struct cpsw_slave *slave)
1055 {
1056         char name[32];
1057
1058         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1059         soft_reset(name, &slave->sliver->soft_reset);
1060 }
1061
1062 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1063 {
1064         u32 slave_port;
1065
1066         soft_reset_slave(slave);
1067
1068         /* setup priority mapping */
1069         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1070
1071         switch (priv->version) {
1072         case CPSW_VERSION_1:
1073                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1074                 break;
1075         case CPSW_VERSION_2:
1076         case CPSW_VERSION_3:
1077         case CPSW_VERSION_4:
1078                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1079                 break;
1080         }
1081
1082         /* setup max packet size, and mac address */
1083         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1084         cpsw_set_slave_mac(slave, priv);
1085
1086         slave->mac_control = 0; /* no link yet */
1087
1088         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1089
1090         if (priv->data.dual_emac)
1091                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1092         else
1093                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1094                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1095
1096         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1097                                  &cpsw_adjust_link, slave->data->phy_if);
1098         if (IS_ERR(slave->phy)) {
1099                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1100                         slave->data->phy_id, slave->slave_num);
1101                 slave->phy = NULL;
1102         } else {
1103                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1104                          slave->phy->phy_id);
1105                 phy_start(slave->phy);
1106
1107                 /* Configure GMII_SEL register */
1108                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1109                              slave->slave_num);
1110         }
1111 }
1112
1113 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1114 {
1115         const int vlan = priv->data.default_vlan;
1116         const int port = priv->host_port;
1117         u32 reg;
1118         int i;
1119
1120         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1121                CPSW2_PORT_VLAN;
1122
1123         writel(vlan, &priv->host_port_regs->port_vlan);
1124
1125         for (i = 0; i < priv->data.slaves; i++)
1126                 slave_write(priv->slaves + i, vlan, reg);
1127
1128         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1129                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1130                           (ALE_PORT_1 | ALE_PORT_2) << port);
1131 }
1132
1133 static void cpsw_init_host_port(struct cpsw_priv *priv)
1134 {
1135         u32 control_reg;
1136         u32 fifo_mode;
1137
1138         /* soft reset the controller and initialize ale */
1139         soft_reset("cpsw", &priv->regs->soft_reset);
1140         cpsw_ale_start(priv->ale);
1141
1142         /* switch to vlan unaware mode */
1143         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1144                              CPSW_ALE_VLAN_AWARE);
1145         control_reg = readl(&priv->regs->control);
1146         control_reg |= CPSW_VLAN_AWARE;
1147         writel(control_reg, &priv->regs->control);
1148         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1149                      CPSW_FIFO_NORMAL_MODE;
1150         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1151
1152         /* setup host port priority mapping */
1153         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1154                      &priv->host_port_regs->cpdma_tx_pri_map);
1155         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1156
1157         cpsw_ale_control_set(priv->ale, priv->host_port,
1158                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1159
1160         if (!priv->data.dual_emac) {
1161                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1162                                    0, 0);
1163                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1164                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1165         }
1166 }
1167
1168 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1169 {
1170         u32 slave_port;
1171
1172         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1173
1174         if (!slave->phy)
1175                 return;
1176         phy_stop(slave->phy);
1177         phy_disconnect(slave->phy);
1178         slave->phy = NULL;
1179         cpsw_ale_control_set(priv->ale, slave_port,
1180                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1181 }
1182
1183 static int cpsw_ndo_open(struct net_device *ndev)
1184 {
1185         struct cpsw_priv *priv = netdev_priv(ndev);
1186         struct cpsw_priv *prim_cpsw;
1187         int i, ret;
1188         u32 reg;
1189
1190         if (!cpsw_common_res_usage_state(priv))
1191                 cpsw_intr_disable(priv);
1192         netif_carrier_off(ndev);
1193
1194         pm_runtime_get_sync(&priv->pdev->dev);
1195
1196         reg = priv->version;
1197
1198         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1199                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1200                  CPSW_RTL_VERSION(reg));
1201
1202         /* initialize host and slave ports */
1203         if (!cpsw_common_res_usage_state(priv))
1204                 cpsw_init_host_port(priv);
1205         for_each_slave(priv, cpsw_slave_open, priv);
1206
1207         /* Add default VLAN */
1208         if (!priv->data.dual_emac)
1209                 cpsw_add_default_vlan(priv);
1210         else
1211                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1212                                   ALE_ALL_PORTS << priv->host_port,
1213                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1214
1215         if (!cpsw_common_res_usage_state(priv)) {
1216                 /* setup tx dma to fixed prio and zero offset */
1217                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1218                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1219
1220                 /* disable priority elevation */
1221                 __raw_writel(0, &priv->regs->ptype);
1222
1223                 /* enable statistics collection only on all ports */
1224                 __raw_writel(0x7, &priv->regs->stat_port_en);
1225
1226                 if (WARN_ON(!priv->data.rx_descs))
1227                         priv->data.rx_descs = 128;
1228
1229                 for (i = 0; i < priv->data.rx_descs; i++) {
1230                         struct sk_buff *skb;
1231
1232                         ret = -ENOMEM;
1233                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1234                                         priv->rx_packet_max, GFP_KERNEL);
1235                         if (!skb)
1236                                 goto err_cleanup;
1237                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1238                                         skb_tailroom(skb), 0);
1239                         if (ret < 0) {
1240                                 kfree_skb(skb);
1241                                 goto err_cleanup;
1242                         }
1243                 }
1244                 /* continue even if we didn't manage to submit all
1245                  * receive descs
1246                  */
1247                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1248
1249                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1250                                   priv->data.cpts_clock_mult,
1251                                   priv->data.cpts_clock_shift))
1252                         dev_err(priv->dev, "error registering cpts device\n");
1253
1254         }
1255
1256         /* Enable Interrupt pacing if configured */
1257         if (priv->coal_intvl != 0) {
1258                 struct ethtool_coalesce coal;
1259
1260                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1261                 cpsw_set_coalesce(ndev, &coal);
1262         }
1263
1264         napi_enable(&priv->napi);
1265         cpdma_ctlr_start(priv->dma);
1266         cpsw_intr_enable(priv);
1267         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1268         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1269
1270         prim_cpsw = cpsw_get_slave_priv(priv, 0);
1271         if (prim_cpsw->irq_enabled == false) {
1272                 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1273                         prim_cpsw->irq_enabled = true;
1274                         cpsw_enable_irq(prim_cpsw);
1275                 }
1276         }
1277
1278         if (priv->data.dual_emac)
1279                 priv->slaves[priv->emac_port].open_stat = true;
1280         return 0;
1281
1282 err_cleanup:
1283         cpdma_ctlr_stop(priv->dma);
1284         for_each_slave(priv, cpsw_slave_stop, priv);
1285         pm_runtime_put_sync(&priv->pdev->dev);
1286         netif_carrier_off(priv->ndev);
1287         return ret;
1288 }
1289
1290 static int cpsw_ndo_stop(struct net_device *ndev)
1291 {
1292         struct cpsw_priv *priv = netdev_priv(ndev);
1293
1294         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1295         netif_stop_queue(priv->ndev);
1296         napi_disable(&priv->napi);
1297         netif_carrier_off(priv->ndev);
1298
1299         if (cpsw_common_res_usage_state(priv) <= 1) {
1300                 cpts_unregister(priv->cpts);
1301                 cpsw_intr_disable(priv);
1302                 cpdma_ctlr_int_ctrl(priv->dma, false);
1303                 cpdma_ctlr_stop(priv->dma);
1304                 cpsw_ale_stop(priv->ale);
1305         }
1306         for_each_slave(priv, cpsw_slave_stop, priv);
1307         pm_runtime_put_sync(&priv->pdev->dev);
1308         if (priv->data.dual_emac)
1309                 priv->slaves[priv->emac_port].open_stat = false;
1310         return 0;
1311 }
1312
1313 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1314                                        struct net_device *ndev)
1315 {
1316         struct cpsw_priv *priv = netdev_priv(ndev);
1317         int ret;
1318
1319         ndev->trans_start = jiffies;
1320
1321         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1322                 cpsw_err(priv, tx_err, "packet pad failed\n");
1323                 ndev->stats.tx_dropped++;
1324                 return NETDEV_TX_OK;
1325         }
1326
1327         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1328                                 priv->cpts->tx_enable)
1329                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1330
1331         skb_tx_timestamp(skb);
1332
1333         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1334         if (unlikely(ret != 0)) {
1335                 cpsw_err(priv, tx_err, "desc submit failed\n");
1336                 goto fail;
1337         }
1338
1339         /* If there is no more tx desc left free then we need to
1340          * tell the kernel to stop sending us tx frames.
1341          */
1342         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1343                 netif_stop_queue(ndev);
1344
1345         return NETDEV_TX_OK;
1346 fail:
1347         ndev->stats.tx_dropped++;
1348         netif_stop_queue(ndev);
1349         return NETDEV_TX_BUSY;
1350 }
1351
1352 #ifdef CONFIG_TI_CPTS
1353
1354 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1355 {
1356         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1357         u32 ts_en, seq_id;
1358
1359         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1360                 slave_write(slave, 0, CPSW1_TS_CTL);
1361                 return;
1362         }
1363
1364         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1365         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1366
1367         if (priv->cpts->tx_enable)
1368                 ts_en |= CPSW_V1_TS_TX_EN;
1369
1370         if (priv->cpts->rx_enable)
1371                 ts_en |= CPSW_V1_TS_RX_EN;
1372
1373         slave_write(slave, ts_en, CPSW1_TS_CTL);
1374         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1375 }
1376
1377 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1378 {
1379         struct cpsw_slave *slave;
1380         u32 ctrl, mtype;
1381
1382         if (priv->data.dual_emac)
1383                 slave = &priv->slaves[priv->emac_port];
1384         else
1385                 slave = &priv->slaves[priv->data.active_slave];
1386
1387         ctrl = slave_read(slave, CPSW2_CONTROL);
1388         switch (priv->version) {
1389         case CPSW_VERSION_2:
1390                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1391
1392                 if (priv->cpts->tx_enable)
1393                         ctrl |= CTRL_V2_TX_TS_BITS;
1394
1395                 if (priv->cpts->rx_enable)
1396                         ctrl |= CTRL_V2_RX_TS_BITS;
1397         break;
1398         case CPSW_VERSION_3:
1399         default:
1400                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1401
1402                 if (priv->cpts->tx_enable)
1403                         ctrl |= CTRL_V3_TX_TS_BITS;
1404
1405                 if (priv->cpts->rx_enable)
1406                         ctrl |= CTRL_V3_RX_TS_BITS;
1407         break;
1408         }
1409
1410         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1411
1412         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1413         slave_write(slave, ctrl, CPSW2_CONTROL);
1414         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1415 }
1416
1417 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1418 {
1419         struct cpsw_priv *priv = netdev_priv(dev);
1420         struct cpts *cpts = priv->cpts;
1421         struct hwtstamp_config cfg;
1422
1423         if (priv->version != CPSW_VERSION_1 &&
1424             priv->version != CPSW_VERSION_2 &&
1425             priv->version != CPSW_VERSION_3)
1426                 return -EOPNOTSUPP;
1427
1428         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1429                 return -EFAULT;
1430
1431         /* reserved for future extensions */
1432         if (cfg.flags)
1433                 return -EINVAL;
1434
1435         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1436                 return -ERANGE;
1437
1438         switch (cfg.rx_filter) {
1439         case HWTSTAMP_FILTER_NONE:
1440                 cpts->rx_enable = 0;
1441                 break;
1442         case HWTSTAMP_FILTER_ALL:
1443         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1444         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1445         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1446                 return -ERANGE;
1447         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1448         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1449         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1450         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1451         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1452         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1453         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1454         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1455         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1456                 cpts->rx_enable = 1;
1457                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1458                 break;
1459         default:
1460                 return -ERANGE;
1461         }
1462
1463         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1464
1465         switch (priv->version) {
1466         case CPSW_VERSION_1:
1467                 cpsw_hwtstamp_v1(priv);
1468                 break;
1469         case CPSW_VERSION_2:
1470         case CPSW_VERSION_3:
1471                 cpsw_hwtstamp_v2(priv);
1472                 break;
1473         default:
1474                 WARN_ON(1);
1475         }
1476
1477         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1478 }
1479
1480 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1481 {
1482         struct cpsw_priv *priv = netdev_priv(dev);
1483         struct cpts *cpts = priv->cpts;
1484         struct hwtstamp_config cfg;
1485
1486         if (priv->version != CPSW_VERSION_1 &&
1487             priv->version != CPSW_VERSION_2 &&
1488             priv->version != CPSW_VERSION_3)
1489                 return -EOPNOTSUPP;
1490
1491         cfg.flags = 0;
1492         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1493         cfg.rx_filter = (cpts->rx_enable ?
1494                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1495
1496         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1497 }
1498
1499 #endif /*CONFIG_TI_CPTS*/
1500
1501 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1502 {
1503         struct cpsw_priv *priv = netdev_priv(dev);
1504         int slave_no = cpsw_slave_index(priv);
1505
1506         if (!netif_running(dev))
1507                 return -EINVAL;
1508
1509         switch (cmd) {
1510 #ifdef CONFIG_TI_CPTS
1511         case SIOCSHWTSTAMP:
1512                 return cpsw_hwtstamp_set(dev, req);
1513         case SIOCGHWTSTAMP:
1514                 return cpsw_hwtstamp_get(dev, req);
1515 #endif
1516         }
1517
1518         if (!priv->slaves[slave_no].phy)
1519                 return -EOPNOTSUPP;
1520         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1521 }
1522
1523 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1524 {
1525         struct cpsw_priv *priv = netdev_priv(ndev);
1526
1527         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1528         ndev->stats.tx_errors++;
1529         cpsw_intr_disable(priv);
1530         cpdma_ctlr_int_ctrl(priv->dma, false);
1531         cpdma_chan_stop(priv->txch);
1532         cpdma_chan_start(priv->txch);
1533         cpdma_ctlr_int_ctrl(priv->dma, true);
1534         cpsw_intr_enable(priv);
1535         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1536         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1537
1538 }
1539
1540 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1541 {
1542         struct cpsw_priv *priv = netdev_priv(ndev);
1543         struct sockaddr *addr = (struct sockaddr *)p;
1544         int flags = 0;
1545         u16 vid = 0;
1546
1547         if (!is_valid_ether_addr(addr->sa_data))
1548                 return -EADDRNOTAVAIL;
1549
1550         if (priv->data.dual_emac) {
1551                 vid = priv->slaves[priv->emac_port].port_vlan;
1552                 flags = ALE_VLAN;
1553         }
1554
1555         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1556                            flags, vid);
1557         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1558                            flags, vid);
1559
1560         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1561         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1562         for_each_slave(priv, cpsw_set_slave_mac, priv);
1563
1564         return 0;
1565 }
1566
1567 #ifdef CONFIG_NET_POLL_CONTROLLER
1568 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1569 {
1570         struct cpsw_priv *priv = netdev_priv(ndev);
1571
1572         cpsw_intr_disable(priv);
1573         cpdma_ctlr_int_ctrl(priv->dma, false);
1574         cpsw_interrupt(ndev->irq, priv);
1575         cpdma_ctlr_int_ctrl(priv->dma, true);
1576         cpsw_intr_enable(priv);
1577         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1578         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1579
1580 }
1581 #endif
1582
1583 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1584                                 unsigned short vid)
1585 {
1586         int ret;
1587
1588         ret = cpsw_ale_add_vlan(priv->ale, vid,
1589                                 ALE_ALL_PORTS << priv->host_port,
1590                                 0, ALE_ALL_PORTS << priv->host_port,
1591                                 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1592         if (ret != 0)
1593                 return ret;
1594
1595         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1596                                  priv->host_port, ALE_VLAN, vid);
1597         if (ret != 0)
1598                 goto clean_vid;
1599
1600         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1601                                  ALE_ALL_PORTS << priv->host_port,
1602                                  ALE_VLAN, vid, 0);
1603         if (ret != 0)
1604                 goto clean_vlan_ucast;
1605         return 0;
1606
1607 clean_vlan_ucast:
1608         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1609                             priv->host_port, ALE_VLAN, vid);
1610 clean_vid:
1611         cpsw_ale_del_vlan(priv->ale, vid, 0);
1612         return ret;
1613 }
1614
1615 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1616                                     __be16 proto, u16 vid)
1617 {
1618         struct cpsw_priv *priv = netdev_priv(ndev);
1619
1620         if (vid == priv->data.default_vlan)
1621                 return 0;
1622
1623         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1624         return cpsw_add_vlan_ale_entry(priv, vid);
1625 }
1626
1627 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1628                                      __be16 proto, u16 vid)
1629 {
1630         struct cpsw_priv *priv = netdev_priv(ndev);
1631         int ret;
1632
1633         if (vid == priv->data.default_vlan)
1634                 return 0;
1635
1636         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1637         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1638         if (ret != 0)
1639                 return ret;
1640
1641         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1642                                  priv->host_port, ALE_VLAN, vid);
1643         if (ret != 0)
1644                 return ret;
1645
1646         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1647                                   0, ALE_VLAN, vid);
1648 }
1649
1650 static const struct net_device_ops cpsw_netdev_ops = {
1651         .ndo_open               = cpsw_ndo_open,
1652         .ndo_stop               = cpsw_ndo_stop,
1653         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1654         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1655         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1656         .ndo_validate_addr      = eth_validate_addr,
1657         .ndo_change_mtu         = eth_change_mtu,
1658         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1659         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1660 #ifdef CONFIG_NET_POLL_CONTROLLER
1661         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1662 #endif
1663         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1664         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1665 };
1666
1667 static int cpsw_get_regs_len(struct net_device *ndev)
1668 {
1669         struct cpsw_priv *priv = netdev_priv(ndev);
1670
1671         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1672 }
1673
1674 static void cpsw_get_regs(struct net_device *ndev,
1675                           struct ethtool_regs *regs, void *p)
1676 {
1677         struct cpsw_priv *priv = netdev_priv(ndev);
1678         u32 *reg = p;
1679
1680         /* update CPSW IP version */
1681         regs->version = priv->version;
1682
1683         cpsw_ale_dump(priv->ale, reg);
1684 }
1685
1686 static void cpsw_get_drvinfo(struct net_device *ndev,
1687                              struct ethtool_drvinfo *info)
1688 {
1689         struct cpsw_priv *priv = netdev_priv(ndev);
1690
1691         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1692         strlcpy(info->version, "1.0", sizeof(info->version));
1693         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1694         info->regdump_len = cpsw_get_regs_len(ndev);
1695 }
1696
1697 static u32 cpsw_get_msglevel(struct net_device *ndev)
1698 {
1699         struct cpsw_priv *priv = netdev_priv(ndev);
1700         return priv->msg_enable;
1701 }
1702
1703 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1704 {
1705         struct cpsw_priv *priv = netdev_priv(ndev);
1706         priv->msg_enable = value;
1707 }
1708
1709 static int cpsw_get_ts_info(struct net_device *ndev,
1710                             struct ethtool_ts_info *info)
1711 {
1712 #ifdef CONFIG_TI_CPTS
1713         struct cpsw_priv *priv = netdev_priv(ndev);
1714
1715         info->so_timestamping =
1716                 SOF_TIMESTAMPING_TX_HARDWARE |
1717                 SOF_TIMESTAMPING_TX_SOFTWARE |
1718                 SOF_TIMESTAMPING_RX_HARDWARE |
1719                 SOF_TIMESTAMPING_RX_SOFTWARE |
1720                 SOF_TIMESTAMPING_SOFTWARE |
1721                 SOF_TIMESTAMPING_RAW_HARDWARE;
1722         info->phc_index = priv->cpts->phc_index;
1723         info->tx_types =
1724                 (1 << HWTSTAMP_TX_OFF) |
1725                 (1 << HWTSTAMP_TX_ON);
1726         info->rx_filters =
1727                 (1 << HWTSTAMP_FILTER_NONE) |
1728                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1729 #else
1730         info->so_timestamping =
1731                 SOF_TIMESTAMPING_TX_SOFTWARE |
1732                 SOF_TIMESTAMPING_RX_SOFTWARE |
1733                 SOF_TIMESTAMPING_SOFTWARE;
1734         info->phc_index = -1;
1735         info->tx_types = 0;
1736         info->rx_filters = 0;
1737 #endif
1738         return 0;
1739 }
1740
1741 static int cpsw_get_settings(struct net_device *ndev,
1742                              struct ethtool_cmd *ecmd)
1743 {
1744         struct cpsw_priv *priv = netdev_priv(ndev);
1745         int slave_no = cpsw_slave_index(priv);
1746
1747         if (priv->slaves[slave_no].phy)
1748                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1749         else
1750                 return -EOPNOTSUPP;
1751 }
1752
1753 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1754 {
1755         struct cpsw_priv *priv = netdev_priv(ndev);
1756         int slave_no = cpsw_slave_index(priv);
1757
1758         if (priv->slaves[slave_no].phy)
1759                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1760         else
1761                 return -EOPNOTSUPP;
1762 }
1763
1764 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1765 {
1766         struct cpsw_priv *priv = netdev_priv(ndev);
1767         int slave_no = cpsw_slave_index(priv);
1768
1769         wol->supported = 0;
1770         wol->wolopts = 0;
1771
1772         if (priv->slaves[slave_no].phy)
1773                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1774 }
1775
1776 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1777 {
1778         struct cpsw_priv *priv = netdev_priv(ndev);
1779         int slave_no = cpsw_slave_index(priv);
1780
1781         if (priv->slaves[slave_no].phy)
1782                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1783         else
1784                 return -EOPNOTSUPP;
1785 }
1786
1787 static const struct ethtool_ops cpsw_ethtool_ops = {
1788         .get_drvinfo    = cpsw_get_drvinfo,
1789         .get_msglevel   = cpsw_get_msglevel,
1790         .set_msglevel   = cpsw_set_msglevel,
1791         .get_link       = ethtool_op_get_link,
1792         .get_ts_info    = cpsw_get_ts_info,
1793         .get_settings   = cpsw_get_settings,
1794         .set_settings   = cpsw_set_settings,
1795         .get_coalesce   = cpsw_get_coalesce,
1796         .set_coalesce   = cpsw_set_coalesce,
1797         .get_sset_count         = cpsw_get_sset_count,
1798         .get_strings            = cpsw_get_strings,
1799         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1800         .get_wol        = cpsw_get_wol,
1801         .set_wol        = cpsw_set_wol,
1802         .get_regs_len   = cpsw_get_regs_len,
1803         .get_regs       = cpsw_get_regs,
1804 };
1805
1806 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1807                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1808 {
1809         void __iomem            *regs = priv->regs;
1810         int                     slave_num = slave->slave_num;
1811         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1812
1813         slave->data     = data;
1814         slave->regs     = regs + slave_reg_ofs;
1815         slave->sliver   = regs + sliver_reg_ofs;
1816         slave->port_vlan = data->dual_emac_res_vlan;
1817 }
1818
1819 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1820                          struct platform_device *pdev)
1821 {
1822         struct device_node *node = pdev->dev.of_node;
1823         struct device_node *slave_node;
1824         int i = 0, ret;
1825         u32 prop;
1826
1827         if (!node)
1828                 return -EINVAL;
1829
1830         if (of_property_read_u32(node, "slaves", &prop)) {
1831                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1832                 return -EINVAL;
1833         }
1834         data->slaves = prop;
1835
1836         if (of_property_read_u32(node, "active_slave", &prop)) {
1837                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1838                 return -EINVAL;
1839         }
1840         data->active_slave = prop;
1841
1842         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1843                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1844                 return -EINVAL;
1845         }
1846         data->cpts_clock_mult = prop;
1847
1848         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1849                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1850                 return -EINVAL;
1851         }
1852         data->cpts_clock_shift = prop;
1853
1854         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1855                                         * sizeof(struct cpsw_slave_data),
1856                                         GFP_KERNEL);
1857         if (!data->slave_data)
1858                 return -ENOMEM;
1859
1860         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1861                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1862                 return -EINVAL;
1863         }
1864         data->channels = prop;
1865
1866         if (of_property_read_u32(node, "ale_entries", &prop)) {
1867                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1868                 return -EINVAL;
1869         }
1870         data->ale_entries = prop;
1871
1872         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1873                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1874                 return -EINVAL;
1875         }
1876         data->bd_ram_size = prop;
1877
1878         if (of_property_read_u32(node, "rx_descs", &prop)) {
1879                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1880                 return -EINVAL;
1881         }
1882         data->rx_descs = prop;
1883
1884         if (of_property_read_u32(node, "mac_control", &prop)) {
1885                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
1886                 return -EINVAL;
1887         }
1888         data->mac_control = prop;
1889
1890         if (of_property_read_bool(node, "dual_emac"))
1891                 data->dual_emac = 1;
1892
1893         /*
1894          * Populate all the child nodes here...
1895          */
1896         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1897         /* We do not want to force this, as in some cases may not have child */
1898         if (ret)
1899                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
1900
1901         for_each_child_of_node(node, slave_node) {
1902                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1903                 const void *mac_addr = NULL;
1904                 u32 phyid;
1905                 int lenp;
1906                 const __be32 *parp;
1907                 struct device_node *mdio_node;
1908                 struct platform_device *mdio;
1909
1910                 /* This is no slave child node, continue */
1911                 if (strcmp(slave_node->name, "slave"))
1912                         continue;
1913
1914                 parp = of_get_property(slave_node, "phy_id", &lenp);
1915                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1916                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
1917                         return -EINVAL;
1918                 }
1919                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1920                 phyid = be32_to_cpup(parp+1);
1921                 mdio = of_find_device_by_node(mdio_node);
1922                 of_node_put(mdio_node);
1923                 if (!mdio) {
1924                         pr_err("Missing mdio platform device\n");
1925                         return -EINVAL;
1926                 }
1927                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1928                          PHY_ID_FMT, mdio->name, phyid);
1929
1930                 mac_addr = of_get_mac_address(slave_node);
1931                 if (mac_addr)
1932                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1933
1934                 slave_data->phy_if = of_get_phy_mode(slave_node);
1935                 if (slave_data->phy_if < 0) {
1936                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
1937                                 i);
1938                         return slave_data->phy_if;
1939                 }
1940
1941                 if (data->dual_emac) {
1942                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1943                                                  &prop)) {
1944                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
1945                                 slave_data->dual_emac_res_vlan = i+1;
1946                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
1947                                         slave_data->dual_emac_res_vlan, i);
1948                         } else {
1949                                 slave_data->dual_emac_res_vlan = prop;
1950                         }
1951                 }
1952
1953                 i++;
1954                 if (i == data->slaves)
1955                         break;
1956         }
1957
1958         return 0;
1959 }
1960
1961 static int cpsw_probe_dual_emac(struct platform_device *pdev,
1962                                 struct cpsw_priv *priv)
1963 {
1964         struct cpsw_platform_data       *data = &priv->data;
1965         struct net_device               *ndev;
1966         struct cpsw_priv                *priv_sl2;
1967         int ret = 0, i;
1968
1969         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1970         if (!ndev) {
1971                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
1972                 return -ENOMEM;
1973         }
1974
1975         priv_sl2 = netdev_priv(ndev);
1976         spin_lock_init(&priv_sl2->lock);
1977         priv_sl2->data = *data;
1978         priv_sl2->pdev = pdev;
1979         priv_sl2->ndev = ndev;
1980         priv_sl2->dev  = &ndev->dev;
1981         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1982         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1983
1984         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1985                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1986                         ETH_ALEN);
1987                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1988         } else {
1989                 random_ether_addr(priv_sl2->mac_addr);
1990                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1991         }
1992         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1993
1994         priv_sl2->slaves = priv->slaves;
1995         priv_sl2->clk = priv->clk;
1996
1997         priv_sl2->coal_intvl = 0;
1998         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1999
2000         priv_sl2->regs = priv->regs;
2001         priv_sl2->host_port = priv->host_port;
2002         priv_sl2->host_port_regs = priv->host_port_regs;
2003         priv_sl2->wr_regs = priv->wr_regs;
2004         priv_sl2->hw_stats = priv->hw_stats;
2005         priv_sl2->dma = priv->dma;
2006         priv_sl2->txch = priv->txch;
2007         priv_sl2->rxch = priv->rxch;
2008         priv_sl2->ale = priv->ale;
2009         priv_sl2->emac_port = 1;
2010         priv->slaves[1].ndev = ndev;
2011         priv_sl2->cpts = priv->cpts;
2012         priv_sl2->version = priv->version;
2013
2014         for (i = 0; i < priv->num_irqs; i++) {
2015                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2016                 priv_sl2->num_irqs = priv->num_irqs;
2017         }
2018         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2019
2020         ndev->netdev_ops = &cpsw_netdev_ops;
2021         ndev->ethtool_ops = &cpsw_ethtool_ops;
2022         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2023
2024         /* register the network device */
2025         SET_NETDEV_DEV(ndev, &pdev->dev);
2026         ret = register_netdev(ndev);
2027         if (ret) {
2028                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2029                 free_netdev(ndev);
2030                 ret = -ENODEV;
2031         }
2032
2033         return ret;
2034 }
2035
2036 static int cpsw_probe(struct platform_device *pdev)
2037 {
2038         struct cpsw_platform_data       *data;
2039         struct net_device               *ndev;
2040         struct cpsw_priv                *priv;
2041         struct cpdma_params             dma_params;
2042         struct cpsw_ale_params          ale_params;
2043         void __iomem                    *ss_regs;
2044         struct resource                 *res, *ss_res;
2045         u32 slave_offset, sliver_offset, slave_size;
2046         int ret = 0, i, k = 0;
2047
2048         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2049         if (!ndev) {
2050                 dev_err(&pdev->dev, "error allocating net_device\n");
2051                 return -ENOMEM;
2052         }
2053
2054         platform_set_drvdata(pdev, ndev);
2055         priv = netdev_priv(ndev);
2056         spin_lock_init(&priv->lock);
2057         priv->pdev = pdev;
2058         priv->ndev = ndev;
2059         priv->dev  = &ndev->dev;
2060         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2061         priv->rx_packet_max = max(rx_packet_max, 128);
2062         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2063         priv->irq_enabled = true;
2064         if (!priv->cpts) {
2065                 dev_err(&pdev->dev, "error allocating cpts\n");
2066                 goto clean_ndev_ret;
2067         }
2068
2069         /*
2070          * This may be required here for child devices.
2071          */
2072         pm_runtime_enable(&pdev->dev);
2073
2074         /* Select default pin state */
2075         pinctrl_pm_select_default_state(&pdev->dev);
2076
2077         if (cpsw_probe_dt(&priv->data, pdev)) {
2078                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2079                 ret = -ENODEV;
2080                 goto clean_runtime_disable_ret;
2081         }
2082         data = &priv->data;
2083
2084         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2085                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2086                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2087         } else {
2088                 eth_random_addr(priv->mac_addr);
2089                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2090         }
2091
2092         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2093
2094         priv->slaves = devm_kzalloc(&pdev->dev,
2095                                     sizeof(struct cpsw_slave) * data->slaves,
2096                                     GFP_KERNEL);
2097         if (!priv->slaves) {
2098                 ret = -ENOMEM;
2099                 goto clean_runtime_disable_ret;
2100         }
2101         for (i = 0; i < data->slaves; i++)
2102                 priv->slaves[i].slave_num = i;
2103
2104         priv->slaves[0].ndev = ndev;
2105         priv->emac_port = 0;
2106
2107         priv->clk = devm_clk_get(&pdev->dev, "fck");
2108         if (IS_ERR(priv->clk)) {
2109                 dev_err(priv->dev, "fck is not found\n");
2110                 ret = -ENODEV;
2111                 goto clean_runtime_disable_ret;
2112         }
2113         priv->coal_intvl = 0;
2114         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2115
2116         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2117         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2118         if (IS_ERR(ss_regs)) {
2119                 ret = PTR_ERR(ss_regs);
2120                 goto clean_runtime_disable_ret;
2121         }
2122         priv->regs = ss_regs;
2123         priv->host_port = HOST_PORT_NUM;
2124
2125         /* Need to enable clocks with runtime PM api to access module
2126          * registers
2127          */
2128         pm_runtime_get_sync(&pdev->dev);
2129         priv->version = readl(&priv->regs->id_ver);
2130         pm_runtime_put_sync(&pdev->dev);
2131
2132         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2133         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2134         if (IS_ERR(priv->wr_regs)) {
2135                 ret = PTR_ERR(priv->wr_regs);
2136                 goto clean_runtime_disable_ret;
2137         }
2138
2139         memset(&dma_params, 0, sizeof(dma_params));
2140         memset(&ale_params, 0, sizeof(ale_params));
2141
2142         switch (priv->version) {
2143         case CPSW_VERSION_1:
2144                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2145                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2146                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2147                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2148                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2149                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2150                 slave_offset         = CPSW1_SLAVE_OFFSET;
2151                 slave_size           = CPSW1_SLAVE_SIZE;
2152                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2153                 dma_params.desc_mem_phys = 0;
2154                 break;
2155         case CPSW_VERSION_2:
2156         case CPSW_VERSION_3:
2157         case CPSW_VERSION_4:
2158                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2159                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2160                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2161                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2162                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2163                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2164                 slave_offset         = CPSW2_SLAVE_OFFSET;
2165                 slave_size           = CPSW2_SLAVE_SIZE;
2166                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2167                 dma_params.desc_mem_phys =
2168                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2169                 break;
2170         default:
2171                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2172                 ret = -ENODEV;
2173                 goto clean_runtime_disable_ret;
2174         }
2175         for (i = 0; i < priv->data.slaves; i++) {
2176                 struct cpsw_slave *slave = &priv->slaves[i];
2177                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2178                 slave_offset  += slave_size;
2179                 sliver_offset += SLIVER_SIZE;
2180         }
2181
2182         dma_params.dev          = &pdev->dev;
2183         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2184         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2185         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2186         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2187         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2188
2189         dma_params.num_chan             = data->channels;
2190         dma_params.has_soft_reset       = true;
2191         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2192         dma_params.desc_mem_size        = data->bd_ram_size;
2193         dma_params.desc_align           = 16;
2194         dma_params.has_ext_regs         = true;
2195         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2196
2197         priv->dma = cpdma_ctlr_create(&dma_params);
2198         if (!priv->dma) {
2199                 dev_err(priv->dev, "error initializing dma\n");
2200                 ret = -ENOMEM;
2201                 goto clean_runtime_disable_ret;
2202         }
2203
2204         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2205                                        cpsw_tx_handler);
2206         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2207                                        cpsw_rx_handler);
2208
2209         if (WARN_ON(!priv->txch || !priv->rxch)) {
2210                 dev_err(priv->dev, "error initializing dma channels\n");
2211                 ret = -ENOMEM;
2212                 goto clean_dma_ret;
2213         }
2214
2215         ale_params.dev                  = &ndev->dev;
2216         ale_params.ale_ageout           = ale_ageout;
2217         ale_params.ale_entries          = data->ale_entries;
2218         ale_params.ale_ports            = data->slaves;
2219
2220         priv->ale = cpsw_ale_create(&ale_params);
2221         if (!priv->ale) {
2222                 dev_err(priv->dev, "error initializing ale engine\n");
2223                 ret = -ENODEV;
2224                 goto clean_dma_ret;
2225         }
2226
2227         ndev->irq = platform_get_irq(pdev, 0);
2228         if (ndev->irq < 0) {
2229                 dev_err(priv->dev, "error getting irq resource\n");
2230                 ret = -ENOENT;
2231                 goto clean_ale_ret;
2232         }
2233
2234         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2235                 for (i = res->start; i <= res->end; i++) {
2236                         if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0,
2237                                              dev_name(&pdev->dev), priv)) {
2238                                 dev_err(priv->dev, "error attaching irq\n");
2239                                 goto clean_ale_ret;
2240                         }
2241                         priv->irqs_table[k] = i;
2242                         priv->num_irqs = k + 1;
2243                 }
2244                 k++;
2245         }
2246
2247         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2248
2249         ndev->netdev_ops = &cpsw_netdev_ops;
2250         ndev->ethtool_ops = &cpsw_ethtool_ops;
2251         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2252
2253         /* register the network device */
2254         SET_NETDEV_DEV(ndev, &pdev->dev);
2255         ret = register_netdev(ndev);
2256         if (ret) {
2257                 dev_err(priv->dev, "error registering net device\n");
2258                 ret = -ENODEV;
2259                 goto clean_ale_ret;
2260         }
2261
2262         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2263                     &ss_res->start, ndev->irq);
2264
2265         if (priv->data.dual_emac) {
2266                 ret = cpsw_probe_dual_emac(pdev, priv);
2267                 if (ret) {
2268                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2269                         goto clean_ale_ret;
2270                 }
2271         }
2272
2273         return 0;
2274
2275 clean_ale_ret:
2276         cpsw_ale_destroy(priv->ale);
2277 clean_dma_ret:
2278         cpdma_chan_destroy(priv->txch);
2279         cpdma_chan_destroy(priv->rxch);
2280         cpdma_ctlr_destroy(priv->dma);
2281 clean_runtime_disable_ret:
2282         pm_runtime_disable(&pdev->dev);
2283 clean_ndev_ret:
2284         free_netdev(priv->ndev);
2285         return ret;
2286 }
2287
2288 static int cpsw_remove(struct platform_device *pdev)
2289 {
2290         struct net_device *ndev = platform_get_drvdata(pdev);
2291         struct cpsw_priv *priv = netdev_priv(ndev);
2292
2293         if (priv->data.dual_emac)
2294                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2295         unregister_netdev(ndev);
2296
2297         cpsw_ale_destroy(priv->ale);
2298         cpdma_chan_destroy(priv->txch);
2299         cpdma_chan_destroy(priv->rxch);
2300         cpdma_ctlr_destroy(priv->dma);
2301         pm_runtime_disable(&pdev->dev);
2302         if (priv->data.dual_emac)
2303                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2304         free_netdev(ndev);
2305         return 0;
2306 }
2307
2308 static int cpsw_suspend(struct device *dev)
2309 {
2310         struct platform_device  *pdev = to_platform_device(dev);
2311         struct net_device       *ndev = platform_get_drvdata(pdev);
2312         struct cpsw_priv        *priv = netdev_priv(ndev);
2313
2314         if (netif_running(ndev))
2315                 cpsw_ndo_stop(ndev);
2316
2317         for_each_slave(priv, soft_reset_slave);
2318
2319         pm_runtime_put_sync(&pdev->dev);
2320
2321         /* Select sleep pin state */
2322         pinctrl_pm_select_sleep_state(&pdev->dev);
2323
2324         return 0;
2325 }
2326
2327 static int cpsw_resume(struct device *dev)
2328 {
2329         struct platform_device  *pdev = to_platform_device(dev);
2330         struct net_device       *ndev = platform_get_drvdata(pdev);
2331
2332         pm_runtime_get_sync(&pdev->dev);
2333
2334         /* Select default pin state */
2335         pinctrl_pm_select_default_state(&pdev->dev);
2336
2337         if (netif_running(ndev))
2338                 cpsw_ndo_open(ndev);
2339         return 0;
2340 }
2341
2342 static const struct dev_pm_ops cpsw_pm_ops = {
2343         .suspend        = cpsw_suspend,
2344         .resume         = cpsw_resume,
2345 };
2346
2347 static const struct of_device_id cpsw_of_mtable[] = {
2348         { .compatible = "ti,cpsw", },
2349         { /* sentinel */ },
2350 };
2351 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2352
2353 static struct platform_driver cpsw_driver = {
2354         .driver = {
2355                 .name    = "cpsw",
2356                 .owner   = THIS_MODULE,
2357                 .pm      = &cpsw_pm_ops,
2358                 .of_match_table = cpsw_of_mtable,
2359         },
2360         .probe = cpsw_probe,
2361         .remove = cpsw_remove,
2362 };
2363
2364 static int __init cpsw_init(void)
2365 {
2366         return platform_driver_register(&cpsw_driver);
2367 }
2368 late_initcall(cpsw_init);
2369
2370 static void __exit cpsw_exit(void)
2371 {
2372         platform_driver_unregister(&cpsw_driver);
2373 }
2374 module_exit(cpsw_exit);
2375
2376 MODULE_LICENSE("GPL");
2377 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2378 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2379 MODULE_DESCRIPTION("TI CPSW Ethernet driver");