drivers/net/ethernet/ti/davinci_cpdma.c

   1 /*
   2  * Texas Instruments CPDMA Driver
   3  *
   4  * Copyright (C) 2010 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/device.h>
  18 #include <linux/module.h>
  19 #include <linux/slab.h>
  20 #include <linux/err.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/io.h>
  23 #include <linux/delay.h>
  24 #include <linux/genalloc.h>
  25 #include "davinci_cpdma.h"
  26
  27 /* DMA Registers */
  28 #define CPDMA_TXIDVER           0x00
  29 #define CPDMA_TXCONTROL         0x04
  30 #define CPDMA_TXTEARDOWN        0x08
  31 #define CPDMA_RXIDVER           0x10
  32 #define CPDMA_RXCONTROL         0x14
  33 #define CPDMA_SOFTRESET         0x1c
  34 #define CPDMA_RXTEARDOWN        0x18
  35 #define CPDMA_TXINTSTATRAW      0x80
  36 #define CPDMA_TXINTSTATMASKED   0x84
  37 #define CPDMA_TXINTMASKSET      0x88
  38 #define CPDMA_TXINTMASKCLEAR    0x8c
  39 #define CPDMA_MACINVECTOR       0x90
  40 #define CPDMA_MACEOIVECTOR      0x94
  41 #define CPDMA_RXINTSTATRAW      0xa0
  42 #define CPDMA_RXINTSTATMASKED   0xa4
  43 #define CPDMA_RXINTMASKSET      0xa8
  44 #define CPDMA_RXINTMASKCLEAR    0xac
  45 #define CPDMA_DMAINTSTATRAW     0xb0
  46 #define CPDMA_DMAINTSTATMASKED  0xb4
  47 #define CPDMA_DMAINTMASKSET     0xb8
  48 #define CPDMA_DMAINTMASKCLEAR   0xbc
  49 #define CPDMA_DMAINT_HOSTERR    BIT(1)
  50
  51 /* the following exist only if has_ext_regs is set */
  52 #define CPDMA_DMACONTROL        0x20
  53 #define CPDMA_DMASTATUS         0x24
  54 #define CPDMA_RXBUFFOFS         0x28
  55 #define CPDMA_EM_CONTROL        0x2c
  56
  57 /* Descriptor mode bits */
  58 #define CPDMA_DESC_SOP          BIT(31)
  59 #define CPDMA_DESC_EOP          BIT(30)
  60 #define CPDMA_DESC_OWNER        BIT(29)
  61 #define CPDMA_DESC_EOQ          BIT(28)
  62 #define CPDMA_DESC_TD_COMPLETE  BIT(27)
  63 #define CPDMA_DESC_PASS_CRC     BIT(26)
  64 #define CPDMA_DESC_TO_PORT_EN   BIT(20)
  65 #define CPDMA_TO_PORT_SHIFT     16
  66 #define CPDMA_DESC_PORT_MASK    (BIT(18) | BIT(17) | BIT(16))
  67 #define CPDMA_DESC_CRC_LEN      4
  68
  69 #define CPDMA_TEARDOWN_VALUE    0xfffffffc
  70
  71 struct cpdma_desc {
  72         /* hardware fields */
  73         u32                     hw_next;
  74         u32                     hw_buffer;
  75         u32                     hw_len;
  76         u32                     hw_mode;
  77         /* software fields */
  78         void                    *sw_token;
  79         u32                     sw_buffer;
  80         u32                     sw_len;
  81 };
  82
  83 struct cpdma_desc_pool {
  84         phys_addr_t             phys;
  85         dma_addr_t              hw_addr;
  86         void __iomem            *iomap;         /* ioremap map */
  87         void                    *cpumap;        /* dma_alloc map */
  88         int                     desc_size, mem_size;
  89         int                     num_desc;
  90         struct device           *dev;
  91         struct gen_pool         *gen_pool;
  92 };
  93
  94 enum cpdma_state {
  95         CPDMA_STATE_IDLE,
  96         CPDMA_STATE_ACTIVE,
  97         CPDMA_STATE_TEARDOWN,
  98 };
  99
 100 struct cpdma_ctlr {
 101         enum cpdma_state        state;
 102         struct cpdma_params     params;
 103         struct device           *dev;
 104         struct cpdma_desc_pool  *pool;
 105         spinlock_t              lock;
 106         struct cpdma_chan       *channels[2 * CPDMA_MAX_CHANNELS];
 107         int chan_num;
 108 };
 109
 110 struct cpdma_chan {
 111         struct cpdma_desc __iomem       *head, *tail;
 112         void __iomem                    *hdp, *cp, *rxfree;
 113         enum cpdma_state                state;
 114         struct cpdma_ctlr               *ctlr;
 115         int                             chan_num;
 116         spinlock_t                      lock;
 117         int                             count;
 118         u32                             desc_num;
 119         u32                             mask;
 120         cpdma_handler_fn                handler;
 121         enum dma_data_direction         dir;
 122         struct cpdma_chan_stats         stats;
 123         /* offsets into dmaregs */
 124         int     int_set, int_clear, td;
 125 };
 126
 127 /* The following make access to common cpdma_ctlr params more readable */
 128 #define dmaregs         params.dmaregs
 129 #define num_chan        params.num_chan
 130
 131 /* various accessors */
 132 #define dma_reg_read(ctlr, ofs)         __raw_readl((ctlr)->dmaregs + (ofs))
 133 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 134 #define desc_read(desc, fld)            __raw_readl(&(desc)->fld)
 135 #define dma_reg_write(ctlr, ofs, v)     __raw_writel(v, (ctlr)->dmaregs + (ofs))
 136 #define chan_write(chan, fld, v)        __raw_writel(v, (chan)->fld)
 137 #define desc_write(desc, fld, v)        __raw_writel((u32)(v), &(desc)->fld)
 138
 139 #define cpdma_desc_to_port(chan, mode, directed)                        \
 140         do {                                                            \
 141                 if (!is_rx_chan(chan) && ((directed == 1) ||            \
 142                                           (directed == 2)))             \
 143                         mode |= (CPDMA_DESC_TO_PORT_EN |                \
 144                                  (directed << CPDMA_TO_PORT_SHIFT));    \
 145         } while (0)
 146
 147 static void cpdma_desc_pool_destroy(struct cpdma_desc_pool *pool)
 148 {
 149         if (!pool)
 150                 return;
 151
 152         WARN(gen_pool_size(pool->gen_pool) != gen_pool_avail(pool->gen_pool),
 153              "cpdma_desc_pool size %d != avail %d",
 154              gen_pool_size(pool->gen_pool),
 155              gen_pool_avail(pool->gen_pool));
 156         if (pool->cpumap)
 157                 dma_free_coherent(pool->dev, pool->mem_size, pool->cpumap,
 158                                   pool->phys);
 159         else
 160                 iounmap(pool->iomap);
 161 }
 162
 163 /*
 164  * Utility constructs for a cpdma descriptor pool.  Some devices (e.g. davinci
 165  * emac) have dedicated on-chip memory for these descriptors.  Some other
 166  * devices (e.g. cpsw switches) use plain old memory.  Descriptor pools
 167  * abstract out these details
 168  */
 169 static struct cpdma_desc_pool *
 170 cpdma_desc_pool_create(struct device *dev, u32 phys, dma_addr_t hw_addr,
 171                                 int size, int align)
 172 {
 173         struct cpdma_desc_pool *pool;
 174         int ret;
 175
 176         pool = devm_kzalloc(dev, sizeof(*pool), GFP_KERNEL);
 177         if (!pool)
 178                 goto gen_pool_create_fail;
 179
 180         pool->dev       = dev;
 181         pool->mem_size  = size;
 182         pool->desc_size = ALIGN(sizeof(struct cpdma_desc), align);
 183         pool->num_desc  = size / pool->desc_size;
 184
 185         pool->gen_pool = devm_gen_pool_create(dev, ilog2(pool->desc_size), -1,
 186                                               "cpdma");
 187         if (IS_ERR(pool->gen_pool)) {
 188                 dev_err(dev, "pool create failed %ld\n",
 189                         PTR_ERR(pool->gen_pool));
 190                 goto gen_pool_create_fail;
 191         }
 192
 193         if (phys) {
 194                 pool->phys  = phys;
 195                 pool->iomap = ioremap(phys, size); /* should be memremap? */
 196                 pool->hw_addr = hw_addr;
 197         } else {
 198                 pool->cpumap = dma_alloc_coherent(dev, size, &pool->hw_addr,
 199                                                   GFP_KERNEL);
 200                 pool->iomap = (void __iomem __force *)pool->cpumap;
 201                 pool->phys = pool->hw_addr; /* assumes no IOMMU, don't use this value */
 202         }
 203
 204         if (!pool->iomap)
 205                 goto gen_pool_create_fail;
 206
 207         ret = gen_pool_add_virt(pool->gen_pool, (unsigned long)pool->iomap,
 208                                 pool->phys, pool->mem_size, -1);
 209         if (ret < 0) {
 210                 dev_err(dev, "pool add failed %d\n", ret);
 211                 goto gen_pool_add_virt_fail;
 212         }
 213
 214         return pool;
 215
 216 gen_pool_add_virt_fail:
 217         cpdma_desc_pool_destroy(pool);
 218 gen_pool_create_fail:
 219         return NULL;
 220 }
 221
 222 static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool,
 223                   struct cpdma_desc __iomem *desc)
 224 {
 225         if (!desc)
 226                 return 0;
 227         return pool->hw_addr + (__force long)desc - (__force long)pool->iomap;
 228 }
 229
 230 static inline struct cpdma_desc __iomem *
 231 desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma)
 232 {
 233         return dma ? pool->iomap + dma - pool->hw_addr : NULL;
 234 }
 235
 236 static struct cpdma_desc __iomem *
 237 cpdma_desc_alloc(struct cpdma_desc_pool *pool)
 238 {
 239         return (struct cpdma_desc __iomem *)
 240                 gen_pool_alloc(pool->gen_pool, pool->desc_size);
 241 }
 242
 243 static void cpdma_desc_free(struct cpdma_desc_pool *pool,
 244                             struct cpdma_desc __iomem *desc, int num_desc)
 245 {
 246         gen_pool_free(pool->gen_pool, (unsigned long)desc, pool->desc_size);
 247 }
 248
 249 struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params)
 250 {
 251         struct cpdma_ctlr *ctlr;
 252
 253         ctlr = devm_kzalloc(params->dev, sizeof(*ctlr), GFP_KERNEL);
 254         if (!ctlr)
 255                 return NULL;
 256
 257         ctlr->state = CPDMA_STATE_IDLE;
 258         ctlr->params = *params;
 259         ctlr->dev = params->dev;
 260         ctlr->chan_num = 0;
 261         spin_lock_init(&ctlr->lock);
 262
 263         ctlr->pool = cpdma_desc_pool_create(ctlr->dev,
 264                                             ctlr->params.desc_mem_phys,
 265                                             ctlr->params.desc_hw_addr,
 266                                             ctlr->params.desc_mem_size,
 267                                             ctlr->params.desc_align);
 268         if (!ctlr->pool)
 269                 return NULL;
 270
 271         if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS))
 272                 ctlr->num_chan = CPDMA_MAX_CHANNELS;
 273         return ctlr;
 274 }
 275 EXPORT_SYMBOL_GPL(cpdma_ctlr_create);
 276
 277 int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
 278 {
 279         unsigned long flags;
 280         int i;
 281
 282         spin_lock_irqsave(&ctlr->lock, flags);
 283         if (ctlr->state != CPDMA_STATE_IDLE) {
 284                 spin_unlock_irqrestore(&ctlr->lock, flags);
 285                 return -EBUSY;
 286         }
 287
 288         if (ctlr->params.has_soft_reset) {
 289                 unsigned timeout = 10 * 100;
 290
 291                 dma_reg_write(ctlr, CPDMA_SOFTRESET, 1);
 292                 while (timeout) {
 293                         if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0)
 294                                 break;
 295                         udelay(10);
 296                         timeout--;
 297                 }
 298                 WARN_ON(!timeout);
 299         }
 300
 301         for (i = 0; i < ctlr->num_chan; i++) {
 302                 __raw_writel(0, ctlr->params.txhdp + 4 * i);
 303                 __raw_writel(0, ctlr->params.rxhdp + 4 * i);
 304                 __raw_writel(0, ctlr->params.txcp + 4 * i);
 305                 __raw_writel(0, ctlr->params.rxcp + 4 * i);
 306         }
 307
 308         dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
 309         dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
 310
 311         dma_reg_write(ctlr, CPDMA_TXCONTROL, 1);
 312         dma_reg_write(ctlr, CPDMA_RXCONTROL, 1);
 313
 314         ctlr->state = CPDMA_STATE_ACTIVE;
 315
 316         for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
 317                 if (ctlr->channels[i])
 318                         cpdma_chan_start(ctlr->channels[i]);
 319         }
 320         spin_unlock_irqrestore(&ctlr->lock, flags);
 321         return 0;
 322 }
 323 EXPORT_SYMBOL_GPL(cpdma_ctlr_start);
 324
 325 int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
 326 {
 327         unsigned long flags;
 328         int i;
 329
 330         spin_lock_irqsave(&ctlr->lock, flags);
 331         if (ctlr->state == CPDMA_STATE_TEARDOWN) {
 332                 spin_unlock_irqrestore(&ctlr->lock, flags);
 333                 return -EINVAL;
 334         }
 335
 336         ctlr->state = CPDMA_STATE_TEARDOWN;
 337         spin_unlock_irqrestore(&ctlr->lock, flags);
 338
 339         for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
 340                 if (ctlr->channels[i])
 341                         cpdma_chan_stop(ctlr->channels[i]);
 342         }
 343
 344         spin_lock_irqsave(&ctlr->lock, flags);
 345         dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
 346         dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
 347
 348         dma_reg_write(ctlr, CPDMA_TXCONTROL, 0);
 349         dma_reg_write(ctlr, CPDMA_RXCONTROL, 0);
 350
 351         ctlr->state = CPDMA_STATE_IDLE;
 352
 353         spin_unlock_irqrestore(&ctlr->lock, flags);
 354         return 0;
 355 }
 356 EXPORT_SYMBOL_GPL(cpdma_ctlr_stop);
 357
 358 int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr)
 359 {
 360         int ret = 0, i;
 361
 362         if (!ctlr)
 363                 return -EINVAL;
 364
 365         if (ctlr->state != CPDMA_STATE_IDLE)
 366                 cpdma_ctlr_stop(ctlr);
 367
 368         for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++)
 369                 cpdma_chan_destroy(ctlr->channels[i]);
 370
 371         cpdma_desc_pool_destroy(ctlr->pool);
 372         return ret;
 373 }
 374 EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy);
 375
 376 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
 377 {
 378         unsigned long flags;
 379         int i, reg;
 380
 381         spin_lock_irqsave(&ctlr->lock, flags);
 382         if (ctlr->state != CPDMA_STATE_ACTIVE) {
 383                 spin_unlock_irqrestore(&ctlr->lock, flags);
 384                 return -EINVAL;
 385         }
 386
 387         reg = enable ? CPDMA_DMAINTMASKSET : CPDMA_DMAINTMASKCLEAR;
 388         dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR);
 389
 390         for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
 391                 if (ctlr->channels[i])
 392                         cpdma_chan_int_ctrl(ctlr->channels[i], enable);
 393         }
 394
 395         spin_unlock_irqrestore(&ctlr->lock, flags);
 396         return 0;
 397 }
 398 EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl);
 399
 400 void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value)
 401 {
 402         dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value);
 403 }
 404 EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi);
 405
 406 u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr)
 407 {
 408         return dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED);
 409 }
 410 EXPORT_SYMBOL_GPL(cpdma_ctrl_rxchs_state);
 411
 412 u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr)
 413 {
 414         return dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED);
 415 }
 416 EXPORT_SYMBOL_GPL(cpdma_ctrl_txchs_state);
 417
 418 /**
 419  * cpdma_chan_split_pool - Splits ctrl pool between all channels.
 420  * Has to be called under ctlr lock
 421  */
 422 static void cpdma_chan_split_pool(struct cpdma_ctlr *ctlr)
 423 {
 424         struct cpdma_desc_pool *pool = ctlr->pool;
 425         struct cpdma_chan *chan;
 426         int ch_desc_num;
 427         int i;
 428
 429         if (!ctlr->chan_num)
 430                 return;
 431
 432         /* calculate average size of pool slice */
 433         ch_desc_num = pool->num_desc / ctlr->chan_num;
 434
 435         /* split ctlr pool */
 436         for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
 437                 chan = ctlr->channels[i];
 438                 if (chan)
 439                         chan->desc_num = ch_desc_num;
 440         }
 441 }
 442
 443 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
 444                                      cpdma_handler_fn handler)
 445 {
 446         struct cpdma_chan *chan;
 447         int offset = (chan_num % CPDMA_MAX_CHANNELS) * 4;
 448         unsigned long flags;
 449
 450         if (__chan_linear(chan_num) >= ctlr->num_chan)
 451                 return NULL;
 452
 453         chan = devm_kzalloc(ctlr->dev, sizeof(*chan), GFP_KERNEL);
 454         if (!chan)
 455                 return ERR_PTR(-ENOMEM);
 456
 457         spin_lock_irqsave(&ctlr->lock, flags);
 458         if (ctlr->channels[chan_num]) {
 459                 spin_unlock_irqrestore(&ctlr->lock, flags);
 460                 devm_kfree(ctlr->dev, chan);
 461                 return ERR_PTR(-EBUSY);
 462         }
 463
 464         chan->ctlr      = ctlr;
 465         chan->state     = CPDMA_STATE_IDLE;
 466         chan->chan_num  = chan_num;
 467         chan->handler   = handler;
 468         chan->desc_num = ctlr->pool->num_desc / 2;
 469
 470         if (is_rx_chan(chan)) {
 471                 chan->hdp       = ctlr->params.rxhdp + offset;
 472                 chan->cp        = ctlr->params.rxcp + offset;
 473                 chan->rxfree    = ctlr->params.rxfree + offset;
 474                 chan->int_set   = CPDMA_RXINTMASKSET;
 475                 chan->int_clear = CPDMA_RXINTMASKCLEAR;
 476                 chan->td        = CPDMA_RXTEARDOWN;
 477                 chan->dir       = DMA_FROM_DEVICE;
 478         } else {
 479                 chan->hdp       = ctlr->params.txhdp + offset;
 480                 chan->cp        = ctlr->params.txcp + offset;
 481                 chan->int_set   = CPDMA_TXINTMASKSET;
 482                 chan->int_clear = CPDMA_TXINTMASKCLEAR;
 483                 chan->td        = CPDMA_TXTEARDOWN;
 484                 chan->dir       = DMA_TO_DEVICE;
 485         }
 486         chan->mask = BIT(chan_linear(chan));
 487
 488         spin_lock_init(&chan->lock);
 489
 490         ctlr->channels[chan_num] = chan;
 491         ctlr->chan_num++;
 492
 493         cpdma_chan_split_pool(ctlr);
 494
 495         spin_unlock_irqrestore(&ctlr->lock, flags);
 496         return chan;
 497 }
 498 EXPORT_SYMBOL_GPL(cpdma_chan_create);
 499
 500 int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan)
 501 {
 502         unsigned long flags;
 503         int desc_num;
 504
 505         spin_lock_irqsave(&chan->lock, flags);
 506         desc_num = chan->desc_num;
 507         spin_unlock_irqrestore(&chan->lock, flags);
 508
 509         return desc_num;
 510 }
 511 EXPORT_SYMBOL_GPL(cpdma_chan_get_rx_buf_num);
 512
 513 int cpdma_chan_destroy(struct cpdma_chan *chan)
 514 {
 515         struct cpdma_ctlr *ctlr;
 516         unsigned long flags;
 517
 518         if (!chan)
 519                 return -EINVAL;
 520         ctlr = chan->ctlr;
 521
 522         spin_lock_irqsave(&ctlr->lock, flags);
 523         if (chan->state != CPDMA_STATE_IDLE)
 524                 cpdma_chan_stop(chan);
 525         ctlr->channels[chan->chan_num] = NULL;
 526         ctlr->chan_num--;
 527
 528         cpdma_chan_split_pool(ctlr);
 529
 530         spin_unlock_irqrestore(&ctlr->lock, flags);
 531         return 0;
 532 }
 533 EXPORT_SYMBOL_GPL(cpdma_chan_destroy);
 534
 535 int cpdma_chan_get_stats(struct cpdma_chan *chan,
 536                          struct cpdma_chan_stats *stats)
 537 {
 538         unsigned long flags;
 539         if (!chan)
 540                 return -EINVAL;
 541         spin_lock_irqsave(&chan->lock, flags);
 542         memcpy(stats, &chan->stats, sizeof(*stats));
 543         spin_unlock_irqrestore(&chan->lock, flags);
 544         return 0;
 545 }
 546 EXPORT_SYMBOL_GPL(cpdma_chan_get_stats);
 547
 548 static void __cpdma_chan_submit(struct cpdma_chan *chan,
 549                                 struct cpdma_desc __iomem *desc)
 550 {
 551         struct cpdma_ctlr               *ctlr = chan->ctlr;
 552         struct cpdma_desc __iomem       *prev = chan->tail;
 553         struct cpdma_desc_pool          *pool = ctlr->pool;
 554         dma_addr_t                      desc_dma;
 555         u32                             mode;
 556
 557         desc_dma = desc_phys(pool, desc);
 558
 559         /* simple case - idle channel */
 560         if (!chan->head) {
 561                 chan->stats.head_enqueue++;
 562                 chan->head = desc;
 563                 chan->tail = desc;
 564                 if (chan->state == CPDMA_STATE_ACTIVE)
 565                         chan_write(chan, hdp, desc_dma);
 566                 return;
 567         }
 568
 569         /* first chain the descriptor at the tail of the list */
 570         desc_write(prev, hw_next, desc_dma);
 571         chan->tail = desc;
 572         chan->stats.tail_enqueue++;
 573
 574         /* next check if EOQ has been triggered already */
 575         mode = desc_read(prev, hw_mode);
 576         if (((mode & (CPDMA_DESC_EOQ | CPDMA_DESC_OWNER)) == CPDMA_DESC_EOQ) &&
 577             (chan->state == CPDMA_STATE_ACTIVE)) {
 578                 desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ);
 579                 chan_write(chan, hdp, desc_dma);
 580                 chan->stats.misqueued++;
 581         }
 582 }
 583
 584 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
 585                       int len, int directed)
 586 {
 587         struct cpdma_ctlr               *ctlr = chan->ctlr;
 588         struct cpdma_desc __iomem       *desc;
 589         dma_addr_t                      buffer;
 590         unsigned long                   flags;
 591         u32                             mode;
 592         int                             ret = 0;
 593
 594         spin_lock_irqsave(&chan->lock, flags);
 595
 596         if (chan->state == CPDMA_STATE_TEARDOWN) {
 597                 ret = -EINVAL;
 598                 goto unlock_ret;
 599         }
 600
 601         if (chan->count >= chan->desc_num)      {
 602                 chan->stats.desc_alloc_fail++;
 603                 ret = -ENOMEM;
 604                 goto unlock_ret;
 605         }
 606
 607         desc = cpdma_desc_alloc(ctlr->pool);
 608         if (!desc) {
 609                 chan->stats.desc_alloc_fail++;
 610                 ret = -ENOMEM;
 611                 goto unlock_ret;
 612         }
 613
 614         if (len < ctlr->params.min_packet_size) {
 615                 len = ctlr->params.min_packet_size;
 616                 chan->stats.runt_transmit_buff++;
 617         }
 618
 619         buffer = dma_map_single(ctlr->dev, data, len, chan->dir);
 620         ret = dma_mapping_error(ctlr->dev, buffer);
 621         if (ret) {
 622                 cpdma_desc_free(ctlr->pool, desc, 1);
 623                 ret = -EINVAL;
 624                 goto unlock_ret;
 625         }
 626
 627         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 628         cpdma_desc_to_port(chan, mode, directed);
 629
 630         desc_write(desc, hw_next,   0);
 631         desc_write(desc, hw_buffer, buffer);
 632         desc_write(desc, hw_len,    len);
 633         desc_write(desc, hw_mode,   mode | len);
 634         desc_write(desc, sw_token,  token);
 635         desc_write(desc, sw_buffer, buffer);
 636         desc_write(desc, sw_len,    len);
 637
 638         __cpdma_chan_submit(chan, desc);
 639
 640         if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree)
 641                 chan_write(chan, rxfree, 1);
 642
 643         chan->count++;
 644
 645 unlock_ret:
 646         spin_unlock_irqrestore(&chan->lock, flags);
 647         return ret;
 648 }
 649 EXPORT_SYMBOL_GPL(cpdma_chan_submit);
 650
 651 bool cpdma_check_free_tx_desc(struct cpdma_chan *chan)
 652 {
 653         struct cpdma_ctlr       *ctlr = chan->ctlr;
 654         struct cpdma_desc_pool  *pool = ctlr->pool;
 655         bool                    free_tx_desc;
 656         unsigned long           flags;
 657
 658         spin_lock_irqsave(&chan->lock, flags);
 659         free_tx_desc = (chan->count < chan->desc_num) &&
 660                          gen_pool_avail(pool->gen_pool);
 661         spin_unlock_irqrestore(&chan->lock, flags);
 662         return free_tx_desc;
 663 }
 664 EXPORT_SYMBOL_GPL(cpdma_check_free_tx_desc);
 665
 666 static void __cpdma_chan_free(struct cpdma_chan *chan,
 667                               struct cpdma_desc __iomem *desc,
 668                               int outlen, int status)
 669 {
 670         struct cpdma_ctlr               *ctlr = chan->ctlr;
 671         struct cpdma_desc_pool          *pool = ctlr->pool;
 672         dma_addr_t                      buff_dma;
 673         int                             origlen;
 674         void                            *token;
 675
 676         token      = (void *)desc_read(desc, sw_token);
 677         buff_dma   = desc_read(desc, sw_buffer);
 678         origlen    = desc_read(desc, sw_len);
 679
 680         dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir);
 681         cpdma_desc_free(pool, desc, 1);
 682         (*chan->handler)(token, outlen, status);
 683 }
 684
 685 static int __cpdma_chan_process(struct cpdma_chan *chan)
 686 {
 687         struct cpdma_ctlr               *ctlr = chan->ctlr;
 688         struct cpdma_desc __iomem       *desc;
 689         int                             status, outlen;
 690         int                             cb_status = 0;
 691         struct cpdma_desc_pool          *pool = ctlr->pool;
 692         dma_addr_t                      desc_dma;
 693         unsigned long                   flags;
 694
 695         spin_lock_irqsave(&chan->lock, flags);
 696
 697         desc = chan->head;
 698         if (!desc) {
 699                 chan->stats.empty_dequeue++;
 700                 status = -ENOENT;
 701                 goto unlock_ret;
 702         }
 703         desc_dma = desc_phys(pool, desc);
 704
 705         status  = __raw_readl(&desc->hw_mode);
 706         outlen  = status & 0x7ff;
 707         if (status & CPDMA_DESC_OWNER) {
 708                 chan->stats.busy_dequeue++;
 709                 status = -EBUSY;
 710                 goto unlock_ret;
 711         }
 712
 713         if (status & CPDMA_DESC_PASS_CRC)
 714                 outlen -= CPDMA_DESC_CRC_LEN;
 715
 716         status  = status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE |
 717                             CPDMA_DESC_PORT_MASK);
 718
 719         chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
 720         chan_write(chan, cp, desc_dma);
 721         chan->count--;
 722         chan->stats.good_dequeue++;
 723
 724         if (status & CPDMA_DESC_EOQ) {
 725                 chan->stats.requeue++;
 726                 chan_write(chan, hdp, desc_phys(pool, chan->head));
 727         }
 728
 729         spin_unlock_irqrestore(&chan->lock, flags);
 730         if (unlikely(status & CPDMA_DESC_TD_COMPLETE))
 731                 cb_status = -ENOSYS;
 732         else
 733                 cb_status = status;
 734
 735         __cpdma_chan_free(chan, desc, outlen, cb_status);
 736         return status;
 737
 738 unlock_ret:
 739         spin_unlock_irqrestore(&chan->lock, flags);
 740         return status;
 741 }
 742
 743 int cpdma_chan_process(struct cpdma_chan *chan, int quota)
 744 {
 745         int used = 0, ret = 0;
 746
 747         if (chan->state != CPDMA_STATE_ACTIVE)
 748                 return -EINVAL;
 749
 750         while (used < quota) {
 751                 ret = __cpdma_chan_process(chan);
 752                 if (ret < 0)
 753                         break;
 754                 used++;
 755         }
 756         return used;
 757 }
 758 EXPORT_SYMBOL_GPL(cpdma_chan_process);
 759
 760 int cpdma_chan_start(struct cpdma_chan *chan)
 761 {
 762         struct cpdma_ctlr       *ctlr = chan->ctlr;
 763         struct cpdma_desc_pool  *pool = ctlr->pool;
 764         unsigned long           flags;
 765
 766         spin_lock_irqsave(&chan->lock, flags);
 767         if (chan->state != CPDMA_STATE_IDLE) {
 768                 spin_unlock_irqrestore(&chan->lock, flags);
 769                 return -EBUSY;
 770         }
 771         if (ctlr->state != CPDMA_STATE_ACTIVE) {
 772                 spin_unlock_irqrestore(&chan->lock, flags);
 773                 return -EINVAL;
 774         }
 775         dma_reg_write(ctlr, chan->int_set, chan->mask);
 776         chan->state = CPDMA_STATE_ACTIVE;
 777         if (chan->head) {
 778                 chan_write(chan, hdp, desc_phys(pool, chan->head));
 779                 if (chan->rxfree)
 780                         chan_write(chan, rxfree, chan->count);
 781         }
 782
 783         spin_unlock_irqrestore(&chan->lock, flags);
 784         return 0;
 785 }
 786 EXPORT_SYMBOL_GPL(cpdma_chan_start);
 787
 788 int cpdma_chan_stop(struct cpdma_chan *chan)
 789 {
 790         struct cpdma_ctlr       *ctlr = chan->ctlr;
 791         struct cpdma_desc_pool  *pool = ctlr->pool;
 792         unsigned long           flags;
 793         int                     ret;
 794         unsigned                timeout;
 795
 796         spin_lock_irqsave(&chan->lock, flags);
 797         if (chan->state == CPDMA_STATE_TEARDOWN) {
 798                 spin_unlock_irqrestore(&chan->lock, flags);
 799                 return -EINVAL;
 800         }
 801
 802         chan->state = CPDMA_STATE_TEARDOWN;
 803         dma_reg_write(ctlr, chan->int_clear, chan->mask);
 804
 805         /* trigger teardown */
 806         dma_reg_write(ctlr, chan->td, chan_linear(chan));
 807
 808         /* wait for teardown complete */
 809         timeout = 100 * 100; /* 100 ms */
 810         while (timeout) {
 811                 u32 cp = chan_read(chan, cp);
 812                 if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE)
 813                         break;
 814                 udelay(10);
 815                 timeout--;
 816         }
 817         WARN_ON(!timeout);
 818         chan_write(chan, cp, CPDMA_TEARDOWN_VALUE);
 819
 820         /* handle completed packets */
 821         spin_unlock_irqrestore(&chan->lock, flags);
 822         do {
 823                 ret = __cpdma_chan_process(chan);
 824                 if (ret < 0)
 825                         break;
 826         } while ((ret & CPDMA_DESC_TD_COMPLETE) == 0);
 827         spin_lock_irqsave(&chan->lock, flags);
 828
 829         /* remaining packets haven't been tx/rx'ed, clean them up */
 830         while (chan->head) {
 831                 struct cpdma_desc __iomem *desc = chan->head;
 832                 dma_addr_t next_dma;
 833
 834                 next_dma = desc_read(desc, hw_next);
 835                 chan->head = desc_from_phys(pool, next_dma);
 836                 chan->count--;
 837                 chan->stats.teardown_dequeue++;
 838
 839                 /* issue callback without locks held */
 840                 spin_unlock_irqrestore(&chan->lock, flags);
 841                 __cpdma_chan_free(chan, desc, 0, -ENOSYS);
 842                 spin_lock_irqsave(&chan->lock, flags);
 843         }
 844
 845         chan->state = CPDMA_STATE_IDLE;
 846         spin_unlock_irqrestore(&chan->lock, flags);
 847         return 0;
 848 }
 849 EXPORT_SYMBOL_GPL(cpdma_chan_stop);
 850
 851 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
 852 {
 853         unsigned long flags;
 854
 855         spin_lock_irqsave(&chan->lock, flags);
 856         if (chan->state != CPDMA_STATE_ACTIVE) {
 857                 spin_unlock_irqrestore(&chan->lock, flags);
 858                 return -EINVAL;
 859         }
 860
 861         dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear,
 862                       chan->mask);
 863         spin_unlock_irqrestore(&chan->lock, flags);
 864
 865         return 0;
 866 }
 867
 868 struct cpdma_control_info {
 869         u32             reg;
 870         u32             shift, mask;
 871         int             access;
 872 #define ACCESS_RO       BIT(0)
 873 #define ACCESS_WO       BIT(1)
 874 #define ACCESS_RW       (ACCESS_RO | ACCESS_WO)
 875 };
 876
 877 static struct cpdma_control_info controls[] = {
 878         [CPDMA_CMD_IDLE]          = {CPDMA_DMACONTROL,  3,  1,      ACCESS_WO},
 879         [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL,  4,  1,      ACCESS_RW},
 880         [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL,  2,  1,      ACCESS_RW},
 881         [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL,  1,  1,      ACCESS_RW},
 882         [CPDMA_TX_PRIO_FIXED]     = {CPDMA_DMACONTROL,  0,  1,      ACCESS_RW},
 883         [CPDMA_STAT_IDLE]         = {CPDMA_DMASTATUS,   31, 1,      ACCESS_RO},
 884         [CPDMA_STAT_TX_ERR_CODE]  = {CPDMA_DMASTATUS,   20, 0xf,    ACCESS_RW},
 885         [CPDMA_STAT_TX_ERR_CHAN]  = {CPDMA_DMASTATUS,   16, 0x7,    ACCESS_RW},
 886         [CPDMA_STAT_RX_ERR_CODE]  = {CPDMA_DMASTATUS,   12, 0xf,    ACCESS_RW},
 887         [CPDMA_STAT_RX_ERR_CHAN]  = {CPDMA_DMASTATUS,   8,  0x7,    ACCESS_RW},
 888         [CPDMA_RX_BUFFER_OFFSET]  = {CPDMA_RXBUFFOFS,   0,  0xffff, ACCESS_RW},
 889 };
 890
 891 int cpdma_control_get(struct cpdma_ctlr *ctlr, int control)
 892 {
 893         unsigned long flags;
 894         struct cpdma_control_info *info = &controls[control];
 895         int ret;
 896
 897         spin_lock_irqsave(&ctlr->lock, flags);
 898
 899         ret = -ENOTSUPP;
 900         if (!ctlr->params.has_ext_regs)
 901                 goto unlock_ret;
 902
 903         ret = -EINVAL;
 904         if (ctlr->state != CPDMA_STATE_ACTIVE)
 905                 goto unlock_ret;
 906
 907         ret = -ENOENT;
 908         if (control < 0 || control >= ARRAY_SIZE(controls))
 909                 goto unlock_ret;
 910
 911         ret = -EPERM;
 912         if ((info->access & ACCESS_RO) != ACCESS_RO)
 913                 goto unlock_ret;
 914
 915         ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask;
 916
 917 unlock_ret:
 918         spin_unlock_irqrestore(&ctlr->lock, flags);
 919         return ret;
 920 }
 921
 922 int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
 923 {
 924         unsigned long flags;
 925         struct cpdma_control_info *info = &controls[control];
 926         int ret;
 927         u32 val;
 928
 929         spin_lock_irqsave(&ctlr->lock, flags);
 930
 931         ret = -ENOTSUPP;
 932         if (!ctlr->params.has_ext_regs)
 933                 goto unlock_ret;
 934
 935         ret = -EINVAL;
 936         if (ctlr->state != CPDMA_STATE_ACTIVE)
 937                 goto unlock_ret;
 938
 939         ret = -ENOENT;
 940         if (control < 0 || control >= ARRAY_SIZE(controls))
 941                 goto unlock_ret;
 942
 943         ret = -EPERM;
 944         if ((info->access & ACCESS_WO) != ACCESS_WO)
 945                 goto unlock_ret;
 946
 947         val  = dma_reg_read(ctlr, info->reg);
 948         val &= ~(info->mask << info->shift);
 949         val |= (value & info->mask) << info->shift;
 950         dma_reg_write(ctlr, info->reg, val);
 951         ret = 0;
 952
 953 unlock_ret:
 954         spin_unlock_irqrestore(&ctlr->lock, flags);
 955         return ret;
 956 }
 957 EXPORT_SYMBOL_GPL(cpdma_control_set);
 958
 959 MODULE_LICENSE("GPL");