1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
3 Written 1998-2001 by Donald Becker.
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28 [link no longer provides useful info -jgarzik]
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #define DRV_NAME "via-rhine"
35 #define DRV_VERSION "1.5.0"
36 #define DRV_RELDATE "2010-10-09"
38 #include <linux/types.h>
40 /* A few user-configurable values.
41 These may be modified when a driver module is loaded. */
43 #define RHINE_MSG_DEFAULT \
46 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
47 Setting to > 1518 effectively disables this feature. */
48 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
49 defined(CONFIG_SPARC) || defined(__ia64__) || \
50 defined(__sh__) || defined(__mips__)
51 static int rx_copybreak = 1518;
53 static int rx_copybreak;
56 /* Work-around for broken BIOSes: they are unable to get the chip back out of
57 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
61 * In case you are looking for 'options[]' or 'full_duplex[]', they
62 * are gone. Use ethtool(8) instead.
65 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
66 The Rhine has a 64 element 8390-like hash table. */
67 static const int multicast_filter_limit = 32;
70 /* Operational parameters that are set at compile time. */
72 /* Keep the ring sizes a power of two for compile efficiency.
73 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
74 Making the Tx ring too large decreases the effectiveness of channel
75 bonding and packet priority.
76 There are no ill effects from too-large receive rings. */
77 #define TX_RING_SIZE 16
78 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
79 #define RX_RING_SIZE 64
81 /* Operational parameters that usually are not changed. */
83 /* Time in jiffies before concluding the transmitter is hung. */
84 #define TX_TIMEOUT (2*HZ)
86 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
88 #include <linux/module.h>
89 #include <linux/moduleparam.h>
90 #include <linux/kernel.h>
91 #include <linux/string.h>
92 #include <linux/timer.h>
93 #include <linux/errno.h>
94 #include <linux/ioport.h>
95 #include <linux/interrupt.h>
96 #include <linux/pci.h>
97 #include <linux/dma-mapping.h>
98 #include <linux/netdevice.h>
99 #include <linux/etherdevice.h>
100 #include <linux/skbuff.h>
101 #include <linux/init.h>
102 #include <linux/delay.h>
103 #include <linux/mii.h>
104 #include <linux/ethtool.h>
105 #include <linux/crc32.h>
106 #include <linux/if_vlan.h>
107 #include <linux/bitops.h>
108 #include <linux/workqueue.h>
109 #include <asm/processor.h> /* Processor type for cache alignment. */
112 #include <asm/uaccess.h>
113 #include <linux/dmi.h>
115 /* These identify the driver base version and may not be removed. */
116 static const char version[] __devinitconst =
117 "v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker";
119 /* This driver was written to use PCI memory space. Some early versions
120 of the Rhine may only work correctly with I/O space accesses. */
121 #ifdef CONFIG_VIA_RHINE_MMIO
126 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
127 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
128 MODULE_LICENSE("GPL");
130 module_param(debug, int, 0);
131 module_param(rx_copybreak, int, 0);
132 module_param(avoid_D3, bool, 0);
133 MODULE_PARM_DESC(debug, "VIA Rhine debug message flags");
134 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
135 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
143 I. Board Compatibility
145 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
148 II. Board-specific settings
150 Boards with this chip are functional only in a bus-master PCI slot.
152 Many operational settings are loaded from the EEPROM to the Config word at
153 offset 0x78. For most of these settings, this driver assumes that they are
155 If this driver is compiled to use PCI memory space operations the EEPROM
156 must be configured to enable memory ops.
158 III. Driver operation
162 This driver uses two statically allocated fixed-size descriptor lists
163 formed into rings by a branch from the final descriptor to the beginning of
164 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
166 IIIb/c. Transmit/Receive Structure
168 This driver attempts to use a zero-copy receive and transmit scheme.
170 Alas, all data buffers are required to start on a 32 bit boundary, so
171 the driver must often copy transmit packets into bounce buffers.
173 The driver allocates full frame size skbuffs for the Rx ring buffers at
174 open() time and passes the skb->data field to the chip as receive data
175 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
176 a fresh skbuff is allocated and the frame is copied to the new skbuff.
177 When the incoming frame is larger, the skbuff is passed directly up the
178 protocol stack. Buffers consumed this way are replaced by newly allocated
179 skbuffs in the last phase of rhine_rx().
181 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
182 using a full-sized skbuff for small frames vs. the copying costs of larger
183 frames. New boards are typically used in generously configured machines
184 and the underfilled buffers have negligible impact compared to the benefit of
185 a single allocation size, so the default value of zero results in never
186 copying packets. When copying is done, the cost is usually mitigated by using
187 a combined copy/checksum routine. Copying also preloads the cache, which is
188 most useful with small frames.
190 Since the VIA chips are only able to transfer data to buffers on 32 bit
191 boundaries, the IP header at offset 14 in an ethernet frame isn't
192 longword aligned for further processing. Copying these unaligned buffers
193 has the beneficial effect of 16-byte aligning the IP header.
195 IIId. Synchronization
197 The driver runs as two independent, single-threaded flows of control. One
198 is the send-packet routine, which enforces single-threaded use by the
199 netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
200 which is single threaded by the hardware and interrupt handling software.
202 The send packet thread has partial control over the Tx ring. It locks the
203 netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
204 the ring is not available it stops the transmit queue by
205 calling netif_stop_queue.
207 The interrupt handler has exclusive control over the Rx ring and records stats
208 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
209 empty by incrementing the dirty_tx mark. If at least half of the entries in
210 the Rx ring are available the transmit queue is woken up if it was stopped.
216 Preliminary VT86C100A manual from http://www.via.com.tw/
217 http://www.scyld.com/expert/100mbps.html
218 http://www.scyld.com/expert/NWay.html
219 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
220 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
225 The VT86C100A manual is not reliable information.
226 The 3043 chip does not handle unaligned transmit or receive buffers, resulting
227 in significant performance degradation for bounce buffer copies on transmit
228 and unaligned IP headers on receive.
229 The chip does not pad to minimum transmit length.
234 /* This table drives the PCI probe routines. It's mostly boilerplate in all
235 of the drivers, and will likely be provided by some future kernel.
236 Note the matching code -- the first table entry matchs all 56** cards but
237 second only the 1234 card.
244 VT8231 = 0x50, /* Integrated MAC */
245 VT8233 = 0x60, /* Integrated MAC */
246 VT8235 = 0x74, /* Integrated MAC */
247 VT8237 = 0x78, /* Integrated MAC */
254 VT6105M = 0x90, /* Management adapter */
258 rqWOL = 0x0001, /* Wake-On-LAN support */
259 rqForceReset = 0x0002,
260 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
261 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
262 rqRhineI = 0x0100, /* See comment below */
265 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
266 * MMIO as well as for the collision counter and the Tx FIFO underflow
267 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
270 /* Beware of PCI posted writes */
271 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
273 static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = {
274 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
275 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
276 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
277 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
278 { } /* terminate list */
280 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
283 /* Offsets to the device registers. */
284 enum register_offsets {
285 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
286 ChipCmd1=0x09, TQWake=0x0A,
287 IntrStatus=0x0C, IntrEnable=0x0E,
288 MulticastFilter0=0x10, MulticastFilter1=0x14,
289 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
290 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
291 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
292 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
293 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
294 StickyHW=0x83, IntrStatus2=0x84,
295 CamMask=0x88, CamCon=0x92, CamAddr=0x93,
296 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
297 WOLcrClr1=0xA6, WOLcgClr=0xA7,
298 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
301 /* Bits in ConfigD */
303 BackOptional=0x01, BackModify=0x02,
304 BackCaptureEffect=0x04, BackRandom=0x08
307 /* Bits in the TxConfig (TCR) register */
310 TCR_LB0=0x02, /* loopback[0] */
311 TCR_LB1=0x04, /* loopback[1] */
319 /* Bits in the CamCon (CAMC) register */
327 /* Bits in the PCIBusConfig1 (BCR1) register */
335 BCR1_TXQNOBK=0x40, /* for VT6105 */
336 BCR1_VIDFR=0x80, /* for VT6105 */
337 BCR1_MED0=0x40, /* for VT6102 */
338 BCR1_MED1=0x80, /* for VT6102 */
342 /* Registers we check that mmio and reg are the same. */
343 static const int mmio_verify_registers[] = {
344 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
349 /* Bits in the interrupt status/mask registers. */
350 enum intr_status_bits {
354 IntrTxError = 0x0008,
355 IntrRxEmpty = 0x0020,
357 IntrStatsMax = 0x0080,
358 IntrRxEarly = 0x0100,
359 IntrTxUnderrun = 0x0210,
360 IntrRxOverflow = 0x0400,
361 IntrRxDropped = 0x0800,
362 IntrRxNoBuf = 0x1000,
363 IntrTxAborted = 0x2000,
364 IntrLinkChange = 0x4000,
365 IntrRxWakeUp = 0x8000,
366 IntrTxDescRace = 0x080000, /* mapped from IntrStatus2 */
367 IntrNormalSummary = IntrRxDone | IntrTxDone,
368 IntrTxErrSummary = IntrTxDescRace | IntrTxAborted | IntrTxError |
372 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
381 /* The Rx and Tx buffer descriptors. */
384 __le32 desc_length; /* Chain flag, Buffer/frame length */
390 __le32 desc_length; /* Chain flag, Tx Config, Frame length */
395 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
396 #define TXDESC 0x00e08000
398 enum rx_status_bits {
399 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
402 /* Bits in *_desc.*_status */
403 enum desc_status_bits {
407 /* Bits in *_desc.*_length */
408 enum desc_length_bits {
412 /* Bits in ChipCmd. */
414 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
415 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
416 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
417 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
420 struct rhine_private {
421 /* Bit mask for configured VLAN ids */
422 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
424 /* Descriptor rings */
425 struct rx_desc *rx_ring;
426 struct tx_desc *tx_ring;
427 dma_addr_t rx_ring_dma;
428 dma_addr_t tx_ring_dma;
430 /* The addresses of receive-in-place skbuffs. */
431 struct sk_buff *rx_skbuff[RX_RING_SIZE];
432 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
434 /* The saved address of a sent-in-place packet/buffer, for later free(). */
435 struct sk_buff *tx_skbuff[TX_RING_SIZE];
436 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
438 /* Tx bounce buffers (Rhine-I only) */
439 unsigned char *tx_buf[TX_RING_SIZE];
440 unsigned char *tx_bufs;
441 dma_addr_t tx_bufs_dma;
443 struct pci_dev *pdev;
445 struct net_device *dev;
446 struct napi_struct napi;
448 struct mutex task_lock;
450 struct work_struct slow_event_task;
451 struct work_struct reset_task;
455 /* Frequently used values: keep some adjacent for cache effect. */
457 struct rx_desc *rx_head_desc;
458 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
459 unsigned int cur_tx, dirty_tx;
460 unsigned int rx_buf_sz; /* Based on MTU+slack. */
463 u8 tx_thresh, rx_thresh;
465 struct mii_if_info mii_if;
469 #define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
470 #define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
471 #define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
473 #define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x))
474 #define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x))
475 #define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x))
477 #define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
478 #define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
479 #define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
481 #define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
482 #define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
483 #define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
486 static int mdio_read(struct net_device *dev, int phy_id, int location);
487 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
488 static int rhine_open(struct net_device *dev);
489 static void rhine_reset_task(struct work_struct *work);
490 static void rhine_slow_event_task(struct work_struct *work);
491 static void rhine_tx_timeout(struct net_device *dev);
492 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
493 struct net_device *dev);
494 static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
495 static void rhine_tx(struct net_device *dev);
496 static int rhine_rx(struct net_device *dev, int limit);
497 static void rhine_set_rx_mode(struct net_device *dev);
498 static struct net_device_stats *rhine_get_stats(struct net_device *dev);
499 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
500 static const struct ethtool_ops netdev_ethtool_ops;
501 static int rhine_close(struct net_device *dev);
502 static int rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);
503 static int rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
504 static void rhine_restart_tx(struct net_device *dev);
506 static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low)
508 void __iomem *ioaddr = rp->base;
511 for (i = 0; i < 1024; i++) {
512 bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask);
514 if (low ^ has_mask_bits)
519 netif_dbg(rp, hw, rp->dev, "%s bit wait (%02x/%02x) cycle "
520 "count: %04d\n", low ? "low" : "high", reg, mask, i);
524 static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask)
526 rhine_wait_bit(rp, reg, mask, false);
529 static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask)
531 rhine_wait_bit(rp, reg, mask, true);
534 static u32 rhine_get_events(struct rhine_private *rp)
536 void __iomem *ioaddr = rp->base;
539 intr_status = ioread16(ioaddr + IntrStatus);
540 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
541 if (rp->quirks & rqStatusWBRace)
542 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
546 static void rhine_ack_events(struct rhine_private *rp, u32 mask)
548 void __iomem *ioaddr = rp->base;
550 if (rp->quirks & rqStatusWBRace)
551 iowrite8(mask >> 16, ioaddr + IntrStatus2);
552 iowrite16(mask, ioaddr + IntrStatus);
557 * Get power related registers into sane state.
558 * Notify user about past WOL event.
560 static void rhine_power_init(struct net_device *dev)
562 struct rhine_private *rp = netdev_priv(dev);
563 void __iomem *ioaddr = rp->base;
566 if (rp->quirks & rqWOL) {
567 /* Make sure chip is in power state D0 */
568 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
570 /* Disable "force PME-enable" */
571 iowrite8(0x80, ioaddr + WOLcgClr);
573 /* Clear power-event config bits (WOL) */
574 iowrite8(0xFF, ioaddr + WOLcrClr);
575 /* More recent cards can manage two additional patterns */
576 if (rp->quirks & rq6patterns)
577 iowrite8(0x03, ioaddr + WOLcrClr1);
579 /* Save power-event status bits */
580 wolstat = ioread8(ioaddr + PwrcsrSet);
581 if (rp->quirks & rq6patterns)
582 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
584 /* Clear power-event status bits */
585 iowrite8(0xFF, ioaddr + PwrcsrClr);
586 if (rp->quirks & rq6patterns)
587 iowrite8(0x03, ioaddr + PwrcsrClr1);
593 reason = "Magic packet";
596 reason = "Link went up";
599 reason = "Link went down";
602 reason = "Unicast packet";
605 reason = "Multicast/broadcast packet";
610 netdev_info(dev, "Woke system up. Reason: %s\n",
616 static void rhine_chip_reset(struct net_device *dev)
618 struct rhine_private *rp = netdev_priv(dev);
619 void __iomem *ioaddr = rp->base;
622 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
625 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
626 netdev_info(dev, "Reset not complete yet. Trying harder.\n");
629 if (rp->quirks & rqForceReset)
630 iowrite8(0x40, ioaddr + MiscCmd);
632 /* Reset can take somewhat longer (rare) */
633 rhine_wait_bit_low(rp, ChipCmd1, Cmd1Reset);
636 cmd1 = ioread8(ioaddr + ChipCmd1);
637 netif_info(rp, hw, dev, "Reset %s\n", (cmd1 & Cmd1Reset) ?
638 "failed" : "succeeded");
642 static void enable_mmio(long pioaddr, u32 quirks)
645 if (quirks & rqRhineI) {
646 /* More recent docs say that this bit is reserved ... */
647 n = inb(pioaddr + ConfigA) | 0x20;
648 outb(n, pioaddr + ConfigA);
650 n = inb(pioaddr + ConfigD) | 0x80;
651 outb(n, pioaddr + ConfigD);
657 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
658 * (plus 0x6C for Rhine-I/II)
660 static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
662 struct rhine_private *rp = netdev_priv(dev);
663 void __iomem *ioaddr = rp->base;
666 outb(0x20, pioaddr + MACRegEEcsr);
667 for (i = 0; i < 1024; i++) {
668 if (!(inb(pioaddr + MACRegEEcsr) & 0x20))
672 pr_info("%4d cycles used @ %s:%d\n", i, __func__, __LINE__);
676 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
677 * MMIO. If reloading EEPROM was done first this could be avoided, but
678 * it is not known if that still works with the "win98-reboot" problem.
680 enable_mmio(pioaddr, rp->quirks);
683 /* Turn off EEPROM-controlled wake-up (magic packet) */
684 if (rp->quirks & rqWOL)
685 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
689 #ifdef CONFIG_NET_POLL_CONTROLLER
690 static void rhine_poll(struct net_device *dev)
692 struct rhine_private *rp = netdev_priv(dev);
693 const int irq = rp->pdev->irq;
696 rhine_interrupt(irq, dev);
701 static void rhine_kick_tx_threshold(struct rhine_private *rp)
703 if (rp->tx_thresh < 0xe0) {
704 void __iomem *ioaddr = rp->base;
706 rp->tx_thresh += 0x20;
707 BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig);
711 static void rhine_tx_err(struct rhine_private *rp, u32 status)
713 struct net_device *dev = rp->dev;
715 if (status & IntrTxAborted) {
716 netif_info(rp, tx_err, dev,
717 "Abort %08x, frame dropped\n", status);
720 if (status & IntrTxUnderrun) {
721 rhine_kick_tx_threshold(rp);
722 netif_info(rp, tx_err ,dev, "Transmitter underrun, "
723 "Tx threshold now %02x\n", rp->tx_thresh);
726 if (status & IntrTxDescRace)
727 netif_info(rp, tx_err, dev, "Tx descriptor write-back race\n");
729 if ((status & IntrTxError) &&
730 (status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace)) == 0) {
731 rhine_kick_tx_threshold(rp);
732 netif_info(rp, tx_err, dev, "Unspecified error. "
733 "Tx threshold now %02x\n", rp->tx_thresh);
736 rhine_restart_tx(dev);
739 static void rhine_update_rx_crc_and_missed_errord(struct rhine_private *rp)
741 void __iomem *ioaddr = rp->base;
742 struct net_device_stats *stats = &rp->dev->stats;
744 stats->rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
745 stats->rx_missed_errors += ioread16(ioaddr + RxMissed);
748 * Clears the "tally counters" for CRC errors and missed frames(?).
749 * It has been reported that some chips need a write of 0 to clear
750 * these, for others the counters are set to 1 when written to and
751 * instead cleared when read. So we clear them both ways ...
753 iowrite32(0, ioaddr + RxMissed);
754 ioread16(ioaddr + RxCRCErrs);
755 ioread16(ioaddr + RxMissed);
758 #define RHINE_EVENT_NAPI_RX (IntrRxDone | \
766 #define RHINE_EVENT_NAPI_TX_ERR (IntrTxError | \
770 #define RHINE_EVENT_NAPI_TX (IntrTxDone | RHINE_EVENT_NAPI_TX_ERR)
772 #define RHINE_EVENT_NAPI (RHINE_EVENT_NAPI_RX | \
773 RHINE_EVENT_NAPI_TX | \
775 #define RHINE_EVENT_SLOW (IntrPCIErr | IntrLinkChange)
776 #define RHINE_EVENT (RHINE_EVENT_NAPI | RHINE_EVENT_SLOW)
778 static int rhine_napipoll(struct napi_struct *napi, int budget)
780 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
781 struct net_device *dev = rp->dev;
782 void __iomem *ioaddr = rp->base;
783 u16 enable_mask = RHINE_EVENT & 0xffff;
787 status = rhine_get_events(rp);
788 rhine_ack_events(rp, status & ~RHINE_EVENT_SLOW);
790 if (status & RHINE_EVENT_NAPI_RX)
791 work_done += rhine_rx(dev, budget);
793 if (status & RHINE_EVENT_NAPI_TX) {
794 if (status & RHINE_EVENT_NAPI_TX_ERR) {
795 /* Avoid scavenging before Tx engine turned off */
796 rhine_wait_bit_low(rp, ChipCmd, CmdTxOn);
797 if (ioread8(ioaddr + ChipCmd) & CmdTxOn)
798 netif_warn(rp, tx_err, dev, "Tx still on\n");
803 if (status & RHINE_EVENT_NAPI_TX_ERR)
804 rhine_tx_err(rp, status);
807 if (status & IntrStatsMax) {
808 spin_lock(&rp->lock);
809 rhine_update_rx_crc_and_missed_errord(rp);
810 spin_unlock(&rp->lock);
813 if (status & RHINE_EVENT_SLOW) {
814 enable_mask &= ~RHINE_EVENT_SLOW;
815 schedule_work(&rp->slow_event_task);
818 if (work_done < budget) {
820 iowrite16(enable_mask, ioaddr + IntrEnable);
826 static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
828 struct rhine_private *rp = netdev_priv(dev);
830 /* Reset the chip to erase previous misconfiguration. */
831 rhine_chip_reset(dev);
833 /* Rhine-I needs extra time to recuperate before EEPROM reload */
834 if (rp->quirks & rqRhineI)
837 /* Reload EEPROM controlled bytes cleared by soft reset */
838 rhine_reload_eeprom(pioaddr, dev);
841 static const struct net_device_ops rhine_netdev_ops = {
842 .ndo_open = rhine_open,
843 .ndo_stop = rhine_close,
844 .ndo_start_xmit = rhine_start_tx,
845 .ndo_get_stats = rhine_get_stats,
846 .ndo_set_rx_mode = rhine_set_rx_mode,
847 .ndo_change_mtu = eth_change_mtu,
848 .ndo_validate_addr = eth_validate_addr,
849 .ndo_set_mac_address = eth_mac_addr,
850 .ndo_do_ioctl = netdev_ioctl,
851 .ndo_tx_timeout = rhine_tx_timeout,
852 .ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid,
853 .ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid,
854 #ifdef CONFIG_NET_POLL_CONTROLLER
855 .ndo_poll_controller = rhine_poll,
859 static int __devinit rhine_init_one(struct pci_dev *pdev,
860 const struct pci_device_id *ent)
862 struct net_device *dev;
863 struct rhine_private *rp;
868 void __iomem *ioaddr;
877 /* when built into the kernel, we only print version if device is found */
879 pr_info_once("%s\n", version);
886 if (pdev->revision < VTunknown0) {
890 else if (pdev->revision >= VT6102) {
891 quirks = rqWOL | rqForceReset;
892 if (pdev->revision < VT6105) {
894 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
897 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
898 if (pdev->revision >= VT6105_B0)
899 quirks |= rq6patterns;
900 if (pdev->revision < VT6105M)
903 name = "Rhine III (Management Adapter)";
907 rc = pci_enable_device(pdev);
911 /* this should always be supported */
912 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
915 "32-bit PCI DMA addresses not supported by the card!?\n");
920 if ((pci_resource_len(pdev, 0) < io_size) ||
921 (pci_resource_len(pdev, 1) < io_size)) {
923 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
927 pioaddr = pci_resource_start(pdev, 0);
928 memaddr = pci_resource_start(pdev, 1);
930 pci_set_master(pdev);
932 dev = alloc_etherdev(sizeof(struct rhine_private));
937 SET_NETDEV_DEV(dev, &pdev->dev);
939 rp = netdev_priv(dev);
942 rp->pioaddr = pioaddr;
944 rp->msg_enable = netif_msg_init(debug, RHINE_MSG_DEFAULT);
946 rc = pci_request_regions(pdev, DRV_NAME);
948 goto err_out_free_netdev;
950 ioaddr = pci_iomap(pdev, bar, io_size);
954 "ioremap failed for device %s, region 0x%X @ 0x%lX\n",
955 pci_name(pdev), io_size, memaddr);
956 goto err_out_free_res;
960 enable_mmio(pioaddr, quirks);
962 /* Check that selected MMIO registers match the PIO ones */
964 while (mmio_verify_registers[i]) {
965 int reg = mmio_verify_registers[i++];
966 unsigned char a = inb(pioaddr+reg);
967 unsigned char b = readb(ioaddr+reg);
971 "MMIO do not match PIO [%02x] (%02x != %02x)\n",
976 #endif /* USE_MMIO */
980 /* Get chip registers into a sane state */
981 rhine_power_init(dev);
982 rhine_hw_init(dev, pioaddr);
984 for (i = 0; i < 6; i++)
985 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
987 if (!is_valid_ether_addr(dev->dev_addr)) {
988 /* Report it and use a random ethernet address instead */
989 netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
990 eth_hw_addr_random(dev);
991 netdev_info(dev, "Using random MAC address: %pM\n",
994 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
996 /* For Rhine-I/II, phy_id is loaded from EEPROM */
998 phy_id = ioread8(ioaddr + 0x6C);
1000 spin_lock_init(&rp->lock);
1001 mutex_init(&rp->task_lock);
1002 INIT_WORK(&rp->reset_task, rhine_reset_task);
1003 INIT_WORK(&rp->slow_event_task, rhine_slow_event_task);
1005 rp->mii_if.dev = dev;
1006 rp->mii_if.mdio_read = mdio_read;
1007 rp->mii_if.mdio_write = mdio_write;
1008 rp->mii_if.phy_id_mask = 0x1f;
1009 rp->mii_if.reg_num_mask = 0x1f;
1011 /* The chip-specific entries in the device structure. */
1012 dev->netdev_ops = &rhine_netdev_ops;
1013 dev->ethtool_ops = &netdev_ethtool_ops,
1014 dev->watchdog_timeo = TX_TIMEOUT;
1016 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
1018 if (rp->quirks & rqRhineI)
1019 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
1021 if (pdev->revision >= VT6105M)
1022 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
1023 NETIF_F_HW_VLAN_FILTER;
1025 /* dev->name not defined before register_netdev()! */
1026 rc = register_netdev(dev);
1030 netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",
1037 dev->dev_addr, pdev->irq);
1039 pci_set_drvdata(pdev, dev);
1043 int mii_status = mdio_read(dev, phy_id, 1);
1044 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
1045 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
1046 if (mii_status != 0xffff && mii_status != 0x0000) {
1047 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
1049 "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",
1051 mii_status, rp->mii_if.advertising,
1052 mdio_read(dev, phy_id, 5));
1054 /* set IFF_RUNNING */
1055 if (mii_status & BMSR_LSTATUS)
1056 netif_carrier_on(dev);
1058 netif_carrier_off(dev);
1062 rp->mii_if.phy_id = phy_id;
1064 netif_info(rp, probe, dev, "No D3 power state at shutdown\n");
1069 pci_iounmap(pdev, ioaddr);
1071 pci_release_regions(pdev);
1072 err_out_free_netdev:
1078 static int alloc_ring(struct net_device* dev)
1080 struct rhine_private *rp = netdev_priv(dev);
1082 dma_addr_t ring_dma;
1084 ring = pci_alloc_consistent(rp->pdev,
1085 RX_RING_SIZE * sizeof(struct rx_desc) +
1086 TX_RING_SIZE * sizeof(struct tx_desc),
1089 netdev_err(dev, "Could not allocate DMA memory\n");
1092 if (rp->quirks & rqRhineI) {
1093 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
1094 PKT_BUF_SZ * TX_RING_SIZE,
1096 if (rp->tx_bufs == NULL) {
1097 pci_free_consistent(rp->pdev,
1098 RX_RING_SIZE * sizeof(struct rx_desc) +
1099 TX_RING_SIZE * sizeof(struct tx_desc),
1106 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
1107 rp->rx_ring_dma = ring_dma;
1108 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
1113 static void free_ring(struct net_device* dev)
1115 struct rhine_private *rp = netdev_priv(dev);
1117 pci_free_consistent(rp->pdev,
1118 RX_RING_SIZE * sizeof(struct rx_desc) +
1119 TX_RING_SIZE * sizeof(struct tx_desc),
1120 rp->rx_ring, rp->rx_ring_dma);
1124 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
1125 rp->tx_bufs, rp->tx_bufs_dma);
1131 static void alloc_rbufs(struct net_device *dev)
1133 struct rhine_private *rp = netdev_priv(dev);
1137 rp->dirty_rx = rp->cur_rx = 0;
1139 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1140 rp->rx_head_desc = &rp->rx_ring[0];
1141 next = rp->rx_ring_dma;
1143 /* Init the ring entries */
1144 for (i = 0; i < RX_RING_SIZE; i++) {
1145 rp->rx_ring[i].rx_status = 0;
1146 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
1147 next += sizeof(struct rx_desc);
1148 rp->rx_ring[i].next_desc = cpu_to_le32(next);
1149 rp->rx_skbuff[i] = NULL;
1151 /* Mark the last entry as wrapping the ring. */
1152 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
1154 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1155 for (i = 0; i < RX_RING_SIZE; i++) {
1156 struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1157 rp->rx_skbuff[i] = skb;
1161 rp->rx_skbuff_dma[i] =
1162 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
1163 PCI_DMA_FROMDEVICE);
1165 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
1166 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1168 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1171 static void free_rbufs(struct net_device* dev)
1173 struct rhine_private *rp = netdev_priv(dev);
1176 /* Free all the skbuffs in the Rx queue. */
1177 for (i = 0; i < RX_RING_SIZE; i++) {
1178 rp->rx_ring[i].rx_status = 0;
1179 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1180 if (rp->rx_skbuff[i]) {
1181 pci_unmap_single(rp->pdev,
1182 rp->rx_skbuff_dma[i],
1183 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1184 dev_kfree_skb(rp->rx_skbuff[i]);
1186 rp->rx_skbuff[i] = NULL;
1190 static void alloc_tbufs(struct net_device* dev)
1192 struct rhine_private *rp = netdev_priv(dev);
1196 rp->dirty_tx = rp->cur_tx = 0;
1197 next = rp->tx_ring_dma;
1198 for (i = 0; i < TX_RING_SIZE; i++) {
1199 rp->tx_skbuff[i] = NULL;
1200 rp->tx_ring[i].tx_status = 0;
1201 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1202 next += sizeof(struct tx_desc);
1203 rp->tx_ring[i].next_desc = cpu_to_le32(next);
1204 if (rp->quirks & rqRhineI)
1205 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
1207 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1211 static void free_tbufs(struct net_device* dev)
1213 struct rhine_private *rp = netdev_priv(dev);
1216 for (i = 0; i < TX_RING_SIZE; i++) {
1217 rp->tx_ring[i].tx_status = 0;
1218 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1219 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1220 if (rp->tx_skbuff[i]) {
1221 if (rp->tx_skbuff_dma[i]) {
1222 pci_unmap_single(rp->pdev,
1223 rp->tx_skbuff_dma[i],
1224 rp->tx_skbuff[i]->len,
1227 dev_kfree_skb(rp->tx_skbuff[i]);
1229 rp->tx_skbuff[i] = NULL;
1230 rp->tx_buf[i] = NULL;
1234 static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1236 struct rhine_private *rp = netdev_priv(dev);
1237 void __iomem *ioaddr = rp->base;
1239 mii_check_media(&rp->mii_if, netif_msg_link(rp), init_media);
1241 if (rp->mii_if.full_duplex)
1242 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1245 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1248 netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1249 rp->mii_if.force_media, netif_carrier_ok(dev));
1252 /* Called after status of force_media possibly changed */
1253 static void rhine_set_carrier(struct mii_if_info *mii)
1255 struct net_device *dev = mii->dev;
1256 struct rhine_private *rp = netdev_priv(dev);
1258 if (mii->force_media) {
1259 /* autoneg is off: Link is always assumed to be up */
1260 if (!netif_carrier_ok(dev))
1261 netif_carrier_on(dev);
1262 } else /* Let MMI library update carrier status */
1263 rhine_check_media(dev, 0);
1265 netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1266 mii->force_media, netif_carrier_ok(dev));
1270 * rhine_set_cam - set CAM multicast filters
1271 * @ioaddr: register block of this Rhine
1272 * @idx: multicast CAM index [0..MCAM_SIZE-1]
1273 * @addr: multicast address (6 bytes)
1275 * Load addresses into multicast filters.
1277 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
1281 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1284 /* Paranoid -- idx out of range should never happen */
1285 idx &= (MCAM_SIZE - 1);
1287 iowrite8((u8) idx, ioaddr + CamAddr);
1289 for (i = 0; i < 6; i++, addr++)
1290 iowrite8(*addr, ioaddr + MulticastFilter0 + i);
1294 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1297 iowrite8(0, ioaddr + CamCon);
1301 * rhine_set_vlan_cam - set CAM VLAN filters
1302 * @ioaddr: register block of this Rhine
1303 * @idx: VLAN CAM index [0..VCAM_SIZE-1]
1304 * @addr: VLAN ID (2 bytes)
1306 * Load addresses into VLAN filters.
1308 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
1310 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1313 /* Paranoid -- idx out of range should never happen */
1314 idx &= (VCAM_SIZE - 1);
1316 iowrite8((u8) idx, ioaddr + CamAddr);
1318 iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
1322 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1325 iowrite8(0, ioaddr + CamCon);
1329 * rhine_set_cam_mask - set multicast CAM mask
1330 * @ioaddr: register block of this Rhine
1331 * @mask: multicast CAM mask
1333 * Mask sets multicast filters active/inactive.
1335 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
1337 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1341 iowrite32(mask, ioaddr + CamMask);
1344 iowrite8(0, ioaddr + CamCon);
1348 * rhine_set_vlan_cam_mask - set VLAN CAM mask
1349 * @ioaddr: register block of this Rhine
1350 * @mask: VLAN CAM mask
1352 * Mask sets VLAN filters active/inactive.
1354 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
1356 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1360 iowrite32(mask, ioaddr + CamMask);
1363 iowrite8(0, ioaddr + CamCon);
1367 * rhine_init_cam_filter - initialize CAM filters
1368 * @dev: network device
1370 * Initialize (disable) hardware VLAN and multicast support on this
1373 static void rhine_init_cam_filter(struct net_device *dev)
1375 struct rhine_private *rp = netdev_priv(dev);
1376 void __iomem *ioaddr = rp->base;
1378 /* Disable all CAMs */
1379 rhine_set_vlan_cam_mask(ioaddr, 0);
1380 rhine_set_cam_mask(ioaddr, 0);
1382 /* disable hardware VLAN support */
1383 BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
1384 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
1388 * rhine_update_vcam - update VLAN CAM filters
1389 * @rp: rhine_private data of this Rhine
1391 * Update VLAN CAM filters to match configuration change.
1393 static void rhine_update_vcam(struct net_device *dev)
1395 struct rhine_private *rp = netdev_priv(dev);
1396 void __iomem *ioaddr = rp->base;
1398 u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */
1401 for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
1402 rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
1404 if (++i >= VCAM_SIZE)
1407 rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
1410 static int rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
1412 struct rhine_private *rp = netdev_priv(dev);
1414 spin_lock_bh(&rp->lock);
1415 set_bit(vid, rp->active_vlans);
1416 rhine_update_vcam(dev);
1417 spin_unlock_bh(&rp->lock);
1421 static int rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1423 struct rhine_private *rp = netdev_priv(dev);
1425 spin_lock_bh(&rp->lock);
1426 clear_bit(vid, rp->active_vlans);
1427 rhine_update_vcam(dev);
1428 spin_unlock_bh(&rp->lock);
1432 static void init_registers(struct net_device *dev)
1434 struct rhine_private *rp = netdev_priv(dev);
1435 void __iomem *ioaddr = rp->base;
1438 for (i = 0; i < 6; i++)
1439 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1441 /* Initialize other registers. */
1442 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1443 /* Configure initial FIFO thresholds. */
1444 iowrite8(0x20, ioaddr + TxConfig);
1445 rp->tx_thresh = 0x20;
1446 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1448 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1449 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1451 rhine_set_rx_mode(dev);
1453 if (rp->pdev->revision >= VT6105M)
1454 rhine_init_cam_filter(dev);
1456 napi_enable(&rp->napi);
1458 iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable);
1460 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1462 rhine_check_media(dev, 1);
1465 /* Enable MII link status auto-polling (required for IntrLinkChange) */
1466 static void rhine_enable_linkmon(struct rhine_private *rp)
1468 void __iomem *ioaddr = rp->base;
1470 iowrite8(0, ioaddr + MIICmd);
1471 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1472 iowrite8(0x80, ioaddr + MIICmd);
1474 rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1476 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1479 /* Disable MII link status auto-polling (required for MDIO access) */
1480 static void rhine_disable_linkmon(struct rhine_private *rp)
1482 void __iomem *ioaddr = rp->base;
1484 iowrite8(0, ioaddr + MIICmd);
1486 if (rp->quirks & rqRhineI) {
1487 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1489 /* Can be called from ISR. Evil. */
1492 /* 0x80 must be set immediately before turning it off */
1493 iowrite8(0x80, ioaddr + MIICmd);
1495 rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1497 /* Heh. Now clear 0x80 again. */
1498 iowrite8(0, ioaddr + MIICmd);
1501 rhine_wait_bit_high(rp, MIIRegAddr, 0x80);
1504 /* Read and write over the MII Management Data I/O (MDIO) interface. */
1506 static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1508 struct rhine_private *rp = netdev_priv(dev);
1509 void __iomem *ioaddr = rp->base;
1512 rhine_disable_linkmon(rp);
1514 /* rhine_disable_linkmon already cleared MIICmd */
1515 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1516 iowrite8(regnum, ioaddr + MIIRegAddr);
1517 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1518 rhine_wait_bit_low(rp, MIICmd, 0x40);
1519 result = ioread16(ioaddr + MIIData);
1521 rhine_enable_linkmon(rp);
1525 static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1527 struct rhine_private *rp = netdev_priv(dev);
1528 void __iomem *ioaddr = rp->base;
1530 rhine_disable_linkmon(rp);
1532 /* rhine_disable_linkmon already cleared MIICmd */
1533 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1534 iowrite8(regnum, ioaddr + MIIRegAddr);
1535 iowrite16(value, ioaddr + MIIData);
1536 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1537 rhine_wait_bit_low(rp, MIICmd, 0x20);
1539 rhine_enable_linkmon(rp);
1542 static void rhine_task_disable(struct rhine_private *rp)
1544 mutex_lock(&rp->task_lock);
1545 rp->task_enable = false;
1546 mutex_unlock(&rp->task_lock);
1548 cancel_work_sync(&rp->slow_event_task);
1549 cancel_work_sync(&rp->reset_task);
1552 static void rhine_task_enable(struct rhine_private *rp)
1554 mutex_lock(&rp->task_lock);
1555 rp->task_enable = true;
1556 mutex_unlock(&rp->task_lock);
1559 static int rhine_open(struct net_device *dev)
1561 struct rhine_private *rp = netdev_priv(dev);
1562 void __iomem *ioaddr = rp->base;
1565 rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name,
1570 netif_dbg(rp, ifup, dev, "%s() irq %d\n", __func__, rp->pdev->irq);
1572 rc = alloc_ring(dev);
1574 free_irq(rp->pdev->irq, dev);
1579 rhine_chip_reset(dev);
1580 rhine_task_enable(rp);
1581 init_registers(dev);
1583 netif_dbg(rp, ifup, dev, "%s() Done - status %04x MII status: %04x\n",
1584 __func__, ioread16(ioaddr + ChipCmd),
1585 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1587 netif_start_queue(dev);
1592 static void rhine_reset_task(struct work_struct *work)
1594 struct rhine_private *rp = container_of(work, struct rhine_private,
1596 struct net_device *dev = rp->dev;
1598 mutex_lock(&rp->task_lock);
1600 if (!rp->task_enable)
1603 napi_disable(&rp->napi);
1604 spin_lock_bh(&rp->lock);
1606 /* clear all descriptors */
1612 /* Reinitialize the hardware. */
1613 rhine_chip_reset(dev);
1614 init_registers(dev);
1616 spin_unlock_bh(&rp->lock);
1618 dev->trans_start = jiffies; /* prevent tx timeout */
1619 dev->stats.tx_errors++;
1620 netif_wake_queue(dev);
1623 mutex_unlock(&rp->task_lock);
1626 static void rhine_tx_timeout(struct net_device *dev)
1628 struct rhine_private *rp = netdev_priv(dev);
1629 void __iomem *ioaddr = rp->base;
1631 netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",
1632 ioread16(ioaddr + IntrStatus),
1633 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1635 schedule_work(&rp->reset_task);
1638 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
1639 struct net_device *dev)
1641 struct rhine_private *rp = netdev_priv(dev);
1642 void __iomem *ioaddr = rp->base;
1645 /* Caution: the write order is important here, set the field
1646 with the "ownership" bits last. */
1648 /* Calculate the next Tx descriptor entry. */
1649 entry = rp->cur_tx % TX_RING_SIZE;
1651 if (skb_padto(skb, ETH_ZLEN))
1652 return NETDEV_TX_OK;
1654 rp->tx_skbuff[entry] = skb;
1656 if ((rp->quirks & rqRhineI) &&
1657 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
1658 /* Must use alignment buffer. */
1659 if (skb->len > PKT_BUF_SZ) {
1660 /* packet too long, drop it */
1662 rp->tx_skbuff[entry] = NULL;
1663 dev->stats.tx_dropped++;
1664 return NETDEV_TX_OK;
1667 /* Padding is not copied and so must be redone. */
1668 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1669 if (skb->len < ETH_ZLEN)
1670 memset(rp->tx_buf[entry] + skb->len, 0,
1671 ETH_ZLEN - skb->len);
1672 rp->tx_skbuff_dma[entry] = 0;
1673 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1674 (rp->tx_buf[entry] -
1677 rp->tx_skbuff_dma[entry] =
1678 pci_map_single(rp->pdev, skb->data, skb->len,
1680 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1683 rp->tx_ring[entry].desc_length =
1684 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1686 if (unlikely(vlan_tx_tag_present(skb))) {
1687 rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);
1688 /* request tagging */
1689 rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
1692 rp->tx_ring[entry].tx_status = 0;
1696 rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
1701 /* Non-x86 Todo: explicitly flush cache lines here. */
1703 if (vlan_tx_tag_present(skb))
1704 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1705 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1707 /* Wake the potentially-idle transmit channel */
1708 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1712 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1713 netif_stop_queue(dev);
1715 netif_dbg(rp, tx_queued, dev, "Transmit frame #%d queued in slot %d\n",
1716 rp->cur_tx - 1, entry);
1718 return NETDEV_TX_OK;
1721 static void rhine_irq_disable(struct rhine_private *rp)
1723 iowrite16(0x0000, rp->base + IntrEnable);
1727 /* The interrupt handler does all of the Rx thread work and cleans up
1728 after the Tx thread. */
1729 static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1731 struct net_device *dev = dev_instance;
1732 struct rhine_private *rp = netdev_priv(dev);
1736 status = rhine_get_events(rp);
1738 netif_dbg(rp, intr, dev, "Interrupt, status %08x\n", status);
1740 if (status & RHINE_EVENT) {
1743 rhine_irq_disable(rp);
1744 napi_schedule(&rp->napi);
1747 if (status & ~(IntrLinkChange | IntrStatsMax | RHINE_EVENT_NAPI)) {
1748 netif_err(rp, intr, dev, "Something Wicked happened! %08x\n",
1752 return IRQ_RETVAL(handled);
1755 /* This routine is logically part of the interrupt handler, but isolated
1757 static void rhine_tx(struct net_device *dev)
1759 struct rhine_private *rp = netdev_priv(dev);
1760 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1762 /* find and cleanup dirty tx descriptors */
1763 while (rp->dirty_tx != rp->cur_tx) {
1764 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1765 netif_dbg(rp, tx_done, dev, "Tx scavenge %d status %08x\n",
1767 if (txstatus & DescOwn)
1769 if (txstatus & 0x8000) {
1770 netif_dbg(rp, tx_done, dev,
1771 "Transmit error, Tx status %08x\n", txstatus);
1772 dev->stats.tx_errors++;
1773 if (txstatus & 0x0400)
1774 dev->stats.tx_carrier_errors++;
1775 if (txstatus & 0x0200)
1776 dev->stats.tx_window_errors++;
1777 if (txstatus & 0x0100)
1778 dev->stats.tx_aborted_errors++;
1779 if (txstatus & 0x0080)
1780 dev->stats.tx_heartbeat_errors++;
1781 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1782 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1783 dev->stats.tx_fifo_errors++;
1784 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1785 break; /* Keep the skb - we try again */
1787 /* Transmitter restarted in 'abnormal' handler. */
1789 if (rp->quirks & rqRhineI)
1790 dev->stats.collisions += (txstatus >> 3) & 0x0F;
1792 dev->stats.collisions += txstatus & 0x0F;
1793 netif_dbg(rp, tx_done, dev, "collisions: %1.1x:%1.1x\n",
1794 (txstatus >> 3) & 0xF, txstatus & 0xF);
1795 dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1796 dev->stats.tx_packets++;
1798 /* Free the original skb. */
1799 if (rp->tx_skbuff_dma[entry]) {
1800 pci_unmap_single(rp->pdev,
1801 rp->tx_skbuff_dma[entry],
1802 rp->tx_skbuff[entry]->len,
1805 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1806 rp->tx_skbuff[entry] = NULL;
1807 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1809 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1810 netif_wake_queue(dev);
1814 * rhine_get_vlan_tci - extract TCI from Rx data buffer
1815 * @skb: pointer to sk_buff
1816 * @data_size: used data area of the buffer including CRC
1818 * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
1819 * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
1820 * aligned following the CRC.
1822 static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
1824 u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
1825 return be16_to_cpup((__be16 *)trailer);
1828 /* Process up to limit frames from receive ring */
1829 static int rhine_rx(struct net_device *dev, int limit)
1831 struct rhine_private *rp = netdev_priv(dev);
1833 int entry = rp->cur_rx % RX_RING_SIZE;
1835 netif_dbg(rp, rx_status, dev, "%s(), entry %d status %08x\n", __func__,
1836 entry, le32_to_cpu(rp->rx_head_desc->rx_status));
1838 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1839 for (count = 0; count < limit; ++count) {
1840 struct rx_desc *desc = rp->rx_head_desc;
1841 u32 desc_status = le32_to_cpu(desc->rx_status);
1842 u32 desc_length = le32_to_cpu(desc->desc_length);
1843 int data_size = desc_status >> 16;
1845 if (desc_status & DescOwn)
1848 netif_dbg(rp, rx_status, dev, "%s() status %08x\n", __func__,
1851 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1852 if ((desc_status & RxWholePkt) != RxWholePkt) {
1854 "Oversized Ethernet frame spanned multiple buffers, "
1855 "entry %#x length %d status %08x!\n",
1859 "Oversized Ethernet frame %p vs %p\n",
1861 &rp->rx_ring[entry]);
1862 dev->stats.rx_length_errors++;
1863 } else if (desc_status & RxErr) {
1864 /* There was a error. */
1865 netif_dbg(rp, rx_err, dev,
1866 "%s() Rx error %08x\n", __func__,
1868 dev->stats.rx_errors++;
1869 if (desc_status & 0x0030)
1870 dev->stats.rx_length_errors++;
1871 if (desc_status & 0x0048)
1872 dev->stats.rx_fifo_errors++;
1873 if (desc_status & 0x0004)
1874 dev->stats.rx_frame_errors++;
1875 if (desc_status & 0x0002) {
1876 /* this can also be updated outside the interrupt handler */
1877 spin_lock(&rp->lock);
1878 dev->stats.rx_crc_errors++;
1879 spin_unlock(&rp->lock);
1883 struct sk_buff *skb = NULL;
1884 /* Length should omit the CRC */
1885 int pkt_len = data_size - 4;
1888 /* Check if the packet is long enough to accept without
1889 copying to a minimally-sized skbuff. */
1890 if (pkt_len < rx_copybreak)
1891 skb = netdev_alloc_skb_ip_align(dev, pkt_len);
1893 pci_dma_sync_single_for_cpu(rp->pdev,
1894 rp->rx_skbuff_dma[entry],
1896 PCI_DMA_FROMDEVICE);
1898 skb_copy_to_linear_data(skb,
1899 rp->rx_skbuff[entry]->data,
1901 skb_put(skb, pkt_len);
1902 pci_dma_sync_single_for_device(rp->pdev,
1903 rp->rx_skbuff_dma[entry],
1905 PCI_DMA_FROMDEVICE);
1907 skb = rp->rx_skbuff[entry];
1909 netdev_err(dev, "Inconsistent Rx descriptor chain\n");
1912 rp->rx_skbuff[entry] = NULL;
1913 skb_put(skb, pkt_len);
1914 pci_unmap_single(rp->pdev,
1915 rp->rx_skbuff_dma[entry],
1917 PCI_DMA_FROMDEVICE);
1920 if (unlikely(desc_length & DescTag))
1921 vlan_tci = rhine_get_vlan_tci(skb, data_size);
1923 skb->protocol = eth_type_trans(skb, dev);
1925 if (unlikely(desc_length & DescTag))
1926 __vlan_hwaccel_put_tag(skb, vlan_tci);
1927 netif_receive_skb(skb);
1928 dev->stats.rx_bytes += pkt_len;
1929 dev->stats.rx_packets++;
1931 entry = (++rp->cur_rx) % RX_RING_SIZE;
1932 rp->rx_head_desc = &rp->rx_ring[entry];
1935 /* Refill the Rx ring buffers. */
1936 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1937 struct sk_buff *skb;
1938 entry = rp->dirty_rx % RX_RING_SIZE;
1939 if (rp->rx_skbuff[entry] == NULL) {
1940 skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1941 rp->rx_skbuff[entry] = skb;
1943 break; /* Better luck next round. */
1944 rp->rx_skbuff_dma[entry] =
1945 pci_map_single(rp->pdev, skb->data,
1947 PCI_DMA_FROMDEVICE);
1948 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1950 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1956 static void rhine_restart_tx(struct net_device *dev) {
1957 struct rhine_private *rp = netdev_priv(dev);
1958 void __iomem *ioaddr = rp->base;
1959 int entry = rp->dirty_tx % TX_RING_SIZE;
1963 * If new errors occurred, we need to sort them out before doing Tx.
1964 * In that case the ISR will be back here RSN anyway.
1966 intr_status = rhine_get_events(rp);
1968 if ((intr_status & IntrTxErrSummary) == 0) {
1970 /* We know better than the chip where it should continue. */
1971 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1972 ioaddr + TxRingPtr);
1974 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1977 if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
1978 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1979 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1981 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1986 /* This should never happen */
1987 netif_warn(rp, tx_err, dev, "another error occurred %08x\n",
1993 static void rhine_slow_event_task(struct work_struct *work)
1995 struct rhine_private *rp =
1996 container_of(work, struct rhine_private, slow_event_task);
1997 struct net_device *dev = rp->dev;
2000 mutex_lock(&rp->task_lock);
2002 if (!rp->task_enable)
2005 intr_status = rhine_get_events(rp);
2006 rhine_ack_events(rp, intr_status & RHINE_EVENT_SLOW);
2008 if (intr_status & IntrLinkChange)
2009 rhine_check_media(dev, 0);
2011 if (intr_status & IntrPCIErr)
2012 netif_warn(rp, hw, dev, "PCI error\n");
2014 napi_disable(&rp->napi);
2015 rhine_irq_disable(rp);
2016 /* Slow and safe. Consider __napi_schedule as a replacement ? */
2017 napi_enable(&rp->napi);
2018 napi_schedule(&rp->napi);
2021 mutex_unlock(&rp->task_lock);
2024 static struct net_device_stats *rhine_get_stats(struct net_device *dev)
2026 struct rhine_private *rp = netdev_priv(dev);
2028 spin_lock_bh(&rp->lock);
2029 rhine_update_rx_crc_and_missed_errord(rp);
2030 spin_unlock_bh(&rp->lock);
2035 static void rhine_set_rx_mode(struct net_device *dev)
2037 struct rhine_private *rp = netdev_priv(dev);
2038 void __iomem *ioaddr = rp->base;
2039 u32 mc_filter[2]; /* Multicast hash filter */
2040 u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */
2041 struct netdev_hw_addr *ha;
2043 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2045 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
2046 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
2047 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2048 (dev->flags & IFF_ALLMULTI)) {
2049 /* Too many to match, or accept all multicasts. */
2050 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
2051 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
2052 } else if (rp->pdev->revision >= VT6105M) {
2054 u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */
2055 netdev_for_each_mc_addr(ha, dev) {
2058 rhine_set_cam(ioaddr, i, ha->addr);
2062 rhine_set_cam_mask(ioaddr, mCAMmask);
2064 memset(mc_filter, 0, sizeof(mc_filter));
2065 netdev_for_each_mc_addr(ha, dev) {
2066 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2068 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2070 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
2071 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
2073 /* enable/disable VLAN receive filtering */
2074 if (rp->pdev->revision >= VT6105M) {
2075 if (dev->flags & IFF_PROMISC)
2076 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2078 BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2080 BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
2083 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2085 struct rhine_private *rp = netdev_priv(dev);
2087 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2088 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2089 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
2092 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2094 struct rhine_private *rp = netdev_priv(dev);
2097 mutex_lock(&rp->task_lock);
2098 rc = mii_ethtool_gset(&rp->mii_if, cmd);
2099 mutex_unlock(&rp->task_lock);
2104 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2106 struct rhine_private *rp = netdev_priv(dev);
2109 mutex_lock(&rp->task_lock);
2110 rc = mii_ethtool_sset(&rp->mii_if, cmd);
2111 rhine_set_carrier(&rp->mii_if);
2112 mutex_unlock(&rp->task_lock);
2117 static int netdev_nway_reset(struct net_device *dev)
2119 struct rhine_private *rp = netdev_priv(dev);
2121 return mii_nway_restart(&rp->mii_if);
2124 static u32 netdev_get_link(struct net_device *dev)
2126 struct rhine_private *rp = netdev_priv(dev);
2128 return mii_link_ok(&rp->mii_if);
2131 static u32 netdev_get_msglevel(struct net_device *dev)
2133 struct rhine_private *rp = netdev_priv(dev);
2135 return rp->msg_enable;
2138 static void netdev_set_msglevel(struct net_device *dev, u32 value)
2140 struct rhine_private *rp = netdev_priv(dev);
2142 rp->msg_enable = value;
2145 static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2147 struct rhine_private *rp = netdev_priv(dev);
2149 if (!(rp->quirks & rqWOL))
2152 spin_lock_irq(&rp->lock);
2153 wol->supported = WAKE_PHY | WAKE_MAGIC |
2154 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2155 wol->wolopts = rp->wolopts;
2156 spin_unlock_irq(&rp->lock);
2159 static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2161 struct rhine_private *rp = netdev_priv(dev);
2162 u32 support = WAKE_PHY | WAKE_MAGIC |
2163 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2165 if (!(rp->quirks & rqWOL))
2168 if (wol->wolopts & ~support)
2171 spin_lock_irq(&rp->lock);
2172 rp->wolopts = wol->wolopts;
2173 spin_unlock_irq(&rp->lock);
2178 static const struct ethtool_ops netdev_ethtool_ops = {
2179 .get_drvinfo = netdev_get_drvinfo,
2180 .get_settings = netdev_get_settings,
2181 .set_settings = netdev_set_settings,
2182 .nway_reset = netdev_nway_reset,
2183 .get_link = netdev_get_link,
2184 .get_msglevel = netdev_get_msglevel,
2185 .set_msglevel = netdev_set_msglevel,
2186 .get_wol = rhine_get_wol,
2187 .set_wol = rhine_set_wol,
2190 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2192 struct rhine_private *rp = netdev_priv(dev);
2195 if (!netif_running(dev))
2198 mutex_lock(&rp->task_lock);
2199 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
2200 rhine_set_carrier(&rp->mii_if);
2201 mutex_unlock(&rp->task_lock);
2206 static int rhine_close(struct net_device *dev)
2208 struct rhine_private *rp = netdev_priv(dev);
2209 void __iomem *ioaddr = rp->base;
2211 rhine_task_disable(rp);
2212 napi_disable(&rp->napi);
2213 netif_stop_queue(dev);
2215 netif_dbg(rp, ifdown, dev, "Shutting down ethercard, status was %04x\n",
2216 ioread16(ioaddr + ChipCmd));
2218 /* Switch to loopback mode to avoid hardware races. */
2219 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
2221 rhine_irq_disable(rp);
2223 /* Stop the chip's Tx and Rx processes. */
2224 iowrite16(CmdStop, ioaddr + ChipCmd);
2226 free_irq(rp->pdev->irq, dev);
2235 static void __devexit rhine_remove_one(struct pci_dev *pdev)
2237 struct net_device *dev = pci_get_drvdata(pdev);
2238 struct rhine_private *rp = netdev_priv(dev);
2240 unregister_netdev(dev);
2242 pci_iounmap(pdev, rp->base);
2243 pci_release_regions(pdev);
2246 pci_disable_device(pdev);
2247 pci_set_drvdata(pdev, NULL);
2250 static void rhine_shutdown (struct pci_dev *pdev)
2252 struct net_device *dev = pci_get_drvdata(pdev);
2253 struct rhine_private *rp = netdev_priv(dev);
2254 void __iomem *ioaddr = rp->base;
2256 if (!(rp->quirks & rqWOL))
2257 return; /* Nothing to do for non-WOL adapters */
2259 rhine_power_init(dev);
2261 /* Make sure we use pattern 0, 1 and not 4, 5 */
2262 if (rp->quirks & rq6patterns)
2263 iowrite8(0x04, ioaddr + WOLcgClr);
2265 spin_lock(&rp->lock);
2267 if (rp->wolopts & WAKE_MAGIC) {
2268 iowrite8(WOLmagic, ioaddr + WOLcrSet);
2270 * Turn EEPROM-controlled wake-up back on -- some hardware may
2271 * not cooperate otherwise.
2273 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
2276 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
2277 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
2279 if (rp->wolopts & WAKE_PHY)
2280 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
2282 if (rp->wolopts & WAKE_UCAST)
2283 iowrite8(WOLucast, ioaddr + WOLcrSet);
2286 /* Enable legacy WOL (for old motherboards) */
2287 iowrite8(0x01, ioaddr + PwcfgSet);
2288 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
2291 spin_unlock(&rp->lock);
2293 if (system_state == SYSTEM_POWER_OFF && !avoid_D3) {
2294 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
2296 pci_wake_from_d3(pdev, true);
2297 pci_set_power_state(pdev, PCI_D3hot);
2301 #ifdef CONFIG_PM_SLEEP
2302 static int rhine_suspend(struct device *device)
2304 struct pci_dev *pdev = to_pci_dev(device);
2305 struct net_device *dev = pci_get_drvdata(pdev);
2306 struct rhine_private *rp = netdev_priv(dev);
2308 if (!netif_running(dev))
2311 rhine_task_disable(rp);
2312 rhine_irq_disable(rp);
2313 napi_disable(&rp->napi);
2315 netif_device_detach(dev);
2317 rhine_shutdown(pdev);
2322 static int rhine_resume(struct device *device)
2324 struct pci_dev *pdev = to_pci_dev(device);
2325 struct net_device *dev = pci_get_drvdata(pdev);
2326 struct rhine_private *rp = netdev_priv(dev);
2328 if (!netif_running(dev))
2332 enable_mmio(rp->pioaddr, rp->quirks);
2334 rhine_power_init(dev);
2339 rhine_task_enable(rp);
2340 spin_lock_bh(&rp->lock);
2341 init_registers(dev);
2342 spin_unlock_bh(&rp->lock);
2344 netif_device_attach(dev);
2349 static SIMPLE_DEV_PM_OPS(rhine_pm_ops, rhine_suspend, rhine_resume);
2350 #define RHINE_PM_OPS (&rhine_pm_ops)
2354 #define RHINE_PM_OPS NULL
2356 #endif /* !CONFIG_PM_SLEEP */
2358 static struct pci_driver rhine_driver = {
2360 .id_table = rhine_pci_tbl,
2361 .probe = rhine_init_one,
2362 .remove = __devexit_p(rhine_remove_one),
2363 .shutdown = rhine_shutdown,
2364 .driver.pm = RHINE_PM_OPS,
2367 static struct dmi_system_id __initdata rhine_dmi_table[] = {
2371 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
2372 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2378 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
2379 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2385 static int __init rhine_init(void)
2387 /* when a module, this is printed whether or not devices are found in probe */
2389 pr_info("%s\n", version);
2391 if (dmi_check_system(rhine_dmi_table)) {
2392 /* these BIOSes fail at PXE boot if chip is in D3 */
2394 pr_warn("Broken BIOS detected, avoid_D3 enabled\n");
2397 pr_info("avoid_D3 set\n");
2399 return pci_register_driver(&rhine_driver);
2403 static void __exit rhine_cleanup(void)
2405 pci_unregister_driver(&rhine_driver);
2409 module_init(rhine_init);
2410 module_exit(rhine_cleanup);