Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger...
[cascardo/linux.git] / drivers / net / hamradio / dmascc.c
1 /*
2  * Driver for high-speed SCC boards (those with DMA support)
3  * Copyright (C) 1997-2000 Klaus Kudielka
4  *
5  * S5SCC/DMA support by Janko Koleznik S52HI
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21
22
23 #include <linux/module.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/errno.h>
27 #include <linux/if_arp.h>
28 #include <linux/in.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/kernel.h>
33 #include <linux/mm.h>
34 #include <linux/netdevice.h>
35 #include <linux/slab.h>
36 #include <linux/rtnetlink.h>
37 #include <linux/sockios.h>
38 #include <linux/workqueue.h>
39 #include <linux/atomic.h>
40 #include <asm/dma.h>
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/uaccess.h>
44 #include <net/ax25.h>
45 #include "z8530.h"
46
47
48 /* Number of buffers per channel */
49
50 #define NUM_TX_BUF      2       /* NUM_TX_BUF >= 1 (min. 2 recommended) */
51 #define NUM_RX_BUF      6       /* NUM_RX_BUF >= 1 (min. 2 recommended) */
52 #define BUF_SIZE        1576    /* BUF_SIZE >= mtu + hard_header_len */
53
54
55 /* Cards supported */
56
57 #define HW_PI           { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
58                             0, 8, 1843200, 3686400 }
59 #define HW_PI2          { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
60                             0, 8, 3686400, 7372800 }
61 #define HW_TWIN         { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
62                             0, 4, 6144000, 6144000 }
63 #define HW_S5           { "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \
64                           0, 8, 4915200, 9830400 }
65
66 #define HARDWARE        { HW_PI, HW_PI2, HW_TWIN, HW_S5 }
67
68 #define TMR_0_HZ        25600   /* Frequency of timer 0 */
69
70 #define TYPE_PI         0
71 #define TYPE_PI2        1
72 #define TYPE_TWIN       2
73 #define TYPE_S5         3
74 #define NUM_TYPES       4
75
76 #define MAX_NUM_DEVS    32
77
78
79 /* SCC chips supported */
80
81 #define Z8530           0
82 #define Z85C30          1
83 #define Z85230          2
84
85 #define CHIPNAMES       { "Z8530", "Z85C30", "Z85230" }
86
87
88 /* I/O registers */
89
90 /* 8530 registers relative to card base */
91 #define SCCB_CMD        0x00
92 #define SCCB_DATA       0x01
93 #define SCCA_CMD        0x02
94 #define SCCA_DATA       0x03
95
96 /* 8253/8254 registers relative to card base */
97 #define TMR_CNT0        0x00
98 #define TMR_CNT1        0x01
99 #define TMR_CNT2        0x02
100 #define TMR_CTRL        0x03
101
102 /* Additional PI/PI2 registers relative to card base */
103 #define PI_DREQ_MASK    0x04
104
105 /* Additional PackeTwin registers relative to card base */
106 #define TWIN_INT_REG    0x08
107 #define TWIN_CLR_TMR1   0x09
108 #define TWIN_CLR_TMR2   0x0a
109 #define TWIN_SPARE_1    0x0b
110 #define TWIN_DMA_CFG    0x08
111 #define TWIN_SERIAL_CFG 0x09
112 #define TWIN_DMA_CLR_FF 0x0a
113 #define TWIN_SPARE_2    0x0b
114
115
116 /* PackeTwin I/O register values */
117
118 /* INT_REG */
119 #define TWIN_SCC_MSK       0x01
120 #define TWIN_TMR1_MSK      0x02
121 #define TWIN_TMR2_MSK      0x04
122 #define TWIN_INT_MSK       0x07
123
124 /* SERIAL_CFG */
125 #define TWIN_DTRA_ON       0x01
126 #define TWIN_DTRB_ON       0x02
127 #define TWIN_EXTCLKA       0x04
128 #define TWIN_EXTCLKB       0x08
129 #define TWIN_LOOPA_ON      0x10
130 #define TWIN_LOOPB_ON      0x20
131 #define TWIN_EI            0x80
132
133 /* DMA_CFG */
134 #define TWIN_DMA_HDX_T1    0x08
135 #define TWIN_DMA_HDX_R1    0x0a
136 #define TWIN_DMA_HDX_T3    0x14
137 #define TWIN_DMA_HDX_R3    0x16
138 #define TWIN_DMA_FDX_T3R1  0x1b
139 #define TWIN_DMA_FDX_T1R3  0x1d
140
141
142 /* Status values */
143
144 #define IDLE      0
145 #define TX_HEAD   1
146 #define TX_DATA   2
147 #define TX_PAUSE  3
148 #define TX_TAIL   4
149 #define RTS_OFF   5
150 #define WAIT      6
151 #define DCD_ON    7
152 #define RX_ON     8
153 #define DCD_OFF   9
154
155
156 /* Ioctls */
157
158 #define SIOCGSCCPARAM SIOCDEVPRIVATE
159 #define SIOCSSCCPARAM (SIOCDEVPRIVATE+1)
160
161
162 /* Data types */
163
164 struct scc_param {
165         int pclk_hz;            /* frequency of BRG input (don't change) */
166         int brg_tc;             /* BRG terminal count; BRG disabled if < 0 */
167         int nrzi;               /* 0 (nrz), 1 (nrzi) */
168         int clocks;             /* see dmascc_cfg documentation */
169         int txdelay;            /* [1/TMR_0_HZ] */
170         int txtimeout;          /* [1/HZ] */
171         int txtail;             /* [1/TMR_0_HZ] */
172         int waittime;           /* [1/TMR_0_HZ] */
173         int slottime;           /* [1/TMR_0_HZ] */
174         int persist;            /* 1 ... 256 */
175         int dma;                /* -1 (disable), 0, 1, 3 */
176         int txpause;            /* [1/TMR_0_HZ] */
177         int rtsoff;             /* [1/TMR_0_HZ] */
178         int dcdon;              /* [1/TMR_0_HZ] */
179         int dcdoff;             /* [1/TMR_0_HZ] */
180 };
181
182 struct scc_hardware {
183         char *name;
184         int io_region;
185         int io_delta;
186         int io_size;
187         int num_devs;
188         int scc_offset;
189         int tmr_offset;
190         int tmr_hz;
191         int pclk_hz;
192 };
193
194 struct scc_priv {
195         int type;
196         int chip;
197         struct net_device *dev;
198         struct scc_info *info;
199
200         int channel;
201         int card_base, scc_cmd, scc_data;
202         int tmr_cnt, tmr_ctrl, tmr_mode;
203         struct scc_param param;
204         char rx_buf[NUM_RX_BUF][BUF_SIZE];
205         int rx_len[NUM_RX_BUF];
206         int rx_ptr;
207         struct work_struct rx_work;
208         int rx_head, rx_tail, rx_count;
209         int rx_over;
210         char tx_buf[NUM_TX_BUF][BUF_SIZE];
211         int tx_len[NUM_TX_BUF];
212         int tx_ptr;
213         int tx_head, tx_tail, tx_count;
214         int state;
215         unsigned long tx_start;
216         int rr0;
217         spinlock_t *register_lock;      /* Per scc_info */
218         spinlock_t ring_lock;
219 };
220
221 struct scc_info {
222         int irq_used;
223         int twin_serial_cfg;
224         struct net_device *dev[2];
225         struct scc_priv priv[2];
226         struct scc_info *next;
227         spinlock_t register_lock;       /* Per device register lock */
228 };
229
230
231 /* Function declarations */
232 static int setup_adapter(int card_base, int type, int n) __init;
233
234 static void write_scc(struct scc_priv *priv, int reg, int val);
235 static void write_scc_data(struct scc_priv *priv, int val, int fast);
236 static int read_scc(struct scc_priv *priv, int reg);
237 static int read_scc_data(struct scc_priv *priv);
238
239 static int scc_open(struct net_device *dev);
240 static int scc_close(struct net_device *dev);
241 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
242 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev);
243 static int scc_set_mac_address(struct net_device *dev, void *sa);
244
245 static inline void tx_on(struct scc_priv *priv);
246 static inline void rx_on(struct scc_priv *priv);
247 static inline void rx_off(struct scc_priv *priv);
248 static void start_timer(struct scc_priv *priv, int t, int r15);
249 static inline unsigned char random(void);
250
251 static inline void z8530_isr(struct scc_info *info);
252 static irqreturn_t scc_isr(int irq, void *dev_id);
253 static void rx_isr(struct scc_priv *priv);
254 static void special_condition(struct scc_priv *priv, int rc);
255 static void rx_bh(struct work_struct *);
256 static void tx_isr(struct scc_priv *priv);
257 static void es_isr(struct scc_priv *priv);
258 static void tm_isr(struct scc_priv *priv);
259
260
261 /* Initialization variables */
262
263 static int io[MAX_NUM_DEVS] __initdata = { 0, };
264
265 /* Beware! hw[] is also used in dmascc_exit(). */
266 static struct scc_hardware hw[NUM_TYPES] = HARDWARE;
267
268
269 /* Global variables */
270
271 static struct scc_info *first;
272 static unsigned long rand;
273
274
275 MODULE_AUTHOR("Klaus Kudielka");
276 MODULE_DESCRIPTION("Driver for high-speed SCC boards");
277 module_param_array(io, int, NULL, 0);
278 MODULE_LICENSE("GPL");
279
280 static void __exit dmascc_exit(void)
281 {
282         int i;
283         struct scc_info *info;
284
285         while (first) {
286                 info = first;
287
288                 /* Unregister devices */
289                 for (i = 0; i < 2; i++)
290                         unregister_netdev(info->dev[i]);
291
292                 /* Reset board */
293                 if (info->priv[0].type == TYPE_TWIN)
294                         outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
295                 write_scc(&info->priv[0], R9, FHWRES);
296                 release_region(info->dev[0]->base_addr,
297                                hw[info->priv[0].type].io_size);
298
299                 for (i = 0; i < 2; i++)
300                         free_netdev(info->dev[i]);
301
302                 /* Free memory */
303                 first = info->next;
304                 kfree(info);
305         }
306 }
307
308 static int __init dmascc_init(void)
309 {
310         int h, i, j, n;
311         int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS],
312             t1[MAX_NUM_DEVS];
313         unsigned t_val;
314         unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS],
315             counting[MAX_NUM_DEVS];
316
317         /* Initialize random number generator */
318         rand = jiffies;
319         /* Cards found = 0 */
320         n = 0;
321         /* Warning message */
322         if (!io[0])
323                 printk(KERN_INFO "dmascc: autoprobing (dangerous)\n");
324
325         /* Run autodetection for each card type */
326         for (h = 0; h < NUM_TYPES; h++) {
327
328                 if (io[0]) {
329                         /* User-specified I/O address regions */
330                         for (i = 0; i < hw[h].num_devs; i++)
331                                 base[i] = 0;
332                         for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {
333                                 j = (io[i] -
334                                      hw[h].io_region) / hw[h].io_delta;
335                                 if (j >= 0 && j < hw[h].num_devs &&
336                                     hw[h].io_region +
337                                     j * hw[h].io_delta == io[i]) {
338                                         base[j] = io[i];
339                                 }
340                         }
341                 } else {
342                         /* Default I/O address regions */
343                         for (i = 0; i < hw[h].num_devs; i++) {
344                                 base[i] =
345                                     hw[h].io_region + i * hw[h].io_delta;
346                         }
347                 }
348
349                 /* Check valid I/O address regions */
350                 for (i = 0; i < hw[h].num_devs; i++)
351                         if (base[i]) {
352                                 if (!request_region
353                                     (base[i], hw[h].io_size, "dmascc"))
354                                         base[i] = 0;
355                                 else {
356                                         tcmd[i] =
357                                             base[i] + hw[h].tmr_offset +
358                                             TMR_CTRL;
359                                         t0[i] =
360                                             base[i] + hw[h].tmr_offset +
361                                             TMR_CNT0;
362                                         t1[i] =
363                                             base[i] + hw[h].tmr_offset +
364                                             TMR_CNT1;
365                                 }
366                         }
367
368                 /* Start timers */
369                 for (i = 0; i < hw[h].num_devs; i++)
370                         if (base[i]) {
371                                 /* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */
372                                 outb(0x36, tcmd[i]);
373                                 outb((hw[h].tmr_hz / TMR_0_HZ) & 0xFF,
374                                      t0[i]);
375                                 outb((hw[h].tmr_hz / TMR_0_HZ) >> 8,
376                                      t0[i]);
377                                 /* Timer 1: LSB+MSB, Mode 0, HZ/10 */
378                                 outb(0x70, tcmd[i]);
379                                 outb((TMR_0_HZ / HZ * 10) & 0xFF, t1[i]);
380                                 outb((TMR_0_HZ / HZ * 10) >> 8, t1[i]);
381                                 start[i] = jiffies;
382                                 delay[i] = 0;
383                                 counting[i] = 1;
384                                 /* Timer 2: LSB+MSB, Mode 0 */
385                                 outb(0xb0, tcmd[i]);
386                         }
387                 time = jiffies;
388                 /* Wait until counter registers are loaded */
389                 udelay(2000000 / TMR_0_HZ);
390
391                 /* Timing loop */
392                 while (jiffies - time < 13) {
393                         for (i = 0; i < hw[h].num_devs; i++)
394                                 if (base[i] && counting[i]) {
395                                         /* Read back Timer 1: latch; read LSB; read MSB */
396                                         outb(0x40, tcmd[i]);
397                                         t_val =
398                                             inb(t1[i]) + (inb(t1[i]) << 8);
399                                         /* Also check whether counter did wrap */
400                                         if (t_val == 0 ||
401                                             t_val > TMR_0_HZ / HZ * 10)
402                                                 counting[i] = 0;
403                                         delay[i] = jiffies - start[i];
404                                 }
405                 }
406
407                 /* Evaluate measurements */
408                 for (i = 0; i < hw[h].num_devs; i++)
409                         if (base[i]) {
410                                 if ((delay[i] >= 9 && delay[i] <= 11) &&
411                                     /* Ok, we have found an adapter */
412                                     (setup_adapter(base[i], h, n) == 0))
413                                         n++;
414                                 else
415                                         release_region(base[i],
416                                                        hw[h].io_size);
417                         }
418
419         }                       /* NUM_TYPES */
420
421         /* If any adapter was successfully initialized, return ok */
422         if (n)
423                 return 0;
424
425         /* If no adapter found, return error */
426         printk(KERN_INFO "dmascc: no adapters found\n");
427         return -EIO;
428 }
429
430 module_init(dmascc_init);
431 module_exit(dmascc_exit);
432
433 static void __init dev_setup(struct net_device *dev)
434 {
435         dev->type = ARPHRD_AX25;
436         dev->hard_header_len = AX25_MAX_HEADER_LEN;
437         dev->mtu = 1500;
438         dev->addr_len = AX25_ADDR_LEN;
439         dev->tx_queue_len = 64;
440         memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
441         memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
442 }
443
444 static const struct net_device_ops scc_netdev_ops = {
445         .ndo_open = scc_open,
446         .ndo_stop = scc_close,
447         .ndo_start_xmit = scc_send_packet,
448         .ndo_do_ioctl = scc_ioctl,
449         .ndo_set_mac_address = scc_set_mac_address,
450 };
451
452 static int __init setup_adapter(int card_base, int type, int n)
453 {
454         int i, irq, chip;
455         struct scc_info *info;
456         struct net_device *dev;
457         struct scc_priv *priv;
458         unsigned long time;
459         unsigned int irqs;
460         int tmr_base = card_base + hw[type].tmr_offset;
461         int scc_base = card_base + hw[type].scc_offset;
462         char *chipnames[] = CHIPNAMES;
463
464         /* Initialize what is necessary for write_scc and write_scc_data */
465         info = kzalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA);
466         if (!info)
467                 goto out;
468
469         info->dev[0] = alloc_netdev(0, "", NET_NAME_UNKNOWN, dev_setup);
470         if (!info->dev[0]) {
471                 printk(KERN_ERR "dmascc: "
472                        "could not allocate memory for %s at %#3x\n",
473                        hw[type].name, card_base);
474                 goto out1;
475         }
476
477         info->dev[1] = alloc_netdev(0, "", NET_NAME_UNKNOWN, dev_setup);
478         if (!info->dev[1]) {
479                 printk(KERN_ERR "dmascc: "
480                        "could not allocate memory for %s at %#3x\n",
481                        hw[type].name, card_base);
482                 goto out2;
483         }
484         spin_lock_init(&info->register_lock);
485
486         priv = &info->priv[0];
487         priv->type = type;
488         priv->card_base = card_base;
489         priv->scc_cmd = scc_base + SCCA_CMD;
490         priv->scc_data = scc_base + SCCA_DATA;
491         priv->register_lock = &info->register_lock;
492
493         /* Reset SCC */
494         write_scc(priv, R9, FHWRES | MIE | NV);
495
496         /* Determine type of chip by enabling SDLC/HDLC enhancements */
497         write_scc(priv, R15, SHDLCE);
498         if (!read_scc(priv, R15)) {
499                 /* WR7' not present. This is an ordinary Z8530 SCC. */
500                 chip = Z8530;
501         } else {
502                 /* Put one character in TX FIFO */
503                 write_scc_data(priv, 0, 0);
504                 if (read_scc(priv, R0) & Tx_BUF_EMP) {
505                         /* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
506                         chip = Z85230;
507                 } else {
508                         /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
509                         chip = Z85C30;
510                 }
511         }
512         write_scc(priv, R15, 0);
513
514         /* Start IRQ auto-detection */
515         irqs = probe_irq_on();
516
517         /* Enable interrupts */
518         if (type == TYPE_TWIN) {
519                 outb(0, card_base + TWIN_DMA_CFG);
520                 inb(card_base + TWIN_CLR_TMR1);
521                 inb(card_base + TWIN_CLR_TMR2);
522                 info->twin_serial_cfg = TWIN_EI;
523                 outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG);
524         } else {
525                 write_scc(priv, R15, CTSIE);
526                 write_scc(priv, R0, RES_EXT_INT);
527                 write_scc(priv, R1, EXT_INT_ENAB);
528         }
529
530         /* Start timer */
531         outb(1, tmr_base + TMR_CNT1);
532         outb(0, tmr_base + TMR_CNT1);
533
534         /* Wait and detect IRQ */
535         time = jiffies;
536         while (jiffies - time < 2 + HZ / TMR_0_HZ);
537         irq = probe_irq_off(irqs);
538
539         /* Clear pending interrupt, disable interrupts */
540         if (type == TYPE_TWIN) {
541                 inb(card_base + TWIN_CLR_TMR1);
542         } else {
543                 write_scc(priv, R1, 0);
544                 write_scc(priv, R15, 0);
545                 write_scc(priv, R0, RES_EXT_INT);
546         }
547
548         if (irq <= 0) {
549                 printk(KERN_ERR
550                        "dmascc: could not find irq of %s at %#3x (irq=%d)\n",
551                        hw[type].name, card_base, irq);
552                 goto out3;
553         }
554
555         /* Set up data structures */
556         for (i = 0; i < 2; i++) {
557                 dev = info->dev[i];
558                 priv = &info->priv[i];
559                 priv->type = type;
560                 priv->chip = chip;
561                 priv->dev = dev;
562                 priv->info = info;
563                 priv->channel = i;
564                 spin_lock_init(&priv->ring_lock);
565                 priv->register_lock = &info->register_lock;
566                 priv->card_base = card_base;
567                 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD);
568                 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA);
569                 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
570                 priv->tmr_ctrl = tmr_base + TMR_CTRL;
571                 priv->tmr_mode = i ? 0xb0 : 0x70;
572                 priv->param.pclk_hz = hw[type].pclk_hz;
573                 priv->param.brg_tc = -1;
574                 priv->param.clocks = TCTRxCP | RCRTxCP;
575                 priv->param.persist = 256;
576                 priv->param.dma = -1;
577                 INIT_WORK(&priv->rx_work, rx_bh);
578                 dev->ml_priv = priv;
579                 sprintf(dev->name, "dmascc%i", 2 * n + i);
580                 dev->base_addr = card_base;
581                 dev->irq = irq;
582                 dev->netdev_ops = &scc_netdev_ops;
583                 dev->header_ops = &ax25_header_ops;
584         }
585         if (register_netdev(info->dev[0])) {
586                 printk(KERN_ERR "dmascc: could not register %s\n",
587                        info->dev[0]->name);
588                 goto out3;
589         }
590         if (register_netdev(info->dev[1])) {
591                 printk(KERN_ERR "dmascc: could not register %s\n",
592                        info->dev[1]->name);
593                 goto out4;
594         }
595
596
597         info->next = first;
598         first = info;
599         printk(KERN_INFO "dmascc: found %s (%s) at %#3x, irq %d\n",
600                hw[type].name, chipnames[chip], card_base, irq);
601         return 0;
602
603       out4:
604         unregister_netdev(info->dev[0]);
605       out3:
606         if (info->priv[0].type == TYPE_TWIN)
607                 outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
608         write_scc(&info->priv[0], R9, FHWRES);
609         free_netdev(info->dev[1]);
610       out2:
611         free_netdev(info->dev[0]);
612       out1:
613         kfree(info);
614       out:
615         return -1;
616 }
617
618
619 /* Driver functions */
620
621 static void write_scc(struct scc_priv *priv, int reg, int val)
622 {
623         unsigned long flags;
624         switch (priv->type) {
625         case TYPE_S5:
626                 if (reg)
627                         outb(reg, priv->scc_cmd);
628                 outb(val, priv->scc_cmd);
629                 return;
630         case TYPE_TWIN:
631                 if (reg)
632                         outb_p(reg, priv->scc_cmd);
633                 outb_p(val, priv->scc_cmd);
634                 return;
635         default:
636                 spin_lock_irqsave(priv->register_lock, flags);
637                 outb_p(0, priv->card_base + PI_DREQ_MASK);
638                 if (reg)
639                         outb_p(reg, priv->scc_cmd);
640                 outb_p(val, priv->scc_cmd);
641                 outb(1, priv->card_base + PI_DREQ_MASK);
642                 spin_unlock_irqrestore(priv->register_lock, flags);
643                 return;
644         }
645 }
646
647
648 static void write_scc_data(struct scc_priv *priv, int val, int fast)
649 {
650         unsigned long flags;
651         switch (priv->type) {
652         case TYPE_S5:
653                 outb(val, priv->scc_data);
654                 return;
655         case TYPE_TWIN:
656                 outb_p(val, priv->scc_data);
657                 return;
658         default:
659                 if (fast)
660                         outb_p(val, priv->scc_data);
661                 else {
662                         spin_lock_irqsave(priv->register_lock, flags);
663                         outb_p(0, priv->card_base + PI_DREQ_MASK);
664                         outb_p(val, priv->scc_data);
665                         outb(1, priv->card_base + PI_DREQ_MASK);
666                         spin_unlock_irqrestore(priv->register_lock, flags);
667                 }
668                 return;
669         }
670 }
671
672
673 static int read_scc(struct scc_priv *priv, int reg)
674 {
675         int rc;
676         unsigned long flags;
677         switch (priv->type) {
678         case TYPE_S5:
679                 if (reg)
680                         outb(reg, priv->scc_cmd);
681                 return inb(priv->scc_cmd);
682         case TYPE_TWIN:
683                 if (reg)
684                         outb_p(reg, priv->scc_cmd);
685                 return inb_p(priv->scc_cmd);
686         default:
687                 spin_lock_irqsave(priv->register_lock, flags);
688                 outb_p(0, priv->card_base + PI_DREQ_MASK);
689                 if (reg)
690                         outb_p(reg, priv->scc_cmd);
691                 rc = inb_p(priv->scc_cmd);
692                 outb(1, priv->card_base + PI_DREQ_MASK);
693                 spin_unlock_irqrestore(priv->register_lock, flags);
694                 return rc;
695         }
696 }
697
698
699 static int read_scc_data(struct scc_priv *priv)
700 {
701         int rc;
702         unsigned long flags;
703         switch (priv->type) {
704         case TYPE_S5:
705                 return inb(priv->scc_data);
706         case TYPE_TWIN:
707                 return inb_p(priv->scc_data);
708         default:
709                 spin_lock_irqsave(priv->register_lock, flags);
710                 outb_p(0, priv->card_base + PI_DREQ_MASK);
711                 rc = inb_p(priv->scc_data);
712                 outb(1, priv->card_base + PI_DREQ_MASK);
713                 spin_unlock_irqrestore(priv->register_lock, flags);
714                 return rc;
715         }
716 }
717
718
719 static int scc_open(struct net_device *dev)
720 {
721         struct scc_priv *priv = dev->ml_priv;
722         struct scc_info *info = priv->info;
723         int card_base = priv->card_base;
724
725         /* Request IRQ if not already used by other channel */
726         if (!info->irq_used) {
727                 if (request_irq(dev->irq, scc_isr, 0, "dmascc", info)) {
728                         return -EAGAIN;
729                 }
730         }
731         info->irq_used++;
732
733         /* Request DMA if required */
734         if (priv->param.dma >= 0) {
735                 if (request_dma(priv->param.dma, "dmascc")) {
736                         if (--info->irq_used == 0)
737                                 free_irq(dev->irq, info);
738                         return -EAGAIN;
739                 } else {
740                         unsigned long flags = claim_dma_lock();
741                         clear_dma_ff(priv->param.dma);
742                         release_dma_lock(flags);
743                 }
744         }
745
746         /* Initialize local variables */
747         priv->rx_ptr = 0;
748         priv->rx_over = 0;
749         priv->rx_head = priv->rx_tail = priv->rx_count = 0;
750         priv->state = IDLE;
751         priv->tx_head = priv->tx_tail = priv->tx_count = 0;
752         priv->tx_ptr = 0;
753
754         /* Reset channel */
755         write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
756         /* X1 clock, SDLC mode */
757         write_scc(priv, R4, SDLC | X1CLK);
758         /* DMA */
759         write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
760         /* 8 bit RX char, RX disable */
761         write_scc(priv, R3, Rx8);
762         /* 8 bit TX char, TX disable */
763         write_scc(priv, R5, Tx8);
764         /* SDLC address field */
765         write_scc(priv, R6, 0);
766         /* SDLC flag */
767         write_scc(priv, R7, FLAG);
768         switch (priv->chip) {
769         case Z85C30:
770                 /* Select WR7' */
771                 write_scc(priv, R15, SHDLCE);
772                 /* Auto EOM reset */
773                 write_scc(priv, R7, AUTOEOM);
774                 write_scc(priv, R15, 0);
775                 break;
776         case Z85230:
777                 /* Select WR7' */
778                 write_scc(priv, R15, SHDLCE);
779                 /* The following bits are set (see 2.5.2.1):
780                    - Automatic EOM reset
781                    - Interrupt request if RX FIFO is half full
782                    This bit should be ignored in DMA mode (according to the
783                    documentation), but actually isn't. The receiver doesn't work if
784                    it is set. Thus, we have to clear it in DMA mode.
785                    - Interrupt/DMA request if TX FIFO is completely empty
786                    a) If set, the ESCC behaves as if it had no TX FIFO (Z85C30
787                    compatibility).
788                    b) If cleared, DMA requests may follow each other very quickly,
789                    filling up the TX FIFO.
790                    Advantage: TX works even in case of high bus latency.
791                    Disadvantage: Edge-triggered DMA request circuitry may miss
792                    a request. No more data is delivered, resulting
793                    in a TX FIFO underrun.
794                    Both PI2 and S5SCC/DMA seem to work fine with TXFIFOE cleared.
795                    The PackeTwin doesn't. I don't know about the PI, but let's
796                    assume it behaves like the PI2.
797                  */
798                 if (priv->param.dma >= 0) {
799                         if (priv->type == TYPE_TWIN)
800                                 write_scc(priv, R7, AUTOEOM | TXFIFOE);
801                         else
802                                 write_scc(priv, R7, AUTOEOM);
803                 } else {
804                         write_scc(priv, R7, AUTOEOM | RXFIFOH);
805                 }
806                 write_scc(priv, R15, 0);
807                 break;
808         }
809         /* Preset CRC, NRZ(I) encoding */
810         write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
811
812         /* Configure baud rate generator */
813         if (priv->param.brg_tc >= 0) {
814                 /* Program BR generator */
815                 write_scc(priv, R12, priv->param.brg_tc & 0xFF);
816                 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);
817                 /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
818                    PackeTwin, not connected on the PI2); set DPLL source to BRG */
819                 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
820                 /* Enable DPLL */
821                 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
822         } else {
823                 /* Disable BR generator */
824                 write_scc(priv, R14, DTRREQ | BRSRC);
825         }
826
827         /* Configure clocks */
828         if (priv->type == TYPE_TWIN) {
829                 /* Disable external TX clock receiver */
830                 outb((info->twin_serial_cfg &=
831                       ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
832                      card_base + TWIN_SERIAL_CFG);
833         }
834         write_scc(priv, R11, priv->param.clocks);
835         if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
836                 /* Enable external TX clock receiver */
837                 outb((info->twin_serial_cfg |=
838                       (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
839                      card_base + TWIN_SERIAL_CFG);
840         }
841
842         /* Configure PackeTwin */
843         if (priv->type == TYPE_TWIN) {
844                 /* Assert DTR, enable interrupts */
845                 outb((info->twin_serial_cfg |= TWIN_EI |
846                       (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
847                      card_base + TWIN_SERIAL_CFG);
848         }
849
850         /* Read current status */
851         priv->rr0 = read_scc(priv, R0);
852         /* Enable DCD interrupt */
853         write_scc(priv, R15, DCDIE);
854
855         netif_start_queue(dev);
856
857         return 0;
858 }
859
860
861 static int scc_close(struct net_device *dev)
862 {
863         struct scc_priv *priv = dev->ml_priv;
864         struct scc_info *info = priv->info;
865         int card_base = priv->card_base;
866
867         netif_stop_queue(dev);
868
869         if (priv->type == TYPE_TWIN) {
870                 /* Drop DTR */
871                 outb((info->twin_serial_cfg &=
872                       (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
873                      card_base + TWIN_SERIAL_CFG);
874         }
875
876         /* Reset channel, free DMA and IRQ */
877         write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
878         if (priv->param.dma >= 0) {
879                 if (priv->type == TYPE_TWIN)
880                         outb(0, card_base + TWIN_DMA_CFG);
881                 free_dma(priv->param.dma);
882         }
883         if (--info->irq_used == 0)
884                 free_irq(dev->irq, info);
885
886         return 0;
887 }
888
889
890 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
891 {
892         struct scc_priv *priv = dev->ml_priv;
893
894         switch (cmd) {
895         case SIOCGSCCPARAM:
896                 if (copy_to_user
897                     (ifr->ifr_data, &priv->param,
898                      sizeof(struct scc_param)))
899                         return -EFAULT;
900                 return 0;
901         case SIOCSSCCPARAM:
902                 if (!capable(CAP_NET_ADMIN))
903                         return -EPERM;
904                 if (netif_running(dev))
905                         return -EAGAIN;
906                 if (copy_from_user
907                     (&priv->param, ifr->ifr_data,
908                      sizeof(struct scc_param)))
909                         return -EFAULT;
910                 return 0;
911         default:
912                 return -EINVAL;
913         }
914 }
915
916
917 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev)
918 {
919         struct scc_priv *priv = dev->ml_priv;
920         unsigned long flags;
921         int i;
922
923         /* Temporarily stop the scheduler feeding us packets */
924         netif_stop_queue(dev);
925
926         /* Transfer data to DMA buffer */
927         i = priv->tx_head;
928         skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1);
929         priv->tx_len[i] = skb->len - 1;
930
931         /* Clear interrupts while we touch our circular buffers */
932
933         spin_lock_irqsave(&priv->ring_lock, flags);
934         /* Move the ring buffer's head */
935         priv->tx_head = (i + 1) % NUM_TX_BUF;
936         priv->tx_count++;
937
938         /* If we just filled up the last buffer, leave queue stopped.
939            The higher layers must wait until we have a DMA buffer
940            to accept the data. */
941         if (priv->tx_count < NUM_TX_BUF)
942                 netif_wake_queue(dev);
943
944         /* Set new TX state */
945         if (priv->state == IDLE) {
946                 /* Assert RTS, start timer */
947                 priv->state = TX_HEAD;
948                 priv->tx_start = jiffies;
949                 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
950                 write_scc(priv, R15, 0);
951                 start_timer(priv, priv->param.txdelay, 0);
952         }
953
954         /* Turn interrupts back on and free buffer */
955         spin_unlock_irqrestore(&priv->ring_lock, flags);
956         dev_kfree_skb(skb);
957
958         return NETDEV_TX_OK;
959 }
960
961
962 static int scc_set_mac_address(struct net_device *dev, void *sa)
963 {
964         memcpy(dev->dev_addr, ((struct sockaddr *) sa)->sa_data,
965                dev->addr_len);
966         return 0;
967 }
968
969
970 static inline void tx_on(struct scc_priv *priv)
971 {
972         int i, n;
973         unsigned long flags;
974
975         if (priv->param.dma >= 0) {
976                 n = (priv->chip == Z85230) ? 3 : 1;
977                 /* Program DMA controller */
978                 flags = claim_dma_lock();
979                 set_dma_mode(priv->param.dma, DMA_MODE_WRITE);
980                 set_dma_addr(priv->param.dma,
981                              (int) priv->tx_buf[priv->tx_tail] + n);
982                 set_dma_count(priv->param.dma,
983                               priv->tx_len[priv->tx_tail] - n);
984                 release_dma_lock(flags);
985                 /* Enable TX underrun interrupt */
986                 write_scc(priv, R15, TxUIE);
987                 /* Configure DREQ */
988                 if (priv->type == TYPE_TWIN)
989                         outb((priv->param.dma ==
990                               1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3,
991                              priv->card_base + TWIN_DMA_CFG);
992                 else
993                         write_scc(priv, R1,
994                                   EXT_INT_ENAB | WT_FN_RDYFN |
995                                   WT_RDY_ENAB);
996                 /* Write first byte(s) */
997                 spin_lock_irqsave(priv->register_lock, flags);
998                 for (i = 0; i < n; i++)
999                         write_scc_data(priv,
1000                                        priv->tx_buf[priv->tx_tail][i], 1);
1001                 enable_dma(priv->param.dma);
1002                 spin_unlock_irqrestore(priv->register_lock, flags);
1003         } else {
1004                 write_scc(priv, R15, TxUIE);
1005                 write_scc(priv, R1,
1006                           EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB);
1007                 tx_isr(priv);
1008         }
1009         /* Reset EOM latch if we do not have the AUTOEOM feature */
1010         if (priv->chip == Z8530)
1011                 write_scc(priv, R0, RES_EOM_L);
1012 }
1013
1014
1015 static inline void rx_on(struct scc_priv *priv)
1016 {
1017         unsigned long flags;
1018
1019         /* Clear RX FIFO */
1020         while (read_scc(priv, R0) & Rx_CH_AV)
1021                 read_scc_data(priv);
1022         priv->rx_over = 0;
1023         if (priv->param.dma >= 0) {
1024                 /* Program DMA controller */
1025                 flags = claim_dma_lock();
1026                 set_dma_mode(priv->param.dma, DMA_MODE_READ);
1027                 set_dma_addr(priv->param.dma,
1028                              (int) priv->rx_buf[priv->rx_head]);
1029                 set_dma_count(priv->param.dma, BUF_SIZE);
1030                 release_dma_lock(flags);
1031                 enable_dma(priv->param.dma);
1032                 /* Configure PackeTwin DMA */
1033                 if (priv->type == TYPE_TWIN) {
1034                         outb((priv->param.dma ==
1035                               1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3,
1036                              priv->card_base + TWIN_DMA_CFG);
1037                 }
1038                 /* Sp. cond. intr. only, ext int enable, RX DMA enable */
1039                 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |
1040                           WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB);
1041         } else {
1042                 /* Reset current frame */
1043                 priv->rx_ptr = 0;
1044                 /* Intr. on all Rx characters and Sp. cond., ext int enable */
1045                 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1046                           WT_FN_RDYFN);
1047         }
1048         write_scc(priv, R0, ERR_RES);
1049         write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1050 }
1051
1052
1053 static inline void rx_off(struct scc_priv *priv)
1054 {
1055         /* Disable receiver */
1056         write_scc(priv, R3, Rx8);
1057         /* Disable DREQ / RX interrupt */
1058         if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1059                 outb(0, priv->card_base + TWIN_DMA_CFG);
1060         else
1061                 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1062         /* Disable DMA */
1063         if (priv->param.dma >= 0)
1064                 disable_dma(priv->param.dma);
1065 }
1066
1067
1068 static void start_timer(struct scc_priv *priv, int t, int r15)
1069 {
1070         outb(priv->tmr_mode, priv->tmr_ctrl);
1071         if (t == 0) {
1072                 tm_isr(priv);
1073         } else if (t > 0) {
1074                 outb(t & 0xFF, priv->tmr_cnt);
1075                 outb((t >> 8) & 0xFF, priv->tmr_cnt);
1076                 if (priv->type != TYPE_TWIN) {
1077                         write_scc(priv, R15, r15 | CTSIE);
1078                         priv->rr0 |= CTS;
1079                 }
1080         }
1081 }
1082
1083
1084 static inline unsigned char random(void)
1085 {
1086         /* See "Numerical Recipes in C", second edition, p. 284 */
1087         rand = rand * 1664525L + 1013904223L;
1088         return (unsigned char) (rand >> 24);
1089 }
1090
1091 static inline void z8530_isr(struct scc_info *info)
1092 {
1093         int is, i = 100;
1094
1095         while ((is = read_scc(&info->priv[0], R3)) && i--) {
1096                 if (is & CHARxIP) {
1097                         rx_isr(&info->priv[0]);
1098                 } else if (is & CHATxIP) {
1099                         tx_isr(&info->priv[0]);
1100                 } else if (is & CHAEXT) {
1101                         es_isr(&info->priv[0]);
1102                 } else if (is & CHBRxIP) {
1103                         rx_isr(&info->priv[1]);
1104                 } else if (is & CHBTxIP) {
1105                         tx_isr(&info->priv[1]);
1106                 } else {
1107                         es_isr(&info->priv[1]);
1108                 }
1109                 write_scc(&info->priv[0], R0, RES_H_IUS);
1110                 i++;
1111         }
1112         if (i < 0) {
1113                 printk(KERN_ERR "dmascc: stuck in ISR with RR3=0x%02x.\n",
1114                        is);
1115         }
1116         /* Ok, no interrupts pending from this 8530. The INT line should
1117            be inactive now. */
1118 }
1119
1120
1121 static irqreturn_t scc_isr(int irq, void *dev_id)
1122 {
1123         struct scc_info *info = dev_id;
1124
1125         spin_lock(info->priv[0].register_lock);
1126         /* At this point interrupts are enabled, and the interrupt under service
1127            is already acknowledged, but masked off.
1128
1129            Interrupt processing: We loop until we know that the IRQ line is
1130            low. If another positive edge occurs afterwards during the ISR,
1131            another interrupt will be triggered by the interrupt controller
1132            as soon as the IRQ level is enabled again (see asm/irq.h).
1133
1134            Bottom-half handlers will be processed after scc_isr(). This is
1135            important, since we only have small ringbuffers and want new data
1136            to be fetched/delivered immediately. */
1137
1138         if (info->priv[0].type == TYPE_TWIN) {
1139                 int is, card_base = info->priv[0].card_base;
1140                 while ((is = ~inb(card_base + TWIN_INT_REG)) &
1141                        TWIN_INT_MSK) {
1142                         if (is & TWIN_SCC_MSK) {
1143                                 z8530_isr(info);
1144                         } else if (is & TWIN_TMR1_MSK) {
1145                                 inb(card_base + TWIN_CLR_TMR1);
1146                                 tm_isr(&info->priv[0]);
1147                         } else {
1148                                 inb(card_base + TWIN_CLR_TMR2);
1149                                 tm_isr(&info->priv[1]);
1150                         }
1151                 }
1152         } else
1153                 z8530_isr(info);
1154         spin_unlock(info->priv[0].register_lock);
1155         return IRQ_HANDLED;
1156 }
1157
1158
1159 static void rx_isr(struct scc_priv *priv)
1160 {
1161         if (priv->param.dma >= 0) {
1162                 /* Check special condition and perform error reset. See 2.4.7.5. */
1163                 special_condition(priv, read_scc(priv, R1));
1164                 write_scc(priv, R0, ERR_RES);
1165         } else {
1166                 /* Check special condition for each character. Error reset not necessary.
1167                    Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */
1168                 int rc;
1169                 while (read_scc(priv, R0) & Rx_CH_AV) {
1170                         rc = read_scc(priv, R1);
1171                         if (priv->rx_ptr < BUF_SIZE)
1172                                 priv->rx_buf[priv->rx_head][priv->
1173                                                             rx_ptr++] =
1174                                     read_scc_data(priv);
1175                         else {
1176                                 priv->rx_over = 2;
1177                                 read_scc_data(priv);
1178                         }
1179                         special_condition(priv, rc);
1180                 }
1181         }
1182 }
1183
1184
1185 static void special_condition(struct scc_priv *priv, int rc)
1186 {
1187         int cb;
1188         unsigned long flags;
1189
1190         /* See Figure 2-15. Only overrun and EOF need to be checked. */
1191
1192         if (rc & Rx_OVR) {
1193                 /* Receiver overrun */
1194                 priv->rx_over = 1;
1195                 if (priv->param.dma < 0)
1196                         write_scc(priv, R0, ERR_RES);
1197         } else if (rc & END_FR) {
1198                 /* End of frame. Get byte count */
1199                 if (priv->param.dma >= 0) {
1200                         flags = claim_dma_lock();
1201                         cb = BUF_SIZE - get_dma_residue(priv->param.dma) -
1202                             2;
1203                         release_dma_lock(flags);
1204                 } else {
1205                         cb = priv->rx_ptr - 2;
1206                 }
1207                 if (priv->rx_over) {
1208                         /* We had an overrun */
1209                         priv->dev->stats.rx_errors++;
1210                         if (priv->rx_over == 2)
1211                                 priv->dev->stats.rx_length_errors++;
1212                         else
1213                                 priv->dev->stats.rx_fifo_errors++;
1214                         priv->rx_over = 0;
1215                 } else if (rc & CRC_ERR) {
1216                         /* Count invalid CRC only if packet length >= minimum */
1217                         if (cb >= 15) {
1218                                 priv->dev->stats.rx_errors++;
1219                                 priv->dev->stats.rx_crc_errors++;
1220                         }
1221                 } else {
1222                         if (cb >= 15) {
1223                                 if (priv->rx_count < NUM_RX_BUF - 1) {
1224                                         /* Put good frame in FIFO */
1225                                         priv->rx_len[priv->rx_head] = cb;
1226                                         priv->rx_head =
1227                                             (priv->rx_head +
1228                                              1) % NUM_RX_BUF;
1229                                         priv->rx_count++;
1230                                         schedule_work(&priv->rx_work);
1231                                 } else {
1232                                         priv->dev->stats.rx_errors++;
1233                                         priv->dev->stats.rx_over_errors++;
1234                                 }
1235                         }
1236                 }
1237                 /* Get ready for new frame */
1238                 if (priv->param.dma >= 0) {
1239                         flags = claim_dma_lock();
1240                         set_dma_addr(priv->param.dma,
1241                                      (int) priv->rx_buf[priv->rx_head]);
1242                         set_dma_count(priv->param.dma, BUF_SIZE);
1243                         release_dma_lock(flags);
1244                 } else {
1245                         priv->rx_ptr = 0;
1246                 }
1247         }
1248 }
1249
1250
1251 static void rx_bh(struct work_struct *ugli_api)
1252 {
1253         struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work);
1254         int i = priv->rx_tail;
1255         int cb;
1256         unsigned long flags;
1257         struct sk_buff *skb;
1258         unsigned char *data;
1259
1260         spin_lock_irqsave(&priv->ring_lock, flags);
1261         while (priv->rx_count) {
1262                 spin_unlock_irqrestore(&priv->ring_lock, flags);
1263                 cb = priv->rx_len[i];
1264                 /* Allocate buffer */
1265                 skb = dev_alloc_skb(cb + 1);
1266                 if (skb == NULL) {
1267                         /* Drop packet */
1268                         priv->dev->stats.rx_dropped++;
1269                 } else {
1270                         /* Fill buffer */
1271                         data = skb_put(skb, cb + 1);
1272                         data[0] = 0;
1273                         memcpy(&data[1], priv->rx_buf[i], cb);
1274                         skb->protocol = ax25_type_trans(skb, priv->dev);
1275                         netif_rx(skb);
1276                         priv->dev->stats.rx_packets++;
1277                         priv->dev->stats.rx_bytes += cb;
1278                 }
1279                 spin_lock_irqsave(&priv->ring_lock, flags);
1280                 /* Move tail */
1281                 priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
1282                 priv->rx_count--;
1283         }
1284         spin_unlock_irqrestore(&priv->ring_lock, flags);
1285 }
1286
1287
1288 static void tx_isr(struct scc_priv *priv)
1289 {
1290         int i = priv->tx_tail, p = priv->tx_ptr;
1291
1292         /* Suspend TX interrupts if we don't want to send anything.
1293            See Figure 2-22. */
1294         if (p == priv->tx_len[i]) {
1295                 write_scc(priv, R0, RES_Tx_P);
1296                 return;
1297         }
1298
1299         /* Write characters */
1300         while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
1301                 write_scc_data(priv, priv->tx_buf[i][p++], 0);
1302         }
1303
1304         /* Reset EOM latch of Z8530 */
1305         if (!priv->tx_ptr && p && priv->chip == Z8530)
1306                 write_scc(priv, R0, RES_EOM_L);
1307
1308         priv->tx_ptr = p;
1309 }
1310
1311
1312 static void es_isr(struct scc_priv *priv)
1313 {
1314         int i, rr0, drr0, res;
1315         unsigned long flags;
1316
1317         /* Read status, reset interrupt bit (open latches) */
1318         rr0 = read_scc(priv, R0);
1319         write_scc(priv, R0, RES_EXT_INT);
1320         drr0 = priv->rr0 ^ rr0;
1321         priv->rr0 = rr0;
1322
1323         /* Transmit underrun (2.4.9.6). We can't check the TxEOM flag, since
1324            it might have already been cleared again by AUTOEOM. */
1325         if (priv->state == TX_DATA) {
1326                 /* Get remaining bytes */
1327                 i = priv->tx_tail;
1328                 if (priv->param.dma >= 0) {
1329                         disable_dma(priv->param.dma);
1330                         flags = claim_dma_lock();
1331                         res = get_dma_residue(priv->param.dma);
1332                         release_dma_lock(flags);
1333                 } else {
1334                         res = priv->tx_len[i] - priv->tx_ptr;
1335                         priv->tx_ptr = 0;
1336                 }
1337                 /* Disable DREQ / TX interrupt */
1338                 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1339                         outb(0, priv->card_base + TWIN_DMA_CFG);
1340                 else
1341                         write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1342                 if (res) {
1343                         /* Update packet statistics */
1344                         priv->dev->stats.tx_errors++;
1345                         priv->dev->stats.tx_fifo_errors++;
1346                         /* Other underrun interrupts may already be waiting */
1347                         write_scc(priv, R0, RES_EXT_INT);
1348                         write_scc(priv, R0, RES_EXT_INT);
1349                 } else {
1350                         /* Update packet statistics */
1351                         priv->dev->stats.tx_packets++;
1352                         priv->dev->stats.tx_bytes += priv->tx_len[i];
1353                         /* Remove frame from FIFO */
1354                         priv->tx_tail = (i + 1) % NUM_TX_BUF;
1355                         priv->tx_count--;
1356                         /* Inform upper layers */
1357                         netif_wake_queue(priv->dev);
1358                 }
1359                 /* Switch state */
1360                 write_scc(priv, R15, 0);
1361                 if (priv->tx_count &&
1362                     (jiffies - priv->tx_start) < priv->param.txtimeout) {
1363                         priv->state = TX_PAUSE;
1364                         start_timer(priv, priv->param.txpause, 0);
1365                 } else {
1366                         priv->state = TX_TAIL;
1367                         start_timer(priv, priv->param.txtail, 0);
1368                 }
1369         }
1370
1371         /* DCD transition */
1372         if (drr0 & DCD) {
1373                 if (rr0 & DCD) {
1374                         switch (priv->state) {
1375                         case IDLE:
1376                         case WAIT:
1377                                 priv->state = DCD_ON;
1378                                 write_scc(priv, R15, 0);
1379                                 start_timer(priv, priv->param.dcdon, 0);
1380                         }
1381                 } else {
1382                         switch (priv->state) {
1383                         case RX_ON:
1384                                 rx_off(priv);
1385                                 priv->state = DCD_OFF;
1386                                 write_scc(priv, R15, 0);
1387                                 start_timer(priv, priv->param.dcdoff, 0);
1388                         }
1389                 }
1390         }
1391
1392         /* CTS transition */
1393         if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN)
1394                 tm_isr(priv);
1395
1396 }
1397
1398
1399 static void tm_isr(struct scc_priv *priv)
1400 {
1401         switch (priv->state) {
1402         case TX_HEAD:
1403         case TX_PAUSE:
1404                 tx_on(priv);
1405                 priv->state = TX_DATA;
1406                 break;
1407         case TX_TAIL:
1408                 write_scc(priv, R5, TxCRC_ENAB | Tx8);
1409                 priv->state = RTS_OFF;
1410                 if (priv->type != TYPE_TWIN)
1411                         write_scc(priv, R15, 0);
1412                 start_timer(priv, priv->param.rtsoff, 0);
1413                 break;
1414         case RTS_OFF:
1415                 write_scc(priv, R15, DCDIE);
1416                 priv->rr0 = read_scc(priv, R0);
1417                 if (priv->rr0 & DCD) {
1418                         priv->dev->stats.collisions++;
1419                         rx_on(priv);
1420                         priv->state = RX_ON;
1421                 } else {
1422                         priv->state = WAIT;
1423                         start_timer(priv, priv->param.waittime, DCDIE);
1424                 }
1425                 break;
1426         case WAIT:
1427                 if (priv->tx_count) {
1428                         priv->state = TX_HEAD;
1429                         priv->tx_start = jiffies;
1430                         write_scc(priv, R5,
1431                                   TxCRC_ENAB | RTS | TxENAB | Tx8);
1432                         write_scc(priv, R15, 0);
1433                         start_timer(priv, priv->param.txdelay, 0);
1434                 } else {
1435                         priv->state = IDLE;
1436                         if (priv->type != TYPE_TWIN)
1437                                 write_scc(priv, R15, DCDIE);
1438                 }
1439                 break;
1440         case DCD_ON:
1441         case DCD_OFF:
1442                 write_scc(priv, R15, DCDIE);
1443                 priv->rr0 = read_scc(priv, R0);
1444                 if (priv->rr0 & DCD) {
1445                         rx_on(priv);
1446                         priv->state = RX_ON;
1447                 } else {
1448                         priv->state = WAIT;
1449                         start_timer(priv,
1450                                     random() / priv->param.persist *
1451                                     priv->param.slottime, DCDIE);
1452                 }
1453                 break;
1454         }
1455 }