drivers/net/phy/bcm7xxx.c

   1 /*
   2  * Broadcom BCM7xxx internal transceivers support.
   3  *
   4  * Copyright (C) 2014, Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/phy.h>
  14 #include <linux/delay.h>
  15 #include <linux/bitops.h>
  16 #include <linux/brcmphy.h>
  17 #include <linux/mdio.h>
  18
  19 /* Broadcom BCM7xxx internal PHY registers */
  20 #define MII_BCM7XXX_CHANNEL_WIDTH       0x2000
  21
  22 /* 40nm only register definitions */
  23 #define MII_BCM7XXX_100TX_AUX_CTL       0x10
  24 #define MII_BCM7XXX_100TX_FALSE_CAR     0x13
  25 #define MII_BCM7XXX_100TX_DISC          0x14
  26 #define MII_BCM7XXX_AUX_MODE            0x1d
  27 #define  MII_BCM7XX_64CLK_MDIO          BIT(12)
  28 #define MII_BCM7XXX_CORE_BASE1E         0x1e
  29 #define MII_BCM7XXX_TEST                0x1f
  30 #define  MII_BCM7XXX_SHD_MODE_2         BIT(2)
  31
  32 /* 28nm only register definitions */
  33 #define MISC_ADDR(base, channel)        base, channel
  34
  35 #define DSP_TAP10                       MISC_ADDR(0x0a, 0)
  36 #define PLL_PLLCTRL_1                   MISC_ADDR(0x32, 1)
  37 #define PLL_PLLCTRL_2                   MISC_ADDR(0x32, 2)
  38 #define PLL_PLLCTRL_4                   MISC_ADDR(0x33, 0)
  39
  40 #define AFE_RXCONFIG_0                  MISC_ADDR(0x38, 0)
  41 #define AFE_RXCONFIG_1                  MISC_ADDR(0x38, 1)
  42 #define AFE_RX_LP_COUNTER               MISC_ADDR(0x38, 3)
  43 #define AFE_TX_CONFIG                   MISC_ADDR(0x39, 0)
  44 #define AFE_HPF_TRIM_OTHERS             MISC_ADDR(0x3a, 0)
  45
  46 #define CORE_EXPB0                      0xb0
  47
  48 static void phy_write_exp(struct phy_device *phydev,
  49                                         u16 reg, u16 value)
  50 {
  51         phy_write(phydev, MII_BCM54XX_EXP_SEL, MII_BCM54XX_EXP_SEL_ER | reg);
  52         phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
  53 }
  54
  55 static void phy_write_misc(struct phy_device *phydev,
  56                                         u16 reg, u16 chl, u16 value)
  57 {
  58         int tmp;
  59
  60         phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
  61
  62         tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
  63         tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
  64         phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
  65
  66         tmp = (chl * MII_BCM7XXX_CHANNEL_WIDTH) | reg;
  67         phy_write(phydev, MII_BCM54XX_EXP_SEL, tmp);
  68
  69         phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
  70 }
  71
  72 static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
  73 {
  74         /* Increase VCO range to prevent unlocking problem of PLL at low
  75          * temp
  76          */
  77         phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
  78
  79         /* Change Ki to 011 */
  80         phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
  81
  82         /* Disable loading of TVCO buffer to bandgap, set bandgap trim
  83          * to 111
  84          */
  85         phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
  86
  87         /* Adjust bias current trim by -3 */
  88         phy_write_misc(phydev, DSP_TAP10, 0x690b);
  89
  90         /* Switch to CORE_BASE1E */
  91         phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);
  92
  93         /* Reset R_CAL/RC_CAL Engine */
  94         phy_write_exp(phydev, CORE_EXPB0, 0x0010);
  95
  96         /* Disable Reset R_CAL/RC_CAL Engine */
  97         phy_write_exp(phydev, CORE_EXPB0, 0x0000);
  98
  99         /* write AFE_RXCONFIG_0 */
 100         phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
 101
 102         /* write AFE_RXCONFIG_1 */
 103         phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
 104
 105         /* write AFE_RX_LP_COUNTER */
 106         phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
 107
 108         /* write AFE_HPF_TRIM_OTHERS */
 109         phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
 110
 111         /* write AFTE_TX_CONFIG */
 112         phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
 113
 114         return 0;
 115 }
 116
 117 static int bcm7xxx_apd_enable(struct phy_device *phydev)
 118 {
 119         int val;
 120
 121         /* Enable powering down of the DLL during auto-power down */
 122         val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
 123         if (val < 0)
 124                 return val;
 125
 126         val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
 127         bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
 128
 129         /* Enable auto-power down */
 130         val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
 131         if (val < 0)
 132                 return val;
 133
 134         val |= BCM54XX_SHD_APD_EN;
 135         return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
 136 }
 137
 138 static int bcm7xxx_eee_enable(struct phy_device *phydev)
 139 {
 140         int val;
 141
 142         val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
 143                                     MDIO_MMD_AN, phydev->addr);
 144         if (val < 0)
 145                 return val;
 146
 147         /* Enable general EEE feature at the PHY level */
 148         val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
 149
 150         phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
 151                                MDIO_MMD_AN, phydev->addr, val);
 152
 153         /* Advertise supported modes */
 154         val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
 155                                     MDIO_MMD_AN, phydev->addr);
 156
 157         val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
 158         phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
 159                                MDIO_MMD_AN, phydev->addr, val);
 160
 161         return 0;
 162 }
 163
 164 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
 165 {
 166         u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
 167         u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
 168         int ret = 0;
 169
 170         pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
 171                      dev_name(&phydev->dev), phydev->drv->name, rev, patch);
 172
 173         switch (rev) {
 174         case 0xb0:
 175                 ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
 176                 break;
 177         default:
 178                 break;
 179         }
 180
 181         if (ret)
 182                 return ret;
 183
 184         ret = bcm7xxx_eee_enable(phydev);
 185         if (ret)
 186                 return ret;
 187
 188         return bcm7xxx_apd_enable(phydev);
 189 }
 190
 191 static int bcm7xxx_28nm_resume(struct phy_device *phydev)
 192 {
 193         int ret;
 194
 195         /* Re-apply workarounds coming out suspend/resume */
 196         ret = bcm7xxx_28nm_config_init(phydev);
 197         if (ret)
 198                 return ret;
 199
 200         /* 28nm Gigabit PHYs come out of reset without any half-duplex
 201          * or "hub" compliant advertised mode, fix that. This does not
 202          * cause any problems with the PHY library since genphy_config_aneg()
 203          * gracefully handles auto-negotiated and forced modes.
 204          */
 205         return genphy_config_aneg(phydev);
 206 }
 207
 208 static int phy_set_clr_bits(struct phy_device *dev, int location,
 209                                         int set_mask, int clr_mask)
 210 {
 211         int v, ret;
 212
 213         v = phy_read(dev, location);
 214         if (v < 0)
 215                 return v;
 216
 217         v &= ~clr_mask;
 218         v |= set_mask;
 219
 220         ret = phy_write(dev, location, v);
 221         if (ret < 0)
 222                 return ret;
 223
 224         return v;
 225 }
 226
 227 static int bcm7xxx_config_init(struct phy_device *phydev)
 228 {
 229         int ret;
 230
 231         /* Enable 64 clock MDIO */
 232         phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
 233         phy_read(phydev, MII_BCM7XXX_AUX_MODE);
 234
 235         /* Workaround only required for 100Mbits/sec capable PHYs */
 236         if (phydev->supported & PHY_GBIT_FEATURES)
 237                 return 0;
 238
 239         /* set shadow mode 2 */
 240         ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
 241                         MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
 242         if (ret < 0)
 243                 return ret;
 244
 245         /* set iddq_clkbias */
 246         phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
 247         udelay(10);
 248
 249         /* reset iddq_clkbias */
 250         phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
 251
 252         phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
 253
 254         /* reset shadow mode 2 */
 255         ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
 256         if (ret < 0)
 257                 return ret;
 258
 259         return 0;
 260 }
 261
 262 /* Workaround for putting the PHY in IDDQ mode, required
 263  * for all BCM7XXX 40nm and 65nm PHYs
 264  */
 265 static int bcm7xxx_suspend(struct phy_device *phydev)
 266 {
 267         int ret;
 268         const struct bcm7xxx_regs {
 269                 int reg;
 270                 u16 value;
 271         } bcm7xxx_suspend_cfg[] = {
 272                 { MII_BCM7XXX_TEST, 0x008b },
 273                 { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
 274                 { MII_BCM7XXX_100TX_DISC, 0x7000 },
 275                 { MII_BCM7XXX_TEST, 0x000f },
 276                 { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
 277                 { MII_BCM7XXX_TEST, 0x000b },
 278         };
 279         unsigned int i;
 280
 281         for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
 282                 ret = phy_write(phydev,
 283                                 bcm7xxx_suspend_cfg[i].reg,
 284                                 bcm7xxx_suspend_cfg[i].value);
 285                 if (ret)
 286                         return ret;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
 293 {
 294         return 0;
 295 }
 296
 297 #define BCM7XXX_28NM_GPHY(_oui, _name)                                  \
 298 {                                                                       \
 299         .phy_id         = (_oui),                                       \
 300         .phy_id_mask    = 0xfffffff0,                                   \
 301         .name           = _name,                                        \
 302         .features       = PHY_GBIT_FEATURES |                           \
 303                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,       \
 304         .flags          = PHY_IS_INTERNAL,                              \
 305         .config_init    = bcm7xxx_28nm_config_init,                     \
 306         .config_aneg    = genphy_config_aneg,                           \
 307         .read_status    = genphy_read_status,                           \
 308         .resume         = bcm7xxx_28nm_resume,                          \
 309         .driver         = { .owner = THIS_MODULE },                     \
 310 }
 311
 312 static struct phy_driver bcm7xxx_driver[] = {
 313         BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
 314         BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
 315         BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
 316         BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
 317         BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
 318 {
 319         .phy_id         = PHY_ID_BCM7425,
 320         .phy_id_mask    = 0xfffffff0,
 321         .name           = "Broadcom BCM7425",
 322         .features       = PHY_GBIT_FEATURES |
 323                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 324         .flags          = 0,
 325         .config_init    = bcm7xxx_config_init,
 326         .config_aneg    = genphy_config_aneg,
 327         .read_status    = genphy_read_status,
 328         .suspend        = bcm7xxx_suspend,
 329         .resume         = bcm7xxx_config_init,
 330         .driver         = { .owner = THIS_MODULE },
 331 }, {
 332         .phy_id         = PHY_ID_BCM7429,
 333         .phy_id_mask    = 0xfffffff0,
 334         .name           = "Broadcom BCM7429",
 335         .features       = PHY_GBIT_FEATURES |
 336                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 337         .flags          = PHY_IS_INTERNAL,
 338         .config_init    = bcm7xxx_config_init,
 339         .config_aneg    = genphy_config_aneg,
 340         .read_status    = genphy_read_status,
 341         .suspend        = bcm7xxx_suspend,
 342         .resume         = bcm7xxx_config_init,
 343         .driver         = { .owner = THIS_MODULE },
 344 }, {
 345         .phy_id         = PHY_BCM_OUI_4,
 346         .phy_id_mask    = 0xffff0000,
 347         .name           = "Broadcom BCM7XXX 40nm",
 348         .features       = PHY_GBIT_FEATURES |
 349                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 350         .flags          = PHY_IS_INTERNAL,
 351         .config_init    = bcm7xxx_config_init,
 352         .config_aneg    = genphy_config_aneg,
 353         .read_status    = genphy_read_status,
 354         .suspend        = bcm7xxx_suspend,
 355         .resume         = bcm7xxx_config_init,
 356         .driver         = { .owner = THIS_MODULE },
 357 }, {
 358         .phy_id         = PHY_BCM_OUI_5,
 359         .phy_id_mask    = 0xffffff00,
 360         .name           = "Broadcom BCM7XXX 65nm",
 361         .features       = PHY_BASIC_FEATURES |
 362                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 363         .flags          = PHY_IS_INTERNAL,
 364         .config_init    = bcm7xxx_dummy_config_init,
 365         .config_aneg    = genphy_config_aneg,
 366         .read_status    = genphy_read_status,
 367         .suspend        = bcm7xxx_suspend,
 368         .resume         = bcm7xxx_config_init,
 369         .driver         = { .owner = THIS_MODULE },
 370 } };
 371
 372 static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
 373         { PHY_ID_BCM7250, 0xfffffff0, },
 374         { PHY_ID_BCM7364, 0xfffffff0, },
 375         { PHY_ID_BCM7366, 0xfffffff0, },
 376         { PHY_ID_BCM7425, 0xfffffff0, },
 377         { PHY_ID_BCM7429, 0xfffffff0, },
 378         { PHY_ID_BCM7439, 0xfffffff0, },
 379         { PHY_ID_BCM7445, 0xfffffff0, },
 380         { PHY_BCM_OUI_4, 0xffff0000 },
 381         { PHY_BCM_OUI_5, 0xffffff00 },
 382         { }
 383 };
 384
 385 module_phy_driver(bcm7xxx_driver);
 386
 387 MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
 388
 389 MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
 390 MODULE_LICENSE("GPL");
 391 MODULE_AUTHOR("Broadcom Corporation");