drivers/net/phy/vitesse.c

   1 /*
   2  * Driver for Vitesse PHYs
   3  *
   4  * Author: Kriston Carson
   5  *
   6  * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/mii.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20
  21 /* Vitesse Extended Control Register 1 */
  22 #define MII_VSC8244_EXT_CON1           0x17
  23 #define MII_VSC8244_EXTCON1_INIT       0x0000
  24 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK        0x0c00
  25 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK        0x0300
  26 #define MII_VSC8244_EXTCON1_TX_SKEW     0x0800
  27 #define MII_VSC8244_EXTCON1_RX_SKEW     0x0200
  28
  29 /* Vitesse Interrupt Mask Register */
  30 #define MII_VSC8244_IMASK               0x19
  31 #define MII_VSC8244_IMASK_IEN           0x8000
  32 #define MII_VSC8244_IMASK_SPEED         0x4000
  33 #define MII_VSC8244_IMASK_LINK          0x2000
  34 #define MII_VSC8244_IMASK_DUPLEX        0x1000
  35 #define MII_VSC8244_IMASK_MASK          0xf000
  36
  37 #define MII_VSC8221_IMASK_MASK          0xa000
  38
  39 /* Vitesse Interrupt Status Register */
  40 #define MII_VSC8244_ISTAT               0x1a
  41 #define MII_VSC8244_ISTAT_STATUS        0x8000
  42 #define MII_VSC8244_ISTAT_SPEED         0x4000
  43 #define MII_VSC8244_ISTAT_LINK          0x2000
  44 #define MII_VSC8244_ISTAT_DUPLEX        0x1000
  45
  46 /* Vitesse Auxiliary Control/Status Register */
  47 #define MII_VSC8244_AUX_CONSTAT         0x1c
  48 #define MII_VSC8244_AUXCONSTAT_INIT     0x0000
  49 #define MII_VSC8244_AUXCONSTAT_DUPLEX   0x0020
  50 #define MII_VSC8244_AUXCONSTAT_SPEED    0x0018
  51 #define MII_VSC8244_AUXCONSTAT_GBIT     0x0010
  52 #define MII_VSC8244_AUXCONSTAT_100      0x0008
  53
  54 #define MII_VSC8221_AUXCONSTAT_INIT     0x0004 /* need to set this bit? */
  55 #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
  56
  57 #define PHY_ID_VSC8234                  0x000fc620
  58 #define PHY_ID_VSC8244                  0x000fc6c0
  59 #define PHY_ID_VSC8574                  0x000704a0
  60 #define PHY_ID_VSC8221                  0x000fc550
  61 #define PHY_ID_VSC8211                  0x000fc4b0
  62
  63 MODULE_DESCRIPTION("Vitesse PHY driver");
  64 MODULE_AUTHOR("Kriston Carson");
  65 MODULE_LICENSE("GPL");
  66
  67 static int vsc824x_add_skew(struct phy_device *phydev)
  68 {
  69         int err;
  70         int extcon;
  71
  72         extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
  73
  74         if (extcon < 0)
  75                 return extcon;
  76
  77         extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
  78                         MII_VSC8244_EXTCON1_RX_SKEW_MASK);
  79
  80         extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
  81                         MII_VSC8244_EXTCON1_RX_SKEW);
  82
  83         err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
  84
  85         return err;
  86 }
  87
  88 static int vsc824x_config_init(struct phy_device *phydev)
  89 {
  90         int err;
  91
  92         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
  93                         MII_VSC8244_AUXCONSTAT_INIT);
  94         if (err < 0)
  95                 return err;
  96
  97         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  98                 err = vsc824x_add_skew(phydev);
  99
 100         return err;
 101 }
 102
 103 static int vsc824x_ack_interrupt(struct phy_device *phydev)
 104 {
 105         int err = 0;
 106
 107         /* Don't bother to ACK the interrupts if interrupts
 108          * are disabled.  The 824x cannot clear the interrupts
 109          * if they are disabled.
 110          */
 111         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 112                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 113
 114         return (err < 0) ? err : 0;
 115 }
 116
 117 static int vsc82xx_config_intr(struct phy_device *phydev)
 118 {
 119         int err;
 120
 121         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 122                 err = phy_write(phydev, MII_VSC8244_IMASK,
 123                         (phydev->drv->phy_id == PHY_ID_VSC8234 ||
 124                          phydev->drv->phy_id == PHY_ID_VSC8244 ||
 125                          phydev->drv->phy_id == PHY_ID_VSC8574) ?
 126                                 MII_VSC8244_IMASK_MASK :
 127                                 MII_VSC8221_IMASK_MASK);
 128         else {
 129                 /* The Vitesse PHY cannot clear the interrupt
 130                  * once it has disabled them, so we clear them first
 131                  */
 132                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 133
 134                 if (err < 0)
 135                         return err;
 136
 137                 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
 138         }
 139
 140         return err;
 141 }
 142
 143 static int vsc8221_config_init(struct phy_device *phydev)
 144 {
 145         int err;
 146
 147         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
 148                         MII_VSC8221_AUXCONSTAT_INIT);
 149         return err;
 150
 151         /* Perhaps we should set EXT_CON1 based on the interface?
 152          * Options are 802.3Z SerDes or SGMII
 153          */
 154 }
 155
 156 /* Vitesse 82xx */
 157 static struct phy_driver vsc82xx_driver[] = {
 158 {
 159         .phy_id         = PHY_ID_VSC8234,
 160         .name           = "Vitesse VSC8234",
 161         .phy_id_mask    = 0x000ffff0,
 162         .features       = PHY_GBIT_FEATURES,
 163         .flags          = PHY_HAS_INTERRUPT,
 164         .config_init    = &vsc824x_config_init,
 165         .config_aneg    = &genphy_config_aneg,
 166         .read_status    = &genphy_read_status,
 167         .ack_interrupt  = &vsc824x_ack_interrupt,
 168         .config_intr    = &vsc82xx_config_intr,
 169         .driver         = { .owner = THIS_MODULE,},
 170 }, {
 171         .phy_id         = PHY_ID_VSC8244,
 172         .name           = "Vitesse VSC8244",
 173         .phy_id_mask    = 0x000fffc0,
 174         .features       = PHY_GBIT_FEATURES,
 175         .flags          = PHY_HAS_INTERRUPT,
 176         .config_init    = &vsc824x_config_init,
 177         .config_aneg    = &genphy_config_aneg,
 178         .read_status    = &genphy_read_status,
 179         .ack_interrupt  = &vsc824x_ack_interrupt,
 180         .config_intr    = &vsc82xx_config_intr,
 181         .driver         = { .owner = THIS_MODULE,},
 182 }, {
 183         .phy_id         = PHY_ID_VSC8574,
 184         .name           = "Vitesse VSC8574",
 185         .phy_id_mask    = 0x000ffff0,
 186         .features       = PHY_GBIT_FEATURES,
 187         .flags          = PHY_HAS_INTERRUPT,
 188         .config_init    = &vsc824x_config_init,
 189         .config_aneg    = &genphy_config_aneg,
 190         .read_status    = &genphy_read_status,
 191         .ack_interrupt  = &vsc824x_ack_interrupt,
 192         .config_intr    = &vsc82xx_config_intr,
 193         .driver         = { .owner = THIS_MODULE,},
 194 }, {
 195         /* Vitesse 8221 */
 196         .phy_id         = PHY_ID_VSC8221,
 197         .phy_id_mask    = 0x000ffff0,
 198         .name           = "Vitesse VSC8221",
 199         .features       = PHY_GBIT_FEATURES,
 200         .flags          = PHY_HAS_INTERRUPT,
 201         .config_init    = &vsc8221_config_init,
 202         .config_aneg    = &genphy_config_aneg,
 203         .read_status    = &genphy_read_status,
 204         .ack_interrupt  = &vsc824x_ack_interrupt,
 205         .config_intr    = &vsc82xx_config_intr,
 206         .driver         = { .owner = THIS_MODULE,},
 207 }, {
 208         /* Vitesse 8211 */
 209         .phy_id         = PHY_ID_VSC8211,
 210         .phy_id_mask    = 0x000ffff0,
 211         .name           = "Vitesse VSC8211",
 212         .features       = PHY_GBIT_FEATURES,
 213         .flags          = PHY_HAS_INTERRUPT,
 214         .config_init    = &vsc8221_config_init,
 215         .config_aneg    = &genphy_config_aneg,
 216         .read_status    = &genphy_read_status,
 217         .ack_interrupt  = &vsc824x_ack_interrupt,
 218         .config_intr    = &vsc82xx_config_intr,
 219         .driver         = { .owner = THIS_MODULE,},
 220 } };
 221
 222 static int __init vsc82xx_init(void)
 223 {
 224         return phy_drivers_register(vsc82xx_driver,
 225                 ARRAY_SIZE(vsc82xx_driver));
 226 }
 227
 228 static void __exit vsc82xx_exit(void)
 229 {
 230         return phy_drivers_unregister(vsc82xx_driver,
 231                 ARRAY_SIZE(vsc82xx_driver));
 232 }
 233
 234 module_init(vsc82xx_init);
 235 module_exit(vsc82xx_exit);
 236
 237 static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
 238         { PHY_ID_VSC8234, 0x000ffff0 },
 239         { PHY_ID_VSC8244, 0x000fffc0 },
 240         { PHY_ID_VSC8574, 0x000ffff0 },
 241         { PHY_ID_VSC8221, 0x000ffff0 },
 242         { PHY_ID_VSC8211, 0x000ffff0 },
 243         { }
 244 };
 245
 246 MODULE_DEVICE_TABLE(mdio, vitesse_tbl);