2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
47 #include <net/checksum.h>
50 #include <asm/system.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
56 #include <asm/idprom.h>
65 #define DRV_MODULE_NAME "tg3"
67 #define TG3_MIN_NUM 117
68 #define DRV_MODULE_VERSION \
69 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE "January 25, 2011"
72 #define TG3_DEF_MAC_MODE 0
73 #define TG3_DEF_RX_MODE 0
74 #define TG3_DEF_TX_MODE 0
75 #define TG3_DEF_MSG_ENABLE \
85 /* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
88 #define TG3_TX_TIMEOUT (5 * HZ)
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU 60
92 #define TG3_MAX_MTU(tp) \
93 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
99 #define TG3_RX_STD_RING_SIZE(tp) \
100 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
101 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JMB_RING_SIZE(tp) \
104 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
105 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
106 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
107 #define TG3_RSS_INDIR_TBL_SIZE 128
109 /* Do not place this n-ring entries value into the tp struct itself,
110 * we really want to expose these constants to GCC so that modulo et
111 * al. operations are done with shifts and masks instead of with
112 * hw multiply/modulo instructions. Another solution would be to
113 * replace things like '% foo' with '& (foo - 1)'.
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119 #define TG3_RX_STD_RING_BYTES(tp) \
120 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
121 #define TG3_RX_JMB_RING_BYTES(tp) \
122 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
123 #define TG3_RX_RCB_RING_BYTES(tp) \
124 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129 #define TG3_DMA_BYTE_ENAB 64
131 #define TG3_RX_STD_DMA_SZ 1536
132 #define TG3_RX_JMB_DMA_SZ 9046
134 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
140 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
143 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
146 * that are at least dword aligned when used in PCIX mode. The driver
147 * works around this bug by double copying the packet. This workaround
148 * is built into the normal double copy length check for efficiency.
150 * However, the double copy is only necessary on those architectures
151 * where unaligned memory accesses are inefficient. For those architectures
152 * where unaligned memory accesses incur little penalty, we can reintegrate
153 * the 5701 in the normal rx path. Doing so saves a device structure
154 * dereference by hardcoding the double copy threshold in place.
156 #define TG3_RX_COPY_THRESHOLD 256
157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
158 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
160 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
163 /* minimum number of free TX descriptors required to wake up TX process */
164 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
166 #define TG3_RAW_IP_ALIGN 2
168 /* number of ETHTOOL_GSTATS u64's */
169 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
171 #define TG3_NUM_TEST 6
173 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
175 #define FIRMWARE_TG3 "tigon/tg3.bin"
176 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
177 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
179 static char version[] __devinitdata =
180 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
182 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
183 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
184 MODULE_LICENSE("GPL");
185 MODULE_VERSION(DRV_MODULE_VERSION);
186 MODULE_FIRMWARE(FIRMWARE_TG3);
187 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
188 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
190 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
191 module_param(tg3_debug, int, 0);
192 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
194 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
267 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
268 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
269 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
270 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
271 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
272 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
273 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
277 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
279 static const struct {
280 const char string[ETH_GSTRING_LEN];
281 } ethtool_stats_keys[TG3_NUM_STATS] = {
284 { "rx_ucast_packets" },
285 { "rx_mcast_packets" },
286 { "rx_bcast_packets" },
288 { "rx_align_errors" },
289 { "rx_xon_pause_rcvd" },
290 { "rx_xoff_pause_rcvd" },
291 { "rx_mac_ctrl_rcvd" },
292 { "rx_xoff_entered" },
293 { "rx_frame_too_long_errors" },
295 { "rx_undersize_packets" },
296 { "rx_in_length_errors" },
297 { "rx_out_length_errors" },
298 { "rx_64_or_less_octet_packets" },
299 { "rx_65_to_127_octet_packets" },
300 { "rx_128_to_255_octet_packets" },
301 { "rx_256_to_511_octet_packets" },
302 { "rx_512_to_1023_octet_packets" },
303 { "rx_1024_to_1522_octet_packets" },
304 { "rx_1523_to_2047_octet_packets" },
305 { "rx_2048_to_4095_octet_packets" },
306 { "rx_4096_to_8191_octet_packets" },
307 { "rx_8192_to_9022_octet_packets" },
314 { "tx_flow_control" },
316 { "tx_single_collisions" },
317 { "tx_mult_collisions" },
319 { "tx_excessive_collisions" },
320 { "tx_late_collisions" },
321 { "tx_collide_2times" },
322 { "tx_collide_3times" },
323 { "tx_collide_4times" },
324 { "tx_collide_5times" },
325 { "tx_collide_6times" },
326 { "tx_collide_7times" },
327 { "tx_collide_8times" },
328 { "tx_collide_9times" },
329 { "tx_collide_10times" },
330 { "tx_collide_11times" },
331 { "tx_collide_12times" },
332 { "tx_collide_13times" },
333 { "tx_collide_14times" },
334 { "tx_collide_15times" },
335 { "tx_ucast_packets" },
336 { "tx_mcast_packets" },
337 { "tx_bcast_packets" },
338 { "tx_carrier_sense_errors" },
342 { "dma_writeq_full" },
343 { "dma_write_prioq_full" },
347 { "rx_threshold_hit" },
349 { "dma_readq_full" },
350 { "dma_read_prioq_full" },
351 { "tx_comp_queue_full" },
353 { "ring_set_send_prod_index" },
354 { "ring_status_update" },
356 { "nic_avoided_irqs" },
357 { "nic_tx_threshold_hit" }
360 static const struct {
361 const char string[ETH_GSTRING_LEN];
362 } ethtool_test_keys[TG3_NUM_TEST] = {
363 { "nvram test (online) " },
364 { "link test (online) " },
365 { "register test (offline)" },
366 { "memory test (offline)" },
367 { "loopback test (offline)" },
368 { "interrupt test (offline)" },
371 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
373 writel(val, tp->regs + off);
376 static u32 tg3_read32(struct tg3 *tp, u32 off)
378 return readl(tp->regs + off);
381 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
383 writel(val, tp->aperegs + off);
386 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
388 return readl(tp->aperegs + off);
391 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
395 spin_lock_irqsave(&tp->indirect_lock, flags);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
397 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
398 spin_unlock_irqrestore(&tp->indirect_lock, flags);
401 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
403 writel(val, tp->regs + off);
404 readl(tp->regs + off);
407 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
412 spin_lock_irqsave(&tp->indirect_lock, flags);
413 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
414 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
415 spin_unlock_irqrestore(&tp->indirect_lock, flags);
419 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
423 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
424 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
425 TG3_64BIT_REG_LOW, val);
428 if (off == TG3_RX_STD_PROD_IDX_REG) {
429 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
430 TG3_64BIT_REG_LOW, val);
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
439 /* In indirect mode when disabling interrupts, we also need
440 * to clear the interrupt bit in the GRC local ctrl register.
442 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
444 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
445 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
449 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
454 spin_lock_irqsave(&tp->indirect_lock, flags);
455 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
456 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
457 spin_unlock_irqrestore(&tp->indirect_lock, flags);
461 /* usec_wait specifies the wait time in usec when writing to certain registers
462 * where it is unsafe to read back the register without some delay.
463 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
464 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
466 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
468 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
469 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
470 /* Non-posted methods */
471 tp->write32(tp, off, val);
474 tg3_write32(tp, off, val);
479 /* Wait again after the read for the posted method to guarantee that
480 * the wait time is met.
486 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
488 tp->write32_mbox(tp, off, val);
489 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
490 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
491 tp->read32_mbox(tp, off);
494 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
496 void __iomem *mbox = tp->regs + off;
498 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
500 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
504 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
506 return readl(tp->regs + off + GRCMBOX_BASE);
509 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
511 writel(val, tp->regs + off + GRCMBOX_BASE);
514 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
515 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
516 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
517 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
518 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
520 #define tw32(reg, val) tp->write32(tp, reg, val)
521 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
522 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
523 #define tr32(reg) tp->read32(tp, reg)
525 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
529 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
530 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
533 spin_lock_irqsave(&tp->indirect_lock, flags);
534 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
535 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
536 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
538 /* Always leave this as zero. */
539 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
541 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
542 tw32_f(TG3PCI_MEM_WIN_DATA, val);
544 /* Always leave this as zero. */
545 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
547 spin_unlock_irqrestore(&tp->indirect_lock, flags);
550 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
554 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
555 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
560 spin_lock_irqsave(&tp->indirect_lock, flags);
561 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
562 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
563 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
565 /* Always leave this as zero. */
566 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
568 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
569 *val = tr32(TG3PCI_MEM_WIN_DATA);
571 /* Always leave this as zero. */
572 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
574 spin_unlock_irqrestore(&tp->indirect_lock, flags);
577 static void tg3_ape_lock_init(struct tg3 *tp)
582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
583 regbase = TG3_APE_LOCK_GRANT;
585 regbase = TG3_APE_PER_LOCK_GRANT;
587 /* Make sure the driver hasn't any stale locks. */
588 for (i = 0; i < 8; i++)
589 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
592 static int tg3_ape_lock(struct tg3 *tp, int locknum)
596 u32 status, req, gnt;
598 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
602 case TG3_APE_LOCK_GRC:
603 case TG3_APE_LOCK_MEM:
609 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
610 req = TG3_APE_LOCK_REQ;
611 gnt = TG3_APE_LOCK_GRANT;
613 req = TG3_APE_PER_LOCK_REQ;
614 gnt = TG3_APE_PER_LOCK_GRANT;
619 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
621 /* Wait for up to 1 millisecond to acquire lock. */
622 for (i = 0; i < 100; i++) {
623 status = tg3_ape_read32(tp, gnt + off);
624 if (status == APE_LOCK_GRANT_DRIVER)
629 if (status != APE_LOCK_GRANT_DRIVER) {
630 /* Revoke the lock request. */
631 tg3_ape_write32(tp, gnt + off,
632 APE_LOCK_GRANT_DRIVER);
640 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
644 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
648 case TG3_APE_LOCK_GRC:
649 case TG3_APE_LOCK_MEM:
655 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
656 gnt = TG3_APE_LOCK_GRANT;
658 gnt = TG3_APE_PER_LOCK_GRANT;
660 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
663 static void tg3_disable_ints(struct tg3 *tp)
667 tw32(TG3PCI_MISC_HOST_CTRL,
668 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
669 for (i = 0; i < tp->irq_max; i++)
670 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
673 static void tg3_enable_ints(struct tg3 *tp)
680 tw32(TG3PCI_MISC_HOST_CTRL,
681 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
683 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
684 for (i = 0; i < tp->irq_cnt; i++) {
685 struct tg3_napi *tnapi = &tp->napi[i];
687 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
688 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
689 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
691 tp->coal_now |= tnapi->coal_now;
694 /* Force an initial interrupt */
695 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
696 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
697 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
699 tw32(HOSTCC_MODE, tp->coal_now);
701 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
704 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
706 struct tg3 *tp = tnapi->tp;
707 struct tg3_hw_status *sblk = tnapi->hw_status;
708 unsigned int work_exists = 0;
710 /* check for phy events */
711 if (!(tp->tg3_flags &
712 (TG3_FLAG_USE_LINKCHG_REG |
713 TG3_FLAG_POLL_SERDES))) {
714 if (sblk->status & SD_STATUS_LINK_CHG)
717 /* check for RX/TX work to do */
718 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
719 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
726 * similar to tg3_enable_ints, but it accurately determines whether there
727 * is new work pending and can return without flushing the PIO write
728 * which reenables interrupts
730 static void tg3_int_reenable(struct tg3_napi *tnapi)
732 struct tg3 *tp = tnapi->tp;
734 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
737 /* When doing tagged status, this work check is unnecessary.
738 * The last_tag we write above tells the chip which piece of
739 * work we've completed.
741 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
743 tw32(HOSTCC_MODE, tp->coalesce_mode |
744 HOSTCC_MODE_ENABLE | tnapi->coal_now);
747 static void tg3_switch_clocks(struct tg3 *tp)
752 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
753 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
756 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
758 orig_clock_ctrl = clock_ctrl;
759 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
760 CLOCK_CTRL_CLKRUN_OENABLE |
762 tp->pci_clock_ctrl = clock_ctrl;
764 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
765 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
766 tw32_wait_f(TG3PCI_CLOCK_CTRL,
767 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
769 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
770 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
774 tw32_wait_f(TG3PCI_CLOCK_CTRL,
775 clock_ctrl | (CLOCK_CTRL_ALTCLK),
778 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
781 #define PHY_BUSY_LOOPS 5000
783 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
789 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
791 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
797 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
803 tw32_f(MAC_MI_COM, frame_val);
805 loops = PHY_BUSY_LOOPS;
808 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
812 frame_val = tr32(MAC_MI_COM);
820 *val = frame_val & MI_COM_DATA_MASK;
824 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
825 tw32_f(MAC_MI_MODE, tp->mi_mode);
832 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
838 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
839 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
842 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
844 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
848 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
849 MI_COM_PHY_ADDR_MASK);
850 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
851 MI_COM_REG_ADDR_MASK);
852 frame_val |= (val & MI_COM_DATA_MASK);
853 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
855 tw32_f(MAC_MI_COM, frame_val);
857 loops = PHY_BUSY_LOOPS;
860 frame_val = tr32(MAC_MI_COM);
861 if ((frame_val & MI_COM_BUSY) == 0) {
863 frame_val = tr32(MAC_MI_COM);
873 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
874 tw32_f(MAC_MI_MODE, tp->mi_mode);
881 static int tg3_bmcr_reset(struct tg3 *tp)
886 /* OK, reset it, and poll the BMCR_RESET bit until it
887 * clears or we time out.
889 phy_control = BMCR_RESET;
890 err = tg3_writephy(tp, MII_BMCR, phy_control);
896 err = tg3_readphy(tp, MII_BMCR, &phy_control);
900 if ((phy_control & BMCR_RESET) == 0) {
912 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
914 struct tg3 *tp = bp->priv;
917 spin_lock_bh(&tp->lock);
919 if (tg3_readphy(tp, reg, &val))
922 spin_unlock_bh(&tp->lock);
927 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
929 struct tg3 *tp = bp->priv;
932 spin_lock_bh(&tp->lock);
934 if (tg3_writephy(tp, reg, val))
937 spin_unlock_bh(&tp->lock);
942 static int tg3_mdio_reset(struct mii_bus *bp)
947 static void tg3_mdio_config_5785(struct tg3 *tp)
950 struct phy_device *phydev;
952 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
953 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
954 case PHY_ID_BCM50610:
955 case PHY_ID_BCM50610M:
956 val = MAC_PHYCFG2_50610_LED_MODES;
958 case PHY_ID_BCMAC131:
959 val = MAC_PHYCFG2_AC131_LED_MODES;
961 case PHY_ID_RTL8211C:
962 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
964 case PHY_ID_RTL8201E:
965 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
971 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
972 tw32(MAC_PHYCFG2, val);
974 val = tr32(MAC_PHYCFG1);
975 val &= ~(MAC_PHYCFG1_RGMII_INT |
976 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
977 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
978 tw32(MAC_PHYCFG1, val);
983 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
984 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
985 MAC_PHYCFG2_FMODE_MASK_MASK |
986 MAC_PHYCFG2_GMODE_MASK_MASK |
987 MAC_PHYCFG2_ACT_MASK_MASK |
988 MAC_PHYCFG2_QUAL_MASK_MASK |
989 MAC_PHYCFG2_INBAND_ENABLE;
991 tw32(MAC_PHYCFG2, val);
993 val = tr32(MAC_PHYCFG1);
994 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
995 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
996 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
997 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
998 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
999 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1000 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1002 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1003 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1004 tw32(MAC_PHYCFG1, val);
1006 val = tr32(MAC_EXT_RGMII_MODE);
1007 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1008 MAC_RGMII_MODE_RX_QUALITY |
1009 MAC_RGMII_MODE_RX_ACTIVITY |
1010 MAC_RGMII_MODE_RX_ENG_DET |
1011 MAC_RGMII_MODE_TX_ENABLE |
1012 MAC_RGMII_MODE_TX_LOWPWR |
1013 MAC_RGMII_MODE_TX_RESET);
1014 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1015 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1016 val |= MAC_RGMII_MODE_RX_INT_B |
1017 MAC_RGMII_MODE_RX_QUALITY |
1018 MAC_RGMII_MODE_RX_ACTIVITY |
1019 MAC_RGMII_MODE_RX_ENG_DET;
1020 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1021 val |= MAC_RGMII_MODE_TX_ENABLE |
1022 MAC_RGMII_MODE_TX_LOWPWR |
1023 MAC_RGMII_MODE_TX_RESET;
1025 tw32(MAC_EXT_RGMII_MODE, val);
1028 static void tg3_mdio_start(struct tg3 *tp)
1030 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1031 tw32_f(MAC_MI_MODE, tp->mi_mode);
1034 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1036 tg3_mdio_config_5785(tp);
1039 static int tg3_mdio_init(struct tg3 *tp)
1043 struct phy_device *phydev;
1045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1049 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1051 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1052 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1054 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1055 TG3_CPMU_PHY_STRAP_IS_SERDES;
1059 tp->phy_addr = TG3_PHY_MII_ADDR;
1063 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1064 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1067 tp->mdio_bus = mdiobus_alloc();
1068 if (tp->mdio_bus == NULL)
1071 tp->mdio_bus->name = "tg3 mdio bus";
1072 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1073 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1074 tp->mdio_bus->priv = tp;
1075 tp->mdio_bus->parent = &tp->pdev->dev;
1076 tp->mdio_bus->read = &tg3_mdio_read;
1077 tp->mdio_bus->write = &tg3_mdio_write;
1078 tp->mdio_bus->reset = &tg3_mdio_reset;
1079 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1080 tp->mdio_bus->irq = &tp->mdio_irq[0];
1082 for (i = 0; i < PHY_MAX_ADDR; i++)
1083 tp->mdio_bus->irq[i] = PHY_POLL;
1085 /* The bus registration will look for all the PHYs on the mdio bus.
1086 * Unfortunately, it does not ensure the PHY is powered up before
1087 * accessing the PHY ID registers. A chip reset is the
1088 * quickest way to bring the device back to an operational state..
1090 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1093 i = mdiobus_register(tp->mdio_bus);
1095 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1096 mdiobus_free(tp->mdio_bus);
1100 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1102 if (!phydev || !phydev->drv) {
1103 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1104 mdiobus_unregister(tp->mdio_bus);
1105 mdiobus_free(tp->mdio_bus);
1109 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1110 case PHY_ID_BCM57780:
1111 phydev->interface = PHY_INTERFACE_MODE_GMII;
1112 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1114 case PHY_ID_BCM50610:
1115 case PHY_ID_BCM50610M:
1116 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1117 PHY_BRCM_RX_REFCLK_UNUSED |
1118 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1119 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1121 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1122 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1123 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1124 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1125 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1127 case PHY_ID_RTL8211C:
1128 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1130 case PHY_ID_RTL8201E:
1131 case PHY_ID_BCMAC131:
1132 phydev->interface = PHY_INTERFACE_MODE_MII;
1133 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1134 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1138 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1140 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1141 tg3_mdio_config_5785(tp);
1146 static void tg3_mdio_fini(struct tg3 *tp)
1148 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1149 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1150 mdiobus_unregister(tp->mdio_bus);
1151 mdiobus_free(tp->mdio_bus);
1155 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1159 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1163 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1167 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1168 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1172 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1178 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1182 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1186 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1190 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1191 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1195 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1201 /* tp->lock is held. */
1202 static inline void tg3_generate_fw_event(struct tg3 *tp)
1206 val = tr32(GRC_RX_CPU_EVENT);
1207 val |= GRC_RX_CPU_DRIVER_EVENT;
1208 tw32_f(GRC_RX_CPU_EVENT, val);
1210 tp->last_event_jiffies = jiffies;
1213 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1215 /* tp->lock is held. */
1216 static void tg3_wait_for_event_ack(struct tg3 *tp)
1219 unsigned int delay_cnt;
1222 /* If enough time has passed, no wait is necessary. */
1223 time_remain = (long)(tp->last_event_jiffies + 1 +
1224 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1226 if (time_remain < 0)
1229 /* Check if we can shorten the wait time. */
1230 delay_cnt = jiffies_to_usecs(time_remain);
1231 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1232 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1233 delay_cnt = (delay_cnt >> 3) + 1;
1235 for (i = 0; i < delay_cnt; i++) {
1236 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1242 /* tp->lock is held. */
1243 static void tg3_ump_link_report(struct tg3 *tp)
1248 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1249 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1252 tg3_wait_for_event_ack(tp);
1254 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1256 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1259 if (!tg3_readphy(tp, MII_BMCR, ®))
1261 if (!tg3_readphy(tp, MII_BMSR, ®))
1262 val |= (reg & 0xffff);
1263 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1266 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1268 if (!tg3_readphy(tp, MII_LPA, ®))
1269 val |= (reg & 0xffff);
1270 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1273 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1274 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1276 if (!tg3_readphy(tp, MII_STAT1000, ®))
1277 val |= (reg & 0xffff);
1279 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1281 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1285 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1287 tg3_generate_fw_event(tp);
1290 static void tg3_link_report(struct tg3 *tp)
1292 if (!netif_carrier_ok(tp->dev)) {
1293 netif_info(tp, link, tp->dev, "Link is down\n");
1294 tg3_ump_link_report(tp);
1295 } else if (netif_msg_link(tp)) {
1296 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1297 (tp->link_config.active_speed == SPEED_1000 ?
1299 (tp->link_config.active_speed == SPEED_100 ?
1301 (tp->link_config.active_duplex == DUPLEX_FULL ?
1304 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1305 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1307 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1309 tg3_ump_link_report(tp);
1313 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1317 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1318 miireg = ADVERTISE_PAUSE_CAP;
1319 else if (flow_ctrl & FLOW_CTRL_TX)
1320 miireg = ADVERTISE_PAUSE_ASYM;
1321 else if (flow_ctrl & FLOW_CTRL_RX)
1322 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1329 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1333 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1334 miireg = ADVERTISE_1000XPAUSE;
1335 else if (flow_ctrl & FLOW_CTRL_TX)
1336 miireg = ADVERTISE_1000XPSE_ASYM;
1337 else if (flow_ctrl & FLOW_CTRL_RX)
1338 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1345 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1349 if (lcladv & ADVERTISE_1000XPAUSE) {
1350 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1351 if (rmtadv & LPA_1000XPAUSE)
1352 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1353 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1356 if (rmtadv & LPA_1000XPAUSE)
1357 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1359 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1360 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1367 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1371 u32 old_rx_mode = tp->rx_mode;
1372 u32 old_tx_mode = tp->tx_mode;
1374 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1375 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1377 autoneg = tp->link_config.autoneg;
1379 if (autoneg == AUTONEG_ENABLE &&
1380 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1381 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1382 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1384 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1386 flowctrl = tp->link_config.flowctrl;
1388 tp->link_config.active_flowctrl = flowctrl;
1390 if (flowctrl & FLOW_CTRL_RX)
1391 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1393 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1395 if (old_rx_mode != tp->rx_mode)
1396 tw32_f(MAC_RX_MODE, tp->rx_mode);
1398 if (flowctrl & FLOW_CTRL_TX)
1399 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1401 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1403 if (old_tx_mode != tp->tx_mode)
1404 tw32_f(MAC_TX_MODE, tp->tx_mode);
1407 static void tg3_adjust_link(struct net_device *dev)
1409 u8 oldflowctrl, linkmesg = 0;
1410 u32 mac_mode, lcl_adv, rmt_adv;
1411 struct tg3 *tp = netdev_priv(dev);
1412 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1414 spin_lock_bh(&tp->lock);
1416 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1417 MAC_MODE_HALF_DUPLEX);
1419 oldflowctrl = tp->link_config.active_flowctrl;
1425 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1426 mac_mode |= MAC_MODE_PORT_MODE_MII;
1427 else if (phydev->speed == SPEED_1000 ||
1428 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1429 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1431 mac_mode |= MAC_MODE_PORT_MODE_MII;
1433 if (phydev->duplex == DUPLEX_HALF)
1434 mac_mode |= MAC_MODE_HALF_DUPLEX;
1436 lcl_adv = tg3_advert_flowctrl_1000T(
1437 tp->link_config.flowctrl);
1440 rmt_adv = LPA_PAUSE_CAP;
1441 if (phydev->asym_pause)
1442 rmt_adv |= LPA_PAUSE_ASYM;
1445 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1447 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1449 if (mac_mode != tp->mac_mode) {
1450 tp->mac_mode = mac_mode;
1451 tw32_f(MAC_MODE, tp->mac_mode);
1455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1456 if (phydev->speed == SPEED_10)
1458 MAC_MI_STAT_10MBPS_MODE |
1459 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1464 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1465 tw32(MAC_TX_LENGTHS,
1466 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1467 (6 << TX_LENGTHS_IPG_SHIFT) |
1468 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1470 tw32(MAC_TX_LENGTHS,
1471 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1472 (6 << TX_LENGTHS_IPG_SHIFT) |
1473 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1475 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1476 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1477 phydev->speed != tp->link_config.active_speed ||
1478 phydev->duplex != tp->link_config.active_duplex ||
1479 oldflowctrl != tp->link_config.active_flowctrl)
1482 tp->link_config.active_speed = phydev->speed;
1483 tp->link_config.active_duplex = phydev->duplex;
1485 spin_unlock_bh(&tp->lock);
1488 tg3_link_report(tp);
1491 static int tg3_phy_init(struct tg3 *tp)
1493 struct phy_device *phydev;
1495 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1498 /* Bring the PHY back to a known state. */
1501 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503 /* Attach the MAC to the PHY. */
1504 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1505 phydev->dev_flags, phydev->interface);
1506 if (IS_ERR(phydev)) {
1507 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1508 return PTR_ERR(phydev);
1511 /* Mask with MAC supported features. */
1512 switch (phydev->interface) {
1513 case PHY_INTERFACE_MODE_GMII:
1514 case PHY_INTERFACE_MODE_RGMII:
1515 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1516 phydev->supported &= (PHY_GBIT_FEATURES |
1518 SUPPORTED_Asym_Pause);
1522 case PHY_INTERFACE_MODE_MII:
1523 phydev->supported &= (PHY_BASIC_FEATURES |
1525 SUPPORTED_Asym_Pause);
1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1532 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1534 phydev->advertising = phydev->supported;
1539 static void tg3_phy_start(struct tg3 *tp)
1541 struct phy_device *phydev;
1543 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1546 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1548 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1549 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1550 phydev->speed = tp->link_config.orig_speed;
1551 phydev->duplex = tp->link_config.orig_duplex;
1552 phydev->autoneg = tp->link_config.orig_autoneg;
1553 phydev->advertising = tp->link_config.orig_advertising;
1558 phy_start_aneg(phydev);
1561 static void tg3_phy_stop(struct tg3 *tp)
1563 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1566 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1569 static void tg3_phy_fini(struct tg3 *tp)
1571 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1572 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1573 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1577 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1581 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1583 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1588 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1592 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1594 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1599 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1603 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1606 tg3_writephy(tp, MII_TG3_FET_TEST,
1607 phytest | MII_TG3_FET_SHADOW_EN);
1608 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1610 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1612 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1613 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1615 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1619 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1623 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1624 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1625 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1626 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1629 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1630 tg3_phy_fet_toggle_apd(tp, enable);
1634 reg = MII_TG3_MISC_SHDW_WREN |
1635 MII_TG3_MISC_SHDW_SCR5_SEL |
1636 MII_TG3_MISC_SHDW_SCR5_LPED |
1637 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1638 MII_TG3_MISC_SHDW_SCR5_SDTL |
1639 MII_TG3_MISC_SHDW_SCR5_C125OE;
1640 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1641 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1643 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1646 reg = MII_TG3_MISC_SHDW_WREN |
1647 MII_TG3_MISC_SHDW_APD_SEL |
1648 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1650 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1652 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1655 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1659 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1660 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1663 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1666 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1667 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1669 tg3_writephy(tp, MII_TG3_FET_TEST,
1670 ephy | MII_TG3_FET_SHADOW_EN);
1671 if (!tg3_readphy(tp, reg, &phy)) {
1673 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1675 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1676 tg3_writephy(tp, reg, phy);
1678 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1681 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1682 MII_TG3_AUXCTL_SHDWSEL_MISC;
1683 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1684 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1686 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1688 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1689 phy |= MII_TG3_AUXCTL_MISC_WREN;
1690 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1695 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1699 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1702 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1703 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1704 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1705 (val | (1 << 15) | (1 << 4)));
1708 static void tg3_phy_apply_otp(struct tg3 *tp)
1717 /* Enable SM_DSP clock and tx 6dB coding. */
1718 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1719 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1720 MII_TG3_AUXCTL_ACTL_TX_6DB;
1721 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1723 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1724 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1725 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1727 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1728 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1729 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1731 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1732 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1733 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1735 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1736 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1738 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1739 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1741 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1742 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1743 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1745 /* Turn off SM_DSP clock. */
1746 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1747 MII_TG3_AUXCTL_ACTL_TX_6DB;
1748 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1751 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1755 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1760 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1761 current_link_up == 1 &&
1762 tp->link_config.active_duplex == DUPLEX_FULL &&
1763 (tp->link_config.active_speed == SPEED_100 ||
1764 tp->link_config.active_speed == SPEED_1000)) {
1767 if (tp->link_config.active_speed == SPEED_1000)
1768 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1770 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1772 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1774 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1775 TG3_CL45_D7_EEERES_STAT, &val);
1778 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1779 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1782 case ASIC_REV_57765:
1783 /* Enable SM_DSP clock and tx 6dB coding. */
1784 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1785 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1786 MII_TG3_AUXCTL_ACTL_TX_6DB;
1787 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1789 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1791 /* Turn off SM_DSP clock. */
1792 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1793 MII_TG3_AUXCTL_ACTL_TX_6DB;
1794 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1797 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1802 if (!tp->setlpicnt) {
1803 val = tr32(TG3_CPMU_EEE_MODE);
1804 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1808 static int tg3_wait_macro_done(struct tg3 *tp)
1815 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1816 if ((tmp32 & 0x1000) == 0)
1826 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1828 static const u32 test_pat[4][6] = {
1829 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1830 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1831 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1832 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1836 for (chan = 0; chan < 4; chan++) {
1839 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1840 (chan * 0x2000) | 0x0200);
1841 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1843 for (i = 0; i < 6; i++)
1844 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1847 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1848 if (tg3_wait_macro_done(tp)) {
1853 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1854 (chan * 0x2000) | 0x0200);
1855 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1856 if (tg3_wait_macro_done(tp)) {
1861 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1862 if (tg3_wait_macro_done(tp)) {
1867 for (i = 0; i < 6; i += 2) {
1870 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1871 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1872 tg3_wait_macro_done(tp)) {
1878 if (low != test_pat[chan][i] ||
1879 high != test_pat[chan][i+1]) {
1880 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1881 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1882 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1892 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1896 for (chan = 0; chan < 4; chan++) {
1899 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1900 (chan * 0x2000) | 0x0200);
1901 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1902 for (i = 0; i < 6; i++)
1903 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1904 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1905 if (tg3_wait_macro_done(tp))
1912 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1914 u32 reg32, phy9_orig;
1915 int retries, do_phy_reset, err;
1921 err = tg3_bmcr_reset(tp);
1927 /* Disable transmitter and interrupt. */
1928 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1932 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1934 /* Set full-duplex, 1000 mbps. */
1935 tg3_writephy(tp, MII_BMCR,
1936 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1938 /* Set to master mode. */
1939 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1942 tg3_writephy(tp, MII_TG3_CTRL,
1943 (MII_TG3_CTRL_AS_MASTER |
1944 MII_TG3_CTRL_ENABLE_AS_MASTER));
1946 /* Enable SM_DSP_CLOCK and 6dB. */
1947 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1949 /* Block the PHY control access. */
1950 tg3_phydsp_write(tp, 0x8005, 0x0800);
1952 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1955 } while (--retries);
1957 err = tg3_phy_reset_chanpat(tp);
1961 tg3_phydsp_write(tp, 0x8005, 0x0000);
1963 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1964 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1968 /* Set Extended packet length bit for jumbo frames */
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1971 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1974 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1976 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1978 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1985 /* This will reset the tigon3 PHY if there is no valid
1986 * link unless the FORCE argument is non-zero.
1988 static int tg3_phy_reset(struct tg3 *tp)
1993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1994 val = tr32(GRC_MISC_CFG);
1995 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1998 err = tg3_readphy(tp, MII_BMSR, &val);
1999 err |= tg3_readphy(tp, MII_BMSR, &val);
2003 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2004 netif_carrier_off(tp->dev);
2005 tg3_link_report(tp);
2008 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2011 err = tg3_phy_reset_5703_4_5(tp);
2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2019 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2020 cpmuctrl = tr32(TG3_CPMU_CTRL);
2021 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2023 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2026 err = tg3_bmcr_reset(tp);
2030 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2031 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2032 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2034 tw32(TG3_CPMU_CTRL, cpmuctrl);
2037 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2038 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2039 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2040 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2041 CPMU_LSPD_1000MB_MACCLK_12_5) {
2042 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2044 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2048 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2049 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2050 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2053 tg3_phy_apply_otp(tp);
2055 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2056 tg3_phy_toggle_apd(tp, true);
2058 tg3_phy_toggle_apd(tp, false);
2061 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2062 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2063 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2064 tg3_phydsp_write(tp, 0x000a, 0x0323);
2065 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2067 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2068 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2069 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2071 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2072 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2073 tg3_phydsp_write(tp, 0x000a, 0x310b);
2074 tg3_phydsp_write(tp, 0x201f, 0x9506);
2075 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2076 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2077 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2078 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2079 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2080 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2081 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2082 tg3_writephy(tp, MII_TG3_TEST1,
2083 MII_TG3_TEST1_TRIM_EN | 0x4);
2085 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2086 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2088 /* Set Extended packet length bit (bit 14) on all chips that */
2089 /* support jumbo frames */
2090 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2091 /* Cannot do read-modify-write on 5401 */
2092 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2093 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2094 /* Set bit 14 with read-modify-write to preserve other bits */
2095 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2096 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2097 tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2100 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2101 * jumbo frames transmission.
2103 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2104 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2105 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2106 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2110 /* adjust output voltage */
2111 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2114 tg3_phy_toggle_automdix(tp, 1);
2115 tg3_phy_set_wirespeed(tp);
2119 static void tg3_frob_aux_power(struct tg3 *tp)
2121 bool need_vaux = false;
2123 /* The GPIOs do something completely different on 57765. */
2124 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2129 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2131 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) &&
2132 tp->pdev_peer != tp->pdev) {
2133 struct net_device *dev_peer;
2135 dev_peer = pci_get_drvdata(tp->pdev_peer);
2137 /* remove_one() may have been run on the peer. */
2139 struct tg3 *tp_peer = netdev_priv(dev_peer);
2141 if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2144 if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2145 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2150 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2151 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2155 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2156 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2157 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2158 (GRC_LCLCTRL_GPIO_OE0 |
2159 GRC_LCLCTRL_GPIO_OE1 |
2160 GRC_LCLCTRL_GPIO_OE2 |
2161 GRC_LCLCTRL_GPIO_OUTPUT0 |
2162 GRC_LCLCTRL_GPIO_OUTPUT1),
2164 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2165 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2166 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2167 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2168 GRC_LCLCTRL_GPIO_OE1 |
2169 GRC_LCLCTRL_GPIO_OE2 |
2170 GRC_LCLCTRL_GPIO_OUTPUT0 |
2171 GRC_LCLCTRL_GPIO_OUTPUT1 |
2173 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2175 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2176 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2178 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2179 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2182 u32 grc_local_ctrl = 0;
2184 /* Workaround to prevent overdrawing Amps. */
2185 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2187 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2188 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2189 grc_local_ctrl, 100);
2192 /* On 5753 and variants, GPIO2 cannot be used. */
2193 no_gpio2 = tp->nic_sram_data_cfg &
2194 NIC_SRAM_DATA_CFG_NO_GPIO2;
2196 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2197 GRC_LCLCTRL_GPIO_OE1 |
2198 GRC_LCLCTRL_GPIO_OE2 |
2199 GRC_LCLCTRL_GPIO_OUTPUT1 |
2200 GRC_LCLCTRL_GPIO_OUTPUT2;
2202 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2203 GRC_LCLCTRL_GPIO_OUTPUT2);
2205 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2206 grc_local_ctrl, 100);
2208 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2210 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211 grc_local_ctrl, 100);
2214 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2215 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2216 grc_local_ctrl, 100);
2220 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2221 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2222 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2223 (GRC_LCLCTRL_GPIO_OE1 |
2224 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2226 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2227 GRC_LCLCTRL_GPIO_OE1, 100);
2229 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2230 (GRC_LCLCTRL_GPIO_OE1 |
2231 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2236 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2238 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2240 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2241 if (speed != SPEED_10)
2243 } else if (speed == SPEED_10)
2249 static int tg3_setup_phy(struct tg3 *, int);
2251 #define RESET_KIND_SHUTDOWN 0
2252 #define RESET_KIND_INIT 1
2253 #define RESET_KIND_SUSPEND 2
2255 static void tg3_write_sig_post_reset(struct tg3 *, int);
2256 static int tg3_halt_cpu(struct tg3 *, u32);
2258 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2262 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2264 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2265 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2268 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2269 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2270 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2275 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2277 val = tr32(GRC_MISC_CFG);
2278 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2281 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2283 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2286 tg3_writephy(tp, MII_ADVERTISE, 0);
2287 tg3_writephy(tp, MII_BMCR,
2288 BMCR_ANENABLE | BMCR_ANRESTART);
2290 tg3_writephy(tp, MII_TG3_FET_TEST,
2291 phytest | MII_TG3_FET_SHADOW_EN);
2292 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2293 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2295 MII_TG3_FET_SHDW_AUXMODE4,
2298 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2301 } else if (do_low_power) {
2302 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2303 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2305 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2306 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2307 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2308 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2309 MII_TG3_AUXCTL_PCTL_VREG_11V);
2312 /* The PHY should not be powered down on some chips because
2315 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2316 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2317 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2318 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2321 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2322 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2323 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2324 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2325 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2326 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2329 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2332 /* tp->lock is held. */
2333 static int tg3_nvram_lock(struct tg3 *tp)
2335 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2338 if (tp->nvram_lock_cnt == 0) {
2339 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2340 for (i = 0; i < 8000; i++) {
2341 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2346 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2350 tp->nvram_lock_cnt++;
2355 /* tp->lock is held. */
2356 static void tg3_nvram_unlock(struct tg3 *tp)
2358 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2359 if (tp->nvram_lock_cnt > 0)
2360 tp->nvram_lock_cnt--;
2361 if (tp->nvram_lock_cnt == 0)
2362 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2366 /* tp->lock is held. */
2367 static void tg3_enable_nvram_access(struct tg3 *tp)
2369 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2370 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2371 u32 nvaccess = tr32(NVRAM_ACCESS);
2373 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2377 /* tp->lock is held. */
2378 static void tg3_disable_nvram_access(struct tg3 *tp)
2380 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2381 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2382 u32 nvaccess = tr32(NVRAM_ACCESS);
2384 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2388 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2389 u32 offset, u32 *val)
2394 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2397 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2398 EEPROM_ADDR_DEVID_MASK |
2400 tw32(GRC_EEPROM_ADDR,
2402 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2403 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2404 EEPROM_ADDR_ADDR_MASK) |
2405 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2407 for (i = 0; i < 1000; i++) {
2408 tmp = tr32(GRC_EEPROM_ADDR);
2410 if (tmp & EEPROM_ADDR_COMPLETE)
2414 if (!(tmp & EEPROM_ADDR_COMPLETE))
2417 tmp = tr32(GRC_EEPROM_DATA);
2420 * The data will always be opposite the native endian
2421 * format. Perform a blind byteswap to compensate.
2428 #define NVRAM_CMD_TIMEOUT 10000
2430 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2434 tw32(NVRAM_CMD, nvram_cmd);
2435 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2437 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2443 if (i == NVRAM_CMD_TIMEOUT)
2449 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2451 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2452 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2453 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2454 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2455 (tp->nvram_jedecnum == JEDEC_ATMEL))
2457 addr = ((addr / tp->nvram_pagesize) <<
2458 ATMEL_AT45DB0X1B_PAGE_POS) +
2459 (addr % tp->nvram_pagesize);
2464 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2466 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2467 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2468 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2469 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2470 (tp->nvram_jedecnum == JEDEC_ATMEL))
2472 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2473 tp->nvram_pagesize) +
2474 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2479 /* NOTE: Data read in from NVRAM is byteswapped according to
2480 * the byteswapping settings for all other register accesses.
2481 * tg3 devices are BE devices, so on a BE machine, the data
2482 * returned will be exactly as it is seen in NVRAM. On a LE
2483 * machine, the 32-bit value will be byteswapped.
2485 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2489 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2490 return tg3_nvram_read_using_eeprom(tp, offset, val);
2492 offset = tg3_nvram_phys_addr(tp, offset);
2494 if (offset > NVRAM_ADDR_MSK)
2497 ret = tg3_nvram_lock(tp);
2501 tg3_enable_nvram_access(tp);
2503 tw32(NVRAM_ADDR, offset);
2504 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2505 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2508 *val = tr32(NVRAM_RDDATA);
2510 tg3_disable_nvram_access(tp);
2512 tg3_nvram_unlock(tp);
2517 /* Ensures NVRAM data is in bytestream format. */
2518 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2521 int res = tg3_nvram_read(tp, offset, &v);
2523 *val = cpu_to_be32(v);
2527 /* tp->lock is held. */
2528 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2530 u32 addr_high, addr_low;
2533 addr_high = ((tp->dev->dev_addr[0] << 8) |
2534 tp->dev->dev_addr[1]);
2535 addr_low = ((tp->dev->dev_addr[2] << 24) |
2536 (tp->dev->dev_addr[3] << 16) |
2537 (tp->dev->dev_addr[4] << 8) |
2538 (tp->dev->dev_addr[5] << 0));
2539 for (i = 0; i < 4; i++) {
2540 if (i == 1 && skip_mac_1)
2542 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2543 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2546 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2547 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2548 for (i = 0; i < 12; i++) {
2549 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2550 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2554 addr_high = (tp->dev->dev_addr[0] +
2555 tp->dev->dev_addr[1] +
2556 tp->dev->dev_addr[2] +
2557 tp->dev->dev_addr[3] +
2558 tp->dev->dev_addr[4] +
2559 tp->dev->dev_addr[5]) &
2560 TX_BACKOFF_SEED_MASK;
2561 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2564 static void tg3_enable_register_access(struct tg3 *tp)
2567 * Make sure register accesses (indirect or otherwise) will function
2570 pci_write_config_dword(tp->pdev,
2571 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2574 static int tg3_power_up(struct tg3 *tp)
2576 tg3_enable_register_access(tp);
2578 pci_set_power_state(tp->pdev, PCI_D0);
2580 /* Switch out of Vaux if it is a NIC */
2581 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2582 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2587 static int tg3_power_down_prepare(struct tg3 *tp)
2590 bool device_should_wake, do_low_power;
2592 tg3_enable_register_access(tp);
2594 /* Restore the CLKREQ setting. */
2595 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2598 pci_read_config_word(tp->pdev,
2599 tp->pcie_cap + PCI_EXP_LNKCTL,
2601 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2602 pci_write_config_word(tp->pdev,
2603 tp->pcie_cap + PCI_EXP_LNKCTL,
2607 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2608 tw32(TG3PCI_MISC_HOST_CTRL,
2609 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2611 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2612 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2614 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2615 do_low_power = false;
2616 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2617 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2618 struct phy_device *phydev;
2619 u32 phyid, advertising;
2621 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2623 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2625 tp->link_config.orig_speed = phydev->speed;
2626 tp->link_config.orig_duplex = phydev->duplex;
2627 tp->link_config.orig_autoneg = phydev->autoneg;
2628 tp->link_config.orig_advertising = phydev->advertising;
2630 advertising = ADVERTISED_TP |
2632 ADVERTISED_Autoneg |
2633 ADVERTISED_10baseT_Half;
2635 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2636 device_should_wake) {
2637 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2639 ADVERTISED_100baseT_Half |
2640 ADVERTISED_100baseT_Full |
2641 ADVERTISED_10baseT_Full;
2643 advertising |= ADVERTISED_10baseT_Full;
2646 phydev->advertising = advertising;
2648 phy_start_aneg(phydev);
2650 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2651 if (phyid != PHY_ID_BCMAC131) {
2652 phyid &= PHY_BCM_OUI_MASK;
2653 if (phyid == PHY_BCM_OUI_1 ||
2654 phyid == PHY_BCM_OUI_2 ||
2655 phyid == PHY_BCM_OUI_3)
2656 do_low_power = true;
2660 do_low_power = true;
2662 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2663 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2664 tp->link_config.orig_speed = tp->link_config.speed;
2665 tp->link_config.orig_duplex = tp->link_config.duplex;
2666 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2669 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2670 tp->link_config.speed = SPEED_10;
2671 tp->link_config.duplex = DUPLEX_HALF;
2672 tp->link_config.autoneg = AUTONEG_ENABLE;
2673 tg3_setup_phy(tp, 0);
2677 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2680 val = tr32(GRC_VCPU_EXT_CTRL);
2681 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2682 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2686 for (i = 0; i < 200; i++) {
2687 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2688 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2693 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2694 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2695 WOL_DRV_STATE_SHUTDOWN |
2699 if (device_should_wake) {
2702 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2704 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2708 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2709 mac_mode = MAC_MODE_PORT_MODE_GMII;
2711 mac_mode = MAC_MODE_PORT_MODE_MII;
2713 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2714 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2716 u32 speed = (tp->tg3_flags &
2717 TG3_FLAG_WOL_SPEED_100MB) ?
2718 SPEED_100 : SPEED_10;
2719 if (tg3_5700_link_polarity(tp, speed))
2720 mac_mode |= MAC_MODE_LINK_POLARITY;
2722 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2725 mac_mode = MAC_MODE_PORT_MODE_TBI;
2728 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2729 tw32(MAC_LED_CTRL, tp->led_ctrl);
2731 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2732 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2733 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2734 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2735 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2736 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2738 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2739 mac_mode |= MAC_MODE_APE_TX_EN |
2740 MAC_MODE_APE_RX_EN |
2741 MAC_MODE_TDE_ENABLE;
2743 tw32_f(MAC_MODE, mac_mode);
2746 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2750 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2751 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2752 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2755 base_val = tp->pci_clock_ctrl;
2756 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2757 CLOCK_CTRL_TXCLK_DISABLE);
2759 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2760 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2761 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2762 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2763 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2765 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2766 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2767 u32 newbits1, newbits2;
2769 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2770 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2771 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2772 CLOCK_CTRL_TXCLK_DISABLE |
2774 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2775 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2776 newbits1 = CLOCK_CTRL_625_CORE;
2777 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2779 newbits1 = CLOCK_CTRL_ALTCLK;
2780 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2783 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2786 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2789 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2793 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2794 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2795 CLOCK_CTRL_TXCLK_DISABLE |
2796 CLOCK_CTRL_44MHZ_CORE);
2798 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2801 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2802 tp->pci_clock_ctrl | newbits3, 40);
2806 if (!(device_should_wake) &&
2807 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2808 tg3_power_down_phy(tp, do_low_power);
2810 tg3_frob_aux_power(tp);
2812 /* Workaround for unstable PLL clock */
2813 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2814 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2815 u32 val = tr32(0x7d00);
2817 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2819 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2822 err = tg3_nvram_lock(tp);
2823 tg3_halt_cpu(tp, RX_CPU_BASE);
2825 tg3_nvram_unlock(tp);
2829 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2834 static void tg3_power_down(struct tg3 *tp)
2836 tg3_power_down_prepare(tp);
2838 pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2839 pci_set_power_state(tp->pdev, PCI_D3hot);
2842 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2844 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2845 case MII_TG3_AUX_STAT_10HALF:
2847 *duplex = DUPLEX_HALF;
2850 case MII_TG3_AUX_STAT_10FULL:
2852 *duplex = DUPLEX_FULL;
2855 case MII_TG3_AUX_STAT_100HALF:
2857 *duplex = DUPLEX_HALF;
2860 case MII_TG3_AUX_STAT_100FULL:
2862 *duplex = DUPLEX_FULL;
2865 case MII_TG3_AUX_STAT_1000HALF:
2866 *speed = SPEED_1000;
2867 *duplex = DUPLEX_HALF;
2870 case MII_TG3_AUX_STAT_1000FULL:
2871 *speed = SPEED_1000;
2872 *duplex = DUPLEX_FULL;
2876 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2877 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2879 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2883 *speed = SPEED_INVALID;
2884 *duplex = DUPLEX_INVALID;
2889 static void tg3_phy_copper_begin(struct tg3 *tp)
2894 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2895 /* Entering low power mode. Disable gigabit and
2896 * 100baseT advertisements.
2898 tg3_writephy(tp, MII_TG3_CTRL, 0);
2900 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2901 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2902 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2903 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2905 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2906 } else if (tp->link_config.speed == SPEED_INVALID) {
2907 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2908 tp->link_config.advertising &=
2909 ~(ADVERTISED_1000baseT_Half |
2910 ADVERTISED_1000baseT_Full);
2912 new_adv = ADVERTISE_CSMA;
2913 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2914 new_adv |= ADVERTISE_10HALF;
2915 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2916 new_adv |= ADVERTISE_10FULL;
2917 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2918 new_adv |= ADVERTISE_100HALF;
2919 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2920 new_adv |= ADVERTISE_100FULL;
2922 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2924 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2926 if (tp->link_config.advertising &
2927 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2929 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2930 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2931 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2932 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2933 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2934 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2935 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2936 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2937 MII_TG3_CTRL_ENABLE_AS_MASTER);
2938 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2940 tg3_writephy(tp, MII_TG3_CTRL, 0);
2943 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2944 new_adv |= ADVERTISE_CSMA;
2946 /* Asking for a specific link mode. */
2947 if (tp->link_config.speed == SPEED_1000) {
2948 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2950 if (tp->link_config.duplex == DUPLEX_FULL)
2951 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2953 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2954 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2955 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2956 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2957 MII_TG3_CTRL_ENABLE_AS_MASTER);
2959 if (tp->link_config.speed == SPEED_100) {
2960 if (tp->link_config.duplex == DUPLEX_FULL)
2961 new_adv |= ADVERTISE_100FULL;
2963 new_adv |= ADVERTISE_100HALF;
2965 if (tp->link_config.duplex == DUPLEX_FULL)
2966 new_adv |= ADVERTISE_10FULL;
2968 new_adv |= ADVERTISE_10HALF;
2970 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2975 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2978 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2981 tw32(TG3_CPMU_EEE_MODE,
2982 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2984 /* Enable SM_DSP clock and tx 6dB coding. */
2985 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2986 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2987 MII_TG3_AUXCTL_ACTL_TX_6DB;
2988 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2990 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2992 case ASIC_REV_57765:
2993 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2994 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2995 MII_TG3_DSP_CH34TP2_HIBW01);
2998 val = MII_TG3_DSP_TAP26_ALNOKO |
2999 MII_TG3_DSP_TAP26_RMRXSTO |
3000 MII_TG3_DSP_TAP26_OPCSINPT;
3001 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3005 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3006 /* Advertise 100-BaseTX EEE ability */
3007 if (tp->link_config.advertising &
3008 ADVERTISED_100baseT_Full)
3009 val |= MDIO_AN_EEE_ADV_100TX;
3010 /* Advertise 1000-BaseT EEE ability */
3011 if (tp->link_config.advertising &
3012 ADVERTISED_1000baseT_Full)
3013 val |= MDIO_AN_EEE_ADV_1000T;
3015 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3017 /* Turn off SM_DSP clock. */
3018 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3019 MII_TG3_AUXCTL_ACTL_TX_6DB;
3020 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3023 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3024 tp->link_config.speed != SPEED_INVALID) {
3025 u32 bmcr, orig_bmcr;
3027 tp->link_config.active_speed = tp->link_config.speed;
3028 tp->link_config.active_duplex = tp->link_config.duplex;
3031 switch (tp->link_config.speed) {
3037 bmcr |= BMCR_SPEED100;
3041 bmcr |= TG3_BMCR_SPEED1000;
3045 if (tp->link_config.duplex == DUPLEX_FULL)
3046 bmcr |= BMCR_FULLDPLX;
3048 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3049 (bmcr != orig_bmcr)) {
3050 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3051 for (i = 0; i < 1500; i++) {
3055 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3056 tg3_readphy(tp, MII_BMSR, &tmp))
3058 if (!(tmp & BMSR_LSTATUS)) {
3063 tg3_writephy(tp, MII_BMCR, bmcr);
3067 tg3_writephy(tp, MII_BMCR,
3068 BMCR_ANENABLE | BMCR_ANRESTART);
3072 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3076 /* Turn off tap power management. */
3077 /* Set Extended packet length bit */
3078 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3080 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3081 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3082 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3083 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3084 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3091 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3093 u32 adv_reg, all_mask = 0;
3095 if (mask & ADVERTISED_10baseT_Half)
3096 all_mask |= ADVERTISE_10HALF;
3097 if (mask & ADVERTISED_10baseT_Full)
3098 all_mask |= ADVERTISE_10FULL;
3099 if (mask & ADVERTISED_100baseT_Half)
3100 all_mask |= ADVERTISE_100HALF;
3101 if (mask & ADVERTISED_100baseT_Full)
3102 all_mask |= ADVERTISE_100FULL;
3104 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3107 if ((adv_reg & all_mask) != all_mask)
3109 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3113 if (mask & ADVERTISED_1000baseT_Half)
3114 all_mask |= ADVERTISE_1000HALF;
3115 if (mask & ADVERTISED_1000baseT_Full)
3116 all_mask |= ADVERTISE_1000FULL;
3118 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3121 if ((tg3_ctrl & all_mask) != all_mask)
3127 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3131 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3134 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3135 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3137 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3138 if (curadv != reqadv)
3141 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3142 tg3_readphy(tp, MII_LPA, rmtadv);
3144 /* Reprogram the advertisement register, even if it
3145 * does not affect the current link. If the link
3146 * gets renegotiated in the future, we can save an
3147 * additional renegotiation cycle by advertising
3148 * it correctly in the first place.
3150 if (curadv != reqadv) {
3151 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3152 ADVERTISE_PAUSE_ASYM);
3153 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3160 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3162 int current_link_up;
3164 u32 lcl_adv, rmt_adv;
3172 (MAC_STATUS_SYNC_CHANGED |
3173 MAC_STATUS_CFG_CHANGED |
3174 MAC_STATUS_MI_COMPLETION |
3175 MAC_STATUS_LNKSTATE_CHANGED));
3178 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3180 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3184 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3186 /* Some third-party PHYs need to be reset on link going
3189 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3191 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3192 netif_carrier_ok(tp->dev)) {
3193 tg3_readphy(tp, MII_BMSR, &bmsr);
3194 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3195 !(bmsr & BMSR_LSTATUS))
3201 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3202 tg3_readphy(tp, MII_BMSR, &bmsr);
3203 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3204 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3207 if (!(bmsr & BMSR_LSTATUS)) {
3208 err = tg3_init_5401phy_dsp(tp);
3212 tg3_readphy(tp, MII_BMSR, &bmsr);
3213 for (i = 0; i < 1000; i++) {
3215 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3216 (bmsr & BMSR_LSTATUS)) {
3222 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3223 TG3_PHY_REV_BCM5401_B0 &&
3224 !(bmsr & BMSR_LSTATUS) &&
3225 tp->link_config.active_speed == SPEED_1000) {
3226 err = tg3_phy_reset(tp);
3228 err = tg3_init_5401phy_dsp(tp);
3233 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3234 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3235 /* 5701 {A0,B0} CRC bug workaround */
3236 tg3_writephy(tp, 0x15, 0x0a75);
3237 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3238 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3239 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3242 /* Clear pending interrupts... */
3243 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3244 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3246 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3247 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3248 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3249 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3251 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3252 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3253 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3254 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3255 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3257 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3260 current_link_up = 0;
3261 current_speed = SPEED_INVALID;
3262 current_duplex = DUPLEX_INVALID;
3264 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3265 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3266 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3267 if (!(val & (1 << 10))) {
3269 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3275 for (i = 0; i < 100; i++) {
3276 tg3_readphy(tp, MII_BMSR, &bmsr);
3277 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3278 (bmsr & BMSR_LSTATUS))
3283 if (bmsr & BMSR_LSTATUS) {
3286 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3287 for (i = 0; i < 2000; i++) {
3289 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3294 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3299 for (i = 0; i < 200; i++) {
3300 tg3_readphy(tp, MII_BMCR, &bmcr);
3301 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3303 if (bmcr && bmcr != 0x7fff)
3311 tp->link_config.active_speed = current_speed;
3312 tp->link_config.active_duplex = current_duplex;
3314 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3315 if ((bmcr & BMCR_ANENABLE) &&
3316 tg3_copper_is_advertising_all(tp,
3317 tp->link_config.advertising)) {
3318 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3320 current_link_up = 1;
3323 if (!(bmcr & BMCR_ANENABLE) &&
3324 tp->link_config.speed == current_speed &&
3325 tp->link_config.duplex == current_duplex &&
3326 tp->link_config.flowctrl ==
3327 tp->link_config.active_flowctrl) {
3328 current_link_up = 1;
3332 if (current_link_up == 1 &&
3333 tp->link_config.active_duplex == DUPLEX_FULL)
3334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3338 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3339 tg3_phy_copper_begin(tp);
3341 tg3_readphy(tp, MII_BMSR, &bmsr);
3342 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3343 (bmsr & BMSR_LSTATUS))
3344 current_link_up = 1;
3347 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3348 if (current_link_up == 1) {
3349 if (tp->link_config.active_speed == SPEED_100 ||
3350 tp->link_config.active_speed == SPEED_10)
3351 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3353 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3354 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3355 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3357 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3359 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3360 if (tp->link_config.active_duplex == DUPLEX_HALF)
3361 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3364 if (current_link_up == 1 &&
3365 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3366 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3368 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3371 /* ??? Without this setting Netgear GA302T PHY does not
3372 * ??? send/receive packets...
3374 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3375 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3376 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3377 tw32_f(MAC_MI_MODE, tp->mi_mode);
3381 tw32_f(MAC_MODE, tp->mac_mode);
3384 tg3_phy_eee_adjust(tp, current_link_up);
3386 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3387 /* Polled via timer. */
3388 tw32_f(MAC_EVENT, 0);
3390 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3394 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3395 current_link_up == 1 &&
3396 tp->link_config.active_speed == SPEED_1000 &&
3397 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3398 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3401 (MAC_STATUS_SYNC_CHANGED |
3402 MAC_STATUS_CFG_CHANGED));
3405 NIC_SRAM_FIRMWARE_MBOX,
3406 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3409 /* Prevent send BD corruption. */
3410 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3411 u16 oldlnkctl, newlnkctl;
3413 pci_read_config_word(tp->pdev,
3414 tp->pcie_cap + PCI_EXP_LNKCTL,
3416 if (tp->link_config.active_speed == SPEED_100 ||
3417 tp->link_config.active_speed == SPEED_10)
3418 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3420 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3421 if (newlnkctl != oldlnkctl)
3422 pci_write_config_word(tp->pdev,
3423 tp->pcie_cap + PCI_EXP_LNKCTL,
3427 if (current_link_up != netif_carrier_ok(tp->dev)) {
3428 if (current_link_up)
3429 netif_carrier_on(tp->dev);
3431 netif_carrier_off(tp->dev);
3432 tg3_link_report(tp);
3438 struct tg3_fiber_aneginfo {
3440 #define ANEG_STATE_UNKNOWN 0
3441 #define ANEG_STATE_AN_ENABLE 1
3442 #define ANEG_STATE_RESTART_INIT 2
3443 #define ANEG_STATE_RESTART 3
3444 #define ANEG_STATE_DISABLE_LINK_OK 4
3445 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3446 #define ANEG_STATE_ABILITY_DETECT 6
3447 #define ANEG_STATE_ACK_DETECT_INIT 7
3448 #define ANEG_STATE_ACK_DETECT 8
3449 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3450 #define ANEG_STATE_COMPLETE_ACK 10
3451 #define ANEG_STATE_IDLE_DETECT_INIT 11
3452 #define ANEG_STATE_IDLE_DETECT 12
3453 #define ANEG_STATE_LINK_OK 13
3454 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3455 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3458 #define MR_AN_ENABLE 0x00000001
3459 #define MR_RESTART_AN 0x00000002
3460 #define MR_AN_COMPLETE 0x00000004
3461 #define MR_PAGE_RX 0x00000008
3462 #define MR_NP_LOADED 0x00000010
3463 #define MR_TOGGLE_TX 0x00000020
3464 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3465 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3466 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3467 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3468 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3469 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3470 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3471 #define MR_TOGGLE_RX 0x00002000
3472 #define MR_NP_RX 0x00004000
3474 #define MR_LINK_OK 0x80000000
3476 unsigned long link_time, cur_time;
3478 u32 ability_match_cfg;
3479 int ability_match_count;
3481 char ability_match, idle_match, ack_match;
3483 u32 txconfig, rxconfig;
3484 #define ANEG_CFG_NP 0x00000080
3485 #define ANEG_CFG_ACK 0x00000040
3486 #define ANEG_CFG_RF2 0x00000020
3487 #define ANEG_CFG_RF1 0x00000010
3488 #define ANEG_CFG_PS2 0x00000001
3489 #define ANEG_CFG_PS1 0x00008000
3490 #define ANEG_CFG_HD 0x00004000
3491 #define ANEG_CFG_FD 0x00002000
3492 #define ANEG_CFG_INVAL 0x00001f06
3497 #define ANEG_TIMER_ENAB 2
3498 #define ANEG_FAILED -1
3500 #define ANEG_STATE_SETTLE_TIME 10000
3502 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3503 struct tg3_fiber_aneginfo *ap)
3506 unsigned long delta;
3510 if (ap->state == ANEG_STATE_UNKNOWN) {
3514 ap->ability_match_cfg = 0;
3515 ap->ability_match_count = 0;
3516 ap->ability_match = 0;
3522 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3523 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3525 if (rx_cfg_reg != ap->ability_match_cfg) {
3526 ap->ability_match_cfg = rx_cfg_reg;
3527 ap->ability_match = 0;
3528 ap->ability_match_count = 0;
3530 if (++ap->ability_match_count > 1) {
3531 ap->ability_match = 1;
3532 ap->ability_match_cfg = rx_cfg_reg;
3535 if (rx_cfg_reg & ANEG_CFG_ACK)
3543 ap->ability_match_cfg = 0;
3544 ap->ability_match_count = 0;
3545 ap->ability_match = 0;
3551 ap->rxconfig = rx_cfg_reg;
3554 switch (ap->state) {
3555 case ANEG_STATE_UNKNOWN:
3556 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3557 ap->state = ANEG_STATE_AN_ENABLE;
3560 case ANEG_STATE_AN_ENABLE:
3561 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3562 if (ap->flags & MR_AN_ENABLE) {
3565 ap->ability_match_cfg = 0;
3566 ap->ability_match_count = 0;
3567 ap->ability_match = 0;
3571 ap->state = ANEG_STATE_RESTART_INIT;
3573 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3577 case ANEG_STATE_RESTART_INIT:
3578 ap->link_time = ap->cur_time;
3579 ap->flags &= ~(MR_NP_LOADED);
3581 tw32(MAC_TX_AUTO_NEG, 0);
3582 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3583 tw32_f(MAC_MODE, tp->mac_mode);
3586 ret = ANEG_TIMER_ENAB;
3587 ap->state = ANEG_STATE_RESTART;
3590 case ANEG_STATE_RESTART:
3591 delta = ap->cur_time - ap->link_time;
3592 if (delta > ANEG_STATE_SETTLE_TIME)
3593 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3595 ret = ANEG_TIMER_ENAB;
3598 case ANEG_STATE_DISABLE_LINK_OK:
3602 case ANEG_STATE_ABILITY_DETECT_INIT:
3603 ap->flags &= ~(MR_TOGGLE_TX);
3604 ap->txconfig = ANEG_CFG_FD;
3605 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3606 if (flowctrl & ADVERTISE_1000XPAUSE)
3607 ap->txconfig |= ANEG_CFG_PS1;
3608 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3609 ap->txconfig |= ANEG_CFG_PS2;
3610 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3611 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3612 tw32_f(MAC_MODE, tp->mac_mode);
3615 ap->state = ANEG_STATE_ABILITY_DETECT;
3618 case ANEG_STATE_ABILITY_DETECT:
3619 if (ap->ability_match != 0 && ap->rxconfig != 0)
3620 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3623 case ANEG_STATE_ACK_DETECT_INIT:
3624 ap->txconfig |= ANEG_CFG_ACK;
3625 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3626 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3627 tw32_f(MAC_MODE, tp->mac_mode);
3630 ap->state = ANEG_STATE_ACK_DETECT;
3633 case ANEG_STATE_ACK_DETECT:
3634 if (ap->ack_match != 0) {
3635 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3636 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3637 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3639 ap->state = ANEG_STATE_AN_ENABLE;
3641 } else if (ap->ability_match != 0 &&
3642 ap->rxconfig == 0) {
3643 ap->state = ANEG_STATE_AN_ENABLE;
3647 case ANEG_STATE_COMPLETE_ACK_INIT:
3648 if (ap->rxconfig & ANEG_CFG_INVAL) {
3652 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3653 MR_LP_ADV_HALF_DUPLEX |
3654 MR_LP_ADV_SYM_PAUSE |
3655 MR_LP_ADV_ASYM_PAUSE |
3656 MR_LP_ADV_REMOTE_FAULT1 |
3657 MR_LP_ADV_REMOTE_FAULT2 |
3658 MR_LP_ADV_NEXT_PAGE |
3661 if (ap->rxconfig & ANEG_CFG_FD)
3662 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3663 if (ap->rxconfig & ANEG_CFG_HD)
3664 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3665 if (ap->rxconfig & ANEG_CFG_PS1)
3666 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3667 if (ap->rxconfig & ANEG_CFG_PS2)
3668 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3669 if (ap->rxconfig & ANEG_CFG_RF1)
3670 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3671 if (ap->rxconfig & ANEG_CFG_RF2)
3672 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3673 if (ap->rxconfig & ANEG_CFG_NP)
3674 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3676 ap->link_time = ap->cur_time;
3678 ap->flags ^= (MR_TOGGLE_TX);
3679 if (ap->rxconfig & 0x0008)
3680 ap->flags |= MR_TOGGLE_RX;
3681 if (ap->rxconfig & ANEG_CFG_NP)
3682 ap->flags |= MR_NP_RX;
3683 ap->flags |= MR_PAGE_RX;
3685 ap->state = ANEG_STATE_COMPLETE_ACK;
3686 ret = ANEG_TIMER_ENAB;
3689 case ANEG_STATE_COMPLETE_ACK:
3690 if (ap->ability_match != 0 &&
3691 ap->rxconfig == 0) {
3692 ap->state = ANEG_STATE_AN_ENABLE;
3695 delta = ap->cur_time - ap->link_time;
3696 if (delta > ANEG_STATE_SETTLE_TIME) {
3697 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3698 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3700 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3701 !(ap->flags & MR_NP_RX)) {
3702 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3710 case ANEG_STATE_IDLE_DETECT_INIT:
3711 ap->link_time = ap->cur_time;
3712 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3713 tw32_f(MAC_MODE, tp->mac_mode);
3716 ap->state = ANEG_STATE_IDLE_DETECT;
3717 ret = ANEG_TIMER_ENAB;
3720 case ANEG_STATE_IDLE_DETECT:
3721 if (ap->ability_match != 0 &&
3722 ap->rxconfig == 0) {
3723 ap->state = ANEG_STATE_AN_ENABLE;
3726 delta = ap->cur_time - ap->link_time;
3727 if (delta > ANEG_STATE_SETTLE_TIME) {
3728 /* XXX another gem from the Broadcom driver :( */
3729 ap->state = ANEG_STATE_LINK_OK;
3733 case ANEG_STATE_LINK_OK:
3734 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3738 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3739 /* ??? unimplemented */
3742 case ANEG_STATE_NEXT_PAGE_WAIT:
3743 /* ??? unimplemented */
3754 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3757 struct tg3_fiber_aneginfo aninfo;
3758 int status = ANEG_FAILED;
3762 tw32_f(MAC_TX_AUTO_NEG, 0);
3764 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3765 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3768 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3771 memset(&aninfo, 0, sizeof(aninfo));
3772 aninfo.flags |= MR_AN_ENABLE;
3773 aninfo.state = ANEG_STATE_UNKNOWN;
3774 aninfo.cur_time = 0;
3776 while (++tick < 195000) {
3777 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3778 if (status == ANEG_DONE || status == ANEG_FAILED)
3784 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3785 tw32_f(MAC_MODE, tp->mac_mode);
3788 *txflags = aninfo.txconfig;
3789 *rxflags = aninfo.flags;
3791 if (status == ANEG_DONE &&
3792 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3793 MR_LP_ADV_FULL_DUPLEX)))
3799 static void tg3_init_bcm8002(struct tg3 *tp)
3801 u32 mac_status = tr32(MAC_STATUS);
3804 /* Reset when initting first time or we have a link. */
3805 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3806 !(mac_status & MAC_STATUS_PCS_SYNCED))
3809 /* Set PLL lock range. */
3810 tg3_writephy(tp, 0x16, 0x8007);
3813 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3815 /* Wait for reset to complete. */
3816 /* XXX schedule_timeout() ... */
3817 for (i = 0; i < 500; i++)
3820 /* Config mode; select PMA/Ch 1 regs. */
3821 tg3_writephy(tp, 0x10, 0x8411);
3823 /* Enable auto-lock and comdet, select txclk for tx. */
3824 tg3_writephy(tp, 0x11, 0x0a10);
3826 tg3_writephy(tp, 0x18, 0x00a0);
3827 tg3_writephy(tp, 0x16, 0x41ff);
3829 /* Assert and deassert POR. */
3830 tg3_writephy(tp, 0x13, 0x0400);
3832 tg3_writephy(tp, 0x13, 0x0000);
3834 tg3_writephy(tp, 0x11, 0x0a50);
3836 tg3_writephy(tp, 0x11, 0x0a10);
3838 /* Wait for signal to stabilize */
3839 /* XXX schedule_timeout() ... */
3840 for (i = 0; i < 15000; i++)
3843 /* Deselect the channel register so we can read the PHYID
3846 tg3_writephy(tp, 0x10, 0x8011);
3849 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3852 u32 sg_dig_ctrl, sg_dig_status;
3853 u32 serdes_cfg, expected_sg_dig_ctrl;
3854 int workaround, port_a;
3855 int current_link_up;
3858 expected_sg_dig_ctrl = 0;
3861 current_link_up = 0;
3863 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3864 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3866 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3869 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3870 /* preserve bits 20-23 for voltage regulator */
3871 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3874 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3876 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3877 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3879 u32 val = serdes_cfg;
3885 tw32_f(MAC_SERDES_CFG, val);
3888 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3890 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3891 tg3_setup_flow_control(tp, 0, 0);
3892 current_link_up = 1;
3897 /* Want auto-negotiation. */
3898 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3900 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3901 if (flowctrl & ADVERTISE_1000XPAUSE)
3902 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3903 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3904 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3906 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3907 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3908 tp->serdes_counter &&
3909 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3910 MAC_STATUS_RCVD_CFG)) ==
3911 MAC_STATUS_PCS_SYNCED)) {
3912 tp->serdes_counter--;
3913 current_link_up = 1;
3918 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3919 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3921 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3923 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3924 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3925 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3926 MAC_STATUS_SIGNAL_DET)) {
3927 sg_dig_status = tr32(SG_DIG_STATUS);
3928 mac_status = tr32(MAC_STATUS);
3930 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3931 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3932 u32 local_adv = 0, remote_adv = 0;
3934 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3935 local_adv |= ADVERTISE_1000XPAUSE;
3936 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3937 local_adv |= ADVERTISE_1000XPSE_ASYM;
3939 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3940 remote_adv |= LPA_1000XPAUSE;
3941 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3942 remote_adv |= LPA_1000XPAUSE_ASYM;
3944 tg3_setup_flow_control(tp, local_adv, remote_adv);
3945 current_link_up = 1;
3946 tp->serdes_counter = 0;
3947 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3948 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3949 if (tp->serdes_counter)
3950 tp->serdes_counter--;
3953 u32 val = serdes_cfg;
3960 tw32_f(MAC_SERDES_CFG, val);
3963 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3966 /* Link parallel detection - link is up */
3967 /* only if we have PCS_SYNC and not */
3968 /* receiving config code words */
3969 mac_status = tr32(MAC_STATUS);
3970 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3971 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3972 tg3_setup_flow_control(tp, 0, 0);
3973 current_link_up = 1;
3975 TG3_PHYFLG_PARALLEL_DETECT;
3976 tp->serdes_counter =
3977 SERDES_PARALLEL_DET_TIMEOUT;
3979 goto restart_autoneg;
3983 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3984 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3988 return current_link_up;
3991 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3993 int current_link_up = 0;
3995 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3998 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3999 u32 txflags, rxflags;
4002 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4003 u32 local_adv = 0, remote_adv = 0;
4005 if (txflags & ANEG_CFG_PS1)
4006 local_adv |= ADVERTISE_1000XPAUSE;
4007 if (txflags & ANEG_CFG_PS2)
4008 local_adv |= ADVERTISE_1000XPSE_ASYM;
4010 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4011 remote_adv |= LPA_1000XPAUSE;
4012 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4013 remote_adv |= LPA_1000XPAUSE_ASYM;
4015 tg3_setup_flow_control(tp, local_adv, remote_adv);
4017 current_link_up = 1;
4019 for (i = 0; i < 30; i++) {
4022 (MAC_STATUS_SYNC_CHANGED |
4023 MAC_STATUS_CFG_CHANGED));
4025 if ((tr32(MAC_STATUS) &
4026 (MAC_STATUS_SYNC_CHANGED |
4027 MAC_STATUS_CFG_CHANGED)) == 0)
4031 mac_status = tr32(MAC_STATUS);
4032 if (current_link_up == 0 &&
4033 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4034 !(mac_status & MAC_STATUS_RCVD_CFG))
4035 current_link_up = 1;
4037 tg3_setup_flow_control(tp, 0, 0);
4039 /* Forcing 1000FD link up. */
4040 current_link_up = 1;
4042 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4045 tw32_f(MAC_MODE, tp->mac_mode);
4050 return current_link_up;
4053 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4056 u16 orig_active_speed;
4057 u8 orig_active_duplex;
4059 int current_link_up;
4062 orig_pause_cfg = tp->link_config.active_flowctrl;
4063 orig_active_speed = tp->link_config.active_speed;
4064 orig_active_duplex = tp->link_config.active_duplex;
4066 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4067 netif_carrier_ok(tp->dev) &&
4068 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4069 mac_status = tr32(MAC_STATUS);
4070 mac_status &= (MAC_STATUS_PCS_SYNCED |
4071 MAC_STATUS_SIGNAL_DET |
4072 MAC_STATUS_CFG_CHANGED |
4073 MAC_STATUS_RCVD_CFG);
4074 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4075 MAC_STATUS_SIGNAL_DET)) {
4076 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4077 MAC_STATUS_CFG_CHANGED));
4082 tw32_f(MAC_TX_AUTO_NEG, 0);
4084 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4085 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4086 tw32_f(MAC_MODE, tp->mac_mode);
4089 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4090 tg3_init_bcm8002(tp);
4092 /* Enable link change event even when serdes polling. */
4093 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4096 current_link_up = 0;
4097 mac_status = tr32(MAC_STATUS);
4099 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4100 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4102 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4104 tp->napi[0].hw_status->status =
4105 (SD_STATUS_UPDATED |
4106 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4108 for (i = 0; i < 100; i++) {
4109 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4110 MAC_STATUS_CFG_CHANGED));
4112 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4113 MAC_STATUS_CFG_CHANGED |
4114 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4118 mac_status = tr32(MAC_STATUS);
4119 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4120 current_link_up = 0;
4121 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4122 tp->serdes_counter == 0) {
4123 tw32_f(MAC_MODE, (tp->mac_mode |
4124 MAC_MODE_SEND_CONFIGS));
4126 tw32_f(MAC_MODE, tp->mac_mode);
4130 if (current_link_up == 1) {
4131 tp->link_config.active_speed = SPEED_1000;
4132 tp->link_config.active_duplex = DUPLEX_FULL;
4133 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4134 LED_CTRL_LNKLED_OVERRIDE |
4135 LED_CTRL_1000MBPS_ON));
4137 tp->link_config.active_speed = SPEED_INVALID;
4138 tp->link_config.active_duplex = DUPLEX_INVALID;
4139 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4140 LED_CTRL_LNKLED_OVERRIDE |
4141 LED_CTRL_TRAFFIC_OVERRIDE));
4144 if (current_link_up != netif_carrier_ok(tp->dev)) {
4145 if (current_link_up)
4146 netif_carrier_on(tp->dev);
4148 netif_carrier_off(tp->dev);
4149 tg3_link_report(tp);
4151 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4152 if (orig_pause_cfg != now_pause_cfg ||
4153 orig_active_speed != tp->link_config.active_speed ||
4154 orig_active_duplex != tp->link_config.active_duplex)
4155 tg3_link_report(tp);
4161 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4163 int current_link_up, err = 0;
4167 u32 local_adv, remote_adv;
4169 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4170 tw32_f(MAC_MODE, tp->mac_mode);
4176 (MAC_STATUS_SYNC_CHANGED |
4177 MAC_STATUS_CFG_CHANGED |
4178 MAC_STATUS_MI_COMPLETION |
4179 MAC_STATUS_LNKSTATE_CHANGED));
4185 current_link_up = 0;
4186 current_speed = SPEED_INVALID;
4187 current_duplex = DUPLEX_INVALID;
4189 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4190 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4192 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4193 bmsr |= BMSR_LSTATUS;
4195 bmsr &= ~BMSR_LSTATUS;
4198 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4200 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4201 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4202 /* do nothing, just check for link up at the end */
4203 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4206 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4207 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4208 ADVERTISE_1000XPAUSE |
4209 ADVERTISE_1000XPSE_ASYM |
4212 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4214 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4215 new_adv |= ADVERTISE_1000XHALF;
4216 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4217 new_adv |= ADVERTISE_1000XFULL;
4219 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4220 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4221 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4222 tg3_writephy(tp, MII_BMCR, bmcr);
4224 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4225 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4226 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4233 bmcr &= ~BMCR_SPEED1000;
4234 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4236 if (tp->link_config.duplex == DUPLEX_FULL)
4237 new_bmcr |= BMCR_FULLDPLX;
4239 if (new_bmcr != bmcr) {
4240 /* BMCR_SPEED1000 is a reserved bit that needs
4241 * to be set on write.
4243 new_bmcr |= BMCR_SPEED1000;
4245 /* Force a linkdown */
4246 if (netif_carrier_ok(tp->dev)) {
4249 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4250 adv &= ~(ADVERTISE_1000XFULL |
4251 ADVERTISE_1000XHALF |
4253 tg3_writephy(tp, MII_ADVERTISE, adv);
4254 tg3_writephy(tp, MII_BMCR, bmcr |
4258 netif_carrier_off(tp->dev);
4260 tg3_writephy(tp, MII_BMCR, new_bmcr);
4262 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4263 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4264 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4266 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4267 bmsr |= BMSR_LSTATUS;
4269 bmsr &= ~BMSR_LSTATUS;
4271 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4275 if (bmsr & BMSR_LSTATUS) {
4276 current_speed = SPEED_1000;
4277 current_link_up = 1;
4278 if (bmcr & BMCR_FULLDPLX)
4279 current_duplex = DUPLEX_FULL;
4281 current_duplex = DUPLEX_HALF;
4286 if (bmcr & BMCR_ANENABLE) {
4289 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4290 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4291 common = local_adv & remote_adv;
4292 if (common & (ADVERTISE_1000XHALF |
4293 ADVERTISE_1000XFULL)) {
4294 if (common & ADVERTISE_1000XFULL)
4295 current_duplex = DUPLEX_FULL;
4297 current_duplex = DUPLEX_HALF;
4298 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4299 /* Link is up via parallel detect */
4301 current_link_up = 0;
4306 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4307 tg3_setup_flow_control(tp, local_adv, remote_adv);
4309 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4310 if (tp->link_config.active_duplex == DUPLEX_HALF)
4311 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4313 tw32_f(MAC_MODE, tp->mac_mode);
4316 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4318 tp->link_config.active_speed = current_speed;
4319 tp->link_config.active_duplex = current_duplex;
4321 if (current_link_up != netif_carrier_ok(tp->dev)) {
4322 if (current_link_up)
4323 netif_carrier_on(tp->dev);
4325 netif_carrier_off(tp->dev);
4326 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4328 tg3_link_report(tp);
4333 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4335 if (tp->serdes_counter) {
4336 /* Give autoneg time to complete. */
4337 tp->serdes_counter--;
4341 if (!netif_carrier_ok(tp->dev) &&
4342 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4345 tg3_readphy(tp, MII_BMCR, &bmcr);
4346 if (bmcr & BMCR_ANENABLE) {
4349 /* Select shadow register 0x1f */
4350 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4351 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4353 /* Select expansion interrupt status register */
4354 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4355 MII_TG3_DSP_EXP1_INT_STAT);
4356 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4357 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4359 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4360 /* We have signal detect and not receiving
4361 * config code words, link is up by parallel
4365 bmcr &= ~BMCR_ANENABLE;
4366 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4367 tg3_writephy(tp, MII_BMCR, bmcr);
4368 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4371 } else if (netif_carrier_ok(tp->dev) &&
4372 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4373 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4376 /* Select expansion interrupt status register */
4377 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4378 MII_TG3_DSP_EXP1_INT_STAT);
4379 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4383 /* Config code words received, turn on autoneg. */
4384 tg3_readphy(tp, MII_BMCR, &bmcr);
4385 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4387 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4393 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4397 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4398 err = tg3_setup_fiber_phy(tp, force_reset);
4399 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4400 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4402 err = tg3_setup_copper_phy(tp, force_reset);
4404 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4407 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4408 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4410 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4415 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4416 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4417 tw32(GRC_MISC_CFG, val);
4420 if (tp->link_config.active_speed == SPEED_1000 &&
4421 tp->link_config.active_duplex == DUPLEX_HALF)
4422 tw32(MAC_TX_LENGTHS,
4423 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4424 (6 << TX_LENGTHS_IPG_SHIFT) |
4425 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4427 tw32(MAC_TX_LENGTHS,
4428 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4429 (6 << TX_LENGTHS_IPG_SHIFT) |
4430 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4432 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4433 if (netif_carrier_ok(tp->dev)) {
4434 tw32(HOSTCC_STAT_COAL_TICKS,
4435 tp->coal.stats_block_coalesce_usecs);
4437 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4441 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4442 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4443 if (!netif_carrier_ok(tp->dev))
4444 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4447 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4448 tw32(PCIE_PWR_MGMT_THRESH, val);
4454 static inline int tg3_irq_sync(struct tg3 *tp)
4456 return tp->irq_sync;
4459 /* This is called whenever we suspect that the system chipset is re-
4460 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4461 * is bogus tx completions. We try to recover by setting the
4462 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4465 static void tg3_tx_recover(struct tg3 *tp)
4467 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4468 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4470 netdev_warn(tp->dev,
4471 "The system may be re-ordering memory-mapped I/O "
4472 "cycles to the network device, attempting to recover. "
4473 "Please report the problem to the driver maintainer "
4474 "and include system chipset information.\n");
4476 spin_lock(&tp->lock);
4477 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4478 spin_unlock(&tp->lock);
4481 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4483 /* Tell compiler to fetch tx indices from memory. */
4485 return tnapi->tx_pending -
4486 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4489 /* Tigon3 never reports partial packet sends. So we do not
4490 * need special logic to handle SKBs that have not had all
4491 * of their frags sent yet, like SunGEM does.
4493 static void tg3_tx(struct tg3_napi *tnapi)
4495 struct tg3 *tp = tnapi->tp;
4496 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4497 u32 sw_idx = tnapi->tx_cons;
4498 struct netdev_queue *txq;
4499 int index = tnapi - tp->napi;
4501 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4504 txq = netdev_get_tx_queue(tp->dev, index);
4506 while (sw_idx != hw_idx) {
4507 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4508 struct sk_buff *skb = ri->skb;
4511 if (unlikely(skb == NULL)) {
4516 pci_unmap_single(tp->pdev,
4517 dma_unmap_addr(ri, mapping),
4523 sw_idx = NEXT_TX(sw_idx);
4525 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4526 ri = &tnapi->tx_buffers[sw_idx];
4527 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4530 pci_unmap_page(tp->pdev,
4531 dma_unmap_addr(ri, mapping),
4532 skb_shinfo(skb)->frags[i].size,
4534 sw_idx = NEXT_TX(sw_idx);
4539 if (unlikely(tx_bug)) {
4545 tnapi->tx_cons = sw_idx;
4547 /* Need to make the tx_cons update visible to tg3_start_xmit()
4548 * before checking for netif_queue_stopped(). Without the
4549 * memory barrier, there is a small possibility that tg3_start_xmit()
4550 * will miss it and cause the queue to be stopped forever.
4554 if (unlikely(netif_tx_queue_stopped(txq) &&
4555 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4556 __netif_tx_lock(txq, smp_processor_id());
4557 if (netif_tx_queue_stopped(txq) &&
4558 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4559 netif_tx_wake_queue(txq);
4560 __netif_tx_unlock(txq);
4564 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4569 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4570 map_sz, PCI_DMA_FROMDEVICE);
4571 dev_kfree_skb_any(ri->skb);
4575 /* Returns size of skb allocated or < 0 on error.
4577 * We only need to fill in the address because the other members
4578 * of the RX descriptor are invariant, see tg3_init_rings.
4580 * Note the purposeful assymetry of cpu vs. chip accesses. For
4581 * posting buffers we only dirty the first cache line of the RX
4582 * descriptor (containing the address). Whereas for the RX status
4583 * buffers the cpu only reads the last cacheline of the RX descriptor
4584 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4586 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4587 u32 opaque_key, u32 dest_idx_unmasked)
4589 struct tg3_rx_buffer_desc *desc;
4590 struct ring_info *map;
4591 struct sk_buff *skb;
4593 int skb_size, dest_idx;
4595 switch (opaque_key) {
4596 case RXD_OPAQUE_RING_STD:
4597 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4598 desc = &tpr->rx_std[dest_idx];
4599 map = &tpr->rx_std_buffers[dest_idx];
4600 skb_size = tp->rx_pkt_map_sz;
4603 case RXD_OPAQUE_RING_JUMBO:
4604 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4605 desc = &tpr->rx_jmb[dest_idx].std;
4606 map = &tpr->rx_jmb_buffers[dest_idx];
4607 skb_size = TG3_RX_JMB_MAP_SZ;
4614 /* Do not overwrite any of the map or rp information
4615 * until we are sure we can commit to a new buffer.
4617 * Callers depend upon this behavior and assume that
4618 * we leave everything unchanged if we fail.
4620 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4624 skb_reserve(skb, tp->rx_offset);
4626 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4627 PCI_DMA_FROMDEVICE);
4628 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4634 dma_unmap_addr_set(map, mapping, mapping);
4636 desc->addr_hi = ((u64)mapping >> 32);
4637 desc->addr_lo = ((u64)mapping & 0xffffffff);
4642 /* We only need to move over in the address because the other
4643 * members of the RX descriptor are invariant. See notes above
4644 * tg3_alloc_rx_skb for full details.
4646 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4647 struct tg3_rx_prodring_set *dpr,
4648 u32 opaque_key, int src_idx,
4649 u32 dest_idx_unmasked)
4651 struct tg3 *tp = tnapi->tp;
4652 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4653 struct ring_info *src_map, *dest_map;
4654 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4657 switch (opaque_key) {
4658 case RXD_OPAQUE_RING_STD:
4659 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4660 dest_desc = &dpr->rx_std[dest_idx];
4661 dest_map = &dpr->rx_std_buffers[dest_idx];
4662 src_desc = &spr->rx_std[src_idx];
4663 src_map = &spr->rx_std_buffers[src_idx];
4666 case RXD_OPAQUE_RING_JUMBO:
4667 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4668 dest_desc = &dpr->rx_jmb[dest_idx].std;
4669 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4670 src_desc = &spr->rx_jmb[src_idx].std;
4671 src_map = &spr->rx_jmb_buffers[src_idx];
4678 dest_map->skb = src_map->skb;
4679 dma_unmap_addr_set(dest_map, mapping,
4680 dma_unmap_addr(src_map, mapping));
4681 dest_desc->addr_hi = src_desc->addr_hi;
4682 dest_desc->addr_lo = src_desc->addr_lo;
4684 /* Ensure that the update to the skb happens after the physical
4685 * addresses have been transferred to the new BD location.
4689 src_map->skb = NULL;
4692 /* The RX ring scheme is composed of multiple rings which post fresh
4693 * buffers to the chip, and one special ring the chip uses to report
4694 * status back to the host.
4696 * The special ring reports the status of received packets to the
4697 * host. The chip does not write into the original descriptor the
4698 * RX buffer was obtained from. The chip simply takes the original
4699 * descriptor as provided by the host, updates the status and length
4700 * field, then writes this into the next status ring entry.
4702 * Each ring the host uses to post buffers to the chip is described
4703 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4704 * it is first placed into the on-chip ram. When the packet's length
4705 * is known, it walks down the TG3_BDINFO entries to select the ring.
4706 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4707 * which is within the range of the new packet's length is chosen.
4709 * The "separate ring for rx status" scheme may sound queer, but it makes
4710 * sense from a cache coherency perspective. If only the host writes
4711 * to the buffer post rings, and only the chip writes to the rx status
4712 * rings, then cache lines never move beyond shared-modified state.
4713 * If both the host and chip were to write into the same ring, cache line
4714 * eviction could occur since both entities want it in an exclusive state.
4716 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4718 struct tg3 *tp = tnapi->tp;
4719 u32 work_mask, rx_std_posted = 0;
4720 u32 std_prod_idx, jmb_prod_idx;
4721 u32 sw_idx = tnapi->rx_rcb_ptr;
4724 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4726 hw_idx = *(tnapi->rx_rcb_prod_idx);
4728 * We need to order the read of hw_idx and the read of
4729 * the opaque cookie.
4734 std_prod_idx = tpr->rx_std_prod_idx;
4735 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4736 while (sw_idx != hw_idx && budget > 0) {
4737 struct ring_info *ri;
4738 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4740 struct sk_buff *skb;
4741 dma_addr_t dma_addr;
4742 u32 opaque_key, desc_idx, *post_ptr;
4744 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4745 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4746 if (opaque_key == RXD_OPAQUE_RING_STD) {
4747 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4748 dma_addr = dma_unmap_addr(ri, mapping);
4750 post_ptr = &std_prod_idx;
4752 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4753 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4754 dma_addr = dma_unmap_addr(ri, mapping);
4756 post_ptr = &jmb_prod_idx;
4758 goto next_pkt_nopost;
4760 work_mask |= opaque_key;
4762 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4763 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4765 tg3_recycle_rx(tnapi, tpr, opaque_key,
4766 desc_idx, *post_ptr);
4768 /* Other statistics kept track of by card. */
4773 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4776 if (len > TG3_RX_COPY_THRESH(tp)) {
4779 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4784 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4785 PCI_DMA_FROMDEVICE);
4787 /* Ensure that the update to the skb happens
4788 * after the usage of the old DMA mapping.
4796 struct sk_buff *copy_skb;
4798 tg3_recycle_rx(tnapi, tpr, opaque_key,
4799 desc_idx, *post_ptr);
4801 copy_skb = netdev_alloc_skb(tp->dev, len +
4803 if (copy_skb == NULL)
4804 goto drop_it_no_recycle;
4806 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4807 skb_put(copy_skb, len);
4808 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4809 skb_copy_from_linear_data(skb, copy_skb->data, len);
4810 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4812 /* We'll reuse the original ring buffer. */
4816 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4817 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4818 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4819 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4820 skb->ip_summed = CHECKSUM_UNNECESSARY;
4822 skb_checksum_none_assert(skb);
4824 skb->protocol = eth_type_trans(skb, tp->dev);
4826 if (len > (tp->dev->mtu + ETH_HLEN) &&
4827 skb->protocol != htons(ETH_P_8021Q)) {
4829 goto drop_it_no_recycle;
4832 if (desc->type_flags & RXD_FLAG_VLAN &&
4833 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4834 __vlan_hwaccel_put_tag(skb,
4835 desc->err_vlan & RXD_VLAN_MASK);
4837 napi_gro_receive(&tnapi->napi, skb);
4845 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4846 tpr->rx_std_prod_idx = std_prod_idx &
4847 tp->rx_std_ring_mask;
4848 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4849 tpr->rx_std_prod_idx);
4850 work_mask &= ~RXD_OPAQUE_RING_STD;
4855 sw_idx &= tp->rx_ret_ring_mask;
4857 /* Refresh hw_idx to see if there is new work */
4858 if (sw_idx == hw_idx) {
4859 hw_idx = *(tnapi->rx_rcb_prod_idx);
4864 /* ACK the status ring. */
4865 tnapi->rx_rcb_ptr = sw_idx;
4866 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4868 /* Refill RX ring(s). */
4869 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4870 if (work_mask & RXD_OPAQUE_RING_STD) {
4871 tpr->rx_std_prod_idx = std_prod_idx &
4872 tp->rx_std_ring_mask;
4873 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4874 tpr->rx_std_prod_idx);
4876 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4877 tpr->rx_jmb_prod_idx = jmb_prod_idx &
4878 tp->rx_jmb_ring_mask;
4879 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4880 tpr->rx_jmb_prod_idx);
4883 } else if (work_mask) {
4884 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4885 * updated before the producer indices can be updated.
4889 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4890 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4892 if (tnapi != &tp->napi[1])
4893 napi_schedule(&tp->napi[1].napi);
4899 static void tg3_poll_link(struct tg3 *tp)
4901 /* handle link change and other phy events */
4902 if (!(tp->tg3_flags &
4903 (TG3_FLAG_USE_LINKCHG_REG |
4904 TG3_FLAG_POLL_SERDES))) {
4905 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4907 if (sblk->status & SD_STATUS_LINK_CHG) {
4908 sblk->status = SD_STATUS_UPDATED |
4909 (sblk->status & ~SD_STATUS_LINK_CHG);
4910 spin_lock(&tp->lock);
4911 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4913 (MAC_STATUS_SYNC_CHANGED |
4914 MAC_STATUS_CFG_CHANGED |
4915 MAC_STATUS_MI_COMPLETION |
4916 MAC_STATUS_LNKSTATE_CHANGED));
4919 tg3_setup_phy(tp, 0);
4920 spin_unlock(&tp->lock);
4925 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4926 struct tg3_rx_prodring_set *dpr,
4927 struct tg3_rx_prodring_set *spr)
4929 u32 si, di, cpycnt, src_prod_idx;
4933 src_prod_idx = spr->rx_std_prod_idx;
4935 /* Make sure updates to the rx_std_buffers[] entries and the
4936 * standard producer index are seen in the correct order.
4940 if (spr->rx_std_cons_idx == src_prod_idx)
4943 if (spr->rx_std_cons_idx < src_prod_idx)
4944 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4946 cpycnt = tp->rx_std_ring_mask + 1 -
4947 spr->rx_std_cons_idx;
4949 cpycnt = min(cpycnt,
4950 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4952 si = spr->rx_std_cons_idx;
4953 di = dpr->rx_std_prod_idx;
4955 for (i = di; i < di + cpycnt; i++) {
4956 if (dpr->rx_std_buffers[i].skb) {
4966 /* Ensure that updates to the rx_std_buffers ring and the
4967 * shadowed hardware producer ring from tg3_recycle_skb() are
4968 * ordered correctly WRT the skb check above.
4972 memcpy(&dpr->rx_std_buffers[di],
4973 &spr->rx_std_buffers[si],
4974 cpycnt * sizeof(struct ring_info));
4976 for (i = 0; i < cpycnt; i++, di++, si++) {
4977 struct tg3_rx_buffer_desc *sbd, *dbd;
4978 sbd = &spr->rx_std[si];
4979 dbd = &dpr->rx_std[di];
4980 dbd->addr_hi = sbd->addr_hi;
4981 dbd->addr_lo = sbd->addr_lo;
4984 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4985 tp->rx_std_ring_mask;
4986 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4987 tp->rx_std_ring_mask;
4991 src_prod_idx = spr->rx_jmb_prod_idx;
4993 /* Make sure updates to the rx_jmb_buffers[] entries and
4994 * the jumbo producer index are seen in the correct order.
4998 if (spr->rx_jmb_cons_idx == src_prod_idx)
5001 if (spr->rx_jmb_cons_idx < src_prod_idx)
5002 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5004 cpycnt = tp->rx_jmb_ring_mask + 1 -
5005 spr->rx_jmb_cons_idx;
5007 cpycnt = min(cpycnt,
5008 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5010 si = spr->rx_jmb_cons_idx;
5011 di = dpr->rx_jmb_prod_idx;
5013 for (i = di; i < di + cpycnt; i++) {
5014 if (dpr->rx_jmb_buffers[i].skb) {
5024 /* Ensure that updates to the rx_jmb_buffers ring and the
5025 * shadowed hardware producer ring from tg3_recycle_skb() are
5026 * ordered correctly WRT the skb check above.
5030 memcpy(&dpr->rx_jmb_buffers[di],
5031 &spr->rx_jmb_buffers[si],
5032 cpycnt * sizeof(struct ring_info));
5034 for (i = 0; i < cpycnt; i++, di++, si++) {
5035 struct tg3_rx_buffer_desc *sbd, *dbd;
5036 sbd = &spr->rx_jmb[si].std;
5037 dbd = &dpr->rx_jmb[di].std;
5038 dbd->addr_hi = sbd->addr_hi;
5039 dbd->addr_lo = sbd->addr_lo;
5042 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5043 tp->rx_jmb_ring_mask;
5044 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5045 tp->rx_jmb_ring_mask;
5051 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5053 struct tg3 *tp = tnapi->tp;
5055 /* run TX completion thread */
5056 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5058 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5062 /* run RX thread, within the bounds set by NAPI.
5063 * All RX "locking" is done by ensuring outside
5064 * code synchronizes with tg3->napi.poll()
5066 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5067 work_done += tg3_rx(tnapi, budget - work_done);
5069 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5070 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5072 u32 std_prod_idx = dpr->rx_std_prod_idx;
5073 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5075 for (i = 1; i < tp->irq_cnt; i++)
5076 err |= tg3_rx_prodring_xfer(tp, dpr,
5077 &tp->napi[i].prodring);
5081 if (std_prod_idx != dpr->rx_std_prod_idx)
5082 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5083 dpr->rx_std_prod_idx);
5085 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5086 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5087 dpr->rx_jmb_prod_idx);
5092 tw32_f(HOSTCC_MODE, tp->coal_now);
5098 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5100 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5101 struct tg3 *tp = tnapi->tp;
5103 struct tg3_hw_status *sblk = tnapi->hw_status;
5106 work_done = tg3_poll_work(tnapi, work_done, budget);
5108 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5111 if (unlikely(work_done >= budget))
5114 /* tp->last_tag is used in tg3_int_reenable() below
5115 * to tell the hw how much work has been processed,
5116 * so we must read it before checking for more work.
5118 tnapi->last_tag = sblk->status_tag;
5119 tnapi->last_irq_tag = tnapi->last_tag;
5122 /* check for RX/TX work to do */
5123 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5124 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5125 napi_complete(napi);
5126 /* Reenable interrupts. */
5127 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5136 /* work_done is guaranteed to be less than budget. */
5137 napi_complete(napi);
5138 schedule_work(&tp->reset_task);
5142 static int tg3_poll(struct napi_struct *napi, int budget)
5144 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5145 struct tg3 *tp = tnapi->tp;
5147 struct tg3_hw_status *sblk = tnapi->hw_status;
5152 work_done = tg3_poll_work(tnapi, work_done, budget);
5154 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5157 if (unlikely(work_done >= budget))
5160 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5161 /* tp->last_tag is used in tg3_int_reenable() below
5162 * to tell the hw how much work has been processed,
5163 * so we must read it before checking for more work.
5165 tnapi->last_tag = sblk->status_tag;
5166 tnapi->last_irq_tag = tnapi->last_tag;
5169 sblk->status &= ~SD_STATUS_UPDATED;
5171 if (likely(!tg3_has_work(tnapi))) {
5172 napi_complete(napi);
5173 tg3_int_reenable(tnapi);
5181 /* work_done is guaranteed to be less than budget. */
5182 napi_complete(napi);
5183 schedule_work(&tp->reset_task);
5187 static void tg3_napi_disable(struct tg3 *tp)
5191 for (i = tp->irq_cnt - 1; i >= 0; i--)
5192 napi_disable(&tp->napi[i].napi);
5195 static void tg3_napi_enable(struct tg3 *tp)
5199 for (i = 0; i < tp->irq_cnt; i++)
5200 napi_enable(&tp->napi[i].napi);
5203 static void tg3_napi_init(struct tg3 *tp)
5207 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5208 for (i = 1; i < tp->irq_cnt; i++)
5209 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5212 static void tg3_napi_fini(struct tg3 *tp)
5216 for (i = 0; i < tp->irq_cnt; i++)
5217 netif_napi_del(&tp->napi[i].napi);
5220 static inline void tg3_netif_stop(struct tg3 *tp)
5222 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5223 tg3_napi_disable(tp);
5224 netif_tx_disable(tp->dev);
5227 static inline void tg3_netif_start(struct tg3 *tp)
5229 /* NOTE: unconditional netif_tx_wake_all_queues is only
5230 * appropriate so long as all callers are assured to
5231 * have free tx slots (such as after tg3_init_hw)
5233 netif_tx_wake_all_queues(tp->dev);
5235 tg3_napi_enable(tp);
5236 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5237 tg3_enable_ints(tp);
5240 static void tg3_irq_quiesce(struct tg3 *tp)
5244 BUG_ON(tp->irq_sync);
5249 for (i = 0; i < tp->irq_cnt; i++)
5250 synchronize_irq(tp->napi[i].irq_vec);
5253 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5254 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5255 * with as well. Most of the time, this is not necessary except when
5256 * shutting down the device.
5258 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5260 spin_lock_bh(&tp->lock);
5262 tg3_irq_quiesce(tp);
5265 static inline void tg3_full_unlock(struct tg3 *tp)
5267 spin_unlock_bh(&tp->lock);
5270 /* One-shot MSI handler - Chip automatically disables interrupt
5271 * after sending MSI so driver doesn't have to do it.
5273 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5275 struct tg3_napi *tnapi = dev_id;
5276 struct tg3 *tp = tnapi->tp;
5278 prefetch(tnapi->hw_status);
5280 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5282 if (likely(!tg3_irq_sync(tp)))
5283 napi_schedule(&tnapi->napi);
5288 /* MSI ISR - No need to check for interrupt sharing and no need to
5289 * flush status block and interrupt mailbox. PCI ordering rules
5290 * guarantee that MSI will arrive after the status block.
5292 static irqreturn_t tg3_msi(int irq, void *dev_id)
5294 struct tg3_napi *tnapi = dev_id;
5295 struct tg3 *tp = tnapi->tp;
5297 prefetch(tnapi->hw_status);
5299 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5301 * Writing any value to intr-mbox-0 clears PCI INTA# and
5302 * chip-internal interrupt pending events.
5303 * Writing non-zero to intr-mbox-0 additional tells the
5304 * NIC to stop sending us irqs, engaging "in-intr-handler"
5307 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5308 if (likely(!tg3_irq_sync(tp)))
5309 napi_schedule(&tnapi->napi);
5311 return IRQ_RETVAL(1);
5314 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5316 struct tg3_napi *tnapi = dev_id;
5317 struct tg3 *tp = tnapi->tp;
5318 struct tg3_hw_status *sblk = tnapi->hw_status;
5319 unsigned int handled = 1;
5321 /* In INTx mode, it is possible for the interrupt to arrive at
5322 * the CPU before the status block posted prior to the interrupt.
5323 * Reading the PCI State register will confirm whether the
5324 * interrupt is ours and will flush the status block.
5326 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5327 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5328 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5335 * Writing any value to intr-mbox-0 clears PCI INTA# and
5336 * chip-internal interrupt pending events.
5337 * Writing non-zero to intr-mbox-0 additional tells the
5338 * NIC to stop sending us irqs, engaging "in-intr-handler"
5341 * Flush the mailbox to de-assert the IRQ immediately to prevent
5342 * spurious interrupts. The flush impacts performance but
5343 * excessive spurious interrupts can be worse in some cases.
5345 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5346 if (tg3_irq_sync(tp))
5348 sblk->status &= ~SD_STATUS_UPDATED;
5349 if (likely(tg3_has_work(tnapi))) {
5350 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5351 napi_schedule(&tnapi->napi);
5353 /* No work, shared interrupt perhaps? re-enable
5354 * interrupts, and flush that PCI write
5356 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5360 return IRQ_RETVAL(handled);
5363 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5365 struct tg3_napi *tnapi = dev_id;
5366 struct tg3 *tp = tnapi->tp;
5367 struct tg3_hw_status *sblk = tnapi->hw_status;
5368 unsigned int handled = 1;
5370 /* In INTx mode, it is possible for the interrupt to arrive at
5371 * the CPU before the status block posted prior to the interrupt.
5372 * Reading the PCI State register will confirm whether the
5373 * interrupt is ours and will flush the status block.
5375 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5376 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5377 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5384 * writing any value to intr-mbox-0 clears PCI INTA# and
5385 * chip-internal interrupt pending events.
5386 * writing non-zero to intr-mbox-0 additional tells the
5387 * NIC to stop sending us irqs, engaging "in-intr-handler"
5390 * Flush the mailbox to de-assert the IRQ immediately to prevent
5391 * spurious interrupts. The flush impacts performance but
5392 * excessive spurious interrupts can be worse in some cases.
5394 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5397 * In a shared interrupt configuration, sometimes other devices'
5398 * interrupts will scream. We record the current status tag here
5399 * so that the above check can report that the screaming interrupts
5400 * are unhandled. Eventually they will be silenced.
5402 tnapi->last_irq_tag = sblk->status_tag;
5404 if (tg3_irq_sync(tp))
5407 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5409 napi_schedule(&tnapi->napi);
5412 return IRQ_RETVAL(handled);
5415 /* ISR for interrupt test */
5416 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5418 struct tg3_napi *tnapi = dev_id;
5419 struct tg3 *tp = tnapi->tp;
5420 struct tg3_hw_status *sblk = tnapi->hw_status;
5422 if ((sblk->status & SD_STATUS_UPDATED) ||
5423 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5424 tg3_disable_ints(tp);
5425 return IRQ_RETVAL(1);
5427 return IRQ_RETVAL(0);
5430 static int tg3_init_hw(struct tg3 *, int);
5431 static int tg3_halt(struct tg3 *, int, int);
5433 /* Restart hardware after configuration changes, self-test, etc.
5434 * Invoked with tp->lock held.
5436 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5437 __releases(tp->lock)
5438 __acquires(tp->lock)
5442 err = tg3_init_hw(tp, reset_phy);
5445 "Failed to re-initialize device, aborting\n");
5446 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5447 tg3_full_unlock(tp);
5448 del_timer_sync(&tp->timer);
5450 tg3_napi_enable(tp);
5452 tg3_full_lock(tp, 0);
5457 #ifdef CONFIG_NET_POLL_CONTROLLER
5458 static void tg3_poll_controller(struct net_device *dev)
5461 struct tg3 *tp = netdev_priv(dev);
5463 for (i = 0; i < tp->irq_cnt; i++)
5464 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5468 static void tg3_reset_task(struct work_struct *work)
5470 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5472 unsigned int restart_timer;
5474 tg3_full_lock(tp, 0);
5476 if (!netif_running(tp->dev)) {
5477 tg3_full_unlock(tp);
5481 tg3_full_unlock(tp);
5487 tg3_full_lock(tp, 1);
5489 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5490 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5492 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5493 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5494 tp->write32_rx_mbox = tg3_write_flush_reg32;
5495 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5496 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5499 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5500 err = tg3_init_hw(tp, 1);
5504 tg3_netif_start(tp);
5507 mod_timer(&tp->timer, jiffies + 1);
5510 tg3_full_unlock(tp);
5516 static void tg3_dump_short_state(struct tg3 *tp)
5518 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5519 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5520 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5521 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5524 static void tg3_tx_timeout(struct net_device *dev)
5526 struct tg3 *tp = netdev_priv(dev);
5528 if (netif_msg_tx_err(tp)) {
5529 netdev_err(dev, "transmit timed out, resetting\n");
5530 tg3_dump_short_state(tp);
5533 schedule_work(&tp->reset_task);
5536 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5537 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5539 u32 base = (u32) mapping & 0xffffffff;
5541 return (base > 0xffffdcc0) && (base + len + 8 < base);
5544 /* Test for DMA addresses > 40-bit */
5545 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5548 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5549 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5550 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5557 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5559 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5560 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5561 struct sk_buff *skb, u32 last_plus_one,
5562 u32 *start, u32 base_flags, u32 mss)
5564 struct tg3 *tp = tnapi->tp;
5565 struct sk_buff *new_skb;
5566 dma_addr_t new_addr = 0;
5570 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5571 new_skb = skb_copy(skb, GFP_ATOMIC);
5573 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5575 new_skb = skb_copy_expand(skb,
5576 skb_headroom(skb) + more_headroom,
5577 skb_tailroom(skb), GFP_ATOMIC);
5583 /* New SKB is guaranteed to be linear. */
5585 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5587 /* Make sure the mapping succeeded */
5588 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5590 dev_kfree_skb(new_skb);
5593 /* Make sure new skb does not cross any 4G boundaries.
5594 * Drop the packet if it does.
5596 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5597 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5598 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5601 dev_kfree_skb(new_skb);
5604 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5605 base_flags, 1 | (mss << 1));
5606 *start = NEXT_TX(entry);
5610 /* Now clean up the sw ring entries. */
5612 while (entry != last_plus_one) {
5616 len = skb_headlen(skb);
5618 len = skb_shinfo(skb)->frags[i-1].size;
5620 pci_unmap_single(tp->pdev,
5621 dma_unmap_addr(&tnapi->tx_buffers[entry],
5623 len, PCI_DMA_TODEVICE);
5625 tnapi->tx_buffers[entry].skb = new_skb;
5626 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5629 tnapi->tx_buffers[entry].skb = NULL;
5631 entry = NEXT_TX(entry);
5640 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5641 dma_addr_t mapping, int len, u32 flags,
5644 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5645 int is_end = (mss_and_is_end & 0x1);
5646 u32 mss = (mss_and_is_end >> 1);
5650 flags |= TXD_FLAG_END;
5651 if (flags & TXD_FLAG_VLAN) {
5652 vlan_tag = flags >> 16;
5655 vlan_tag |= (mss << TXD_MSS_SHIFT);
5657 txd->addr_hi = ((u64) mapping >> 32);
5658 txd->addr_lo = ((u64) mapping & 0xffffffff);
5659 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5660 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5663 /* hard_start_xmit for devices that don't have any bugs and
5664 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5666 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5667 struct net_device *dev)
5669 struct tg3 *tp = netdev_priv(dev);
5670 u32 len, entry, base_flags, mss;
5672 struct tg3_napi *tnapi;
5673 struct netdev_queue *txq;
5674 unsigned int i, last;
5676 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5677 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5678 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5681 /* We are running in BH disabled context with netif_tx_lock
5682 * and TX reclaim runs via tp->napi.poll inside of a software
5683 * interrupt. Furthermore, IRQ processing runs lockless so we have
5684 * no IRQ context deadlocks to worry about either. Rejoice!
5686 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5687 if (!netif_tx_queue_stopped(txq)) {
5688 netif_tx_stop_queue(txq);
5690 /* This is a hard error, log it. */
5692 "BUG! Tx Ring full when queue awake!\n");
5694 return NETDEV_TX_BUSY;
5697 entry = tnapi->tx_prod;
5699 mss = skb_shinfo(skb)->gso_size;
5701 int tcp_opt_len, ip_tcp_len;
5704 if (skb_header_cloned(skb) &&
5705 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5710 if (skb_is_gso_v6(skb)) {
5711 hdrlen = skb_headlen(skb) - ETH_HLEN;
5713 struct iphdr *iph = ip_hdr(skb);
5715 tcp_opt_len = tcp_optlen(skb);
5716 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5719 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5720 hdrlen = ip_tcp_len + tcp_opt_len;
5723 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5724 mss |= (hdrlen & 0xc) << 12;
5726 base_flags |= 0x00000010;
5727 base_flags |= (hdrlen & 0x3e0) << 5;
5731 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5732 TXD_FLAG_CPU_POST_DMA);
5734 tcp_hdr(skb)->check = 0;
5736 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5737 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5740 if (vlan_tx_tag_present(skb))
5741 base_flags |= (TXD_FLAG_VLAN |
5742 (vlan_tx_tag_get(skb) << 16));
5744 len = skb_headlen(skb);
5746 /* Queue skb data, a.k.a. the main skb fragment. */
5747 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5748 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5753 tnapi->tx_buffers[entry].skb = skb;
5754 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5756 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5757 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5758 base_flags |= TXD_FLAG_JMB_PKT;
5760 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5761 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5763 entry = NEXT_TX(entry);
5765 /* Now loop through additional data fragments, and queue them. */
5766 if (skb_shinfo(skb)->nr_frags > 0) {
5767 last = skb_shinfo(skb)->nr_frags - 1;
5768 for (i = 0; i <= last; i++) {
5769 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5772 mapping = pci_map_page(tp->pdev,
5775 len, PCI_DMA_TODEVICE);
5776 if (pci_dma_mapping_error(tp->pdev, mapping))
5779 tnapi->tx_buffers[entry].skb = NULL;
5780 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5783 tg3_set_txd(tnapi, entry, mapping, len,
5784 base_flags, (i == last) | (mss << 1));
5786 entry = NEXT_TX(entry);
5790 /* Packets are ready, update Tx producer idx local and on card. */
5791 tw32_tx_mbox(tnapi->prodmbox, entry);
5793 tnapi->tx_prod = entry;
5794 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5795 netif_tx_stop_queue(txq);
5797 /* netif_tx_stop_queue() must be done before checking
5798 * checking tx index in tg3_tx_avail() below, because in
5799 * tg3_tx(), we update tx index before checking for
5800 * netif_tx_queue_stopped().
5803 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5804 netif_tx_wake_queue(txq);
5810 return NETDEV_TX_OK;
5814 entry = tnapi->tx_prod;
5815 tnapi->tx_buffers[entry].skb = NULL;
5816 pci_unmap_single(tp->pdev,
5817 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5820 for (i = 0; i <= last; i++) {
5821 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5822 entry = NEXT_TX(entry);
5824 pci_unmap_page(tp->pdev,
5825 dma_unmap_addr(&tnapi->tx_buffers[entry],
5827 frag->size, PCI_DMA_TODEVICE);
5831 return NETDEV_TX_OK;
5834 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5835 struct net_device *);
5837 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5838 * TSO header is greater than 80 bytes.
5840 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5842 struct sk_buff *segs, *nskb;
5843 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5845 /* Estimate the number of fragments in the worst case */
5846 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5847 netif_stop_queue(tp->dev);
5849 /* netif_tx_stop_queue() must be done before checking
5850 * checking tx index in tg3_tx_avail() below, because in
5851 * tg3_tx(), we update tx index before checking for
5852 * netif_tx_queue_stopped().
5855 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5856 return NETDEV_TX_BUSY;
5858 netif_wake_queue(tp->dev);
5861 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5863 goto tg3_tso_bug_end;
5869 tg3_start_xmit_dma_bug(nskb, tp->dev);
5875 return NETDEV_TX_OK;
5878 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5879 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5881 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5882 struct net_device *dev)
5884 struct tg3 *tp = netdev_priv(dev);
5885 u32 len, entry, base_flags, mss;
5886 int would_hit_hwbug;
5888 struct tg3_napi *tnapi;
5889 struct netdev_queue *txq;
5890 unsigned int i, last;
5892 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5893 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5894 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5897 /* We are running in BH disabled context with netif_tx_lock
5898 * and TX reclaim runs via tp->napi.poll inside of a software
5899 * interrupt. Furthermore, IRQ processing runs lockless so we have
5900 * no IRQ context deadlocks to worry about either. Rejoice!
5902 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5903 if (!netif_tx_queue_stopped(txq)) {
5904 netif_tx_stop_queue(txq);
5906 /* This is a hard error, log it. */
5908 "BUG! Tx Ring full when queue awake!\n");
5910 return NETDEV_TX_BUSY;
5913 entry = tnapi->tx_prod;
5915 if (skb->ip_summed == CHECKSUM_PARTIAL)
5916 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5918 mss = skb_shinfo(skb)->gso_size;
5921 u32 tcp_opt_len, hdr_len;
5923 if (skb_header_cloned(skb) &&
5924 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5930 tcp_opt_len = tcp_optlen(skb);
5932 if (skb_is_gso_v6(skb)) {
5933 hdr_len = skb_headlen(skb) - ETH_HLEN;
5937 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5938 hdr_len = ip_tcp_len + tcp_opt_len;
5941 iph->tot_len = htons(mss + hdr_len);
5944 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5945 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5946 return tg3_tso_bug(tp, skb);
5948 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5949 TXD_FLAG_CPU_POST_DMA);
5951 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5952 tcp_hdr(skb)->check = 0;
5953 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5955 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5960 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5961 mss |= (hdr_len & 0xc) << 12;
5963 base_flags |= 0x00000010;
5964 base_flags |= (hdr_len & 0x3e0) << 5;
5965 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5966 mss |= hdr_len << 9;
5967 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5968 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5969 if (tcp_opt_len || iph->ihl > 5) {
5972 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5973 mss |= (tsflags << 11);
5976 if (tcp_opt_len || iph->ihl > 5) {
5979 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5980 base_flags |= tsflags << 12;
5985 if (vlan_tx_tag_present(skb))
5986 base_flags |= (TXD_FLAG_VLAN |
5987 (vlan_tx_tag_get(skb) << 16));
5989 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5990 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5991 base_flags |= TXD_FLAG_JMB_PKT;
5993 len = skb_headlen(skb);
5995 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5996 if (pci_dma_mapping_error(tp->pdev, mapping)) {
6001 tnapi->tx_buffers[entry].skb = skb;
6002 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6004 would_hit_hwbug = 0;
6006 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6007 would_hit_hwbug = 1;
6009 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6010 tg3_4g_overflow_test(mapping, len))
6011 would_hit_hwbug = 1;
6013 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6014 tg3_40bit_overflow_test(tp, mapping, len))
6015 would_hit_hwbug = 1;
6017 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6018 would_hit_hwbug = 1;
6020 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6021 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6023 entry = NEXT_TX(entry);
6025 /* Now loop through additional data fragments, and queue them. */
6026 if (skb_shinfo(skb)->nr_frags > 0) {
6027 last = skb_shinfo(skb)->nr_frags - 1;
6028 for (i = 0; i <= last; i++) {
6029 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6032 mapping = pci_map_page(tp->pdev,
6035 len, PCI_DMA_TODEVICE);
6037 tnapi->tx_buffers[entry].skb = NULL;
6038 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6040 if (pci_dma_mapping_error(tp->pdev, mapping))
6043 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6045 would_hit_hwbug = 1;
6047 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6048 tg3_4g_overflow_test(mapping, len))
6049 would_hit_hwbug = 1;
6051 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6052 tg3_40bit_overflow_test(tp, mapping, len))
6053 would_hit_hwbug = 1;
6055 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6056 tg3_set_txd(tnapi, entry, mapping, len,
6057 base_flags, (i == last)|(mss << 1));
6059 tg3_set_txd(tnapi, entry, mapping, len,
6060 base_flags, (i == last));
6062 entry = NEXT_TX(entry);
6066 if (would_hit_hwbug) {
6067 u32 last_plus_one = entry;
6070 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6071 start &= (TG3_TX_RING_SIZE - 1);
6073 /* If the workaround fails due to memory/mapping
6074 * failure, silently drop this packet.
6076 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6077 &start, base_flags, mss))
6083 /* Packets are ready, update Tx producer idx local and on card. */
6084 tw32_tx_mbox(tnapi->prodmbox, entry);
6086 tnapi->tx_prod = entry;
6087 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6088 netif_tx_stop_queue(txq);
6090 /* netif_tx_stop_queue() must be done before checking
6091 * checking tx index in tg3_tx_avail() below, because in
6092 * tg3_tx(), we update tx index before checking for
6093 * netif_tx_queue_stopped().
6096 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6097 netif_tx_wake_queue(txq);
6103 return NETDEV_TX_OK;
6107 entry = tnapi->tx_prod;
6108 tnapi->tx_buffers[entry].skb = NULL;
6109 pci_unmap_single(tp->pdev,
6110 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6113 for (i = 0; i <= last; i++) {
6114 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6115 entry = NEXT_TX(entry);
6117 pci_unmap_page(tp->pdev,
6118 dma_unmap_addr(&tnapi->tx_buffers[entry],
6120 frag->size, PCI_DMA_TODEVICE);
6124 return NETDEV_TX_OK;
6127 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6132 if (new_mtu > ETH_DATA_LEN) {
6133 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6134 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6135 ethtool_op_set_tso(dev, 0);
6137 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6140 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6141 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6142 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6146 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6148 struct tg3 *tp = netdev_priv(dev);
6151 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6154 if (!netif_running(dev)) {
6155 /* We'll just catch it later when the
6158 tg3_set_mtu(dev, tp, new_mtu);
6166 tg3_full_lock(tp, 1);
6168 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6170 tg3_set_mtu(dev, tp, new_mtu);
6172 err = tg3_restart_hw(tp, 0);
6175 tg3_netif_start(tp);
6177 tg3_full_unlock(tp);
6185 static void tg3_rx_prodring_free(struct tg3 *tp,
6186 struct tg3_rx_prodring_set *tpr)
6190 if (tpr != &tp->napi[0].prodring) {
6191 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6192 i = (i + 1) & tp->rx_std_ring_mask)
6193 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6196 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6197 for (i = tpr->rx_jmb_cons_idx;
6198 i != tpr->rx_jmb_prod_idx;
6199 i = (i + 1) & tp->rx_jmb_ring_mask) {
6200 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6208 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6209 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6212 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6213 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6214 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6215 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6220 /* Initialize rx rings for packet processing.
6222 * The chip has been shut down and the driver detached from
6223 * the networking, so no interrupts or new tx packets will
6224 * end up in the driver. tp->{tx,}lock are held and thus
6227 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6228 struct tg3_rx_prodring_set *tpr)
6230 u32 i, rx_pkt_dma_sz;
6232 tpr->rx_std_cons_idx = 0;
6233 tpr->rx_std_prod_idx = 0;
6234 tpr->rx_jmb_cons_idx = 0;
6235 tpr->rx_jmb_prod_idx = 0;
6237 if (tpr != &tp->napi[0].prodring) {
6238 memset(&tpr->rx_std_buffers[0], 0,
6239 TG3_RX_STD_BUFF_RING_SIZE(tp));
6240 if (tpr->rx_jmb_buffers)
6241 memset(&tpr->rx_jmb_buffers[0], 0,
6242 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6246 /* Zero out all descriptors. */
6247 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6249 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6250 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6251 tp->dev->mtu > ETH_DATA_LEN)
6252 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6253 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6255 /* Initialize invariants of the rings, we only set this
6256 * stuff once. This works because the card does not
6257 * write into the rx buffer posting rings.
6259 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6260 struct tg3_rx_buffer_desc *rxd;
6262 rxd = &tpr->rx_std[i];
6263 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6264 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6265 rxd->opaque = (RXD_OPAQUE_RING_STD |
6266 (i << RXD_OPAQUE_INDEX_SHIFT));
6269 /* Now allocate fresh SKBs for each rx ring. */
6270 for (i = 0; i < tp->rx_pending; i++) {
6271 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6272 netdev_warn(tp->dev,
6273 "Using a smaller RX standard ring. Only "
6274 "%d out of %d buffers were allocated "
6275 "successfully\n", i, tp->rx_pending);
6283 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6284 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6287 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6289 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6292 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6293 struct tg3_rx_buffer_desc *rxd;
6295 rxd = &tpr->rx_jmb[i].std;
6296 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6297 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6299 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6300 (i << RXD_OPAQUE_INDEX_SHIFT));
6303 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6304 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6305 netdev_warn(tp->dev,
6306 "Using a smaller RX jumbo ring. Only %d "
6307 "out of %d buffers were allocated "
6308 "successfully\n", i, tp->rx_jumbo_pending);
6311 tp->rx_jumbo_pending = i;
6320 tg3_rx_prodring_free(tp, tpr);
6324 static void tg3_rx_prodring_fini(struct tg3 *tp,
6325 struct tg3_rx_prodring_set *tpr)
6327 kfree(tpr->rx_std_buffers);
6328 tpr->rx_std_buffers = NULL;
6329 kfree(tpr->rx_jmb_buffers);
6330 tpr->rx_jmb_buffers = NULL;
6332 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6333 tpr->rx_std, tpr->rx_std_mapping);
6337 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6338 tpr->rx_jmb, tpr->rx_jmb_mapping);
6343 static int tg3_rx_prodring_init(struct tg3 *tp,
6344 struct tg3_rx_prodring_set *tpr)
6346 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6348 if (!tpr->rx_std_buffers)
6351 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6352 TG3_RX_STD_RING_BYTES(tp),
6353 &tpr->rx_std_mapping,
6358 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6359 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6360 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6362 if (!tpr->rx_jmb_buffers)
6365 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6366 TG3_RX_JMB_RING_BYTES(tp),
6367 &tpr->rx_jmb_mapping,
6376 tg3_rx_prodring_fini(tp, tpr);
6380 /* Free up pending packets in all rx/tx rings.
6382 * The chip has been shut down and the driver detached from
6383 * the networking, so no interrupts or new tx packets will
6384 * end up in the driver. tp->{tx,}lock is not held and we are not
6385 * in an interrupt context and thus may sleep.
6387 static void tg3_free_rings(struct tg3 *tp)
6391 for (j = 0; j < tp->irq_cnt; j++) {
6392 struct tg3_napi *tnapi = &tp->napi[j];
6394 tg3_rx_prodring_free(tp, &tnapi->prodring);
6396 if (!tnapi->tx_buffers)
6399 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6400 struct ring_info *txp;
6401 struct sk_buff *skb;
6404 txp = &tnapi->tx_buffers[i];
6412 pci_unmap_single(tp->pdev,
6413 dma_unmap_addr(txp, mapping),
6420 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6421 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6422 pci_unmap_page(tp->pdev,
6423 dma_unmap_addr(txp, mapping),
6424 skb_shinfo(skb)->frags[k].size,
6429 dev_kfree_skb_any(skb);
6434 /* Initialize tx/rx rings for packet processing.
6436 * The chip has been shut down and the driver detached from
6437 * the networking, so no interrupts or new tx packets will
6438 * end up in the driver. tp->{tx,}lock are held and thus
6441 static int tg3_init_rings(struct tg3 *tp)
6445 /* Free up all the SKBs. */
6448 for (i = 0; i < tp->irq_cnt; i++) {
6449 struct tg3_napi *tnapi = &tp->napi[i];
6451 tnapi->last_tag = 0;
6452 tnapi->last_irq_tag = 0;
6453 tnapi->hw_status->status = 0;
6454 tnapi->hw_status->status_tag = 0;
6455 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6460 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6462 tnapi->rx_rcb_ptr = 0;
6464 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6466 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6476 * Must not be invoked with interrupt sources disabled and
6477 * the hardware shutdown down.
6479 static void tg3_free_consistent(struct tg3 *tp)
6483 for (i = 0; i < tp->irq_cnt; i++) {
6484 struct tg3_napi *tnapi = &tp->napi[i];
6486 if (tnapi->tx_ring) {
6487 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6488 tnapi->tx_ring, tnapi->tx_desc_mapping);
6489 tnapi->tx_ring = NULL;
6492 kfree(tnapi->tx_buffers);
6493 tnapi->tx_buffers = NULL;
6495 if (tnapi->rx_rcb) {
6496 dma_free_coherent(&tp->pdev->dev,
6497 TG3_RX_RCB_RING_BYTES(tp),
6499 tnapi->rx_rcb_mapping);
6500 tnapi->rx_rcb = NULL;
6503 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6505 if (tnapi->hw_status) {
6506 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6508 tnapi->status_mapping);
6509 tnapi->hw_status = NULL;
6514 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6515 tp->hw_stats, tp->stats_mapping);
6516 tp->hw_stats = NULL;
6521 * Must not be invoked with interrupt sources disabled and
6522 * the hardware shutdown down. Can sleep.
6524 static int tg3_alloc_consistent(struct tg3 *tp)
6528 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6529 sizeof(struct tg3_hw_stats),
6535 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6537 for (i = 0; i < tp->irq_cnt; i++) {
6538 struct tg3_napi *tnapi = &tp->napi[i];
6539 struct tg3_hw_status *sblk;
6541 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6543 &tnapi->status_mapping,
6545 if (!tnapi->hw_status)
6548 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6549 sblk = tnapi->hw_status;
6551 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6554 /* If multivector TSS is enabled, vector 0 does not handle
6555 * tx interrupts. Don't allocate any resources for it.
6557 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6558 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6559 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6562 if (!tnapi->tx_buffers)
6565 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6567 &tnapi->tx_desc_mapping,
6569 if (!tnapi->tx_ring)
6574 * When RSS is enabled, the status block format changes
6575 * slightly. The "rx_jumbo_consumer", "reserved",
6576 * and "rx_mini_consumer" members get mapped to the
6577 * other three rx return ring producer indexes.
6581 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6584 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6587 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6590 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6595 * If multivector RSS is enabled, vector 0 does not handle
6596 * rx or tx interrupts. Don't allocate any resources for it.
6598 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6601 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6602 TG3_RX_RCB_RING_BYTES(tp),
6603 &tnapi->rx_rcb_mapping,
6608 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6614 tg3_free_consistent(tp);
6618 #define MAX_WAIT_CNT 1000
6620 /* To stop a block, clear the enable bit and poll till it
6621 * clears. tp->lock is held.
6623 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6628 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6635 /* We can't enable/disable these bits of the
6636 * 5705/5750, just say success.
6649 for (i = 0; i < MAX_WAIT_CNT; i++) {
6652 if ((val & enable_bit) == 0)
6656 if (i == MAX_WAIT_CNT && !silent) {
6657 dev_err(&tp->pdev->dev,
6658 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6666 /* tp->lock is held. */
6667 static int tg3_abort_hw(struct tg3 *tp, int silent)
6671 tg3_disable_ints(tp);
6673 tp->rx_mode &= ~RX_MODE_ENABLE;
6674 tw32_f(MAC_RX_MODE, tp->rx_mode);
6677 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6678 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6679 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6680 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6681 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6682 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6684 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6685 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6686 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6687 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6688 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6689 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6690 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6692 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6693 tw32_f(MAC_MODE, tp->mac_mode);
6696 tp->tx_mode &= ~TX_MODE_ENABLE;
6697 tw32_f(MAC_TX_MODE, tp->tx_mode);
6699 for (i = 0; i < MAX_WAIT_CNT; i++) {
6701 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6704 if (i >= MAX_WAIT_CNT) {
6705 dev_err(&tp->pdev->dev,
6706 "%s timed out, TX_MODE_ENABLE will not clear "
6707 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6711 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6712 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6713 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6715 tw32(FTQ_RESET, 0xffffffff);
6716 tw32(FTQ_RESET, 0x00000000);
6718 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6719 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6721 for (i = 0; i < tp->irq_cnt; i++) {
6722 struct tg3_napi *tnapi = &tp->napi[i];
6723 if (tnapi->hw_status)
6724 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6727 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6732 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6737 /* NCSI does not support APE events */
6738 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6741 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6742 if (apedata != APE_SEG_SIG_MAGIC)
6745 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6746 if (!(apedata & APE_FW_STATUS_READY))
6749 /* Wait for up to 1 millisecond for APE to service previous event. */
6750 for (i = 0; i < 10; i++) {
6751 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6754 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6756 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6757 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6758 event | APE_EVENT_STATUS_EVENT_PENDING);
6760 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6762 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6768 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6769 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6772 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6777 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6781 case RESET_KIND_INIT:
6782 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6783 APE_HOST_SEG_SIG_MAGIC);
6784 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6785 APE_HOST_SEG_LEN_MAGIC);
6786 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6787 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6788 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6789 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6790 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6791 APE_HOST_BEHAV_NO_PHYLOCK);
6792 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6793 TG3_APE_HOST_DRVR_STATE_START);
6795 event = APE_EVENT_STATUS_STATE_START;
6797 case RESET_KIND_SHUTDOWN:
6798 /* With the interface we are currently using,
6799 * APE does not track driver state. Wiping
6800 * out the HOST SEGMENT SIGNATURE forces
6801 * the APE to assume OS absent status.
6803 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6805 if (device_may_wakeup(&tp->pdev->dev) &&
6806 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6807 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6808 TG3_APE_HOST_WOL_SPEED_AUTO);
6809 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6811 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6813 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6815 event = APE_EVENT_STATUS_STATE_UNLOAD;
6817 case RESET_KIND_SUSPEND:
6818 event = APE_EVENT_STATUS_STATE_SUSPEND;
6824 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6826 tg3_ape_send_event(tp, event);
6829 /* tp->lock is held. */
6830 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6832 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6833 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6835 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6837 case RESET_KIND_INIT:
6838 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6842 case RESET_KIND_SHUTDOWN:
6843 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6847 case RESET_KIND_SUSPEND:
6848 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6857 if (kind == RESET_KIND_INIT ||
6858 kind == RESET_KIND_SUSPEND)
6859 tg3_ape_driver_state_change(tp, kind);
6862 /* tp->lock is held. */
6863 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6865 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6867 case RESET_KIND_INIT:
6868 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6869 DRV_STATE_START_DONE);
6872 case RESET_KIND_SHUTDOWN:
6873 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6874 DRV_STATE_UNLOAD_DONE);
6882 if (kind == RESET_KIND_SHUTDOWN)
6883 tg3_ape_driver_state_change(tp, kind);
6886 /* tp->lock is held. */
6887 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6889 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6891 case RESET_KIND_INIT:
6892 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6896 case RESET_KIND_SHUTDOWN:
6897 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6901 case RESET_KIND_SUSPEND:
6902 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6912 static int tg3_poll_fw(struct tg3 *tp)
6917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6918 /* Wait up to 20ms for init done. */
6919 for (i = 0; i < 200; i++) {
6920 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6927 /* Wait for firmware initialization to complete. */
6928 for (i = 0; i < 100000; i++) {
6929 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6930 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6935 /* Chip might not be fitted with firmware. Some Sun onboard
6936 * parts are configured like that. So don't signal the timeout
6937 * of the above loop as an error, but do report the lack of
6938 * running firmware once.
6941 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6942 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6944 netdev_info(tp->dev, "No firmware running\n");
6947 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6948 /* The 57765 A0 needs a little more
6949 * time to do some important work.
6957 /* Save PCI command register before chip reset */
6958 static void tg3_save_pci_state(struct tg3 *tp)
6960 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6963 /* Restore PCI state after chip reset */
6964 static void tg3_restore_pci_state(struct tg3 *tp)
6968 /* Re-enable indirect register accesses. */
6969 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6970 tp->misc_host_ctrl);
6972 /* Set MAX PCI retry to zero. */
6973 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6974 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6975 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6976 val |= PCISTATE_RETRY_SAME_DMA;
6977 /* Allow reads and writes to the APE register and memory space. */
6978 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6979 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6980 PCISTATE_ALLOW_APE_SHMEM_WR |
6981 PCISTATE_ALLOW_APE_PSPACE_WR;
6982 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6984 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6986 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6987 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6988 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
6990 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6991 tp->pci_cacheline_sz);
6992 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6997 /* Make sure PCI-X relaxed ordering bit is clear. */
6998 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7001 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7003 pcix_cmd &= ~PCI_X_CMD_ERO;
7004 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7008 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7010 /* Chip reset on 5780 will reset MSI enable bit,
7011 * so need to restore it.
7013 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7016 pci_read_config_word(tp->pdev,
7017 tp->msi_cap + PCI_MSI_FLAGS,
7019 pci_write_config_word(tp->pdev,
7020 tp->msi_cap + PCI_MSI_FLAGS,
7021 ctrl | PCI_MSI_FLAGS_ENABLE);
7022 val = tr32(MSGINT_MODE);
7023 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7028 static void tg3_stop_fw(struct tg3 *);
7030 /* tp->lock is held. */
7031 static int tg3_chip_reset(struct tg3 *tp)
7034 void (*write_op)(struct tg3 *, u32, u32);
7039 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7041 /* No matching tg3_nvram_unlock() after this because
7042 * chip reset below will undo the nvram lock.
7044 tp->nvram_lock_cnt = 0;
7046 /* GRC_MISC_CFG core clock reset will clear the memory
7047 * enable bit in PCI register 4 and the MSI enable bit
7048 * on some chips, so we save relevant registers here.
7050 tg3_save_pci_state(tp);
7052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7053 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7054 tw32(GRC_FASTBOOT_PC, 0);
7057 * We must avoid the readl() that normally takes place.
7058 * It locks machines, causes machine checks, and other
7059 * fun things. So, temporarily disable the 5701
7060 * hardware workaround, while we do the reset.
7062 write_op = tp->write32;
7063 if (write_op == tg3_write_flush_reg32)
7064 tp->write32 = tg3_write32;
7066 /* Prevent the irq handler from reading or writing PCI registers
7067 * during chip reset when the memory enable bit in the PCI command
7068 * register may be cleared. The chip does not generate interrupt
7069 * at this time, but the irq handler may still be called due to irq
7070 * sharing or irqpoll.
7072 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7073 for (i = 0; i < tp->irq_cnt; i++) {
7074 struct tg3_napi *tnapi = &tp->napi[i];
7075 if (tnapi->hw_status) {
7076 tnapi->hw_status->status = 0;
7077 tnapi->hw_status->status_tag = 0;
7079 tnapi->last_tag = 0;
7080 tnapi->last_irq_tag = 0;
7084 for (i = 0; i < tp->irq_cnt; i++)
7085 synchronize_irq(tp->napi[i].irq_vec);
7087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7088 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7089 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7093 val = GRC_MISC_CFG_CORECLK_RESET;
7095 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7096 /* Force PCIe 1.0a mode */
7097 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7098 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7099 tr32(TG3_PCIE_PHY_TSTCTL) ==
7100 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7101 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7103 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7104 tw32(GRC_MISC_CFG, (1 << 29));
7109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7110 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7111 tw32(GRC_VCPU_EXT_CTRL,
7112 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7115 /* Manage gphy power for all CPMU absent PCIe devices. */
7116 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7117 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7118 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7120 tw32(GRC_MISC_CFG, val);
7122 /* restore 5701 hardware bug workaround write method */
7123 tp->write32 = write_op;
7125 /* Unfortunately, we have to delay before the PCI read back.
7126 * Some 575X chips even will not respond to a PCI cfg access
7127 * when the reset command is given to the chip.
7129 * How do these hardware designers expect things to work
7130 * properly if the PCI write is posted for a long period
7131 * of time? It is always necessary to have some method by
7132 * which a register read back can occur to push the write
7133 * out which does the reset.
7135 * For most tg3 variants the trick below was working.
7140 /* Flush PCI posted writes. The normal MMIO registers
7141 * are inaccessible at this time so this is the only
7142 * way to make this reliably (actually, this is no longer
7143 * the case, see above). I tried to use indirect
7144 * register read/write but this upset some 5701 variants.
7146 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7150 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7153 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7157 /* Wait for link training to complete. */
7158 for (i = 0; i < 5000; i++)
7161 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7162 pci_write_config_dword(tp->pdev, 0xc4,
7163 cfg_val | (1 << 15));
7166 /* Clear the "no snoop" and "relaxed ordering" bits. */
7167 pci_read_config_word(tp->pdev,
7168 tp->pcie_cap + PCI_EXP_DEVCTL,
7170 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7171 PCI_EXP_DEVCTL_NOSNOOP_EN);
7173 * Older PCIe devices only support the 128 byte
7174 * MPS setting. Enforce the restriction.
7176 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7177 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7178 pci_write_config_word(tp->pdev,
7179 tp->pcie_cap + PCI_EXP_DEVCTL,
7182 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7184 /* Clear error status */
7185 pci_write_config_word(tp->pdev,
7186 tp->pcie_cap + PCI_EXP_DEVSTA,
7187 PCI_EXP_DEVSTA_CED |
7188 PCI_EXP_DEVSTA_NFED |
7189 PCI_EXP_DEVSTA_FED |
7190 PCI_EXP_DEVSTA_URD);
7193 tg3_restore_pci_state(tp);
7195 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7198 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7199 val = tr32(MEMARB_MODE);
7200 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7202 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7204 tw32(0x5000, 0x400);
7207 tw32(GRC_MODE, tp->grc_mode);
7209 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7212 tw32(0xc4, val | (1 << 15));
7215 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7216 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7217 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7218 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7219 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7220 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7223 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7224 tp->mac_mode = MAC_MODE_APE_TX_EN |
7225 MAC_MODE_APE_RX_EN |
7226 MAC_MODE_TDE_ENABLE;
7228 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7229 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7231 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7232 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7237 tw32_f(MAC_MODE, val);
7240 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7242 err = tg3_poll_fw(tp);
7248 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7249 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7250 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7251 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7254 tw32(0x7c00, val | (1 << 25));
7257 /* Reprobe ASF enable state. */
7258 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7259 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7260 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7261 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7264 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7265 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7266 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7267 tp->last_event_jiffies = jiffies;
7268 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7269 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7276 /* tp->lock is held. */
7277 static void tg3_stop_fw(struct tg3 *tp)
7279 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7280 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7281 /* Wait for RX cpu to ACK the previous event. */
7282 tg3_wait_for_event_ack(tp);
7284 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7286 tg3_generate_fw_event(tp);
7288 /* Wait for RX cpu to ACK this event. */
7289 tg3_wait_for_event_ack(tp);
7293 /* tp->lock is held. */
7294 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7300 tg3_write_sig_pre_reset(tp, kind);
7302 tg3_abort_hw(tp, silent);
7303 err = tg3_chip_reset(tp);
7305 __tg3_set_mac_addr(tp, 0);
7307 tg3_write_sig_legacy(tp, kind);
7308 tg3_write_sig_post_reset(tp, kind);
7316 #define RX_CPU_SCRATCH_BASE 0x30000
7317 #define RX_CPU_SCRATCH_SIZE 0x04000
7318 #define TX_CPU_SCRATCH_BASE 0x34000
7319 #define TX_CPU_SCRATCH_SIZE 0x04000
7321 /* tp->lock is held. */
7322 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7326 BUG_ON(offset == TX_CPU_BASE &&
7327 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7329 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7330 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7332 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7335 if (offset == RX_CPU_BASE) {
7336 for (i = 0; i < 10000; i++) {
7337 tw32(offset + CPU_STATE, 0xffffffff);
7338 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7339 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7343 tw32(offset + CPU_STATE, 0xffffffff);
7344 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7347 for (i = 0; i < 10000; i++) {
7348 tw32(offset + CPU_STATE, 0xffffffff);
7349 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7350 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7356 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7357 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7361 /* Clear firmware's nvram arbitration. */
7362 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7363 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7368 unsigned int fw_base;
7369 unsigned int fw_len;
7370 const __be32 *fw_data;
7373 /* tp->lock is held. */
7374 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7375 int cpu_scratch_size, struct fw_info *info)
7377 int err, lock_err, i;
7378 void (*write_op)(struct tg3 *, u32, u32);
7380 if (cpu_base == TX_CPU_BASE &&
7381 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7383 "%s: Trying to load TX cpu firmware which is 5705\n",
7388 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7389 write_op = tg3_write_mem;
7391 write_op = tg3_write_indirect_reg32;
7393 /* It is possible that bootcode is still loading at this point.
7394 * Get the nvram lock first before halting the cpu.
7396 lock_err = tg3_nvram_lock(tp);
7397 err = tg3_halt_cpu(tp, cpu_base);
7399 tg3_nvram_unlock(tp);
7403 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7404 write_op(tp, cpu_scratch_base + i, 0);
7405 tw32(cpu_base + CPU_STATE, 0xffffffff);
7406 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7407 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7408 write_op(tp, (cpu_scratch_base +
7409 (info->fw_base & 0xffff) +
7411 be32_to_cpu(info->fw_data[i]));
7419 /* tp->lock is held. */
7420 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7422 struct fw_info info;
7423 const __be32 *fw_data;
7426 fw_data = (void *)tp->fw->data;
7428 /* Firmware blob starts with version numbers, followed by
7429 start address and length. We are setting complete length.
7430 length = end_address_of_bss - start_address_of_text.
7431 Remainder is the blob to be loaded contiguously
7432 from start address. */
7434 info.fw_base = be32_to_cpu(fw_data[1]);
7435 info.fw_len = tp->fw->size - 12;
7436 info.fw_data = &fw_data[3];
7438 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7439 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7444 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7445 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7450 /* Now startup only the RX cpu. */
7451 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7452 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7454 for (i = 0; i < 5; i++) {
7455 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7457 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7458 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7459 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7463 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7464 "should be %08x\n", __func__,
7465 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7468 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7469 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7474 /* 5705 needs a special version of the TSO firmware. */
7476 /* tp->lock is held. */
7477 static int tg3_load_tso_firmware(struct tg3 *tp)
7479 struct fw_info info;
7480 const __be32 *fw_data;
7481 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7484 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7487 fw_data = (void *)tp->fw->data;
7489 /* Firmware blob starts with version numbers, followed by
7490 start address and length. We are setting complete length.
7491 length = end_address_of_bss - start_address_of_text.
7492 Remainder is the blob to be loaded contiguously
7493 from start address. */
7495 info.fw_base = be32_to_cpu(fw_data[1]);
7496 cpu_scratch_size = tp->fw_len;
7497 info.fw_len = tp->fw->size - 12;
7498 info.fw_data = &fw_data[3];
7500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7501 cpu_base = RX_CPU_BASE;
7502 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7504 cpu_base = TX_CPU_BASE;
7505 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7506 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7509 err = tg3_load_firmware_cpu(tp, cpu_base,
7510 cpu_scratch_base, cpu_scratch_size,
7515 /* Now startup the cpu. */
7516 tw32(cpu_base + CPU_STATE, 0xffffffff);
7517 tw32_f(cpu_base + CPU_PC, info.fw_base);
7519 for (i = 0; i < 5; i++) {
7520 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7522 tw32(cpu_base + CPU_STATE, 0xffffffff);
7523 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7524 tw32_f(cpu_base + CPU_PC, info.fw_base);
7529 "%s fails to set CPU PC, is %08x should be %08x\n",
7530 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7533 tw32(cpu_base + CPU_STATE, 0xffffffff);
7534 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7539 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7541 struct tg3 *tp = netdev_priv(dev);
7542 struct sockaddr *addr = p;
7543 int err = 0, skip_mac_1 = 0;
7545 if (!is_valid_ether_addr(addr->sa_data))
7548 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7550 if (!netif_running(dev))
7553 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7554 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7556 addr0_high = tr32(MAC_ADDR_0_HIGH);
7557 addr0_low = tr32(MAC_ADDR_0_LOW);
7558 addr1_high = tr32(MAC_ADDR_1_HIGH);
7559 addr1_low = tr32(MAC_ADDR_1_LOW);
7561 /* Skip MAC addr 1 if ASF is using it. */
7562 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7563 !(addr1_high == 0 && addr1_low == 0))
7566 spin_lock_bh(&tp->lock);
7567 __tg3_set_mac_addr(tp, skip_mac_1);
7568 spin_unlock_bh(&tp->lock);
7573 /* tp->lock is held. */
7574 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7575 dma_addr_t mapping, u32 maxlen_flags,
7579 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7580 ((u64) mapping >> 32));
7582 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7583 ((u64) mapping & 0xffffffff));
7585 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7588 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7590 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7594 static void __tg3_set_rx_mode(struct net_device *);
7595 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7600 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7601 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7602 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7604 tw32(HOSTCC_TXCOL_TICKS, 0);
7605 tw32(HOSTCC_TXMAX_FRAMES, 0);
7606 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7609 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7610 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7611 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7612 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7614 tw32(HOSTCC_RXCOL_TICKS, 0);
7615 tw32(HOSTCC_RXMAX_FRAMES, 0);
7616 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7619 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7620 u32 val = ec->stats_block_coalesce_usecs;
7622 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7623 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7625 if (!netif_carrier_ok(tp->dev))
7628 tw32(HOSTCC_STAT_COAL_TICKS, val);
7631 for (i = 0; i < tp->irq_cnt - 1; i++) {
7634 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7635 tw32(reg, ec->rx_coalesce_usecs);
7636 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7637 tw32(reg, ec->rx_max_coalesced_frames);
7638 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7639 tw32(reg, ec->rx_max_coalesced_frames_irq);
7641 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7642 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7643 tw32(reg, ec->tx_coalesce_usecs);
7644 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7645 tw32(reg, ec->tx_max_coalesced_frames);
7646 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7647 tw32(reg, ec->tx_max_coalesced_frames_irq);
7651 for (; i < tp->irq_max - 1; i++) {
7652 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7653 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7654 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7656 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7657 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7658 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7659 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7664 /* tp->lock is held. */
7665 static void tg3_rings_reset(struct tg3 *tp)
7668 u32 stblk, txrcb, rxrcb, limit;
7669 struct tg3_napi *tnapi = &tp->napi[0];
7671 /* Disable all transmit rings but the first. */
7672 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7673 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7674 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7675 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7676 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7677 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7678 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7680 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7682 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7683 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7684 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7685 BDINFO_FLAGS_DISABLED);
7688 /* Disable all receive return rings but the first. */
7689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7690 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7691 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7692 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7693 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7694 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7695 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7696 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7698 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7700 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7701 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7702 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7703 BDINFO_FLAGS_DISABLED);
7705 /* Disable interrupts */
7706 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7708 /* Zero mailbox registers. */
7709 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7710 for (i = 1; i < tp->irq_max; i++) {
7711 tp->napi[i].tx_prod = 0;
7712 tp->napi[i].tx_cons = 0;
7713 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7714 tw32_mailbox(tp->napi[i].prodmbox, 0);
7715 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7716 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7718 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7719 tw32_mailbox(tp->napi[0].prodmbox, 0);
7721 tp->napi[0].tx_prod = 0;
7722 tp->napi[0].tx_cons = 0;
7723 tw32_mailbox(tp->napi[0].prodmbox, 0);
7724 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7727 /* Make sure the NIC-based send BD rings are disabled. */
7728 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7729 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7730 for (i = 0; i < 16; i++)
7731 tw32_tx_mbox(mbox + i * 8, 0);
7734 txrcb = NIC_SRAM_SEND_RCB;
7735 rxrcb = NIC_SRAM_RCV_RET_RCB;
7737 /* Clear status block in ram. */
7738 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7740 /* Set status block DMA address */
7741 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7742 ((u64) tnapi->status_mapping >> 32));
7743 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7744 ((u64) tnapi->status_mapping & 0xffffffff));
7746 if (tnapi->tx_ring) {
7747 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7748 (TG3_TX_RING_SIZE <<
7749 BDINFO_FLAGS_MAXLEN_SHIFT),
7750 NIC_SRAM_TX_BUFFER_DESC);
7751 txrcb += TG3_BDINFO_SIZE;
7754 if (tnapi->rx_rcb) {
7755 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7756 (tp->rx_ret_ring_mask + 1) <<
7757 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7758 rxrcb += TG3_BDINFO_SIZE;
7761 stblk = HOSTCC_STATBLCK_RING1;
7763 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7764 u64 mapping = (u64)tnapi->status_mapping;
7765 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7766 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7768 /* Clear status block in ram. */
7769 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7771 if (tnapi->tx_ring) {
7772 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7773 (TG3_TX_RING_SIZE <<
7774 BDINFO_FLAGS_MAXLEN_SHIFT),
7775 NIC_SRAM_TX_BUFFER_DESC);
7776 txrcb += TG3_BDINFO_SIZE;
7779 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7780 ((tp->rx_ret_ring_mask + 1) <<
7781 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7784 rxrcb += TG3_BDINFO_SIZE;
7788 /* tp->lock is held. */
7789 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7791 u32 val, rdmac_mode;
7793 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7795 tg3_disable_ints(tp);
7799 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7801 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7802 tg3_abort_hw(tp, 1);
7804 /* Enable MAC control of LPI */
7805 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7806 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7807 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7808 TG3_CPMU_EEE_LNKIDL_UART_IDL);
7810 tw32_f(TG3_CPMU_EEE_CTRL,
7811 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7813 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7814 TG3_CPMU_EEEMD_LPI_IN_TX |
7815 TG3_CPMU_EEEMD_LPI_IN_RX |
7816 TG3_CPMU_EEEMD_EEE_ENABLE;
7818 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7819 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7821 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7822 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7824 tw32_f(TG3_CPMU_EEE_MODE, val);
7826 tw32_f(TG3_CPMU_EEE_DBTMR1,
7827 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7828 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7830 tw32_f(TG3_CPMU_EEE_DBTMR2,
7831 TG3_CPMU_DBTMR2_APE_TX_2047US |
7832 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7838 err = tg3_chip_reset(tp);
7842 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7844 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7845 val = tr32(TG3_CPMU_CTRL);
7846 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7847 tw32(TG3_CPMU_CTRL, val);
7849 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7850 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7851 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7852 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7854 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7855 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7856 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7857 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7859 val = tr32(TG3_CPMU_HST_ACC);
7860 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7861 val |= CPMU_HST_ACC_MACCLK_6_25;
7862 tw32(TG3_CPMU_HST_ACC, val);
7865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7866 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7867 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7868 PCIE_PWR_MGMT_L1_THRESH_4MS;
7869 tw32(PCIE_PWR_MGMT_THRESH, val);
7871 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7872 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7874 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7876 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7877 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7880 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7881 u32 grc_mode = tr32(GRC_MODE);
7883 /* Access the lower 1K of PL PCIE block registers. */
7884 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7885 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7887 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7888 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7889 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7891 tw32(GRC_MODE, grc_mode);
7894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7895 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7896 u32 grc_mode = tr32(GRC_MODE);
7898 /* Access the lower 1K of PL PCIE block registers. */
7899 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7900 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7902 val = tr32(TG3_PCIE_TLDLPL_PORT +
7903 TG3_PCIE_PL_LO_PHYCTL5);
7904 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7905 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7907 tw32(GRC_MODE, grc_mode);
7910 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7911 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7912 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7913 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7916 /* This works around an issue with Athlon chipsets on
7917 * B3 tigon3 silicon. This bit has no effect on any
7918 * other revision. But do not set this on PCI Express
7919 * chips and don't even touch the clocks if the CPMU is present.
7921 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7922 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7923 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7924 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7927 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7928 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7929 val = tr32(TG3PCI_PCISTATE);
7930 val |= PCISTATE_RETRY_SAME_DMA;
7931 tw32(TG3PCI_PCISTATE, val);
7934 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7935 /* Allow reads and writes to the
7936 * APE register and memory space.
7938 val = tr32(TG3PCI_PCISTATE);
7939 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7940 PCISTATE_ALLOW_APE_SHMEM_WR |
7941 PCISTATE_ALLOW_APE_PSPACE_WR;
7942 tw32(TG3PCI_PCISTATE, val);
7945 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7946 /* Enable some hw fixes. */
7947 val = tr32(TG3PCI_MSI_DATA);
7948 val |= (1 << 26) | (1 << 28) | (1 << 29);
7949 tw32(TG3PCI_MSI_DATA, val);
7952 /* Descriptor ring init may make accesses to the
7953 * NIC SRAM area to setup the TX descriptors, so we
7954 * can only do this after the hardware has been
7955 * successfully reset.
7957 err = tg3_init_rings(tp);
7961 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7962 val = tr32(TG3PCI_DMA_RW_CTRL) &
7963 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7964 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7965 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7966 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7967 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7968 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7969 /* This value is determined during the probe time DMA
7970 * engine test, tg3_test_dma.
7972 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7975 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7976 GRC_MODE_4X_NIC_SEND_RINGS |
7977 GRC_MODE_NO_TX_PHDR_CSUM |
7978 GRC_MODE_NO_RX_PHDR_CSUM);
7979 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7981 /* Pseudo-header checksum is done by hardware logic and not
7982 * the offload processers, so make the chip do the pseudo-
7983 * header checksums on receive. For transmit it is more
7984 * convenient to do the pseudo-header checksum in software
7985 * as Linux does that on transmit for us in all cases.
7987 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7991 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7993 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7994 val = tr32(GRC_MISC_CFG);
7996 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7997 tw32(GRC_MISC_CFG, val);
7999 /* Initialize MBUF/DESC pool. */
8000 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8002 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8003 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8005 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8007 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8008 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8009 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8010 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8013 fw_len = tp->fw_len;
8014 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8015 tw32(BUFMGR_MB_POOL_ADDR,
8016 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8017 tw32(BUFMGR_MB_POOL_SIZE,
8018 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8021 if (tp->dev->mtu <= ETH_DATA_LEN) {
8022 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8023 tp->bufmgr_config.mbuf_read_dma_low_water);
8024 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8025 tp->bufmgr_config.mbuf_mac_rx_low_water);
8026 tw32(BUFMGR_MB_HIGH_WATER,
8027 tp->bufmgr_config.mbuf_high_water);
8029 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8030 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8031 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8032 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8033 tw32(BUFMGR_MB_HIGH_WATER,
8034 tp->bufmgr_config.mbuf_high_water_jumbo);
8036 tw32(BUFMGR_DMA_LOW_WATER,
8037 tp->bufmgr_config.dma_low_water);
8038 tw32(BUFMGR_DMA_HIGH_WATER,
8039 tp->bufmgr_config.dma_high_water);
8041 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8043 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8044 tw32(BUFMGR_MODE, val);
8045 for (i = 0; i < 2000; i++) {
8046 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8051 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8055 /* Setup replenish threshold. */
8056 val = tp->rx_pending / 8;
8059 else if (val > tp->rx_std_max_post)
8060 val = tp->rx_std_max_post;
8061 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8062 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8063 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8065 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8066 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8069 tw32(RCVBDI_STD_THRESH, val);
8071 /* Initialize TG3_BDINFO's at:
8072 * RCVDBDI_STD_BD: standard eth size rx ring
8073 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8074 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8077 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8078 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8079 * ring attribute flags
8080 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8082 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8083 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8085 * The size of each ring is fixed in the firmware, but the location is
8088 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8089 ((u64) tpr->rx_std_mapping >> 32));
8090 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8091 ((u64) tpr->rx_std_mapping & 0xffffffff));
8092 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8093 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8094 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8095 NIC_SRAM_RX_BUFFER_DESC);
8097 /* Disable the mini ring */
8098 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8099 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8100 BDINFO_FLAGS_DISABLED);
8102 /* Program the jumbo buffer descriptor ring control
8103 * blocks on those devices that have them.
8105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8106 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8107 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
8108 /* Setup replenish threshold. */
8109 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8111 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8112 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8113 ((u64) tpr->rx_jmb_mapping >> 32));
8114 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8115 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8116 val = TG3_RX_JMB_RING_SIZE(tp) <<
8117 BDINFO_FLAGS_MAXLEN_SHIFT;
8118 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8119 val | BDINFO_FLAGS_USE_EXT_RECV);
8120 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8121 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8122 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8123 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8125 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8126 BDINFO_FLAGS_DISABLED);
8129 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8131 val = TG3_RX_STD_MAX_SIZE_5700;
8133 val = TG3_RX_STD_MAX_SIZE_5717;
8134 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8135 val |= (TG3_RX_STD_DMA_SZ << 2);
8137 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8139 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8141 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8143 tpr->rx_std_prod_idx = tp->rx_pending;
8144 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8146 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8147 tp->rx_jumbo_pending : 0;
8148 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8150 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8151 tw32(STD_REPLENISH_LWM, 32);
8152 tw32(JMB_REPLENISH_LWM, 16);
8155 tg3_rings_reset(tp);
8157 /* Initialize MAC address and backoff seed. */
8158 __tg3_set_mac_addr(tp, 0);
8160 /* MTU + ethernet header + FCS + optional VLAN tag */
8161 tw32(MAC_RX_MTU_SIZE,
8162 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8164 /* The slot time is changed by tg3_setup_phy if we
8165 * run at gigabit with half duplex.
8167 tw32(MAC_TX_LENGTHS,
8168 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8169 (6 << TX_LENGTHS_IPG_SHIFT) |
8170 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8172 /* Receive rules. */
8173 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8174 tw32(RCVLPC_CONFIG, 0x0181);
8176 /* Calculate RDMAC_MODE setting early, we need it to determine
8177 * the RCVLPC_STATE_ENABLE mask.
8179 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8180 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8181 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8182 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8183 RDMAC_MODE_LNGREAD_ENAB);
8185 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8186 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8188 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8191 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8192 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8193 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8195 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8196 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8197 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8198 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8199 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8200 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8201 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8202 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8206 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8207 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8209 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8210 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8212 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8213 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8214 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8215 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8219 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8221 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8222 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8224 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8225 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8226 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8227 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8228 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8229 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8231 tw32(TG3_RDMA_RSRVCTRL_REG,
8232 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8236 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8237 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8238 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8239 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8242 /* Receive/send statistics. */
8243 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8244 val = tr32(RCVLPC_STATS_ENABLE);
8245 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8246 tw32(RCVLPC_STATS_ENABLE, val);
8247 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8248 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8249 val = tr32(RCVLPC_STATS_ENABLE);
8250 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8251 tw32(RCVLPC_STATS_ENABLE, val);
8253 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8255 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8256 tw32(SNDDATAI_STATSENAB, 0xffffff);
8257 tw32(SNDDATAI_STATSCTRL,
8258 (SNDDATAI_SCTRL_ENABLE |
8259 SNDDATAI_SCTRL_FASTUPD));
8261 /* Setup host coalescing engine. */
8262 tw32(HOSTCC_MODE, 0);
8263 for (i = 0; i < 2000; i++) {
8264 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8269 __tg3_set_coalesce(tp, &tp->coal);
8271 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8272 /* Status/statistics block address. See tg3_timer,
8273 * the tg3_periodic_fetch_stats call there, and
8274 * tg3_get_stats to see how this works for 5705/5750 chips.
8276 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8277 ((u64) tp->stats_mapping >> 32));
8278 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8279 ((u64) tp->stats_mapping & 0xffffffff));
8280 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8282 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8284 /* Clear statistics and status block memory areas */
8285 for (i = NIC_SRAM_STATS_BLK;
8286 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8288 tg3_write_mem(tp, i, 0);
8293 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8295 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8296 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8297 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8298 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8300 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8301 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8302 /* reset to prevent losing 1st rx packet intermittently */
8303 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8307 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8308 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8311 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8312 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8313 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8314 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8315 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8316 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8317 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8320 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8321 * If TG3_FLG2_IS_NIC is zero, we should read the
8322 * register to preserve the GPIO settings for LOMs. The GPIOs,
8323 * whether used as inputs or outputs, are set by boot code after
8326 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8329 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8330 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8331 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8333 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8334 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8335 GRC_LCLCTRL_GPIO_OUTPUT3;
8337 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8338 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8340 tp->grc_local_ctrl &= ~gpio_mask;
8341 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8343 /* GPIO1 must be driven high for eeprom write protect */
8344 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8345 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8346 GRC_LCLCTRL_GPIO_OUTPUT1);
8348 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8351 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
8353 val = tr32(MSGINT_MODE);
8354 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8355 tw32(MSGINT_MODE, val);
8358 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8359 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8363 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8364 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8365 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8366 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8367 WDMAC_MODE_LNGREAD_ENAB);
8369 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8370 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8371 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8372 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8373 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8375 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8376 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8377 val |= WDMAC_MODE_RX_ACCEL;
8381 /* Enable host coalescing bug fix */
8382 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8383 val |= WDMAC_MODE_STATUS_TAG_FIX;
8385 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8386 val |= WDMAC_MODE_BURST_ALL_DATA;
8388 tw32_f(WDMAC_MODE, val);
8391 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8394 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8397 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8398 pcix_cmd |= PCI_X_CMD_READ_2K;
8399 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8400 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8401 pcix_cmd |= PCI_X_CMD_READ_2K;
8403 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8407 tw32_f(RDMAC_MODE, rdmac_mode);
8410 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8411 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8412 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8416 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8418 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8420 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8421 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8422 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8423 if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
8424 val |= RCVDBDI_MODE_LRG_RING_SZ;
8425 tw32(RCVDBDI_MODE, val);
8426 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8427 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8428 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8429 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8430 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8431 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8432 tw32(SNDBDI_MODE, val);
8433 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8435 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8436 err = tg3_load_5701_a0_firmware_fix(tp);
8441 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8442 err = tg3_load_tso_firmware(tp);
8447 tp->tx_mode = TX_MODE_ENABLE;
8448 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8449 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8450 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8451 tw32_f(MAC_TX_MODE, tp->tx_mode);
8454 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8455 u32 reg = MAC_RSS_INDIR_TBL_0;
8456 u8 *ent = (u8 *)&val;
8458 /* Setup the indirection table */
8459 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8460 int idx = i % sizeof(val);
8462 ent[idx] = i % (tp->irq_cnt - 1);
8463 if (idx == sizeof(val) - 1) {
8469 /* Setup the "secret" hash key. */
8470 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8471 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8472 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8473 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8474 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8475 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8476 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8477 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8478 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8479 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8482 tp->rx_mode = RX_MODE_ENABLE;
8483 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8484 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8486 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8487 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8488 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8489 RX_MODE_RSS_IPV6_HASH_EN |
8490 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8491 RX_MODE_RSS_IPV4_HASH_EN |
8492 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8494 tw32_f(MAC_RX_MODE, tp->rx_mode);
8497 tw32(MAC_LED_CTRL, tp->led_ctrl);
8499 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8500 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8501 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8504 tw32_f(MAC_RX_MODE, tp->rx_mode);
8507 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8508 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8509 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8510 /* Set drive transmission level to 1.2V */
8511 /* only if the signal pre-emphasis bit is not set */
8512 val = tr32(MAC_SERDES_CFG);
8515 tw32(MAC_SERDES_CFG, val);
8517 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8518 tw32(MAC_SERDES_CFG, 0x616000);
8521 /* Prevent chip from dropping frames when flow control
8524 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8528 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8531 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8532 /* Use hardware link auto-negotiation */
8533 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8536 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8537 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8540 tmp = tr32(SERDES_RX_CTRL);
8541 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8542 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8543 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8544 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8547 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8548 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8549 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8550 tp->link_config.speed = tp->link_config.orig_speed;
8551 tp->link_config.duplex = tp->link_config.orig_duplex;
8552 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8555 err = tg3_setup_phy(tp, 0);
8559 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8560 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8563 /* Clear CRC stats. */
8564 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8565 tg3_writephy(tp, MII_TG3_TEST1,
8566 tmp | MII_TG3_TEST1_CRC_EN);
8567 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8572 __tg3_set_rx_mode(tp->dev);
8574 /* Initialize receive rules. */
8575 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8576 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8577 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8578 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8580 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8581 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8585 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8589 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8591 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8593 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8595 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8597 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8599 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8601 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8603 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8605 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8607 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8609 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8611 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8613 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8615 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8623 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8624 /* Write our heartbeat update interval to APE. */
8625 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8626 APE_HOST_HEARTBEAT_INT_DISABLE);
8628 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8633 /* Called at device open time to get the chip ready for
8634 * packet processing. Invoked with tp->lock held.
8636 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8638 tg3_switch_clocks(tp);
8640 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8642 return tg3_reset_hw(tp, reset_phy);
8645 #define TG3_STAT_ADD32(PSTAT, REG) \
8646 do { u32 __val = tr32(REG); \
8647 (PSTAT)->low += __val; \
8648 if ((PSTAT)->low < __val) \
8649 (PSTAT)->high += 1; \
8652 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8654 struct tg3_hw_stats *sp = tp->hw_stats;
8656 if (!netif_carrier_ok(tp->dev))
8659 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8660 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8661 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8662 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8663 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8664 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8665 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8666 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8667 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8668 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8669 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8670 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8671 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8673 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8674 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8675 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8676 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8677 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8678 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8679 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8680 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8681 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8682 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8683 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8684 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8685 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8686 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8688 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8689 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8690 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8693 static void tg3_timer(unsigned long __opaque)
8695 struct tg3 *tp = (struct tg3 *) __opaque;
8700 spin_lock(&tp->lock);
8702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8703 /* All of this garbage is because when using non-tagged
8704 * IRQ status the mailbox/status_block protocol the chip
8705 * uses with the cpu is race prone.
8707 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8708 tw32(GRC_LOCAL_CTRL,
8709 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8711 tw32(HOSTCC_MODE, tp->coalesce_mode |
8712 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8715 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8716 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8717 spin_unlock(&tp->lock);
8718 schedule_work(&tp->reset_task);
8723 /* This part only runs once per second. */
8724 if (!--tp->timer_counter) {
8725 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8726 tg3_periodic_fetch_stats(tp);
8728 if (tp->setlpicnt && !--tp->setlpicnt) {
8729 u32 val = tr32(TG3_CPMU_EEE_MODE);
8730 tw32(TG3_CPMU_EEE_MODE,
8731 val | TG3_CPMU_EEEMD_LPI_ENABLE);
8734 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8738 mac_stat = tr32(MAC_STATUS);
8741 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8742 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8744 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8748 tg3_setup_phy(tp, 0);
8749 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8750 u32 mac_stat = tr32(MAC_STATUS);
8753 if (netif_carrier_ok(tp->dev) &&
8754 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8757 if (!netif_carrier_ok(tp->dev) &&
8758 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8759 MAC_STATUS_SIGNAL_DET))) {
8763 if (!tp->serdes_counter) {
8766 ~MAC_MODE_PORT_MODE_MASK));
8768 tw32_f(MAC_MODE, tp->mac_mode);
8771 tg3_setup_phy(tp, 0);
8773 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8774 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8775 tg3_serdes_parallel_detect(tp);
8778 tp->timer_counter = tp->timer_multiplier;
8781 /* Heartbeat is only sent once every 2 seconds.
8783 * The heartbeat is to tell the ASF firmware that the host
8784 * driver is still alive. In the event that the OS crashes,
8785 * ASF needs to reset the hardware to free up the FIFO space
8786 * that may be filled with rx packets destined for the host.
8787 * If the FIFO is full, ASF will no longer function properly.
8789 * Unintended resets have been reported on real time kernels
8790 * where the timer doesn't run on time. Netpoll will also have
8793 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8794 * to check the ring condition when the heartbeat is expiring
8795 * before doing the reset. This will prevent most unintended
8798 if (!--tp->asf_counter) {
8799 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8800 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8801 tg3_wait_for_event_ack(tp);
8803 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8804 FWCMD_NICDRV_ALIVE3);
8805 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8806 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8807 TG3_FW_UPDATE_TIMEOUT_SEC);
8809 tg3_generate_fw_event(tp);
8811 tp->asf_counter = tp->asf_multiplier;
8814 spin_unlock(&tp->lock);
8817 tp->timer.expires = jiffies + tp->timer_offset;
8818 add_timer(&tp->timer);
8821 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8824 unsigned long flags;
8826 struct tg3_napi *tnapi = &tp->napi[irq_num];
8828 if (tp->irq_cnt == 1)
8829 name = tp->dev->name;
8831 name = &tnapi->irq_lbl[0];
8832 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8833 name[IFNAMSIZ-1] = 0;
8836 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8838 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8843 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8844 fn = tg3_interrupt_tagged;
8845 flags = IRQF_SHARED;
8848 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8851 static int tg3_test_interrupt(struct tg3 *tp)
8853 struct tg3_napi *tnapi = &tp->napi[0];
8854 struct net_device *dev = tp->dev;
8855 int err, i, intr_ok = 0;
8858 if (!netif_running(dev))
8861 tg3_disable_ints(tp);
8863 free_irq(tnapi->irq_vec, tnapi);
8866 * Turn off MSI one shot mode. Otherwise this test has no
8867 * observable way to know whether the interrupt was delivered.
8869 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8870 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8871 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8872 tw32(MSGINT_MODE, val);
8875 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8876 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8880 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8881 tg3_enable_ints(tp);
8883 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8886 for (i = 0; i < 5; i++) {
8887 u32 int_mbox, misc_host_ctrl;
8889 int_mbox = tr32_mailbox(tnapi->int_mbox);
8890 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8892 if ((int_mbox != 0) ||
8893 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8901 tg3_disable_ints(tp);
8903 free_irq(tnapi->irq_vec, tnapi);
8905 err = tg3_request_irq(tp, 0);
8911 /* Reenable MSI one shot mode. */
8912 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8913 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8914 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8915 tw32(MSGINT_MODE, val);
8923 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8924 * successfully restored
8926 static int tg3_test_msi(struct tg3 *tp)
8931 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8934 /* Turn off SERR reporting in case MSI terminates with Master
8937 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8938 pci_write_config_word(tp->pdev, PCI_COMMAND,
8939 pci_cmd & ~PCI_COMMAND_SERR);
8941 err = tg3_test_interrupt(tp);
8943 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8948 /* other failures */
8952 /* MSI test failed, go back to INTx mode */
8953 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8954 "to INTx mode. Please report this failure to the PCI "
8955 "maintainer and include system chipset information\n");
8957 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8959 pci_disable_msi(tp->pdev);
8961 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8962 tp->napi[0].irq_vec = tp->pdev->irq;
8964 err = tg3_request_irq(tp, 0);
8968 /* Need to reset the chip because the MSI cycle may have terminated
8969 * with Master Abort.
8971 tg3_full_lock(tp, 1);
8973 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8974 err = tg3_init_hw(tp, 1);
8976 tg3_full_unlock(tp);
8979 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8984 static int tg3_request_firmware(struct tg3 *tp)
8986 const __be32 *fw_data;
8988 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8989 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8994 fw_data = (void *)tp->fw->data;
8996 /* Firmware blob starts with version numbers, followed by
8997 * start address and _full_ length including BSS sections
8998 * (which must be longer than the actual data, of course
9001 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9002 if (tp->fw_len < (tp->fw->size - 12)) {
9003 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9004 tp->fw_len, tp->fw_needed);
9005 release_firmware(tp->fw);
9010 /* We no longer need firmware; we have it. */
9011 tp->fw_needed = NULL;
9015 static bool tg3_enable_msix(struct tg3 *tp)
9017 int i, rc, cpus = num_online_cpus();
9018 struct msix_entry msix_ent[tp->irq_max];
9021 /* Just fallback to the simpler MSI mode. */
9025 * We want as many rx rings enabled as there are cpus.
9026 * The first MSIX vector only deals with link interrupts, etc,
9027 * so we add one to the number of vectors we are requesting.
9029 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9031 for (i = 0; i < tp->irq_max; i++) {
9032 msix_ent[i].entry = i;
9033 msix_ent[i].vector = 0;
9036 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9039 } else if (rc != 0) {
9040 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9042 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9047 for (i = 0; i < tp->irq_max; i++)
9048 tp->napi[i].irq_vec = msix_ent[i].vector;
9050 netif_set_real_num_tx_queues(tp->dev, 1);
9051 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9052 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9053 pci_disable_msix(tp->pdev);
9057 if (tp->irq_cnt > 1) {
9058 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
9060 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9061 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9068 static void tg3_ints_init(struct tg3 *tp)
9070 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9071 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9072 /* All MSI supporting chips should support tagged
9073 * status. Assert that this is the case.
9075 netdev_warn(tp->dev,
9076 "MSI without TAGGED_STATUS? Not using MSI\n");
9080 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9081 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9082 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9083 pci_enable_msi(tp->pdev) == 0)
9084 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9086 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9087 u32 msi_mode = tr32(MSGINT_MODE);
9088 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
9090 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9091 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9094 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9096 tp->napi[0].irq_vec = tp->pdev->irq;
9097 netif_set_real_num_tx_queues(tp->dev, 1);
9098 netif_set_real_num_rx_queues(tp->dev, 1);
9102 static void tg3_ints_fini(struct tg3 *tp)
9104 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9105 pci_disable_msix(tp->pdev);
9106 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9107 pci_disable_msi(tp->pdev);
9108 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9109 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9112 static int tg3_open(struct net_device *dev)
9114 struct tg3 *tp = netdev_priv(dev);
9117 if (tp->fw_needed) {
9118 err = tg3_request_firmware(tp);
9119 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9123 netdev_warn(tp->dev, "TSO capability disabled\n");
9124 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9125 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9126 netdev_notice(tp->dev, "TSO capability restored\n");
9127 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9131 netif_carrier_off(tp->dev);
9133 err = tg3_power_up(tp);
9137 tg3_full_lock(tp, 0);
9139 tg3_disable_ints(tp);
9140 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9142 tg3_full_unlock(tp);
9145 * Setup interrupts first so we know how
9146 * many NAPI resources to allocate
9150 /* The placement of this call is tied
9151 * to the setup and use of Host TX descriptors.
9153 err = tg3_alloc_consistent(tp);
9159 tg3_napi_enable(tp);
9161 for (i = 0; i < tp->irq_cnt; i++) {
9162 struct tg3_napi *tnapi = &tp->napi[i];
9163 err = tg3_request_irq(tp, i);
9165 for (i--; i >= 0; i--)
9166 free_irq(tnapi->irq_vec, tnapi);
9174 tg3_full_lock(tp, 0);
9176 err = tg3_init_hw(tp, 1);
9178 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9181 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9182 tp->timer_offset = HZ;
9184 tp->timer_offset = HZ / 10;
9186 BUG_ON(tp->timer_offset > HZ);
9187 tp->timer_counter = tp->timer_multiplier =
9188 (HZ / tp->timer_offset);
9189 tp->asf_counter = tp->asf_multiplier =
9190 ((HZ / tp->timer_offset) * 2);
9192 init_timer(&tp->timer);
9193 tp->timer.expires = jiffies + tp->timer_offset;
9194 tp->timer.data = (unsigned long) tp;
9195 tp->timer.function = tg3_timer;
9198 tg3_full_unlock(tp);
9203 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9204 err = tg3_test_msi(tp);
9207 tg3_full_lock(tp, 0);
9208 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9210 tg3_full_unlock(tp);
9215 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9216 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9217 u32 val = tr32(PCIE_TRANSACTION_CFG);
9219 tw32(PCIE_TRANSACTION_CFG,
9220 val | PCIE_TRANS_CFG_1SHOT_MSI);
9226 tg3_full_lock(tp, 0);
9228 add_timer(&tp->timer);
9229 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9230 tg3_enable_ints(tp);
9232 tg3_full_unlock(tp);
9234 netif_tx_start_all_queues(dev);
9239 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9240 struct tg3_napi *tnapi = &tp->napi[i];
9241 free_irq(tnapi->irq_vec, tnapi);
9245 tg3_napi_disable(tp);
9247 tg3_free_consistent(tp);
9254 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9255 struct rtnl_link_stats64 *);
9256 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9258 static int tg3_close(struct net_device *dev)
9261 struct tg3 *tp = netdev_priv(dev);
9263 tg3_napi_disable(tp);
9264 cancel_work_sync(&tp->reset_task);
9266 netif_tx_stop_all_queues(dev);
9268 del_timer_sync(&tp->timer);
9272 tg3_full_lock(tp, 1);
9274 tg3_disable_ints(tp);
9276 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9278 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9280 tg3_full_unlock(tp);
9282 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9283 struct tg3_napi *tnapi = &tp->napi[i];
9284 free_irq(tnapi->irq_vec, tnapi);
9289 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9291 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9292 sizeof(tp->estats_prev));
9296 tg3_free_consistent(tp);
9300 netif_carrier_off(tp->dev);
9305 static inline u64 get_stat64(tg3_stat64_t *val)
9307 return ((u64)val->high << 32) | ((u64)val->low);
9310 static u64 calc_crc_errors(struct tg3 *tp)
9312 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9314 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9315 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9316 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9319 spin_lock_bh(&tp->lock);
9320 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9321 tg3_writephy(tp, MII_TG3_TEST1,
9322 val | MII_TG3_TEST1_CRC_EN);
9323 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9326 spin_unlock_bh(&tp->lock);
9328 tp->phy_crc_errors += val;
9330 return tp->phy_crc_errors;
9333 return get_stat64(&hw_stats->rx_fcs_errors);
9336 #define ESTAT_ADD(member) \
9337 estats->member = old_estats->member + \
9338 get_stat64(&hw_stats->member)
9340 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9342 struct tg3_ethtool_stats *estats = &tp->estats;
9343 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9344 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9349 ESTAT_ADD(rx_octets);
9350 ESTAT_ADD(rx_fragments);
9351 ESTAT_ADD(rx_ucast_packets);
9352 ESTAT_ADD(rx_mcast_packets);
9353 ESTAT_ADD(rx_bcast_packets);
9354 ESTAT_ADD(rx_fcs_errors);
9355 ESTAT_ADD(rx_align_errors);
9356 ESTAT_ADD(rx_xon_pause_rcvd);
9357 ESTAT_ADD(rx_xoff_pause_rcvd);
9358 ESTAT_ADD(rx_mac_ctrl_rcvd);
9359 ESTAT_ADD(rx_xoff_entered);
9360 ESTAT_ADD(rx_frame_too_long_errors);
9361 ESTAT_ADD(rx_jabbers);
9362 ESTAT_ADD(rx_undersize_packets);
9363 ESTAT_ADD(rx_in_length_errors);
9364 ESTAT_ADD(rx_out_length_errors);
9365 ESTAT_ADD(rx_64_or_less_octet_packets);
9366 ESTAT_ADD(rx_65_to_127_octet_packets);
9367 ESTAT_ADD(rx_128_to_255_octet_packets);
9368 ESTAT_ADD(rx_256_to_511_octet_packets);
9369 ESTAT_ADD(rx_512_to_1023_octet_packets);
9370 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9371 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9372 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9373 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9374 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9376 ESTAT_ADD(tx_octets);
9377 ESTAT_ADD(tx_collisions);
9378 ESTAT_ADD(tx_xon_sent);
9379 ESTAT_ADD(tx_xoff_sent);
9380 ESTAT_ADD(tx_flow_control);
9381 ESTAT_ADD(tx_mac_errors);
9382 ESTAT_ADD(tx_single_collisions);
9383 ESTAT_ADD(tx_mult_collisions);
9384 ESTAT_ADD(tx_deferred);
9385 ESTAT_ADD(tx_excessive_collisions);
9386 ESTAT_ADD(tx_late_collisions);
9387 ESTAT_ADD(tx_collide_2times);
9388 ESTAT_ADD(tx_collide_3times);
9389 ESTAT_ADD(tx_collide_4times);
9390 ESTAT_ADD(tx_collide_5times);
9391 ESTAT_ADD(tx_collide_6times);
9392 ESTAT_ADD(tx_collide_7times);
9393 ESTAT_ADD(tx_collide_8times);
9394 ESTAT_ADD(tx_collide_9times);
9395 ESTAT_ADD(tx_collide_10times);
9396 ESTAT_ADD(tx_collide_11times);
9397 ESTAT_ADD(tx_collide_12times);
9398 ESTAT_ADD(tx_collide_13times);
9399 ESTAT_ADD(tx_collide_14times);
9400 ESTAT_ADD(tx_collide_15times);
9401 ESTAT_ADD(tx_ucast_packets);
9402 ESTAT_ADD(tx_mcast_packets);
9403 ESTAT_ADD(tx_bcast_packets);
9404 ESTAT_ADD(tx_carrier_sense_errors);
9405 ESTAT_ADD(tx_discards);
9406 ESTAT_ADD(tx_errors);
9408 ESTAT_ADD(dma_writeq_full);
9409 ESTAT_ADD(dma_write_prioq_full);
9410 ESTAT_ADD(rxbds_empty);
9411 ESTAT_ADD(rx_discards);
9412 ESTAT_ADD(rx_errors);
9413 ESTAT_ADD(rx_threshold_hit);
9415 ESTAT_ADD(dma_readq_full);
9416 ESTAT_ADD(dma_read_prioq_full);
9417 ESTAT_ADD(tx_comp_queue_full);
9419 ESTAT_ADD(ring_set_send_prod_index);
9420 ESTAT_ADD(ring_status_update);
9421 ESTAT_ADD(nic_irqs);
9422 ESTAT_ADD(nic_avoided_irqs);
9423 ESTAT_ADD(nic_tx_threshold_hit);
9428 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9429 struct rtnl_link_stats64 *stats)
9431 struct tg3 *tp = netdev_priv(dev);
9432 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9433 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9438 stats->rx_packets = old_stats->rx_packets +
9439 get_stat64(&hw_stats->rx_ucast_packets) +
9440 get_stat64(&hw_stats->rx_mcast_packets) +
9441 get_stat64(&hw_stats->rx_bcast_packets);
9443 stats->tx_packets = old_stats->tx_packets +
9444 get_stat64(&hw_stats->tx_ucast_packets) +
9445 get_stat64(&hw_stats->tx_mcast_packets) +
9446 get_stat64(&hw_stats->tx_bcast_packets);
9448 stats->rx_bytes = old_stats->rx_bytes +
9449 get_stat64(&hw_stats->rx_octets);
9450 stats->tx_bytes = old_stats->tx_bytes +
9451 get_stat64(&hw_stats->tx_octets);
9453 stats->rx_errors = old_stats->rx_errors +
9454 get_stat64(&hw_stats->rx_errors);
9455 stats->tx_errors = old_stats->tx_errors +
9456 get_stat64(&hw_stats->tx_errors) +
9457 get_stat64(&hw_stats->tx_mac_errors) +
9458 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9459 get_stat64(&hw_stats->tx_discards);
9461 stats->multicast = old_stats->multicast +
9462 get_stat64(&hw_stats->rx_mcast_packets);
9463 stats->collisions = old_stats->collisions +
9464 get_stat64(&hw_stats->tx_collisions);
9466 stats->rx_length_errors = old_stats->rx_length_errors +
9467 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9468 get_stat64(&hw_stats->rx_undersize_packets);
9470 stats->rx_over_errors = old_stats->rx_over_errors +
9471 get_stat64(&hw_stats->rxbds_empty);
9472 stats->rx_frame_errors = old_stats->rx_frame_errors +
9473 get_stat64(&hw_stats->rx_align_errors);
9474 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9475 get_stat64(&hw_stats->tx_discards);
9476 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9477 get_stat64(&hw_stats->tx_carrier_sense_errors);
9479 stats->rx_crc_errors = old_stats->rx_crc_errors +
9480 calc_crc_errors(tp);
9482 stats->rx_missed_errors = old_stats->rx_missed_errors +
9483 get_stat64(&hw_stats->rx_discards);
9485 stats->rx_dropped = tp->rx_dropped;
9490 static inline u32 calc_crc(unsigned char *buf, int len)
9498 for (j = 0; j < len; j++) {
9501 for (k = 0; k < 8; k++) {
9514 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9516 /* accept or reject all multicast frames */
9517 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9518 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9519 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9520 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9523 static void __tg3_set_rx_mode(struct net_device *dev)
9525 struct tg3 *tp = netdev_priv(dev);
9528 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9529 RX_MODE_KEEP_VLAN_TAG);
9531 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9532 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9535 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9536 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9539 if (dev->flags & IFF_PROMISC) {
9540 /* Promiscuous mode. */
9541 rx_mode |= RX_MODE_PROMISC;
9542 } else if (dev->flags & IFF_ALLMULTI) {
9543 /* Accept all multicast. */
9544 tg3_set_multi(tp, 1);
9545 } else if (netdev_mc_empty(dev)) {
9546 /* Reject all multicast. */
9547 tg3_set_multi(tp, 0);
9549 /* Accept one or more multicast(s). */
9550 struct netdev_hw_addr *ha;
9551 u32 mc_filter[4] = { 0, };
9556 netdev_for_each_mc_addr(ha, dev) {
9557 crc = calc_crc(ha->addr, ETH_ALEN);
9559 regidx = (bit & 0x60) >> 5;
9561 mc_filter[regidx] |= (1 << bit);
9564 tw32(MAC_HASH_REG_0, mc_filter[0]);
9565 tw32(MAC_HASH_REG_1, mc_filter[1]);
9566 tw32(MAC_HASH_REG_2, mc_filter[2]);
9567 tw32(MAC_HASH_REG_3, mc_filter[3]);
9570 if (rx_mode != tp->rx_mode) {
9571 tp->rx_mode = rx_mode;
9572 tw32_f(MAC_RX_MODE, rx_mode);
9577 static void tg3_set_rx_mode(struct net_device *dev)
9579 struct tg3 *tp = netdev_priv(dev);
9581 if (!netif_running(dev))
9584 tg3_full_lock(tp, 0);
9585 __tg3_set_rx_mode(dev);
9586 tg3_full_unlock(tp);
9589 #define TG3_REGDUMP_LEN (32 * 1024)
9591 static int tg3_get_regs_len(struct net_device *dev)
9593 return TG3_REGDUMP_LEN;
9596 static void tg3_get_regs(struct net_device *dev,
9597 struct ethtool_regs *regs, void *_p)
9600 struct tg3 *tp = netdev_priv(dev);
9606 memset(p, 0, TG3_REGDUMP_LEN);
9608 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9611 tg3_full_lock(tp, 0);
9613 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9614 #define GET_REG32_LOOP(base, len) \
9615 do { p = (u32 *)(orig_p + (base)); \
9616 for (i = 0; i < len; i += 4) \
9617 __GET_REG32((base) + i); \
9619 #define GET_REG32_1(reg) \
9620 do { p = (u32 *)(orig_p + (reg)); \
9621 __GET_REG32((reg)); \
9624 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9625 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9626 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9627 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9628 GET_REG32_1(SNDDATAC_MODE);
9629 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9630 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9631 GET_REG32_1(SNDBDC_MODE);
9632 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9633 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9634 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9635 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9636 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9637 GET_REG32_1(RCVDCC_MODE);
9638 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9639 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9640 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9641 GET_REG32_1(MBFREE_MODE);
9642 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9643 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9644 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9645 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9646 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9647 GET_REG32_1(RX_CPU_MODE);
9648 GET_REG32_1(RX_CPU_STATE);
9649 GET_REG32_1(RX_CPU_PGMCTR);
9650 GET_REG32_1(RX_CPU_HWBKPT);
9651 GET_REG32_1(TX_CPU_MODE);
9652 GET_REG32_1(TX_CPU_STATE);
9653 GET_REG32_1(TX_CPU_PGMCTR);
9654 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9655 GET_REG32_LOOP(FTQ_RESET, 0x120);
9656 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9657 GET_REG32_1(DMAC_MODE);
9658 GET_REG32_LOOP(GRC_MODE, 0x4c);
9659 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9660 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9663 #undef GET_REG32_LOOP
9666 tg3_full_unlock(tp);
9669 static int tg3_get_eeprom_len(struct net_device *dev)
9671 struct tg3 *tp = netdev_priv(dev);
9673 return tp->nvram_size;
9676 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9678 struct tg3 *tp = netdev_priv(dev);
9681 u32 i, offset, len, b_offset, b_count;
9684 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9687 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9690 offset = eeprom->offset;
9694 eeprom->magic = TG3_EEPROM_MAGIC;
9697 /* adjustments to start on required 4 byte boundary */
9698 b_offset = offset & 3;
9699 b_count = 4 - b_offset;
9700 if (b_count > len) {
9701 /* i.e. offset=1 len=2 */
9704 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9707 memcpy(data, ((char *)&val) + b_offset, b_count);
9710 eeprom->len += b_count;
9713 /* read bytes upto the last 4 byte boundary */
9714 pd = &data[eeprom->len];
9715 for (i = 0; i < (len - (len & 3)); i += 4) {
9716 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9721 memcpy(pd + i, &val, 4);
9726 /* read last bytes not ending on 4 byte boundary */
9727 pd = &data[eeprom->len];
9729 b_offset = offset + len - b_count;
9730 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9733 memcpy(pd, &val, b_count);
9734 eeprom->len += b_count;
9739 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9741 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9743 struct tg3 *tp = netdev_priv(dev);
9745 u32 offset, len, b_offset, odd_len;
9749 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9752 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9753 eeprom->magic != TG3_EEPROM_MAGIC)
9756 offset = eeprom->offset;
9759 if ((b_offset = (offset & 3))) {
9760 /* adjustments to start on required 4 byte boundary */
9761 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9772 /* adjustments to end on required 4 byte boundary */
9774 len = (len + 3) & ~3;
9775 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9781 if (b_offset || odd_len) {
9782 buf = kmalloc(len, GFP_KERNEL);
9786 memcpy(buf, &start, 4);
9788 memcpy(buf+len-4, &end, 4);
9789 memcpy(buf + b_offset, data, eeprom->len);
9792 ret = tg3_nvram_write_block(tp, offset, len, buf);
9800 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9802 struct tg3 *tp = netdev_priv(dev);
9804 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9805 struct phy_device *phydev;
9806 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9808 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9809 return phy_ethtool_gset(phydev, cmd);
9812 cmd->supported = (SUPPORTED_Autoneg);
9814 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9815 cmd->supported |= (SUPPORTED_1000baseT_Half |
9816 SUPPORTED_1000baseT_Full);
9818 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9819 cmd->supported |= (SUPPORTED_100baseT_Half |
9820 SUPPORTED_100baseT_Full |
9821 SUPPORTED_10baseT_Half |
9822 SUPPORTED_10baseT_Full |
9824 cmd->port = PORT_TP;
9826 cmd->supported |= SUPPORTED_FIBRE;
9827 cmd->port = PORT_FIBRE;
9830 cmd->advertising = tp->link_config.advertising;
9831 if (netif_running(dev)) {
9832 cmd->speed = tp->link_config.active_speed;
9833 cmd->duplex = tp->link_config.active_duplex;
9835 cmd->speed = SPEED_INVALID;
9836 cmd->duplex = DUPLEX_INVALID;
9838 cmd->phy_address = tp->phy_addr;
9839 cmd->transceiver = XCVR_INTERNAL;
9840 cmd->autoneg = tp->link_config.autoneg;
9846 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9848 struct tg3 *tp = netdev_priv(dev);
9850 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9851 struct phy_device *phydev;
9852 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9854 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9855 return phy_ethtool_sset(phydev, cmd);
9858 if (cmd->autoneg != AUTONEG_ENABLE &&
9859 cmd->autoneg != AUTONEG_DISABLE)
9862 if (cmd->autoneg == AUTONEG_DISABLE &&
9863 cmd->duplex != DUPLEX_FULL &&
9864 cmd->duplex != DUPLEX_HALF)
9867 if (cmd->autoneg == AUTONEG_ENABLE) {
9868 u32 mask = ADVERTISED_Autoneg |
9870 ADVERTISED_Asym_Pause;
9872 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9873 mask |= ADVERTISED_1000baseT_Half |
9874 ADVERTISED_1000baseT_Full;
9876 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9877 mask |= ADVERTISED_100baseT_Half |
9878 ADVERTISED_100baseT_Full |
9879 ADVERTISED_10baseT_Half |
9880 ADVERTISED_10baseT_Full |
9883 mask |= ADVERTISED_FIBRE;
9885 if (cmd->advertising & ~mask)
9888 mask &= (ADVERTISED_1000baseT_Half |
9889 ADVERTISED_1000baseT_Full |
9890 ADVERTISED_100baseT_Half |
9891 ADVERTISED_100baseT_Full |
9892 ADVERTISED_10baseT_Half |
9893 ADVERTISED_10baseT_Full);
9895 cmd->advertising &= mask;
9897 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9898 if (cmd->speed != SPEED_1000)
9901 if (cmd->duplex != DUPLEX_FULL)
9904 if (cmd->speed != SPEED_100 &&
9905 cmd->speed != SPEED_10)
9910 tg3_full_lock(tp, 0);
9912 tp->link_config.autoneg = cmd->autoneg;
9913 if (cmd->autoneg == AUTONEG_ENABLE) {
9914 tp->link_config.advertising = (cmd->advertising |
9915 ADVERTISED_Autoneg);
9916 tp->link_config.speed = SPEED_INVALID;
9917 tp->link_config.duplex = DUPLEX_INVALID;
9919 tp->link_config.advertising = 0;
9920 tp->link_config.speed = cmd->speed;
9921 tp->link_config.duplex = cmd->duplex;
9924 tp->link_config.orig_speed = tp->link_config.speed;
9925 tp->link_config.orig_duplex = tp->link_config.duplex;
9926 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9928 if (netif_running(dev))
9929 tg3_setup_phy(tp, 1);
9931 tg3_full_unlock(tp);
9936 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9938 struct tg3 *tp = netdev_priv(dev);
9940 strcpy(info->driver, DRV_MODULE_NAME);
9941 strcpy(info->version, DRV_MODULE_VERSION);
9942 strcpy(info->fw_version, tp->fw_ver);
9943 strcpy(info->bus_info, pci_name(tp->pdev));
9946 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9948 struct tg3 *tp = netdev_priv(dev);
9950 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9951 device_can_wakeup(&tp->pdev->dev))
9952 wol->supported = WAKE_MAGIC;
9956 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9957 device_can_wakeup(&tp->pdev->dev))
9958 wol->wolopts = WAKE_MAGIC;
9959 memset(&wol->sopass, 0, sizeof(wol->sopass));
9962 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9964 struct tg3 *tp = netdev_priv(dev);
9965 struct device *dp = &tp->pdev->dev;
9967 if (wol->wolopts & ~WAKE_MAGIC)
9969 if ((wol->wolopts & WAKE_MAGIC) &&
9970 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9973 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
9975 spin_lock_bh(&tp->lock);
9976 if (device_may_wakeup(dp))
9977 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9979 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9980 spin_unlock_bh(&tp->lock);
9986 static u32 tg3_get_msglevel(struct net_device *dev)
9988 struct tg3 *tp = netdev_priv(dev);
9989 return tp->msg_enable;
9992 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9994 struct tg3 *tp = netdev_priv(dev);
9995 tp->msg_enable = value;
9998 static int tg3_set_tso(struct net_device *dev, u32 value)
10000 struct tg3 *tp = netdev_priv(dev);
10002 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
10007 if ((dev->features & NETIF_F_IPV6_CSUM) &&
10008 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
10009 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
10011 dev->features |= NETIF_F_TSO6;
10012 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
10013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10014 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
10015 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
10016 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
10017 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10018 dev->features |= NETIF_F_TSO_ECN;
10020 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
10022 return ethtool_op_set_tso(dev, value);
10025 static int tg3_nway_reset(struct net_device *dev)
10027 struct tg3 *tp = netdev_priv(dev);
10030 if (!netif_running(dev))
10033 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10036 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10037 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10039 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10043 spin_lock_bh(&tp->lock);
10045 tg3_readphy(tp, MII_BMCR, &bmcr);
10046 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10047 ((bmcr & BMCR_ANENABLE) ||
10048 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10049 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10053 spin_unlock_bh(&tp->lock);
10059 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10061 struct tg3 *tp = netdev_priv(dev);
10063 ering->rx_max_pending = tp->rx_std_ring_mask;
10064 ering->rx_mini_max_pending = 0;
10065 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10066 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10068 ering->rx_jumbo_max_pending = 0;
10070 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10072 ering->rx_pending = tp->rx_pending;
10073 ering->rx_mini_pending = 0;
10074 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10075 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10077 ering->rx_jumbo_pending = 0;
10079 ering->tx_pending = tp->napi[0].tx_pending;
10082 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10084 struct tg3 *tp = netdev_priv(dev);
10085 int i, irq_sync = 0, err = 0;
10087 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10088 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10089 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10090 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10091 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10092 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10095 if (netif_running(dev)) {
10097 tg3_netif_stop(tp);
10101 tg3_full_lock(tp, irq_sync);
10103 tp->rx_pending = ering->rx_pending;
10105 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10106 tp->rx_pending > 63)
10107 tp->rx_pending = 63;
10108 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10110 for (i = 0; i < tp->irq_max; i++)
10111 tp->napi[i].tx_pending = ering->tx_pending;
10113 if (netif_running(dev)) {
10114 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10115 err = tg3_restart_hw(tp, 1);
10117 tg3_netif_start(tp);
10120 tg3_full_unlock(tp);
10122 if (irq_sync && !err)
10128 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10130 struct tg3 *tp = netdev_priv(dev);
10132 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10134 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10135 epause->rx_pause = 1;
10137 epause->rx_pause = 0;
10139 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10140 epause->tx_pause = 1;
10142 epause->tx_pause = 0;
10145 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10147 struct tg3 *tp = netdev_priv(dev);
10150 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10152 struct phy_device *phydev;
10154 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10156 if (!(phydev->supported & SUPPORTED_Pause) ||
10157 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10158 (epause->rx_pause != epause->tx_pause)))
10161 tp->link_config.flowctrl = 0;
10162 if (epause->rx_pause) {
10163 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10165 if (epause->tx_pause) {
10166 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10167 newadv = ADVERTISED_Pause;
10169 newadv = ADVERTISED_Pause |
10170 ADVERTISED_Asym_Pause;
10171 } else if (epause->tx_pause) {
10172 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10173 newadv = ADVERTISED_Asym_Pause;
10177 if (epause->autoneg)
10178 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10180 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10182 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10183 u32 oldadv = phydev->advertising &
10184 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10185 if (oldadv != newadv) {
10186 phydev->advertising &=
10187 ~(ADVERTISED_Pause |
10188 ADVERTISED_Asym_Pause);
10189 phydev->advertising |= newadv;
10190 if (phydev->autoneg) {
10192 * Always renegotiate the link to
10193 * inform our link partner of our
10194 * flow control settings, even if the
10195 * flow control is forced. Let
10196 * tg3_adjust_link() do the final
10197 * flow control setup.
10199 return phy_start_aneg(phydev);
10203 if (!epause->autoneg)
10204 tg3_setup_flow_control(tp, 0, 0);
10206 tp->link_config.orig_advertising &=
10207 ~(ADVERTISED_Pause |
10208 ADVERTISED_Asym_Pause);
10209 tp->link_config.orig_advertising |= newadv;
10214 if (netif_running(dev)) {
10215 tg3_netif_stop(tp);
10219 tg3_full_lock(tp, irq_sync);
10221 if (epause->autoneg)
10222 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10224 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10225 if (epause->rx_pause)
10226 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10228 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10229 if (epause->tx_pause)
10230 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10232 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10234 if (netif_running(dev)) {
10235 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10236 err = tg3_restart_hw(tp, 1);
10238 tg3_netif_start(tp);
10241 tg3_full_unlock(tp);
10247 static u32 tg3_get_rx_csum(struct net_device *dev)
10249 struct tg3 *tp = netdev_priv(dev);
10250 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10253 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10255 struct tg3 *tp = netdev_priv(dev);
10257 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10263 spin_lock_bh(&tp->lock);
10265 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10267 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10268 spin_unlock_bh(&tp->lock);
10273 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10275 struct tg3 *tp = netdev_priv(dev);
10277 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10283 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10284 ethtool_op_set_tx_ipv6_csum(dev, data);
10286 ethtool_op_set_tx_csum(dev, data);
10291 static int tg3_get_sset_count(struct net_device *dev, int sset)
10295 return TG3_NUM_TEST;
10297 return TG3_NUM_STATS;
10299 return -EOPNOTSUPP;
10303 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10305 switch (stringset) {
10307 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10310 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10313 WARN_ON(1); /* we need a WARN() */
10318 static int tg3_phys_id(struct net_device *dev, u32 data)
10320 struct tg3 *tp = netdev_priv(dev);
10323 if (!netif_running(tp->dev))
10327 data = UINT_MAX / 2;
10329 for (i = 0; i < (data * 2); i++) {
10331 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10332 LED_CTRL_1000MBPS_ON |
10333 LED_CTRL_100MBPS_ON |
10334 LED_CTRL_10MBPS_ON |
10335 LED_CTRL_TRAFFIC_OVERRIDE |
10336 LED_CTRL_TRAFFIC_BLINK |
10337 LED_CTRL_TRAFFIC_LED);
10340 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10341 LED_CTRL_TRAFFIC_OVERRIDE);
10343 if (msleep_interruptible(500))
10346 tw32(MAC_LED_CTRL, tp->led_ctrl);
10350 static void tg3_get_ethtool_stats(struct net_device *dev,
10351 struct ethtool_stats *estats, u64 *tmp_stats)
10353 struct tg3 *tp = netdev_priv(dev);
10354 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10357 #define NVRAM_TEST_SIZE 0x100
10358 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10359 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10360 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10361 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10362 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10364 static int tg3_test_nvram(struct tg3 *tp)
10368 int i, j, k, err = 0, size;
10370 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10373 if (tg3_nvram_read(tp, 0, &magic) != 0)
10376 if (magic == TG3_EEPROM_MAGIC)
10377 size = NVRAM_TEST_SIZE;
10378 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10379 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10380 TG3_EEPROM_SB_FORMAT_1) {
10381 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10382 case TG3_EEPROM_SB_REVISION_0:
10383 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10385 case TG3_EEPROM_SB_REVISION_2:
10386 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10388 case TG3_EEPROM_SB_REVISION_3:
10389 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10396 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10397 size = NVRAM_SELFBOOT_HW_SIZE;
10401 buf = kmalloc(size, GFP_KERNEL);
10406 for (i = 0, j = 0; i < size; i += 4, j++) {
10407 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10414 /* Selfboot format */
10415 magic = be32_to_cpu(buf[0]);
10416 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10417 TG3_EEPROM_MAGIC_FW) {
10418 u8 *buf8 = (u8 *) buf, csum8 = 0;
10420 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10421 TG3_EEPROM_SB_REVISION_2) {
10422 /* For rev 2, the csum doesn't include the MBA. */
10423 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10425 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10428 for (i = 0; i < size; i++)
10441 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10442 TG3_EEPROM_MAGIC_HW) {
10443 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10444 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10445 u8 *buf8 = (u8 *) buf;
10447 /* Separate the parity bits and the data bytes. */
10448 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10449 if ((i == 0) || (i == 8)) {
10453 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10454 parity[k++] = buf8[i] & msk;
10456 } else if (i == 16) {
10460 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10461 parity[k++] = buf8[i] & msk;
10464 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10465 parity[k++] = buf8[i] & msk;
10468 data[j++] = buf8[i];
10472 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10473 u8 hw8 = hweight8(data[i]);
10475 if ((hw8 & 0x1) && parity[i])
10477 else if (!(hw8 & 0x1) && !parity[i])
10486 /* Bootstrap checksum at offset 0x10 */
10487 csum = calc_crc((unsigned char *) buf, 0x10);
10488 if (csum != le32_to_cpu(buf[0x10/4]))
10491 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10492 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10493 if (csum != le32_to_cpu(buf[0xfc/4]))
10496 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
10497 /* The data is in little-endian format in NVRAM.
10498 * Use the big-endian read routines to preserve
10499 * the byte order as it exists in NVRAM.
10501 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
10505 i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10506 PCI_VPD_LRDT_RO_DATA);
10508 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10512 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10515 i += PCI_VPD_LRDT_TAG_SIZE;
10516 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10517 PCI_VPD_RO_KEYWORD_CHKSUM);
10521 j += PCI_VPD_INFO_FLD_HDR_SIZE;
10523 for (i = 0; i <= j; i++)
10524 csum8 += ((u8 *)buf)[i];
10538 #define TG3_SERDES_TIMEOUT_SEC 2
10539 #define TG3_COPPER_TIMEOUT_SEC 6
10541 static int tg3_test_link(struct tg3 *tp)
10545 if (!netif_running(tp->dev))
10548 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10549 max = TG3_SERDES_TIMEOUT_SEC;
10551 max = TG3_COPPER_TIMEOUT_SEC;
10553 for (i = 0; i < max; i++) {
10554 if (netif_carrier_ok(tp->dev))
10557 if (msleep_interruptible(1000))
10564 /* Only test the commonly used registers */
10565 static int tg3_test_registers(struct tg3 *tp)
10567 int i, is_5705, is_5750;
10568 u32 offset, read_mask, write_mask, val, save_val, read_val;
10572 #define TG3_FL_5705 0x1
10573 #define TG3_FL_NOT_5705 0x2
10574 #define TG3_FL_NOT_5788 0x4
10575 #define TG3_FL_NOT_5750 0x8
10579 /* MAC Control Registers */
10580 { MAC_MODE, TG3_FL_NOT_5705,
10581 0x00000000, 0x00ef6f8c },
10582 { MAC_MODE, TG3_FL_5705,
10583 0x00000000, 0x01ef6b8c },
10584 { MAC_STATUS, TG3_FL_NOT_5705,
10585 0x03800107, 0x00000000 },
10586 { MAC_STATUS, TG3_FL_5705,
10587 0x03800100, 0x00000000 },
10588 { MAC_ADDR_0_HIGH, 0x0000,
10589 0x00000000, 0x0000ffff },
10590 { MAC_ADDR_0_LOW, 0x0000,
10591 0x00000000, 0xffffffff },
10592 { MAC_RX_MTU_SIZE, 0x0000,
10593 0x00000000, 0x0000ffff },
10594 { MAC_TX_MODE, 0x0000,
10595 0x00000000, 0x00000070 },
10596 { MAC_TX_LENGTHS, 0x0000,
10597 0x00000000, 0x00003fff },
10598 { MAC_RX_MODE, TG3_FL_NOT_5705,
10599 0x00000000, 0x000007fc },
10600 { MAC_RX_MODE, TG3_FL_5705,
10601 0x00000000, 0x000007dc },
10602 { MAC_HASH_REG_0, 0x0000,
10603 0x00000000, 0xffffffff },
10604 { MAC_HASH_REG_1, 0x0000,
10605 0x00000000, 0xffffffff },
10606 { MAC_HASH_REG_2, 0x0000,
10607 0x00000000, 0xffffffff },
10608 { MAC_HASH_REG_3, 0x0000,
10609 0x00000000, 0xffffffff },
10611 /* Receive Data and Receive BD Initiator Control Registers. */
10612 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10613 0x00000000, 0xffffffff },
10614 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10615 0x00000000, 0xffffffff },
10616 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10617 0x00000000, 0x00000003 },
10618 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10619 0x00000000, 0xffffffff },
10620 { RCVDBDI_STD_BD+0, 0x0000,
10621 0x00000000, 0xffffffff },
10622 { RCVDBDI_STD_BD+4, 0x0000,
10623 0x00000000, 0xffffffff },
10624 { RCVDBDI_STD_BD+8, 0x0000,
10625 0x00000000, 0xffff0002 },
10626 { RCVDBDI_STD_BD+0xc, 0x0000,
10627 0x00000000, 0xffffffff },
10629 /* Receive BD Initiator Control Registers. */
10630 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10631 0x00000000, 0xffffffff },
10632 { RCVBDI_STD_THRESH, TG3_FL_5705,
10633 0x00000000, 0x000003ff },
10634 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10635 0x00000000, 0xffffffff },
10637 /* Host Coalescing Control Registers. */
10638 { HOSTCC_MODE, TG3_FL_NOT_5705,
10639 0x00000000, 0x00000004 },
10640 { HOSTCC_MODE, TG3_FL_5705,
10641 0x00000000, 0x000000f6 },
10642 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10643 0x00000000, 0xffffffff },
10644 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10645 0x00000000, 0x000003ff },
10646 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10647 0x00000000, 0xffffffff },
10648 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10649 0x00000000, 0x000003ff },
10650 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10651 0x00000000, 0xffffffff },
10652 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10653 0x00000000, 0x000000ff },
10654 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10655 0x00000000, 0xffffffff },
10656 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10657 0x00000000, 0x000000ff },
10658 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10659 0x00000000, 0xffffffff },
10660 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10661 0x00000000, 0xffffffff },
10662 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10663 0x00000000, 0xffffffff },
10664 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10665 0x00000000, 0x000000ff },
10666 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10667 0x00000000, 0xffffffff },
10668 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10669 0x00000000, 0x000000ff },
10670 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10671 0x00000000, 0xffffffff },
10672 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10673 0x00000000, 0xffffffff },
10674 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10675 0x00000000, 0xffffffff },
10676 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10677 0x00000000, 0xffffffff },
10678 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10679 0x00000000, 0xffffffff },
10680 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10681 0xffffffff, 0x00000000 },
10682 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10683 0xffffffff, 0x00000000 },
10685 /* Buffer Manager Control Registers. */
10686 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10687 0x00000000, 0x007fff80 },
10688 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10689 0x00000000, 0x007fffff },
10690 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10691 0x00000000, 0x0000003f },
10692 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10693 0x00000000, 0x000001ff },
10694 { BUFMGR_MB_HIGH_WATER, 0x0000,
10695 0x00000000, 0x000001ff },
10696 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10697 0xffffffff, 0x00000000 },
10698 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10699 0xffffffff, 0x00000000 },
10701 /* Mailbox Registers */
10702 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10703 0x00000000, 0x000001ff },
10704 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10705 0x00000000, 0x000001ff },
10706 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10707 0x00000000, 0x000007ff },
10708 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10709 0x00000000, 0x000001ff },
10711 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10714 is_5705 = is_5750 = 0;
10715 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10717 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10721 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10722 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10725 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10728 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10729 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10732 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10735 offset = (u32) reg_tbl[i].offset;
10736 read_mask = reg_tbl[i].read_mask;
10737 write_mask = reg_tbl[i].write_mask;
10739 /* Save the original register content */
10740 save_val = tr32(offset);
10742 /* Determine the read-only value. */
10743 read_val = save_val & read_mask;
10745 /* Write zero to the register, then make sure the read-only bits
10746 * are not changed and the read/write bits are all zeros.
10750 val = tr32(offset);
10752 /* Test the read-only and read/write bits. */
10753 if (((val & read_mask) != read_val) || (val & write_mask))
10756 /* Write ones to all the bits defined by RdMask and WrMask, then
10757 * make sure the read-only bits are not changed and the
10758 * read/write bits are all ones.
10760 tw32(offset, read_mask | write_mask);
10762 val = tr32(offset);
10764 /* Test the read-only bits. */
10765 if ((val & read_mask) != read_val)
10768 /* Test the read/write bits. */
10769 if ((val & write_mask) != write_mask)
10772 tw32(offset, save_val);
10778 if (netif_msg_hw(tp))
10779 netdev_err(tp->dev,
10780 "Register test failed at offset %x\n", offset);
10781 tw32(offset, save_val);
10785 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10787 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10791 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10792 for (j = 0; j < len; j += 4) {
10795 tg3_write_mem(tp, offset + j, test_pattern[i]);
10796 tg3_read_mem(tp, offset + j, &val);
10797 if (val != test_pattern[i])
10804 static int tg3_test_memory(struct tg3 *tp)
10806 static struct mem_entry {
10809 } mem_tbl_570x[] = {
10810 { 0x00000000, 0x00b50},
10811 { 0x00002000, 0x1c000},
10812 { 0xffffffff, 0x00000}
10813 }, mem_tbl_5705[] = {
10814 { 0x00000100, 0x0000c},
10815 { 0x00000200, 0x00008},
10816 { 0x00004000, 0x00800},
10817 { 0x00006000, 0x01000},
10818 { 0x00008000, 0x02000},
10819 { 0x00010000, 0x0e000},
10820 { 0xffffffff, 0x00000}
10821 }, mem_tbl_5755[] = {
10822 { 0x00000200, 0x00008},
10823 { 0x00004000, 0x00800},
10824 { 0x00006000, 0x00800},
10825 { 0x00008000, 0x02000},
10826 { 0x00010000, 0x0c000},
10827 { 0xffffffff, 0x00000}
10828 }, mem_tbl_5906[] = {
10829 { 0x00000200, 0x00008},
10830 { 0x00004000, 0x00400},
10831 { 0x00006000, 0x00400},
10832 { 0x00008000, 0x01000},
10833 { 0x00010000, 0x01000},
10834 { 0xffffffff, 0x00000}
10835 }, mem_tbl_5717[] = {
10836 { 0x00000200, 0x00008},
10837 { 0x00010000, 0x0a000},
10838 { 0x00020000, 0x13c00},
10839 { 0xffffffff, 0x00000}
10840 }, mem_tbl_57765[] = {
10841 { 0x00000200, 0x00008},
10842 { 0x00004000, 0x00800},
10843 { 0x00006000, 0x09800},
10844 { 0x00010000, 0x0a000},
10845 { 0xffffffff, 0x00000}
10847 struct mem_entry *mem_tbl;
10851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10852 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10853 mem_tbl = mem_tbl_5717;
10854 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10855 mem_tbl = mem_tbl_57765;
10856 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10857 mem_tbl = mem_tbl_5755;
10858 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10859 mem_tbl = mem_tbl_5906;
10860 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10861 mem_tbl = mem_tbl_5705;
10863 mem_tbl = mem_tbl_570x;
10865 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10866 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10874 #define TG3_MAC_LOOPBACK 0
10875 #define TG3_PHY_LOOPBACK 1
10877 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10879 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10880 u32 desc_idx, coal_now;
10881 struct sk_buff *skb, *rx_skb;
10884 int num_pkts, tx_len, rx_len, i, err;
10885 struct tg3_rx_buffer_desc *desc;
10886 struct tg3_napi *tnapi, *rnapi;
10887 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10889 tnapi = &tp->napi[0];
10890 rnapi = &tp->napi[0];
10891 if (tp->irq_cnt > 1) {
10892 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10893 rnapi = &tp->napi[1];
10894 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10895 tnapi = &tp->napi[1];
10897 coal_now = tnapi->coal_now | rnapi->coal_now;
10899 if (loopback_mode == TG3_MAC_LOOPBACK) {
10900 /* HW errata - mac loopback fails in some cases on 5780.
10901 * Normal traffic and PHY loopback are not affected by
10902 * errata. Also, the MAC loopback test is deprecated for
10903 * all newer ASIC revisions.
10905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10906 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
10909 mac_mode = tp->mac_mode &
10910 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10911 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
10912 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10913 mac_mode |= MAC_MODE_LINK_POLARITY;
10914 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10915 mac_mode |= MAC_MODE_PORT_MODE_MII;
10917 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10918 tw32(MAC_MODE, mac_mode);
10919 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10922 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10923 tg3_phy_fet_toggle_apd(tp, false);
10924 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10926 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10928 tg3_phy_toggle_automdix(tp, 0);
10930 tg3_writephy(tp, MII_BMCR, val);
10933 mac_mode = tp->mac_mode &
10934 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10935 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10936 tg3_writephy(tp, MII_TG3_FET_PTEST,
10937 MII_TG3_FET_PTEST_FRC_TX_LINK |
10938 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10939 /* The write needs to be flushed for the AC131 */
10940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10941 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10942 mac_mode |= MAC_MODE_PORT_MODE_MII;
10944 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10946 /* reset to prevent losing 1st rx packet intermittently */
10947 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10948 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10950 tw32_f(MAC_RX_MODE, tp->rx_mode);
10952 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10953 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10954 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10955 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10956 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10957 mac_mode |= MAC_MODE_LINK_POLARITY;
10958 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10959 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10961 tw32(MAC_MODE, mac_mode);
10963 /* Wait for link */
10964 for (i = 0; i < 100; i++) {
10965 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
10976 skb = netdev_alloc_skb(tp->dev, tx_len);
10980 tx_data = skb_put(skb, tx_len);
10981 memcpy(tx_data, tp->dev->dev_addr, 6);
10982 memset(tx_data + 6, 0x0, 8);
10984 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10986 for (i = 14; i < tx_len; i++)
10987 tx_data[i] = (u8) (i & 0xff);
10989 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10990 if (pci_dma_mapping_error(tp->pdev, map)) {
10991 dev_kfree_skb(skb);
10995 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11000 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11004 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
11009 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11010 tr32_mailbox(tnapi->prodmbox);
11014 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11015 for (i = 0; i < 35; i++) {
11016 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11021 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11022 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11023 if ((tx_idx == tnapi->tx_prod) &&
11024 (rx_idx == (rx_start_idx + num_pkts)))
11028 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
11029 dev_kfree_skb(skb);
11031 if (tx_idx != tnapi->tx_prod)
11034 if (rx_idx != rx_start_idx + num_pkts)
11037 desc = &rnapi->rx_rcb[rx_start_idx];
11038 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11039 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11040 if (opaque_key != RXD_OPAQUE_RING_STD)
11043 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11044 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11047 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11048 if (rx_len != tx_len)
11051 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11053 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11054 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11056 for (i = 14; i < tx_len; i++) {
11057 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11062 /* tg3_free_rings will unmap and free the rx_skb */
11067 #define TG3_MAC_LOOPBACK_FAILED 1
11068 #define TG3_PHY_LOOPBACK_FAILED 2
11069 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
11070 TG3_PHY_LOOPBACK_FAILED)
11072 static int tg3_test_loopback(struct tg3 *tp)
11075 u32 eee_cap, cpmuctrl = 0;
11077 if (!netif_running(tp->dev))
11078 return TG3_LOOPBACK_FAILED;
11080 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11081 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11083 err = tg3_reset_hw(tp, 1);
11085 err = TG3_LOOPBACK_FAILED;
11089 /* Turn off gphy autopowerdown. */
11090 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11091 tg3_phy_toggle_apd(tp, false);
11093 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11097 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11099 /* Wait for up to 40 microseconds to acquire lock. */
11100 for (i = 0; i < 4; i++) {
11101 status = tr32(TG3_CPMU_MUTEX_GNT);
11102 if (status == CPMU_MUTEX_GNT_DRIVER)
11107 if (status != CPMU_MUTEX_GNT_DRIVER) {
11108 err = TG3_LOOPBACK_FAILED;
11112 /* Turn off link-based power management. */
11113 cpmuctrl = tr32(TG3_CPMU_CTRL);
11114 tw32(TG3_CPMU_CTRL,
11115 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11116 CPMU_CTRL_LINK_AWARE_MODE));
11119 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11120 err |= TG3_MAC_LOOPBACK_FAILED;
11122 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11123 tw32(TG3_CPMU_CTRL, cpmuctrl);
11125 /* Release the mutex */
11126 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11130 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11131 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11132 err |= TG3_PHY_LOOPBACK_FAILED;
11135 /* Re-enable gphy autopowerdown. */
11136 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11137 tg3_phy_toggle_apd(tp, true);
11140 tp->phy_flags |= eee_cap;
11145 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11148 struct tg3 *tp = netdev_priv(dev);
11150 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11153 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11155 if (tg3_test_nvram(tp) != 0) {
11156 etest->flags |= ETH_TEST_FL_FAILED;
11159 if (tg3_test_link(tp) != 0) {
11160 etest->flags |= ETH_TEST_FL_FAILED;
11163 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11164 int err, err2 = 0, irq_sync = 0;
11166 if (netif_running(dev)) {
11168 tg3_netif_stop(tp);
11172 tg3_full_lock(tp, irq_sync);
11174 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11175 err = tg3_nvram_lock(tp);
11176 tg3_halt_cpu(tp, RX_CPU_BASE);
11177 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11178 tg3_halt_cpu(tp, TX_CPU_BASE);
11180 tg3_nvram_unlock(tp);
11182 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11185 if (tg3_test_registers(tp) != 0) {
11186 etest->flags |= ETH_TEST_FL_FAILED;
11189 if (tg3_test_memory(tp) != 0) {
11190 etest->flags |= ETH_TEST_FL_FAILED;
11193 if ((data[4] = tg3_test_loopback(tp)) != 0)
11194 etest->flags |= ETH_TEST_FL_FAILED;
11196 tg3_full_unlock(tp);
11198 if (tg3_test_interrupt(tp) != 0) {
11199 etest->flags |= ETH_TEST_FL_FAILED;
11203 tg3_full_lock(tp, 0);
11205 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11206 if (netif_running(dev)) {
11207 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11208 err2 = tg3_restart_hw(tp, 1);
11210 tg3_netif_start(tp);
11213 tg3_full_unlock(tp);
11215 if (irq_sync && !err2)
11218 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11219 tg3_power_down(tp);
11223 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11225 struct mii_ioctl_data *data = if_mii(ifr);
11226 struct tg3 *tp = netdev_priv(dev);
11229 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11230 struct phy_device *phydev;
11231 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11233 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11234 return phy_mii_ioctl(phydev, ifr, cmd);
11239 data->phy_id = tp->phy_addr;
11242 case SIOCGMIIREG: {
11245 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11246 break; /* We have no PHY */
11248 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11249 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11250 !netif_running(dev)))
11253 spin_lock_bh(&tp->lock);
11254 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11255 spin_unlock_bh(&tp->lock);
11257 data->val_out = mii_regval;
11263 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11264 break; /* We have no PHY */
11266 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11267 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11268 !netif_running(dev)))
11271 spin_lock_bh(&tp->lock);
11272 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11273 spin_unlock_bh(&tp->lock);
11281 return -EOPNOTSUPP;
11284 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11286 struct tg3 *tp = netdev_priv(dev);
11288 memcpy(ec, &tp->coal, sizeof(*ec));
11292 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11294 struct tg3 *tp = netdev_priv(dev);
11295 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11296 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11298 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11299 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11300 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11301 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11302 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11305 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11306 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11307 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11308 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11309 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11310 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11311 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11312 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11313 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11314 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11317 /* No rx interrupts will be generated if both are zero */
11318 if ((ec->rx_coalesce_usecs == 0) &&
11319 (ec->rx_max_coalesced_frames == 0))
11322 /* No tx interrupts will be generated if both are zero */
11323 if ((ec->tx_coalesce_usecs == 0) &&
11324 (ec->tx_max_coalesced_frames == 0))
11327 /* Only copy relevant parameters, ignore all others. */
11328 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11329 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11330 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11331 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11332 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11333 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11334 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11335 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11336 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11338 if (netif_running(dev)) {
11339 tg3_full_lock(tp, 0);
11340 __tg3_set_coalesce(tp, &tp->coal);
11341 tg3_full_unlock(tp);
11346 static const struct ethtool_ops tg3_ethtool_ops = {
11347 .get_settings = tg3_get_settings,
11348 .set_settings = tg3_set_settings,
11349 .get_drvinfo = tg3_get_drvinfo,
11350 .get_regs_len = tg3_get_regs_len,
11351 .get_regs = tg3_get_regs,
11352 .get_wol = tg3_get_wol,
11353 .set_wol = tg3_set_wol,
11354 .get_msglevel = tg3_get_msglevel,
11355 .set_msglevel = tg3_set_msglevel,
11356 .nway_reset = tg3_nway_reset,
11357 .get_link = ethtool_op_get_link,
11358 .get_eeprom_len = tg3_get_eeprom_len,
11359 .get_eeprom = tg3_get_eeprom,
11360 .set_eeprom = tg3_set_eeprom,
11361 .get_ringparam = tg3_get_ringparam,
11362 .set_ringparam = tg3_set_ringparam,
11363 .get_pauseparam = tg3_get_pauseparam,
11364 .set_pauseparam = tg3_set_pauseparam,
11365 .get_rx_csum = tg3_get_rx_csum,
11366 .set_rx_csum = tg3_set_rx_csum,
11367 .set_tx_csum = tg3_set_tx_csum,
11368 .set_sg = ethtool_op_set_sg,
11369 .set_tso = tg3_set_tso,
11370 .self_test = tg3_self_test,
11371 .get_strings = tg3_get_strings,
11372 .phys_id = tg3_phys_id,
11373 .get_ethtool_stats = tg3_get_ethtool_stats,
11374 .get_coalesce = tg3_get_coalesce,
11375 .set_coalesce = tg3_set_coalesce,
11376 .get_sset_count = tg3_get_sset_count,
11379 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11381 u32 cursize, val, magic;
11383 tp->nvram_size = EEPROM_CHIP_SIZE;
11385 if (tg3_nvram_read(tp, 0, &magic) != 0)
11388 if ((magic != TG3_EEPROM_MAGIC) &&
11389 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11390 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11394 * Size the chip by reading offsets at increasing powers of two.
11395 * When we encounter our validation signature, we know the addressing
11396 * has wrapped around, and thus have our chip size.
11400 while (cursize < tp->nvram_size) {
11401 if (tg3_nvram_read(tp, cursize, &val) != 0)
11410 tp->nvram_size = cursize;
11413 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11417 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11418 tg3_nvram_read(tp, 0, &val) != 0)
11421 /* Selfboot format */
11422 if (val != TG3_EEPROM_MAGIC) {
11423 tg3_get_eeprom_size(tp);
11427 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11429 /* This is confusing. We want to operate on the
11430 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11431 * call will read from NVRAM and byteswap the data
11432 * according to the byteswapping settings for all
11433 * other register accesses. This ensures the data we
11434 * want will always reside in the lower 16-bits.
11435 * However, the data in NVRAM is in LE format, which
11436 * means the data from the NVRAM read will always be
11437 * opposite the endianness of the CPU. The 16-bit
11438 * byteswap then brings the data to CPU endianness.
11440 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11444 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11447 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11451 nvcfg1 = tr32(NVRAM_CFG1);
11452 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11453 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11455 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11456 tw32(NVRAM_CFG1, nvcfg1);
11459 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11460 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11461 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11462 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11463 tp->nvram_jedecnum = JEDEC_ATMEL;
11464 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11465 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11467 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11468 tp->nvram_jedecnum = JEDEC_ATMEL;
11469 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11471 case FLASH_VENDOR_ATMEL_EEPROM:
11472 tp->nvram_jedecnum = JEDEC_ATMEL;
11473 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11474 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11476 case FLASH_VENDOR_ST:
11477 tp->nvram_jedecnum = JEDEC_ST;
11478 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11479 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11481 case FLASH_VENDOR_SAIFUN:
11482 tp->nvram_jedecnum = JEDEC_SAIFUN;
11483 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11485 case FLASH_VENDOR_SST_SMALL:
11486 case FLASH_VENDOR_SST_LARGE:
11487 tp->nvram_jedecnum = JEDEC_SST;
11488 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11492 tp->nvram_jedecnum = JEDEC_ATMEL;
11493 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11494 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11498 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11500 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11501 case FLASH_5752PAGE_SIZE_256:
11502 tp->nvram_pagesize = 256;
11504 case FLASH_5752PAGE_SIZE_512:
11505 tp->nvram_pagesize = 512;
11507 case FLASH_5752PAGE_SIZE_1K:
11508 tp->nvram_pagesize = 1024;
11510 case FLASH_5752PAGE_SIZE_2K:
11511 tp->nvram_pagesize = 2048;
11513 case FLASH_5752PAGE_SIZE_4K:
11514 tp->nvram_pagesize = 4096;
11516 case FLASH_5752PAGE_SIZE_264:
11517 tp->nvram_pagesize = 264;
11519 case FLASH_5752PAGE_SIZE_528:
11520 tp->nvram_pagesize = 528;
11525 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11529 nvcfg1 = tr32(NVRAM_CFG1);
11531 /* NVRAM protection for TPM */
11532 if (nvcfg1 & (1 << 27))
11533 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11535 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11536 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11537 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11538 tp->nvram_jedecnum = JEDEC_ATMEL;
11539 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11541 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11542 tp->nvram_jedecnum = JEDEC_ATMEL;
11543 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11544 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11546 case FLASH_5752VENDOR_ST_M45PE10:
11547 case FLASH_5752VENDOR_ST_M45PE20:
11548 case FLASH_5752VENDOR_ST_M45PE40:
11549 tp->nvram_jedecnum = JEDEC_ST;
11550 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11551 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11555 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11556 tg3_nvram_get_pagesize(tp, nvcfg1);
11558 /* For eeprom, set pagesize to maximum eeprom size */
11559 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11561 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11562 tw32(NVRAM_CFG1, nvcfg1);
11566 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11568 u32 nvcfg1, protect = 0;
11570 nvcfg1 = tr32(NVRAM_CFG1);
11572 /* NVRAM protection for TPM */
11573 if (nvcfg1 & (1 << 27)) {
11574 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11578 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11580 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11581 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11582 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11583 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11584 tp->nvram_jedecnum = JEDEC_ATMEL;
11585 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11586 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11587 tp->nvram_pagesize = 264;
11588 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11589 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11590 tp->nvram_size = (protect ? 0x3e200 :
11591 TG3_NVRAM_SIZE_512KB);
11592 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11593 tp->nvram_size = (protect ? 0x1f200 :
11594 TG3_NVRAM_SIZE_256KB);
11596 tp->nvram_size = (protect ? 0x1f200 :
11597 TG3_NVRAM_SIZE_128KB);
11599 case FLASH_5752VENDOR_ST_M45PE10:
11600 case FLASH_5752VENDOR_ST_M45PE20:
11601 case FLASH_5752VENDOR_ST_M45PE40:
11602 tp->nvram_jedecnum = JEDEC_ST;
11603 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11604 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11605 tp->nvram_pagesize = 256;
11606 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11607 tp->nvram_size = (protect ?
11608 TG3_NVRAM_SIZE_64KB :
11609 TG3_NVRAM_SIZE_128KB);
11610 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11611 tp->nvram_size = (protect ?
11612 TG3_NVRAM_SIZE_64KB :
11613 TG3_NVRAM_SIZE_256KB);
11615 tp->nvram_size = (protect ?
11616 TG3_NVRAM_SIZE_128KB :
11617 TG3_NVRAM_SIZE_512KB);
11622 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11626 nvcfg1 = tr32(NVRAM_CFG1);
11628 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11629 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11630 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11631 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11632 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11633 tp->nvram_jedecnum = JEDEC_ATMEL;
11634 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11635 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11637 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11638 tw32(NVRAM_CFG1, nvcfg1);
11640 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11641 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11642 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11643 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11644 tp->nvram_jedecnum = JEDEC_ATMEL;
11645 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11646 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11647 tp->nvram_pagesize = 264;
11649 case FLASH_5752VENDOR_ST_M45PE10:
11650 case FLASH_5752VENDOR_ST_M45PE20:
11651 case FLASH_5752VENDOR_ST_M45PE40:
11652 tp->nvram_jedecnum = JEDEC_ST;
11653 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11654 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11655 tp->nvram_pagesize = 256;
11660 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11662 u32 nvcfg1, protect = 0;
11664 nvcfg1 = tr32(NVRAM_CFG1);
11666 /* NVRAM protection for TPM */
11667 if (nvcfg1 & (1 << 27)) {
11668 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11672 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11674 case FLASH_5761VENDOR_ATMEL_ADB021D:
11675 case FLASH_5761VENDOR_ATMEL_ADB041D:
11676 case FLASH_5761VENDOR_ATMEL_ADB081D:
11677 case FLASH_5761VENDOR_ATMEL_ADB161D:
11678 case FLASH_5761VENDOR_ATMEL_MDB021D:
11679 case FLASH_5761VENDOR_ATMEL_MDB041D:
11680 case FLASH_5761VENDOR_ATMEL_MDB081D:
11681 case FLASH_5761VENDOR_ATMEL_MDB161D:
11682 tp->nvram_jedecnum = JEDEC_ATMEL;
11683 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11684 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11685 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11686 tp->nvram_pagesize = 256;
11688 case FLASH_5761VENDOR_ST_A_M45PE20:
11689 case FLASH_5761VENDOR_ST_A_M45PE40:
11690 case FLASH_5761VENDOR_ST_A_M45PE80:
11691 case FLASH_5761VENDOR_ST_A_M45PE16:
11692 case FLASH_5761VENDOR_ST_M_M45PE20:
11693 case FLASH_5761VENDOR_ST_M_M45PE40:
11694 case FLASH_5761VENDOR_ST_M_M45PE80:
11695 case FLASH_5761VENDOR_ST_M_M45PE16:
11696 tp->nvram_jedecnum = JEDEC_ST;
11697 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11698 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11699 tp->nvram_pagesize = 256;
11704 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11707 case FLASH_5761VENDOR_ATMEL_ADB161D:
11708 case FLASH_5761VENDOR_ATMEL_MDB161D:
11709 case FLASH_5761VENDOR_ST_A_M45PE16:
11710 case FLASH_5761VENDOR_ST_M_M45PE16:
11711 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11713 case FLASH_5761VENDOR_ATMEL_ADB081D:
11714 case FLASH_5761VENDOR_ATMEL_MDB081D:
11715 case FLASH_5761VENDOR_ST_A_M45PE80:
11716 case FLASH_5761VENDOR_ST_M_M45PE80:
11717 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11719 case FLASH_5761VENDOR_ATMEL_ADB041D:
11720 case FLASH_5761VENDOR_ATMEL_MDB041D:
11721 case FLASH_5761VENDOR_ST_A_M45PE40:
11722 case FLASH_5761VENDOR_ST_M_M45PE40:
11723 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11725 case FLASH_5761VENDOR_ATMEL_ADB021D:
11726 case FLASH_5761VENDOR_ATMEL_MDB021D:
11727 case FLASH_5761VENDOR_ST_A_M45PE20:
11728 case FLASH_5761VENDOR_ST_M_M45PE20:
11729 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11735 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11737 tp->nvram_jedecnum = JEDEC_ATMEL;
11738 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11739 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11742 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11746 nvcfg1 = tr32(NVRAM_CFG1);
11748 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11749 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11750 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11751 tp->nvram_jedecnum = JEDEC_ATMEL;
11752 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11753 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11755 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11756 tw32(NVRAM_CFG1, nvcfg1);
11758 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11759 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11760 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11761 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11762 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11763 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11764 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11765 tp->nvram_jedecnum = JEDEC_ATMEL;
11766 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11767 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11769 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11770 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11771 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11772 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11773 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11775 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11776 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11777 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11779 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11780 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11781 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11785 case FLASH_5752VENDOR_ST_M45PE10:
11786 case FLASH_5752VENDOR_ST_M45PE20:
11787 case FLASH_5752VENDOR_ST_M45PE40:
11788 tp->nvram_jedecnum = JEDEC_ST;
11789 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11790 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11792 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11793 case FLASH_5752VENDOR_ST_M45PE10:
11794 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11796 case FLASH_5752VENDOR_ST_M45PE20:
11797 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11799 case FLASH_5752VENDOR_ST_M45PE40:
11800 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11805 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11809 tg3_nvram_get_pagesize(tp, nvcfg1);
11810 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11811 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11815 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11819 nvcfg1 = tr32(NVRAM_CFG1);
11821 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11822 case FLASH_5717VENDOR_ATMEL_EEPROM:
11823 case FLASH_5717VENDOR_MICRO_EEPROM:
11824 tp->nvram_jedecnum = JEDEC_ATMEL;
11825 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11826 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11828 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11829 tw32(NVRAM_CFG1, nvcfg1);
11831 case FLASH_5717VENDOR_ATMEL_MDB011D:
11832 case FLASH_5717VENDOR_ATMEL_ADB011B:
11833 case FLASH_5717VENDOR_ATMEL_ADB011D:
11834 case FLASH_5717VENDOR_ATMEL_MDB021D:
11835 case FLASH_5717VENDOR_ATMEL_ADB021B:
11836 case FLASH_5717VENDOR_ATMEL_ADB021D:
11837 case FLASH_5717VENDOR_ATMEL_45USPT:
11838 tp->nvram_jedecnum = JEDEC_ATMEL;
11839 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11840 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11842 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11843 case FLASH_5717VENDOR_ATMEL_MDB021D:
11844 case FLASH_5717VENDOR_ATMEL_ADB021B:
11845 case FLASH_5717VENDOR_ATMEL_ADB021D:
11846 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11849 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11853 case FLASH_5717VENDOR_ST_M_M25PE10:
11854 case FLASH_5717VENDOR_ST_A_M25PE10:
11855 case FLASH_5717VENDOR_ST_M_M45PE10:
11856 case FLASH_5717VENDOR_ST_A_M45PE10:
11857 case FLASH_5717VENDOR_ST_M_M25PE20:
11858 case FLASH_5717VENDOR_ST_A_M25PE20:
11859 case FLASH_5717VENDOR_ST_M_M45PE20:
11860 case FLASH_5717VENDOR_ST_A_M45PE20:
11861 case FLASH_5717VENDOR_ST_25USPT:
11862 case FLASH_5717VENDOR_ST_45USPT:
11863 tp->nvram_jedecnum = JEDEC_ST;
11864 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11865 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11867 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11868 case FLASH_5717VENDOR_ST_M_M25PE20:
11869 case FLASH_5717VENDOR_ST_A_M25PE20:
11870 case FLASH_5717VENDOR_ST_M_M45PE20:
11871 case FLASH_5717VENDOR_ST_A_M45PE20:
11872 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11875 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11880 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11884 tg3_nvram_get_pagesize(tp, nvcfg1);
11885 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11886 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11889 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11890 static void __devinit tg3_nvram_init(struct tg3 *tp)
11892 tw32_f(GRC_EEPROM_ADDR,
11893 (EEPROM_ADDR_FSM_RESET |
11894 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11895 EEPROM_ADDR_CLKPERD_SHIFT)));
11899 /* Enable seeprom accesses. */
11900 tw32_f(GRC_LOCAL_CTRL,
11901 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11904 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11905 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11906 tp->tg3_flags |= TG3_FLAG_NVRAM;
11908 if (tg3_nvram_lock(tp)) {
11909 netdev_warn(tp->dev,
11910 "Cannot get nvram lock, %s failed\n",
11914 tg3_enable_nvram_access(tp);
11916 tp->nvram_size = 0;
11918 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11919 tg3_get_5752_nvram_info(tp);
11920 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11921 tg3_get_5755_nvram_info(tp);
11922 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11924 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11925 tg3_get_5787_nvram_info(tp);
11926 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11927 tg3_get_5761_nvram_info(tp);
11928 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11929 tg3_get_5906_nvram_info(tp);
11930 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11931 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11932 tg3_get_57780_nvram_info(tp);
11933 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11935 tg3_get_5717_nvram_info(tp);
11937 tg3_get_nvram_info(tp);
11939 if (tp->nvram_size == 0)
11940 tg3_get_nvram_size(tp);
11942 tg3_disable_nvram_access(tp);
11943 tg3_nvram_unlock(tp);
11946 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11948 tg3_get_eeprom_size(tp);
11952 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11953 u32 offset, u32 len, u8 *buf)
11958 for (i = 0; i < len; i += 4) {
11964 memcpy(&data, buf + i, 4);
11967 * The SEEPROM interface expects the data to always be opposite
11968 * the native endian format. We accomplish this by reversing
11969 * all the operations that would have been performed on the
11970 * data from a call to tg3_nvram_read_be32().
11972 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11974 val = tr32(GRC_EEPROM_ADDR);
11975 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11977 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11979 tw32(GRC_EEPROM_ADDR, val |
11980 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11981 (addr & EEPROM_ADDR_ADDR_MASK) |
11982 EEPROM_ADDR_START |
11983 EEPROM_ADDR_WRITE);
11985 for (j = 0; j < 1000; j++) {
11986 val = tr32(GRC_EEPROM_ADDR);
11988 if (val & EEPROM_ADDR_COMPLETE)
11992 if (!(val & EEPROM_ADDR_COMPLETE)) {
12001 /* offset and length are dword aligned */
12002 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12006 u32 pagesize = tp->nvram_pagesize;
12007 u32 pagemask = pagesize - 1;
12011 tmp = kmalloc(pagesize, GFP_KERNEL);
12017 u32 phy_addr, page_off, size;
12019 phy_addr = offset & ~pagemask;
12021 for (j = 0; j < pagesize; j += 4) {
12022 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12023 (__be32 *) (tmp + j));
12030 page_off = offset & pagemask;
12037 memcpy(tmp + page_off, buf, size);
12039 offset = offset + (pagesize - page_off);
12041 tg3_enable_nvram_access(tp);
12044 * Before we can erase the flash page, we need
12045 * to issue a special "write enable" command.
12047 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12049 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12052 /* Erase the target page */
12053 tw32(NVRAM_ADDR, phy_addr);
12055 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12056 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12058 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12061 /* Issue another write enable to start the write. */
12062 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12064 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12067 for (j = 0; j < pagesize; j += 4) {
12070 data = *((__be32 *) (tmp + j));
12072 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12074 tw32(NVRAM_ADDR, phy_addr + j);
12076 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12080 nvram_cmd |= NVRAM_CMD_FIRST;
12081 else if (j == (pagesize - 4))
12082 nvram_cmd |= NVRAM_CMD_LAST;
12084 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12091 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12092 tg3_nvram_exec_cmd(tp, nvram_cmd);
12099 /* offset and length are dword aligned */
12100 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12105 for (i = 0; i < len; i += 4, offset += 4) {
12106 u32 page_off, phy_addr, nvram_cmd;
12109 memcpy(&data, buf + i, 4);
12110 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12112 page_off = offset % tp->nvram_pagesize;
12114 phy_addr = tg3_nvram_phys_addr(tp, offset);
12116 tw32(NVRAM_ADDR, phy_addr);
12118 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12120 if (page_off == 0 || i == 0)
12121 nvram_cmd |= NVRAM_CMD_FIRST;
12122 if (page_off == (tp->nvram_pagesize - 4))
12123 nvram_cmd |= NVRAM_CMD_LAST;
12125 if (i == (len - 4))
12126 nvram_cmd |= NVRAM_CMD_LAST;
12128 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12129 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12130 (tp->nvram_jedecnum == JEDEC_ST) &&
12131 (nvram_cmd & NVRAM_CMD_FIRST)) {
12133 if ((ret = tg3_nvram_exec_cmd(tp,
12134 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12139 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12140 /* We always do complete word writes to eeprom. */
12141 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12144 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12150 /* offset and length are dword aligned */
12151 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12155 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12156 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12157 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12161 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12162 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12166 ret = tg3_nvram_lock(tp);
12170 tg3_enable_nvram_access(tp);
12171 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12172 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12173 tw32(NVRAM_WRITE1, 0x406);
12175 grc_mode = tr32(GRC_MODE);
12176 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12178 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12179 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12181 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12184 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12188 grc_mode = tr32(GRC_MODE);
12189 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12191 tg3_disable_nvram_access(tp);
12192 tg3_nvram_unlock(tp);
12195 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12196 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12203 struct subsys_tbl_ent {
12204 u16 subsys_vendor, subsys_devid;
12208 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12209 /* Broadcom boards. */
12210 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12211 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12212 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12213 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12214 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12215 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12216 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12217 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12218 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12219 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12220 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12221 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12222 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12223 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12224 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12225 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12226 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12227 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12228 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12229 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12230 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12231 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12234 { TG3PCI_SUBVENDOR_ID_3COM,
12235 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12236 { TG3PCI_SUBVENDOR_ID_3COM,
12237 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12238 { TG3PCI_SUBVENDOR_ID_3COM,
12239 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12240 { TG3PCI_SUBVENDOR_ID_3COM,
12241 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12242 { TG3PCI_SUBVENDOR_ID_3COM,
12243 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12246 { TG3PCI_SUBVENDOR_ID_DELL,
12247 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12248 { TG3PCI_SUBVENDOR_ID_DELL,
12249 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12250 { TG3PCI_SUBVENDOR_ID_DELL,
12251 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12252 { TG3PCI_SUBVENDOR_ID_DELL,
12253 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12255 /* Compaq boards. */
12256 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12257 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12258 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12259 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12260 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12261 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12262 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12263 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12264 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12265 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12268 { TG3PCI_SUBVENDOR_ID_IBM,
12269 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12272 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12276 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12277 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12278 tp->pdev->subsystem_vendor) &&
12279 (subsys_id_to_phy_id[i].subsys_devid ==
12280 tp->pdev->subsystem_device))
12281 return &subsys_id_to_phy_id[i];
12286 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12291 /* On some early chips the SRAM cannot be accessed in D3hot state,
12292 * so need make sure we're in D0.
12294 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12295 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12296 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12299 /* Make sure register accesses (indirect or otherwise)
12300 * will function correctly.
12302 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12303 tp->misc_host_ctrl);
12305 /* The memory arbiter has to be enabled in order for SRAM accesses
12306 * to succeed. Normally on powerup the tg3 chip firmware will make
12307 * sure it is enabled, but other entities such as system netboot
12308 * code might disable it.
12310 val = tr32(MEMARB_MODE);
12311 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12313 tp->phy_id = TG3_PHY_ID_INVALID;
12314 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12316 /* Assume an onboard device and WOL capable by default. */
12317 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12319 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12320 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12321 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12322 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12324 val = tr32(VCPU_CFGSHDW);
12325 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12326 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12327 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12328 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12329 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12333 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12334 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12335 u32 nic_cfg, led_cfg;
12336 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12337 int eeprom_phy_serdes = 0;
12339 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12340 tp->nic_sram_data_cfg = nic_cfg;
12342 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12343 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12344 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12345 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12346 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12347 (ver > 0) && (ver < 0x100))
12348 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12351 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12353 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12354 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12355 eeprom_phy_serdes = 1;
12357 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12358 if (nic_phy_id != 0) {
12359 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12360 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12362 eeprom_phy_id = (id1 >> 16) << 10;
12363 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12364 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12368 tp->phy_id = eeprom_phy_id;
12369 if (eeprom_phy_serdes) {
12370 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12371 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12373 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12376 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12377 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12378 SHASTA_EXT_LED_MODE_MASK);
12380 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12384 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12385 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12388 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12389 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12392 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12393 tp->led_ctrl = LED_CTRL_MODE_MAC;
12395 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12396 * read on some older 5700/5701 bootcode.
12398 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12400 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12402 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12406 case SHASTA_EXT_LED_SHARED:
12407 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12408 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12409 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12410 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12411 LED_CTRL_MODE_PHY_2);
12414 case SHASTA_EXT_LED_MAC:
12415 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12418 case SHASTA_EXT_LED_COMBO:
12419 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12420 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12421 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12422 LED_CTRL_MODE_PHY_2);
12427 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12428 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12429 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12430 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12432 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12433 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12435 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12436 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12437 if ((tp->pdev->subsystem_vendor ==
12438 PCI_VENDOR_ID_ARIMA) &&
12439 (tp->pdev->subsystem_device == 0x205a ||
12440 tp->pdev->subsystem_device == 0x2063))
12441 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12443 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12444 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12447 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12448 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12449 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12450 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12453 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12454 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12455 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12457 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12458 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12459 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12461 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12462 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12463 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12465 if (cfg2 & (1 << 17))
12466 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12468 /* serdes signal pre-emphasis in register 0x590 set by */
12469 /* bootcode if bit 18 is set */
12470 if (cfg2 & (1 << 18))
12471 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12473 if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) ||
12474 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12475 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12476 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12477 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12479 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12480 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12481 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12484 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12485 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12486 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12489 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12490 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12491 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12492 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12493 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12494 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12497 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
12498 device_set_wakeup_enable(&tp->pdev->dev,
12499 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12501 device_set_wakeup_capable(&tp->pdev->dev, false);
12504 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12509 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12510 tw32(OTP_CTRL, cmd);
12512 /* Wait for up to 1 ms for command to execute. */
12513 for (i = 0; i < 100; i++) {
12514 val = tr32(OTP_STATUS);
12515 if (val & OTP_STATUS_CMD_DONE)
12520 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12523 /* Read the gphy configuration from the OTP region of the chip. The gphy
12524 * configuration is a 32-bit value that straddles the alignment boundary.
12525 * We do two 32-bit reads and then shift and merge the results.
12527 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12529 u32 bhalf_otp, thalf_otp;
12531 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12533 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12536 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12538 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12541 thalf_otp = tr32(OTP_READ_DATA);
12543 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12545 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12548 bhalf_otp = tr32(OTP_READ_DATA);
12550 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12553 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12555 u32 adv = ADVERTISED_Autoneg |
12558 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12559 adv |= ADVERTISED_1000baseT_Half |
12560 ADVERTISED_1000baseT_Full;
12562 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12563 adv |= ADVERTISED_100baseT_Half |
12564 ADVERTISED_100baseT_Full |
12565 ADVERTISED_10baseT_Half |
12566 ADVERTISED_10baseT_Full |
12569 adv |= ADVERTISED_FIBRE;
12571 tp->link_config.advertising = adv;
12572 tp->link_config.speed = SPEED_INVALID;
12573 tp->link_config.duplex = DUPLEX_INVALID;
12574 tp->link_config.autoneg = AUTONEG_ENABLE;
12575 tp->link_config.active_speed = SPEED_INVALID;
12576 tp->link_config.active_duplex = DUPLEX_INVALID;
12577 tp->link_config.orig_speed = SPEED_INVALID;
12578 tp->link_config.orig_duplex = DUPLEX_INVALID;
12579 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12582 static int __devinit tg3_phy_probe(struct tg3 *tp)
12584 u32 hw_phy_id_1, hw_phy_id_2;
12585 u32 hw_phy_id, hw_phy_id_masked;
12588 /* flow control autonegotiation is default behavior */
12589 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12590 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12592 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12593 return tg3_phy_init(tp);
12595 /* Reading the PHY ID register can conflict with ASF
12596 * firmware access to the PHY hardware.
12599 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12600 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12601 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12603 /* Now read the physical PHY_ID from the chip and verify
12604 * that it is sane. If it doesn't look good, we fall back
12605 * to either the hard-coded table based PHY_ID and failing
12606 * that the value found in the eeprom area.
12608 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12609 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12611 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12612 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12613 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12615 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12618 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12619 tp->phy_id = hw_phy_id;
12620 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12621 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12623 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12625 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12626 /* Do nothing, phy ID already set up in
12627 * tg3_get_eeprom_hw_cfg().
12630 struct subsys_tbl_ent *p;
12632 /* No eeprom signature? Try the hardcoded
12633 * subsys device table.
12635 p = tg3_lookup_by_subsys(tp);
12639 tp->phy_id = p->phy_id;
12641 tp->phy_id == TG3_PHY_ID_BCM8002)
12642 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12646 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12647 ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12648 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12649 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12650 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12651 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12653 tg3_phy_init_link_config(tp);
12655 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12656 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12657 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12658 u32 bmsr, adv_reg, tg3_ctrl, mask;
12660 tg3_readphy(tp, MII_BMSR, &bmsr);
12661 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12662 (bmsr & BMSR_LSTATUS))
12663 goto skip_phy_reset;
12665 err = tg3_phy_reset(tp);
12669 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12670 ADVERTISE_100HALF | ADVERTISE_100FULL |
12671 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12673 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12674 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12675 MII_TG3_CTRL_ADV_1000_FULL);
12676 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12677 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12678 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12679 MII_TG3_CTRL_ENABLE_AS_MASTER);
12682 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12683 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12684 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12685 if (!tg3_copper_is_advertising_all(tp, mask)) {
12686 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12688 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12689 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12691 tg3_writephy(tp, MII_BMCR,
12692 BMCR_ANENABLE | BMCR_ANRESTART);
12694 tg3_phy_set_wirespeed(tp);
12696 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12697 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12698 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12702 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12703 err = tg3_init_5401phy_dsp(tp);
12707 err = tg3_init_5401phy_dsp(tp);
12713 static void __devinit tg3_read_vpd(struct tg3 *tp)
12716 unsigned int block_end, rosize, len;
12720 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12721 tg3_nvram_read(tp, 0x0, &magic))
12724 vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12728 if (magic == TG3_EEPROM_MAGIC) {
12729 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12732 /* The data is in little-endian format in NVRAM.
12733 * Use the big-endian read routines to preserve
12734 * the byte order as it exists in NVRAM.
12736 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12737 goto out_not_found;
12739 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12743 unsigned int pos = 0;
12745 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12746 cnt = pci_read_vpd(tp->pdev, pos,
12747 TG3_NVM_VPD_LEN - pos,
12749 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12752 goto out_not_found;
12754 if (pos != TG3_NVM_VPD_LEN)
12755 goto out_not_found;
12758 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12759 PCI_VPD_LRDT_RO_DATA);
12761 goto out_not_found;
12763 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12764 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12765 i += PCI_VPD_LRDT_TAG_SIZE;
12767 if (block_end > TG3_NVM_VPD_LEN)
12768 goto out_not_found;
12770 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12771 PCI_VPD_RO_KEYWORD_MFR_ID);
12773 len = pci_vpd_info_field_size(&vpd_data[j]);
12775 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12776 if (j + len > block_end || len != 4 ||
12777 memcmp(&vpd_data[j], "1028", 4))
12780 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12781 PCI_VPD_RO_KEYWORD_VENDOR0);
12785 len = pci_vpd_info_field_size(&vpd_data[j]);
12787 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12788 if (j + len > block_end)
12791 memcpy(tp->fw_ver, &vpd_data[j], len);
12792 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12796 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12797 PCI_VPD_RO_KEYWORD_PARTNO);
12799 goto out_not_found;
12801 len = pci_vpd_info_field_size(&vpd_data[i]);
12803 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12804 if (len > TG3_BPN_SIZE ||
12805 (len + i) > TG3_NVM_VPD_LEN)
12806 goto out_not_found;
12808 memcpy(tp->board_part_number, &vpd_data[i], len);
12812 if (tp->board_part_number[0])
12816 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12817 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12818 strcpy(tp->board_part_number, "BCM5717");
12819 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12820 strcpy(tp->board_part_number, "BCM5718");
12823 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12824 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12825 strcpy(tp->board_part_number, "BCM57780");
12826 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12827 strcpy(tp->board_part_number, "BCM57760");
12828 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12829 strcpy(tp->board_part_number, "BCM57790");
12830 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12831 strcpy(tp->board_part_number, "BCM57788");
12834 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12835 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12836 strcpy(tp->board_part_number, "BCM57761");
12837 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12838 strcpy(tp->board_part_number, "BCM57765");
12839 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12840 strcpy(tp->board_part_number, "BCM57781");
12841 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12842 strcpy(tp->board_part_number, "BCM57785");
12843 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12844 strcpy(tp->board_part_number, "BCM57791");
12845 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12846 strcpy(tp->board_part_number, "BCM57795");
12849 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12850 strcpy(tp->board_part_number, "BCM95906");
12853 strcpy(tp->board_part_number, "none");
12857 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12861 if (tg3_nvram_read(tp, offset, &val) ||
12862 (val & 0xfc000000) != 0x0c000000 ||
12863 tg3_nvram_read(tp, offset + 4, &val) ||
12870 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12872 u32 val, offset, start, ver_offset;
12874 bool newver = false;
12876 if (tg3_nvram_read(tp, 0xc, &offset) ||
12877 tg3_nvram_read(tp, 0x4, &start))
12880 offset = tg3_nvram_logical_addr(tp, offset);
12882 if (tg3_nvram_read(tp, offset, &val))
12885 if ((val & 0xfc000000) == 0x0c000000) {
12886 if (tg3_nvram_read(tp, offset + 4, &val))
12893 dst_off = strlen(tp->fw_ver);
12896 if (TG3_VER_SIZE - dst_off < 16 ||
12897 tg3_nvram_read(tp, offset + 8, &ver_offset))
12900 offset = offset + ver_offset - start;
12901 for (i = 0; i < 16; i += 4) {
12903 if (tg3_nvram_read_be32(tp, offset + i, &v))
12906 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12911 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12914 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12915 TG3_NVM_BCVER_MAJSFT;
12916 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12917 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12918 "v%d.%02d", major, minor);
12922 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12924 u32 val, major, minor;
12926 /* Use native endian representation */
12927 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12930 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12931 TG3_NVM_HWSB_CFG1_MAJSFT;
12932 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12933 TG3_NVM_HWSB_CFG1_MINSFT;
12935 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12938 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12940 u32 offset, major, minor, build;
12942 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12944 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12947 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12948 case TG3_EEPROM_SB_REVISION_0:
12949 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12951 case TG3_EEPROM_SB_REVISION_2:
12952 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12954 case TG3_EEPROM_SB_REVISION_3:
12955 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12957 case TG3_EEPROM_SB_REVISION_4:
12958 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12960 case TG3_EEPROM_SB_REVISION_5:
12961 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12963 case TG3_EEPROM_SB_REVISION_6:
12964 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12970 if (tg3_nvram_read(tp, offset, &val))
12973 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12974 TG3_EEPROM_SB_EDH_BLD_SHFT;
12975 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12976 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12977 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12979 if (minor > 99 || build > 26)
12982 offset = strlen(tp->fw_ver);
12983 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12984 " v%d.%02d", major, minor);
12987 offset = strlen(tp->fw_ver);
12988 if (offset < TG3_VER_SIZE - 1)
12989 tp->fw_ver[offset] = 'a' + build - 1;
12993 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12995 u32 val, offset, start;
12998 for (offset = TG3_NVM_DIR_START;
12999 offset < TG3_NVM_DIR_END;
13000 offset += TG3_NVM_DIRENT_SIZE) {
13001 if (tg3_nvram_read(tp, offset, &val))
13004 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13008 if (offset == TG3_NVM_DIR_END)
13011 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
13012 start = 0x08000000;
13013 else if (tg3_nvram_read(tp, offset - 4, &start))
13016 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13017 !tg3_fw_img_is_valid(tp, offset) ||
13018 tg3_nvram_read(tp, offset + 8, &val))
13021 offset += val - start;
13023 vlen = strlen(tp->fw_ver);
13025 tp->fw_ver[vlen++] = ',';
13026 tp->fw_ver[vlen++] = ' ';
13028 for (i = 0; i < 4; i++) {
13030 if (tg3_nvram_read_be32(tp, offset, &v))
13033 offset += sizeof(v);
13035 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13036 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13040 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13045 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13051 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13052 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
13055 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13056 if (apedata != APE_SEG_SIG_MAGIC)
13059 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13060 if (!(apedata & APE_FW_STATUS_READY))
13063 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13065 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13066 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
13072 vlen = strlen(tp->fw_ver);
13074 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13076 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13077 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13078 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13079 (apedata & APE_FW_VERSION_BLDMSK));
13082 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13085 bool vpd_vers = false;
13087 if (tp->fw_ver[0] != 0)
13090 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13091 strcat(tp->fw_ver, "sb");
13095 if (tg3_nvram_read(tp, 0, &val))
13098 if (val == TG3_EEPROM_MAGIC)
13099 tg3_read_bc_ver(tp);
13100 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13101 tg3_read_sb_ver(tp, val);
13102 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13103 tg3_read_hwsb_ver(tp);
13107 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13108 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13111 tg3_read_mgmtfw_ver(tp);
13114 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13117 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13119 static inline void vlan_features_add(struct net_device *dev, unsigned long flags)
13121 dev->vlan_features |= flags;
13124 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13126 if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
13127 return TG3_RX_RET_MAX_SIZE_5717;
13128 else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13129 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13130 return TG3_RX_RET_MAX_SIZE_5700;
13132 return TG3_RX_RET_MAX_SIZE_5705;
13135 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13136 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13137 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13138 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13142 static int __devinit tg3_get_invariants(struct tg3 *tp)
13145 u32 pci_state_reg, grc_misc_cfg;
13150 /* Force memory write invalidate off. If we leave it on,
13151 * then on 5700_BX chips we have to enable a workaround.
13152 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13153 * to match the cacheline size. The Broadcom driver have this
13154 * workaround but turns MWI off all the times so never uses
13155 * it. This seems to suggest that the workaround is insufficient.
13157 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13158 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13159 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13161 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13162 * has the register indirect write enable bit set before
13163 * we try to access any of the MMIO registers. It is also
13164 * critical that the PCI-X hw workaround situation is decided
13165 * before that as well.
13167 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13170 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13171 MISC_HOST_CTRL_CHIPREV_SHIFT);
13172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13173 u32 prod_id_asic_rev;
13175 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13176 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13177 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13178 pci_read_config_dword(tp->pdev,
13179 TG3PCI_GEN2_PRODID_ASICREV,
13180 &prod_id_asic_rev);
13181 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13182 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13183 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13184 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13185 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13186 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13187 pci_read_config_dword(tp->pdev,
13188 TG3PCI_GEN15_PRODID_ASICREV,
13189 &prod_id_asic_rev);
13191 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13192 &prod_id_asic_rev);
13194 tp->pci_chip_rev_id = prod_id_asic_rev;
13197 /* Wrong chip ID in 5752 A0. This code can be removed later
13198 * as A0 is not in production.
13200 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13201 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13203 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13204 * we need to disable memory and use config. cycles
13205 * only to access all registers. The 5702/03 chips
13206 * can mistakenly decode the special cycles from the
13207 * ICH chipsets as memory write cycles, causing corruption
13208 * of register and memory space. Only certain ICH bridges
13209 * will drive special cycles with non-zero data during the
13210 * address phase which can fall within the 5703's address
13211 * range. This is not an ICH bug as the PCI spec allows
13212 * non-zero address during special cycles. However, only
13213 * these ICH bridges are known to drive non-zero addresses
13214 * during special cycles.
13216 * Since special cycles do not cross PCI bridges, we only
13217 * enable this workaround if the 5703 is on the secondary
13218 * bus of these ICH bridges.
13220 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13221 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13222 static struct tg3_dev_id {
13226 } ich_chipsets[] = {
13227 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13229 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13231 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13233 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13237 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13238 struct pci_dev *bridge = NULL;
13240 while (pci_id->vendor != 0) {
13241 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13247 if (pci_id->rev != PCI_ANY_ID) {
13248 if (bridge->revision > pci_id->rev)
13251 if (bridge->subordinate &&
13252 (bridge->subordinate->number ==
13253 tp->pdev->bus->number)) {
13255 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13256 pci_dev_put(bridge);
13262 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13263 static struct tg3_dev_id {
13266 } bridge_chipsets[] = {
13267 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13268 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13271 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13272 struct pci_dev *bridge = NULL;
13274 while (pci_id->vendor != 0) {
13275 bridge = pci_get_device(pci_id->vendor,
13282 if (bridge->subordinate &&
13283 (bridge->subordinate->number <=
13284 tp->pdev->bus->number) &&
13285 (bridge->subordinate->subordinate >=
13286 tp->pdev->bus->number)) {
13287 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13288 pci_dev_put(bridge);
13294 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13295 * DMA addresses > 40-bit. This bridge may have other additional
13296 * 57xx devices behind it in some 4-port NIC designs for example.
13297 * Any tg3 device found behind the bridge will also need the 40-bit
13300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13301 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13302 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13303 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13304 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13306 struct pci_dev *bridge = NULL;
13309 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13310 PCI_DEVICE_ID_SERVERWORKS_EPB,
13312 if (bridge && bridge->subordinate &&
13313 (bridge->subordinate->number <=
13314 tp->pdev->bus->number) &&
13315 (bridge->subordinate->subordinate >=
13316 tp->pdev->bus->number)) {
13317 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13318 pci_dev_put(bridge);
13324 /* Initialize misc host control in PCI block. */
13325 tp->misc_host_ctrl |= (misc_ctrl_reg &
13326 MISC_HOST_CTRL_CHIPREV);
13327 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13328 tp->misc_host_ctrl);
13330 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13331 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13332 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13333 tp->pdev_peer = tg3_find_peer(tp);
13335 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13336 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13337 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13338 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13340 /* Intentionally exclude ASIC_REV_5906 */
13341 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13342 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13343 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13344 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13345 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13347 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13348 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13352 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13353 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13354 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13355 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13357 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13358 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13359 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13361 /* 5700 B0 chips do not support checksumming correctly due
13362 * to hardware bugs.
13364 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13365 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13367 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13369 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13370 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13371 features |= NETIF_F_IPV6_CSUM;
13372 tp->dev->features |= features;
13373 vlan_features_add(tp->dev, features);
13376 /* Determine TSO capabilities */
13377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13378 ; /* Do nothing. HW bug. */
13379 else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13380 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13381 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13382 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13383 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13384 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13385 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13386 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13387 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13388 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13389 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13390 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13391 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13392 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13393 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13394 tp->fw_needed = FIRMWARE_TG3TSO5;
13396 tp->fw_needed = FIRMWARE_TG3TSO;
13401 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13402 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13403 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13404 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13405 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13406 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13407 tp->pdev_peer == tp->pdev))
13408 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13410 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13412 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13415 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13416 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13417 tp->irq_max = TG3_IRQ_MAX_VECS;
13421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13422 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13423 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13424 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13425 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13426 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13427 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13430 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13431 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13432 tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
13434 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
13435 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13436 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13438 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13439 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13440 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13441 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13443 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13446 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13447 if (tp->pcie_cap != 0) {
13450 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13452 tp->pcie_readrq = 4096;
13453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13454 tp->pcie_readrq = 2048;
13456 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13458 pci_read_config_word(tp->pdev,
13459 tp->pcie_cap + PCI_EXP_LNKCTL,
13461 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13463 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13464 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13466 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13467 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13468 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13469 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13470 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13472 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13473 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13474 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13475 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13476 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13477 if (!tp->pcix_cap) {
13478 dev_err(&tp->pdev->dev,
13479 "Cannot find PCI-X capability, aborting\n");
13483 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13484 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13487 /* If we have an AMD 762 or VIA K8T800 chipset, write
13488 * reordering to the mailbox registers done by the host
13489 * controller can cause major troubles. We read back from
13490 * every mailbox register write to force the writes to be
13491 * posted to the chip in order.
13493 if (pci_dev_present(tg3_write_reorder_chipsets) &&
13494 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13495 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13497 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13498 &tp->pci_cacheline_sz);
13499 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13500 &tp->pci_lat_timer);
13501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13502 tp->pci_lat_timer < 64) {
13503 tp->pci_lat_timer = 64;
13504 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13505 tp->pci_lat_timer);
13508 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13509 /* 5700 BX chips need to have their TX producer index
13510 * mailboxes written twice to workaround a bug.
13512 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13514 /* If we are in PCI-X mode, enable register write workaround.
13516 * The workaround is to use indirect register accesses
13517 * for all chip writes not to mailbox registers.
13519 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13522 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13524 /* The chip can have it's power management PCI config
13525 * space registers clobbered due to this bug.
13526 * So explicitly force the chip into D0 here.
13528 pci_read_config_dword(tp->pdev,
13529 tp->pm_cap + PCI_PM_CTRL,
13531 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13532 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13533 pci_write_config_dword(tp->pdev,
13534 tp->pm_cap + PCI_PM_CTRL,
13537 /* Also, force SERR#/PERR# in PCI command. */
13538 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13539 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13540 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13544 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13545 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13546 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13547 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13549 /* Chip-specific fixup from Broadcom driver */
13550 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13551 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13552 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13553 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13556 /* Default fast path register access methods */
13557 tp->read32 = tg3_read32;
13558 tp->write32 = tg3_write32;
13559 tp->read32_mbox = tg3_read32;
13560 tp->write32_mbox = tg3_write32;
13561 tp->write32_tx_mbox = tg3_write32;
13562 tp->write32_rx_mbox = tg3_write32;
13564 /* Various workaround register access methods */
13565 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13566 tp->write32 = tg3_write_indirect_reg32;
13567 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13568 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13569 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13571 * Back to back register writes can cause problems on these
13572 * chips, the workaround is to read back all reg writes
13573 * except those to mailbox regs.
13575 * See tg3_write_indirect_reg32().
13577 tp->write32 = tg3_write_flush_reg32;
13580 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13581 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13582 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13583 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13584 tp->write32_rx_mbox = tg3_write_flush_reg32;
13587 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13588 tp->read32 = tg3_read_indirect_reg32;
13589 tp->write32 = tg3_write_indirect_reg32;
13590 tp->read32_mbox = tg3_read_indirect_mbox;
13591 tp->write32_mbox = tg3_write_indirect_mbox;
13592 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13593 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13598 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13599 pci_cmd &= ~PCI_COMMAND_MEMORY;
13600 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13603 tp->read32_mbox = tg3_read32_mbox_5906;
13604 tp->write32_mbox = tg3_write32_mbox_5906;
13605 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13606 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13609 if (tp->write32 == tg3_write_indirect_reg32 ||
13610 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13611 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13612 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13613 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13615 /* Get eeprom hw config before calling tg3_set_power_state().
13616 * In particular, the TG3_FLG2_IS_NIC flag must be
13617 * determined before calling tg3_set_power_state() so that
13618 * we know whether or not to switch out of Vaux power.
13619 * When the flag is set, it means that GPIO1 is used for eeprom
13620 * write protect and also implies that it is a LOM where GPIOs
13621 * are not used to switch power.
13623 tg3_get_eeprom_hw_cfg(tp);
13625 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13626 /* Allow reads and writes to the
13627 * APE register and memory space.
13629 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13630 PCISTATE_ALLOW_APE_SHMEM_WR |
13631 PCISTATE_ALLOW_APE_PSPACE_WR;
13632 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13639 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13640 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13641 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13643 /* Set up tp->grc_local_ctrl before calling tg_power_up().
13644 * GPIO1 driven high will bring 5700's external PHY out of reset.
13645 * It is also used as eeprom write protect on LOMs.
13647 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13648 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13649 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13650 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13651 GRC_LCLCTRL_GPIO_OUTPUT1);
13652 /* Unused GPIO3 must be driven as output on 5752 because there
13653 * are no pull-up resistors on unused GPIO pins.
13655 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13656 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13659 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13660 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13661 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13663 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13664 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13665 /* Turn off the debug UART. */
13666 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13667 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13668 /* Keep VMain power. */
13669 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13670 GRC_LCLCTRL_GPIO_OUTPUT0;
13673 /* Force the chip into D0. */
13674 err = tg3_power_up(tp);
13676 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13680 /* Derive initial jumbo mode from MTU assigned in
13681 * ether_setup() via the alloc_etherdev() call
13683 if (tp->dev->mtu > ETH_DATA_LEN &&
13684 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13685 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13687 /* Determine WakeOnLan speed to use. */
13688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13689 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13690 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13691 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13692 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13694 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13697 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13698 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13700 /* A few boards don't want Ethernet@WireSpeed phy feature */
13701 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13702 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13703 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13704 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13705 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13706 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13707 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13709 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13710 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13711 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13712 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13713 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13715 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13716 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13717 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13718 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13719 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13721 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13723 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13724 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13725 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13726 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13727 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13728 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13730 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13733 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13734 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13735 tp->phy_otp = tg3_read_otp_phycfg(tp);
13736 if (tp->phy_otp == 0)
13737 tp->phy_otp = TG3_OTP_DEFAULT;
13740 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13741 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13743 tp->mi_mode = MAC_MI_MODE_BASE;
13745 tp->coalesce_mode = 0;
13746 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13747 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13748 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13750 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13751 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13752 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13754 err = tg3_mdio_init(tp);
13758 /* Initialize data/descriptor byte/word swapping. */
13759 val = tr32(GRC_MODE);
13760 val &= GRC_MODE_HOST_STACKUP;
13761 tw32(GRC_MODE, val | tp->grc_mode);
13763 tg3_switch_clocks(tp);
13765 /* Clear this out for sanity. */
13766 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13768 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13770 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13771 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13772 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13774 if (chiprevid == CHIPREV_ID_5701_A0 ||
13775 chiprevid == CHIPREV_ID_5701_B0 ||
13776 chiprevid == CHIPREV_ID_5701_B2 ||
13777 chiprevid == CHIPREV_ID_5701_B5) {
13778 void __iomem *sram_base;
13780 /* Write some dummy words into the SRAM status block
13781 * area, see if it reads back correctly. If the return
13782 * value is bad, force enable the PCIX workaround.
13784 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13786 writel(0x00000000, sram_base);
13787 writel(0x00000000, sram_base + 4);
13788 writel(0xffffffff, sram_base + 4);
13789 if (readl(sram_base) != 0x00000000)
13790 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13795 tg3_nvram_init(tp);
13797 grc_misc_cfg = tr32(GRC_MISC_CFG);
13798 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13800 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13801 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13802 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13803 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13805 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13806 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13807 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13808 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13809 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13810 HOSTCC_MODE_CLRTICK_TXBD);
13812 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13813 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13814 tp->misc_host_ctrl);
13817 /* Preserve the APE MAC_MODE bits */
13818 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13819 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13821 tp->mac_mode = TG3_DEF_MAC_MODE;
13823 /* these are limited to 10/100 only */
13824 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13825 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13826 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13827 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13828 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13829 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13830 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13831 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13832 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13833 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13834 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13835 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13836 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13837 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13838 (tp->phy_flags & TG3_PHYFLG_IS_FET))
13839 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13841 err = tg3_phy_probe(tp);
13843 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13844 /* ... but do not return immediately ... */
13849 tg3_read_fw_ver(tp);
13851 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13852 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13855 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13857 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13860 /* 5700 {AX,BX} chips have a broken status block link
13861 * change bit implementation, so we must use the
13862 * status register in those cases.
13864 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13865 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13867 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13869 /* The led_ctrl is set during tg3_phy_probe, here we might
13870 * have to force the link status polling mechanism based
13871 * upon subsystem IDs.
13873 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13874 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13875 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13876 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13877 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13880 /* For all SERDES we poll the MAC status register. */
13881 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13882 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13884 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13886 tp->rx_offset = NET_IP_ALIGN;
13887 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13889 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13891 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13892 tp->rx_copy_thresh = ~(u16)0;
13896 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13897 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13898 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13900 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13902 /* Increment the rx prod index on the rx std ring by at most
13903 * 8 for these chips to workaround hw errata.
13905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13907 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13908 tp->rx_std_max_post = 8;
13910 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13911 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13912 PCIE_PWR_MGMT_L1_THRESH_MSK;
13917 #ifdef CONFIG_SPARC
13918 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13920 struct net_device *dev = tp->dev;
13921 struct pci_dev *pdev = tp->pdev;
13922 struct device_node *dp = pci_device_to_OF_node(pdev);
13923 const unsigned char *addr;
13926 addr = of_get_property(dp, "local-mac-address", &len);
13927 if (addr && len == 6) {
13928 memcpy(dev->dev_addr, addr, 6);
13929 memcpy(dev->perm_addr, dev->dev_addr, 6);
13935 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13937 struct net_device *dev = tp->dev;
13939 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13940 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13945 static int __devinit tg3_get_device_address(struct tg3 *tp)
13947 struct net_device *dev = tp->dev;
13948 u32 hi, lo, mac_offset;
13951 #ifdef CONFIG_SPARC
13952 if (!tg3_get_macaddr_sparc(tp))
13957 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13958 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13959 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13961 if (tg3_nvram_lock(tp))
13962 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13964 tg3_nvram_unlock(tp);
13965 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13966 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13967 if (PCI_FUNC(tp->pdev->devfn) & 1)
13969 if (PCI_FUNC(tp->pdev->devfn) > 1)
13970 mac_offset += 0x18c;
13971 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13974 /* First try to get it from MAC address mailbox. */
13975 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13976 if ((hi >> 16) == 0x484b) {
13977 dev->dev_addr[0] = (hi >> 8) & 0xff;
13978 dev->dev_addr[1] = (hi >> 0) & 0xff;
13980 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13981 dev->dev_addr[2] = (lo >> 24) & 0xff;
13982 dev->dev_addr[3] = (lo >> 16) & 0xff;
13983 dev->dev_addr[4] = (lo >> 8) & 0xff;
13984 dev->dev_addr[5] = (lo >> 0) & 0xff;
13986 /* Some old bootcode may report a 0 MAC address in SRAM */
13987 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13990 /* Next, try NVRAM. */
13991 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13992 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13993 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13994 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13995 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13997 /* Finally just fetch it out of the MAC control regs. */
13999 hi = tr32(MAC_ADDR_0_HIGH);
14000 lo = tr32(MAC_ADDR_0_LOW);
14002 dev->dev_addr[5] = lo & 0xff;
14003 dev->dev_addr[4] = (lo >> 8) & 0xff;
14004 dev->dev_addr[3] = (lo >> 16) & 0xff;
14005 dev->dev_addr[2] = (lo >> 24) & 0xff;
14006 dev->dev_addr[1] = hi & 0xff;
14007 dev->dev_addr[0] = (hi >> 8) & 0xff;
14011 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14012 #ifdef CONFIG_SPARC
14013 if (!tg3_get_default_macaddr_sparc(tp))
14018 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14022 #define BOUNDARY_SINGLE_CACHELINE 1
14023 #define BOUNDARY_MULTI_CACHELINE 2
14025 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14027 int cacheline_size;
14031 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14033 cacheline_size = 1024;
14035 cacheline_size = (int) byte * 4;
14037 /* On 5703 and later chips, the boundary bits have no
14040 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14041 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14042 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14045 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14046 goal = BOUNDARY_MULTI_CACHELINE;
14048 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14049 goal = BOUNDARY_SINGLE_CACHELINE;
14055 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14056 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14063 /* PCI controllers on most RISC systems tend to disconnect
14064 * when a device tries to burst across a cache-line boundary.
14065 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14067 * Unfortunately, for PCI-E there are only limited
14068 * write-side controls for this, and thus for reads
14069 * we will still get the disconnects. We'll also waste
14070 * these PCI cycles for both read and write for chips
14071 * other than 5700 and 5701 which do not implement the
14074 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14075 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14076 switch (cacheline_size) {
14081 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14082 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14083 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14085 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14086 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14091 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14092 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14096 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14097 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14100 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14101 switch (cacheline_size) {
14105 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14106 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14107 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14113 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14114 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14118 switch (cacheline_size) {
14120 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14121 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14122 DMA_RWCTRL_WRITE_BNDRY_16);
14127 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14128 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14129 DMA_RWCTRL_WRITE_BNDRY_32);
14134 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14135 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14136 DMA_RWCTRL_WRITE_BNDRY_64);
14141 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14142 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14143 DMA_RWCTRL_WRITE_BNDRY_128);
14148 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14149 DMA_RWCTRL_WRITE_BNDRY_256);
14152 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14153 DMA_RWCTRL_WRITE_BNDRY_512);
14157 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14158 DMA_RWCTRL_WRITE_BNDRY_1024);
14167 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14169 struct tg3_internal_buffer_desc test_desc;
14170 u32 sram_dma_descs;
14173 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14175 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14176 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14177 tw32(RDMAC_STATUS, 0);
14178 tw32(WDMAC_STATUS, 0);
14180 tw32(BUFMGR_MODE, 0);
14181 tw32(FTQ_RESET, 0);
14183 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14184 test_desc.addr_lo = buf_dma & 0xffffffff;
14185 test_desc.nic_mbuf = 0x00002100;
14186 test_desc.len = size;
14189 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14190 * the *second* time the tg3 driver was getting loaded after an
14193 * Broadcom tells me:
14194 * ...the DMA engine is connected to the GRC block and a DMA
14195 * reset may affect the GRC block in some unpredictable way...
14196 * The behavior of resets to individual blocks has not been tested.
14198 * Broadcom noted the GRC reset will also reset all sub-components.
14201 test_desc.cqid_sqid = (13 << 8) | 2;
14203 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14206 test_desc.cqid_sqid = (16 << 8) | 7;
14208 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14211 test_desc.flags = 0x00000005;
14213 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14216 val = *(((u32 *)&test_desc) + i);
14217 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14218 sram_dma_descs + (i * sizeof(u32)));
14219 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14221 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14224 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14226 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14229 for (i = 0; i < 40; i++) {
14233 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14235 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14236 if ((val & 0xffff) == sram_dma_descs) {
14247 #define TEST_BUFFER_SIZE 0x2000
14249 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14250 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14254 static int __devinit tg3_test_dma(struct tg3 *tp)
14256 dma_addr_t buf_dma;
14257 u32 *buf, saved_dma_rwctrl;
14260 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14261 &buf_dma, GFP_KERNEL);
14267 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14268 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14270 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14272 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14275 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14276 /* DMA read watermark not used on PCIE */
14277 tp->dma_rwctrl |= 0x00180000;
14278 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14279 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14280 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14281 tp->dma_rwctrl |= 0x003f0000;
14283 tp->dma_rwctrl |= 0x003f000f;
14285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14286 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14287 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14288 u32 read_water = 0x7;
14290 /* If the 5704 is behind the EPB bridge, we can
14291 * do the less restrictive ONE_DMA workaround for
14292 * better performance.
14294 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14295 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14296 tp->dma_rwctrl |= 0x8000;
14297 else if (ccval == 0x6 || ccval == 0x7)
14298 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14302 /* Set bit 23 to enable PCIX hw bug fix */
14304 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14305 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14307 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14308 /* 5780 always in PCIX mode */
14309 tp->dma_rwctrl |= 0x00144000;
14310 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14311 /* 5714 always in PCIX mode */
14312 tp->dma_rwctrl |= 0x00148000;
14314 tp->dma_rwctrl |= 0x001b000f;
14318 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14319 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14320 tp->dma_rwctrl &= 0xfffffff0;
14322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14323 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14324 /* Remove this if it causes problems for some boards. */
14325 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14327 /* On 5700/5701 chips, we need to set this bit.
14328 * Otherwise the chip will issue cacheline transactions
14329 * to streamable DMA memory with not all the byte
14330 * enables turned on. This is an error on several
14331 * RISC PCI controllers, in particular sparc64.
14333 * On 5703/5704 chips, this bit has been reassigned
14334 * a different meaning. In particular, it is used
14335 * on those chips to enable a PCI-X workaround.
14337 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14340 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14343 /* Unneeded, already done by tg3_get_invariants. */
14344 tg3_switch_clocks(tp);
14347 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14348 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14351 /* It is best to perform DMA test with maximum write burst size
14352 * to expose the 5700/5701 write DMA bug.
14354 saved_dma_rwctrl = tp->dma_rwctrl;
14355 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14356 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14361 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14364 /* Send the buffer to the chip. */
14365 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14367 dev_err(&tp->pdev->dev,
14368 "%s: Buffer write failed. err = %d\n",
14374 /* validate data reached card RAM correctly. */
14375 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14377 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14378 if (le32_to_cpu(val) != p[i]) {
14379 dev_err(&tp->pdev->dev,
14380 "%s: Buffer corrupted on device! "
14381 "(%d != %d)\n", __func__, val, i);
14382 /* ret = -ENODEV here? */
14387 /* Now read it back. */
14388 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14390 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14391 "err = %d\n", __func__, ret);
14396 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14400 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14401 DMA_RWCTRL_WRITE_BNDRY_16) {
14402 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14403 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14404 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14407 dev_err(&tp->pdev->dev,
14408 "%s: Buffer corrupted on read back! "
14409 "(%d != %d)\n", __func__, p[i], i);
14415 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14421 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14422 DMA_RWCTRL_WRITE_BNDRY_16) {
14424 /* DMA test passed without adjusting DMA boundary,
14425 * now look for chipsets that are known to expose the
14426 * DMA bug without failing the test.
14428 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14429 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14430 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14432 /* Safe to use the calculated DMA boundary. */
14433 tp->dma_rwctrl = saved_dma_rwctrl;
14436 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14440 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14445 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14447 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14448 tp->bufmgr_config.mbuf_read_dma_low_water =
14449 DEFAULT_MB_RDMA_LOW_WATER_5705;
14450 tp->bufmgr_config.mbuf_mac_rx_low_water =
14451 DEFAULT_MB_MACRX_LOW_WATER_57765;
14452 tp->bufmgr_config.mbuf_high_water =
14453 DEFAULT_MB_HIGH_WATER_57765;
14455 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14456 DEFAULT_MB_RDMA_LOW_WATER_5705;
14457 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14458 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14459 tp->bufmgr_config.mbuf_high_water_jumbo =
14460 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14461 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14462 tp->bufmgr_config.mbuf_read_dma_low_water =
14463 DEFAULT_MB_RDMA_LOW_WATER_5705;
14464 tp->bufmgr_config.mbuf_mac_rx_low_water =
14465 DEFAULT_MB_MACRX_LOW_WATER_5705;
14466 tp->bufmgr_config.mbuf_high_water =
14467 DEFAULT_MB_HIGH_WATER_5705;
14468 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14469 tp->bufmgr_config.mbuf_mac_rx_low_water =
14470 DEFAULT_MB_MACRX_LOW_WATER_5906;
14471 tp->bufmgr_config.mbuf_high_water =
14472 DEFAULT_MB_HIGH_WATER_5906;
14475 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14476 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14477 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14478 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14479 tp->bufmgr_config.mbuf_high_water_jumbo =
14480 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14482 tp->bufmgr_config.mbuf_read_dma_low_water =
14483 DEFAULT_MB_RDMA_LOW_WATER;
14484 tp->bufmgr_config.mbuf_mac_rx_low_water =
14485 DEFAULT_MB_MACRX_LOW_WATER;
14486 tp->bufmgr_config.mbuf_high_water =
14487 DEFAULT_MB_HIGH_WATER;
14489 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14490 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14491 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14492 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14493 tp->bufmgr_config.mbuf_high_water_jumbo =
14494 DEFAULT_MB_HIGH_WATER_JUMBO;
14497 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14498 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14501 static char * __devinit tg3_phy_string(struct tg3 *tp)
14503 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14504 case TG3_PHY_ID_BCM5400: return "5400";
14505 case TG3_PHY_ID_BCM5401: return "5401";
14506 case TG3_PHY_ID_BCM5411: return "5411";
14507 case TG3_PHY_ID_BCM5701: return "5701";
14508 case TG3_PHY_ID_BCM5703: return "5703";
14509 case TG3_PHY_ID_BCM5704: return "5704";
14510 case TG3_PHY_ID_BCM5705: return "5705";
14511 case TG3_PHY_ID_BCM5750: return "5750";
14512 case TG3_PHY_ID_BCM5752: return "5752";
14513 case TG3_PHY_ID_BCM5714: return "5714";
14514 case TG3_PHY_ID_BCM5780: return "5780";
14515 case TG3_PHY_ID_BCM5755: return "5755";
14516 case TG3_PHY_ID_BCM5787: return "5787";
14517 case TG3_PHY_ID_BCM5784: return "5784";
14518 case TG3_PHY_ID_BCM5756: return "5722/5756";
14519 case TG3_PHY_ID_BCM5906: return "5906";
14520 case TG3_PHY_ID_BCM5761: return "5761";
14521 case TG3_PHY_ID_BCM5718C: return "5718C";
14522 case TG3_PHY_ID_BCM5718S: return "5718S";
14523 case TG3_PHY_ID_BCM57765: return "57765";
14524 case TG3_PHY_ID_BCM5719C: return "5719C";
14525 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14526 case 0: return "serdes";
14527 default: return "unknown";
14531 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14533 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14534 strcpy(str, "PCI Express");
14536 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14537 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14539 strcpy(str, "PCIX:");
14541 if ((clock_ctrl == 7) ||
14542 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14543 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14544 strcat(str, "133MHz");
14545 else if (clock_ctrl == 0)
14546 strcat(str, "33MHz");
14547 else if (clock_ctrl == 2)
14548 strcat(str, "50MHz");
14549 else if (clock_ctrl == 4)
14550 strcat(str, "66MHz");
14551 else if (clock_ctrl == 6)
14552 strcat(str, "100MHz");
14554 strcpy(str, "PCI:");
14555 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14556 strcat(str, "66MHz");
14558 strcat(str, "33MHz");
14560 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14561 strcat(str, ":32-bit");
14563 strcat(str, ":64-bit");
14567 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14569 struct pci_dev *peer;
14570 unsigned int func, devnr = tp->pdev->devfn & ~7;
14572 for (func = 0; func < 8; func++) {
14573 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14574 if (peer && peer != tp->pdev)
14578 /* 5704 can be configured in single-port mode, set peer to
14579 * tp->pdev in that case.
14587 * We don't need to keep the refcount elevated; there's no way
14588 * to remove one half of this device without removing the other
14595 static void __devinit tg3_init_coal(struct tg3 *tp)
14597 struct ethtool_coalesce *ec = &tp->coal;
14599 memset(ec, 0, sizeof(*ec));
14600 ec->cmd = ETHTOOL_GCOALESCE;
14601 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14602 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14603 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14604 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14605 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14606 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14607 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14608 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14609 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14611 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14612 HOSTCC_MODE_CLRTICK_TXBD)) {
14613 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14614 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14615 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14616 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14619 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14620 ec->rx_coalesce_usecs_irq = 0;
14621 ec->tx_coalesce_usecs_irq = 0;
14622 ec->stats_block_coalesce_usecs = 0;
14626 static const struct net_device_ops tg3_netdev_ops = {
14627 .ndo_open = tg3_open,
14628 .ndo_stop = tg3_close,
14629 .ndo_start_xmit = tg3_start_xmit,
14630 .ndo_get_stats64 = tg3_get_stats64,
14631 .ndo_validate_addr = eth_validate_addr,
14632 .ndo_set_multicast_list = tg3_set_rx_mode,
14633 .ndo_set_mac_address = tg3_set_mac_addr,
14634 .ndo_do_ioctl = tg3_ioctl,
14635 .ndo_tx_timeout = tg3_tx_timeout,
14636 .ndo_change_mtu = tg3_change_mtu,
14637 #ifdef CONFIG_NET_POLL_CONTROLLER
14638 .ndo_poll_controller = tg3_poll_controller,
14642 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14643 .ndo_open = tg3_open,
14644 .ndo_stop = tg3_close,
14645 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14646 .ndo_get_stats64 = tg3_get_stats64,
14647 .ndo_validate_addr = eth_validate_addr,
14648 .ndo_set_multicast_list = tg3_set_rx_mode,
14649 .ndo_set_mac_address = tg3_set_mac_addr,
14650 .ndo_do_ioctl = tg3_ioctl,
14651 .ndo_tx_timeout = tg3_tx_timeout,
14652 .ndo_change_mtu = tg3_change_mtu,
14653 #ifdef CONFIG_NET_POLL_CONTROLLER
14654 .ndo_poll_controller = tg3_poll_controller,
14658 static int __devinit tg3_init_one(struct pci_dev *pdev,
14659 const struct pci_device_id *ent)
14661 struct net_device *dev;
14663 int i, err, pm_cap;
14664 u32 sndmbx, rcvmbx, intmbx;
14666 u64 dma_mask, persist_dma_mask;
14668 printk_once(KERN_INFO "%s\n", version);
14670 err = pci_enable_device(pdev);
14672 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14676 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14678 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14679 goto err_out_disable_pdev;
14682 pci_set_master(pdev);
14684 /* Find power-management capability. */
14685 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14687 dev_err(&pdev->dev,
14688 "Cannot find Power Management capability, aborting\n");
14690 goto err_out_free_res;
14693 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14695 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14697 goto err_out_free_res;
14700 SET_NETDEV_DEV(dev, &pdev->dev);
14702 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14704 tp = netdev_priv(dev);
14707 tp->pm_cap = pm_cap;
14708 tp->rx_mode = TG3_DEF_RX_MODE;
14709 tp->tx_mode = TG3_DEF_TX_MODE;
14712 tp->msg_enable = tg3_debug;
14714 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14716 /* The word/byte swap controls here control register access byte
14717 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14720 tp->misc_host_ctrl =
14721 MISC_HOST_CTRL_MASK_PCI_INT |
14722 MISC_HOST_CTRL_WORD_SWAP |
14723 MISC_HOST_CTRL_INDIR_ACCESS |
14724 MISC_HOST_CTRL_PCISTATE_RW;
14726 /* The NONFRM (non-frame) byte/word swap controls take effect
14727 * on descriptor entries, anything which isn't packet data.
14729 * The StrongARM chips on the board (one for tx, one for rx)
14730 * are running in big-endian mode.
14732 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14733 GRC_MODE_WSWAP_NONFRM_DATA);
14734 #ifdef __BIG_ENDIAN
14735 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14737 spin_lock_init(&tp->lock);
14738 spin_lock_init(&tp->indirect_lock);
14739 INIT_WORK(&tp->reset_task, tg3_reset_task);
14741 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14743 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14745 goto err_out_free_dev;
14748 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14749 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14751 dev->ethtool_ops = &tg3_ethtool_ops;
14752 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14753 dev->irq = pdev->irq;
14755 err = tg3_get_invariants(tp);
14757 dev_err(&pdev->dev,
14758 "Problem fetching invariants of chip, aborting\n");
14759 goto err_out_iounmap;
14762 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14763 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14764 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14765 dev->netdev_ops = &tg3_netdev_ops;
14767 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14770 /* The EPB bridge inside 5714, 5715, and 5780 and any
14771 * device behind the EPB cannot support DMA addresses > 40-bit.
14772 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14773 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14774 * do DMA address check in tg3_start_xmit().
14776 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14777 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14778 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14779 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14780 #ifdef CONFIG_HIGHMEM
14781 dma_mask = DMA_BIT_MASK(64);
14784 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14786 /* Configure DMA attributes. */
14787 if (dma_mask > DMA_BIT_MASK(32)) {
14788 err = pci_set_dma_mask(pdev, dma_mask);
14790 dev->features |= NETIF_F_HIGHDMA;
14791 err = pci_set_consistent_dma_mask(pdev,
14794 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14795 "DMA for consistent allocations\n");
14796 goto err_out_iounmap;
14800 if (err || dma_mask == DMA_BIT_MASK(32)) {
14801 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14803 dev_err(&pdev->dev,
14804 "No usable DMA configuration, aborting\n");
14805 goto err_out_iounmap;
14809 tg3_init_bufmgr_config(tp);
14811 /* Selectively allow TSO based on operating conditions */
14812 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14813 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14814 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14816 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14817 tp->fw_needed = NULL;
14820 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14821 tp->fw_needed = FIRMWARE_TG3;
14823 /* TSO is on by default on chips that support hardware TSO.
14824 * Firmware TSO on older chips gives lower performance, so it
14825 * is off by default, but can be enabled using ethtool.
14827 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14828 (dev->features & NETIF_F_IP_CSUM)) {
14829 dev->features |= NETIF_F_TSO;
14830 vlan_features_add(dev, NETIF_F_TSO);
14832 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14833 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14834 if (dev->features & NETIF_F_IPV6_CSUM) {
14835 dev->features |= NETIF_F_TSO6;
14836 vlan_features_add(dev, NETIF_F_TSO6);
14838 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14839 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14840 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14841 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14843 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14844 dev->features |= NETIF_F_TSO_ECN;
14845 vlan_features_add(dev, NETIF_F_TSO_ECN);
14849 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14850 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14851 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14852 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14853 tp->rx_pending = 63;
14856 err = tg3_get_device_address(tp);
14858 dev_err(&pdev->dev,
14859 "Could not obtain valid ethernet address, aborting\n");
14860 goto err_out_iounmap;
14863 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14864 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14865 if (!tp->aperegs) {
14866 dev_err(&pdev->dev,
14867 "Cannot map APE registers, aborting\n");
14869 goto err_out_iounmap;
14872 tg3_ape_lock_init(tp);
14874 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14875 tg3_read_dash_ver(tp);
14879 * Reset chip in case UNDI or EFI driver did not shutdown
14880 * DMA self test will enable WDMAC and we'll see (spurious)
14881 * pending DMA on the PCI bus at that point.
14883 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14884 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14885 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14886 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14889 err = tg3_test_dma(tp);
14891 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14892 goto err_out_apeunmap;
14895 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14896 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14897 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14898 for (i = 0; i < tp->irq_max; i++) {
14899 struct tg3_napi *tnapi = &tp->napi[i];
14902 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14904 tnapi->int_mbox = intmbx;
14910 tnapi->consmbox = rcvmbx;
14911 tnapi->prodmbox = sndmbx;
14914 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14916 tnapi->coal_now = HOSTCC_MODE_NOW;
14918 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14922 * If we support MSIX, we'll be using RSS. If we're using
14923 * RSS, the first vector only handles link interrupts and the
14924 * remaining vectors handle rx and tx interrupts. Reuse the
14925 * mailbox values for the next iteration. The values we setup
14926 * above are still useful for the single vectored mode.
14941 pci_set_drvdata(pdev, dev);
14943 err = register_netdev(dev);
14945 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14946 goto err_out_apeunmap;
14949 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14950 tp->board_part_number,
14951 tp->pci_chip_rev_id,
14952 tg3_bus_string(tp, str),
14955 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14956 struct phy_device *phydev;
14957 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14959 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14960 phydev->drv->name, dev_name(&phydev->dev));
14964 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14965 ethtype = "10/100Base-TX";
14966 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14967 ethtype = "1000Base-SX";
14969 ethtype = "10/100/1000Base-T";
14971 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14972 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14973 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14976 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14977 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14978 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14979 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14980 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14981 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14982 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14984 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14985 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14991 iounmap(tp->aperegs);
14992 tp->aperegs = NULL;
15005 pci_release_regions(pdev);
15007 err_out_disable_pdev:
15008 pci_disable_device(pdev);
15009 pci_set_drvdata(pdev, NULL);
15013 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15015 struct net_device *dev = pci_get_drvdata(pdev);
15018 struct tg3 *tp = netdev_priv(dev);
15021 release_firmware(tp->fw);
15023 cancel_work_sync(&tp->reset_task);
15025 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15030 unregister_netdev(dev);
15032 iounmap(tp->aperegs);
15033 tp->aperegs = NULL;
15040 pci_release_regions(pdev);
15041 pci_disable_device(pdev);
15042 pci_set_drvdata(pdev, NULL);
15046 #ifdef CONFIG_PM_SLEEP
15047 static int tg3_suspend(struct device *device)
15049 struct pci_dev *pdev = to_pci_dev(device);
15050 struct net_device *dev = pci_get_drvdata(pdev);
15051 struct tg3 *tp = netdev_priv(dev);
15054 if (!netif_running(dev))
15057 flush_work_sync(&tp->reset_task);
15059 tg3_netif_stop(tp);
15061 del_timer_sync(&tp->timer);
15063 tg3_full_lock(tp, 1);
15064 tg3_disable_ints(tp);
15065 tg3_full_unlock(tp);
15067 netif_device_detach(dev);
15069 tg3_full_lock(tp, 0);
15070 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15071 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15072 tg3_full_unlock(tp);
15074 err = tg3_power_down_prepare(tp);
15078 tg3_full_lock(tp, 0);
15080 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15081 err2 = tg3_restart_hw(tp, 1);
15085 tp->timer.expires = jiffies + tp->timer_offset;
15086 add_timer(&tp->timer);
15088 netif_device_attach(dev);
15089 tg3_netif_start(tp);
15092 tg3_full_unlock(tp);
15101 static int tg3_resume(struct device *device)
15103 struct pci_dev *pdev = to_pci_dev(device);
15104 struct net_device *dev = pci_get_drvdata(pdev);
15105 struct tg3 *tp = netdev_priv(dev);
15108 if (!netif_running(dev))
15111 netif_device_attach(dev);
15113 tg3_full_lock(tp, 0);
15115 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15116 err = tg3_restart_hw(tp, 1);
15120 tp->timer.expires = jiffies + tp->timer_offset;
15121 add_timer(&tp->timer);
15123 tg3_netif_start(tp);
15126 tg3_full_unlock(tp);
15134 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15135 #define TG3_PM_OPS (&tg3_pm_ops)
15139 #define TG3_PM_OPS NULL
15141 #endif /* CONFIG_PM_SLEEP */
15143 static struct pci_driver tg3_driver = {
15144 .name = DRV_MODULE_NAME,
15145 .id_table = tg3_pci_tbl,
15146 .probe = tg3_init_one,
15147 .remove = __devexit_p(tg3_remove_one),
15148 .driver.pm = TG3_PM_OPS,
15151 static int __init tg3_init(void)
15153 return pci_register_driver(&tg3_driver);
15156 static void __exit tg3_cleanup(void)
15158 pci_unregister_driver(&tg3_driver);
15161 module_init(tg3_init);
15162 module_exit(tg3_cleanup);