2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <linux/interrupt.h>
27 * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
29 #define DIAG_TRANSFER_LIMIT 2048
32 * maximum number of bytes that can be
33 * handled atomically by DiagRead/DiagWrite
35 #define DIAG_TRANSFER_LIMIT 2048
45 * PCI-specific Target state
47 * NOTE: Structure is shared between Host software and Target firmware!
49 * Much of this may be of interest to the Host so
50 * HOST_INTEREST->hi_interconnect_state points here
51 * (and all members are 32-bit quantities in order to
52 * facilitate Host access). In particular, Host software is
53 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
56 /* Pipe configuration Target address */
57 /* NB: ce_pipe_config[CE_COUNT] */
60 /* Service to pipe map Target address */
61 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
64 /* number of MSI interrupts requested */
67 /* number of MSI interrupts granted */
70 /* Message Signalled Interrupt address */
77 * Data for firmware interrupt;
78 * MSI data for other interrupts are
79 * in various SoC registers
83 /* PCIE_PWR_METHOD_* */
84 u32 power_mgmt_method;
86 /* PCIE_CONFIG_FLAG_* */
90 /* PCIE_CONFIG_FLAG definitions */
91 #define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
93 /* Host software's Copy Engine configuration. */
94 #define CE_ATTR_FLAGS 0
97 * Configuration information for a Copy Engine pipe.
98 * Passed from Host to Target during startup (one per CE).
100 * NOTE: Structure is shared between Host software and Target firmware!
102 struct ce_pipe_config {
112 * Directions for interconnect pipe configuration.
113 * These definitions may be used during configuration and are shared
114 * between Host and Target.
116 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
117 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
118 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
119 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
120 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
121 * over the interconnect.
123 #define PIPEDIR_NONE 0
124 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
125 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
126 #define PIPEDIR_INOUT 3 /* bidirectional */
128 /* Establish a mapping between a service/direction and a pipe. */
129 struct service_to_pipe {
135 /* Per-pipe state. */
136 struct ath10k_pci_pipe {
137 /* Handle of underlying Copy Engine */
138 struct ath10k_ce_pipe *ce_hdl;
140 /* Our pipe number; facilitiates use of pipe_info ptrs. */
143 /* Convenience back pointer to hif_ce_state. */
144 struct ath10k *hif_ce_state;
148 /* protects compl_free and num_send_allowed */
149 spinlock_t pipe_lock;
151 struct ath10k_pci *ar_pci;
152 struct tasklet_struct intr;
156 struct pci_dev *pdev;
162 * Number of MSI interrupts granted, 0 --> using legacy PCI line
167 struct tasklet_struct intr_tq;
168 struct tasklet_struct msi_fw_err;
172 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
174 struct ath10k_hif_cb msg_callbacks_current;
176 /* Copy Engine used for Diagnostic Accesses */
177 struct ath10k_ce_pipe *ce_diag;
179 /* FIXME: document what this really protects */
182 /* Map CE id to ce_state */
183 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
184 struct timer_list rx_post_retry;
187 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
189 return (struct ath10k_pci *)ar->drv_priv;
192 #define ATH10K_PCI_RX_POST_RETRY_MS 50
193 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
194 #define PCIE_WAKE_TIMEOUT 5000 /* 5ms */
198 #define CDC_WAR_MAGIC_STR 0xceef0000
199 #define CDC_WAR_DATA_CE 4
202 * TODO: Should be a function call specific to each Target-type.
203 * This convoluted macro converts from Target CPU Virtual Address Space to CE
204 * Address Space. As part of this process, we conservatively fetch the current
205 * PCIE_BAR. MOST of the time, this should match the upper bits of PCI space
206 * for this device; but that's not guaranteed.
208 #define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr) \
209 (((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS| \
210 CORE_CTRL_ADDRESS)) & 0x7ff) << 21) | \
211 0x100000 | ((addr) & 0xfffff))
213 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
214 #define DIAG_ACCESS_CE_TIMEOUT_MS 10
216 /* Target exposes its registers for direct access. However before host can
217 * access them it needs to make sure the target is awake (ath10k_pci_wake,
218 * ath10k_pci_wake_wait, ath10k_pci_is_awake). Once target is awake it won't go
219 * to sleep unless host tells it to (ath10k_pci_sleep).
221 * If host tries to access target registers without waking it up it can
222 * scribble over host memory.
224 * If target is asleep waking it up may take up to even 2ms.
227 static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset,
230 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
232 iowrite32(value, ar_pci->mem + offset);
235 static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
237 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
239 return ioread32(ar_pci->mem + offset);
242 static inline u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
244 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
247 static inline void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
249 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
252 static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
254 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
256 return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
259 static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
261 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
263 iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);