2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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14 * similar Disclaimer requirement for further binary redistribution.
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16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
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39 * Definitions for the Atheros Wireless LAN controller driver.
41 #ifndef _DEV_ATH_ATHVAR_H
42 #define _DEV_ATH_ATHVAR_H
44 #include <linux/interrupt.h>
45 #include <linux/list.h>
46 #include <linux/wireless.h>
47 #include <linux/if_ether.h>
48 #include <linux/leds.h>
49 #include <linux/rfkill.h>
50 #include <linux/workqueue.h>
59 #define ATH_RXBUF 40 /* number of RX buffers */
60 #define ATH_TXBUF 200 /* number of TX buffers */
61 #define ATH_BCBUF 4 /* number of beacon buffers */
62 #define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
63 #define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
66 struct list_head list;
67 struct ath5k_desc *desc; /* virtual addr of desc */
68 dma_addr_t daddr; /* physical addr of desc */
69 struct sk_buff *skb; /* skbuff for buf */
70 dma_addr_t skbaddr;/* physical addr of skb data */
74 * Data transmit queue state. One of these exists for each
75 * hardware transmit queue. Packets sent to us from above
76 * are assigned to queues based on their priority. Not all
77 * devices support a complete set of hardware transmit queues.
78 * For those devices the array sc_ac2q will map multiple
79 * priorities to fewer hardware queues (typically all to one
83 unsigned int qnum; /* hardware q number */
84 u32 *link; /* link ptr in last TX desc */
85 struct list_head q; /* transmit queue */
86 spinlock_t lock; /* lock on q and link */
88 int txq_len; /* number of queued buffers */
90 unsigned int txq_stuck; /* informational counter */
93 #define ATH5K_LED_MAX_NAME_LEN 31
96 * State for LED triggers
100 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
101 struct ath5k_softc *sc; /* driver state */
102 struct led_classdev led_dev; /* led classdev */
106 struct ath5k_rfkill {
107 /* GPIO PIN for rfkill */
109 /* polarity of rfkill GPIO PIN */
111 /* RFKILL toggle tasklet */
112 struct tasklet_struct toggleq;
116 struct ath5k_statistics {
118 unsigned int antenna_rx[5]; /* frames count per antenna RX */
119 unsigned int antenna_tx[5]; /* frames count per antenna TX */
122 unsigned int rx_all_count; /* all RX frames, including errors */
123 unsigned int tx_all_count; /* all TX frames, including errors */
124 unsigned int rx_bytes_count; /* all RX bytes, including errored pks
125 * and the MAC headers for each packet
127 unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
128 * and the MAC headers and padding for
131 unsigned int rxerr_crc;
132 unsigned int rxerr_phy;
133 unsigned int rxerr_phy_code[32];
134 unsigned int rxerr_fifo;
135 unsigned int rxerr_decrypt;
136 unsigned int rxerr_mic;
137 unsigned int rxerr_proc;
138 unsigned int rxerr_jumbo;
139 unsigned int txerr_retry;
140 unsigned int txerr_fifo;
141 unsigned int txerr_filt;
144 unsigned int ack_fail;
145 unsigned int rts_fail;
147 unsigned int fcs_error;
148 unsigned int beacons;
150 unsigned int mib_intr;
151 unsigned int rxorn_intr;
152 unsigned int rxeol_intr;
156 #define ATH_CHAN_MAX (26+26+26+200+200)
158 #define ATH_CHAN_MAX (14+14+14+252+20)
162 bool assoc; /* are we associated or not */
163 enum nl80211_iftype opmode;
165 struct ath5k_buf *bbuf; /* beacon buffer */
169 /* Software Carrier, keeps track of the driver state
170 * associated with an instance of a device */
172 struct pci_dev *pdev; /* for dma mapping */
173 void __iomem *iobase; /* address of the device */
174 struct mutex lock; /* dev-level lock */
175 struct ieee80211_hw *hw; /* IEEE 802.11 common */
176 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
177 struct ieee80211_channel channels[ATH_CHAN_MAX];
178 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
179 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
180 enum nl80211_iftype opmode;
181 struct ath5k_hw *ah; /* Atheros HW */
183 struct ieee80211_supported_band *curband;
185 #ifdef CONFIG_ATH5K_DEBUG
186 struct ath5k_dbg_info debug; /* debug info */
187 #endif /* CONFIG_ATH5K_DEBUG */
189 struct ath5k_buf *bufptr; /* allocated buffer ptr */
190 struct ath5k_desc *desc; /* TX/RX descriptors */
191 dma_addr_t desc_daddr; /* DMA (physical) address */
192 size_t desc_len; /* size of TX/RX descriptors */
194 DECLARE_BITMAP(status, 5);
195 #define ATH_STAT_INVALID 0 /* disable hardware accesses */
196 #define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
197 #define ATH_STAT_PROMISC 2
198 #define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
199 #define ATH_STAT_STARTED 4 /* opened & irqs enabled */
201 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
202 unsigned int curmode; /* current phy mode */
203 struct ieee80211_channel *curchan; /* current h/w channel */
207 enum ath5k_int imask; /* interrupt mask copy */
210 u8 bssidmask[ETH_ALEN];
212 unsigned int led_pin, /* GPIO pin for driving LED */
213 led_on; /* pin setting for LED on */
215 struct work_struct reset_work; /* deferred chip reset */
217 unsigned int rxbufsize; /* rx size based on mtu */
218 struct list_head rxbuf; /* receive buffer */
219 spinlock_t rxbuflock;
220 u32 *rxlink; /* link ptr in last RX desc */
221 struct tasklet_struct rxtq; /* rx intr tasklet */
222 struct ath5k_led rx_led; /* rx led */
224 struct list_head txbuf; /* transmit buffer */
225 spinlock_t txbuflock;
226 unsigned int txbuf_len; /* buf count in txbuf list */
227 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
228 struct tasklet_struct txtq; /* tx intr tasklet */
229 struct ath5k_led tx_led; /* tx led */
231 struct ath5k_rfkill rf_kill;
233 struct tasklet_struct calib; /* calibration tasklet */
235 spinlock_t block; /* protects beacon */
236 struct tasklet_struct beacontq; /* beacon intr tasklet */
237 struct list_head bcbuf; /* beacon buffer */
238 struct ieee80211_vif *bslot[ATH_BCBUF];
241 unsigned int bhalq, /* SW q for outgoing beacons */
242 bmisscount, /* missed beacon transmits */
243 bintval, /* beacon interval in TU */
245 unsigned int nexttbtt; /* next beacon time in TU */
246 struct ath5k_txq *cabq; /* content after beacon */
248 int power_level; /* Requested tx power in dbm */
249 bool assoc; /* associate state */
250 bool enable_beacon; /* true if beacons are on */
252 struct ath5k_statistics stats;
254 struct ath5k_ani_state ani_state;
255 struct tasklet_struct ani_tasklet; /* ANI calibration */
257 struct delayed_work tx_complete_work;
260 #define ath5k_hw_hasbssidmask(_ah) \
261 (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
262 #define ath5k_hw_hasveol(_ah) \
263 (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)