4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <linux/delay.h>
24 #include <linux/slab.h>
38 * Get the PHY Chip revision
40 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
47 * Set the radio chip access register
51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
62 /* ...wait until PHY is ready and read the selected radio revision */
63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
65 for (i = 0; i < 8; i++)
66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
68 if (ah->ah_version == AR5K_AR5210) {
69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
74 ((srev & 0x0f) << 4), 8);
77 /* Reset to the 5GHz mode */
78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
84 * Check if a channel is supported
86 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
88 /* Check if the channel is in our supported range */
89 if (flags & CHANNEL_2GHZ) {
90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
93 } else if (flags & CHANNEL_5GHZ)
94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
101 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
102 struct ieee80211_channel *channel)
106 if ((ah->ah_radio == AR5K_RF5112) ||
107 (ah->ah_radio == AR5K_RF5413) ||
108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
113 if ((channel->center_freq % refclk_freq != 0) &&
114 ((channel->center_freq % refclk_freq < 10) ||
115 (channel->center_freq % refclk_freq > 22)))
122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
124 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
125 const struct ath5k_rf_reg *rf_regs,
126 u32 val, u8 reg_id, bool set)
128 const struct ath5k_rf_reg *rfreg = NULL;
129 u8 offset, bank, num_bits, col, position;
131 u32 mask, data, last_bit, bits_shifted, first_bit;
137 rfb = ah->ah_rf_banks;
139 for (i = 0; i < ah->ah_rf_regs_count; i++) {
140 if (rf_regs[i].index == reg_id) {
146 if (rfb == NULL || rfreg == NULL) {
147 ATH5K_PRINTF("Rf register not found!\n");
148 /* should not happen */
153 num_bits = rfreg->field.len;
154 first_bit = rfreg->field.pos;
155 col = rfreg->field.col;
157 /* first_bit is an offset from bank's
158 * start. Since we have all banks on
159 * the same array, we use this offset
160 * to mark each bank's start */
161 offset = ah->ah_offset[bank];
164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
165 ATH5K_PRINTF("invalid values at offset %u\n", offset);
169 entry = ((first_bit - 1) / 8) + offset;
170 position = (first_bit - 1) % 8;
173 data = ath5k_hw_bitswap(val, num_bits);
175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
176 position = 0, entry++) {
178 last_bit = (position + bits_left > 8) ? 8 :
179 position + bits_left;
181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
186 rfb[entry] |= ((data << position) << (col * 8)) & mask;
187 data >>= (8 - position);
189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
191 bits_shifted += last_bit - position;
194 bits_left -= 8 - position;
197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
205 * @ah: the &struct ath5k_hw
206 * @channel: the currently set channel upon reset
208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
211 * Since delta slope is floating point we split it on its exponent and
212 * mantissa and provide these values on hw.
214 * For more infos i think this patent is related
215 * http://www.freepatentsonline.com/7184495.html
217 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
218 struct ieee80211_channel *channel)
220 /* Get exponent and mantissa and set it */
221 u32 coef_scaled, coef_exp, coef_man,
222 ds_coef_exp, ds_coef_man, clock;
224 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
225 !(channel->hw_value & CHANNEL_OFDM));
228 * ALGO: coef = (5 * clock / carrier_freq) / 2
229 * we scale coef by shifting clock value by 24 for
230 * better precision since we use integers */
231 switch (ah->ah_bwmode) {
232 case AR5K_BWMODE_40MHZ:
235 case AR5K_BWMODE_10MHZ:
238 case AR5K_BWMODE_5MHZ:
245 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
248 * ALGO: coef_exp = 14 - highest set bit position */
249 coef_exp = ilog2(coef_scaled);
251 /* Doesn't make sense if it's zero*/
252 if (!coef_scaled || !coef_exp)
255 /* Note: we've shifted coef_scaled by 24 */
256 coef_exp = 14 - (coef_exp - 24);
259 /* Get mantissa (significant digits)
260 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
261 coef_man = coef_scaled +
262 (1 << (24 - coef_exp - 1));
264 /* Calculate delta slope coefficient exponent
265 * and mantissa (remove scaling) and set them on hw */
266 ds_coef_man = coef_man >> (24 - coef_exp);
267 ds_coef_exp = coef_exp - 16;
269 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
270 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
271 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
272 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
277 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
280 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
286 /**********************\
287 * RF Gain optimization *
288 \**********************/
291 * This code is used to optimize RF gain on different environments
292 * (temperature mostly) based on feedback from a power detector.
294 * It's only used on RF5111 and RF5112, later RF chips seem to have
295 * auto adjustment on hw -notice they have a much smaller BANK 7 and
296 * no gain optimization ladder-.
298 * For more infos check out this patent doc
299 * http://www.freepatentsonline.com/7400691.html
301 * This paper describes power drops as seen on the receiver due to
303 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
304 * %20of%20Power%20Control.pdf
306 * And this is the MadWiFi bug entry related to the above
307 * http://madwifi-project.org/ticket/1659
308 * with various measurements and diagrams
310 * TODO: Deal with power drops due to probes by setting an apropriate
311 * tx power on the probe packets ! Make this part of the calibration process.
314 /* Initialize ah_gain durring attach */
315 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
317 /* Initialize the gain optimization values */
318 switch (ah->ah_radio) {
320 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
321 ah->ah_gain.g_low = 20;
322 ah->ah_gain.g_high = 35;
323 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
326 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
327 ah->ah_gain.g_low = 20;
328 ah->ah_gain.g_high = 85;
329 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
338 /* Schedule a gain probe check on the next transmited packet.
339 * That means our next packet is going to be sent with lower
340 * tx power and a Peak to Average Power Detector (PAPD) will try
341 * to measure the gain.
343 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
344 * just after we enable the probe so that we don't mess with
345 * standard traffic ? Maybe it's time to use sw interrupts and
346 * a probe tasklet !!!
348 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
351 /* Skip if gain calibration is inactive or
352 * we already handle a probe request */
353 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
356 /* Send the packet with 2dB below max power as
357 * patent doc suggest */
358 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
359 AR5K_PHY_PAPD_PROBE_TXPOWER) |
360 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
362 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
366 /* Calculate gain_F measurement correction
367 * based on the current step for RF5112 rev. 2 */
368 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
372 const struct ath5k_gain_opt *go;
373 const struct ath5k_gain_opt_step *g_step;
374 const struct ath5k_rf_reg *rf_regs;
376 /* Only RF5112 Rev. 2 supports it */
377 if ((ah->ah_radio != AR5K_RF5112) ||
378 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
381 go = &rfgain_opt_5112;
382 rf_regs = rf_regs_5112a;
383 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
385 g_step = &go->go_step[ah->ah_gain.g_step_idx];
387 if (ah->ah_rf_banks == NULL)
390 rf = ah->ah_rf_banks;
391 ah->ah_gain.g_f_corr = 0;
393 /* No VGA (Variable Gain Amplifier) override, skip */
394 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
397 /* Mix gain stepping */
398 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
400 /* Mix gain override */
401 mix = g_step->gos_param[0];
405 ah->ah_gain.g_f_corr = step * 2;
408 ah->ah_gain.g_f_corr = (step - 5) * 2;
411 ah->ah_gain.g_f_corr = step;
414 ah->ah_gain.g_f_corr = 0;
418 return ah->ah_gain.g_f_corr;
421 /* Check if current gain_F measurement is in the range of our
422 * power detector windows. If we get a measurement outside range
423 * we know it's not accurate (detectors can't measure anything outside
424 * their detection window) so we must ignore it */
425 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
427 const struct ath5k_rf_reg *rf_regs;
428 u32 step, mix_ovr, level[4];
431 if (ah->ah_rf_banks == NULL)
434 rf = ah->ah_rf_banks;
436 if (ah->ah_radio == AR5K_RF5111) {
438 rf_regs = rf_regs_5111;
439 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
441 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
445 level[1] = (step == 63) ? 50 : step + 4;
446 level[2] = (step != 63) ? 64 : level[0];
447 level[3] = level[2] + 50 ;
449 ah->ah_gain.g_high = level[3] -
450 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
451 ah->ah_gain.g_low = level[0] +
452 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
455 rf_regs = rf_regs_5112;
456 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
458 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
461 level[0] = level[2] = 0;
464 level[1] = level[3] = 83;
466 level[1] = level[3] = 107;
467 ah->ah_gain.g_high = 55;
471 return (ah->ah_gain.g_current >= level[0] &&
472 ah->ah_gain.g_current <= level[1]) ||
473 (ah->ah_gain.g_current >= level[2] &&
474 ah->ah_gain.g_current <= level[3]);
477 /* Perform gain_F adjustment by choosing the right set
478 * of parameters from RF gain optimization ladder */
479 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
481 const struct ath5k_gain_opt *go;
482 const struct ath5k_gain_opt_step *g_step;
485 switch (ah->ah_radio) {
487 go = &rfgain_opt_5111;
490 go = &rfgain_opt_5112;
496 g_step = &go->go_step[ah->ah_gain.g_step_idx];
498 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
500 /* Reached maximum */
501 if (ah->ah_gain.g_step_idx == 0)
504 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
505 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
506 ah->ah_gain.g_step_idx > 0;
507 g_step = &go->go_step[ah->ah_gain.g_step_idx])
508 ah->ah_gain.g_target -= 2 *
509 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
516 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
518 /* Reached minimum */
519 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
522 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
523 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
524 ah->ah_gain.g_step_idx < go->go_steps_count-1;
525 g_step = &go->go_step[ah->ah_gain.g_step_idx])
526 ah->ah_gain.g_target -= 2 *
527 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
535 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
536 "ret %d, gain step %u, current gain %u, target gain %u\n",
537 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
538 ah->ah_gain.g_target);
543 /* Main callback for thermal RF gain calibration engine
544 * Check for a new gain reading and schedule an adjustment
547 * TODO: Use sw interrupt to schedule reset if gain_F needs
549 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
552 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
554 if (ah->ah_rf_banks == NULL ||
555 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
556 return AR5K_RFGAIN_INACTIVE;
558 /* No check requested, either engine is inactive
559 * or an adjustment is already requested */
560 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
563 /* Read the PAPD (Peak to Average Power Detector)
565 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
567 /* No probe is scheduled, read gain_F measurement */
568 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
569 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
570 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
572 /* If tx packet is CCK correct the gain_F measurement
573 * by cck ofdm gain delta */
574 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
575 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
576 ah->ah_gain.g_current +=
577 ee->ee_cck_ofdm_gain_delta;
579 ah->ah_gain.g_current +=
580 AR5K_GAIN_CCK_PROBE_CORR;
583 /* Further correct gain_F measurement for
585 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
586 ath5k_hw_rf_gainf_corr(ah);
587 ah->ah_gain.g_current =
588 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
589 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
593 /* Check if measurement is ok and if we need
594 * to adjust gain, schedule a gain adjustment,
595 * else switch back to the acive state */
596 if (ath5k_hw_rf_check_gainf_readback(ah) &&
597 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
598 ath5k_hw_rf_gainf_adjust(ah)) {
599 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
601 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
606 return ah->ah_gain.g_state;
609 /* Write initial RF gain table to set the RF sensitivity
610 * this one works on all RF chips and has nothing to do
611 * with gain_F calibration */
612 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
614 const struct ath5k_ini_rfgain *ath5k_rfg;
615 unsigned int i, size, index;
617 switch (ah->ah_radio) {
619 ath5k_rfg = rfgain_5111;
620 size = ARRAY_SIZE(rfgain_5111);
623 ath5k_rfg = rfgain_5112;
624 size = ARRAY_SIZE(rfgain_5112);
627 ath5k_rfg = rfgain_2413;
628 size = ARRAY_SIZE(rfgain_2413);
631 ath5k_rfg = rfgain_2316;
632 size = ARRAY_SIZE(rfgain_2316);
635 ath5k_rfg = rfgain_5413;
636 size = ARRAY_SIZE(rfgain_5413);
640 ath5k_rfg = rfgain_2425;
641 size = ARRAY_SIZE(rfgain_2425);
647 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
649 for (i = 0; i < size; i++) {
651 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
652 (u32)ath5k_rfg[i].rfg_register);
660 /********************\
661 * RF Registers setup *
662 \********************/
665 * Setup RF registers by writing RF buffer on hw
667 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
668 struct ieee80211_channel *channel, unsigned int mode)
670 const struct ath5k_rf_reg *rf_regs;
671 const struct ath5k_ini_rfbuffer *ini_rfb;
672 const struct ath5k_gain_opt *go = NULL;
673 const struct ath5k_gain_opt_step *g_step;
674 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
677 int i, obdb = -1, bank = -1;
679 switch (ah->ah_radio) {
681 rf_regs = rf_regs_5111;
682 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
684 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
685 go = &rfgain_opt_5111;
688 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
689 rf_regs = rf_regs_5112a;
690 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
692 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
694 rf_regs = rf_regs_5112;
695 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
697 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
699 go = &rfgain_opt_5112;
702 rf_regs = rf_regs_2413;
703 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
705 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
708 rf_regs = rf_regs_2316;
709 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
711 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
714 rf_regs = rf_regs_5413;
715 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
717 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
720 rf_regs = rf_regs_2425;
721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
723 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
726 rf_regs = rf_regs_2425;
727 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
728 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
730 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
733 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
740 /* If it's the first time we set RF buffer, allocate
741 * ah->ah_rf_banks based on ah->ah_rf_banks_size
743 if (ah->ah_rf_banks == NULL) {
744 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
746 if (ah->ah_rf_banks == NULL) {
747 ATH5K_ERR(ah->ah_sc, "out of memory\n");
752 /* Copy values to modify them */
753 rfb = ah->ah_rf_banks;
755 for (i = 0; i < ah->ah_rf_banks_size; i++) {
756 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
757 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
761 /* Bank changed, write down the offset */
762 if (bank != ini_rfb[i].rfb_bank) {
763 bank = ini_rfb[i].rfb_bank;
764 ah->ah_offset[bank] = i;
767 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
770 /* Set Output and Driver bias current (OB/DB) */
771 if (channel->hw_value & CHANNEL_2GHZ) {
773 if (channel->hw_value & CHANNEL_CCK)
774 ee_mode = AR5K_EEPROM_MODE_11B;
776 ee_mode = AR5K_EEPROM_MODE_11G;
778 /* For RF511X/RF211X combination we
779 * use b_OB and b_DB parameters stored
780 * in eeprom on ee->ee_ob[ee_mode][0]
782 * For all other chips we use OB/DB for 2Ghz
783 * stored in the b/g modal section just like
784 * 802.11a on ee->ee_ob[ee_mode][1] */
785 if ((ah->ah_radio == AR5K_RF5111) ||
786 (ah->ah_radio == AR5K_RF5112))
791 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
792 AR5K_RF_OB_2GHZ, true);
794 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
795 AR5K_RF_DB_2GHZ, true);
797 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
798 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
799 (ah->ah_radio == AR5K_RF5111)) {
801 /* For 11a, Turbo and XR we need to choose
802 * OB/DB based on frequency range */
803 ee_mode = AR5K_EEPROM_MODE_11A;
804 obdb = channel->center_freq >= 5725 ? 3 :
805 (channel->center_freq >= 5500 ? 2 :
806 (channel->center_freq >= 5260 ? 1 :
807 (channel->center_freq > 4000 ? 0 : -1)));
812 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
813 AR5K_RF_OB_5GHZ, true);
815 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
816 AR5K_RF_DB_5GHZ, true);
819 g_step = &go->go_step[ah->ah_gain.g_step_idx];
821 /* Set turbo mode (N/A on RF5413) */
822 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
823 (ah->ah_radio != AR5K_RF5413))
824 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
826 /* Bank Modifications (chip-specific) */
827 if (ah->ah_radio == AR5K_RF5111) {
829 /* Set gain_F settings according to current step */
830 if (channel->hw_value & CHANNEL_OFDM) {
832 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
833 AR5K_PHY_FRAME_CTL_TX_CLIP,
834 g_step->gos_param[0]);
836 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
837 AR5K_RF_PWD_90, true);
839 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
840 AR5K_RF_PWD_84, true);
842 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
843 AR5K_RF_RFGAIN_SEL, true);
845 /* We programmed gain_F parameters, switch back
847 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
853 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
854 AR5K_RF_PWD_XPD, true);
856 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
857 AR5K_RF_XPD_GAIN, true);
859 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
860 AR5K_RF_GAIN_I, true);
862 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
863 AR5K_RF_PLO_SEL, true);
865 /* Tweak power detectors for half/quarter rate support */
866 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
867 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
870 ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
871 AR5K_RF_WAIT_S, true);
873 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
876 ath5k_hw_rfb_op(ah, rf_regs, wait_i,
877 AR5K_RF_WAIT_I, true);
878 ath5k_hw_rfb_op(ah, rf_regs, 3,
879 AR5K_RF_MAX_TIME, true);
884 if (ah->ah_radio == AR5K_RF5112) {
886 /* Set gain_F settings according to current step */
887 if (channel->hw_value & CHANNEL_OFDM) {
889 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
890 AR5K_RF_MIXGAIN_OVR, true);
892 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
893 AR5K_RF_PWD_138, true);
895 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
896 AR5K_RF_PWD_137, true);
898 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
899 AR5K_RF_PWD_136, true);
901 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
902 AR5K_RF_PWD_132, true);
904 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
905 AR5K_RF_PWD_131, true);
907 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
908 AR5K_RF_PWD_130, true);
910 /* We programmed gain_F parameters, switch back
912 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
917 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
918 AR5K_RF_XPD_SEL, true);
920 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
921 /* Rev. 1 supports only one xpd */
922 ath5k_hw_rfb_op(ah, rf_regs,
923 ee->ee_x_gain[ee_mode],
924 AR5K_RF_XPD_GAIN, true);
927 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
928 if (ee->ee_pd_gains[ee_mode] > 1) {
929 ath5k_hw_rfb_op(ah, rf_regs,
931 AR5K_RF_PD_GAIN_LO, true);
932 ath5k_hw_rfb_op(ah, rf_regs,
934 AR5K_RF_PD_GAIN_HI, true);
936 ath5k_hw_rfb_op(ah, rf_regs,
938 AR5K_RF_PD_GAIN_LO, true);
939 ath5k_hw_rfb_op(ah, rf_regs,
941 AR5K_RF_PD_GAIN_HI, true);
944 /* Lower synth voltage on Rev 2 */
945 ath5k_hw_rfb_op(ah, rf_regs, 2,
946 AR5K_RF_HIGH_VC_CP, true);
948 ath5k_hw_rfb_op(ah, rf_regs, 2,
949 AR5K_RF_MID_VC_CP, true);
951 ath5k_hw_rfb_op(ah, rf_regs, 2,
952 AR5K_RF_LOW_VC_CP, true);
954 ath5k_hw_rfb_op(ah, rf_regs, 2,
955 AR5K_RF_PUSH_UP, true);
957 /* Decrease power consumption on 5213+ BaseBand */
958 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
959 ath5k_hw_rfb_op(ah, rf_regs, 1,
960 AR5K_RF_PAD2GND, true);
962 ath5k_hw_rfb_op(ah, rf_regs, 1,
963 AR5K_RF_XB2_LVL, true);
965 ath5k_hw_rfb_op(ah, rf_regs, 1,
966 AR5K_RF_XB5_LVL, true);
968 ath5k_hw_rfb_op(ah, rf_regs, 1,
969 AR5K_RF_PWD_167, true);
971 ath5k_hw_rfb_op(ah, rf_regs, 1,
972 AR5K_RF_PWD_166, true);
976 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
977 AR5K_RF_GAIN_I, true);
979 /* Tweak power detector for half/quarter rates */
980 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
981 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
984 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
987 ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
988 AR5K_RF_PD_PERIOD_A, true);
989 ath5k_hw_rfb_op(ah, rf_regs, 0xf,
990 AR5K_RF_PD_DELAY_A, true);
995 if (ah->ah_radio == AR5K_RF5413 &&
996 channel->hw_value & CHANNEL_2GHZ) {
998 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
1001 /* Set optimum value for early revisions (on pci-e chips) */
1002 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
1003 ah->ah_mac_srev < AR5K_SREV_AR5413)
1004 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
1005 AR5K_RF_PWD_ICLOBUF_2G, true);
1009 /* Write RF banks on hw */
1010 for (i = 0; i < ah->ah_rf_banks_size; i++) {
1012 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
1019 /**************************\
1020 PHY/RF channel functions
1021 \**************************/
1024 * Convertion needed for RF5110
1026 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1031 * Convert IEEE channel/MHz to an internal channel value used
1032 * by the AR5210 chipset. This has not been verified with
1033 * newer chipsets like the AR5212A who have a completely
1034 * different RF/PHY part.
1036 athchan = (ath5k_hw_bitswap(
1037 (ieee80211_frequency_to_channel(
1038 channel->center_freq) - 24) / 2, 5)
1039 << 1) | (1 << 6) | 0x1;
1044 * Set channel on RF5110
1046 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1047 struct ieee80211_channel *channel)
1052 * Set the channel and wait
1054 data = ath5k_hw_rf5110_chan2athchan(channel);
1055 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1056 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1063 * Convertion needed for 5111
1065 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1066 struct ath5k_athchan_2ghz *athchan)
1070 /* Cast this value to catch negative channel numbers (>= -19) */
1071 channel = (int)ieee;
1074 * Map 2GHz IEEE channel to 5GHz Atheros channel
1076 if (channel <= 13) {
1077 athchan->a2_athchan = 115 + channel;
1078 athchan->a2_flags = 0x46;
1079 } else if (channel == 14) {
1080 athchan->a2_athchan = 124;
1081 athchan->a2_flags = 0x44;
1082 } else if (channel >= 15 && channel <= 26) {
1083 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1084 athchan->a2_flags = 0x46;
1092 * Set channel on 5111
1094 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1095 struct ieee80211_channel *channel)
1097 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1098 unsigned int ath5k_channel =
1099 ieee80211_frequency_to_channel(channel->center_freq);
1100 u32 data0, data1, clock;
1104 * Set the channel on the RF5111 radio
1108 if (channel->hw_value & CHANNEL_2GHZ) {
1109 /* Map 2GHz channel to 5GHz Atheros channel ID */
1110 ret = ath5k_hw_rf5111_chan2athchan(
1111 ieee80211_frequency_to_channel(channel->center_freq),
1112 &ath5k_channel_2ghz);
1116 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1117 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1121 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1123 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1124 (clock << 1) | (1 << 10) | 1;
1127 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1128 << 2) | (clock << 1) | (1 << 10) | 1;
1131 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1133 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1134 AR5K_RF_BUFFER_CONTROL_3);
1140 * Set channel on 5112 and newer
1142 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1143 struct ieee80211_channel *channel)
1145 u32 data, data0, data1, data2;
1148 data = data0 = data1 = data2 = 0;
1149 c = channel->center_freq;
1152 if (!((c - 2224) % 5)) {
1153 data0 = ((2 * (c - 704)) - 3040) / 10;
1155 } else if (!((c - 2192) % 5)) {
1156 data0 = ((2 * (c - 672)) - 3040) / 10;
1161 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1162 } else if ((c % 5) != 2 || c > 5435) {
1163 if (!(c % 20) && c >= 5120) {
1164 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1165 data2 = ath5k_hw_bitswap(3, 2);
1166 } else if (!(c % 10)) {
1167 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1168 data2 = ath5k_hw_bitswap(2, 2);
1169 } else if (!(c % 5)) {
1170 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1171 data2 = ath5k_hw_bitswap(1, 2);
1175 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1176 data2 = ath5k_hw_bitswap(0, 2);
1179 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1181 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1182 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1188 * Set the channel on the RF2425
1190 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1191 struct ieee80211_channel *channel)
1193 u32 data, data0, data2;
1196 data = data0 = data2 = 0;
1197 c = channel->center_freq;
1200 data0 = ath5k_hw_bitswap((c - 2272), 8);
1203 } else if ((c % 5) != 2 || c > 5435) {
1204 if (!(c % 20) && c < 5120)
1205 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1207 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1209 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1212 data2 = ath5k_hw_bitswap(1, 2);
1214 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1215 data2 = ath5k_hw_bitswap(0, 2);
1218 data = (data0 << 4) | data2 << 2 | 0x1001;
1220 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1221 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1227 * Set a channel on the radio chip
1229 static int ath5k_hw_channel(struct ath5k_hw *ah,
1230 struct ieee80211_channel *channel)
1234 * Check bounds supported by the PHY (we don't care about regultory
1235 * restrictions at this point). Note: hw_value already has the band
1236 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1237 * of the band by that */
1238 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1239 ATH5K_ERR(ah->ah_sc,
1240 "channel frequency (%u MHz) out of supported "
1242 channel->center_freq);
1247 * Set the channel and wait
1249 switch (ah->ah_radio) {
1251 ret = ath5k_hw_rf5110_channel(ah, channel);
1254 ret = ath5k_hw_rf5111_channel(ah, channel);
1257 ret = ath5k_hw_rf2425_channel(ah, channel);
1260 ret = ath5k_hw_rf5112_channel(ah, channel);
1267 /* Set JAPAN setting for channel 14 */
1268 if (channel->center_freq == 2484) {
1269 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1270 AR5K_PHY_CCKTXCTL_JAPAN);
1272 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1273 AR5K_PHY_CCKTXCTL_WORLD);
1276 ah->ah_current_channel = channel;
1285 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1289 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1290 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
1293 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1297 ah->ah_nfcal_hist.index = 0;
1298 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1299 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1302 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1304 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1305 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1306 hist->nfval[hist->index] = noise_floor;
1309 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1311 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1315 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1316 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1317 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1318 if (sort[j] > sort[j-1]) {
1320 sort[j] = sort[j-1];
1325 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1326 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1327 "cal %d:%d\n", i, sort[i]);
1329 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1333 * When we tell the hardware to perform a noise floor calibration
1334 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1335 * sample-and-hold the minimum noise level seen at the antennas.
1336 * This value is then stored in a ring buffer of recently measured
1337 * noise floor values so we have a moving window of the last few
1340 * The median of the values in the history is then loaded into the
1341 * hardware for its own use for RSSI and CCA measurements.
1343 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1345 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1350 /* keep last value if calibration hasn't completed */
1351 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1352 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1353 "NF did not complete in calibration window\n");
1358 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
1360 /* completed NF calibration, test threshold */
1361 nf = ath5k_hw_read_measured_noise_floor(ah);
1362 threshold = ee->ee_noise_floor_thr[ee_mode];
1364 if (nf > threshold) {
1365 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1366 "noise floor failure detected; "
1367 "read %d, threshold %d\n",
1370 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1373 ath5k_hw_update_nfcal_hist(ah, nf);
1374 nf = ath5k_hw_get_median_noise_floor(ah);
1376 /* load noise floor (in .5 dBm) so the hardware will use it */
1377 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1378 val |= (nf * 2) & AR5K_PHY_NF_M;
1379 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1381 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1382 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1384 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1388 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1389 * so that we're not capped by the median we just loaded.
1390 * This will be used as the initial value for the next noise
1391 * floor calibration.
1393 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1394 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1395 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1396 AR5K_PHY_AGCCTL_NF_EN |
1397 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1398 AR5K_PHY_AGCCTL_NF);
1400 ah->ah_noise_floor = nf;
1402 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1403 "noise floor calibrated: %d\n", nf);
1407 * Perform a PHY calibration on RF5110
1408 * -Fix BPSK/QAM Constellation (I/Q correction)
1410 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1411 struct ieee80211_channel *channel)
1413 u32 phy_sig, phy_agc, phy_sat, beacon;
1417 * Disable beacons and RX/TX queues, wait
1419 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1420 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1421 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1422 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1427 * Set the channel (with AGC turned off)
1429 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1431 ret = ath5k_hw_channel(ah, channel);
1434 * Activate PHY and wait
1436 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1439 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1445 * Calibrate the radio chip
1448 /* Remember normal state */
1449 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1450 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1451 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1453 /* Update radio registers */
1454 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1455 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1457 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1458 AR5K_PHY_AGCCOARSE_LO)) |
1459 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1460 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1462 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1463 AR5K_PHY_ADCSAT_THR)) |
1464 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1465 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1469 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1471 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1472 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1477 * Enable calibration and wait until completion
1479 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1481 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1482 AR5K_PHY_AGCCTL_CAL, 0, false);
1484 /* Reset to normal state */
1485 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1486 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1487 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1490 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1491 channel->center_freq);
1496 * Re-enable RX/TX and beacons
1498 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1499 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1500 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1506 * Perform I/Q calibration on RF5111/5112 and newer chips
1509 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1512 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1515 if (!ah->ah_calibration ||
1516 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1519 /* Calibration has finished, get the results and re-run */
1520 /* work around empty results which can apparently happen on 5212 */
1521 for (i = 0; i <= 10; i++) {
1522 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1523 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1524 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1525 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1526 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1531 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1533 if (ah->ah_version == AR5K_AR5211)
1534 q_coffd = q_pwr >> 6;
1536 q_coffd = q_pwr >> 7;
1538 /* protect against divide by 0 and loss of sign bits */
1539 if (i_coffd == 0 || q_coffd < 2)
1542 i_coff = (-iq_corr) / i_coffd;
1543 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1545 if (ah->ah_version == AR5K_AR5211)
1546 q_coff = (i_pwr / q_coffd) - 64;
1548 q_coff = (i_pwr / q_coffd) - 128;
1549 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1551 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1552 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1553 i_coff, q_coff, i_coffd, q_coffd);
1555 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1556 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1557 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1558 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1560 /* Re-enable calibration -if we don't we'll commit
1561 * the same values again and again */
1562 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1563 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1564 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1570 * Perform a PHY calibration
1572 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1573 struct ieee80211_channel *channel)
1577 if (ah->ah_radio == AR5K_RF5110)
1578 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1580 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1581 ath5k_hw_request_rfgain_probe(ah);
1588 /***************************\
1589 * Spur mitigation functions *
1590 \***************************/
1593 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1594 struct ieee80211_channel *channel)
1596 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1597 u32 mag_mask[4] = {0, 0, 0, 0};
1598 u32 pilot_mask[2] = {0, 0};
1599 /* Note: fbin values are scaled up by 2 */
1600 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1601 s32 spur_delta_phase, spur_freq_sigma_delta;
1602 s32 spur_offset, num_symbols_x16;
1603 u8 num_symbol_offsets, i, freq_band;
1605 /* Convert current frequency to fbin value (the same way channels
1606 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1607 * up by 2 so we can compare it later */
1608 if (channel->hw_value & CHANNEL_2GHZ) {
1609 chan_fbin = (channel->center_freq - 2300) * 10;
1610 freq_band = AR5K_EEPROM_BAND_2GHZ;
1612 chan_fbin = (channel->center_freq - 4900) * 10;
1613 freq_band = AR5K_EEPROM_BAND_5GHZ;
1616 /* Check if any spur_chan_fbin from EEPROM is
1617 * within our current channel's spur detection range */
1618 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1619 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1620 /* XXX: Half/Quarter channels ?*/
1621 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
1622 spur_detection_window *= 2;
1624 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1625 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1627 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1628 * so it's zero if we got nothing from EEPROM */
1629 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1630 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1634 if ((chan_fbin - spur_detection_window <=
1635 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1636 (chan_fbin + spur_detection_window >=
1637 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1638 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1643 /* We need to enable spur filter for this channel */
1644 if (spur_chan_fbin) {
1645 spur_offset = spur_chan_fbin - chan_fbin;
1648 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1649 * spur_delta_phase -> spur_offset / chip_freq << 11
1650 * Note: Both values have 100Hz resolution
1652 switch (ah->ah_bwmode) {
1653 case AR5K_BWMODE_40MHZ:
1654 /* Both sample_freq and chip_freq are 80MHz */
1655 spur_delta_phase = (spur_offset << 16) / 25;
1656 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1657 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
1659 case AR5K_BWMODE_10MHZ:
1660 /* Both sample_freq and chip_freq are 20MHz (?) */
1661 spur_delta_phase = (spur_offset << 18) / 25;
1662 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1663 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
1664 case AR5K_BWMODE_5MHZ:
1665 /* Both sample_freq and chip_freq are 10MHz (?) */
1666 spur_delta_phase = (spur_offset << 19) / 25;
1667 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1668 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
1670 if (channel->hw_value == CHANNEL_A) {
1671 /* Both sample_freq and chip_freq are 40MHz */
1672 spur_delta_phase = (spur_offset << 17) / 25;
1673 spur_freq_sigma_delta =
1674 (spur_delta_phase >> 10);
1676 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1678 /* sample_freq -> 40MHz chip_freq -> 44MHz
1679 * (for b compatibility) */
1680 spur_delta_phase = (spur_offset << 17) / 25;
1681 spur_freq_sigma_delta =
1682 (spur_offset << 8) / 55;
1684 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1689 /* Calculate pilot and magnitude masks */
1691 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1692 * and divide by symbol_width to find how many symbols we have
1693 * Note: number of symbols is scaled up by 16 */
1694 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1696 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1697 if (!(num_symbols_x16 & 0xF))
1699 num_symbol_offsets = 3;
1702 num_symbol_offsets = 4;
1704 for (i = 0; i < num_symbol_offsets; i++) {
1706 /* Calculate pilot mask */
1708 (num_symbols_x16 / 16) + i + 25;
1710 /* Pilot magnitude mask seems to be a way to
1711 * declare the boundaries for our detection
1712 * window or something, it's 2 for the middle
1713 * value(s) where the symbol is expected to be
1714 * and 1 on the boundary values */
1716 (i == 0 || i == (num_symbol_offsets - 1))
1719 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1720 if (curr_sym_off <= 25)
1721 pilot_mask[0] |= 1 << curr_sym_off;
1722 else if (curr_sym_off >= 27)
1723 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1724 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1725 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1727 /* Calculate magnitude mask (for viterbi decoder) */
1728 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1730 plt_mag_map << (curr_sym_off + 1) * 2;
1731 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1733 plt_mag_map << (curr_sym_off - 15) * 2;
1734 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1736 plt_mag_map << (curr_sym_off - 31) * 2;
1737 else if (curr_sym_off >= 47 && curr_sym_off <= 53)
1739 plt_mag_map << (curr_sym_off - 47) * 2;
1743 /* Write settings on hw to enable spur filter */
1744 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1745 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1746 /* XXX: Self correlator also ? */
1747 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1748 AR5K_PHY_IQ_PILOT_MASK_EN |
1749 AR5K_PHY_IQ_CHAN_MASK_EN |
1750 AR5K_PHY_IQ_SPUR_FILT_EN);
1752 /* Set delta phase and freq sigma delta */
1753 ath5k_hw_reg_write(ah,
1754 AR5K_REG_SM(spur_delta_phase,
1755 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1756 AR5K_REG_SM(spur_freq_sigma_delta,
1757 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1758 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1759 AR5K_PHY_TIMING_11);
1761 /* Write pilot masks */
1762 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1763 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1764 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1767 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1768 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1769 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1772 /* Write magnitude masks */
1773 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1774 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1775 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1776 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1777 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1780 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1781 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1782 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1783 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1784 AR5K_PHY_BIN_MASK2_4_MASK_4,
1787 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1788 AR5K_PHY_IQ_SPUR_FILT_EN) {
1789 /* Clean up spur mitigation settings and disable fliter */
1790 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1791 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1792 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1793 AR5K_PHY_IQ_PILOT_MASK_EN |
1794 AR5K_PHY_IQ_CHAN_MASK_EN |
1795 AR5K_PHY_IQ_SPUR_FILT_EN);
1796 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1798 /* Clear pilot masks */
1799 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1800 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1801 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1804 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1805 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1806 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1809 /* Clear magnitude masks */
1810 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1811 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1812 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1813 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1814 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1817 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1818 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1819 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1820 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1821 AR5K_PHY_BIN_MASK2_4_MASK_4,
1831 static void /*TODO:Boundary check*/
1832 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1834 if (ah->ah_version != AR5K_AR5210)
1835 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1839 * Enable/disable fast rx antenna diversity
1842 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1845 case AR5K_EEPROM_MODE_11G:
1846 /* XXX: This is set to
1847 * disabled on initvals !!! */
1848 case AR5K_EEPROM_MODE_11A:
1850 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1851 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1853 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1854 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1856 case AR5K_EEPROM_MODE_11B:
1857 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1858 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1865 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1866 AR5K_PHY_RESTART_DIV_GC, 4);
1868 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1869 AR5K_PHY_FAST_ANT_DIV_EN);
1871 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1872 AR5K_PHY_RESTART_DIV_GC, 0);
1874 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1875 AR5K_PHY_FAST_ANT_DIV_EN);
1880 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1885 * In case a fixed antenna was set as default
1886 * use the same switch table twice.
1888 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1889 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1890 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1891 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1893 ant0 = AR5K_ANT_SWTABLE_A;
1894 ant1 = AR5K_ANT_SWTABLE_B;
1897 /* Set antenna idle switch table */
1898 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1899 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1900 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1901 AR5K_PHY_ANT_CTL_TXRX_EN));
1903 /* Set antenna switch tables */
1904 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1905 AR5K_PHY_ANT_SWITCH_TABLE_0);
1906 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1907 AR5K_PHY_ANT_SWITCH_TABLE_1);
1911 * Set antenna operating mode
1914 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1916 struct ieee80211_channel *channel = ah->ah_current_channel;
1917 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1918 bool use_def_for_sg;
1919 u8 def_ant, tx_ant, ee_mode;
1922 /* if channel is not initialized yet we can't set the antennas
1923 * so just store the mode. it will be set on the next reset */
1924 if (channel == NULL) {
1925 ah->ah_ant_mode = ant_mode;
1929 def_ant = ah->ah_def_ant;
1931 ee_mode = ath5k_eeprom_mode_from_channel(channel);
1933 ATH5K_ERR(ah->ah_sc,
1934 "invalid channel: %d\n", channel->center_freq);
1939 case AR5K_ANTMODE_DEFAULT:
1941 use_def_for_tx = false;
1942 update_def_on_tx = false;
1943 use_def_for_rts = false;
1944 use_def_for_sg = false;
1947 case AR5K_ANTMODE_FIXED_A:
1950 use_def_for_tx = true;
1951 update_def_on_tx = false;
1952 use_def_for_rts = true;
1953 use_def_for_sg = true;
1956 case AR5K_ANTMODE_FIXED_B:
1959 use_def_for_tx = true;
1960 update_def_on_tx = false;
1961 use_def_for_rts = true;
1962 use_def_for_sg = true;
1965 case AR5K_ANTMODE_SINGLE_AP:
1966 def_ant = 1; /* updated on tx */
1968 use_def_for_tx = true;
1969 update_def_on_tx = true;
1970 use_def_for_rts = true;
1971 use_def_for_sg = true;
1974 case AR5K_ANTMODE_SECTOR_AP:
1975 tx_ant = 1; /* variable */
1976 use_def_for_tx = false;
1977 update_def_on_tx = false;
1978 use_def_for_rts = true;
1979 use_def_for_sg = false;
1982 case AR5K_ANTMODE_SECTOR_STA:
1983 tx_ant = 1; /* variable */
1984 use_def_for_tx = true;
1985 update_def_on_tx = false;
1986 use_def_for_rts = true;
1987 use_def_for_sg = false;
1990 case AR5K_ANTMODE_DEBUG:
1993 use_def_for_tx = false;
1994 update_def_on_tx = false;
1995 use_def_for_rts = false;
1996 use_def_for_sg = false;
2003 ah->ah_tx_ant = tx_ant;
2004 ah->ah_ant_mode = ant_mode;
2005 ah->ah_def_ant = def_ant;
2007 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
2008 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
2009 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
2010 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
2012 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
2015 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
2017 ath5k_hw_set_antenna_switch(ah, ee_mode);
2018 /* Note: set diversity before default antenna
2019 * because it won't work correctly */
2020 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
2021 ath5k_hw_set_def_antenna(ah, def_ant);
2034 * Do linear interpolation between two given (x, y) points
2037 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2038 s16 y_left, s16 y_right)
2042 /* Avoid divide by zero and skip interpolation
2043 * if we have the same point */
2044 if ((x_left == x_right) || (y_left == y_right))
2048 * Since we use ints and not fps, we need to scale up in
2049 * order to get a sane ratio value (or else we 'll eg. get
2050 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2051 * to have some accuracy both for 0.5 and 0.25 steps.
2053 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
2055 /* Now scale down to be in range */
2056 result = y_left + (ratio * (target - x_left) / 100);
2062 * Find vertical boundary (min pwr) for the linear PCDAC curve.
2064 * Since we have the top of the curve and we draw the line below
2065 * until we reach 1 (1 pcdac step) we need to know which point
2066 * (x value) that is so that we don't go below y axis and have negative
2067 * pcdac values when creating the curve, or fill the table with zeroes.
2070 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
2071 const s16 *pwrL, const s16 *pwrR)
2074 s16 min_pwrL, min_pwrR;
2077 /* Some vendors write the same pcdac value twice !!! */
2078 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
2079 return max(pwrL[0], pwrR[0]);
2081 if (pwrL[0] == pwrL[1])
2087 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2089 stepL[0], stepL[1]);
2095 if (pwrR[0] == pwrR[1])
2101 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2103 stepR[0], stepR[1]);
2109 /* Keep the right boundary so that it works for both curves */
2110 return max(min_pwrL, min_pwrR);
2114 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2115 * Power to PCDAC curve.
2117 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2118 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2119 * PCDAC/PDADC step for each curve is 64 but we can write more than
2120 * one curves on hw so we can go up to 128 (which is the max step we
2121 * can write on the final table).
2123 * We write y values (PCDAC/PDADC steps) on hw.
2126 ath5k_create_power_curve(s16 pmin, s16 pmax,
2127 const s16 *pwr, const u8 *vpd,
2129 u8 *vpd_table, u8 type)
2131 u8 idx[2] = { 0, 1 };
2138 /* We want the whole line, so adjust boundaries
2139 * to cover the entire power range. Note that
2140 * power values are already 0.25dB so no need
2141 * to multiply pwr_i by 2 */
2142 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2148 /* Find surrounding turning points (TPs)
2149 * and interpolate between them */
2150 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2151 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2153 /* We passed the right TP, move to the next set of TPs
2154 * if we pass the last TP, extrapolate above using the last
2155 * two TPs for ratio */
2156 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2161 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2162 pwr[idx[0]], pwr[idx[1]],
2163 vpd[idx[0]], vpd[idx[1]]);
2165 /* Increase by 0.5dB
2166 * (0.25 dB units) */
2172 * Get the surrounding per-channel power calibration piers
2173 * for a given frequency so that we can interpolate between
2174 * them and come up with an apropriate dataset for our current
2178 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2179 struct ieee80211_channel *channel,
2180 struct ath5k_chan_pcal_info **pcinfo_l,
2181 struct ath5k_chan_pcal_info **pcinfo_r)
2183 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2184 struct ath5k_chan_pcal_info *pcinfo;
2187 u32 target = channel->center_freq;
2192 if (!(channel->hw_value & CHANNEL_OFDM)) {
2193 pcinfo = ee->ee_pwr_cal_b;
2194 mode = AR5K_EEPROM_MODE_11B;
2195 } else if (channel->hw_value & CHANNEL_2GHZ) {
2196 pcinfo = ee->ee_pwr_cal_g;
2197 mode = AR5K_EEPROM_MODE_11G;
2199 pcinfo = ee->ee_pwr_cal_a;
2200 mode = AR5K_EEPROM_MODE_11A;
2202 max = ee->ee_n_piers[mode] - 1;
2204 /* Frequency is below our calibrated
2205 * range. Use the lowest power curve
2207 if (target < pcinfo[0].freq) {
2212 /* Frequency is above our calibrated
2213 * range. Use the highest power curve
2215 if (target > pcinfo[max].freq) {
2216 idx_l = idx_r = max;
2220 /* Frequency is inside our calibrated
2221 * channel range. Pick the surrounding
2222 * calibration piers so that we can
2224 for (i = 0; i <= max; i++) {
2226 /* Frequency matches one of our calibration
2227 * piers, no need to interpolate, just use
2228 * that calibration pier */
2229 if (pcinfo[i].freq == target) {
2234 /* We found a calibration pier that's above
2235 * frequency, use this pier and the previous
2236 * one to interpolate */
2237 if (target < pcinfo[i].freq) {
2245 *pcinfo_l = &pcinfo[idx_l];
2246 *pcinfo_r = &pcinfo[idx_r];
2250 * Get the surrounding per-rate power calibration data
2251 * for a given frequency and interpolate between power
2252 * values to set max target power supported by hw for
2256 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2257 struct ieee80211_channel *channel,
2258 struct ath5k_rate_pcal_info *rates)
2260 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2261 struct ath5k_rate_pcal_info *rpinfo;
2264 u32 target = channel->center_freq;
2269 if (!(channel->hw_value & CHANNEL_OFDM)) {
2270 rpinfo = ee->ee_rate_tpwr_b;
2271 mode = AR5K_EEPROM_MODE_11B;
2272 } else if (channel->hw_value & CHANNEL_2GHZ) {
2273 rpinfo = ee->ee_rate_tpwr_g;
2274 mode = AR5K_EEPROM_MODE_11G;
2276 rpinfo = ee->ee_rate_tpwr_a;
2277 mode = AR5K_EEPROM_MODE_11A;
2279 max = ee->ee_rate_target_pwr_num[mode] - 1;
2281 /* Get the surrounding calibration
2282 * piers - same as above */
2283 if (target < rpinfo[0].freq) {
2288 if (target > rpinfo[max].freq) {
2289 idx_l = idx_r = max;
2293 for (i = 0; i <= max; i++) {
2295 if (rpinfo[i].freq == target) {
2300 if (target < rpinfo[i].freq) {
2308 /* Now interpolate power value, based on the frequency */
2309 rates->freq = target;
2311 rates->target_power_6to24 =
2312 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2314 rpinfo[idx_l].target_power_6to24,
2315 rpinfo[idx_r].target_power_6to24);
2317 rates->target_power_36 =
2318 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2320 rpinfo[idx_l].target_power_36,
2321 rpinfo[idx_r].target_power_36);
2323 rates->target_power_48 =
2324 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2326 rpinfo[idx_l].target_power_48,
2327 rpinfo[idx_r].target_power_48);
2329 rates->target_power_54 =
2330 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2332 rpinfo[idx_l].target_power_54,
2333 rpinfo[idx_r].target_power_54);
2337 * Get the max edge power for this channel if
2338 * we have such data from EEPROM's Conformance Test
2339 * Limits (CTL), and limit max power if needed.
2342 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2343 struct ieee80211_channel *channel)
2345 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2346 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2347 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2348 u8 *ctl_val = ee->ee_ctl;
2349 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2354 u32 target = channel->center_freq;
2356 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2358 switch (channel->hw_value & CHANNEL_MODES) {
2360 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2361 ctl_mode |= AR5K_CTL_TURBO;
2363 ctl_mode |= AR5K_CTL_11A;
2366 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2367 ctl_mode |= AR5K_CTL_TURBOG;
2369 ctl_mode |= AR5K_CTL_11G;
2372 ctl_mode |= AR5K_CTL_11B;
2380 for (i = 0; i < ee->ee_ctls; i++) {
2381 if (ctl_val[i] == ctl_mode) {
2387 /* If we have a CTL dataset available grab it and find the
2388 * edge power for our frequency */
2389 if (ctl_idx == 0xFF)
2392 /* Edge powers are sorted by frequency from lower
2393 * to higher. Each CTL corresponds to 8 edge power
2395 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2397 /* Don't do boundaries check because we
2398 * might have more that one bands defined
2401 /* Get the edge power that's closer to our
2403 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2405 if (target <= rep[rep_idx].freq)
2406 edge_pwr = (s16) rep[rep_idx].edge;
2410 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2415 * Power to PCDAC table functions
2419 * Fill Power to PCDAC table on RF5111
2421 * No further processing is needed for RF5111, the only thing we have to
2422 * do is fill the values below and above calibration range since eeprom data
2423 * may not cover the entire PCDAC table.
2426 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2429 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2430 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2431 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2432 s16 min_pwr, max_pwr;
2434 /* Get table boundaries */
2435 min_pwr = table_min[0];
2436 pcdac_0 = pcdac_tmp[0];
2438 max_pwr = table_max[0];
2439 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2441 /* Extrapolate below minimum using pcdac_0 */
2443 for (i = 0; i < min_pwr; i++)
2444 pcdac_out[pcdac_i++] = pcdac_0;
2446 /* Copy values from pcdac_tmp */
2448 for (i = 0 ; pwr_idx <= max_pwr &&
2449 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2450 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2454 /* Extrapolate above maximum */
2455 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2456 pcdac_out[pcdac_i++] = pcdac_n;
2461 * Combine available XPD Curves and fill Linear Power to PCDAC table
2464 * RFX112 can have up to 2 curves (one for low txpower range and one for
2465 * higher txpower range). We need to put them both on pcdac_out and place
2466 * them in the correct location. In case we only have one curve available
2467 * just fit it on pcdac_out (it's supposed to cover the entire range of
2468 * available pwr levels since it's always the higher power curve). Extrapolate
2469 * below and above final table if needed.
2472 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2473 s16 *table_max, u8 pdcurves)
2475 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2482 s16 mid_pwr_idx = 0;
2483 /* Edge flag turs on the 7nth bit on the PCDAC
2484 * to delcare the higher power curve (force values
2485 * to be greater than 64). If we only have one curve
2486 * we don't need to set this, if we have 2 curves and
2487 * fill the table backwards this can also be used to
2488 * switch from higher power curve to lower power curve */
2492 /* When we have only one curve available
2493 * that's the higher power curve. If we have
2494 * two curves the first is the high power curve
2495 * and the next is the low power curve. */
2497 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2498 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2499 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2500 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2502 /* If table size goes beyond 31.5dB, keep the
2503 * upper 31.5dB range when setting tx power.
2504 * Note: 126 = 31.5 dB in quarter dB steps */
2505 if (table_max[0] - table_min[1] > 126)
2506 min_pwr_idx = table_max[0] - 126;
2508 min_pwr_idx = table_min[1];
2510 /* Since we fill table backwards
2511 * start from high power curve */
2512 pcdac_tmp = pcdac_high_pwr;
2516 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2517 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2518 min_pwr_idx = table_min[0];
2519 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2520 pcdac_tmp = pcdac_high_pwr;
2524 /* This is used when setting tx power*/
2525 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2527 /* Fill Power to PCDAC table backwards */
2529 for (i = 63; i >= 0; i--) {
2530 /* Entering lower power range, reset
2531 * edge flag and set pcdac_tmp to lower
2533 if (edge_flag == 0x40 &&
2534 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2536 pcdac_tmp = pcdac_low_pwr;
2537 pwr = mid_pwr_idx/2;
2540 /* Don't go below 1, extrapolate below if we have
2541 * already swithced to the lower power curve -or
2542 * we only have one curve and edge_flag is zero
2544 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2546 pcdac_out[i] = pcdac_out[i + 1];
2552 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2554 /* Extrapolate above if pcdac is greater than
2555 * 126 -this can happen because we OR pcdac_out
2556 * value with edge_flag on high power curve */
2557 if (pcdac_out[i] > 126)
2560 /* Decrease by a 0.5dB step */
2565 /* Write PCDAC values on hw */
2567 ath5k_write_pcdac_table(struct ath5k_hw *ah)
2569 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2573 * Write TX power values
2575 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2576 ath5k_hw_reg_write(ah,
2577 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2578 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2579 AR5K_PHY_PCDAC_TXPOWER(i));
2585 * Power to PDADC table functions
2589 * Set the gain boundaries and create final Power to PDADC table
2591 * We can have up to 4 pd curves, we need to do a simmilar process
2592 * as we do for RF5112. This time we don't have an edge_flag but we
2593 * set the gain boundaries on a separate register.
2596 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2597 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2599 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2600 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2603 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2606 /* Note: Register value is initialized on initvals
2607 * there is no feedback from hw.
2608 * XXX: What about pd_gain_overlap from EEPROM ? */
2609 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2610 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2612 /* Create final PDADC table */
2613 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2614 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2616 if (pdg == pdcurves - 1)
2617 /* 2 dB boundary stretch for last
2618 * (higher power) curve */
2619 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2621 /* Set gain boundary in the middle
2622 * between this curve and the next one */
2623 gain_boundaries[pdg] =
2624 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2626 /* Sanity check in case our 2 db stretch got out of
2628 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2629 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2631 /* For the first curve (lower power)
2632 * start from 0 dB */
2636 /* For the other curves use the gain overlap */
2637 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2640 /* Force each power step to be at least 0.5 dB */
2641 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2642 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2646 /* If pdadc_0 is negative, we need to extrapolate
2647 * below this pdgain by a number of pwr_steps */
2648 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2649 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2650 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2654 /* Set last pwr level, using gain boundaries */
2655 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2656 /* Limit it to be inside pwr range */
2657 table_size = pwr_max[pdg] - pwr_min[pdg];
2658 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2660 /* Fill pdadc_out table */
2661 while (pdadc_0 < max_idx && pdadc_i < 128)
2662 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2664 /* Need to extrapolate above this pdgain? */
2665 if (pdadc_n <= max_idx)
2668 /* Force each power step to be at least 0.5 dB */
2669 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2670 pwr_step = pdadc_tmp[table_size - 1] -
2671 pdadc_tmp[table_size - 2];
2675 /* Extrapolate above */
2676 while ((pdadc_0 < (s16) pdadc_n) &&
2677 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2678 s16 tmp = pdadc_tmp[table_size - 1] +
2679 (pdadc_0 - max_idx) * pwr_step;
2680 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2685 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2686 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2690 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2691 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2695 /* Set gain boundaries */
2696 ath5k_hw_reg_write(ah,
2697 AR5K_REG_SM(pd_gain_overlap,
2698 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2699 AR5K_REG_SM(gain_boundaries[0],
2700 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2701 AR5K_REG_SM(gain_boundaries[1],
2702 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2703 AR5K_REG_SM(gain_boundaries[2],
2704 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2705 AR5K_REG_SM(gain_boundaries[3],
2706 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2709 /* Used for setting rate power table */
2710 ah->ah_txpower.txp_min_idx = pwr_min[0];
2714 /* Write PDADC values on hw */
2716 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
2718 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2719 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2720 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
2721 u8 pdcurves = ee->ee_pd_gains[ee_mode];
2725 /* Select the right pdgain curves */
2727 /* Clear current settings */
2728 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2729 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2730 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2731 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2732 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2735 * Use pd_gains curve from eeprom
2737 * This overrides the default setting from initvals
2738 * in case some vendors (e.g. Zcomax) don't use the default
2739 * curves. If we don't honor their settings we 'll get a
2740 * 5dB (1 * gain overlap ?) drop.
2742 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2746 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2749 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2752 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2755 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2758 * Write TX power values
2760 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2761 ath5k_hw_reg_write(ah,
2762 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2763 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2764 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2765 ((pdadc_out[4*i + 3] & 0xff) << 24),
2766 AR5K_PHY_PDADC_TXPOWER(i));
2772 * Common code for PCDAC/PDADC tables
2776 * This is the main function that uses all of the above
2777 * to set PCDAC/PDADC table on hw for the current channel.
2778 * This table is used for tx power calibration on the basband,
2779 * without it we get weird tx power levels and in some cases
2780 * distorted spectral mask
2783 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2784 struct ieee80211_channel *channel,
2785 u8 ee_mode, u8 type)
2787 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2788 struct ath5k_chan_pcal_info *pcinfo_L;
2789 struct ath5k_chan_pcal_info *pcinfo_R;
2790 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2791 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2792 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2793 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2796 u32 target = channel->center_freq;
2799 /* Get surounding freq piers for this channel */
2800 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2804 /* Loop over pd gain curves on
2805 * surounding freq piers by index */
2806 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2808 /* Fill curves in reverse order
2809 * from lower power (max gain)
2810 * to higher power. Use curve -> idx
2811 * backmapping we did on eeprom init */
2812 u8 idx = pdg_curve_to_idx[pdg];
2814 /* Grab the needed curves by index */
2815 pdg_L = &pcinfo_L->pd_curves[idx];
2816 pdg_R = &pcinfo_R->pd_curves[idx];
2818 /* Initialize the temp tables */
2819 tmpL = ah->ah_txpower.tmpL[pdg];
2820 tmpR = ah->ah_txpower.tmpR[pdg];
2822 /* Set curve's x boundaries and create
2823 * curves so that they cover the same
2824 * range (if we don't do that one table
2825 * will have values on some range and the
2826 * other one won't have any so interpolation
2828 table_min[pdg] = min(pdg_L->pd_pwr[0],
2829 pdg_R->pd_pwr[0]) / 2;
2831 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2832 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2834 /* Now create the curves on surrounding channels
2835 * and interpolate if needed to get the final
2836 * curve for this gain on this channel */
2838 case AR5K_PWRTABLE_LINEAR_PCDAC:
2839 /* Override min/max so that we don't loose
2840 * accuracy (don't divide by 2) */
2841 table_min[pdg] = min(pdg_L->pd_pwr[0],
2845 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2846 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2848 /* Override minimum so that we don't get
2849 * out of bounds while extrapolating
2850 * below. Don't do this when we have 2
2851 * curves and we are on the high power curve
2852 * because table_min is ok in this case */
2853 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2856 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2861 /* Don't go too low because we will
2862 * miss the upper part of the curve.
2863 * Note: 126 = 31.5dB (max power supported)
2864 * in 0.25dB units */
2865 if (table_max[pdg] - table_min[pdg] > 126)
2866 table_min[pdg] = table_max[pdg] - 126;
2870 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2871 case AR5K_PWRTABLE_PWR_TO_PDADC:
2873 ath5k_create_power_curve(table_min[pdg],
2877 pdg_L->pd_points, tmpL, type);
2879 /* We are in a calibration
2880 * pier, no need to interpolate
2881 * between freq piers */
2882 if (pcinfo_L == pcinfo_R)
2885 ath5k_create_power_curve(table_min[pdg],
2889 pdg_R->pd_points, tmpR, type);
2895 /* Interpolate between curves
2896 * of surounding freq piers to
2897 * get the final curve for this
2898 * pd gain. Re-use tmpL for interpolation
2900 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2901 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2902 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2903 (s16) pcinfo_L->freq,
2904 (s16) pcinfo_R->freq,
2910 /* Now we have a set of curves for this
2911 * channel on tmpL (x range is table_max - table_min
2912 * and y values are tmpL[pdg][]) sorted in the same
2913 * order as EEPROM (because we've used the backmapping).
2914 * So for RF5112 it's from higher power to lower power
2915 * and for RF2413 it's from lower power to higher power.
2916 * For RF5111 we only have one curve. */
2918 /* Fill min and max power levels for this
2919 * channel by interpolating the values on
2920 * surounding channels to complete the dataset */
2921 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2922 (s16) pcinfo_L->freq,
2923 (s16) pcinfo_R->freq,
2924 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2926 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2927 (s16) pcinfo_L->freq,
2928 (s16) pcinfo_R->freq,
2929 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2931 /* Fill PCDAC/PDADC table */
2933 case AR5K_PWRTABLE_LINEAR_PCDAC:
2934 /* For RF5112 we can have one or two curves
2935 * and each curve covers a certain power lvl
2936 * range so we need to do some more processing */
2937 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2938 ee->ee_pd_gains[ee_mode]);
2940 /* Set txp.offset so that we can
2941 * match max power value with max
2943 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2945 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2946 /* We are done for RF5111 since it has only
2947 * one curve, just fit the curve on the table */
2948 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2950 /* No rate powertable adjustment for RF5111 */
2951 ah->ah_txpower.txp_min_idx = 0;
2952 ah->ah_txpower.txp_offset = 0;
2954 case AR5K_PWRTABLE_PWR_TO_PDADC:
2955 /* Set PDADC boundaries and fill
2956 * final PDADC table */
2957 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2958 ee->ee_pd_gains[ee_mode]);
2960 /* Set txp.offset, note that table_min
2961 * can be negative */
2962 ah->ah_txpower.txp_offset = table_min[0];
2968 ah->ah_txpower.txp_setup = true;
2973 /* Write power table for current channel to hw */
2975 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
2977 if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
2978 ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
2980 ath5k_write_pcdac_table(ah);
2984 * Per-rate tx power setting
2986 * This is the code that sets the desired tx power (below
2987 * maximum) on hw for each rate (we also have TPC that sets
2988 * power per packet). We do that by providing an index on the
2989 * PCDAC/PDADC table we set up.
2993 * Set rate power table
2995 * For now we only limit txpower based on maximum tx power
2996 * supported by hw (what's inside rate_info). We need to limit
2997 * this even more, based on regulatory domain etc.
2999 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
3000 * and is indexed as follows:
3001 * rates[0] - rates[7] -> OFDM rates
3002 * rates[8] - rates[14] -> CCK rates
3003 * rates[15] -> XR rates (they all have the same power)
3006 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
3007 struct ath5k_rate_pcal_info *rate_info,
3013 /* max_pwr is power level we got from driver/user in 0.5dB
3014 * units, switch to 0.25dB units so we can compare */
3016 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
3018 /* apply rate limits */
3019 rates = ah->ah_txpower.txp_rates_power_table;
3021 /* OFDM rates 6 to 24Mb/s */
3022 for (i = 0; i < 5; i++)
3023 rates[i] = min(max_pwr, rate_info->target_power_6to24);
3025 /* Rest OFDM rates */
3026 rates[5] = min(rates[0], rate_info->target_power_36);
3027 rates[6] = min(rates[0], rate_info->target_power_48);
3028 rates[7] = min(rates[0], rate_info->target_power_54);
3032 rates[8] = min(rates[0], rate_info->target_power_6to24);
3034 rates[9] = min(rates[0], rate_info->target_power_36);
3036 rates[10] = min(rates[0], rate_info->target_power_36);
3038 rates[11] = min(rates[0], rate_info->target_power_48);
3040 rates[12] = min(rates[0], rate_info->target_power_48);
3042 rates[13] = min(rates[0], rate_info->target_power_54);
3044 rates[14] = min(rates[0], rate_info->target_power_54);
3047 rates[15] = min(rates[0], rate_info->target_power_6to24);
3049 /* CCK rates have different peak to average ratio
3050 * so we have to tweak their power so that gainf
3051 * correction works ok. For this we use OFDM to
3052 * CCK delta from eeprom */
3053 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
3054 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
3055 for (i = 8; i <= 15; i++)
3056 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
3058 /* Now that we have all rates setup use table offset to
3059 * match the power range set by user with the power indices
3060 * on PCDAC/PDADC table */
3061 for (i = 0; i < 16; i++) {
3062 rates[i] += ah->ah_txpower.txp_offset;
3063 /* Don't get out of bounds */
3068 /* Min/max in 0.25dB units */
3069 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
3070 ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
3071 ah->ah_txpower.txp_ofdm = rates[7];
3076 * Set transmission power
3079 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3082 struct ath5k_rate_pcal_info rate_info;
3083 struct ieee80211_channel *curr_channel = ah->ah_current_channel;
3087 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3088 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3092 ee_mode = ath5k_eeprom_mode_from_channel(channel);
3094 ATH5K_ERR(ah->ah_sc,
3095 "invalid channel: %d\n", channel->center_freq);
3099 /* Initialize TX power table */
3100 switch (ah->ah_radio) {
3105 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3108 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3115 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3122 * If we don't change channel/mode skip tx powertable calculation
3123 * and use the cached one.
3125 if (!ah->ah_txpower.txp_setup ||
3126 (channel->hw_value != curr_channel->hw_value) ||
3127 (channel->center_freq != curr_channel->center_freq)) {
3128 /* Reset TX power values */
3129 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3130 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3132 /* Calculate the powertable */
3133 ret = ath5k_setup_channel_powertable(ah, channel,
3139 /* Write table on hw */
3140 ath5k_write_channel_powertable(ah, ee_mode, type);
3142 /* Limit max power if we have a CTL available */
3143 ath5k_get_max_ctl_power(ah, channel);
3145 /* FIXME: Antenna reduction stuff */
3147 /* FIXME: Limit power on turbo modes */
3149 /* FIXME: TPC scale reduction */
3151 /* Get surounding channels for per-rate power table
3153 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3155 /* Setup rate power table */
3156 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3158 /* Write rate power table on hw */
3159 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3160 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3161 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3163 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3164 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3165 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3167 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3168 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3169 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3171 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3172 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3173 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3175 /* FIXME: TPC support */
3176 if (ah->ah_txpower.txp_tpc) {
3177 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3178 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3180 ath5k_hw_reg_write(ah,
3181 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3182 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3183 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3186 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3187 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3193 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3195 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3196 "changing txpower to %d\n", txpower);
3198 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
3205 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3208 struct ieee80211_channel *curr_channel;
3214 * Sanity check for fast flag
3215 * Don't try fast channel change when changing modulation
3216 * mode/band. We check for chip compatibility on
3219 curr_channel = ah->ah_current_channel;
3220 if (fast && (channel->hw_value != curr_channel->hw_value))
3224 * On fast channel change we only set the synth parameters
3225 * while PHY is running, enable calibration and skip the rest.
3228 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3229 AR5K_PHY_RFBUS_REQ_REQUEST);
3230 for (i = 0; i < 100; i++) {
3231 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
3243 * Note: We need to do that before we set
3244 * RF buffer settings on 5211/5212+ so that we
3245 * properly set curve indices.
3247 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ?
3248 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER);
3253 * For 5210 we do all initialization using
3254 * initvals, so we don't have to modify
3255 * any settings (5210 also only supports
3258 if ((ah->ah_version != AR5K_AR5210) && !fast) {
3261 * Write initial RF gain settings
3262 * This should work for both 5111/5112
3264 ret = ath5k_hw_rfgain_init(ah, channel->band);
3273 ret = ath5k_hw_rfregs_init(ah, channel, mode);
3277 /* Write OFDM timings on 5212*/
3278 if (ah->ah_version == AR5K_AR5212 &&
3279 channel->hw_value & CHANNEL_OFDM) {
3281 ret = ath5k_hw_write_ofdm_timings(ah, channel);
3285 /* Spur info is available only from EEPROM versions
3286 * greater than 5.3, but the EEPROM routines will use
3287 * static values for older versions */
3288 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
3289 ath5k_hw_set_spur_mitigation_filter(ah,
3293 /*Enable/disable 802.11b mode on 5111
3294 (enable 2111 frequency converter + CCK)*/
3295 if (ah->ah_radio == AR5K_RF5111) {
3296 if (mode == AR5K_MODE_11B)
3297 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
3300 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
3304 } else if (ah->ah_version == AR5K_AR5210) {
3306 /* Disable phy and wait */
3307 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
3311 /* Set channel on PHY */
3312 ret = ath5k_hw_channel(ah, channel);
3317 * Enable the PHY and wait until completion
3318 * This includes BaseBand and Synthesizer
3321 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
3324 * On 5211+ read activation -> rx delay
3327 if (ah->ah_version != AR5K_AR5210) {
3329 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
3330 AR5K_PHY_RX_DELAY_M;
3331 delay = (channel->hw_value & CHANNEL_CCK) ?
3332 ((delay << 2) / 22) : (delay / 10);
3333 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
3335 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
3337 /* XXX: /2 on turbo ? Let's be safe
3339 udelay(100 + delay);
3346 * Release RF Bus grant
3348 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3349 AR5K_PHY_RFBUS_REQ_REQUEST);
3352 * Perform ADC test to see if baseband is ready
3353 * Set tx hold and check adc test register
3355 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
3356 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
3357 for (i = 0; i <= 20; i++) {
3358 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
3362 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
3366 * Start automatic gain control calibration
3368 * During AGC calibration RX path is re-routed to
3369 * a power detector so we don't receive anything.
3371 * This method is used to calibrate some static offsets
3372 * used together with on-the fly I/Q calibration (the
3373 * one performed via ath5k_hw_phy_calibrate), which doesn't
3374 * interrupt rx path.
3376 * While rx path is re-routed to the power detector we also
3377 * start a noise floor calibration to measure the
3378 * card's noise floor (the noise we measure when we are not
3379 * transmitting or receiving anything).
3381 * If we are in a noisy environment, AGC calibration may time
3382 * out and/or noise floor calibration might timeout.
3384 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3385 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
3387 /* At the same time start I/Q calibration for QAM constellation
3388 * -no need for CCK- */
3389 ah->ah_calibration = false;
3390 if (!(mode == AR5K_MODE_11B)) {
3391 ah->ah_calibration = true;
3392 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
3393 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
3394 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
3398 /* Wait for gain calibration to finish (we check for I/Q calibration
3399 * during ath5k_phy_calibrate) */
3400 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
3401 AR5K_PHY_AGCCTL_CAL, 0, false)) {
3402 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
3403 channel->center_freq);
3406 /* Restore antenna mode */
3407 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);