drivers/net/wireless/ath/ath5k/phy.c

   1 /*
   2  * PHY functions
   3  *
   4  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
   5  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
   6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
   7  * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
   8  *
   9  * Permission to use, copy, modify, and distribute this software for any
  10  * purpose with or without fee is hereby granted, provided that the above
  11  * copyright notice and this permission notice appear in all copies.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20  *
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25
  26 #include "ath5k.h"
  27 #include "reg.h"
  28 #include "base.h"
  29 #include "rfbuffer.h"
  30 #include "rfgain.h"
  31
  32 /*
  33  * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
  34  */
  35 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
  36                                         const struct ath5k_rf_reg *rf_regs,
  37                                         u32 val, u8 reg_id, bool set)
  38 {
  39         const struct ath5k_rf_reg *rfreg = NULL;
  40         u8 offset, bank, num_bits, col, position;
  41         u16 entry;
  42         u32 mask, data, last_bit, bits_shifted, first_bit;
  43         u32 *rfb;
  44         s32 bits_left;
  45         int i;
  46
  47         data = 0;
  48         rfb = ah->ah_rf_banks;
  49
  50         for (i = 0; i < ah->ah_rf_regs_count; i++) {
  51                 if (rf_regs[i].index == reg_id) {
  52                         rfreg = &rf_regs[i];
  53                         break;
  54                 }
  55         }
  56
  57         if (rfb == NULL || rfreg == NULL) {
  58                 ATH5K_PRINTF("Rf register not found!\n");
  59                 /* should not happen */
  60                 return 0;
  61         }
  62
  63         bank = rfreg->bank;
  64         num_bits = rfreg->field.len;
  65         first_bit = rfreg->field.pos;
  66         col = rfreg->field.col;
  67
  68         /* first_bit is an offset from bank's
  69          * start. Since we have all banks on
  70          * the same array, we use this offset
  71          * to mark each bank's start */
  72         offset = ah->ah_offset[bank];
  73
  74         /* Boundary check */
  75         if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
  76                 ATH5K_PRINTF("invalid values at offset %u\n", offset);
  77                 return 0;
  78         }
  79
  80         entry = ((first_bit - 1) / 8) + offset;
  81         position = (first_bit - 1) % 8;
  82
  83         if (set)
  84                 data = ath5k_hw_bitswap(val, num_bits);
  85
  86         for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
  87         position = 0, entry++) {
  88
  89                 last_bit = (position + bits_left > 8) ? 8 :
  90                                         position + bits_left;
  91
  92                 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
  93                                                                 (col * 8);
  94
  95                 if (set) {
  96                         rfb[entry] &= ~mask;
  97                         rfb[entry] |= ((data << position) << (col * 8)) & mask;
  98                         data >>= (8 - position);
  99                 } else {
 100                         data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
 101                                 << bits_shifted;
 102                         bits_shifted += last_bit - position;
 103                 }
 104
 105                 bits_left -= 8 - position;
 106         }
 107
 108         data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
 109
 110         return data;
 111 }
 112
 113 /**********************\
 114 * RF Gain optimization *
 115 \**********************/
 116
 117 /*
 118  * This code is used to optimize RF gain on different environments
 119  * (temperature mostly) based on feedback from a power detector.
 120  *
 121  * It's only used on RF5111 and RF5112, later RF chips seem to have
 122  * auto adjustment on hw -notice they have a much smaller BANK 7 and
 123  * no gain optimization ladder-.
 124  *
 125  * For more infos check out this patent doc
 126  * http://www.freepatentsonline.com/7400691.html
 127  *
 128  * This paper describes power drops as seen on the receiver due to
 129  * probe packets
 130  * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
 131  * %20of%20Power%20Control.pdf
 132  *
 133  * And this is the MadWiFi bug entry related to the above
 134  * http://madwifi-project.org/ticket/1659
 135  * with various measurements and diagrams
 136  *
 137  * TODO: Deal with power drops due to probes by setting an apropriate
 138  * tx power on the probe packets ! Make this part of the calibration process.
 139  */
 140
 141 /* Initialize ah_gain durring attach */
 142 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
 143 {
 144         /* Initialize the gain optimization values */
 145         switch (ah->ah_radio) {
 146         case AR5K_RF5111:
 147                 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
 148                 ah->ah_gain.g_low = 20;
 149                 ah->ah_gain.g_high = 35;
 150                 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 151                 break;
 152         case AR5K_RF5112:
 153                 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
 154                 ah->ah_gain.g_low = 20;
 155                 ah->ah_gain.g_high = 85;
 156                 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 157                 break;
 158         default:
 159                 return -EINVAL;
 160         }
 161
 162         return 0;
 163 }
 164
 165 /* Schedule a gain probe check on the next transmited packet.
 166  * That means our next packet is going to be sent with lower
 167  * tx power and a Peak to Average Power Detector (PAPD) will try
 168  * to measure the gain.
 169  *
 170  * XXX:  How about forcing a tx packet (bypassing PCU arbitrator etc)
 171  * just after we enable the probe so that we don't mess with
 172  * standard traffic ? Maybe it's time to use sw interrupts and
 173  * a probe tasklet !!!
 174  */
 175 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
 176 {
 177
 178         /* Skip if gain calibration is inactive or
 179          * we already handle a probe request */
 180         if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
 181                 return;
 182
 183         /* Send the packet with 2dB below max power as
 184          * patent doc suggest */
 185         ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
 186                         AR5K_PHY_PAPD_PROBE_TXPOWER) |
 187                         AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
 188
 189         ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
 190
 191 }
 192
 193 /* Calculate gain_F measurement correction
 194  * based on the current step for RF5112 rev. 2 */
 195 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
 196 {
 197         u32 mix, step;
 198         u32 *rf;
 199         const struct ath5k_gain_opt *go;
 200         const struct ath5k_gain_opt_step *g_step;
 201         const struct ath5k_rf_reg *rf_regs;
 202
 203         /* Only RF5112 Rev. 2 supports it */
 204         if ((ah->ah_radio != AR5K_RF5112) ||
 205         (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
 206                 return 0;
 207
 208         go = &rfgain_opt_5112;
 209         rf_regs = rf_regs_5112a;
 210         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
 211
 212         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 213
 214         if (ah->ah_rf_banks == NULL)
 215                 return 0;
 216
 217         rf = ah->ah_rf_banks;
 218         ah->ah_gain.g_f_corr = 0;
 219
 220         /* No VGA (Variable Gain Amplifier) override, skip */
 221         if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
 222                 return 0;
 223
 224         /* Mix gain stepping */
 225         step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
 226
 227         /* Mix gain override */
 228         mix = g_step->gos_param[0];
 229
 230         switch (mix) {
 231         case 3:
 232                 ah->ah_gain.g_f_corr = step * 2;
 233                 break;
 234         case 2:
 235                 ah->ah_gain.g_f_corr = (step - 5) * 2;
 236                 break;
 237         case 1:
 238                 ah->ah_gain.g_f_corr = step;
 239                 break;
 240         default:
 241                 ah->ah_gain.g_f_corr = 0;
 242                 break;
 243         }
 244
 245         return ah->ah_gain.g_f_corr;
 246 }
 247
 248 /* Check if current gain_F measurement is in the range of our
 249  * power detector windows. If we get a measurement outside range
 250  * we know it's not accurate (detectors can't measure anything outside
 251  * their detection window) so we must ignore it */
 252 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
 253 {
 254         const struct ath5k_rf_reg *rf_regs;
 255         u32 step, mix_ovr, level[4];
 256         u32 *rf;
 257
 258         if (ah->ah_rf_banks == NULL)
 259                 return false;
 260
 261         rf = ah->ah_rf_banks;
 262
 263         if (ah->ah_radio == AR5K_RF5111) {
 264
 265                 rf_regs = rf_regs_5111;
 266                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
 267
 268                 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
 269                         false);
 270
 271                 level[0] = 0;
 272                 level[1] = (step == 63) ? 50 : step + 4;
 273                 level[2] = (step != 63) ? 64 : level[0];
 274                 level[3] = level[2] + 50 ;
 275
 276                 ah->ah_gain.g_high = level[3] -
 277                         (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
 278                 ah->ah_gain.g_low = level[0] +
 279                         (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
 280         } else {
 281
 282                 rf_regs = rf_regs_5112;
 283                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
 284
 285                 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
 286                         false);
 287
 288                 level[0] = level[2] = 0;
 289
 290                 if (mix_ovr == 1) {
 291                         level[1] = level[3] = 83;
 292                 } else {
 293                         level[1] = level[3] = 107;
 294                         ah->ah_gain.g_high = 55;
 295                 }
 296         }
 297
 298         return (ah->ah_gain.g_current >= level[0] &&
 299                         ah->ah_gain.g_current <= level[1]) ||
 300                 (ah->ah_gain.g_current >= level[2] &&
 301                         ah->ah_gain.g_current <= level[3]);
 302 }
 303
 304 /* Perform gain_F adjustment by choosing the right set
 305  * of parameters from RF gain optimization ladder */
 306 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
 307 {
 308         const struct ath5k_gain_opt *go;
 309         const struct ath5k_gain_opt_step *g_step;
 310         int ret = 0;
 311
 312         switch (ah->ah_radio) {
 313         case AR5K_RF5111:
 314                 go = &rfgain_opt_5111;
 315                 break;
 316         case AR5K_RF5112:
 317                 go = &rfgain_opt_5112;
 318                 break;
 319         default:
 320                 return 0;
 321         }
 322
 323         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 324
 325         if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
 326
 327                 /* Reached maximum */
 328                 if (ah->ah_gain.g_step_idx == 0)
 329                         return -1;
 330
 331                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
 332                                 ah->ah_gain.g_target >=  ah->ah_gain.g_high &&
 333                                 ah->ah_gain.g_step_idx > 0;
 334                                 g_step = &go->go_step[ah->ah_gain.g_step_idx])
 335                         ah->ah_gain.g_target -= 2 *
 336                             (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
 337                             g_step->gos_gain);
 338
 339                 ret = 1;
 340                 goto done;
 341         }
 342
 343         if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
 344
 345                 /* Reached minimum */
 346                 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
 347                         return -2;
 348
 349                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
 350                                 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
 351                                 ah->ah_gain.g_step_idx < go->go_steps_count-1;
 352                                 g_step = &go->go_step[ah->ah_gain.g_step_idx])
 353                         ah->ah_gain.g_target -= 2 *
 354                             (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
 355                             g_step->gos_gain);
 356
 357                 ret = 2;
 358                 goto done;
 359         }
 360
 361 done:
 362         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
 363                 "ret %d, gain step %u, current gain %u, target gain %u\n",
 364                 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
 365                 ah->ah_gain.g_target);
 366
 367         return ret;
 368 }
 369
 370 /* Main callback for thermal RF gain calibration engine
 371  * Check for a new gain reading and schedule an adjustment
 372  * if needed.
 373  *
 374  * TODO: Use sw interrupt to schedule reset if gain_F needs
 375  * adjustment */
 376 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
 377 {
 378         u32 data, type;
 379         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 380
 381         if (ah->ah_rf_banks == NULL ||
 382         ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
 383                 return AR5K_RFGAIN_INACTIVE;
 384
 385         /* No check requested, either engine is inactive
 386          * or an adjustment is already requested */
 387         if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
 388                 goto done;
 389
 390         /* Read the PAPD (Peak to Average Power Detector)
 391          * register */
 392         data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
 393
 394         /* No probe is scheduled, read gain_F measurement */
 395         if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
 396                 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
 397                 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
 398
 399                 /* If tx packet is CCK correct the gain_F measurement
 400                  * by cck ofdm gain delta */
 401                 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
 402                         if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
 403                                 ah->ah_gain.g_current +=
 404                                         ee->ee_cck_ofdm_gain_delta;
 405                         else
 406                                 ah->ah_gain.g_current +=
 407                                         AR5K_GAIN_CCK_PROBE_CORR;
 408                 }
 409
 410                 /* Further correct gain_F measurement for
 411                  * RF5112A radios */
 412                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
 413                         ath5k_hw_rf_gainf_corr(ah);
 414                         ah->ah_gain.g_current =
 415                                 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
 416                                 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
 417                                 0;
 418                 }
 419
 420                 /* Check if measurement is ok and if we need
 421                  * to adjust gain, schedule a gain adjustment,
 422                  * else switch back to the acive state */
 423                 if (ath5k_hw_rf_check_gainf_readback(ah) &&
 424                 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
 425                 ath5k_hw_rf_gainf_adjust(ah)) {
 426                         ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
 427                 } else {
 428                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 429                 }
 430         }
 431
 432 done:
 433         return ah->ah_gain.g_state;
 434 }
 435
 436 /* Write initial RF gain table to set the RF sensitivity
 437  * this one works on all RF chips and has nothing to do
 438  * with gain_F calibration */
 439 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
 440 {
 441         const struct ath5k_ini_rfgain *ath5k_rfg;
 442         unsigned int i, size;
 443
 444         switch (ah->ah_radio) {
 445         case AR5K_RF5111:
 446                 ath5k_rfg = rfgain_5111;
 447                 size = ARRAY_SIZE(rfgain_5111);
 448                 break;
 449         case AR5K_RF5112:
 450                 ath5k_rfg = rfgain_5112;
 451                 size = ARRAY_SIZE(rfgain_5112);
 452                 break;
 453         case AR5K_RF2413:
 454                 ath5k_rfg = rfgain_2413;
 455                 size = ARRAY_SIZE(rfgain_2413);
 456                 break;
 457         case AR5K_RF2316:
 458                 ath5k_rfg = rfgain_2316;
 459                 size = ARRAY_SIZE(rfgain_2316);
 460                 break;
 461         case AR5K_RF5413:
 462                 ath5k_rfg = rfgain_5413;
 463                 size = ARRAY_SIZE(rfgain_5413);
 464                 break;
 465         case AR5K_RF2317:
 466         case AR5K_RF2425:
 467                 ath5k_rfg = rfgain_2425;
 468                 size = ARRAY_SIZE(rfgain_2425);
 469                 break;
 470         default:
 471                 return -EINVAL;
 472         }
 473
 474         switch (freq) {
 475         case AR5K_INI_RFGAIN_2GHZ:
 476         case AR5K_INI_RFGAIN_5GHZ:
 477                 break;
 478         default:
 479                 return -EINVAL;
 480         }
 481
 482         for (i = 0; i < size; i++) {
 483                 AR5K_REG_WAIT(i);
 484                 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
 485                         (u32)ath5k_rfg[i].rfg_register);
 486         }
 487
 488         return 0;
 489 }
 490
 491
 492
 493 /********************\
 494 * RF Registers setup *
 495 \********************/
 496
 497
 498 /*
 499  * Setup RF registers by writing RF buffer on hw
 500  */
 501 int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 502                 unsigned int mode)
 503 {
 504         const struct ath5k_rf_reg *rf_regs;
 505         const struct ath5k_ini_rfbuffer *ini_rfb;
 506         const struct ath5k_gain_opt *go = NULL;
 507         const struct ath5k_gain_opt_step *g_step;
 508         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 509         u8 ee_mode = 0;
 510         u32 *rfb;
 511         int i, obdb = -1, bank = -1;
 512
 513         switch (ah->ah_radio) {
 514         case AR5K_RF5111:
 515                 rf_regs = rf_regs_5111;
 516                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
 517                 ini_rfb = rfb_5111;
 518                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
 519                 go = &rfgain_opt_5111;
 520                 break;
 521         case AR5K_RF5112:
 522                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
 523                         rf_regs = rf_regs_5112a;
 524                         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
 525                         ini_rfb = rfb_5112a;
 526                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
 527                 } else {
 528                         rf_regs = rf_regs_5112;
 529                         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
 530                         ini_rfb = rfb_5112;
 531                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
 532                 }
 533                 go = &rfgain_opt_5112;
 534                 break;
 535         case AR5K_RF2413:
 536                 rf_regs = rf_regs_2413;
 537                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
 538                 ini_rfb = rfb_2413;
 539                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
 540                 break;
 541         case AR5K_RF2316:
 542                 rf_regs = rf_regs_2316;
 543                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
 544                 ini_rfb = rfb_2316;
 545                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
 546                 break;
 547         case AR5K_RF5413:
 548                 rf_regs = rf_regs_5413;
 549                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
 550                 ini_rfb = rfb_5413;
 551                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
 552                 break;
 553         case AR5K_RF2317:
 554                 rf_regs = rf_regs_2425;
 555                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
 556                 ini_rfb = rfb_2317;
 557                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
 558                 break;
 559         case AR5K_RF2425:
 560                 rf_regs = rf_regs_2425;
 561                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
 562                 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
 563                         ini_rfb = rfb_2425;
 564                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
 565                 } else {
 566                         ini_rfb = rfb_2417;
 567                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
 568                 }
 569                 break;
 570         default:
 571                 return -EINVAL;
 572         }
 573
 574         /* If it's the first time we set RF buffer, allocate
 575          * ah->ah_rf_banks based on ah->ah_rf_banks_size
 576          * we set above */
 577         if (ah->ah_rf_banks == NULL) {
 578                 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
 579                                                                 GFP_KERNEL);
 580                 if (ah->ah_rf_banks == NULL) {
 581                         ATH5K_ERR(ah->ah_sc, "out of memory\n");
 582                         return -ENOMEM;
 583                 }
 584         }
 585
 586         /* Copy values to modify them */
 587         rfb = ah->ah_rf_banks;
 588
 589         for (i = 0; i < ah->ah_rf_banks_size; i++) {
 590                 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
 591                         ATH5K_ERR(ah->ah_sc, "invalid bank\n");
 592                         return -EINVAL;
 593                 }
 594
 595                 /* Bank changed, write down the offset */
 596                 if (bank != ini_rfb[i].rfb_bank) {
 597                         bank = ini_rfb[i].rfb_bank;
 598                         ah->ah_offset[bank] = i;
 599                 }
 600
 601                 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
 602         }
 603
 604         /* Set Output and Driver bias current (OB/DB) */
 605         if (channel->hw_value & CHANNEL_2GHZ) {
 606
 607                 if (channel->hw_value & CHANNEL_CCK)
 608                         ee_mode = AR5K_EEPROM_MODE_11B;
 609                 else
 610                         ee_mode = AR5K_EEPROM_MODE_11G;
 611
 612                 /* For RF511X/RF211X combination we
 613                  * use b_OB and b_DB parameters stored
 614                  * in eeprom on ee->ee_ob[ee_mode][0]
 615                  *
 616                  * For all other chips we use OB/DB for 2Ghz
 617                  * stored in the b/g modal section just like
 618                  * 802.11a on ee->ee_ob[ee_mode][1] */
 619                 if ((ah->ah_radio == AR5K_RF5111) ||
 620                 (ah->ah_radio == AR5K_RF5112))
 621                         obdb = 0;
 622                 else
 623                         obdb = 1;
 624
 625                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
 626                                                 AR5K_RF_OB_2GHZ, true);
 627
 628                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
 629                                                 AR5K_RF_DB_2GHZ, true);
 630
 631         /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
 632         } else if ((channel->hw_value & CHANNEL_5GHZ) ||
 633                         (ah->ah_radio == AR5K_RF5111)) {
 634
 635                 /* For 11a, Turbo and XR we need to choose
 636                  * OB/DB based on frequency range */
 637                 ee_mode = AR5K_EEPROM_MODE_11A;
 638                 obdb =   channel->center_freq >= 5725 ? 3 :
 639                         (channel->center_freq >= 5500 ? 2 :
 640                         (channel->center_freq >= 5260 ? 1 :
 641                          (channel->center_freq > 4000 ? 0 : -1)));
 642
 643                 if (obdb < 0)
 644                         return -EINVAL;
 645
 646                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
 647                                                 AR5K_RF_OB_5GHZ, true);
 648
 649                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
 650                                                 AR5K_RF_DB_5GHZ, true);
 651         }
 652
 653         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 654
 655         /* Bank Modifications (chip-specific) */
 656         if (ah->ah_radio == AR5K_RF5111) {
 657
 658                 /* Set gain_F settings according to current step */
 659                 if (channel->hw_value & CHANNEL_OFDM) {
 660
 661                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
 662                                         AR5K_PHY_FRAME_CTL_TX_CLIP,
 663                                         g_step->gos_param[0]);
 664
 665                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
 666                                                         AR5K_RF_PWD_90, true);
 667
 668                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
 669                                                         AR5K_RF_PWD_84, true);
 670
 671                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
 672                                                 AR5K_RF_RFGAIN_SEL, true);
 673
 674                         /* We programmed gain_F parameters, switch back
 675                          * to active state */
 676                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 677
 678                 }
 679
 680                 /* Bank 6/7 setup */
 681
 682                 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
 683                                                 AR5K_RF_PWD_XPD, true);
 684
 685                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
 686                                                 AR5K_RF_XPD_GAIN, true);
 687
 688                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
 689                                                 AR5K_RF_GAIN_I, true);
 690
 691                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
 692                                                 AR5K_RF_PLO_SEL, true);
 693
 694                 /* TODO: Half/quarter channel support */
 695         }
 696
 697         if (ah->ah_radio == AR5K_RF5112) {
 698
 699                 /* Set gain_F settings according to current step */
 700                 if (channel->hw_value & CHANNEL_OFDM) {
 701
 702                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
 703                                                 AR5K_RF_MIXGAIN_OVR, true);
 704
 705                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
 706                                                 AR5K_RF_PWD_138, true);
 707
 708                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
 709                                                 AR5K_RF_PWD_137, true);
 710
 711                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
 712                                                 AR5K_RF_PWD_136, true);
 713
 714                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
 715                                                 AR5K_RF_PWD_132, true);
 716
 717                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
 718                                                 AR5K_RF_PWD_131, true);
 719
 720                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
 721                                                 AR5K_RF_PWD_130, true);
 722
 723                         /* We programmed gain_F parameters, switch back
 724                          * to active state */
 725                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 726                 }
 727
 728                 /* Bank 6/7 setup */
 729
 730                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
 731                                                 AR5K_RF_XPD_SEL, true);
 732
 733                 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
 734                         /* Rev. 1 supports only one xpd */
 735                         ath5k_hw_rfb_op(ah, rf_regs,
 736                                                 ee->ee_x_gain[ee_mode],
 737                                                 AR5K_RF_XPD_GAIN, true);
 738
 739                 } else {
 740                         u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
 741                         if (ee->ee_pd_gains[ee_mode] > 1) {
 742                                 ath5k_hw_rfb_op(ah, rf_regs,
 743                                                 pdg_curve_to_idx[0],
 744                                                 AR5K_RF_PD_GAIN_LO, true);
 745                                 ath5k_hw_rfb_op(ah, rf_regs,
 746                                                 pdg_curve_to_idx[1],
 747                                                 AR5K_RF_PD_GAIN_HI, true);
 748                         } else {
 749                                 ath5k_hw_rfb_op(ah, rf_regs,
 750                                                 pdg_curve_to_idx[0],
 751                                                 AR5K_RF_PD_GAIN_LO, true);
 752                                 ath5k_hw_rfb_op(ah, rf_regs,
 753                                                 pdg_curve_to_idx[0],
 754                                                 AR5K_RF_PD_GAIN_HI, true);
 755                         }
 756
 757                         /* Lower synth voltage on Rev 2 */
 758                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 759                                         AR5K_RF_HIGH_VC_CP, true);
 760
 761                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 762                                         AR5K_RF_MID_VC_CP, true);
 763
 764                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 765                                         AR5K_RF_LOW_VC_CP, true);
 766
 767                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 768                                         AR5K_RF_PUSH_UP, true);
 769
 770                         /* Decrease power consumption on 5213+ BaseBand */
 771                         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
 772                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 773                                                 AR5K_RF_PAD2GND, true);
 774
 775                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 776                                                 AR5K_RF_XB2_LVL, true);
 777
 778                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 779                                                 AR5K_RF_XB5_LVL, true);
 780
 781                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 782                                                 AR5K_RF_PWD_167, true);
 783
 784                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 785                                                 AR5K_RF_PWD_166, true);
 786                         }
 787                 }
 788
 789                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
 790                                                 AR5K_RF_GAIN_I, true);
 791
 792                 /* TODO: Half/quarter channel support */
 793
 794         }
 795
 796         if (ah->ah_radio == AR5K_RF5413 &&
 797         channel->hw_value & CHANNEL_2GHZ) {
 798
 799                 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
 800                                                                         true);
 801
 802                 /* Set optimum value for early revisions (on pci-e chips) */
 803                 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
 804                 ah->ah_mac_srev < AR5K_SREV_AR5413)
 805                         ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
 806                                                 AR5K_RF_PWD_ICLOBUF_2G, true);
 807
 808         }
 809
 810         /* Write RF banks on hw */
 811         for (i = 0; i < ah->ah_rf_banks_size; i++) {
 812                 AR5K_REG_WAIT(i);
 813                 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
 814         }
 815
 816         return 0;
 817 }
 818
 819
 820 /**************************\
 821   PHY/RF channel functions
 822 \**************************/
 823
 824 /*
 825  * Check if a channel is supported
 826  */
 827 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
 828 {
 829         /* Check if the channel is in our supported range */
 830         if (flags & CHANNEL_2GHZ) {
 831                 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
 832                     (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
 833                         return true;
 834         } else if (flags & CHANNEL_5GHZ)
 835                 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
 836                     (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
 837                         return true;
 838
 839         return false;
 840 }
 841
 842 /*
 843  * Convertion needed for RF5110
 844  */
 845 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 846 {
 847         u32 athchan;
 848
 849         /*
 850          * Convert IEEE channel/MHz to an internal channel value used
 851          * by the AR5210 chipset. This has not been verified with
 852          * newer chipsets like the AR5212A who have a completely
 853          * different RF/PHY part.
 854          */
 855         athchan = (ath5k_hw_bitswap(
 856                         (ieee80211_frequency_to_channel(
 857                                 channel->center_freq) - 24) / 2, 5)
 858                                 << 1) | (1 << 6) | 0x1;
 859         return athchan;
 860 }
 861
 862 /*
 863  * Set channel on RF5110
 864  */
 865 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
 866                 struct ieee80211_channel *channel)
 867 {
 868         u32 data;
 869
 870         /*
 871          * Set the channel and wait
 872          */
 873         data = ath5k_hw_rf5110_chan2athchan(channel);
 874         ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
 875         ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
 876         mdelay(1);
 877
 878         return 0;
 879 }
 880
 881 /*
 882  * Convertion needed for 5111
 883  */
 884 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
 885                 struct ath5k_athchan_2ghz *athchan)
 886 {
 887         int channel;
 888
 889         /* Cast this value to catch negative channel numbers (>= -19) */
 890         channel = (int)ieee;
 891
 892         /*
 893          * Map 2GHz IEEE channel to 5GHz Atheros channel
 894          */
 895         if (channel <= 13) {
 896                 athchan->a2_athchan = 115 + channel;
 897                 athchan->a2_flags = 0x46;
 898         } else if (channel == 14) {
 899                 athchan->a2_athchan = 124;
 900                 athchan->a2_flags = 0x44;
 901         } else if (channel >= 15 && channel <= 26) {
 902                 athchan->a2_athchan = ((channel - 14) * 4) + 132;
 903                 athchan->a2_flags = 0x46;
 904         } else
 905                 return -EINVAL;
 906
 907         return 0;
 908 }
 909
 910 /*
 911  * Set channel on 5111
 912  */
 913 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
 914                 struct ieee80211_channel *channel)
 915 {
 916         struct ath5k_athchan_2ghz ath5k_channel_2ghz;
 917         unsigned int ath5k_channel =
 918                 ieee80211_frequency_to_channel(channel->center_freq);
 919         u32 data0, data1, clock;
 920         int ret;
 921
 922         /*
 923          * Set the channel on the RF5111 radio
 924          */
 925         data0 = data1 = 0;
 926
 927         if (channel->hw_value & CHANNEL_2GHZ) {
 928                 /* Map 2GHz channel to 5GHz Atheros channel ID */
 929                 ret = ath5k_hw_rf5111_chan2athchan(
 930                         ieee80211_frequency_to_channel(channel->center_freq),
 931                         &ath5k_channel_2ghz);
 932                 if (ret)
 933                         return ret;
 934
 935                 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
 936                 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
 937                     << 5) | (1 << 4);
 938         }
 939
 940         if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
 941                 clock = 1;
 942                 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
 943                         (clock << 1) | (1 << 10) | 1;
 944         } else {
 945                 clock = 0;
 946                 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
 947                         << 2) | (clock << 1) | (1 << 10) | 1;
 948         }
 949
 950         ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
 951                         AR5K_RF_BUFFER);
 952         ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
 953                         AR5K_RF_BUFFER_CONTROL_3);
 954
 955         return 0;
 956 }
 957
 958 /*
 959  * Set channel on 5112 and newer
 960  */
 961 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
 962                 struct ieee80211_channel *channel)
 963 {
 964         u32 data, data0, data1, data2;
 965         u16 c;
 966
 967         data = data0 = data1 = data2 = 0;
 968         c = channel->center_freq;
 969
 970         if (c < 4800) {
 971                 if (!((c - 2224) % 5)) {
 972                         data0 = ((2 * (c - 704)) - 3040) / 10;
 973                         data1 = 1;
 974                 } else if (!((c - 2192) % 5)) {
 975                         data0 = ((2 * (c - 672)) - 3040) / 10;
 976                         data1 = 0;
 977                 } else
 978                         return -EINVAL;
 979
 980                 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
 981         } else if ((c % 5) != 2 || c > 5435) {
 982                 if (!(c % 20) && c >= 5120) {
 983                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
 984                         data2 = ath5k_hw_bitswap(3, 2);
 985                 } else if (!(c % 10)) {
 986                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
 987                         data2 = ath5k_hw_bitswap(2, 2);
 988                 } else if (!(c % 5)) {
 989                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
 990                         data2 = ath5k_hw_bitswap(1, 2);
 991                 } else
 992                         return -EINVAL;
 993         } else {
 994                 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
 995                 data2 = ath5k_hw_bitswap(0, 2);
 996         }
 997
 998         data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
 999
1000         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1001         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1002
1003         return 0;
1004 }
1005
1006 /*
1007  * Set the channel on the RF2425
1008  */
1009 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1010                 struct ieee80211_channel *channel)
1011 {
1012         u32 data, data0, data2;
1013         u16 c;
1014
1015         data = data0 = data2 = 0;
1016         c = channel->center_freq;
1017
1018         if (c < 4800) {
1019                 data0 = ath5k_hw_bitswap((c - 2272), 8);
1020                 data2 = 0;
1021         /* ? 5GHz ? */
1022         } else if ((c % 5) != 2 || c > 5435) {
1023                 if (!(c % 20) && c < 5120)
1024                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1025                 else if (!(c % 10))
1026                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1027                 else if (!(c % 5))
1028                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1029                 else
1030                         return -EINVAL;
1031                 data2 = ath5k_hw_bitswap(1, 2);
1032         } else {
1033                 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1034                 data2 = ath5k_hw_bitswap(0, 2);
1035         }
1036
1037         data = (data0 << 4) | data2 << 2 | 0x1001;
1038
1039         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1040         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1041
1042         return 0;
1043 }
1044
1045 /*
1046  * Set a channel on the radio chip
1047  */
1048 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1049 {
1050         int ret;
1051         /*
1052          * Check bounds supported by the PHY (we don't care about regultory
1053          * restrictions at this point). Note: hw_value already has the band
1054          * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1055          * of the band by that */
1056         if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1057                 ATH5K_ERR(ah->ah_sc,
1058                         "channel frequency (%u MHz) out of supported "
1059                         "band range\n",
1060                         channel->center_freq);
1061                         return -EINVAL;
1062         }
1063
1064         /*
1065          * Set the channel and wait
1066          */
1067         switch (ah->ah_radio) {
1068         case AR5K_RF5110:
1069                 ret = ath5k_hw_rf5110_channel(ah, channel);
1070                 break;
1071         case AR5K_RF5111:
1072                 ret = ath5k_hw_rf5111_channel(ah, channel);
1073                 break;
1074         case AR5K_RF2425:
1075                 ret = ath5k_hw_rf2425_channel(ah, channel);
1076                 break;
1077         default:
1078                 ret = ath5k_hw_rf5112_channel(ah, channel);
1079                 break;
1080         }
1081
1082         if (ret)
1083                 return ret;
1084
1085         /* Set JAPAN setting for channel 14 */
1086         if (channel->center_freq == 2484) {
1087                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1088                                 AR5K_PHY_CCKTXCTL_JAPAN);
1089         } else {
1090                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1091                                 AR5K_PHY_CCKTXCTL_WORLD);
1092         }
1093
1094         ah->ah_current_channel = channel;
1095         ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1096         ath5k_hw_set_clockrate(ah);
1097
1098         return 0;
1099 }
1100
1101 /*****************\
1102   PHY calibration
1103 \*****************/
1104
1105 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1106 {
1107         s32 val;
1108
1109         val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1110         return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
1111 }
1112
1113 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1114 {
1115         int i;
1116
1117         ah->ah_nfcal_hist.index = 0;
1118         for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1119                 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1120 }
1121
1122 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1123 {
1124         struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1125         hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1126         hist->nfval[hist->index] = noise_floor;
1127 }
1128
1129 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1130 {
1131         s16 sort[ATH5K_NF_CAL_HIST_MAX];
1132         s16 tmp;
1133         int i, j;
1134
1135         memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1136         for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1137                 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1138                         if (sort[j] > sort[j-1]) {
1139                                 tmp = sort[j];
1140                                 sort[j] = sort[j-1];
1141                                 sort[j-1] = tmp;
1142                         }
1143                 }
1144         }
1145         for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1146                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1147                         "cal %d:%d\n", i, sort[i]);
1148         }
1149         return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1150 }
1151
1152 /*
1153  * When we tell the hardware to perform a noise floor calibration
1154  * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1155  * sample-and-hold the minimum noise level seen at the antennas.
1156  * This value is then stored in a ring buffer of recently measured
1157  * noise floor values so we have a moving window of the last few
1158  * samples.
1159  *
1160  * The median of the values in the history is then loaded into the
1161  * hardware for its own use for RSSI and CCA measurements.
1162  */
1163 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1164 {
1165         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1166         u32 val;
1167         s16 nf, threshold;
1168         u8 ee_mode;
1169
1170         /* keep last value if calibration hasn't completed */
1171         if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1172                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1173                         "NF did not complete in calibration window\n");
1174
1175                 return;
1176         }
1177
1178         switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1179         case CHANNEL_A:
1180         case CHANNEL_T:
1181         case CHANNEL_XR:
1182                 ee_mode = AR5K_EEPROM_MODE_11A;
1183                 break;
1184         case CHANNEL_G:
1185         case CHANNEL_TG:
1186                 ee_mode = AR5K_EEPROM_MODE_11G;
1187                 break;
1188         default:
1189         case CHANNEL_B:
1190                 ee_mode = AR5K_EEPROM_MODE_11B;
1191                 break;
1192         }
1193
1194
1195         /* completed NF calibration, test threshold */
1196         nf = ath5k_hw_read_measured_noise_floor(ah);
1197         threshold = ee->ee_noise_floor_thr[ee_mode];
1198
1199         if (nf > threshold) {
1200                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1201                         "noise floor failure detected; "
1202                         "read %d, threshold %d\n",
1203                         nf, threshold);
1204
1205                 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1206         }
1207
1208         ath5k_hw_update_nfcal_hist(ah, nf);
1209         nf = ath5k_hw_get_median_noise_floor(ah);
1210
1211         /* load noise floor (in .5 dBm) so the hardware will use it */
1212         val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1213         val |= (nf * 2) & AR5K_PHY_NF_M;
1214         ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1215
1216         AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1217                 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1218
1219         ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1220                 0, false);
1221
1222         /*
1223          * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1224          * so that we're not capped by the median we just loaded.
1225          * This will be used as the initial value for the next noise
1226          * floor calibration.
1227          */
1228         val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1229         ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1230         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1231                 AR5K_PHY_AGCCTL_NF_EN |
1232                 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1233                 AR5K_PHY_AGCCTL_NF);
1234
1235         ah->ah_noise_floor = nf;
1236
1237         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1238                 "noise floor calibrated: %d\n", nf);
1239 }
1240
1241 /*
1242  * Perform a PHY calibration on RF5110
1243  * -Fix BPSK/QAM Constellation (I/Q correction)
1244  */
1245 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1246                 struct ieee80211_channel *channel)
1247 {
1248         u32 phy_sig, phy_agc, phy_sat, beacon;
1249         int ret;
1250
1251         /*
1252          * Disable beacons and RX/TX queues, wait
1253          */
1254         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1255                 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1256         beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1257         ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1258
1259         mdelay(2);
1260
1261         /*
1262          * Set the channel (with AGC turned off)
1263          */
1264         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1265         udelay(10);
1266         ret = ath5k_hw_channel(ah, channel);
1267
1268         /*
1269          * Activate PHY and wait
1270          */
1271         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1272         mdelay(1);
1273
1274         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1275
1276         if (ret)
1277                 return ret;
1278
1279         /*
1280          * Calibrate the radio chip
1281          */
1282
1283         /* Remember normal state */
1284         phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1285         phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1286         phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1287
1288         /* Update radio registers */
1289         ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1290                 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1291
1292         ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1293                         AR5K_PHY_AGCCOARSE_LO)) |
1294                 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1295                 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1296
1297         ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1298                         AR5K_PHY_ADCSAT_THR)) |
1299                 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1300                 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1301
1302         udelay(20);
1303
1304         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1305         udelay(10);
1306         ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1307         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1308
1309         mdelay(1);
1310
1311         /*
1312          * Enable calibration and wait until completion
1313          */
1314         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1315
1316         ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1317                         AR5K_PHY_AGCCTL_CAL, 0, false);
1318
1319         /* Reset to normal state */
1320         ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1321         ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1322         ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1323
1324         if (ret) {
1325                 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1326                                 channel->center_freq);
1327                 return ret;
1328         }
1329
1330         /*
1331          * Re-enable RX/TX and beacons
1332          */
1333         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1334                 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1335         ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1336
1337         return 0;
1338 }
1339
1340 /*
1341  * Perform I/Q calibration on RF5111/5112 and newer chips
1342  */
1343 static int
1344 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1345 {
1346         u32 i_pwr, q_pwr;
1347         s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1348         int i;
1349
1350         if (!ah->ah_calibration ||
1351                 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1352                 return 0;
1353
1354         /* Calibration has finished, get the results and re-run */
1355         /* work around empty results which can apparently happen on 5212 */
1356         for (i = 0; i <= 10; i++) {
1357                 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1358                 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1359                 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1360                 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1361                         "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1362                 if (i_pwr && q_pwr)
1363                         break;
1364         }
1365
1366         i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1367
1368         if (ah->ah_version == AR5K_AR5211)
1369                 q_coffd = q_pwr >> 6;
1370         else
1371                 q_coffd = q_pwr >> 7;
1372
1373         /* protect against divide by 0 and loss of sign bits */
1374         if (i_coffd == 0 || q_coffd < 2)
1375                 return 0;
1376
1377         i_coff = (-iq_corr) / i_coffd;
1378         i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1379
1380         if (ah->ah_version == AR5K_AR5211)
1381                 q_coff = (i_pwr / q_coffd) - 64;
1382         else
1383                 q_coff = (i_pwr / q_coffd) - 128;
1384         q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1385
1386         ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1387                         "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1388                         i_coff, q_coff, i_coffd, q_coffd);
1389
1390         /* Commit new I/Q values (set enable bit last to match HAL sources) */
1391         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1392         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1393         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1394
1395         /* Re-enable calibration -if we don't we'll commit
1396          * the same values again and again */
1397         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1398                         AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1399         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1400
1401         return 0;
1402 }
1403
1404 /*
1405  * Perform a PHY calibration
1406  */
1407 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1408                 struct ieee80211_channel *channel)
1409 {
1410         int ret;
1411
1412         if (ah->ah_radio == AR5K_RF5110)
1413                 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1414         else {
1415                 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1416                 ath5k_hw_request_rfgain_probe(ah);
1417         }
1418
1419         return ret;
1420 }
1421
1422 /***************************\
1423 * Spur mitigation functions *
1424 \***************************/
1425
1426 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1427                                 struct ieee80211_channel *channel)
1428 {
1429         u8 refclk_freq;
1430
1431         if ((ah->ah_radio == AR5K_RF5112) ||
1432         (ah->ah_radio == AR5K_RF5413) ||
1433         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
1434                 refclk_freq = 40;
1435         else
1436                 refclk_freq = 32;
1437
1438         if ((channel->center_freq % refclk_freq != 0) &&
1439         ((channel->center_freq % refclk_freq < 10) ||
1440         (channel->center_freq % refclk_freq > 22)))
1441                 return true;
1442         else
1443                 return false;
1444 }
1445
1446 void
1447 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1448                                 struct ieee80211_channel *channel)
1449 {
1450         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1451         u32 mag_mask[4] = {0, 0, 0, 0};
1452         u32 pilot_mask[2] = {0, 0};
1453         /* Note: fbin values are scaled up by 2 */
1454         u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1455         s32 spur_delta_phase, spur_freq_sigma_delta;
1456         s32 spur_offset, num_symbols_x16;
1457         u8 num_symbol_offsets, i, freq_band;
1458
1459         /* Convert current frequency to fbin value (the same way channels
1460          * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1461          * up by 2 so we can compare it later */
1462         if (channel->hw_value & CHANNEL_2GHZ) {
1463                 chan_fbin = (channel->center_freq - 2300) * 10;
1464                 freq_band = AR5K_EEPROM_BAND_2GHZ;
1465         } else {
1466                 chan_fbin = (channel->center_freq - 4900) * 10;
1467                 freq_band = AR5K_EEPROM_BAND_5GHZ;
1468         }
1469
1470         /* Check if any spur_chan_fbin from EEPROM is
1471          * within our current channel's spur detection range */
1472         spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1473         spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1474         /* XXX: Half/Quarter channels ?*/
1475         if (channel->hw_value & CHANNEL_TURBO)
1476                 spur_detection_window *= 2;
1477
1478         for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1479                 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1480
1481                 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1482                  * so it's zero if we got nothing from EEPROM */
1483                 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1484                         spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1485                         break;
1486                 }
1487
1488                 if ((chan_fbin - spur_detection_window <=
1489                 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1490                 (chan_fbin + spur_detection_window >=
1491                 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1492                         spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1493                         break;
1494                 }
1495         }
1496
1497         /* We need to enable spur filter for this channel */
1498         if (spur_chan_fbin) {
1499                 spur_offset = spur_chan_fbin - chan_fbin;
1500                 /*
1501                  * Calculate deltas:
1502                  * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1503                  * spur_delta_phase -> spur_offset / chip_freq << 11
1504                  * Note: Both values have 100KHz resolution
1505                  */
1506                 /* XXX: Half/Quarter rate channels ? */
1507                 switch (channel->hw_value) {
1508                 case CHANNEL_A:
1509                         /* Both sample_freq and chip_freq are 40MHz */
1510                         spur_delta_phase = (spur_offset << 17) / 25;
1511                         spur_freq_sigma_delta = (spur_delta_phase >> 10);
1512                         symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1513                         break;
1514                 case CHANNEL_G:
1515                         /* sample_freq -> 40MHz chip_freq -> 44MHz
1516                          * (for b compatibility) */
1517                         spur_freq_sigma_delta = (spur_offset << 8) / 55;
1518                         spur_delta_phase = (spur_offset << 17) / 25;
1519                         symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1520                         break;
1521                 case CHANNEL_T:
1522                 case CHANNEL_TG:
1523                         /* Both sample_freq and chip_freq are 80MHz */
1524                         spur_delta_phase = (spur_offset << 16) / 25;
1525                         spur_freq_sigma_delta = (spur_delta_phase >> 10);
1526                         symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1527                         break;
1528                 default:
1529                         return;
1530                 }
1531
1532                 /* Calculate pilot and magnitude masks */
1533
1534                 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1535                  * and divide by symbol_width to find how many symbols we have
1536                  * Note: number of symbols is scaled up by 16 */
1537                 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1538
1539                 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1540                 if (!(num_symbols_x16 & 0xF))
1541                         /* _X_ */
1542                         num_symbol_offsets = 3;
1543                 else
1544                         /* _xx_ */
1545                         num_symbol_offsets = 4;
1546
1547                 for (i = 0; i < num_symbol_offsets; i++) {
1548
1549                         /* Calculate pilot mask */
1550                         s32 curr_sym_off =
1551                                 (num_symbols_x16 / 16) + i + 25;
1552
1553                         /* Pilot magnitude mask seems to be a way to
1554                          * declare the boundaries for our detection
1555                          * window or something, it's 2 for the middle
1556                          * value(s) where the symbol is expected to be
1557                          * and 1 on the boundary values */
1558                         u8 plt_mag_map =
1559                                 (i == 0 || i == (num_symbol_offsets - 1))
1560                                                                 ? 1 : 2;
1561
1562                         if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1563                                 if (curr_sym_off <= 25)
1564                                         pilot_mask[0] |= 1 << curr_sym_off;
1565                                 else if (curr_sym_off >= 27)
1566                                         pilot_mask[0] |= 1 << (curr_sym_off - 1);
1567                         } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1568                                 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1569
1570                         /* Calculate magnitude mask (for viterbi decoder) */
1571                         if (curr_sym_off >= -1 && curr_sym_off <= 14)
1572                                 mag_mask[0] |=
1573                                         plt_mag_map << (curr_sym_off + 1) * 2;
1574                         else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1575                                 mag_mask[1] |=
1576                                         plt_mag_map << (curr_sym_off - 15) * 2;
1577                         else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1578                                 mag_mask[2] |=
1579                                         plt_mag_map << (curr_sym_off - 31) * 2;
1580                         else if (curr_sym_off >= 47 && curr_sym_off <= 53)
1581                                 mag_mask[3] |=
1582                                         plt_mag_map << (curr_sym_off - 47) * 2;
1583
1584                 }
1585
1586                 /* Write settings on hw to enable spur filter */
1587                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1588                                         AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1589                 /* XXX: Self correlator also ? */
1590                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1591                                         AR5K_PHY_IQ_PILOT_MASK_EN |
1592                                         AR5K_PHY_IQ_CHAN_MASK_EN |
1593                                         AR5K_PHY_IQ_SPUR_FILT_EN);
1594
1595                 /* Set delta phase and freq sigma delta */
1596                 ath5k_hw_reg_write(ah,
1597                                 AR5K_REG_SM(spur_delta_phase,
1598                                         AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1599                                 AR5K_REG_SM(spur_freq_sigma_delta,
1600                                 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1601                                 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1602                                 AR5K_PHY_TIMING_11);
1603
1604                 /* Write pilot masks */
1605                 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1606                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1607                                         AR5K_PHY_TIMING_8_PILOT_MASK_2,
1608                                         pilot_mask[1]);
1609
1610                 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1611                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1612                                         AR5K_PHY_TIMING_10_PILOT_MASK_2,
1613                                         pilot_mask[1]);
1614
1615                 /* Write magnitude masks */
1616                 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1617                 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1618                 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1619                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1620                                         AR5K_PHY_BIN_MASK_CTL_MASK_4,
1621                                         mag_mask[3]);
1622
1623                 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1624                 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1625                 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1626                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1627                                         AR5K_PHY_BIN_MASK2_4_MASK_4,
1628                                         mag_mask[3]);
1629
1630         } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1631         AR5K_PHY_IQ_SPUR_FILT_EN) {
1632                 /* Clean up spur mitigation settings and disable fliter */
1633                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1634                                         AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1635                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1636                                         AR5K_PHY_IQ_PILOT_MASK_EN |
1637                                         AR5K_PHY_IQ_CHAN_MASK_EN |
1638                                         AR5K_PHY_IQ_SPUR_FILT_EN);
1639                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1640
1641                 /* Clear pilot masks */
1642                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1643                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1644                                         AR5K_PHY_TIMING_8_PILOT_MASK_2,
1645                                         0);
1646
1647                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1648                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1649                                         AR5K_PHY_TIMING_10_PILOT_MASK_2,
1650                                         0);
1651
1652                 /* Clear magnitude masks */
1653                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1654                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1655                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1656                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1657                                         AR5K_PHY_BIN_MASK_CTL_MASK_4,
1658                                         0);
1659
1660                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1661                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1662                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1663                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1664                                         AR5K_PHY_BIN_MASK2_4_MASK_4,
1665                                         0);
1666         }
1667 }
1668
1669 /********************\
1670   Misc PHY functions
1671 \********************/
1672
1673 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1674 {
1675         /*Just a try M.F.*/
1676         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1677
1678         return 0;
1679 }
1680
1681 /*
1682  * Get the PHY Chip revision
1683  */
1684 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1685 {
1686         unsigned int i;
1687         u32 srev;
1688         u16 ret;
1689
1690         /*
1691          * Set the radio chip access register
1692          */
1693         switch (chan) {
1694         case CHANNEL_2GHZ:
1695                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1696                 break;
1697         case CHANNEL_5GHZ:
1698                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1699                 break;
1700         default:
1701                 return 0;
1702         }
1703
1704         mdelay(2);
1705
1706         /* ...wait until PHY is ready and read the selected radio revision */
1707         ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1708
1709         for (i = 0; i < 8; i++)
1710                 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1711
1712         if (ah->ah_version == AR5K_AR5210) {
1713                 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1714                 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1715         } else {
1716                 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1717                 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1718                                 ((srev & 0x0f) << 4), 8);
1719         }
1720
1721         /* Reset to the 5GHz mode */
1722         ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1723
1724         return ret;
1725 }
1726
1727 /*****************\
1728 * Antenna control *
1729 \*****************/
1730
1731 static void /*TODO:Boundary check*/
1732 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1733 {
1734         if (ah->ah_version != AR5K_AR5210)
1735                 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1736 }
1737
1738 /*
1739  * Enable/disable fast rx antenna diversity
1740  */
1741 static void
1742 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1743 {
1744         switch (ee_mode) {
1745         case AR5K_EEPROM_MODE_11G:
1746                 /* XXX: This is set to
1747                  * disabled on initvals !!! */
1748         case AR5K_EEPROM_MODE_11A:
1749                 if (enable)
1750                         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1751                                         AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1752                 else
1753                         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1754                                         AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1755                 break;
1756         case AR5K_EEPROM_MODE_11B:
1757                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1758                                         AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1759                 break;
1760         default:
1761                 return;
1762         }
1763
1764         if (enable) {
1765                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1766                                 AR5K_PHY_RESTART_DIV_GC, 4);
1767
1768                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1769                                         AR5K_PHY_FAST_ANT_DIV_EN);
1770         } else {
1771                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1772                                 AR5K_PHY_RESTART_DIV_GC, 0);
1773
1774                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1775                                         AR5K_PHY_FAST_ANT_DIV_EN);
1776         }
1777 }
1778
1779 void
1780 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1781 {
1782         u8 ant0, ant1;
1783
1784         /*
1785          * In case a fixed antenna was set as default
1786          * use the same switch table twice.
1787          */
1788         if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1789                 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1790         else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1791                 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1792         else {
1793                 ant0 = AR5K_ANT_SWTABLE_A;
1794                 ant1 = AR5K_ANT_SWTABLE_B;
1795         }
1796
1797         /* Set antenna idle switch table */
1798         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1799                         AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1800                         (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1801                         AR5K_PHY_ANT_CTL_TXRX_EN));
1802
1803         /* Set antenna switch tables */
1804         ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1805                 AR5K_PHY_ANT_SWITCH_TABLE_0);
1806         ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1807                 AR5K_PHY_ANT_SWITCH_TABLE_1);
1808 }
1809
1810 /*
1811  * Set antenna operating mode
1812  */
1813 void
1814 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1815 {
1816         struct ieee80211_channel *channel = ah->ah_current_channel;
1817         bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1818         bool use_def_for_sg;
1819         u8 def_ant, tx_ant, ee_mode;
1820         u32 sta_id1 = 0;
1821
1822         /* if channel is not initialized yet we can't set the antennas
1823          * so just store the mode. it will be set on the next reset */
1824         if (channel == NULL) {
1825                 ah->ah_ant_mode = ant_mode;
1826                 return;
1827         }
1828
1829         def_ant = ah->ah_def_ant;
1830
1831         switch (channel->hw_value & CHANNEL_MODES) {
1832         case CHANNEL_A:
1833         case CHANNEL_T:
1834         case CHANNEL_XR:
1835                 ee_mode = AR5K_EEPROM_MODE_11A;
1836                 break;
1837         case CHANNEL_G:
1838         case CHANNEL_TG:
1839                 ee_mode = AR5K_EEPROM_MODE_11G;
1840                 break;
1841         case CHANNEL_B:
1842                 ee_mode = AR5K_EEPROM_MODE_11B;
1843                 break;
1844         default:
1845                 ATH5K_ERR(ah->ah_sc,
1846                         "invalid channel: %d\n", channel->center_freq);
1847                 return;
1848         }
1849
1850         switch (ant_mode) {
1851         case AR5K_ANTMODE_DEFAULT:
1852                 tx_ant = 0;
1853                 use_def_for_tx = false;
1854                 update_def_on_tx = false;
1855                 use_def_for_rts = false;
1856                 use_def_for_sg = false;
1857                 fast_div = true;
1858                 break;
1859         case AR5K_ANTMODE_FIXED_A:
1860                 def_ant = 1;
1861                 tx_ant = 1;
1862                 use_def_for_tx = true;
1863                 update_def_on_tx = false;
1864                 use_def_for_rts = true;
1865                 use_def_for_sg = true;
1866                 fast_div = false;
1867                 break;
1868         case AR5K_ANTMODE_FIXED_B:
1869                 def_ant = 2;
1870                 tx_ant = 2;
1871                 use_def_for_tx = true;
1872                 update_def_on_tx = false;
1873                 use_def_for_rts = true;
1874                 use_def_for_sg = true;
1875                 fast_div = false;
1876                 break;
1877         case AR5K_ANTMODE_SINGLE_AP:
1878                 def_ant = 1;    /* updated on tx */
1879                 tx_ant = 0;
1880                 use_def_for_tx = true;
1881                 update_def_on_tx = true;
1882                 use_def_for_rts = true;
1883                 use_def_for_sg = true;
1884                 fast_div = true;
1885                 break;
1886         case AR5K_ANTMODE_SECTOR_AP:
1887                 tx_ant = 1;     /* variable */
1888                 use_def_for_tx = false;
1889                 update_def_on_tx = false;
1890                 use_def_for_rts = true;
1891                 use_def_for_sg = false;
1892                 fast_div = false;
1893                 break;
1894         case AR5K_ANTMODE_SECTOR_STA:
1895                 tx_ant = 1;     /* variable */
1896                 use_def_for_tx = true;
1897                 update_def_on_tx = false;
1898                 use_def_for_rts = true;
1899                 use_def_for_sg = false;
1900                 fast_div = true;
1901                 break;
1902         case AR5K_ANTMODE_DEBUG:
1903                 def_ant = 1;
1904                 tx_ant = 2;
1905                 use_def_for_tx = false;
1906                 update_def_on_tx = false;
1907                 use_def_for_rts = false;
1908                 use_def_for_sg = false;
1909                 fast_div = false;
1910                 break;
1911         default:
1912                 return;
1913         }
1914
1915         ah->ah_tx_ant = tx_ant;
1916         ah->ah_ant_mode = ant_mode;
1917         ah->ah_def_ant = def_ant;
1918
1919         sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1920         sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1921         sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1922         sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1923
1924         AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1925
1926         if (sta_id1)
1927                 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1928
1929         ath5k_hw_set_antenna_switch(ah, ee_mode);
1930         /* Note: set diversity before default antenna
1931          * because it won't work correctly */
1932         ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1933         ath5k_hw_set_def_antenna(ah, def_ant);
1934 }
1935
1936
1937 /****************\
1938 * TX power setup *
1939 \****************/
1940
1941 /*
1942  * Helper functions
1943  */
1944
1945 /*
1946  * Do linear interpolation between two given (x, y) points
1947  */
1948 static s16
1949 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1950                                         s16 y_left, s16 y_right)
1951 {
1952         s16 ratio, result;
1953
1954         /* Avoid divide by zero and skip interpolation
1955          * if we have the same point */
1956         if ((x_left == x_right) || (y_left == y_right))
1957                 return y_left;
1958
1959         /*
1960          * Since we use ints and not fps, we need to scale up in
1961          * order to get a sane ratio value (or else we 'll eg. get
1962          * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1963          * to have some accuracy both for 0.5 and 0.25 steps.
1964          */
1965         ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1966
1967         /* Now scale down to be in range */
1968         result = y_left + (ratio * (target - x_left) / 100);
1969
1970         return result;
1971 }
1972
1973 /*
1974  * Find vertical boundary (min pwr) for the linear PCDAC curve.
1975  *
1976  * Since we have the top of the curve and we draw the line below
1977  * until we reach 1 (1 pcdac step) we need to know which point
1978  * (x value) that is so that we don't go below y axis and have negative
1979  * pcdac values when creating the curve, or fill the table with zeroes.
1980  */
1981 static s16
1982 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1983                                 const s16 *pwrL, const s16 *pwrR)
1984 {
1985         s8 tmp;
1986         s16 min_pwrL, min_pwrR;
1987         s16 pwr_i;
1988
1989         /* Some vendors write the same pcdac value twice !!! */
1990         if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
1991                 return max(pwrL[0], pwrR[0]);
1992
1993         if (pwrL[0] == pwrL[1])
1994                 min_pwrL = pwrL[0];
1995         else {
1996                 pwr_i = pwrL[0];
1997                 do {
1998                         pwr_i--;
1999                         tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2000                                                         pwrL[0], pwrL[1],
2001                                                         stepL[0], stepL[1]);
2002                 } while (tmp > 1);
2003
2004                 min_pwrL = pwr_i;
2005         }
2006
2007         if (pwrR[0] == pwrR[1])
2008                 min_pwrR = pwrR[0];
2009         else {
2010                 pwr_i = pwrR[0];
2011                 do {
2012                         pwr_i--;
2013                         tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2014                                                         pwrR[0], pwrR[1],
2015                                                         stepR[0], stepR[1]);
2016                 } while (tmp > 1);
2017
2018                 min_pwrR = pwr_i;
2019         }
2020
2021         /* Keep the right boundary so that it works for both curves */
2022         return max(min_pwrL, min_pwrR);
2023 }
2024
2025 /*
2026  * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2027  * Power to PCDAC curve.
2028  *
2029  * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2030  * steps (offsets) on y axis. Power can go up to 31.5dB and max
2031  * PCDAC/PDADC step for each curve is 64 but we can write more than
2032  * one curves on hw so we can go up to 128 (which is the max step we
2033  * can write on the final table).
2034  *
2035  * We write y values (PCDAC/PDADC steps) on hw.
2036  */
2037 static void
2038 ath5k_create_power_curve(s16 pmin, s16 pmax,
2039                         const s16 *pwr, const u8 *vpd,
2040                         u8 num_points,
2041                         u8 *vpd_table, u8 type)
2042 {
2043         u8 idx[2] = { 0, 1 };
2044         s16 pwr_i = 2*pmin;
2045         int i;
2046
2047         if (num_points < 2)
2048                 return;
2049
2050         /* We want the whole line, so adjust boundaries
2051          * to cover the entire power range. Note that
2052          * power values are already 0.25dB so no need
2053          * to multiply pwr_i by 2 */
2054         if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2055                 pwr_i = pmin;
2056                 pmin = 0;
2057                 pmax = 63;
2058         }
2059
2060         /* Find surrounding turning points (TPs)
2061          * and interpolate between them */
2062         for (i = 0; (i <= (u16) (pmax - pmin)) &&
2063         (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2064
2065                 /* We passed the right TP, move to the next set of TPs
2066                  * if we pass the last TP, extrapolate above using the last
2067                  * two TPs for ratio */
2068                 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2069                         idx[0]++;
2070                         idx[1]++;
2071                 }
2072
2073                 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2074                                                 pwr[idx[0]], pwr[idx[1]],
2075                                                 vpd[idx[0]], vpd[idx[1]]);
2076
2077                 /* Increase by 0.5dB
2078                  * (0.25 dB units) */
2079                 pwr_i += 2;
2080         }
2081 }
2082
2083 /*
2084  * Get the surrounding per-channel power calibration piers
2085  * for a given frequency so that we can interpolate between
2086  * them and come up with an apropriate dataset for our current
2087  * channel.
2088  */
2089 static void
2090 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2091                         struct ieee80211_channel *channel,
2092                         struct ath5k_chan_pcal_info **pcinfo_l,
2093                         struct ath5k_chan_pcal_info **pcinfo_r)
2094 {
2095         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2096         struct ath5k_chan_pcal_info *pcinfo;
2097         u8 idx_l, idx_r;
2098         u8 mode, max, i;
2099         u32 target = channel->center_freq;
2100
2101         idx_l = 0;
2102         idx_r = 0;
2103
2104         if (!(channel->hw_value & CHANNEL_OFDM)) {
2105                 pcinfo = ee->ee_pwr_cal_b;
2106                 mode = AR5K_EEPROM_MODE_11B;
2107         } else if (channel->hw_value & CHANNEL_2GHZ) {
2108                 pcinfo = ee->ee_pwr_cal_g;
2109                 mode = AR5K_EEPROM_MODE_11G;
2110         } else {
2111                 pcinfo = ee->ee_pwr_cal_a;
2112                 mode = AR5K_EEPROM_MODE_11A;
2113         }
2114         max = ee->ee_n_piers[mode] - 1;
2115
2116         /* Frequency is below our calibrated
2117          * range. Use the lowest power curve
2118          * we have */
2119         if (target < pcinfo[0].freq) {
2120                 idx_l = idx_r = 0;
2121                 goto done;
2122         }
2123
2124         /* Frequency is above our calibrated
2125          * range. Use the highest power curve
2126          * we have */
2127         if (target > pcinfo[max].freq) {
2128                 idx_l = idx_r = max;
2129                 goto done;
2130         }
2131
2132         /* Frequency is inside our calibrated
2133          * channel range. Pick the surrounding
2134          * calibration piers so that we can
2135          * interpolate */
2136         for (i = 0; i <= max; i++) {
2137
2138                 /* Frequency matches one of our calibration
2139                  * piers, no need to interpolate, just use
2140                  * that calibration pier */
2141                 if (pcinfo[i].freq == target) {
2142                         idx_l = idx_r = i;
2143                         goto done;
2144                 }
2145
2146                 /* We found a calibration pier that's above
2147                  * frequency, use this pier and the previous
2148                  * one to interpolate */
2149                 if (target < pcinfo[i].freq) {
2150                         idx_r = i;
2151                         idx_l = idx_r - 1;
2152                         goto done;
2153                 }
2154         }
2155
2156 done:
2157         *pcinfo_l = &pcinfo[idx_l];
2158         *pcinfo_r = &pcinfo[idx_r];
2159 }
2160
2161 /*
2162  * Get the surrounding per-rate power calibration data
2163  * for a given frequency and interpolate between power
2164  * values to set max target power supported by hw for
2165  * each rate.
2166  */
2167 static void
2168 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2169                         struct ieee80211_channel *channel,
2170                         struct ath5k_rate_pcal_info *rates)
2171 {
2172         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2173         struct ath5k_rate_pcal_info *rpinfo;
2174         u8 idx_l, idx_r;
2175         u8 mode, max, i;
2176         u32 target = channel->center_freq;
2177
2178         idx_l = 0;
2179         idx_r = 0;
2180
2181         if (!(channel->hw_value & CHANNEL_OFDM)) {
2182                 rpinfo = ee->ee_rate_tpwr_b;
2183                 mode = AR5K_EEPROM_MODE_11B;
2184         } else if (channel->hw_value & CHANNEL_2GHZ) {
2185                 rpinfo = ee->ee_rate_tpwr_g;
2186                 mode = AR5K_EEPROM_MODE_11G;
2187         } else {
2188                 rpinfo = ee->ee_rate_tpwr_a;
2189                 mode = AR5K_EEPROM_MODE_11A;
2190         }
2191         max = ee->ee_rate_target_pwr_num[mode] - 1;
2192
2193         /* Get the surrounding calibration
2194          * piers - same as above */
2195         if (target < rpinfo[0].freq) {
2196                 idx_l = idx_r = 0;
2197                 goto done;
2198         }
2199
2200         if (target > rpinfo[max].freq) {
2201                 idx_l = idx_r = max;
2202                 goto done;
2203         }
2204
2205         for (i = 0; i <= max; i++) {
2206
2207                 if (rpinfo[i].freq == target) {
2208                         idx_l = idx_r = i;
2209                         goto done;
2210                 }
2211
2212                 if (target < rpinfo[i].freq) {
2213                         idx_r = i;
2214                         idx_l = idx_r - 1;
2215                         goto done;
2216                 }
2217         }
2218
2219 done:
2220         /* Now interpolate power value, based on the frequency */
2221         rates->freq = target;
2222
2223         rates->target_power_6to24 =
2224                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2225                                         rpinfo[idx_r].freq,
2226                                         rpinfo[idx_l].target_power_6to24,
2227                                         rpinfo[idx_r].target_power_6to24);
2228
2229         rates->target_power_36 =
2230                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2231                                         rpinfo[idx_r].freq,
2232                                         rpinfo[idx_l].target_power_36,
2233                                         rpinfo[idx_r].target_power_36);
2234
2235         rates->target_power_48 =
2236                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2237                                         rpinfo[idx_r].freq,
2238                                         rpinfo[idx_l].target_power_48,
2239                                         rpinfo[idx_r].target_power_48);
2240
2241         rates->target_power_54 =
2242                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2243                                         rpinfo[idx_r].freq,
2244                                         rpinfo[idx_l].target_power_54,
2245                                         rpinfo[idx_r].target_power_54);
2246 }
2247
2248 /*
2249  * Get the max edge power for this channel if
2250  * we have such data from EEPROM's Conformance Test
2251  * Limits (CTL), and limit max power if needed.
2252  */
2253 static void
2254 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2255                         struct ieee80211_channel *channel)
2256 {
2257         struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2258         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2259         struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2260         u8 *ctl_val = ee->ee_ctl;
2261         s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2262         s16 edge_pwr = 0;
2263         u8 rep_idx;
2264         u8 i, ctl_mode;
2265         u8 ctl_idx = 0xFF;
2266         u32 target = channel->center_freq;
2267
2268         ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2269
2270         switch (channel->hw_value & CHANNEL_MODES) {
2271         case CHANNEL_A:
2272                 ctl_mode |= AR5K_CTL_11A;
2273                 break;
2274         case CHANNEL_G:
2275                 ctl_mode |= AR5K_CTL_11G;
2276                 break;
2277         case CHANNEL_B:
2278                 ctl_mode |= AR5K_CTL_11B;
2279                 break;
2280         case CHANNEL_T:
2281                 ctl_mode |= AR5K_CTL_TURBO;
2282                 break;
2283         case CHANNEL_TG:
2284                 ctl_mode |= AR5K_CTL_TURBOG;
2285                 break;
2286         case CHANNEL_XR:
2287                 /* Fall through */
2288         default:
2289                 return;
2290         }
2291
2292         for (i = 0; i < ee->ee_ctls; i++) {
2293                 if (ctl_val[i] == ctl_mode) {
2294                         ctl_idx = i;
2295                         break;
2296                 }
2297         }
2298
2299         /* If we have a CTL dataset available grab it and find the
2300          * edge power for our frequency */
2301         if (ctl_idx == 0xFF)
2302                 return;
2303
2304         /* Edge powers are sorted by frequency from lower
2305          * to higher. Each CTL corresponds to 8 edge power
2306          * measurements. */
2307         rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2308
2309         /* Don't do boundaries check because we
2310          * might have more that one bands defined
2311          * for this mode */
2312
2313         /* Get the edge power that's closer to our
2314          * frequency */
2315         for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2316                 rep_idx += i;
2317                 if (target <= rep[rep_idx].freq)
2318                         edge_pwr = (s16) rep[rep_idx].edge;
2319         }
2320
2321         if (edge_pwr)
2322                 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2323 }
2324
2325
2326 /*
2327  * Power to PCDAC table functions
2328  */
2329
2330 /*
2331  * Fill Power to PCDAC table on RF5111
2332  *
2333  * No further processing is needed for RF5111, the only thing we have to
2334  * do is fill the values below and above calibration range since eeprom data
2335  * may not cover the entire PCDAC table.
2336  */
2337 static void
2338 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2339                                                         s16 *table_max)
2340 {
2341         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
2342         u8      *pcdac_tmp = ah->ah_txpower.tmpL[0];
2343         u8      pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2344         s16     min_pwr, max_pwr;
2345
2346         /* Get table boundaries */
2347         min_pwr = table_min[0];
2348         pcdac_0 = pcdac_tmp[0];
2349
2350         max_pwr = table_max[0];
2351         pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2352
2353         /* Extrapolate below minimum using pcdac_0 */
2354         pcdac_i = 0;
2355         for (i = 0; i < min_pwr; i++)
2356                 pcdac_out[pcdac_i++] = pcdac_0;
2357
2358         /* Copy values from pcdac_tmp */
2359         pwr_idx = min_pwr;
2360         for (i = 0 ; pwr_idx <= max_pwr &&
2361         pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2362                 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2363                 pwr_idx++;
2364         }
2365
2366         /* Extrapolate above maximum */
2367         while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2368                 pcdac_out[pcdac_i++] = pcdac_n;
2369
2370 }
2371
2372 /*
2373  * Combine available XPD Curves and fill Linear Power to PCDAC table
2374  * on RF5112
2375  *
2376  * RFX112 can have up to 2 curves (one for low txpower range and one for
2377  * higher txpower range). We need to put them both on pcdac_out and place
2378  * them in the correct location. In case we only have one curve available
2379  * just fit it on pcdac_out (it's supposed to cover the entire range of
2380  * available pwr levels since it's always the higher power curve). Extrapolate
2381  * below and above final table if needed.
2382  */
2383 static void
2384 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2385                                                 s16 *table_max, u8 pdcurves)
2386 {
2387         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
2388         u8      *pcdac_low_pwr;
2389         u8      *pcdac_high_pwr;
2390         u8      *pcdac_tmp;
2391         u8      pwr;
2392         s16     max_pwr_idx;
2393         s16     min_pwr_idx;
2394         s16     mid_pwr_idx = 0;
2395         /* Edge flag turs on the 7nth bit on the PCDAC
2396          * to delcare the higher power curve (force values
2397          * to be greater than 64). If we only have one curve
2398          * we don't need to set this, if we have 2 curves and
2399          * fill the table backwards this can also be used to
2400          * switch from higher power curve to lower power curve */
2401         u8      edge_flag;
2402         int     i;
2403
2404         /* When we have only one curve available
2405          * that's the higher power curve. If we have
2406          * two curves the first is the high power curve
2407          * and the next is the low power curve. */
2408         if (pdcurves > 1) {
2409                 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2410                 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2411                 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2412                 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2413
2414                 /* If table size goes beyond 31.5dB, keep the
2415                  * upper 31.5dB range when setting tx power.
2416                  * Note: 126 = 31.5 dB in quarter dB steps */
2417                 if (table_max[0] - table_min[1] > 126)
2418                         min_pwr_idx = table_max[0] - 126;
2419                 else
2420                         min_pwr_idx = table_min[1];
2421
2422                 /* Since we fill table backwards
2423                  * start from high power curve */
2424                 pcdac_tmp = pcdac_high_pwr;
2425
2426                 edge_flag = 0x40;
2427         } else {
2428                 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2429                 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2430                 min_pwr_idx = table_min[0];
2431                 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2432                 pcdac_tmp = pcdac_high_pwr;
2433                 edge_flag = 0;
2434         }
2435
2436         /* This is used when setting tx power*/
2437         ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2438
2439         /* Fill Power to PCDAC table backwards */
2440         pwr = max_pwr_idx;
2441         for (i = 63; i >= 0; i--) {
2442                 /* Entering lower power range, reset
2443                  * edge flag and set pcdac_tmp to lower
2444                  * power curve.*/
2445                 if (edge_flag == 0x40 &&
2446                 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2447                         edge_flag = 0x00;
2448                         pcdac_tmp = pcdac_low_pwr;
2449                         pwr = mid_pwr_idx/2;
2450                 }
2451
2452                 /* Don't go below 1, extrapolate below if we have
2453                  * already swithced to the lower power curve -or
2454                  * we only have one curve and edge_flag is zero
2455                  * anyway */
2456                 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2457                         while (i >= 0) {
2458                                 pcdac_out[i] = pcdac_out[i + 1];
2459                                 i--;
2460                         }
2461                         break;
2462                 }
2463
2464                 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2465
2466                 /* Extrapolate above if pcdac is greater than
2467                  * 126 -this can happen because we OR pcdac_out
2468                  * value with edge_flag on high power curve */
2469                 if (pcdac_out[i] > 126)
2470                         pcdac_out[i] = 126;
2471
2472                 /* Decrease by a 0.5dB step */
2473                 pwr--;
2474         }
2475 }
2476
2477 /* Write PCDAC values on hw */
2478 static void
2479 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2480 {
2481         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
2482         int     i;
2483
2484         /*
2485          * Write TX power values
2486          */
2487         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2488                 ath5k_hw_reg_write(ah,
2489                         (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2490                         (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2491                         AR5K_PHY_PCDAC_TXPOWER(i));
2492         }
2493 }
2494
2495
2496 /*
2497  * Power to PDADC table functions
2498  */
2499
2500 /*
2501  * Set the gain boundaries and create final Power to PDADC table
2502  *
2503  * We can have up to 4 pd curves, we need to do a simmilar process
2504  * as we do for RF5112. This time we don't have an edge_flag but we
2505  * set the gain boundaries on a separate register.
2506  */
2507 static void
2508 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2509                         s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2510 {
2511         u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2512         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2513         u8 *pdadc_tmp;
2514         s16 pdadc_0;
2515         u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2516         u8 pd_gain_overlap;
2517
2518         /* Note: Register value is initialized on initvals
2519          * there is no feedback from hw.
2520          * XXX: What about pd_gain_overlap from EEPROM ? */
2521         pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2522                 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2523
2524         /* Create final PDADC table */
2525         for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2526                 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2527
2528                 if (pdg == pdcurves - 1)
2529                         /* 2 dB boundary stretch for last
2530                          * (higher power) curve */
2531                         gain_boundaries[pdg] = pwr_max[pdg] + 4;
2532                 else
2533                         /* Set gain boundary in the middle
2534                          * between this curve and the next one */
2535                         gain_boundaries[pdg] =
2536                                 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2537
2538                 /* Sanity check in case our 2 db stretch got out of
2539                  * range. */
2540                 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2541                         gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2542
2543                 /* For the first curve (lower power)
2544                  * start from 0 dB */
2545                 if (pdg == 0)
2546                         pdadc_0 = 0;
2547                 else
2548                         /* For the other curves use the gain overlap */
2549                         pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2550                                                         pd_gain_overlap;
2551
2552                 /* Force each power step to be at least 0.5 dB */
2553                 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2554                         pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2555                 else
2556                         pwr_step = 1;
2557
2558                 /* If pdadc_0 is negative, we need to extrapolate
2559                  * below this pdgain by a number of pwr_steps */
2560                 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2561                         s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2562                         pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2563                         pdadc_0++;
2564                 }
2565
2566                 /* Set last pwr level, using gain boundaries */
2567                 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2568                 /* Limit it to be inside pwr range */
2569                 table_size = pwr_max[pdg] - pwr_min[pdg];
2570                 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2571
2572                 /* Fill pdadc_out table */
2573                 while (pdadc_0 < max_idx && pdadc_i < 128)
2574                         pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2575
2576                 /* Need to extrapolate above this pdgain? */
2577                 if (pdadc_n <= max_idx)
2578                         continue;
2579
2580                 /* Force each power step to be at least 0.5 dB */
2581                 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2582                         pwr_step = pdadc_tmp[table_size - 1] -
2583                                                 pdadc_tmp[table_size - 2];
2584                 else
2585                         pwr_step = 1;
2586
2587                 /* Extrapolate above */
2588                 while ((pdadc_0 < (s16) pdadc_n) &&
2589                 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2590                         s16 tmp = pdadc_tmp[table_size - 1] +
2591                                         (pdadc_0 - max_idx) * pwr_step;
2592                         pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2593                         pdadc_0++;
2594                 }
2595         }
2596
2597         while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2598                 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2599                 pdg++;
2600         }
2601
2602         while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2603                 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2604                 pdadc_i++;
2605         }
2606
2607         /* Set gain boundaries */
2608         ath5k_hw_reg_write(ah,
2609                 AR5K_REG_SM(pd_gain_overlap,
2610                         AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2611                 AR5K_REG_SM(gain_boundaries[0],
2612                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2613                 AR5K_REG_SM(gain_boundaries[1],
2614                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2615                 AR5K_REG_SM(gain_boundaries[2],
2616                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2617                 AR5K_REG_SM(gain_boundaries[3],
2618                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2619                 AR5K_PHY_TPC_RG5);
2620
2621         /* Used for setting rate power table */
2622         ah->ah_txpower.txp_min_idx = pwr_min[0];
2623
2624 }
2625
2626 /* Write PDADC values on hw */
2627 static void
2628 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2629                         u8 pdcurves, u8 *pdg_to_idx)
2630 {
2631         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2632         u32 reg;
2633         u8 i;
2634
2635         /* Select the right pdgain curves */
2636
2637         /* Clear current settings */
2638         reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2639         reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2640                 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2641                 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2642                 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2643
2644         /*
2645          * Use pd_gains curve from eeprom
2646          *
2647          * This overrides the default setting from initvals
2648          * in case some vendors (e.g. Zcomax) don't use the default
2649          * curves. If we don't honor their settings we 'll get a
2650          * 5dB (1 * gain overlap ?) drop.
2651          */
2652         reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2653
2654         switch (pdcurves) {
2655         case 3:
2656                 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2657                 /* Fall through */
2658         case 2:
2659                 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2660                 /* Fall through */
2661         case 1:
2662                 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2663                 break;
2664         }
2665         ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2666
2667         /*
2668          * Write TX power values
2669          */
2670         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2671                 ath5k_hw_reg_write(ah,
2672                         ((pdadc_out[4*i + 0] & 0xff) << 0) |
2673                         ((pdadc_out[4*i + 1] & 0xff) << 8) |
2674                         ((pdadc_out[4*i + 2] & 0xff) << 16) |
2675                         ((pdadc_out[4*i + 3] & 0xff) << 24),
2676                         AR5K_PHY_PDADC_TXPOWER(i));
2677         }
2678 }
2679
2680
2681 /*
2682  * Common code for PCDAC/PDADC tables
2683  */
2684
2685 /*
2686  * This is the main function that uses all of the above
2687  * to set PCDAC/PDADC table on hw for the current channel.
2688  * This table is used for tx power calibration on the basband,
2689  * without it we get weird tx power levels and in some cases
2690  * distorted spectral mask
2691  */
2692 static int
2693 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2694                         struct ieee80211_channel *channel,
2695                         u8 ee_mode, u8 type)
2696 {
2697         struct ath5k_pdgain_info *pdg_L, *pdg_R;
2698         struct ath5k_chan_pcal_info *pcinfo_L;
2699         struct ath5k_chan_pcal_info *pcinfo_R;
2700         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2701         u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2702         s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2703         s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2704         u8 *tmpL;
2705         u8 *tmpR;
2706         u32 target = channel->center_freq;
2707         int pdg, i;
2708
2709         /* Get surounding freq piers for this channel */
2710         ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2711                                                 &pcinfo_L,
2712                                                 &pcinfo_R);
2713
2714         /* Loop over pd gain curves on
2715          * surounding freq piers by index */
2716         for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2717
2718                 /* Fill curves in reverse order
2719                  * from lower power (max gain)
2720                  * to higher power. Use curve -> idx
2721                  * backmapping we did on eeprom init */
2722                 u8 idx = pdg_curve_to_idx[pdg];
2723
2724                 /* Grab the needed curves by index */
2725                 pdg_L = &pcinfo_L->pd_curves[idx];
2726                 pdg_R = &pcinfo_R->pd_curves[idx];
2727
2728                 /* Initialize the temp tables */
2729                 tmpL = ah->ah_txpower.tmpL[pdg];
2730                 tmpR = ah->ah_txpower.tmpR[pdg];
2731
2732                 /* Set curve's x boundaries and create
2733                  * curves so that they cover the same
2734                  * range (if we don't do that one table
2735                  * will have values on some range and the
2736                  * other one won't have any so interpolation
2737                  * will fail) */
2738                 table_min[pdg] = min(pdg_L->pd_pwr[0],
2739                                         pdg_R->pd_pwr[0]) / 2;
2740
2741                 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2742                                 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2743
2744                 /* Now create the curves on surrounding channels
2745                  * and interpolate if needed to get the final
2746                  * curve for this gain on this channel */
2747                 switch (type) {
2748                 case AR5K_PWRTABLE_LINEAR_PCDAC:
2749                         /* Override min/max so that we don't loose
2750                          * accuracy (don't divide by 2) */
2751                         table_min[pdg] = min(pdg_L->pd_pwr[0],
2752                                                 pdg_R->pd_pwr[0]);
2753
2754                         table_max[pdg] =
2755                                 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2756                                         pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2757
2758                         /* Override minimum so that we don't get
2759                          * out of bounds while extrapolating
2760                          * below. Don't do this when we have 2
2761                          * curves and we are on the high power curve
2762                          * because table_min is ok in this case */
2763                         if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2764
2765                                 table_min[pdg] =
2766                                         ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2767                                                                 pdg_R->pd_step,
2768                                                                 pdg_L->pd_pwr,
2769                                                                 pdg_R->pd_pwr);
2770
2771                                 /* Don't go too low because we will
2772                                  * miss the upper part of the curve.
2773                                  * Note: 126 = 31.5dB (max power supported)
2774                                  * in 0.25dB units */
2775                                 if (table_max[pdg] - table_min[pdg] > 126)
2776                                         table_min[pdg] = table_max[pdg] - 126;
2777                         }
2778
2779                         /* Fall through */
2780                 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2781                 case AR5K_PWRTABLE_PWR_TO_PDADC:
2782
2783                         ath5k_create_power_curve(table_min[pdg],
2784                                                 table_max[pdg],
2785                                                 pdg_L->pd_pwr,
2786                                                 pdg_L->pd_step,
2787                                                 pdg_L->pd_points, tmpL, type);
2788
2789                         /* We are in a calibration
2790                          * pier, no need to interpolate
2791                          * between freq piers */
2792                         if (pcinfo_L == pcinfo_R)
2793                                 continue;
2794
2795                         ath5k_create_power_curve(table_min[pdg],
2796                                                 table_max[pdg],
2797                                                 pdg_R->pd_pwr,
2798                                                 pdg_R->pd_step,
2799                                                 pdg_R->pd_points, tmpR, type);
2800                         break;
2801                 default:
2802                         return -EINVAL;
2803                 }
2804
2805                 /* Interpolate between curves
2806                  * of surounding freq piers to
2807                  * get the final curve for this
2808                  * pd gain. Re-use tmpL for interpolation
2809                  * output */
2810                 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2811                 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2812                         tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2813                                                         (s16) pcinfo_L->freq,
2814                                                         (s16) pcinfo_R->freq,
2815                                                         (s16) tmpL[i],
2816                                                         (s16) tmpR[i]);
2817                 }
2818         }
2819
2820         /* Now we have a set of curves for this
2821          * channel on tmpL (x range is table_max - table_min
2822          * and y values are tmpL[pdg][]) sorted in the same
2823          * order as EEPROM (because we've used the backmapping).
2824          * So for RF5112 it's from higher power to lower power
2825          * and for RF2413 it's from lower power to higher power.
2826          * For RF5111 we only have one curve. */
2827
2828         /* Fill min and max power levels for this
2829          * channel by interpolating the values on
2830          * surounding channels to complete the dataset */
2831         ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2832                                         (s16) pcinfo_L->freq,
2833                                         (s16) pcinfo_R->freq,
2834                                         pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2835
2836         ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2837                                         (s16) pcinfo_L->freq,
2838                                         (s16) pcinfo_R->freq,
2839                                         pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2840
2841         /* We are ready to go, fill PCDAC/PDADC
2842          * table and write settings on hardware */
2843         switch (type) {
2844         case AR5K_PWRTABLE_LINEAR_PCDAC:
2845                 /* For RF5112 we can have one or two curves
2846                  * and each curve covers a certain power lvl
2847                  * range so we need to do some more processing */
2848                 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2849                                                 ee->ee_pd_gains[ee_mode]);
2850
2851                 /* Set txp.offset so that we can
2852                  * match max power value with max
2853                  * table index */
2854                 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2855
2856                 /* Write settings on hw */
2857                 ath5k_setup_pcdac_table(ah);
2858                 break;
2859         case AR5K_PWRTABLE_PWR_TO_PCDAC:
2860                 /* We are done for RF5111 since it has only
2861                  * one curve, just fit the curve on the table */
2862                 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2863
2864                 /* No rate powertable adjustment for RF5111 */
2865                 ah->ah_txpower.txp_min_idx = 0;
2866                 ah->ah_txpower.txp_offset = 0;
2867
2868                 /* Write settings on hw */
2869                 ath5k_setup_pcdac_table(ah);
2870                 break;
2871         case AR5K_PWRTABLE_PWR_TO_PDADC:
2872                 /* Set PDADC boundaries and fill
2873                  * final PDADC table */
2874                 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2875                                                 ee->ee_pd_gains[ee_mode]);
2876
2877                 /* Write settings on hw */
2878                 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2879
2880                 /* Set txp.offset, note that table_min
2881                  * can be negative */
2882                 ah->ah_txpower.txp_offset = table_min[0];
2883                 break;
2884         default:
2885                 return -EINVAL;
2886         }
2887
2888         return 0;
2889 }
2890
2891
2892 /*
2893  * Per-rate tx power setting
2894  *
2895  * This is the code that sets the desired tx power (below
2896  * maximum) on hw for each rate (we also have TPC that sets
2897  * power per packet). We do that by providing an index on the
2898  * PCDAC/PDADC table we set up.
2899  */
2900
2901 /*
2902  * Set rate power table
2903  *
2904  * For now we only limit txpower based on maximum tx power
2905  * supported by hw (what's inside rate_info). We need to limit
2906  * this even more, based on regulatory domain etc.
2907  *
2908  * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2909  * and is indexed as follows:
2910  * rates[0] - rates[7] -> OFDM rates
2911  * rates[8] - rates[14] -> CCK rates
2912  * rates[15] -> XR rates (they all have the same power)
2913  */
2914 static void
2915 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2916                         struct ath5k_rate_pcal_info *rate_info,
2917                         u8 ee_mode)
2918 {
2919         unsigned int i;
2920         u16 *rates;
2921
2922         /* max_pwr is power level we got from driver/user in 0.5dB
2923          * units, switch to 0.25dB units so we can compare */
2924         max_pwr *= 2;
2925         max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2926
2927         /* apply rate limits */
2928         rates = ah->ah_txpower.txp_rates_power_table;
2929
2930         /* OFDM rates 6 to 24Mb/s */
2931         for (i = 0; i < 5; i++)
2932                 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2933
2934         /* Rest OFDM rates */
2935         rates[5] = min(rates[0], rate_info->target_power_36);
2936         rates[6] = min(rates[0], rate_info->target_power_48);
2937         rates[7] = min(rates[0], rate_info->target_power_54);
2938
2939         /* CCK rates */
2940         /* 1L */
2941         rates[8] = min(rates[0], rate_info->target_power_6to24);
2942         /* 2L */
2943         rates[9] = min(rates[0], rate_info->target_power_36);
2944         /* 2S */
2945         rates[10] = min(rates[0], rate_info->target_power_36);
2946         /* 5L */
2947         rates[11] = min(rates[0], rate_info->target_power_48);
2948         /* 5S */
2949         rates[12] = min(rates[0], rate_info->target_power_48);
2950         /* 11L */
2951         rates[13] = min(rates[0], rate_info->target_power_54);
2952         /* 11S */
2953         rates[14] = min(rates[0], rate_info->target_power_54);
2954
2955         /* XR rates */
2956         rates[15] = min(rates[0], rate_info->target_power_6to24);
2957
2958         /* CCK rates have different peak to average ratio
2959          * so we have to tweak their power so that gainf
2960          * correction works ok. For this we use OFDM to
2961          * CCK delta from eeprom */
2962         if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2963         (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2964                 for (i = 8; i <= 15; i++)
2965                         rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2966
2967         /* Now that we have all rates setup use table offset to
2968          * match the power range set by user with the power indices
2969          * on PCDAC/PDADC table */
2970         for (i = 0; i < 16; i++) {
2971                 rates[i] += ah->ah_txpower.txp_offset;
2972                 /* Don't get out of bounds */
2973                 if (rates[i] > 63)
2974                         rates[i] = 63;
2975         }
2976
2977         /* Min/max in 0.25dB units */
2978         ah->ah_txpower.txp_min_pwr = 2 * rates[7];
2979         ah->ah_txpower.txp_max_pwr = 2 * rates[0];
2980         ah->ah_txpower.txp_ofdm = rates[7];
2981 }
2982
2983
2984 /*
2985  * Set transmission power
2986  */
2987 int
2988 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2989                 u8 ee_mode, u8 txpower)
2990 {
2991         struct ath5k_rate_pcal_info rate_info;
2992         u8 type;
2993         int ret;
2994
2995         if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2996                 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2997                 return -EINVAL;
2998         }
2999
3000         /* Reset TX power values */
3001         memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3002         ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3003         ah->ah_txpower.txp_min_pwr = 0;
3004         ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3005
3006         /* Initialize TX power table */
3007         switch (ah->ah_radio) {
3008         case AR5K_RF5111:
3009                 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3010                 break;
3011         case AR5K_RF5112:
3012                 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3013                 break;
3014         case AR5K_RF2413:
3015         case AR5K_RF5413:
3016         case AR5K_RF2316:
3017         case AR5K_RF2317:
3018         case AR5K_RF2425:
3019                 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3020                 break;
3021         default:
3022                 return -EINVAL;
3023         }
3024
3025         /* FIXME: Only on channel/mode change */
3026         ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
3027         if (ret)
3028                 return ret;
3029
3030         /* Limit max power if we have a CTL available */
3031         ath5k_get_max_ctl_power(ah, channel);
3032
3033         /* FIXME: Antenna reduction stuff */
3034
3035         /* FIXME: Limit power on turbo modes */
3036
3037         /* FIXME: TPC scale reduction */
3038
3039         /* Get surounding channels for per-rate power table
3040          * calibration */
3041         ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3042
3043         /* Setup rate power table */
3044         ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3045
3046         /* Write rate power table on hw */
3047         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3048                 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3049                 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3050
3051         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3052                 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3053                 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3054
3055         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3056                 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3057                 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3058
3059         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3060                 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3061                 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3062
3063         /* FIXME: TPC support */
3064         if (ah->ah_txpower.txp_tpc) {
3065                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3066                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3067
3068                 ath5k_hw_reg_write(ah,
3069                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3070                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3071                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3072                         AR5K_TPC);
3073         } else {
3074                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3075                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3076         }
3077
3078         return 0;
3079 }
3080
3081 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3082 {
3083         /*Just a try M.F.*/
3084         struct ieee80211_channel *channel = ah->ah_current_channel;
3085         u8 ee_mode;
3086
3087         switch (channel->hw_value & CHANNEL_MODES) {
3088         case CHANNEL_A:
3089         case CHANNEL_T:
3090         case CHANNEL_XR:
3091                 ee_mode = AR5K_EEPROM_MODE_11A;
3092                 break;
3093         case CHANNEL_G:
3094         case CHANNEL_TG:
3095                 ee_mode = AR5K_EEPROM_MODE_11G;
3096                 break;
3097         case CHANNEL_B:
3098                 ee_mode = AR5K_EEPROM_MODE_11B;
3099                 break;
3100         default:
3101                 ATH5K_ERR(ah->ah_sc,
3102                         "invalid channel: %d\n", channel->center_freq);
3103                 return -EINVAL;
3104         }
3105
3106         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3107                 "changing txpower to %d\n", txpower);
3108
3109         return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
3110 }