2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/kernel.h>
21 struct ani_ofdm_level_entry {
22 int spur_immunity_level;
24 int ofdm_weak_signal_on;
27 /* values here are relative to the INI */
34 * WS: OFDM / CCK Weak Signal detection
35 * MRC-CCK: Maximal Ratio Combining for CCK
38 static const struct ani_ofdm_level_entry ofdm_level_table[] = {
40 { 0, 0, 1 }, /* lvl 0 */
41 { 1, 1, 1 }, /* lvl 1 */
42 { 2, 2, 1 }, /* lvl 2 */
43 { 3, 2, 1 }, /* lvl 3 (default) */
44 { 4, 3, 1 }, /* lvl 4 */
45 { 5, 4, 1 }, /* lvl 5 */
46 { 6, 5, 1 }, /* lvl 6 */
47 { 7, 6, 1 }, /* lvl 7 */
48 { 7, 7, 1 }, /* lvl 8 */
49 { 7, 8, 0 } /* lvl 9 */
51 #define ATH9K_ANI_OFDM_NUM_LEVEL \
52 ARRAY_SIZE(ofdm_level_table)
53 #define ATH9K_ANI_OFDM_MAX_LEVEL \
54 (ATH9K_ANI_OFDM_NUM_LEVEL-1)
55 #define ATH9K_ANI_OFDM_DEF_LEVEL \
56 3 /* default level - matches the INI settings */
59 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
60 * With OFDM for single stream you just add up all antenna inputs, you're
61 * only interested in what you get after FFT. Signal aligment is also not
62 * required for OFDM because any phase difference adds up in the frequency
65 * MRC requires extra work for use with CCK. You need to align the antenna
66 * signals from the different antenna before you can add the signals together.
67 * You need aligment of signals as CCK is in time domain, so addition can cancel
68 * your signal completely if phase is 180 degrees (think of adding sine waves).
69 * You also need to remove noise before the addition and this is where ANI
70 * MRC CCK comes into play. One of the antenna inputs may be stronger but
71 * lower SNR, so just adding after alignment can be dangerous.
73 * Regardless of alignment in time, the antenna signals add constructively after
74 * FFT and improve your reception. For more information:
76 * http://en.wikipedia.org/wiki/Maximal-ratio_combining
79 struct ani_cck_level_entry {
84 static const struct ani_cck_level_entry cck_level_table[] = {
88 { 2, 1 }, /* lvl 2 (default) */
93 { 7, 0 }, /* lvl 7 (only for high rssi) */
94 { 8, 0 } /* lvl 8 (only for high rssi) */
97 #define ATH9K_ANI_CCK_NUM_LEVEL \
98 ARRAY_SIZE(cck_level_table)
99 #define ATH9K_ANI_CCK_MAX_LEVEL \
100 (ATH9K_ANI_CCK_NUM_LEVEL-1)
101 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
102 (ATH9K_ANI_CCK_NUM_LEVEL-3)
103 #define ATH9K_ANI_CCK_DEF_LEVEL \
104 2 /* default level - matches the INI settings */
106 static bool use_new_ani(struct ath_hw *ah)
108 return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani;
111 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
112 struct ath9k_mib_stats *stats)
114 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
115 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
116 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
117 stats->rts_good += REG_READ(ah, AR_RTS_OK);
118 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
121 static void ath9k_ani_restart(struct ath_hw *ah)
123 struct ar5416AniState *aniState;
124 struct ath_common *common = ath9k_hw_common(ah);
125 u32 ofdm_base = 0, cck_base = 0;
130 aniState = &ah->curchan->ani;
131 aniState->listenTime = 0;
133 if (!use_new_ani(ah)) {
134 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
135 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
138 ath_print(common, ATH_DBG_ANI,
139 "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base);
141 ENABLE_REGWRITE_BUFFER(ah);
143 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
144 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
145 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
146 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
148 REGWRITE_BUFFER_FLUSH(ah);
150 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
152 aniState->ofdmPhyErrCount = 0;
153 aniState->cckPhyErrCount = 0;
156 static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
158 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
159 struct ar5416AniState *aniState;
162 aniState = &ah->curchan->ani;
164 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
165 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
166 aniState->noiseImmunityLevel + 1)) {
171 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
172 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
173 aniState->spurImmunityLevel + 1)) {
178 if (ah->opmode == NL80211_IFTYPE_AP) {
179 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
180 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
181 aniState->firstepLevel + 1);
185 rssi = BEACON_RSSI(ah);
186 if (rssi > aniState->rssiThrHigh) {
187 if (!aniState->ofdmWeakSigDetectOff) {
188 if (ath9k_hw_ani_control(ah,
189 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
191 ath9k_hw_ani_control(ah,
192 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
196 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
197 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
198 aniState->firstepLevel + 1);
201 } else if (rssi > aniState->rssiThrLow) {
202 if (aniState->ofdmWeakSigDetectOff)
203 ath9k_hw_ani_control(ah,
204 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
206 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
207 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
208 aniState->firstepLevel + 1);
211 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
213 if (!aniState->ofdmWeakSigDetectOff)
214 ath9k_hw_ani_control(ah,
215 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
217 if (aniState->firstepLevel > 0)
218 ath9k_hw_ani_control(ah,
219 ATH9K_ANI_FIRSTEP_LEVEL, 0);
225 static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
227 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
228 struct ar5416AniState *aniState;
231 aniState = &ah->curchan->ani;
232 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
233 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
234 aniState->noiseImmunityLevel + 1)) {
238 if (ah->opmode == NL80211_IFTYPE_AP) {
239 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
240 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
241 aniState->firstepLevel + 1);
245 rssi = BEACON_RSSI(ah);
246 if (rssi > aniState->rssiThrLow) {
247 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
248 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
249 aniState->firstepLevel + 1);
251 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
253 if (aniState->firstepLevel > 0)
254 ath9k_hw_ani_control(ah,
255 ATH9K_ANI_FIRSTEP_LEVEL, 0);
260 /* Adjust the OFDM Noise Immunity Level */
261 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
263 struct ar5416AniState *aniState = &ah->curchan->ani;
264 struct ath_common *common = ath9k_hw_common(ah);
265 const struct ani_ofdm_level_entry *entry_ofdm;
266 const struct ani_cck_level_entry *entry_cck;
268 aniState->noiseFloor = BEACON_RSSI(ah);
270 ath_print(common, ATH_DBG_ANI,
271 "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
272 aniState->ofdmNoiseImmunityLevel,
273 immunityLevel, aniState->noiseFloor,
274 aniState->rssiThrLow, aniState->rssiThrHigh);
276 aniState->ofdmNoiseImmunityLevel = immunityLevel;
278 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
279 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
281 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
282 ath9k_hw_ani_control(ah,
283 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
284 entry_ofdm->spur_immunity_level);
286 if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
287 entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
288 ath9k_hw_ani_control(ah,
289 ATH9K_ANI_FIRSTEP_LEVEL,
290 entry_ofdm->fir_step_level);
292 if ((ah->opmode != NL80211_IFTYPE_STATION &&
293 ah->opmode != NL80211_IFTYPE_ADHOC) ||
294 aniState->noiseFloor <= aniState->rssiThrHigh) {
295 if (aniState->ofdmWeakSigDetectOff)
296 /* force on ofdm weak sig detect */
297 ath9k_hw_ani_control(ah,
298 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
300 else if (aniState->ofdmWeakSigDetectOff ==
301 entry_ofdm->ofdm_weak_signal_on)
302 ath9k_hw_ani_control(ah,
303 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
304 entry_ofdm->ofdm_weak_signal_on);
308 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
310 struct ar5416AniState *aniState;
315 if (!use_new_ani(ah)) {
316 ath9k_hw_ani_ofdm_err_trigger_old(ah);
320 aniState = &ah->curchan->ani;
322 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
323 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
327 * Set the ANI settings to match an CCK level.
329 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
331 struct ar5416AniState *aniState = &ah->curchan->ani;
332 struct ath_common *common = ath9k_hw_common(ah);
333 const struct ani_ofdm_level_entry *entry_ofdm;
334 const struct ani_cck_level_entry *entry_cck;
336 aniState->noiseFloor = BEACON_RSSI(ah);
337 ath_print(common, ATH_DBG_ANI,
338 "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
339 aniState->cckNoiseImmunityLevel, immunityLevel,
340 aniState->noiseFloor, aniState->rssiThrLow,
341 aniState->rssiThrHigh);
343 if ((ah->opmode == NL80211_IFTYPE_STATION ||
344 ah->opmode == NL80211_IFTYPE_ADHOC) &&
345 aniState->noiseFloor <= aniState->rssiThrLow &&
346 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
347 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
349 aniState->cckNoiseImmunityLevel = immunityLevel;
351 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
352 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
354 if (aniState->firstepLevel != entry_cck->fir_step_level &&
355 entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
356 ath9k_hw_ani_control(ah,
357 ATH9K_ANI_FIRSTEP_LEVEL,
358 entry_cck->fir_step_level);
360 /* Skip MRC CCK for pre AR9003 families */
361 if (!AR_SREV_9300_20_OR_LATER(ah))
364 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
365 ath9k_hw_ani_control(ah,
367 entry_cck->mrc_cck_on);
370 static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
372 struct ar5416AniState *aniState;
377 if (!use_new_ani(ah)) {
378 ath9k_hw_ani_cck_err_trigger_old(ah);
382 aniState = &ah->curchan->ani;
384 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
385 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
388 static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
390 struct ar5416AniState *aniState;
393 aniState = &ah->curchan->ani;
395 if (ah->opmode == NL80211_IFTYPE_AP) {
396 if (aniState->firstepLevel > 0) {
397 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
398 aniState->firstepLevel - 1))
402 rssi = BEACON_RSSI(ah);
403 if (rssi > aniState->rssiThrHigh) {
405 } else if (rssi > aniState->rssiThrLow) {
406 if (aniState->ofdmWeakSigDetectOff) {
407 if (ath9k_hw_ani_control(ah,
408 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
412 if (aniState->firstepLevel > 0) {
413 if (ath9k_hw_ani_control(ah,
414 ATH9K_ANI_FIRSTEP_LEVEL,
415 aniState->firstepLevel - 1) == true)
419 if (aniState->firstepLevel > 0) {
420 if (ath9k_hw_ani_control(ah,
421 ATH9K_ANI_FIRSTEP_LEVEL,
422 aniState->firstepLevel - 1) == true)
428 if (aniState->spurImmunityLevel > 0) {
429 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
430 aniState->spurImmunityLevel - 1))
434 if (aniState->noiseImmunityLevel > 0) {
435 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
436 aniState->noiseImmunityLevel - 1);
442 * only lower either OFDM or CCK errors per turn
443 * we lower the other one next time
445 static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
447 struct ar5416AniState *aniState;
449 aniState = &ah->curchan->ani;
451 if (!use_new_ani(ah)) {
452 ath9k_hw_ani_lower_immunity_old(ah);
456 /* lower OFDM noise immunity */
457 if (aniState->ofdmNoiseImmunityLevel > 0 &&
458 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
459 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1);
463 /* lower CCK noise immunity */
464 if (aniState->cckNoiseImmunityLevel > 0)
465 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
468 static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah)
470 struct ath9k_channel *chan = ah->curchan;
471 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
472 u8 clockrate; /* in MHz */
474 if (!ah->curchan) /* should really check for CCK instead */
475 clockrate = ATH9K_CLOCK_RATE_CCK;
476 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
477 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
478 else if (IS_CHAN_A_FAST_CLOCK(ah, chan))
479 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
481 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
483 if (conf_is_ht40(conf))
484 return clockrate * 2;
489 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
494 ath9k_hw_update_cycle_counters(ah);
495 clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;
496 listen_time = ah->listen_time / clock_rate;
502 static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
504 struct ar5416AniState *aniState;
505 struct ath9k_channel *chan = ah->curchan;
506 struct ath_common *common = ath9k_hw_common(ah);
511 aniState = &ah->curchan->ani;
513 if (ah->opmode != NL80211_IFTYPE_STATION
514 && ah->opmode != NL80211_IFTYPE_ADHOC) {
515 ath_print(common, ATH_DBG_ANI,
516 "Reset ANI state opmode %u\n", ah->opmode);
517 ah->stats.ast_ani_reset++;
519 if (ah->opmode == NL80211_IFTYPE_AP) {
521 * ath9k_hw_ani_control() will only process items set on
524 if (IS_CHAN_2GHZ(chan))
525 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
526 ATH9K_ANI_FIRSTEP_LEVEL);
528 ah->ani_function = 0;
531 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
532 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
533 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
534 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
535 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
536 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
537 ATH9K_ANI_CCK_WEAK_SIG_THR);
539 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
540 ATH9K_RX_FILTER_PHYERR);
542 ath9k_ani_restart(ah);
546 if (aniState->noiseImmunityLevel != 0)
547 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
548 aniState->noiseImmunityLevel);
549 if (aniState->spurImmunityLevel != 0)
550 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
551 aniState->spurImmunityLevel);
552 if (aniState->ofdmWeakSigDetectOff)
553 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
554 !aniState->ofdmWeakSigDetectOff);
555 if (aniState->cckWeakSigThreshold)
556 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
557 aniState->cckWeakSigThreshold);
558 if (aniState->firstepLevel != 0)
559 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
560 aniState->firstepLevel);
562 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
563 ~ATH9K_RX_FILTER_PHYERR);
564 ath9k_ani_restart(ah);
566 ENABLE_REGWRITE_BUFFER(ah);
568 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
569 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
571 REGWRITE_BUFFER_FLUSH(ah);
575 * Restore the ANI parameters in the HAL and reset the statistics.
576 * This routine should be called for every hardware reset and for
577 * every channel change.
579 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
581 struct ar5416AniState *aniState = &ah->curchan->ani;
582 struct ath9k_channel *chan = ah->curchan;
583 struct ath_common *common = ath9k_hw_common(ah);
588 if (!use_new_ani(ah))
589 return ath9k_ani_reset_old(ah, is_scanning);
591 BUG_ON(aniState == NULL);
592 ah->stats.ast_ani_reset++;
594 /* only allow a subset of functions in AP mode */
595 if (ah->opmode == NL80211_IFTYPE_AP) {
596 if (IS_CHAN_2GHZ(chan)) {
597 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
598 ATH9K_ANI_FIRSTEP_LEVEL);
599 if (AR_SREV_9300_20_OR_LATER(ah))
600 ah->ani_function |= ATH9K_ANI_MRC_CCK;
602 ah->ani_function = 0;
605 /* always allow mode (on/off) to be controlled */
606 ah->ani_function |= ATH9K_ANI_MODE;
609 (ah->opmode != NL80211_IFTYPE_STATION &&
610 ah->opmode != NL80211_IFTYPE_ADHOC)) {
612 * If we're scanning or in AP mode, the defaults (ini)
613 * should be in place. For an AP we assume the historical
614 * levels for this channel are probably outdated so start
615 * from defaults instead.
617 if (aniState->ofdmNoiseImmunityLevel !=
618 ATH9K_ANI_OFDM_DEF_LEVEL ||
619 aniState->cckNoiseImmunityLevel !=
620 ATH9K_ANI_CCK_DEF_LEVEL) {
621 ath_print(common, ATH_DBG_ANI,
622 "Restore defaults: opmode %u "
623 "chan %d Mhz/0x%x is_scanning=%d "
629 aniState->ofdmNoiseImmunityLevel,
630 aniState->cckNoiseImmunityLevel);
632 ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
633 ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
637 * restore historical levels for this channel
639 ath_print(common, ATH_DBG_ANI,
640 "Restore history: opmode %u "
641 "chan %d Mhz/0x%x is_scanning=%d "
647 aniState->ofdmNoiseImmunityLevel,
648 aniState->cckNoiseImmunityLevel);
650 ath9k_hw_set_ofdm_nil(ah,
651 aniState->ofdmNoiseImmunityLevel);
652 ath9k_hw_set_cck_nil(ah,
653 aniState->cckNoiseImmunityLevel);
657 * enable phy counters if hw supports or if not, enable phy
658 * interrupts (so we can count each one)
660 ath9k_ani_restart(ah);
662 ENABLE_REGWRITE_BUFFER(ah);
664 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
665 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
667 REGWRITE_BUFFER_FLUSH(ah);
670 static void ath9k_hw_ani_read_counters(struct ath_hw *ah)
672 struct ath_common *common = ath9k_hw_common(ah);
673 struct ar5416AniState *aniState = &ah->curchan->ani;
676 u32 ofdmPhyErrCnt, cckPhyErrCnt;
677 u32 phyCnt1, phyCnt2;
680 listenTime = ath9k_hw_ani_get_listen_time(ah);
681 if (listenTime < 0) {
682 ah->stats.ast_ani_lneg++;
683 ath9k_ani_restart(ah);
687 if (!use_new_ani(ah)) {
688 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
689 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
692 aniState->listenTime += listenTime;
694 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
696 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
697 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
699 if (use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
700 if (phyCnt1 < ofdm_base) {
701 ath_print(common, ATH_DBG_ANI,
702 "phyCnt1 0x%x, resetting "
703 "counter value to 0x%x\n",
705 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
706 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
707 AR_PHY_ERR_OFDM_TIMING);
709 if (phyCnt2 < cck_base) {
710 ath_print(common, ATH_DBG_ANI,
711 "phyCnt2 0x%x, resetting "
712 "counter value to 0x%x\n",
714 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
715 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
716 AR_PHY_ERR_CCK_TIMING);
721 ofdmPhyErrCnt = phyCnt1 - ofdm_base;
722 ah->stats.ast_ani_ofdmerrs +=
723 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
724 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
726 cckPhyErrCnt = phyCnt2 - cck_base;
727 ah->stats.ast_ani_cckerrs +=
728 cckPhyErrCnt - aniState->cckPhyErrCount;
729 aniState->cckPhyErrCount = cckPhyErrCnt;
733 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
735 struct ar5416AniState *aniState;
736 struct ath_common *common = ath9k_hw_common(ah);
737 u32 ofdmPhyErrRate, cckPhyErrRate;
742 aniState = &ah->curchan->ani;
743 if (WARN_ON(!aniState))
746 ath9k_hw_ani_read_counters(ah);
748 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
749 aniState->listenTime;
750 cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
751 aniState->listenTime;
753 ath_print(common, ATH_DBG_ANI,
754 "listenTime=%d OFDM:%d errs=%d/s CCK:%d "
755 "errs=%d/s ofdm_turn=%d\n",
756 aniState->listenTime,
757 aniState->ofdmNoiseImmunityLevel,
758 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
759 cckPhyErrRate, aniState->ofdmsTurn);
761 if (aniState->listenTime > 5 * ah->aniperiod) {
762 if (ofdmPhyErrRate <= ah->config.ofdm_trig_low &&
763 cckPhyErrRate <= ah->config.cck_trig_low) {
764 ath9k_hw_ani_lower_immunity(ah);
765 aniState->ofdmsTurn = !aniState->ofdmsTurn;
767 ath9k_ani_restart(ah);
768 } else if (aniState->listenTime > ah->aniperiod) {
769 /* check to see if need to raise immunity */
770 if (ofdmPhyErrRate > ah->config.ofdm_trig_high &&
771 (cckPhyErrRate <= ah->config.cck_trig_high ||
772 aniState->ofdmsTurn)) {
773 ath9k_hw_ani_ofdm_err_trigger(ah);
774 ath9k_ani_restart(ah);
775 aniState->ofdmsTurn = false;
776 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
777 ath9k_hw_ani_cck_err_trigger(ah);
778 ath9k_ani_restart(ah);
779 aniState->ofdmsTurn = true;
783 EXPORT_SYMBOL(ath9k_hw_ani_monitor);
785 void ath9k_enable_mib_counters(struct ath_hw *ah)
787 struct ath_common *common = ath9k_hw_common(ah);
789 ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
791 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
793 ENABLE_REGWRITE_BUFFER(ah);
795 REG_WRITE(ah, AR_FILT_OFDM, 0);
796 REG_WRITE(ah, AR_FILT_CCK, 0);
797 REG_WRITE(ah, AR_MIBC,
798 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
800 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
801 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
803 REGWRITE_BUFFER_FLUSH(ah);
806 /* Freeze the MIB counters, get the stats and then clear them */
807 void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
809 struct ath_common *common = ath9k_hw_common(ah);
811 ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
813 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
814 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
815 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
816 REG_WRITE(ah, AR_FILT_OFDM, 0);
817 REG_WRITE(ah, AR_FILT_CCK, 0);
819 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
821 void ath9k_hw_update_cycle_counters(struct ath_hw *ah)
823 struct ath_cycle_counters cc;
826 memcpy(&cc, &ah->cc, sizeof(cc));
828 /* freeze counters */
829 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
831 ah->cc.cycles = REG_READ(ah, AR_CCCNT);
832 if (ah->cc.cycles < cc.cycles) {
837 ah->cc.rx_clear = REG_READ(ah, AR_RCCNT);
838 ah->cc.rx_frame = REG_READ(ah, AR_RFCNT);
839 ah->cc.tx_frame = REG_READ(ah, AR_TFCNT);
841 /* prevent wraparound */
842 if (ah->cc.cycles & BIT(31))
845 #define CC_DELTA(_field, _reg) ah->cc_delta._field += ah->cc._field - cc._field
846 CC_DELTA(cycles, AR_CCCNT);
847 CC_DELTA(rx_frame, AR_RFCNT);
848 CC_DELTA(rx_clear, AR_RCCNT);
849 CC_DELTA(tx_frame, AR_TFCNT);
852 ah->listen_time += (ah->cc.cycles - cc.cycles) -
853 ((ah->cc.rx_frame - cc.rx_frame) +
854 (ah->cc.tx_frame - cc.tx_frame));
858 REG_WRITE(ah, AR_CCCNT, 0);
859 REG_WRITE(ah, AR_RFCNT, 0);
860 REG_WRITE(ah, AR_RCCNT, 0);
861 REG_WRITE(ah, AR_TFCNT, 0);
862 memset(&ah->cc, 0, sizeof(ah->cc));
865 /* unfreeze counters */
866 REG_WRITE(ah, AR_MIBC, 0);
870 * Process a MIB interrupt. We may potentially be invoked because
871 * any of the MIB counters overflow/trigger so don't assume we're
872 * here because a PHY error counter triggered.
874 void ath9k_hw_proc_mib_event(struct ath_hw *ah)
876 u32 phyCnt1, phyCnt2;
878 /* Reset these counters regardless */
879 REG_WRITE(ah, AR_FILT_OFDM, 0);
880 REG_WRITE(ah, AR_FILT_CCK, 0);
881 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
882 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
884 /* Clear the mib counters and save them in the stats */
885 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
889 * We must always clear the interrupt cause by
890 * resetting the phy error regs.
892 REG_WRITE(ah, AR_PHY_ERR_1, 0);
893 REG_WRITE(ah, AR_PHY_ERR_2, 0);
897 /* NB: these are not reset-on-read */
898 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
899 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
900 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
901 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
903 if (!use_new_ani(ah))
904 ath9k_hw_ani_read_counters(ah);
906 /* NB: always restart to insure the h/w counters are reset */
907 ath9k_ani_restart(ah);
910 EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
912 void ath9k_hw_ani_setup(struct ath_hw *ah)
916 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
917 const int coarseHigh[] = { -14, -14, -14, -14, -12 };
918 const int coarseLow[] = { -64, -64, -64, -64, -70 };
919 const int firpwr[] = { -78, -78, -78, -78, -80 };
921 for (i = 0; i < 5; i++) {
922 ah->totalSizeDesired[i] = totalSizeDesired[i];
923 ah->coarse_high[i] = coarseHigh[i];
924 ah->coarse_low[i] = coarseLow[i];
925 ah->firpwr[i] = firpwr[i];
929 void ath9k_hw_ani_init(struct ath_hw *ah)
931 struct ath_common *common = ath9k_hw_common(ah);
934 ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
936 if (use_new_ani(ah)) {
937 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
938 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
940 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
941 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW;
943 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
944 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
946 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
947 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
950 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
951 struct ath9k_channel *chan = &ah->channels[i];
952 struct ar5416AniState *ani = &chan->ani;
954 if (use_new_ani(ah)) {
955 ani->spurImmunityLevel =
956 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
958 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
960 if (AR_SREV_9300_20_OR_LATER(ah))
962 !ATH9K_ANI_ENABLE_MRC_CCK;
964 ani->mrcCCKOff = true;
966 ani->ofdmsTurn = true;
968 ani->spurImmunityLevel =
969 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
970 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
972 ani->cckWeakSigThreshold =
973 ATH9K_ANI_CCK_WEAK_SIG_THR;
976 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
977 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
978 ani->ofdmWeakSigDetectOff =
979 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
980 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
984 * since we expect some ongoing maintenance on the tables, let's sanity
985 * check here default level should not modify INI setting.
987 if (use_new_ani(ah)) {
988 const struct ani_ofdm_level_entry *entry_ofdm;
989 const struct ani_cck_level_entry *entry_cck;
991 entry_ofdm = &ofdm_level_table[ATH9K_ANI_OFDM_DEF_LEVEL];
992 entry_cck = &cck_level_table[ATH9K_ANI_CCK_DEF_LEVEL];
994 ah->aniperiod = ATH9K_ANI_PERIOD_NEW;
995 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
997 ah->aniperiod = ATH9K_ANI_PERIOD_OLD;
998 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
1001 if (ah->config.enable_ani)
1002 ah->proc_phyerr |= HAL_PROCESS_ANI;
1004 ath9k_ani_restart(ah);
1005 ath9k_enable_mib_counters(ah);