drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20 #include "ar9003_eeprom.h"
  21
  22 #define COMP_HDR_LEN 4
  23 #define COMP_CKSUM_LEN 2
  24
  25 #define LE16(x) __constant_cpu_to_le16(x)
  26 #define LE32(x) __constant_cpu_to_le32(x)
  27
  28 /* Local defines to distinguish between extension and control CTL's */
  29 #define EXT_ADDITIVE (0x8000)
  30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  33
  34 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  35 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  36
  37 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
  38
  39 #define EEPROM_DATA_LEN_9485    1088
  40
  41 static int ar9003_hw_power_interpolate(int32_t x,
  42                                        int32_t *px, int32_t *py, u_int16_t np);
  43
  44
  45 static const struct ar9300_eeprom ar9300_default = {
  46         .eepromVersion = 2,
  47         .templateVersion = 2,
  48         .macAddr = {0, 2, 3, 4, 5, 6},
  49         .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  50                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  51         .baseEepHeader = {
  52                 .regDmn = { LE16(0), LE16(0x1f) },
  53                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
  54                 .opCapFlags = {
  55                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
  56                         .eepMisc = 0,
  57                 },
  58                 .rfSilent = 0,
  59                 .blueToothOptions = 0,
  60                 .deviceCap = 0,
  61                 .deviceType = 5, /* takes lower byte in eeprom location */
  62                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  63                 .params_for_tuning_caps = {0, 0},
  64                 .featureEnable = 0x0c,
  65                  /*
  66                   * bit0 - enable tx temp comp - disabled
  67                   * bit1 - enable tx volt comp - disabled
  68                   * bit2 - enable fastClock - enabled
  69                   * bit3 - enable doubling - enabled
  70                   * bit4 - enable internal regulator - disabled
  71                   * bit5 - enable pa predistortion - disabled
  72                   */
  73                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  74                 .eepromWriteEnableGpio = 3,
  75                 .wlanDisableGpio = 0,
  76                 .wlanLedGpio = 8,
  77                 .rxBandSelectGpio = 0xff,
  78                 .txrxgain = 0,
  79                 .swreg = 0,
  80          },
  81         .modalHeader2G = {
  82         /* ar9300_modal_eep_header  2g */
  83                 /* 4 idle,t1,t2,b(4 bits per setting) */
  84                 .antCtrlCommon = LE32(0x110),
  85                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  86                 .antCtrlCommon2 = LE32(0x22222),
  87
  88                 /*
  89                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
  90                  * rx1, rx12, b (2 bits each)
  91                  */
  92                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
  93
  94                 /*
  95                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
  96                  * for ar9280 (0xa20c/b20c 5:0)
  97                  */
  98                 .xatten1DB = {0, 0, 0},
  99
 100                 /*
 101                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 102                  * for ar9280 (0xa20c/b20c 16:12
 103                  */
 104                 .xatten1Margin = {0, 0, 0},
 105                 .tempSlope = 36,
 106                 .voltSlope = 0,
 107
 108                 /*
 109                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 110                  * channels in usual fbin coding format
 111                  */
 112                 .spurChans = {0, 0, 0, 0, 0},
 113
 114                 /*
 115                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 116                  * if the register is per chain
 117                  */
 118                 .noiseFloorThreshCh = {-1, 0, 0},
 119                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 120                 .quick_drop = 0,
 121                 .xpaBiasLvl = 0,
 122                 .txFrameToDataStart = 0x0e,
 123                 .txFrameToPaOn = 0x0e,
 124                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 125                 .antennaGain = 0,
 126                 .switchSettling = 0x2c,
 127                 .adcDesiredSize = -30,
 128                 .txEndToXpaOff = 0,
 129                 .txEndToRxOn = 0x2,
 130                 .txFrameToXpaOn = 0xe,
 131                 .thresh62 = 28,
 132                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 133                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 134                 .futureModal = {
 135                         0, 0, 0, 0, 0, 0, 0, 0,
 136                 },
 137          },
 138         .base_ext1 = {
 139                 .ant_div_control = 0,
 140                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 141         },
 142         .calFreqPier2G = {
 143                 FREQ2FBIN(2412, 1),
 144                 FREQ2FBIN(2437, 1),
 145                 FREQ2FBIN(2472, 1),
 146          },
 147         /* ar9300_cal_data_per_freq_op_loop 2g */
 148         .calPierData2G = {
 149                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 150                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 151                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 152          },
 153         .calTarget_freqbin_Cck = {
 154                 FREQ2FBIN(2412, 1),
 155                 FREQ2FBIN(2484, 1),
 156          },
 157         .calTarget_freqbin_2G = {
 158                 FREQ2FBIN(2412, 1),
 159                 FREQ2FBIN(2437, 1),
 160                 FREQ2FBIN(2472, 1)
 161          },
 162         .calTarget_freqbin_2GHT20 = {
 163                 FREQ2FBIN(2412, 1),
 164                 FREQ2FBIN(2437, 1),
 165                 FREQ2FBIN(2472, 1)
 166          },
 167         .calTarget_freqbin_2GHT40 = {
 168                 FREQ2FBIN(2412, 1),
 169                 FREQ2FBIN(2437, 1),
 170                 FREQ2FBIN(2472, 1)
 171          },
 172         .calTargetPowerCck = {
 173                  /* 1L-5L,5S,11L,11S */
 174                  { {36, 36, 36, 36} },
 175                  { {36, 36, 36, 36} },
 176         },
 177         .calTargetPower2G = {
 178                  /* 6-24,36,48,54 */
 179                  { {32, 32, 28, 24} },
 180                  { {32, 32, 28, 24} },
 181                  { {32, 32, 28, 24} },
 182         },
 183         .calTargetPower2GHT20 = {
 184                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 185                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 186                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 187         },
 188         .calTargetPower2GHT40 = {
 189                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 190                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 191                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 192         },
 193         .ctlIndex_2G =  {
 194                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 195                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 196         },
 197         .ctl_freqbin_2G = {
 198                 {
 199                         FREQ2FBIN(2412, 1),
 200                         FREQ2FBIN(2417, 1),
 201                         FREQ2FBIN(2457, 1),
 202                         FREQ2FBIN(2462, 1)
 203                 },
 204                 {
 205                         FREQ2FBIN(2412, 1),
 206                         FREQ2FBIN(2417, 1),
 207                         FREQ2FBIN(2462, 1),
 208                         0xFF,
 209                 },
 210
 211                 {
 212                         FREQ2FBIN(2412, 1),
 213                         FREQ2FBIN(2417, 1),
 214                         FREQ2FBIN(2462, 1),
 215                         0xFF,
 216                 },
 217                 {
 218                         FREQ2FBIN(2422, 1),
 219                         FREQ2FBIN(2427, 1),
 220                         FREQ2FBIN(2447, 1),
 221                         FREQ2FBIN(2452, 1)
 222                 },
 223
 224                 {
 225                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 226                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 227                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 228                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 229                 },
 230
 231                 {
 232                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 233                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 234                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 235                         0,
 236                 },
 237
 238                 {
 239                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 240                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 241                         FREQ2FBIN(2472, 1),
 242                         0,
 243                 },
 244
 245                 {
 246                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 247                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 248                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 249                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 250                 },
 251
 252                 {
 253                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 254                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 255                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 256                 },
 257
 258                 {
 259                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 260                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 261                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 262                         0
 263                 },
 264
 265                 {
 266                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 267                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 268                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 269                         0
 270                 },
 271
 272                 {
 273                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 274                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 275                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 276                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 277                 }
 278          },
 279         .ctlPowerData_2G = {
 280                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 281                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 282                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 283
 284                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 285                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 286                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 287
 288                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 289                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 290                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 291
 292                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 293                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 294                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 295          },
 296         .modalHeader5G = {
 297                 /* 4 idle,t1,t2,b (4 bits per setting) */
 298                 .antCtrlCommon = LE32(0x110),
 299                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 300                 .antCtrlCommon2 = LE32(0x22222),
 301                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 302                 .antCtrlChain = {
 303                         LE16(0x000), LE16(0x000), LE16(0x000),
 304                 },
 305                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 306                 .xatten1DB = {0, 0, 0},
 307
 308                 /*
 309                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 310                  * for merlin (0xa20c/b20c 16:12
 311                  */
 312                 .xatten1Margin = {0, 0, 0},
 313                 .tempSlope = 68,
 314                 .voltSlope = 0,
 315                 /* spurChans spur channels in usual fbin coding format */
 316                 .spurChans = {0, 0, 0, 0, 0},
 317                 /* noiseFloorThreshCh Check if the register is per chain */
 318                 .noiseFloorThreshCh = {-1, 0, 0},
 319                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 320                 .quick_drop = 0,
 321                 .xpaBiasLvl = 0,
 322                 .txFrameToDataStart = 0x0e,
 323                 .txFrameToPaOn = 0x0e,
 324                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 325                 .antennaGain = 0,
 326                 .switchSettling = 0x2d,
 327                 .adcDesiredSize = -30,
 328                 .txEndToXpaOff = 0,
 329                 .txEndToRxOn = 0x2,
 330                 .txFrameToXpaOn = 0xe,
 331                 .thresh62 = 28,
 332                 .papdRateMaskHt20 = LE32(0x0c80c080),
 333                 .papdRateMaskHt40 = LE32(0x0080c080),
 334                 .futureModal = {
 335                         0, 0, 0, 0, 0, 0, 0, 0,
 336                 },
 337          },
 338         .base_ext2 = {
 339                 .tempSlopeLow = 0,
 340                 .tempSlopeHigh = 0,
 341                 .xatten1DBLow = {0, 0, 0},
 342                 .xatten1MarginLow = {0, 0, 0},
 343                 .xatten1DBHigh = {0, 0, 0},
 344                 .xatten1MarginHigh = {0, 0, 0}
 345         },
 346         .calFreqPier5G = {
 347                 FREQ2FBIN(5180, 0),
 348                 FREQ2FBIN(5220, 0),
 349                 FREQ2FBIN(5320, 0),
 350                 FREQ2FBIN(5400, 0),
 351                 FREQ2FBIN(5500, 0),
 352                 FREQ2FBIN(5600, 0),
 353                 FREQ2FBIN(5725, 0),
 354                 FREQ2FBIN(5825, 0)
 355         },
 356         .calPierData5G = {
 357                         {
 358                                 {0, 0, 0, 0, 0},
 359                                 {0, 0, 0, 0, 0},
 360                                 {0, 0, 0, 0, 0},
 361                                 {0, 0, 0, 0, 0},
 362                                 {0, 0, 0, 0, 0},
 363                                 {0, 0, 0, 0, 0},
 364                                 {0, 0, 0, 0, 0},
 365                                 {0, 0, 0, 0, 0},
 366                         },
 367                         {
 368                                 {0, 0, 0, 0, 0},
 369                                 {0, 0, 0, 0, 0},
 370                                 {0, 0, 0, 0, 0},
 371                                 {0, 0, 0, 0, 0},
 372                                 {0, 0, 0, 0, 0},
 373                                 {0, 0, 0, 0, 0},
 374                                 {0, 0, 0, 0, 0},
 375                                 {0, 0, 0, 0, 0},
 376                         },
 377                         {
 378                                 {0, 0, 0, 0, 0},
 379                                 {0, 0, 0, 0, 0},
 380                                 {0, 0, 0, 0, 0},
 381                                 {0, 0, 0, 0, 0},
 382                                 {0, 0, 0, 0, 0},
 383                                 {0, 0, 0, 0, 0},
 384                                 {0, 0, 0, 0, 0},
 385                                 {0, 0, 0, 0, 0},
 386                         },
 387
 388         },
 389         .calTarget_freqbin_5G = {
 390                 FREQ2FBIN(5180, 0),
 391                 FREQ2FBIN(5220, 0),
 392                 FREQ2FBIN(5320, 0),
 393                 FREQ2FBIN(5400, 0),
 394                 FREQ2FBIN(5500, 0),
 395                 FREQ2FBIN(5600, 0),
 396                 FREQ2FBIN(5725, 0),
 397                 FREQ2FBIN(5825, 0)
 398         },
 399         .calTarget_freqbin_5GHT20 = {
 400                 FREQ2FBIN(5180, 0),
 401                 FREQ2FBIN(5240, 0),
 402                 FREQ2FBIN(5320, 0),
 403                 FREQ2FBIN(5500, 0),
 404                 FREQ2FBIN(5700, 0),
 405                 FREQ2FBIN(5745, 0),
 406                 FREQ2FBIN(5725, 0),
 407                 FREQ2FBIN(5825, 0)
 408         },
 409         .calTarget_freqbin_5GHT40 = {
 410                 FREQ2FBIN(5180, 0),
 411                 FREQ2FBIN(5240, 0),
 412                 FREQ2FBIN(5320, 0),
 413                 FREQ2FBIN(5500, 0),
 414                 FREQ2FBIN(5700, 0),
 415                 FREQ2FBIN(5745, 0),
 416                 FREQ2FBIN(5725, 0),
 417                 FREQ2FBIN(5825, 0)
 418          },
 419         .calTargetPower5G = {
 420                 /* 6-24,36,48,54 */
 421                 { {20, 20, 20, 10} },
 422                 { {20, 20, 20, 10} },
 423                 { {20, 20, 20, 10} },
 424                 { {20, 20, 20, 10} },
 425                 { {20, 20, 20, 10} },
 426                 { {20, 20, 20, 10} },
 427                 { {20, 20, 20, 10} },
 428                 { {20, 20, 20, 10} },
 429          },
 430         .calTargetPower5GHT20 = {
 431                 /*
 432                  * 0_8_16,1-3_9-11_17-19,
 433                  * 4,5,6,7,12,13,14,15,20,21,22,23
 434                  */
 435                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 436                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 437                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 438                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 439                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 440                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 441                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 442                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 443          },
 444         .calTargetPower5GHT40 =  {
 445                 /*
 446                  * 0_8_16,1-3_9-11_17-19,
 447                  * 4,5,6,7,12,13,14,15,20,21,22,23
 448                  */
 449                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 450                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 451                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 452                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 453                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 454                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 455                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 456                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 457          },
 458         .ctlIndex_5G =  {
 459                 0x10, 0x16, 0x18, 0x40, 0x46,
 460                 0x48, 0x30, 0x36, 0x38
 461         },
 462         .ctl_freqbin_5G =  {
 463                 {
 464                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 465                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 466                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 467                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 468                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 469                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 470                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 471                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 472                 },
 473                 {
 474                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 475                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 476                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 477                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 478                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 479                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 480                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 481                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 482                 },
 483
 484                 {
 485                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 486                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 487                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 488                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 489                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 490                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 491                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 492                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 493                 },
 494
 495                 {
 496                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 497                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 498                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 499                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 500                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 501                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 502                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 503                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 504                 },
 505
 506                 {
 507                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 508                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 509                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 510                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 511                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 512                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 513                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 514                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 515                 },
 516
 517                 {
 518                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 519                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 520                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 521                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 522                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 523                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 524                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 525                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
 526                 },
 527
 528                 {
 529                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 530                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 531                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 532                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 533                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 534                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 535                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 536                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 537                 },
 538
 539                 {
 540                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 541                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 542                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 543                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 544                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 545                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 546                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 547                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 548                 },
 549
 550                 {
 551                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 552                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 553                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 554                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 555                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 556                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 557                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 558                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 559                 }
 560          },
 561         .ctlPowerData_5G = {
 562                 {
 563                         {
 564                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 565                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 566                         }
 567                 },
 568                 {
 569                         {
 570                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 571                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 572                         }
 573                 },
 574                 {
 575                         {
 576                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 577                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 578                         }
 579                 },
 580                 {
 581                         {
 582                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 583                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 584                         }
 585                 },
 586                 {
 587                         {
 588                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 589                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 590                         }
 591                 },
 592                 {
 593                         {
 594                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 595                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 596                         }
 597                 },
 598                 {
 599                         {
 600                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 601                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 602                         }
 603                 },
 604                 {
 605                         {
 606                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 607                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 608                         }
 609                 },
 610                 {
 611                         {
 612                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
 613                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 614                         }
 615                 },
 616          }
 617 };
 618
 619 static const struct ar9300_eeprom ar9300_x113 = {
 620         .eepromVersion = 2,
 621         .templateVersion = 6,
 622         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 623         .custData = {"x113-023-f0000"},
 624         .baseEepHeader = {
 625                 .regDmn = { LE16(0), LE16(0x1f) },
 626                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 627                 .opCapFlags = {
 628                         .opFlags = AR5416_OPFLAGS_11A,
 629                         .eepMisc = 0,
 630                 },
 631                 .rfSilent = 0,
 632                 .blueToothOptions = 0,
 633                 .deviceCap = 0,
 634                 .deviceType = 5, /* takes lower byte in eeprom location */
 635                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 636                 .params_for_tuning_caps = {0, 0},
 637                 .featureEnable = 0x0d,
 638                  /*
 639                   * bit0 - enable tx temp comp - disabled
 640                   * bit1 - enable tx volt comp - disabled
 641                   * bit2 - enable fastClock - enabled
 642                   * bit3 - enable doubling - enabled
 643                   * bit4 - enable internal regulator - disabled
 644                   * bit5 - enable pa predistortion - disabled
 645                   */
 646                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 647                 .eepromWriteEnableGpio = 6,
 648                 .wlanDisableGpio = 0,
 649                 .wlanLedGpio = 8,
 650                 .rxBandSelectGpio = 0xff,
 651                 .txrxgain = 0x21,
 652                 .swreg = 0,
 653          },
 654         .modalHeader2G = {
 655         /* ar9300_modal_eep_header  2g */
 656                 /* 4 idle,t1,t2,b(4 bits per setting) */
 657                 .antCtrlCommon = LE32(0x110),
 658                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 659                 .antCtrlCommon2 = LE32(0x44444),
 660
 661                 /*
 662                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 663                  * rx1, rx12, b (2 bits each)
 664                  */
 665                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 666
 667                 /*
 668                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 669                  * for ar9280 (0xa20c/b20c 5:0)
 670                  */
 671                 .xatten1DB = {0, 0, 0},
 672
 673                 /*
 674                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 675                  * for ar9280 (0xa20c/b20c 16:12
 676                  */
 677                 .xatten1Margin = {0, 0, 0},
 678                 .tempSlope = 25,
 679                 .voltSlope = 0,
 680
 681                 /*
 682                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 683                  * channels in usual fbin coding format
 684                  */
 685                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 686
 687                 /*
 688                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 689                  * if the register is per chain
 690                  */
 691                 .noiseFloorThreshCh = {-1, 0, 0},
 692                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 693                 .quick_drop = 0,
 694                 .xpaBiasLvl = 0,
 695                 .txFrameToDataStart = 0x0e,
 696                 .txFrameToPaOn = 0x0e,
 697                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 698                 .antennaGain = 0,
 699                 .switchSettling = 0x2c,
 700                 .adcDesiredSize = -30,
 701                 .txEndToXpaOff = 0,
 702                 .txEndToRxOn = 0x2,
 703                 .txFrameToXpaOn = 0xe,
 704                 .thresh62 = 28,
 705                 .papdRateMaskHt20 = LE32(0x0c80c080),
 706                 .papdRateMaskHt40 = LE32(0x0080c080),
 707                 .futureModal = {
 708                         0, 0, 0, 0, 0, 0, 0, 0,
 709                 },
 710          },
 711          .base_ext1 = {
 712                 .ant_div_control = 0,
 713                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 714          },
 715         .calFreqPier2G = {
 716                 FREQ2FBIN(2412, 1),
 717                 FREQ2FBIN(2437, 1),
 718                 FREQ2FBIN(2472, 1),
 719          },
 720         /* ar9300_cal_data_per_freq_op_loop 2g */
 721         .calPierData2G = {
 722                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 723                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 724                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 725          },
 726         .calTarget_freqbin_Cck = {
 727                 FREQ2FBIN(2412, 1),
 728                 FREQ2FBIN(2472, 1),
 729          },
 730         .calTarget_freqbin_2G = {
 731                 FREQ2FBIN(2412, 1),
 732                 FREQ2FBIN(2437, 1),
 733                 FREQ2FBIN(2472, 1)
 734          },
 735         .calTarget_freqbin_2GHT20 = {
 736                 FREQ2FBIN(2412, 1),
 737                 FREQ2FBIN(2437, 1),
 738                 FREQ2FBIN(2472, 1)
 739          },
 740         .calTarget_freqbin_2GHT40 = {
 741                 FREQ2FBIN(2412, 1),
 742                 FREQ2FBIN(2437, 1),
 743                 FREQ2FBIN(2472, 1)
 744          },
 745         .calTargetPowerCck = {
 746                  /* 1L-5L,5S,11L,11S */
 747                  { {34, 34, 34, 34} },
 748                  { {34, 34, 34, 34} },
 749         },
 750         .calTargetPower2G = {
 751                  /* 6-24,36,48,54 */
 752                  { {34, 34, 32, 32} },
 753                  { {34, 34, 32, 32} },
 754                  { {34, 34, 32, 32} },
 755         },
 756         .calTargetPower2GHT20 = {
 757                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 758                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 759                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 760         },
 761         .calTargetPower2GHT40 = {
 762                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 763                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 764                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 765         },
 766         .ctlIndex_2G =  {
 767                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 768                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 769         },
 770         .ctl_freqbin_2G = {
 771                 {
 772                         FREQ2FBIN(2412, 1),
 773                         FREQ2FBIN(2417, 1),
 774                         FREQ2FBIN(2457, 1),
 775                         FREQ2FBIN(2462, 1)
 776                 },
 777                 {
 778                         FREQ2FBIN(2412, 1),
 779                         FREQ2FBIN(2417, 1),
 780                         FREQ2FBIN(2462, 1),
 781                         0xFF,
 782                 },
 783
 784                 {
 785                         FREQ2FBIN(2412, 1),
 786                         FREQ2FBIN(2417, 1),
 787                         FREQ2FBIN(2462, 1),
 788                         0xFF,
 789                 },
 790                 {
 791                         FREQ2FBIN(2422, 1),
 792                         FREQ2FBIN(2427, 1),
 793                         FREQ2FBIN(2447, 1),
 794                         FREQ2FBIN(2452, 1)
 795                 },
 796
 797                 {
 798                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 799                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 800                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 801                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 802                 },
 803
 804                 {
 805                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 806                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 807                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 808                         0,
 809                 },
 810
 811                 {
 812                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 813                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 814                         FREQ2FBIN(2472, 1),
 815                         0,
 816                 },
 817
 818                 {
 819                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 820                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 821                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 822                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 823                 },
 824
 825                 {
 826                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 827                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 828                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 829                 },
 830
 831                 {
 832                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 833                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 834                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 835                         0
 836                 },
 837
 838                 {
 839                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 840                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 841                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 842                         0
 843                 },
 844
 845                 {
 846                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 847                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 848                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 849                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 850                 }
 851          },
 852         .ctlPowerData_2G = {
 853                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 854                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 855                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 856
 857                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 858                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 859                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 860
 861                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 862                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 863                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 864
 865                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 866                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 867                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 868          },
 869         .modalHeader5G = {
 870                 /* 4 idle,t1,t2,b (4 bits per setting) */
 871                 .antCtrlCommon = LE32(0x220),
 872                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 873                 .antCtrlCommon2 = LE32(0x11111),
 874                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 875                 .antCtrlChain = {
 876                         LE16(0x150), LE16(0x150), LE16(0x150),
 877                 },
 878                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 879                 .xatten1DB = {0, 0, 0},
 880
 881                 /*
 882                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 883                  * for merlin (0xa20c/b20c 16:12
 884                  */
 885                 .xatten1Margin = {0, 0, 0},
 886                 .tempSlope = 68,
 887                 .voltSlope = 0,
 888                 /* spurChans spur channels in usual fbin coding format */
 889                 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 890                 /* noiseFloorThreshCh Check if the register is per chain */
 891                 .noiseFloorThreshCh = {-1, 0, 0},
 892                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 893                 .quick_drop = 0,
 894                 .xpaBiasLvl = 0xf,
 895                 .txFrameToDataStart = 0x0e,
 896                 .txFrameToPaOn = 0x0e,
 897                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 898                 .antennaGain = 0,
 899                 .switchSettling = 0x2d,
 900                 .adcDesiredSize = -30,
 901                 .txEndToXpaOff = 0,
 902                 .txEndToRxOn = 0x2,
 903                 .txFrameToXpaOn = 0xe,
 904                 .thresh62 = 28,
 905                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 906                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 907                 .futureModal = {
 908                         0, 0, 0, 0, 0, 0, 0, 0,
 909                 },
 910          },
 911         .base_ext2 = {
 912                 .tempSlopeLow = 72,
 913                 .tempSlopeHigh = 105,
 914                 .xatten1DBLow = {0, 0, 0},
 915                 .xatten1MarginLow = {0, 0, 0},
 916                 .xatten1DBHigh = {0, 0, 0},
 917                 .xatten1MarginHigh = {0, 0, 0}
 918          },
 919         .calFreqPier5G = {
 920                 FREQ2FBIN(5180, 0),
 921                 FREQ2FBIN(5240, 0),
 922                 FREQ2FBIN(5320, 0),
 923                 FREQ2FBIN(5400, 0),
 924                 FREQ2FBIN(5500, 0),
 925                 FREQ2FBIN(5600, 0),
 926                 FREQ2FBIN(5745, 0),
 927                 FREQ2FBIN(5785, 0)
 928         },
 929         .calPierData5G = {
 930                         {
 931                                 {0, 0, 0, 0, 0},
 932                                 {0, 0, 0, 0, 0},
 933                                 {0, 0, 0, 0, 0},
 934                                 {0, 0, 0, 0, 0},
 935                                 {0, 0, 0, 0, 0},
 936                                 {0, 0, 0, 0, 0},
 937                                 {0, 0, 0, 0, 0},
 938                                 {0, 0, 0, 0, 0},
 939                         },
 940                         {
 941                                 {0, 0, 0, 0, 0},
 942                                 {0, 0, 0, 0, 0},
 943                                 {0, 0, 0, 0, 0},
 944                                 {0, 0, 0, 0, 0},
 945                                 {0, 0, 0, 0, 0},
 946                                 {0, 0, 0, 0, 0},
 947                                 {0, 0, 0, 0, 0},
 948                                 {0, 0, 0, 0, 0},
 949                         },
 950                         {
 951                                 {0, 0, 0, 0, 0},
 952                                 {0, 0, 0, 0, 0},
 953                                 {0, 0, 0, 0, 0},
 954                                 {0, 0, 0, 0, 0},
 955                                 {0, 0, 0, 0, 0},
 956                                 {0, 0, 0, 0, 0},
 957                                 {0, 0, 0, 0, 0},
 958                                 {0, 0, 0, 0, 0},
 959                         },
 960
 961         },
 962         .calTarget_freqbin_5G = {
 963                 FREQ2FBIN(5180, 0),
 964                 FREQ2FBIN(5220, 0),
 965                 FREQ2FBIN(5320, 0),
 966                 FREQ2FBIN(5400, 0),
 967                 FREQ2FBIN(5500, 0),
 968                 FREQ2FBIN(5600, 0),
 969                 FREQ2FBIN(5745, 0),
 970                 FREQ2FBIN(5785, 0)
 971         },
 972         .calTarget_freqbin_5GHT20 = {
 973                 FREQ2FBIN(5180, 0),
 974                 FREQ2FBIN(5240, 0),
 975                 FREQ2FBIN(5320, 0),
 976                 FREQ2FBIN(5400, 0),
 977                 FREQ2FBIN(5500, 0),
 978                 FREQ2FBIN(5700, 0),
 979                 FREQ2FBIN(5745, 0),
 980                 FREQ2FBIN(5825, 0)
 981         },
 982         .calTarget_freqbin_5GHT40 = {
 983                 FREQ2FBIN(5190, 0),
 984                 FREQ2FBIN(5230, 0),
 985                 FREQ2FBIN(5320, 0),
 986                 FREQ2FBIN(5410, 0),
 987                 FREQ2FBIN(5510, 0),
 988                 FREQ2FBIN(5670, 0),
 989                 FREQ2FBIN(5755, 0),
 990                 FREQ2FBIN(5825, 0)
 991          },
 992         .calTargetPower5G = {
 993                 /* 6-24,36,48,54 */
 994                 { {42, 40, 40, 34} },
 995                 { {42, 40, 40, 34} },
 996                 { {42, 40, 40, 34} },
 997                 { {42, 40, 40, 34} },
 998                 { {42, 40, 40, 34} },
 999                 { {42, 40, 40, 34} },
1000                 { {42, 40, 40, 34} },
1001                 { {42, 40, 40, 34} },
1002          },
1003         .calTargetPower5GHT20 = {
1004                 /*
1005                  * 0_8_16,1-3_9-11_17-19,
1006                  * 4,5,6,7,12,13,14,15,20,21,22,23
1007                  */
1008                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1009                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1010                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1011                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1012                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1013                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1014                 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1015                 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1016          },
1017         .calTargetPower5GHT40 =  {
1018                 /*
1019                  * 0_8_16,1-3_9-11_17-19,
1020                  * 4,5,6,7,12,13,14,15,20,21,22,23
1021                  */
1022                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1023                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1024                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1025                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1026                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1027                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1028                 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1029                 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1030          },
1031         .ctlIndex_5G =  {
1032                 0x10, 0x16, 0x18, 0x40, 0x46,
1033                 0x48, 0x30, 0x36, 0x38
1034         },
1035         .ctl_freqbin_5G =  {
1036                 {
1037                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1038                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1039                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1040                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1041                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1042                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1043                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1044                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1045                 },
1046                 {
1047                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1048                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1049                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1050                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1051                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1052                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1053                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1054                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1055                 },
1056
1057                 {
1058                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1059                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1060                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1061                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1062                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1063                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1064                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1065                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1066                 },
1067
1068                 {
1069                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1070                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1071                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1072                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1073                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1074                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1075                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1076                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1077                 },
1078
1079                 {
1080                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1081                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1082                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1083                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1084                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1085                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1086                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1087                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1088                 },
1089
1090                 {
1091                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1092                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1093                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1094                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1095                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1096                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1097                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1098                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1099                 },
1100
1101                 {
1102                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1103                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1104                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1105                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1106                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1107                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1108                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1109                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1110                 },
1111
1112                 {
1113                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1114                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1115                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1116                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1117                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1118                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1119                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1120                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1121                 },
1122
1123                 {
1124                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1125                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1126                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1127                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1128                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1129                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1130                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1131                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1132                 }
1133          },
1134         .ctlPowerData_5G = {
1135                 {
1136                         {
1137                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1138                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1139                         }
1140                 },
1141                 {
1142                         {
1143                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1144                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1145                         }
1146                 },
1147                 {
1148                         {
1149                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1150                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1151                         }
1152                 },
1153                 {
1154                         {
1155                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1156                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1157                         }
1158                 },
1159                 {
1160                         {
1161                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1162                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1163                         }
1164                 },
1165                 {
1166                         {
1167                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1168                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1169                         }
1170                 },
1171                 {
1172                         {
1173                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1174                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1175                         }
1176                 },
1177                 {
1178                         {
1179                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1180                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1181                         }
1182                 },
1183                 {
1184                         {
1185                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1186                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1187                         }
1188                 },
1189          }
1190 };
1191
1192
1193 static const struct ar9300_eeprom ar9300_h112 = {
1194         .eepromVersion = 2,
1195         .templateVersion = 3,
1196         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1197         .custData = {"h112-241-f0000"},
1198         .baseEepHeader = {
1199                 .regDmn = { LE16(0), LE16(0x1f) },
1200                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1201                 .opCapFlags = {
1202                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1203                         .eepMisc = 0,
1204                 },
1205                 .rfSilent = 0,
1206                 .blueToothOptions = 0,
1207                 .deviceCap = 0,
1208                 .deviceType = 5, /* takes lower byte in eeprom location */
1209                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1210                 .params_for_tuning_caps = {0, 0},
1211                 .featureEnable = 0x0d,
1212                 /*
1213                  * bit0 - enable tx temp comp - disabled
1214                  * bit1 - enable tx volt comp - disabled
1215                  * bit2 - enable fastClock - enabled
1216                  * bit3 - enable doubling - enabled
1217                  * bit4 - enable internal regulator - disabled
1218                  * bit5 - enable pa predistortion - disabled
1219                  */
1220                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1221                 .eepromWriteEnableGpio = 6,
1222                 .wlanDisableGpio = 0,
1223                 .wlanLedGpio = 8,
1224                 .rxBandSelectGpio = 0xff,
1225                 .txrxgain = 0x10,
1226                 .swreg = 0,
1227         },
1228         .modalHeader2G = {
1229                 /* ar9300_modal_eep_header  2g */
1230                 /* 4 idle,t1,t2,b(4 bits per setting) */
1231                 .antCtrlCommon = LE32(0x110),
1232                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1233                 .antCtrlCommon2 = LE32(0x44444),
1234
1235                 /*
1236                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1237                  * rx1, rx12, b (2 bits each)
1238                  */
1239                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1240
1241                 /*
1242                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
1243                  * for ar9280 (0xa20c/b20c 5:0)
1244                  */
1245                 .xatten1DB = {0, 0, 0},
1246
1247                 /*
1248                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1249                  * for ar9280 (0xa20c/b20c 16:12
1250                  */
1251                 .xatten1Margin = {0, 0, 0},
1252                 .tempSlope = 25,
1253                 .voltSlope = 0,
1254
1255                 /*
1256                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1257                  * channels in usual fbin coding format
1258                  */
1259                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1260
1261                 /*
1262                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1263                  * if the register is per chain
1264                  */
1265                 .noiseFloorThreshCh = {-1, 0, 0},
1266                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1267                 .quick_drop = 0,
1268                 .xpaBiasLvl = 0,
1269                 .txFrameToDataStart = 0x0e,
1270                 .txFrameToPaOn = 0x0e,
1271                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1272                 .antennaGain = 0,
1273                 .switchSettling = 0x2c,
1274                 .adcDesiredSize = -30,
1275                 .txEndToXpaOff = 0,
1276                 .txEndToRxOn = 0x2,
1277                 .txFrameToXpaOn = 0xe,
1278                 .thresh62 = 28,
1279                 .papdRateMaskHt20 = LE32(0x0c80c080),
1280                 .papdRateMaskHt40 = LE32(0x0080c080),
1281                 .futureModal = {
1282                         0, 0, 0, 0, 0, 0, 0, 0,
1283                 },
1284         },
1285         .base_ext1 = {
1286                 .ant_div_control = 0,
1287                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1288         },
1289         .calFreqPier2G = {
1290                 FREQ2FBIN(2412, 1),
1291                 FREQ2FBIN(2437, 1),
1292                 FREQ2FBIN(2462, 1),
1293         },
1294         /* ar9300_cal_data_per_freq_op_loop 2g */
1295         .calPierData2G = {
1296                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1297                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1298                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1299         },
1300         .calTarget_freqbin_Cck = {
1301                 FREQ2FBIN(2412, 1),
1302                 FREQ2FBIN(2472, 1),
1303         },
1304         .calTarget_freqbin_2G = {
1305                 FREQ2FBIN(2412, 1),
1306                 FREQ2FBIN(2437, 1),
1307                 FREQ2FBIN(2472, 1)
1308         },
1309         .calTarget_freqbin_2GHT20 = {
1310                 FREQ2FBIN(2412, 1),
1311                 FREQ2FBIN(2437, 1),
1312                 FREQ2FBIN(2472, 1)
1313         },
1314         .calTarget_freqbin_2GHT40 = {
1315                 FREQ2FBIN(2412, 1),
1316                 FREQ2FBIN(2437, 1),
1317                 FREQ2FBIN(2472, 1)
1318         },
1319         .calTargetPowerCck = {
1320                 /* 1L-5L,5S,11L,11S */
1321                 { {34, 34, 34, 34} },
1322                 { {34, 34, 34, 34} },
1323         },
1324         .calTargetPower2G = {
1325                 /* 6-24,36,48,54 */
1326                 { {34, 34, 32, 32} },
1327                 { {34, 34, 32, 32} },
1328                 { {34, 34, 32, 32} },
1329         },
1330         .calTargetPower2GHT20 = {
1331                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1332                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1333                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1334         },
1335         .calTargetPower2GHT40 = {
1336                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1337                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1338                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1339         },
1340         .ctlIndex_2G =  {
1341                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1342                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1343         },
1344         .ctl_freqbin_2G = {
1345                 {
1346                         FREQ2FBIN(2412, 1),
1347                         FREQ2FBIN(2417, 1),
1348                         FREQ2FBIN(2457, 1),
1349                         FREQ2FBIN(2462, 1)
1350                 },
1351                 {
1352                         FREQ2FBIN(2412, 1),
1353                         FREQ2FBIN(2417, 1),
1354                         FREQ2FBIN(2462, 1),
1355                         0xFF,
1356                 },
1357
1358                 {
1359                         FREQ2FBIN(2412, 1),
1360                         FREQ2FBIN(2417, 1),
1361                         FREQ2FBIN(2462, 1),
1362                         0xFF,
1363                 },
1364                 {
1365                         FREQ2FBIN(2422, 1),
1366                         FREQ2FBIN(2427, 1),
1367                         FREQ2FBIN(2447, 1),
1368                         FREQ2FBIN(2452, 1)
1369                 },
1370
1371                 {
1372                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1373                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1374                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1375                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1376                 },
1377
1378                 {
1379                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1380                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1381                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1382                         0,
1383                 },
1384
1385                 {
1386                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1387                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1388                         FREQ2FBIN(2472, 1),
1389                         0,
1390                 },
1391
1392                 {
1393                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1394                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1395                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1396                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1397                 },
1398
1399                 {
1400                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1401                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1402                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1403                 },
1404
1405                 {
1406                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1409                         0
1410                 },
1411
1412                 {
1413                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1416                         0
1417                 },
1418
1419                 {
1420                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1424                 }
1425         },
1426         .ctlPowerData_2G = {
1427                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1428                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1429                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1430
1431                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1432                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1433                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1434
1435                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1436                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1437                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1438
1439                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1440                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1441                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1442         },
1443         .modalHeader5G = {
1444                 /* 4 idle,t1,t2,b (4 bits per setting) */
1445                 .antCtrlCommon = LE32(0x220),
1446                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1447                 .antCtrlCommon2 = LE32(0x44444),
1448                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1449                 .antCtrlChain = {
1450                         LE16(0x150), LE16(0x150), LE16(0x150),
1451                 },
1452                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1453                 .xatten1DB = {0, 0, 0},
1454
1455                 /*
1456                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1457                  * for merlin (0xa20c/b20c 16:12
1458                  */
1459                 .xatten1Margin = {0, 0, 0},
1460                 .tempSlope = 45,
1461                 .voltSlope = 0,
1462                 /* spurChans spur channels in usual fbin coding format */
1463                 .spurChans = {0, 0, 0, 0, 0},
1464                 /* noiseFloorThreshCh Check if the register is per chain */
1465                 .noiseFloorThreshCh = {-1, 0, 0},
1466                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1467                 .quick_drop = 0,
1468                 .xpaBiasLvl = 0,
1469                 .txFrameToDataStart = 0x0e,
1470                 .txFrameToPaOn = 0x0e,
1471                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1472                 .antennaGain = 0,
1473                 .switchSettling = 0x2d,
1474                 .adcDesiredSize = -30,
1475                 .txEndToXpaOff = 0,
1476                 .txEndToRxOn = 0x2,
1477                 .txFrameToXpaOn = 0xe,
1478                 .thresh62 = 28,
1479                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1480                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1481                 .futureModal = {
1482                         0, 0, 0, 0, 0, 0, 0, 0,
1483                 },
1484         },
1485         .base_ext2 = {
1486                 .tempSlopeLow = 40,
1487                 .tempSlopeHigh = 50,
1488                 .xatten1DBLow = {0, 0, 0},
1489                 .xatten1MarginLow = {0, 0, 0},
1490                 .xatten1DBHigh = {0, 0, 0},
1491                 .xatten1MarginHigh = {0, 0, 0}
1492         },
1493         .calFreqPier5G = {
1494                 FREQ2FBIN(5180, 0),
1495                 FREQ2FBIN(5220, 0),
1496                 FREQ2FBIN(5320, 0),
1497                 FREQ2FBIN(5400, 0),
1498                 FREQ2FBIN(5500, 0),
1499                 FREQ2FBIN(5600, 0),
1500                 FREQ2FBIN(5700, 0),
1501                 FREQ2FBIN(5785, 0)
1502         },
1503         .calPierData5G = {
1504                 {
1505                         {0, 0, 0, 0, 0},
1506                         {0, 0, 0, 0, 0},
1507                         {0, 0, 0, 0, 0},
1508                         {0, 0, 0, 0, 0},
1509                         {0, 0, 0, 0, 0},
1510                         {0, 0, 0, 0, 0},
1511                         {0, 0, 0, 0, 0},
1512                         {0, 0, 0, 0, 0},
1513                 },
1514                 {
1515                         {0, 0, 0, 0, 0},
1516                         {0, 0, 0, 0, 0},
1517                         {0, 0, 0, 0, 0},
1518                         {0, 0, 0, 0, 0},
1519                         {0, 0, 0, 0, 0},
1520                         {0, 0, 0, 0, 0},
1521                         {0, 0, 0, 0, 0},
1522                         {0, 0, 0, 0, 0},
1523                 },
1524                 {
1525                         {0, 0, 0, 0, 0},
1526                         {0, 0, 0, 0, 0},
1527                         {0, 0, 0, 0, 0},
1528                         {0, 0, 0, 0, 0},
1529                         {0, 0, 0, 0, 0},
1530                         {0, 0, 0, 0, 0},
1531                         {0, 0, 0, 0, 0},
1532                         {0, 0, 0, 0, 0},
1533                 },
1534
1535         },
1536         .calTarget_freqbin_5G = {
1537                 FREQ2FBIN(5180, 0),
1538                 FREQ2FBIN(5240, 0),
1539                 FREQ2FBIN(5320, 0),
1540                 FREQ2FBIN(5400, 0),
1541                 FREQ2FBIN(5500, 0),
1542                 FREQ2FBIN(5600, 0),
1543                 FREQ2FBIN(5700, 0),
1544                 FREQ2FBIN(5825, 0)
1545         },
1546         .calTarget_freqbin_5GHT20 = {
1547                 FREQ2FBIN(5180, 0),
1548                 FREQ2FBIN(5240, 0),
1549                 FREQ2FBIN(5320, 0),
1550                 FREQ2FBIN(5400, 0),
1551                 FREQ2FBIN(5500, 0),
1552                 FREQ2FBIN(5700, 0),
1553                 FREQ2FBIN(5745, 0),
1554                 FREQ2FBIN(5825, 0)
1555         },
1556         .calTarget_freqbin_5GHT40 = {
1557                 FREQ2FBIN(5180, 0),
1558                 FREQ2FBIN(5240, 0),
1559                 FREQ2FBIN(5320, 0),
1560                 FREQ2FBIN(5400, 0),
1561                 FREQ2FBIN(5500, 0),
1562                 FREQ2FBIN(5700, 0),
1563                 FREQ2FBIN(5745, 0),
1564                 FREQ2FBIN(5825, 0)
1565         },
1566         .calTargetPower5G = {
1567                 /* 6-24,36,48,54 */
1568                 { {30, 30, 28, 24} },
1569                 { {30, 30, 28, 24} },
1570                 { {30, 30, 28, 24} },
1571                 { {30, 30, 28, 24} },
1572                 { {30, 30, 28, 24} },
1573                 { {30, 30, 28, 24} },
1574                 { {30, 30, 28, 24} },
1575                 { {30, 30, 28, 24} },
1576         },
1577         .calTargetPower5GHT20 = {
1578                 /*
1579                  * 0_8_16,1-3_9-11_17-19,
1580                  * 4,5,6,7,12,13,14,15,20,21,22,23
1581                  */
1582                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1583                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1584                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1585                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1586                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1587                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1588                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1589                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1590         },
1591         .calTargetPower5GHT40 =  {
1592                 /*
1593                  * 0_8_16,1-3_9-11_17-19,
1594                  * 4,5,6,7,12,13,14,15,20,21,22,23
1595                  */
1596                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1597                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1598                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1599                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1600                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1601                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1602                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1603                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1604         },
1605         .ctlIndex_5G =  {
1606                 0x10, 0x16, 0x18, 0x40, 0x46,
1607                 0x48, 0x30, 0x36, 0x38
1608         },
1609         .ctl_freqbin_5G =  {
1610                 {
1611                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1612                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1613                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1614                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1615                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1616                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1617                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1618                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1619                 },
1620                 {
1621                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1622                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1623                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1624                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1625                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1626                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1627                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1628                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1629                 },
1630
1631                 {
1632                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1633                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1634                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1635                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1636                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1637                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1638                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1639                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1640                 },
1641
1642                 {
1643                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1644                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1645                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1646                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1647                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1648                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1649                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1650                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1651                 },
1652
1653                 {
1654                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1655                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1656                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1657                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1658                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1659                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1660                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1661                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1662                 },
1663
1664                 {
1665                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1666                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1667                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1668                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1669                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1670                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1671                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1672                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1673                 },
1674
1675                 {
1676                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1677                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1678                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1679                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1680                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1681                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1682                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1683                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1684                 },
1685
1686                 {
1687                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1688                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1689                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1690                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1691                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1692                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1693                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1694                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1695                 },
1696
1697                 {
1698                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1699                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1700                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1701                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1702                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1703                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1704                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1705                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1706                 }
1707         },
1708         .ctlPowerData_5G = {
1709                 {
1710                         {
1711                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1712                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1713                         }
1714                 },
1715                 {
1716                         {
1717                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1718                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1719                         }
1720                 },
1721                 {
1722                         {
1723                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1724                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1725                         }
1726                 },
1727                 {
1728                         {
1729                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1730                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1731                         }
1732                 },
1733                 {
1734                         {
1735                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1736                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1737                         }
1738                 },
1739                 {
1740                         {
1741                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1742                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1743                         }
1744                 },
1745                 {
1746                         {
1747                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1748                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1749                         }
1750                 },
1751                 {
1752                         {
1753                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1754                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1755                         }
1756                 },
1757                 {
1758                         {
1759                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1760                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1761                         }
1762                 },
1763         }
1764 };
1765
1766
1767 static const struct ar9300_eeprom ar9300_x112 = {
1768         .eepromVersion = 2,
1769         .templateVersion = 5,
1770         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1771         .custData = {"x112-041-f0000"},
1772         .baseEepHeader = {
1773                 .regDmn = { LE16(0), LE16(0x1f) },
1774                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1775                 .opCapFlags = {
1776                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1777                         .eepMisc = 0,
1778                 },
1779                 .rfSilent = 0,
1780                 .blueToothOptions = 0,
1781                 .deviceCap = 0,
1782                 .deviceType = 5, /* takes lower byte in eeprom location */
1783                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1784                 .params_for_tuning_caps = {0, 0},
1785                 .featureEnable = 0x0d,
1786                 /*
1787                  * bit0 - enable tx temp comp - disabled
1788                  * bit1 - enable tx volt comp - disabled
1789                  * bit2 - enable fastclock - enabled
1790                  * bit3 - enable doubling - enabled
1791                  * bit4 - enable internal regulator - disabled
1792                  * bit5 - enable pa predistortion - disabled
1793                  */
1794                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1795                 .eepromWriteEnableGpio = 6,
1796                 .wlanDisableGpio = 0,
1797                 .wlanLedGpio = 8,
1798                 .rxBandSelectGpio = 0xff,
1799                 .txrxgain = 0x0,
1800                 .swreg = 0,
1801         },
1802         .modalHeader2G = {
1803                 /* ar9300_modal_eep_header  2g */
1804                 /* 4 idle,t1,t2,b(4 bits per setting) */
1805                 .antCtrlCommon = LE32(0x110),
1806                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1807                 .antCtrlCommon2 = LE32(0x22222),
1808
1809                 /*
1810                  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1811                  * rx1, rx12, b (2 bits each)
1812                  */
1813                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1814
1815                 /*
1816                  * xatten1DB[AR9300_max_chains];  3 xatten1_db
1817                  * for ar9280 (0xa20c/b20c 5:0)
1818                  */
1819                 .xatten1DB = {0x1b, 0x1b, 0x1b},
1820
1821                 /*
1822                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1823                  * for ar9280 (0xa20c/b20c 16:12
1824                  */
1825                 .xatten1Margin = {0x15, 0x15, 0x15},
1826                 .tempSlope = 50,
1827                 .voltSlope = 0,
1828
1829                 /*
1830                  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1831                  * channels in usual fbin coding format
1832                  */
1833                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1834
1835                 /*
1836                  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1837                  * if the register is per chain
1838                  */
1839                 .noiseFloorThreshCh = {-1, 0, 0},
1840                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1841                 .quick_drop = 0,
1842                 .xpaBiasLvl = 0,
1843                 .txFrameToDataStart = 0x0e,
1844                 .txFrameToPaOn = 0x0e,
1845                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1846                 .antennaGain = 0,
1847                 .switchSettling = 0x2c,
1848                 .adcDesiredSize = -30,
1849                 .txEndToXpaOff = 0,
1850                 .txEndToRxOn = 0x2,
1851                 .txFrameToXpaOn = 0xe,
1852                 .thresh62 = 28,
1853                 .papdRateMaskHt20 = LE32(0x0c80c080),
1854                 .papdRateMaskHt40 = LE32(0x0080c080),
1855                 .futureModal = {
1856                         0, 0, 0, 0, 0, 0, 0, 0,
1857                 },
1858         },
1859         .base_ext1 = {
1860                 .ant_div_control = 0,
1861                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1862         },
1863         .calFreqPier2G = {
1864                 FREQ2FBIN(2412, 1),
1865                 FREQ2FBIN(2437, 1),
1866                 FREQ2FBIN(2472, 1),
1867         },
1868         /* ar9300_cal_data_per_freq_op_loop 2g */
1869         .calPierData2G = {
1870                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1871                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1872                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1873         },
1874         .calTarget_freqbin_Cck = {
1875                 FREQ2FBIN(2412, 1),
1876                 FREQ2FBIN(2472, 1),
1877         },
1878         .calTarget_freqbin_2G = {
1879                 FREQ2FBIN(2412, 1),
1880                 FREQ2FBIN(2437, 1),
1881                 FREQ2FBIN(2472, 1)
1882         },
1883         .calTarget_freqbin_2GHT20 = {
1884                 FREQ2FBIN(2412, 1),
1885                 FREQ2FBIN(2437, 1),
1886                 FREQ2FBIN(2472, 1)
1887         },
1888         .calTarget_freqbin_2GHT40 = {
1889                 FREQ2FBIN(2412, 1),
1890                 FREQ2FBIN(2437, 1),
1891                 FREQ2FBIN(2472, 1)
1892         },
1893         .calTargetPowerCck = {
1894                 /* 1L-5L,5S,11L,11s */
1895                 { {38, 38, 38, 38} },
1896                 { {38, 38, 38, 38} },
1897         },
1898         .calTargetPower2G = {
1899                 /* 6-24,36,48,54 */
1900                 { {38, 38, 36, 34} },
1901                 { {38, 38, 36, 34} },
1902                 { {38, 38, 34, 32} },
1903         },
1904         .calTargetPower2GHT20 = {
1905                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1906                 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1907                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1908         },
1909         .calTargetPower2GHT40 = {
1910                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1911                 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1912                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1913         },
1914         .ctlIndex_2G =  {
1915                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1916                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1917         },
1918         .ctl_freqbin_2G = {
1919                 {
1920                         FREQ2FBIN(2412, 1),
1921                         FREQ2FBIN(2417, 1),
1922                         FREQ2FBIN(2457, 1),
1923                         FREQ2FBIN(2462, 1)
1924                 },
1925                 {
1926                         FREQ2FBIN(2412, 1),
1927                         FREQ2FBIN(2417, 1),
1928                         FREQ2FBIN(2462, 1),
1929                         0xFF,
1930                 },
1931
1932                 {
1933                         FREQ2FBIN(2412, 1),
1934                         FREQ2FBIN(2417, 1),
1935                         FREQ2FBIN(2462, 1),
1936                         0xFF,
1937                 },
1938                 {
1939                         FREQ2FBIN(2422, 1),
1940                         FREQ2FBIN(2427, 1),
1941                         FREQ2FBIN(2447, 1),
1942                         FREQ2FBIN(2452, 1)
1943                 },
1944
1945                 {
1946                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1947                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1948                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1949                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1950                 },
1951
1952                 {
1953                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1954                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1955                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1956                         0,
1957                 },
1958
1959                 {
1960                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1961                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1962                         FREQ2FBIN(2472, 1),
1963                         0,
1964                 },
1965
1966                 {
1967                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1968                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1969                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1970                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1971                 },
1972
1973                 {
1974                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1975                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1976                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1977                 },
1978
1979                 {
1980                         /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1981                         /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1982                         /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1983                         0
1984                 },
1985
1986                 {
1987                         /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1988                         /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1989                         /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1990                         0
1991                 },
1992
1993                 {
1994                         /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1995                         /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1996                         /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1997                         /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1998                 }
1999         },
2000         .ctlPowerData_2G = {
2001                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2002                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2003                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2004
2005                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2006                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2007                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2008
2009                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2010                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2011                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2012
2013                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2014                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2015                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2016         },
2017         .modalHeader5G = {
2018                 /* 4 idle,t1,t2,b (4 bits per setting) */
2019                 .antCtrlCommon = LE32(0x110),
2020                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2021                 .antCtrlCommon2 = LE32(0x22222),
2022                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2023                 .antCtrlChain = {
2024                         LE16(0x0), LE16(0x0), LE16(0x0),
2025                 },
2026                 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2027                 .xatten1DB = {0x13, 0x19, 0x17},
2028
2029                 /*
2030                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2031                  * for merlin (0xa20c/b20c 16:12
2032                  */
2033                 .xatten1Margin = {0x19, 0x19, 0x19},
2034                 .tempSlope = 70,
2035                 .voltSlope = 15,
2036                 /* spurChans spur channels in usual fbin coding format */
2037                 .spurChans = {0, 0, 0, 0, 0},
2038                 /* noiseFloorThreshch check if the register is per chain */
2039                 .noiseFloorThreshCh = {-1, 0, 0},
2040                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2041                 .quick_drop = 0,
2042                 .xpaBiasLvl = 0,
2043                 .txFrameToDataStart = 0x0e,
2044                 .txFrameToPaOn = 0x0e,
2045                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2046                 .antennaGain = 0,
2047                 .switchSettling = 0x2d,
2048                 .adcDesiredSize = -30,
2049                 .txEndToXpaOff = 0,
2050                 .txEndToRxOn = 0x2,
2051                 .txFrameToXpaOn = 0xe,
2052                 .thresh62 = 28,
2053                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2054                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2055                 .futureModal = {
2056                         0, 0, 0, 0, 0, 0, 0, 0,
2057                 },
2058         },
2059         .base_ext2 = {
2060                 .tempSlopeLow = 72,
2061                 .tempSlopeHigh = 105,
2062                 .xatten1DBLow = {0x10, 0x14, 0x10},
2063                 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2064                 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2065                 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2066         },
2067         .calFreqPier5G = {
2068                 FREQ2FBIN(5180, 0),
2069                 FREQ2FBIN(5220, 0),
2070                 FREQ2FBIN(5320, 0),
2071                 FREQ2FBIN(5400, 0),
2072                 FREQ2FBIN(5500, 0),
2073                 FREQ2FBIN(5600, 0),
2074                 FREQ2FBIN(5700, 0),
2075                 FREQ2FBIN(5785, 0)
2076         },
2077         .calPierData5G = {
2078                 {
2079                         {0, 0, 0, 0, 0},
2080                         {0, 0, 0, 0, 0},
2081                         {0, 0, 0, 0, 0},
2082                         {0, 0, 0, 0, 0},
2083                         {0, 0, 0, 0, 0},
2084                         {0, 0, 0, 0, 0},
2085                         {0, 0, 0, 0, 0},
2086                         {0, 0, 0, 0, 0},
2087                 },
2088                 {
2089                         {0, 0, 0, 0, 0},
2090                         {0, 0, 0, 0, 0},
2091                         {0, 0, 0, 0, 0},
2092                         {0, 0, 0, 0, 0},
2093                         {0, 0, 0, 0, 0},
2094                         {0, 0, 0, 0, 0},
2095                         {0, 0, 0, 0, 0},
2096                         {0, 0, 0, 0, 0},
2097                 },
2098                 {
2099                         {0, 0, 0, 0, 0},
2100                         {0, 0, 0, 0, 0},
2101                         {0, 0, 0, 0, 0},
2102                         {0, 0, 0, 0, 0},
2103                         {0, 0, 0, 0, 0},
2104                         {0, 0, 0, 0, 0},
2105                         {0, 0, 0, 0, 0},
2106                         {0, 0, 0, 0, 0},
2107                 },
2108
2109         },
2110         .calTarget_freqbin_5G = {
2111                 FREQ2FBIN(5180, 0),
2112                 FREQ2FBIN(5220, 0),
2113                 FREQ2FBIN(5320, 0),
2114                 FREQ2FBIN(5400, 0),
2115                 FREQ2FBIN(5500, 0),
2116                 FREQ2FBIN(5600, 0),
2117                 FREQ2FBIN(5725, 0),
2118                 FREQ2FBIN(5825, 0)
2119         },
2120         .calTarget_freqbin_5GHT20 = {
2121                 FREQ2FBIN(5180, 0),
2122                 FREQ2FBIN(5220, 0),
2123                 FREQ2FBIN(5320, 0),
2124                 FREQ2FBIN(5400, 0),
2125                 FREQ2FBIN(5500, 0),
2126                 FREQ2FBIN(5600, 0),
2127                 FREQ2FBIN(5725, 0),
2128                 FREQ2FBIN(5825, 0)
2129         },
2130         .calTarget_freqbin_5GHT40 = {
2131                 FREQ2FBIN(5180, 0),
2132                 FREQ2FBIN(5220, 0),
2133                 FREQ2FBIN(5320, 0),
2134                 FREQ2FBIN(5400, 0),
2135                 FREQ2FBIN(5500, 0),
2136                 FREQ2FBIN(5600, 0),
2137                 FREQ2FBIN(5725, 0),
2138                 FREQ2FBIN(5825, 0)
2139         },
2140         .calTargetPower5G = {
2141                 /* 6-24,36,48,54 */
2142                 { {32, 32, 28, 26} },
2143                 { {32, 32, 28, 26} },
2144                 { {32, 32, 28, 26} },
2145                 { {32, 32, 26, 24} },
2146                 { {32, 32, 26, 24} },
2147                 { {32, 32, 24, 22} },
2148                 { {30, 30, 24, 22} },
2149                 { {30, 30, 24, 22} },
2150         },
2151         .calTargetPower5GHT20 = {
2152                 /*
2153                  * 0_8_16,1-3_9-11_17-19,
2154                  * 4,5,6,7,12,13,14,15,20,21,22,23
2155                  */
2156                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2157                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2158                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2159                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2160                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2161                 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2162                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2163                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2164         },
2165         .calTargetPower5GHT40 =  {
2166                 /*
2167                  * 0_8_16,1-3_9-11_17-19,
2168                  * 4,5,6,7,12,13,14,15,20,21,22,23
2169                  */
2170                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2171                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2172                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2173                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2174                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2175                 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2176                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2177                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2178         },
2179         .ctlIndex_5G =  {
2180                 0x10, 0x16, 0x18, 0x40, 0x46,
2181                 0x48, 0x30, 0x36, 0x38
2182         },
2183         .ctl_freqbin_5G =  {
2184                 {
2185                         /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2186                         /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2187                         /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2188                         /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2189                         /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2190                         /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2191                         /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2192                         /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2193                 },
2194                 {
2195                         /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2196                         /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2197                         /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2198                         /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2199                         /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2200                         /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2201                         /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2202                         /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2203                 },
2204
2205                 {
2206                         /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2207                         /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2208                         /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2209                         /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2210                         /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2211                         /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2212                         /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2213                         /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2214                 },
2215
2216                 {
2217                         /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2218                         /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2219                         /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2220                         /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2221                         /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2222                         /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2223                         /* Data[3].ctledges[6].bchannel */ 0xFF,
2224                         /* Data[3].ctledges[7].bchannel */ 0xFF,
2225                 },
2226
2227                 {
2228                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2231                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2232                         /* Data[4].ctledges[4].bchannel */ 0xFF,
2233                         /* Data[4].ctledges[5].bchannel */ 0xFF,
2234                         /* Data[4].ctledges[6].bchannel */ 0xFF,
2235                         /* Data[4].ctledges[7].bchannel */ 0xFF,
2236                 },
2237
2238                 {
2239                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2241                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2242                         /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2243                         /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2244                         /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2245                         /* Data[5].ctledges[6].bchannel */ 0xFF,
2246                         /* Data[5].ctledges[7].bchannel */ 0xFF
2247                 },
2248
2249                 {
2250                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252                         /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2253                         /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2254                         /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255                         /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2256                         /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2257                         /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2258                 },
2259
2260                 {
2261                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2264                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2265                         /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2266                         /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2267                         /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2268                         /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2269                 },
2270
2271                 {
2272                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2274                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2275                         /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276                         /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2277                         /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278                         /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2279                         /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2280                 }
2281         },
2282         .ctlPowerData_5G = {
2283                 {
2284                         {
2285                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2286                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2287                         }
2288                 },
2289                 {
2290                         {
2291                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2292                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2293                         }
2294                 },
2295                 {
2296                         {
2297                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2298                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2299                         }
2300                 },
2301                 {
2302                         {
2303                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2304                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2305                         }
2306                 },
2307                 {
2308                         {
2309                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2310                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2311                         }
2312                 },
2313                 {
2314                         {
2315                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2316                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2317                         }
2318                 },
2319                 {
2320                         {
2321                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2322                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2323                         }
2324                 },
2325                 {
2326                         {
2327                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2328                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2329                         }
2330                 },
2331                 {
2332                         {
2333                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2334                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2335                         }
2336                 },
2337         }
2338 };
2339
2340 static const struct ar9300_eeprom ar9300_h116 = {
2341         .eepromVersion = 2,
2342         .templateVersion = 4,
2343         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2344         .custData = {"h116-041-f0000"},
2345         .baseEepHeader = {
2346                 .regDmn = { LE16(0), LE16(0x1f) },
2347                 .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
2348                 .opCapFlags = {
2349                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2350                         .eepMisc = 0,
2351                 },
2352                 .rfSilent = 0,
2353                 .blueToothOptions = 0,
2354                 .deviceCap = 0,
2355                 .deviceType = 5, /* takes lower byte in eeprom location */
2356                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2357                 .params_for_tuning_caps = {0, 0},
2358                 .featureEnable = 0x0d,
2359                  /*
2360                   * bit0 - enable tx temp comp - disabled
2361                   * bit1 - enable tx volt comp - disabled
2362                   * bit2 - enable fastClock - enabled
2363                   * bit3 - enable doubling - enabled
2364                   * bit4 - enable internal regulator - disabled
2365                   * bit5 - enable pa predistortion - disabled
2366                   */
2367                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2368                 .eepromWriteEnableGpio = 6,
2369                 .wlanDisableGpio = 0,
2370                 .wlanLedGpio = 8,
2371                 .rxBandSelectGpio = 0xff,
2372                 .txrxgain = 0x10,
2373                 .swreg = 0,
2374          },
2375         .modalHeader2G = {
2376         /* ar9300_modal_eep_header  2g */
2377                 /* 4 idle,t1,t2,b(4 bits per setting) */
2378                 .antCtrlCommon = LE32(0x110),
2379                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2380                 .antCtrlCommon2 = LE32(0x44444),
2381
2382                 /*
2383                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2384                  * rx1, rx12, b (2 bits each)
2385                  */
2386                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2387
2388                 /*
2389                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
2390                  * for ar9280 (0xa20c/b20c 5:0)
2391                  */
2392                 .xatten1DB = {0x1f, 0x1f, 0x1f},
2393
2394                 /*
2395                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2396                  * for ar9280 (0xa20c/b20c 16:12
2397                  */
2398                 .xatten1Margin = {0x12, 0x12, 0x12},
2399                 .tempSlope = 25,
2400                 .voltSlope = 0,
2401
2402                 /*
2403                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2404                  * channels in usual fbin coding format
2405                  */
2406                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2407
2408                 /*
2409                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2410                  * if the register is per chain
2411                  */
2412                 .noiseFloorThreshCh = {-1, 0, 0},
2413                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2414                 .quick_drop = 0,
2415                 .xpaBiasLvl = 0,
2416                 .txFrameToDataStart = 0x0e,
2417                 .txFrameToPaOn = 0x0e,
2418                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2419                 .antennaGain = 0,
2420                 .switchSettling = 0x2c,
2421                 .adcDesiredSize = -30,
2422                 .txEndToXpaOff = 0,
2423                 .txEndToRxOn = 0x2,
2424                 .txFrameToXpaOn = 0xe,
2425                 .thresh62 = 28,
2426                 .papdRateMaskHt20 = LE32(0x0c80C080),
2427                 .papdRateMaskHt40 = LE32(0x0080C080),
2428                 .futureModal = {
2429                         0, 0, 0, 0, 0, 0, 0, 0,
2430                 },
2431          },
2432          .base_ext1 = {
2433                 .ant_div_control = 0,
2434                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2435          },
2436         .calFreqPier2G = {
2437                 FREQ2FBIN(2412, 1),
2438                 FREQ2FBIN(2437, 1),
2439                 FREQ2FBIN(2462, 1),
2440          },
2441         /* ar9300_cal_data_per_freq_op_loop 2g */
2442         .calPierData2G = {
2443                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2444                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2445                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2446          },
2447         .calTarget_freqbin_Cck = {
2448                 FREQ2FBIN(2412, 1),
2449                 FREQ2FBIN(2472, 1),
2450          },
2451         .calTarget_freqbin_2G = {
2452                 FREQ2FBIN(2412, 1),
2453                 FREQ2FBIN(2437, 1),
2454                 FREQ2FBIN(2472, 1)
2455          },
2456         .calTarget_freqbin_2GHT20 = {
2457                 FREQ2FBIN(2412, 1),
2458                 FREQ2FBIN(2437, 1),
2459                 FREQ2FBIN(2472, 1)
2460          },
2461         .calTarget_freqbin_2GHT40 = {
2462                 FREQ2FBIN(2412, 1),
2463                 FREQ2FBIN(2437, 1),
2464                 FREQ2FBIN(2472, 1)
2465          },
2466         .calTargetPowerCck = {
2467                  /* 1L-5L,5S,11L,11S */
2468                  { {34, 34, 34, 34} },
2469                  { {34, 34, 34, 34} },
2470         },
2471         .calTargetPower2G = {
2472                  /* 6-24,36,48,54 */
2473                  { {34, 34, 32, 32} },
2474                  { {34, 34, 32, 32} },
2475                  { {34, 34, 32, 32} },
2476         },
2477         .calTargetPower2GHT20 = {
2478                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2479                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2480                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2481         },
2482         .calTargetPower2GHT40 = {
2483                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2484                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2485                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2486         },
2487         .ctlIndex_2G =  {
2488                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2489                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2490         },
2491         .ctl_freqbin_2G = {
2492                 {
2493                         FREQ2FBIN(2412, 1),
2494                         FREQ2FBIN(2417, 1),
2495                         FREQ2FBIN(2457, 1),
2496                         FREQ2FBIN(2462, 1)
2497                 },
2498                 {
2499                         FREQ2FBIN(2412, 1),
2500                         FREQ2FBIN(2417, 1),
2501                         FREQ2FBIN(2462, 1),
2502                         0xFF,
2503                 },
2504
2505                 {
2506                         FREQ2FBIN(2412, 1),
2507                         FREQ2FBIN(2417, 1),
2508                         FREQ2FBIN(2462, 1),
2509                         0xFF,
2510                 },
2511                 {
2512                         FREQ2FBIN(2422, 1),
2513                         FREQ2FBIN(2427, 1),
2514                         FREQ2FBIN(2447, 1),
2515                         FREQ2FBIN(2452, 1)
2516                 },
2517
2518                 {
2519                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2520                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2521                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2522                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2523                 },
2524
2525                 {
2526                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2527                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2528                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2529                         0,
2530                 },
2531
2532                 {
2533                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2534                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2535                         FREQ2FBIN(2472, 1),
2536                         0,
2537                 },
2538
2539                 {
2540                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2541                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2542                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2543                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2544                 },
2545
2546                 {
2547                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2548                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2549                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2550                 },
2551
2552                 {
2553                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2554                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2555                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2556                         0
2557                 },
2558
2559                 {
2560                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2561                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2562                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2563                         0
2564                 },
2565
2566                 {
2567                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2568                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2569                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2570                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2571                 }
2572          },
2573         .ctlPowerData_2G = {
2574                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2575                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2576                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2577
2578                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2579                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2580                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2581
2582                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2583                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2584                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2585
2586                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2587                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2588                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2589          },
2590         .modalHeader5G = {
2591                 /* 4 idle,t1,t2,b (4 bits per setting) */
2592                 .antCtrlCommon = LE32(0x220),
2593                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2594                 .antCtrlCommon2 = LE32(0x44444),
2595                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2596                 .antCtrlChain = {
2597                         LE16(0x150), LE16(0x150), LE16(0x150),
2598                 },
2599                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2600                 .xatten1DB = {0x19, 0x19, 0x19},
2601
2602                 /*
2603                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2604                  * for merlin (0xa20c/b20c 16:12
2605                  */
2606                 .xatten1Margin = {0x14, 0x14, 0x14},
2607                 .tempSlope = 70,
2608                 .voltSlope = 0,
2609                 /* spurChans spur channels in usual fbin coding format */
2610                 .spurChans = {0, 0, 0, 0, 0},
2611                 /* noiseFloorThreshCh Check if the register is per chain */
2612                 .noiseFloorThreshCh = {-1, 0, 0},
2613                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2614                 .quick_drop = 0,
2615                 .xpaBiasLvl = 0,
2616                 .txFrameToDataStart = 0x0e,
2617                 .txFrameToPaOn = 0x0e,
2618                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2619                 .antennaGain = 0,
2620                 .switchSettling = 0x2d,
2621                 .adcDesiredSize = -30,
2622                 .txEndToXpaOff = 0,
2623                 .txEndToRxOn = 0x2,
2624                 .txFrameToXpaOn = 0xe,
2625                 .thresh62 = 28,
2626                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2627                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2628                 .futureModal = {
2629                         0, 0, 0, 0, 0, 0, 0, 0,
2630                 },
2631          },
2632         .base_ext2 = {
2633                 .tempSlopeLow = 35,
2634                 .tempSlopeHigh = 50,
2635                 .xatten1DBLow = {0, 0, 0},
2636                 .xatten1MarginLow = {0, 0, 0},
2637                 .xatten1DBHigh = {0, 0, 0},
2638                 .xatten1MarginHigh = {0, 0, 0}
2639          },
2640         .calFreqPier5G = {
2641                 FREQ2FBIN(5160, 0),
2642                 FREQ2FBIN(5220, 0),
2643                 FREQ2FBIN(5320, 0),
2644                 FREQ2FBIN(5400, 0),
2645                 FREQ2FBIN(5500, 0),
2646                 FREQ2FBIN(5600, 0),
2647                 FREQ2FBIN(5700, 0),
2648                 FREQ2FBIN(5785, 0)
2649         },
2650         .calPierData5G = {
2651                         {
2652                                 {0, 0, 0, 0, 0},
2653                                 {0, 0, 0, 0, 0},
2654                                 {0, 0, 0, 0, 0},
2655                                 {0, 0, 0, 0, 0},
2656                                 {0, 0, 0, 0, 0},
2657                                 {0, 0, 0, 0, 0},
2658                                 {0, 0, 0, 0, 0},
2659                                 {0, 0, 0, 0, 0},
2660                         },
2661                         {
2662                                 {0, 0, 0, 0, 0},
2663                                 {0, 0, 0, 0, 0},
2664                                 {0, 0, 0, 0, 0},
2665                                 {0, 0, 0, 0, 0},
2666                                 {0, 0, 0, 0, 0},
2667                                 {0, 0, 0, 0, 0},
2668                                 {0, 0, 0, 0, 0},
2669                                 {0, 0, 0, 0, 0},
2670                         },
2671                         {
2672                                 {0, 0, 0, 0, 0},
2673                                 {0, 0, 0, 0, 0},
2674                                 {0, 0, 0, 0, 0},
2675                                 {0, 0, 0, 0, 0},
2676                                 {0, 0, 0, 0, 0},
2677                                 {0, 0, 0, 0, 0},
2678                                 {0, 0, 0, 0, 0},
2679                                 {0, 0, 0, 0, 0},
2680                         },
2681
2682         },
2683         .calTarget_freqbin_5G = {
2684                 FREQ2FBIN(5180, 0),
2685                 FREQ2FBIN(5240, 0),
2686                 FREQ2FBIN(5320, 0),
2687                 FREQ2FBIN(5400, 0),
2688                 FREQ2FBIN(5500, 0),
2689                 FREQ2FBIN(5600, 0),
2690                 FREQ2FBIN(5700, 0),
2691                 FREQ2FBIN(5825, 0)
2692         },
2693         .calTarget_freqbin_5GHT20 = {
2694                 FREQ2FBIN(5180, 0),
2695                 FREQ2FBIN(5240, 0),
2696                 FREQ2FBIN(5320, 0),
2697                 FREQ2FBIN(5400, 0),
2698                 FREQ2FBIN(5500, 0),
2699                 FREQ2FBIN(5700, 0),
2700                 FREQ2FBIN(5745, 0),
2701                 FREQ2FBIN(5825, 0)
2702         },
2703         .calTarget_freqbin_5GHT40 = {
2704                 FREQ2FBIN(5180, 0),
2705                 FREQ2FBIN(5240, 0),
2706                 FREQ2FBIN(5320, 0),
2707                 FREQ2FBIN(5400, 0),
2708                 FREQ2FBIN(5500, 0),
2709                 FREQ2FBIN(5700, 0),
2710                 FREQ2FBIN(5745, 0),
2711                 FREQ2FBIN(5825, 0)
2712          },
2713         .calTargetPower5G = {
2714                 /* 6-24,36,48,54 */
2715                 { {30, 30, 28, 24} },
2716                 { {30, 30, 28, 24} },
2717                 { {30, 30, 28, 24} },
2718                 { {30, 30, 28, 24} },
2719                 { {30, 30, 28, 24} },
2720                 { {30, 30, 28, 24} },
2721                 { {30, 30, 28, 24} },
2722                 { {30, 30, 28, 24} },
2723          },
2724         .calTargetPower5GHT20 = {
2725                 /*
2726                  * 0_8_16,1-3_9-11_17-19,
2727                  * 4,5,6,7,12,13,14,15,20,21,22,23
2728                  */
2729                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2730                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2731                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2732                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2733                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2734                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2735                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2736                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2737          },
2738         .calTargetPower5GHT40 =  {
2739                 /*
2740                  * 0_8_16,1-3_9-11_17-19,
2741                  * 4,5,6,7,12,13,14,15,20,21,22,23
2742                  */
2743                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2744                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2745                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2746                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2747                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2748                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2749                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2750                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2751          },
2752         .ctlIndex_5G =  {
2753                 0x10, 0x16, 0x18, 0x40, 0x46,
2754                 0x48, 0x30, 0x36, 0x38
2755         },
2756         .ctl_freqbin_5G =  {
2757                 {
2758                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2759                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2760                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2761                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2762                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2763                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2764                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2765                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2766                 },
2767                 {
2768                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2769                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2770                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2771                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2772                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2773                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2774                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2775                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2776                 },
2777
2778                 {
2779                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2780                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2781                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2782                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2783                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2784                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2785                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2786                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2787                 },
2788
2789                 {
2790                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2791                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2792                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2793                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2794                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2795                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2796                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2797                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2798                 },
2799
2800                 {
2801                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2802                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2803                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2804                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2805                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2806                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2807                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2808                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2809                 },
2810
2811                 {
2812                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2813                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2814                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2815                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2816                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2817                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2818                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2819                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
2820                 },
2821
2822                 {
2823                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2824                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2825                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2826                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2827                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2828                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2829                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2830                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2831                 },
2832
2833                 {
2834                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2835                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2836                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2837                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2838                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2839                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2840                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2841                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2842                 },
2843
2844                 {
2845                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2846                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2847                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2848                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2849                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2850                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2851                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2852                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2853                 }
2854          },
2855         .ctlPowerData_5G = {
2856                 {
2857                         {
2858                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2859                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2860                         }
2861                 },
2862                 {
2863                         {
2864                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2865                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2866                         }
2867                 },
2868                 {
2869                         {
2870                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2871                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2872                         }
2873                 },
2874                 {
2875                         {
2876                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2877                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2878                         }
2879                 },
2880                 {
2881                         {
2882                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2883                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2884                         }
2885                 },
2886                 {
2887                         {
2888                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2889                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2890                         }
2891                 },
2892                 {
2893                         {
2894                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2895                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2896                         }
2897                 },
2898                 {
2899                         {
2900                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2901                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2902                         }
2903                 },
2904                 {
2905                         {
2906                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2907                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2908                         }
2909                 },
2910          }
2911 };
2912
2913
2914 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2915         &ar9300_default,
2916         &ar9300_x112,
2917         &ar9300_h116,
2918         &ar9300_h112,
2919         &ar9300_x113,
2920 };
2921
2922 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2923 {
2924 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2925         int it;
2926
2927         for (it = 0; it < N_LOOP; it++)
2928                 if (ar9300_eep_templates[it]->templateVersion == id)
2929                         return ar9300_eep_templates[it];
2930         return NULL;
2931 #undef N_LOOP
2932 }
2933
2934 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2935 {
2936         return 0;
2937 }
2938
2939 static int interpolate(int x, int xa, int xb, int ya, int yb)
2940 {
2941         int bf, factor, plus;
2942
2943         bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2944         factor = bf / 2;
2945         plus = bf % 2;
2946         return ya + factor + plus;
2947 }
2948
2949 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2950                                       enum eeprom_param param)
2951 {
2952         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2953         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2954
2955         switch (param) {
2956         case EEP_MAC_LSW:
2957                 return get_unaligned_be16(eep->macAddr);
2958         case EEP_MAC_MID:
2959                 return get_unaligned_be16(eep->macAddr + 2);
2960         case EEP_MAC_MSW:
2961                 return get_unaligned_be16(eep->macAddr + 4);
2962         case EEP_REG_0:
2963                 return le16_to_cpu(pBase->regDmn[0]);
2964         case EEP_OP_CAP:
2965                 return pBase->deviceCap;
2966         case EEP_OP_MODE:
2967                 return pBase->opCapFlags.opFlags;
2968         case EEP_RF_SILENT:
2969                 return pBase->rfSilent;
2970         case EEP_TX_MASK:
2971                 return (pBase->txrxMask >> 4) & 0xf;
2972         case EEP_RX_MASK:
2973                 return pBase->txrxMask & 0xf;
2974         case EEP_PAPRD:
2975                 return !!(pBase->featureEnable & BIT(5));
2976         case EEP_CHAIN_MASK_REDUCE:
2977                 return (pBase->miscConfiguration >> 0x3) & 0x1;
2978         case EEP_ANT_DIV_CTL1:
2979                 return eep->base_ext1.ant_div_control;
2980         case EEP_ANTENNA_GAIN_5G:
2981                 return eep->modalHeader5G.antennaGain;
2982         case EEP_ANTENNA_GAIN_2G:
2983                 return eep->modalHeader2G.antennaGain;
2984         default:
2985                 return 0;
2986         }
2987 }
2988
2989 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
2990                                     u8 *buffer)
2991 {
2992         u16 val;
2993
2994         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
2995                 return false;
2996
2997         *buffer = (val >> (8 * (address % 2))) & 0xff;
2998         return true;
2999 }
3000
3001 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3002                                     u8 *buffer)
3003 {
3004         u16 val;
3005
3006         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3007                 return false;
3008
3009         buffer[0] = val >> 8;
3010         buffer[1] = val & 0xff;
3011
3012         return true;
3013 }
3014
3015 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3016                                int count)
3017 {
3018         struct ath_common *common = ath9k_hw_common(ah);
3019         int i;
3020
3021         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3022                 ath_dbg(common, EEPROM, "eeprom address not in range\n");
3023                 return false;
3024         }
3025
3026         /*
3027          * Since we're reading the bytes in reverse order from a little-endian
3028          * word stream, an even address means we only use the lower half of
3029          * the 16-bit word at that address
3030          */
3031         if (address % 2 == 0) {
3032                 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3033                         goto error;
3034
3035                 count--;
3036         }
3037
3038         for (i = 0; i < count / 2; i++) {
3039                 if (!ar9300_eeprom_read_word(common, address, buffer))
3040                         goto error;
3041
3042                 address -= 2;
3043                 buffer += 2;
3044         }
3045
3046         if (count % 2)
3047                 if (!ar9300_eeprom_read_byte(common, address, buffer))
3048                         goto error;
3049
3050         return true;
3051
3052 error:
3053         ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3054                 address);
3055         return false;
3056 }
3057
3058 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3059 {
3060         REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3061
3062         if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3063                            AR9300_OTP_STATUS_VALID, 1000))
3064                 return false;
3065
3066         *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3067         return true;
3068 }
3069
3070 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3071                             int count)
3072 {
3073         u32 data;
3074         int i;
3075
3076         for (i = 0; i < count; i++) {
3077                 int offset = 8 * ((address - i) % 4);
3078                 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3079                         return false;
3080
3081                 buffer[i] = (data >> offset) & 0xff;
3082         }
3083
3084         return true;
3085 }
3086
3087
3088 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3089                                    int *length, int *major, int *minor)
3090 {
3091         unsigned long value[4];
3092
3093         value[0] = best[0];
3094         value[1] = best[1];
3095         value[2] = best[2];
3096         value[3] = best[3];
3097         *code = ((value[0] >> 5) & 0x0007);
3098         *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3099         *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3100         *major = (value[2] & 0x000f);
3101         *minor = (value[3] & 0x00ff);
3102 }
3103
3104 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3105 {
3106         int it, checksum = 0;
3107
3108         for (it = 0; it < dsize; it++) {
3109                 checksum += data[it];
3110                 checksum &= 0xffff;
3111         }
3112
3113         return checksum;
3114 }
3115
3116 static bool ar9300_uncompress_block(struct ath_hw *ah,
3117                                     u8 *mptr,
3118                                     int mdataSize,
3119                                     u8 *block,
3120                                     int size)
3121 {
3122         int it;
3123         int spot;
3124         int offset;
3125         int length;
3126         struct ath_common *common = ath9k_hw_common(ah);
3127
3128         spot = 0;
3129
3130         for (it = 0; it < size; it += (length+2)) {
3131                 offset = block[it];
3132                 offset &= 0xff;
3133                 spot += offset;
3134                 length = block[it+1];
3135                 length &= 0xff;
3136
3137                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3138                         ath_dbg(common, EEPROM,
3139                                 "Restore at %d: spot=%d offset=%d length=%d\n",
3140                                 it, spot, offset, length);
3141                         memcpy(&mptr[spot], &block[it+2], length);
3142                         spot += length;
3143                 } else if (length > 0) {
3144                         ath_dbg(common, EEPROM,
3145                                 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3146                                 it, spot, offset, length);
3147                         return false;
3148                 }
3149         }
3150         return true;
3151 }
3152
3153 static int ar9300_compress_decision(struct ath_hw *ah,
3154                                     int it,
3155                                     int code,
3156                                     int reference,
3157                                     u8 *mptr,
3158                                     u8 *word, int length, int mdata_size)
3159 {
3160         struct ath_common *common = ath9k_hw_common(ah);
3161         const struct ar9300_eeprom *eep = NULL;
3162
3163         switch (code) {
3164         case _CompressNone:
3165                 if (length != mdata_size) {
3166                         ath_dbg(common, EEPROM,
3167                                 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3168                                 mdata_size, length);
3169                         return -1;
3170                 }
3171                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3172                 ath_dbg(common, EEPROM,
3173                         "restored eeprom %d: uncompressed, length %d\n",
3174                         it, length);
3175                 break;
3176         case _CompressBlock:
3177                 if (reference == 0) {
3178                 } else {
3179                         eep = ar9003_eeprom_struct_find_by_id(reference);
3180                         if (eep == NULL) {
3181                                 ath_dbg(common, EEPROM,
3182                                         "can't find reference eeprom struct %d\n",
3183                                         reference);
3184                                 return -1;
3185                         }
3186                         memcpy(mptr, eep, mdata_size);
3187                 }
3188                 ath_dbg(common, EEPROM,
3189                         "restore eeprom %d: block, reference %d, length %d\n",
3190                         it, reference, length);
3191                 ar9300_uncompress_block(ah, mptr, mdata_size,
3192                                         (u8 *) (word + COMP_HDR_LEN), length);
3193                 break;
3194         default:
3195                 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
3196                 return -1;
3197         }
3198         return 0;
3199 }
3200
3201 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3202                                int count);
3203
3204 static bool ar9300_check_header(void *data)
3205 {
3206         u32 *word = data;
3207         return !(*word == 0 || *word == ~0);
3208 }
3209
3210 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3211                                        int base_addr)
3212 {
3213         u8 header[4];
3214
3215         if (!read(ah, base_addr, header, 4))
3216                 return false;
3217
3218         return ar9300_check_header(header);
3219 }
3220
3221 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3222                                        int mdata_size)
3223 {
3224         struct ath_common *common = ath9k_hw_common(ah);
3225         u16 *data = (u16 *) mptr;
3226         int i;
3227
3228         for (i = 0; i < mdata_size / 2; i++, data++)
3229                 ath9k_hw_nvram_read(common, i, data);
3230
3231         return 0;
3232 }
3233 /*
3234  * Read the configuration data from the eeprom.
3235  * The data can be put in any specified memory buffer.
3236  *
3237  * Returns -1 on error.
3238  * Returns address of next memory location on success.
3239  */
3240 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3241                                           u8 *mptr, int mdata_size)
3242 {
3243 #define MDEFAULT 15
3244 #define MSTATE 100
3245         int cptr;
3246         u8 *word;
3247         int code;
3248         int reference, length, major, minor;
3249         int osize;
3250         int it;
3251         u16 checksum, mchecksum;
3252         struct ath_common *common = ath9k_hw_common(ah);
3253         struct ar9300_eeprom *eep;
3254         eeprom_read_op read;
3255
3256         if (ath9k_hw_use_flash(ah)) {
3257                 u8 txrx;
3258
3259                 ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3260
3261                 /* check if eeprom contains valid data */
3262                 eep = (struct ar9300_eeprom *) mptr;
3263                 txrx = eep->baseEepHeader.txrxMask;
3264                 if (txrx != 0 && txrx != 0xff)
3265                         return 0;
3266         }
3267
3268         word = kzalloc(2048, GFP_KERNEL);
3269         if (!word)
3270                 return -ENOMEM;
3271
3272         memcpy(mptr, &ar9300_default, mdata_size);
3273
3274         read = ar9300_read_eeprom;
3275         if (AR_SREV_9485(ah))
3276                 cptr = AR9300_BASE_ADDR_4K;
3277         else if (AR_SREV_9330(ah))
3278                 cptr = AR9300_BASE_ADDR_512;
3279         else
3280                 cptr = AR9300_BASE_ADDR;
3281         ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3282                 cptr);
3283         if (ar9300_check_eeprom_header(ah, read, cptr))
3284                 goto found;
3285
3286         cptr = AR9300_BASE_ADDR_512;
3287         ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3288                 cptr);
3289         if (ar9300_check_eeprom_header(ah, read, cptr))
3290                 goto found;
3291
3292         read = ar9300_read_otp;
3293         cptr = AR9300_BASE_ADDR;
3294         ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3295         if (ar9300_check_eeprom_header(ah, read, cptr))
3296                 goto found;
3297
3298         cptr = AR9300_BASE_ADDR_512;
3299         ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3300         if (ar9300_check_eeprom_header(ah, read, cptr))
3301                 goto found;
3302
3303         goto fail;
3304
3305 found:
3306         ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
3307
3308         for (it = 0; it < MSTATE; it++) {
3309                 if (!read(ah, cptr, word, COMP_HDR_LEN))
3310                         goto fail;
3311
3312                 if (!ar9300_check_header(word))
3313                         break;
3314
3315                 ar9300_comp_hdr_unpack(word, &code, &reference,
3316                                        &length, &major, &minor);
3317                 ath_dbg(common, EEPROM,
3318                         "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3319                         cptr, code, reference, length, major, minor);
3320                 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3321                     (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3322                         ath_dbg(common, EEPROM, "Skipping bad header\n");
3323                         cptr -= COMP_HDR_LEN;
3324                         continue;
3325                 }
3326
3327                 osize = length;
3328                 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3329                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3330                 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3331                 ath_dbg(common, EEPROM, "checksum %x %x\n",
3332                         checksum, mchecksum);
3333                 if (checksum == mchecksum) {
3334                         ar9300_compress_decision(ah, it, code, reference, mptr,
3335                                                  word, length, mdata_size);
3336                 } else {
3337                         ath_dbg(common, EEPROM,
3338                                 "skipping block with bad checksum\n");
3339                 }
3340                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3341         }
3342
3343         kfree(word);
3344         return cptr;
3345
3346 fail:
3347         kfree(word);
3348         return -1;
3349 }
3350
3351 /*
3352  * Restore the configuration structure by reading the eeprom.
3353  * This function destroys any existing in-memory structure
3354  * content.
3355  */
3356 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3357 {
3358         u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3359
3360         if (ar9300_eeprom_restore_internal(ah, mptr,
3361                         sizeof(struct ar9300_eeprom)) < 0)
3362                 return false;
3363
3364         return true;
3365 }
3366
3367 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3368 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3369                                     struct ar9300_modal_eep_header *modal_hdr)
3370 {
3371         PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3372         PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3373         PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3374         PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3375         PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3376         PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3377         PR_EEP("Switch Settle", modal_hdr->switchSettling);
3378         PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3379         PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3380         PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3381         PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3382         PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3383         PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3384         PR_EEP("Temp Slope", modal_hdr->tempSlope);
3385         PR_EEP("Volt Slope", modal_hdr->voltSlope);
3386         PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3387         PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3388         PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3389         PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3390         PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3391         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3392         PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3393         PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3394         PR_EEP("Quick Drop", modal_hdr->quick_drop);
3395         PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
3396         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3397         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3398         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3399         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3400         PR_EEP("txClip", modal_hdr->txClip);
3401         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3402
3403         return len;
3404 }
3405
3406 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3407                                        u8 *buf, u32 len, u32 size)
3408 {
3409         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3410         struct ar9300_base_eep_hdr *pBase;
3411
3412         if (!dump_base_hdr) {
3413                 len += snprintf(buf + len, size - len,
3414                                 "%20s :\n", "2GHz modal Header");
3415                 len = ar9003_dump_modal_eeprom(buf, len, size,
3416                                                 &eep->modalHeader2G);
3417                 len += snprintf(buf + len, size - len,
3418                                 "%20s :\n", "5GHz modal Header");
3419                 len = ar9003_dump_modal_eeprom(buf, len, size,
3420                                                 &eep->modalHeader5G);
3421                 goto out;
3422         }
3423
3424         pBase = &eep->baseEepHeader;
3425
3426         PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3427         PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3428         PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3429         PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3430         PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3431         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3432                                 AR5416_OPFLAGS_11A));
3433         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3434                                 AR5416_OPFLAGS_11G));
3435         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3436                                         AR5416_OPFLAGS_N_2G_HT20));
3437         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3438                                         AR5416_OPFLAGS_N_2G_HT40));
3439         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3440                                         AR5416_OPFLAGS_N_5G_HT20));
3441         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3442                                         AR5416_OPFLAGS_N_5G_HT40));
3443         PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3444         PR_EEP("RF Silent", pBase->rfSilent);
3445         PR_EEP("BT option", pBase->blueToothOptions);
3446         PR_EEP("Device Cap", pBase->deviceCap);
3447         PR_EEP("Device Type", pBase->deviceType);
3448         PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3449         PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3450         PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3451         PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3452         PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3453         PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3454         PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3455         PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3456         PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3457         PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3458         PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
3459         PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3460         PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3461         PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3462         PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3463         PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3464         PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3465         PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3466         PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3467
3468         len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3469                         ah->eeprom.ar9300_eep.macAddr);
3470 out:
3471         if (len > size)
3472                 len = size;
3473
3474         return len;
3475 }
3476 #else
3477 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3478                                        u8 *buf, u32 len, u32 size)
3479 {
3480         return 0;
3481 }
3482 #endif
3483
3484 /* XXX: review hardware docs */
3485 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3486 {
3487         return ah->eeprom.ar9300_eep.eepromVersion;
3488 }
3489
3490 /* XXX: could be read from the eepromVersion, not sure yet */
3491 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3492 {
3493         return 0;
3494 }
3495
3496 static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
3497                                                            bool is2ghz)
3498 {
3499         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3500
3501         if (is2ghz)
3502                 return &eep->modalHeader2G;
3503         else
3504                 return &eep->modalHeader5G;
3505 }
3506
3507 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3508 {
3509         int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
3510
3511         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3512                 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3513         else if (AR_SREV_9462(ah) || AR_SREV_9550(ah))
3514                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3515         else {
3516                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3517                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3518                                 AR_CH0_THERM_XPABIASLVL_MSB,
3519                                 bias >> 2);
3520                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3521                                 AR_CH0_THERM_XPASHORT2GND, 1);
3522         }
3523 }
3524
3525 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
3526 {
3527         return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
3528 }
3529
3530
3531 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3532 {
3533         return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
3534 }
3535
3536 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3537 {
3538         return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
3539 }
3540
3541 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
3542                                         bool is2ghz)
3543 {
3544         __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
3545         return le16_to_cpu(val);
3546 }
3547
3548 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3549 {
3550         int chain;
3551         u32 regval;
3552         u32 ant_div_ctl1;
3553         static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3554                         AR_PHY_SWITCH_CHAIN_0,
3555                         AR_PHY_SWITCH_CHAIN_1,
3556                         AR_PHY_SWITCH_CHAIN_2,
3557         };
3558
3559         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3560
3561         if (AR_SREV_9462(ah)) {
3562                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3563                                 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3564         } else if (AR_SREV_9550(ah)) {
3565                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3566                                 AR_SWITCH_TABLE_COM_AR9550_ALL, value);
3567         } else
3568                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3569                               AR_SWITCH_TABLE_COM_ALL, value);
3570
3571
3572         /*
3573          *   AR9462 defines new switch table for BT/WLAN,
3574          *       here's new field name in XXX.ref for both 2G and 5G.
3575          *   Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3576          *   15:12   R/W     SWITCH_TABLE_COM_SPDT_WLAN_RX
3577          * SWITCH_TABLE_COM_SPDT_WLAN_RX
3578          *
3579          *   11:8     R/W     SWITCH_TABLE_COM_SPDT_WLAN_TX
3580          * SWITCH_TABLE_COM_SPDT_WLAN_TX
3581          *
3582          *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3583          * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3584          */
3585         if (AR_SREV_9462_20_OR_LATER(ah)) {
3586                 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3587                 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3588                                 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3589                 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
3590         }
3591
3592         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3593         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3594
3595         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3596                 if ((ah->rxchainmask & BIT(chain)) ||
3597                     (ah->txchainmask & BIT(chain))) {
3598                         value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3599                                                              is2ghz);
3600                         REG_RMW_FIELD(ah, switch_chain_reg[chain],
3601                                       AR_SWITCH_TABLE_ALL, value);
3602                 }
3603         }
3604
3605         if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3606                 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3607                 /*
3608                  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3609                  * are the fields present
3610                  */
3611                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3612                 regval &= (~AR_ANT_DIV_CTRL_ALL);
3613                 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3614                 /* enable_lnadiv */
3615                 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3616                 regval |= ((value >> 6) & 0x1) <<
3617                                 AR_PHY_9485_ANT_DIV_LNADIV_S;
3618                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3619
3620                 /*enable fast_div */
3621                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3622                 regval &= (~AR_FAST_DIV_ENABLE);
3623                 regval |= ((value >> 7) & 0x1) <<
3624                                 AR_FAST_DIV_ENABLE_S;
3625                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3626                 ant_div_ctl1 =
3627                         ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3628                 /* check whether antenna diversity is enabled */
3629                 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3630                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3631                         /*
3632                          * clear bits 25-30 main_lnaconf, alt_lnaconf,
3633                          * main_tb, alt_tb
3634                          */
3635                         regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3636                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3637                                         AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3638                                         AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3639                         /* by default use LNA1 for the main antenna */
3640                         regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3641                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3642                         regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3643                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3644                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3645                 }
3646
3647
3648         }
3649
3650 }
3651
3652 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3653 {
3654         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3655         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3656         int drive_strength;
3657         unsigned long reg;
3658
3659         drive_strength = pBase->miscConfiguration & BIT(0);
3660         if (!drive_strength)
3661                 return;
3662
3663         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3664         reg &= ~0x00ffffc0;
3665         reg |= 0x5 << 21;
3666         reg |= 0x5 << 18;
3667         reg |= 0x5 << 15;
3668         reg |= 0x5 << 12;
3669         reg |= 0x5 << 9;
3670         reg |= 0x5 << 6;
3671         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3672
3673         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3674         reg &= ~0xffffffe0;
3675         reg |= 0x5 << 29;
3676         reg |= 0x5 << 26;
3677         reg |= 0x5 << 23;
3678         reg |= 0x5 << 20;
3679         reg |= 0x5 << 17;
3680         reg |= 0x5 << 14;
3681         reg |= 0x5 << 11;
3682         reg |= 0x5 << 8;
3683         reg |= 0x5 << 5;
3684         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3685
3686         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3687         reg &= ~0xff800000;
3688         reg |= 0x5 << 29;
3689         reg |= 0x5 << 26;
3690         reg |= 0x5 << 23;
3691         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3692 }
3693
3694 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3695                                      struct ath9k_channel *chan)
3696 {
3697         int f[3], t[3];
3698         u16 value;
3699         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3700
3701         if (chain >= 0 && chain < 3) {
3702                 if (IS_CHAN_2GHZ(chan))
3703                         return eep->modalHeader2G.xatten1DB[chain];
3704                 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3705                         t[0] = eep->base_ext2.xatten1DBLow[chain];
3706                         f[0] = 5180;
3707                         t[1] = eep->modalHeader5G.xatten1DB[chain];
3708                         f[1] = 5500;
3709                         t[2] = eep->base_ext2.xatten1DBHigh[chain];
3710                         f[2] = 5785;
3711                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3712                                                             f, t, 3);
3713                         return value;
3714                 } else
3715                         return eep->modalHeader5G.xatten1DB[chain];
3716         }
3717
3718         return 0;
3719 }
3720
3721
3722 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3723                                             struct ath9k_channel *chan)
3724 {
3725         int f[3], t[3];
3726         u16 value;
3727         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3728
3729         if (chain >= 0 && chain < 3) {
3730                 if (IS_CHAN_2GHZ(chan))
3731                         return eep->modalHeader2G.xatten1Margin[chain];
3732                 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3733                         t[0] = eep->base_ext2.xatten1MarginLow[chain];
3734                         f[0] = 5180;
3735                         t[1] = eep->modalHeader5G.xatten1Margin[chain];
3736                         f[1] = 5500;
3737                         t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3738                         f[2] = 5785;
3739                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3740                                                             f, t, 3);
3741                         return value;
3742                 } else
3743                         return eep->modalHeader5G.xatten1Margin[chain];
3744         }
3745
3746         return 0;
3747 }
3748
3749 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3750 {
3751         int i;
3752         u16 value;
3753         unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3754                                           AR_PHY_EXT_ATTEN_CTL_1,
3755                                           AR_PHY_EXT_ATTEN_CTL_2,
3756                                          };
3757
3758         /* Test value. if 0 then attenuation is unused. Don't load anything. */
3759         for (i = 0; i < 3; i++) {
3760                 if (ah->txchainmask & BIT(i)) {
3761                         value = ar9003_hw_atten_chain_get(ah, i, chan);
3762                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3763                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3764
3765                         value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3766                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3767                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3768                                       value);
3769                 }
3770         }
3771 }
3772
3773 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3774 {
3775         int timeout = 100;
3776
3777         while (pmu_set != REG_READ(ah, pmu_reg)) {
3778                 if (timeout-- == 0)
3779                         return false;
3780                 REG_WRITE(ah, pmu_reg, pmu_set);
3781                 udelay(10);
3782         }
3783
3784         return true;
3785 }
3786
3787 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3788 {
3789         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3790         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3791         u32 reg_val;
3792
3793         if (pBase->featureEnable & BIT(4)) {
3794                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3795                         int reg_pmu_set;
3796
3797                         reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3798                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3799                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3800                                 return;
3801
3802                         if (AR_SREV_9330(ah)) {
3803                                 if (ah->is_clk_25mhz) {
3804                                         reg_pmu_set = (3 << 1) | (8 << 4) |
3805                                                       (3 << 8) | (1 << 14) |
3806                                                       (6 << 17) | (1 << 20) |
3807                                                       (3 << 24);
3808                                 } else {
3809                                         reg_pmu_set = (4 << 1)  | (7 << 4) |
3810                                                       (3 << 8)  | (1 << 14) |
3811                                                       (6 << 17) | (1 << 20) |
3812                                                       (3 << 24);
3813                                 }
3814                         } else {
3815                                 reg_pmu_set = (5 << 1) | (7 << 4) |
3816                                               (2 << 8) | (2 << 14) |
3817                                               (6 << 17) | (1 << 20) |
3818                                               (3 << 24) | (1 << 28);
3819                         }
3820
3821                         REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3822                         if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3823                                 return;
3824
3825                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3826                                         | (4 << 26);
3827                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3828                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3829                                 return;
3830
3831                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3832                                         | (1 << 21);
3833                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3834                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3835                                 return;
3836                 } else if (AR_SREV_9462(ah)) {
3837                         reg_val = le32_to_cpu(pBase->swreg);
3838                         REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3839                 } else {
3840                         /* Internal regulator is ON. Write swreg register. */
3841                         reg_val = le32_to_cpu(pBase->swreg);
3842                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3843                                   REG_READ(ah, AR_RTC_REG_CONTROL1) &
3844                                   (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3845                         REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3846                         /* Set REG_CONTROL1.SWREG_PROGRAM */
3847                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3848                                   REG_READ(ah,
3849                                            AR_RTC_REG_CONTROL1) |
3850                                            AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3851                 }
3852         } else {
3853                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3854                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3855                         while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3856                                                 AR_PHY_PMU2_PGM))
3857                                 udelay(10);
3858
3859                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3860                         while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3861                                                 AR_PHY_PMU1_PWD))
3862                                 udelay(10);
3863                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3864                         while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3865                                                 AR_PHY_PMU2_PGM))
3866                                 udelay(10);
3867                 } else if (AR_SREV_9462(ah))
3868                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3869                 else {
3870                         reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3871                                 AR_RTC_FORCE_SWREG_PRD;
3872                         REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3873                 }
3874         }
3875
3876 }
3877
3878 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3879 {
3880         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3881         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3882
3883         if (eep->baseEepHeader.featureEnable & 0x40) {
3884                 tuning_caps_param &= 0x7f;
3885                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3886                               tuning_caps_param);
3887                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3888                               tuning_caps_param);
3889         }
3890 }
3891
3892 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3893 {
3894         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3895         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3896         int quick_drop;
3897         s32 t[3], f[3] = {5180, 5500, 5785};
3898
3899         if (!(pBase->miscConfiguration & BIT(1)))
3900                 return;
3901
3902         if (freq < 4000)
3903                 quick_drop = eep->modalHeader2G.quick_drop;
3904         else {
3905                 t[0] = eep->base_ext1.quick_drop_low;
3906                 t[1] = eep->modalHeader5G.quick_drop;
3907                 t[2] = eep->base_ext1.quick_drop_high;
3908                 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3909         }
3910         REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3911 }
3912
3913 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
3914 {
3915         u32 value;
3916
3917         value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
3918
3919         REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3920                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3921         REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3922                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3923 }
3924
3925 static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
3926 {
3927         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3928         u8 xpa_ctl;
3929
3930         if (!(eep->baseEepHeader.featureEnable & 0x80))
3931                 return;
3932
3933         if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
3934                 return;
3935
3936         xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
3937         if (is2ghz)
3938                 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3939                               AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
3940         else
3941                 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3942                               AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
3943 }
3944
3945 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3946                                              struct ath9k_channel *chan)
3947 {
3948         bool is2ghz = IS_CHAN_2GHZ(chan);
3949         ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
3950         ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
3951         ar9003_hw_ant_ctrl_apply(ah, is2ghz);
3952         ar9003_hw_drive_strength_apply(ah);
3953         ar9003_hw_atten_apply(ah, chan);
3954         ar9003_hw_quick_drop_apply(ah, chan->channel);
3955         if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
3956                 ar9003_hw_internal_regulator_apply(ah);
3957         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3958                 ar9003_hw_apply_tuning_caps(ah);
3959         ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
3960 }
3961
3962 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3963                                       struct ath9k_channel *chan)
3964 {
3965 }
3966
3967 /*
3968  * Returns the interpolated y value corresponding to the specified x value
3969  * from the np ordered pairs of data (px,py).
3970  * The pairs do not have to be in any order.
3971  * If the specified x value is less than any of the px,
3972  * the returned y value is equal to the py for the lowest px.
3973  * If the specified x value is greater than any of the px,
3974  * the returned y value is equal to the py for the highest px.
3975  */
3976 static int ar9003_hw_power_interpolate(int32_t x,
3977                                        int32_t *px, int32_t *py, u_int16_t np)
3978 {
3979         int ip = 0;
3980         int lx = 0, ly = 0, lhave = 0;
3981         int hx = 0, hy = 0, hhave = 0;
3982         int dx = 0;
3983         int y = 0;
3984
3985         lhave = 0;
3986         hhave = 0;
3987
3988         /* identify best lower and higher x calibration measurement */
3989         for (ip = 0; ip < np; ip++) {
3990                 dx = x - px[ip];
3991
3992                 /* this measurement is higher than our desired x */
3993                 if (dx <= 0) {
3994                         if (!hhave || dx > (x - hx)) {
3995                                 /* new best higher x measurement */
3996                                 hx = px[ip];
3997                                 hy = py[ip];
3998                                 hhave = 1;
3999                         }
4000                 }
4001                 /* this measurement is lower than our desired x */
4002                 if (dx >= 0) {
4003                         if (!lhave || dx < (x - lx)) {
4004                                 /* new best lower x measurement */
4005                                 lx = px[ip];
4006                                 ly = py[ip];
4007                                 lhave = 1;
4008                         }
4009                 }
4010         }
4011
4012         /* the low x is good */
4013         if (lhave) {
4014                 /* so is the high x */
4015                 if (hhave) {
4016                         /* they're the same, so just pick one */
4017                         if (hx == lx)
4018                                 y = ly;
4019                         else    /* interpolate  */
4020                                 y = interpolate(x, lx, hx, ly, hy);
4021                 } else          /* only low is good, use it */
4022                         y = ly;
4023         } else if (hhave)       /* only high is good, use it */
4024                 y = hy;
4025         else /* nothing is good,this should never happen unless np=0, ???? */
4026                 y = -(1 << 30);
4027         return y;
4028 }
4029
4030 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4031                                        u16 rateIndex, u16 freq, bool is2GHz)
4032 {
4033         u16 numPiers, i;
4034         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4035         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4036         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4037         struct cal_tgt_pow_legacy *pEepromTargetPwr;
4038         u8 *pFreqBin;
4039
4040         if (is2GHz) {
4041                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4042                 pEepromTargetPwr = eep->calTargetPower2G;
4043                 pFreqBin = eep->calTarget_freqbin_2G;
4044         } else {
4045                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4046                 pEepromTargetPwr = eep->calTargetPower5G;
4047                 pFreqBin = eep->calTarget_freqbin_5G;
4048         }
4049
4050         /*
4051          * create array of channels and targetpower from
4052          * targetpower piers stored on eeprom
4053          */
4054         for (i = 0; i < numPiers; i++) {
4055                 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4056                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4057         }
4058
4059         /* interpolate to get target power for given frequency */
4060         return (u8) ar9003_hw_power_interpolate((s32) freq,
4061                                                  freqArray,
4062                                                  targetPowerArray, numPiers);
4063 }
4064
4065 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4066                                             u16 rateIndex,
4067                                             u16 freq, bool is2GHz)
4068 {
4069         u16 numPiers, i;
4070         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4071         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4072         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4073         struct cal_tgt_pow_ht *pEepromTargetPwr;
4074         u8 *pFreqBin;
4075
4076         if (is2GHz) {
4077                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4078                 pEepromTargetPwr = eep->calTargetPower2GHT20;
4079                 pFreqBin = eep->calTarget_freqbin_2GHT20;
4080         } else {
4081                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4082                 pEepromTargetPwr = eep->calTargetPower5GHT20;
4083                 pFreqBin = eep->calTarget_freqbin_5GHT20;
4084         }
4085
4086         /*
4087          * create array of channels and targetpower
4088          * from targetpower piers stored on eeprom
4089          */
4090         for (i = 0; i < numPiers; i++) {
4091                 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4092                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4093         }
4094
4095         /* interpolate to get target power for given frequency */
4096         return (u8) ar9003_hw_power_interpolate((s32) freq,
4097                                                  freqArray,
4098                                                  targetPowerArray, numPiers);
4099 }
4100
4101 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4102                                             u16 rateIndex,
4103                                             u16 freq, bool is2GHz)
4104 {
4105         u16 numPiers, i;
4106         s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4107         s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4108         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4109         struct cal_tgt_pow_ht *pEepromTargetPwr;
4110         u8 *pFreqBin;
4111
4112         if (is2GHz) {
4113                 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4114                 pEepromTargetPwr = eep->calTargetPower2GHT40;
4115                 pFreqBin = eep->calTarget_freqbin_2GHT40;
4116         } else {
4117                 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4118                 pEepromTargetPwr = eep->calTargetPower5GHT40;
4119                 pFreqBin = eep->calTarget_freqbin_5GHT40;
4120         }
4121
4122         /*
4123          * create array of channels and targetpower from
4124          * targetpower piers stored on eeprom
4125          */
4126         for (i = 0; i < numPiers; i++) {
4127                 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4128                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4129         }
4130
4131         /* interpolate to get target power for given frequency */
4132         return (u8) ar9003_hw_power_interpolate((s32) freq,
4133                                                  freqArray,
4134                                                  targetPowerArray, numPiers);
4135 }
4136
4137 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4138                                            u16 rateIndex, u16 freq)
4139 {
4140         u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4141         s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4142         s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4143         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4144         struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4145         u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4146
4147         /*
4148          * create array of channels and targetpower from
4149          * targetpower piers stored on eeprom
4150          */
4151         for (i = 0; i < numPiers; i++) {
4152                 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
4153                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4154         }
4155
4156         /* interpolate to get target power for given frequency */
4157         return (u8) ar9003_hw_power_interpolate((s32) freq,
4158                                                  freqArray,
4159                                                  targetPowerArray, numPiers);
4160 }
4161
4162 /* Set tx power registers to array of values passed in */
4163 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4164 {
4165 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
4166         /* make sure forced gain is not set */
4167         REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4168
4169         /* Write the OFDM power per rate set */
4170
4171         /* 6 (LSB), 9, 12, 18 (MSB) */
4172         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4173                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4174                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4175                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4176                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4177
4178         /* 24 (LSB), 36, 48, 54 (MSB) */
4179         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4180                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4181                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4182                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4183                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4184
4185         /* Write the CCK power per rate set */
4186
4187         /* 1L (LSB), reserved, 2L, 2S (MSB) */
4188         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4189                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4190                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4191                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
4192                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4193
4194         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4195         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4196                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4197                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4198                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4199                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4200             );
4201
4202         /* Write the power for duplicated frames - HT40 */
4203
4204         /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4205         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4206                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4207                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4208                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
4209                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
4210             );
4211
4212         /* Write the HT20 power per rate set */
4213
4214         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4215         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4216                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4217                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4218                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4219                   POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4220             );
4221
4222         /* 6 (LSB), 7, 12, 13 (MSB) */
4223         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4224                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4225                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4226                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4227                   POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4228             );
4229
4230         /* 14 (LSB), 15, 20, 21 */
4231         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4232                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4233                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4234                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4235                   POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4236             );
4237
4238         /* Mixed HT20 and HT40 rates */
4239
4240         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4241         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4242                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4243                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4244                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4245                   POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4246             );
4247
4248         /*
4249          * Write the HT40 power per rate set
4250          * correct PAR difference between HT40 and HT20/LEGACY
4251          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4252          */
4253         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4254                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4255                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4256                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4257                   POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4258             );
4259
4260         /* 6 (LSB), 7, 12, 13 (MSB) */
4261         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4262                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4263                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4264                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4265                   POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4266             );
4267
4268         /* 14 (LSB), 15, 20, 21 */
4269         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4270                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4271                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4272                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4273                   POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4274             );
4275
4276         return 0;
4277 #undef POW_SM
4278 }
4279
4280 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4281                                                u8 *targetPowerValT2,
4282                                                bool is2GHz)
4283 {
4284         targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4285             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4286                                          is2GHz);
4287         targetPowerValT2[ALL_TARGET_LEGACY_36] =
4288             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4289                                          is2GHz);
4290         targetPowerValT2[ALL_TARGET_LEGACY_48] =
4291             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4292                                          is2GHz);
4293         targetPowerValT2[ALL_TARGET_LEGACY_54] =
4294             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4295                                          is2GHz);
4296 }
4297
4298 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4299                                             u8 *targetPowerValT2)
4300 {
4301         targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4302             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4303                                              freq);
4304         targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4305             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4306         targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4307             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4308         targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4309             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4310 }
4311
4312 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4313                                              u8 *targetPowerValT2, bool is2GHz)
4314 {
4315         targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4316             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4317                                               is2GHz);
4318         targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4319             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4320                                               freq, is2GHz);
4321         targetPowerValT2[ALL_TARGET_HT20_4] =
4322             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4323                                               is2GHz);
4324         targetPowerValT2[ALL_TARGET_HT20_5] =
4325             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4326                                               is2GHz);
4327         targetPowerValT2[ALL_TARGET_HT20_6] =
4328             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4329                                               is2GHz);
4330         targetPowerValT2[ALL_TARGET_HT20_7] =
4331             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4332                                               is2GHz);
4333         targetPowerValT2[ALL_TARGET_HT20_12] =
4334             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4335                                               is2GHz);
4336         targetPowerValT2[ALL_TARGET_HT20_13] =
4337             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4338                                               is2GHz);
4339         targetPowerValT2[ALL_TARGET_HT20_14] =
4340             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4341                                               is2GHz);
4342         targetPowerValT2[ALL_TARGET_HT20_15] =
4343             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4344                                               is2GHz);
4345         targetPowerValT2[ALL_TARGET_HT20_20] =
4346             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4347                                               is2GHz);
4348         targetPowerValT2[ALL_TARGET_HT20_21] =
4349             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4350                                               is2GHz);
4351         targetPowerValT2[ALL_TARGET_HT20_22] =
4352             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4353                                               is2GHz);
4354         targetPowerValT2[ALL_TARGET_HT20_23] =
4355             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4356                                               is2GHz);
4357 }
4358
4359 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4360                                                    u16 freq,
4361                                                    u8 *targetPowerValT2,
4362                                                    bool is2GHz)
4363 {
4364         /* XXX: hard code for now, need to get from eeprom struct */
4365         u8 ht40PowerIncForPdadc = 0;
4366
4367         targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4368             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4369                                               is2GHz) + ht40PowerIncForPdadc;
4370         targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4371             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4372                                               freq,
4373                                               is2GHz) + ht40PowerIncForPdadc;
4374         targetPowerValT2[ALL_TARGET_HT40_4] =
4375             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4376                                               is2GHz) + ht40PowerIncForPdadc;
4377         targetPowerValT2[ALL_TARGET_HT40_5] =
4378             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4379                                               is2GHz) + ht40PowerIncForPdadc;
4380         targetPowerValT2[ALL_TARGET_HT40_6] =
4381             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4382                                               is2GHz) + ht40PowerIncForPdadc;
4383         targetPowerValT2[ALL_TARGET_HT40_7] =
4384             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4385                                               is2GHz) + ht40PowerIncForPdadc;
4386         targetPowerValT2[ALL_TARGET_HT40_12] =
4387             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4388                                               is2GHz) + ht40PowerIncForPdadc;
4389         targetPowerValT2[ALL_TARGET_HT40_13] =
4390             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4391                                               is2GHz) + ht40PowerIncForPdadc;
4392         targetPowerValT2[ALL_TARGET_HT40_14] =
4393             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4394                                               is2GHz) + ht40PowerIncForPdadc;
4395         targetPowerValT2[ALL_TARGET_HT40_15] =
4396             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4397                                               is2GHz) + ht40PowerIncForPdadc;
4398         targetPowerValT2[ALL_TARGET_HT40_20] =
4399             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4400                                               is2GHz) + ht40PowerIncForPdadc;
4401         targetPowerValT2[ALL_TARGET_HT40_21] =
4402             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4403                                               is2GHz) + ht40PowerIncForPdadc;
4404         targetPowerValT2[ALL_TARGET_HT40_22] =
4405             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4406                                               is2GHz) + ht40PowerIncForPdadc;
4407         targetPowerValT2[ALL_TARGET_HT40_23] =
4408             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4409                                               is2GHz) + ht40PowerIncForPdadc;
4410 }
4411
4412 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4413                                               struct ath9k_channel *chan,
4414                                               u8 *targetPowerValT2)
4415 {
4416         bool is2GHz = IS_CHAN_2GHZ(chan);
4417         unsigned int i = 0;
4418         struct ath_common *common = ath9k_hw_common(ah);
4419         u16 freq = chan->channel;
4420
4421         if (is2GHz)
4422                 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4423
4424         ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4425         ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4426
4427         if (IS_CHAN_HT40(chan))
4428                 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4429                                                  is2GHz);
4430
4431         for (i = 0; i < ar9300RateSize; i++) {
4432                 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4433                         i, targetPowerValT2[i]);
4434         }
4435 }
4436
4437 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4438                                   int mode,
4439                                   int ipier,
4440                                   int ichain,
4441                                   int *pfrequency,
4442                                   int *pcorrection,
4443                                   int *ptemperature, int *pvoltage)
4444 {
4445         u8 *pCalPier;
4446         struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4447         int is2GHz;
4448         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4449         struct ath_common *common = ath9k_hw_common(ah);
4450
4451         if (ichain >= AR9300_MAX_CHAINS) {
4452                 ath_dbg(common, EEPROM,
4453                         "Invalid chain index, must be less than %d\n",
4454                         AR9300_MAX_CHAINS);
4455                 return -1;
4456         }
4457
4458         if (mode) {             /* 5GHz */
4459                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4460                         ath_dbg(common, EEPROM,
4461                                 "Invalid 5GHz cal pier index, must be less than %d\n",
4462                                 AR9300_NUM_5G_CAL_PIERS);
4463                         return -1;
4464                 }
4465                 pCalPier = &(eep->calFreqPier5G[ipier]);
4466                 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4467                 is2GHz = 0;
4468         } else {
4469                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4470                         ath_dbg(common, EEPROM,
4471                                 "Invalid 2GHz cal pier index, must be less than %d\n",
4472                                 AR9300_NUM_2G_CAL_PIERS);
4473                         return -1;
4474                 }
4475
4476                 pCalPier = &(eep->calFreqPier2G[ipier]);
4477                 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4478                 is2GHz = 1;
4479         }
4480
4481         *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz);
4482         *pcorrection = pCalPierStruct->refPower;
4483         *ptemperature = pCalPierStruct->tempMeas;
4484         *pvoltage = pCalPierStruct->voltMeas;
4485
4486         return 0;
4487 }
4488
4489 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4490                                             int frequency,
4491                                             int *correction,
4492                                             int *voltage, int *temperature)
4493 {
4494         int tempSlope = 0;
4495         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4496         int f[3], t[3];
4497
4498         REG_RMW(ah, AR_PHY_TPC_11_B0,
4499                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4500                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4501         if (ah->caps.tx_chainmask & BIT(1))
4502                 REG_RMW(ah, AR_PHY_TPC_11_B1,
4503                         (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4504                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4505         if (ah->caps.tx_chainmask & BIT(2))
4506                 REG_RMW(ah, AR_PHY_TPC_11_B2,
4507                         (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4508                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4509
4510         /* enable open loop power control on chip */
4511         REG_RMW(ah, AR_PHY_TPC_6_B0,
4512                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4513                 AR_PHY_TPC_6_ERROR_EST_MODE);
4514         if (ah->caps.tx_chainmask & BIT(1))
4515                 REG_RMW(ah, AR_PHY_TPC_6_B1,
4516                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4517                         AR_PHY_TPC_6_ERROR_EST_MODE);
4518         if (ah->caps.tx_chainmask & BIT(2))
4519                 REG_RMW(ah, AR_PHY_TPC_6_B2,
4520                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4521                         AR_PHY_TPC_6_ERROR_EST_MODE);
4522
4523         /*
4524          * enable temperature compensation
4525          * Need to use register names
4526          */
4527         if (frequency < 4000)
4528                 tempSlope = eep->modalHeader2G.tempSlope;
4529         else if (eep->base_ext2.tempSlopeLow != 0) {
4530                 t[0] = eep->base_ext2.tempSlopeLow;
4531                 f[0] = 5180;
4532                 t[1] = eep->modalHeader5G.tempSlope;
4533                 f[1] = 5500;
4534                 t[2] = eep->base_ext2.tempSlopeHigh;
4535                 f[2] = 5785;
4536                 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4537                                                         f, t, 3);
4538         } else
4539                 tempSlope = eep->modalHeader5G.tempSlope;
4540
4541         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4542
4543         if (AR_SREV_9462_20(ah))
4544                 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4545                               AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4546
4547
4548         REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4549                       temperature[0]);
4550
4551         return 0;
4552 }
4553
4554 /* Apply the recorded correction values. */
4555 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4556 {
4557         int ichain, ipier, npier;
4558         int mode;
4559         int lfrequency[AR9300_MAX_CHAINS],
4560             lcorrection[AR9300_MAX_CHAINS],
4561             ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4562         int hfrequency[AR9300_MAX_CHAINS],
4563             hcorrection[AR9300_MAX_CHAINS],
4564             htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4565         int fdiff;
4566         int correction[AR9300_MAX_CHAINS],
4567             voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4568         int pfrequency, pcorrection, ptemperature, pvoltage;
4569         struct ath_common *common = ath9k_hw_common(ah);
4570
4571         mode = (frequency >= 4000);
4572         if (mode)
4573                 npier = AR9300_NUM_5G_CAL_PIERS;
4574         else
4575                 npier = AR9300_NUM_2G_CAL_PIERS;
4576
4577         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4578                 lfrequency[ichain] = 0;
4579                 hfrequency[ichain] = 100000;
4580         }
4581         /* identify best lower and higher frequency calibration measurement */
4582         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4583                 for (ipier = 0; ipier < npier; ipier++) {
4584                         if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4585                                                     &pfrequency, &pcorrection,
4586                                                     &ptemperature, &pvoltage)) {
4587                                 fdiff = frequency - pfrequency;
4588
4589                                 /*
4590                                  * this measurement is higher than
4591                                  * our desired frequency
4592                                  */
4593                                 if (fdiff <= 0) {
4594                                         if (hfrequency[ichain] <= 0 ||
4595                                             hfrequency[ichain] >= 100000 ||
4596                                             fdiff >
4597                                             (frequency - hfrequency[ichain])) {
4598                                                 /*
4599                                                  * new best higher
4600                                                  * frequency measurement
4601                                                  */
4602                                                 hfrequency[ichain] = pfrequency;
4603                                                 hcorrection[ichain] =
4604                                                     pcorrection;
4605                                                 htemperature[ichain] =
4606                                                     ptemperature;
4607                                                 hvoltage[ichain] = pvoltage;
4608                                         }
4609                                 }
4610                                 if (fdiff >= 0) {
4611                                         if (lfrequency[ichain] <= 0
4612                                             || fdiff <
4613                                             (frequency - lfrequency[ichain])) {
4614                                                 /*
4615                                                  * new best lower
4616                                                  * frequency measurement
4617                                                  */
4618                                                 lfrequency[ichain] = pfrequency;
4619                                                 lcorrection[ichain] =
4620                                                     pcorrection;
4621                                                 ltemperature[ichain] =
4622                                                     ptemperature;
4623                                                 lvoltage[ichain] = pvoltage;
4624                                         }
4625                                 }
4626                         }
4627                 }
4628         }
4629
4630         /* interpolate  */
4631         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4632                 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
4633                         ichain, frequency, lfrequency[ichain],
4634                         lcorrection[ichain], hfrequency[ichain],
4635                         hcorrection[ichain]);
4636                 /* they're the same, so just pick one */
4637                 if (hfrequency[ichain] == lfrequency[ichain]) {
4638                         correction[ichain] = lcorrection[ichain];
4639                         voltage[ichain] = lvoltage[ichain];
4640                         temperature[ichain] = ltemperature[ichain];
4641                 }
4642                 /* the low frequency is good */
4643                 else if (frequency - lfrequency[ichain] < 1000) {
4644                         /* so is the high frequency, interpolate */
4645                         if (hfrequency[ichain] - frequency < 1000) {
4646
4647                                 correction[ichain] = interpolate(frequency,
4648                                                 lfrequency[ichain],
4649                                                 hfrequency[ichain],
4650                                                 lcorrection[ichain],
4651                                                 hcorrection[ichain]);
4652
4653                                 temperature[ichain] = interpolate(frequency,
4654                                                 lfrequency[ichain],
4655                                                 hfrequency[ichain],
4656                                                 ltemperature[ichain],
4657                                                 htemperature[ichain]);
4658
4659                                 voltage[ichain] = interpolate(frequency,
4660                                                 lfrequency[ichain],
4661                                                 hfrequency[ichain],
4662                                                 lvoltage[ichain],
4663                                                 hvoltage[ichain]);
4664                         }
4665                         /* only low is good, use it */
4666                         else {
4667                                 correction[ichain] = lcorrection[ichain];
4668                                 temperature[ichain] = ltemperature[ichain];
4669                                 voltage[ichain] = lvoltage[ichain];
4670                         }
4671                 }
4672                 /* only high is good, use it */
4673                 else if (hfrequency[ichain] - frequency < 1000) {
4674                         correction[ichain] = hcorrection[ichain];
4675                         temperature[ichain] = htemperature[ichain];
4676                         voltage[ichain] = hvoltage[ichain];
4677                 } else {        /* nothing is good, presume 0???? */
4678                         correction[ichain] = 0;
4679                         temperature[ichain] = 0;
4680                         voltage[ichain] = 0;
4681                 }
4682         }
4683
4684         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4685                                          temperature);
4686
4687         ath_dbg(common, EEPROM,
4688                 "for frequency=%d, calibration correction = %d %d %d\n",
4689                 frequency, correction[0], correction[1], correction[2]);
4690
4691         return 0;
4692 }
4693
4694 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4695                                            int idx,
4696                                            int edge,
4697                                            bool is2GHz)
4698 {
4699         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4700         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4701
4702         if (is2GHz)
4703                 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4704         else
4705                 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4706 }
4707
4708 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4709                                              int idx,
4710                                              unsigned int edge,
4711                                              u16 freq,
4712                                              bool is2GHz)
4713 {
4714         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4715         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4716
4717         u8 *ctl_freqbin = is2GHz ?
4718                 &eep->ctl_freqbin_2G[idx][0] :
4719                 &eep->ctl_freqbin_5G[idx][0];
4720
4721         if (is2GHz) {
4722                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4723                     CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4724                         return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4725         } else {
4726                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4727                     CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4728                         return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4729         }
4730
4731         return MAX_RATE_POWER;
4732 }
4733
4734 /*
4735  * Find the maximum conformance test limit for the given channel and CTL info
4736  */
4737 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4738                                         u16 freq, int idx, bool is2GHz)
4739 {
4740         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4741         u8 *ctl_freqbin = is2GHz ?
4742                 &eep->ctl_freqbin_2G[idx][0] :
4743                 &eep->ctl_freqbin_5G[idx][0];
4744         u16 num_edges = is2GHz ?
4745                 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4746         unsigned int edge;
4747
4748         /* Get the edge power */
4749         for (edge = 0;
4750              (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4751              edge++) {
4752                 /*
4753                  * If there's an exact channel match or an inband flag set
4754                  * on the lower channel use the given rdEdgePower
4755                  */
4756                 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4757                         twiceMaxEdgePower =
4758                                 ar9003_hw_get_direct_edge_power(eep, idx,
4759                                                                 edge, is2GHz);
4760                         break;
4761                 } else if ((edge > 0) &&
4762                            (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4763                                                       is2GHz))) {
4764                         twiceMaxEdgePower =
4765                                 ar9003_hw_get_indirect_edge_power(eep, idx,
4766                                                                   edge, freq,
4767                                                                   is2GHz);
4768                         /*
4769                          * Leave loop - no more affecting edges possible in
4770                          * this monotonic increasing list
4771                          */
4772                         break;
4773                 }
4774         }
4775         return twiceMaxEdgePower;
4776 }
4777
4778 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4779                                                struct ath9k_channel *chan,
4780                                                u8 *pPwrArray, u16 cfgCtl,
4781                                                u8 antenna_reduction,
4782                                                u16 powerLimit)
4783 {
4784         struct ath_common *common = ath9k_hw_common(ah);
4785         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4786         u16 twiceMaxEdgePower;
4787         int i;
4788         u16 scaledPower = 0, minCtlPower;
4789         static const u16 ctlModesFor11a[] = {
4790                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4791         };
4792         static const u16 ctlModesFor11g[] = {
4793                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4794                 CTL_11G_EXT, CTL_2GHT40
4795         };
4796         u16 numCtlModes;
4797         const u16 *pCtlMode;
4798         u16 ctlMode, freq;
4799         struct chan_centers centers;
4800         u8 *ctlIndex;
4801         u8 ctlNum;
4802         u16 twiceMinEdgePower;
4803         bool is2ghz = IS_CHAN_2GHZ(chan);
4804
4805         ath9k_hw_get_channel_centers(ah, chan, &centers);
4806         scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
4807                                                 antenna_reduction);
4808
4809         if (is2ghz) {
4810                 /* Setup for CTL modes */
4811                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4812                 numCtlModes =
4813                         ARRAY_SIZE(ctlModesFor11g) -
4814                                    SUB_NUM_CTL_MODES_AT_2G_40;
4815                 pCtlMode = ctlModesFor11g;
4816                 if (IS_CHAN_HT40(chan))
4817                         /* All 2G CTL's */
4818                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4819         } else {
4820                 /* Setup for CTL modes */
4821                 /* CTL_11A, CTL_5GHT20 */
4822                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4823                                          SUB_NUM_CTL_MODES_AT_5G_40;
4824                 pCtlMode = ctlModesFor11a;
4825                 if (IS_CHAN_HT40(chan))
4826                         /* All 5G CTL's */
4827                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4828         }
4829
4830         /*
4831          * For MIMO, need to apply regulatory caps individually across
4832          * dynamically running modes: CCK, OFDM, HT20, HT40
4833          *
4834          * The outer loop walks through each possible applicable runtime mode.
4835          * The inner loop walks through each ctlIndex entry in EEPROM.
4836          * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4837          */
4838         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4839                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4840                         (pCtlMode[ctlMode] == CTL_2GHT40);
4841                 if (isHt40CtlMode)
4842                         freq = centers.synth_center;
4843                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4844                         freq = centers.ext_center;
4845                 else
4846                         freq = centers.ctl_center;
4847
4848                 ath_dbg(common, REGULATORY,
4849                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4850                         ctlMode, numCtlModes, isHt40CtlMode,
4851                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
4852
4853                 /* walk through each CTL index stored in EEPROM */
4854                 if (is2ghz) {
4855                         ctlIndex = pEepData->ctlIndex_2G;
4856                         ctlNum = AR9300_NUM_CTLS_2G;
4857                 } else {
4858                         ctlIndex = pEepData->ctlIndex_5G;
4859                         ctlNum = AR9300_NUM_CTLS_5G;
4860                 }
4861
4862                 twiceMaxEdgePower = MAX_RATE_POWER;
4863                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4864                         ath_dbg(common, REGULATORY,
4865                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4866                                 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4867                                 chan->channel);
4868
4869                                 /*
4870                                  * compare test group from regulatory
4871                                  * channel list with test mode from pCtlMode
4872                                  * list
4873                                  */
4874                                 if ((((cfgCtl & ~CTL_MODE_M) |
4875                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4876                                         ctlIndex[i]) ||
4877                                     (((cfgCtl & ~CTL_MODE_M) |
4878                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4879                                      ((ctlIndex[i] & CTL_MODE_M) |
4880                                        SD_NO_CTL))) {
4881                                         twiceMinEdgePower =
4882                                           ar9003_hw_get_max_edge_power(pEepData,
4883                                                                        freq, i,
4884                                                                        is2ghz);
4885
4886                                         if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4887                                                 /*
4888                                                  * Find the minimum of all CTL
4889                                                  * edge powers that apply to
4890                                                  * this channel
4891                                                  */
4892                                                 twiceMaxEdgePower =
4893                                                         min(twiceMaxEdgePower,
4894                                                             twiceMinEdgePower);
4895                                                 else {
4896                                                         /* specific */
4897                                                         twiceMaxEdgePower =
4898                                                           twiceMinEdgePower;
4899                                                         break;
4900                                                 }
4901                                 }
4902                         }
4903
4904                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4905
4906                         ath_dbg(common, REGULATORY,
4907                                 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4908                                 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4909                                 scaledPower, minCtlPower);
4910
4911                         /* Apply ctl mode to correct target power set */
4912                         switch (pCtlMode[ctlMode]) {
4913                         case CTL_11B:
4914                                 for (i = ALL_TARGET_LEGACY_1L_5L;
4915                                      i <= ALL_TARGET_LEGACY_11S; i++)
4916                                         pPwrArray[i] =
4917                                           (u8)min((u16)pPwrArray[i],
4918                                                   minCtlPower);
4919                                 break;
4920                         case CTL_11A:
4921                         case CTL_11G:
4922                                 for (i = ALL_TARGET_LEGACY_6_24;
4923                                      i <= ALL_TARGET_LEGACY_54; i++)
4924                                         pPwrArray[i] =
4925                                           (u8)min((u16)pPwrArray[i],
4926                                                   minCtlPower);
4927                                 break;
4928                         case CTL_5GHT20:
4929                         case CTL_2GHT20:
4930                                 for (i = ALL_TARGET_HT20_0_8_16;
4931                                      i <= ALL_TARGET_HT20_21; i++)
4932                                         pPwrArray[i] =
4933                                           (u8)min((u16)pPwrArray[i],
4934                                                   minCtlPower);
4935                                 pPwrArray[ALL_TARGET_HT20_22] =
4936                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4937                                           minCtlPower);
4938                                 pPwrArray[ALL_TARGET_HT20_23] =
4939                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4940                                            minCtlPower);
4941                                 break;
4942                         case CTL_5GHT40:
4943                         case CTL_2GHT40:
4944                                 for (i = ALL_TARGET_HT40_0_8_16;
4945                                      i <= ALL_TARGET_HT40_23; i++)
4946                                         pPwrArray[i] =
4947                                           (u8)min((u16)pPwrArray[i],
4948                                                   minCtlPower);
4949                                 break;
4950                         default:
4951                             break;
4952                         }
4953         } /* end ctl mode checking */
4954 }
4955
4956 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4957 {
4958         u8 mod_idx = mcs_idx % 8;
4959
4960         if (mod_idx <= 3)
4961                 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4962         else
4963                 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4964 }
4965
4966 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4967                                         struct ath9k_channel *chan, u16 cfgCtl,
4968                                         u8 twiceAntennaReduction,
4969                                         u8 powerLimit, bool test)
4970 {
4971         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4972         struct ath_common *common = ath9k_hw_common(ah);
4973         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4974         struct ar9300_modal_eep_header *modal_hdr;
4975         u8 targetPowerValT2[ar9300RateSize];
4976         u8 target_power_val_t2_eep[ar9300RateSize];
4977         unsigned int i = 0, paprd_scale_factor = 0;
4978         u8 pwr_idx, min_pwridx = 0;
4979
4980         memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
4981
4982         /*
4983          * Get target powers from EEPROM - our baseline for TX Power
4984          */
4985         ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
4986
4987         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4988                 if (IS_CHAN_2GHZ(chan))
4989                         modal_hdr = &eep->modalHeader2G;
4990                 else
4991                         modal_hdr = &eep->modalHeader5G;
4992
4993                 ah->paprd_ratemask =
4994                         le32_to_cpu(modal_hdr->papdRateMaskHt20) &
4995                         AR9300_PAPRD_RATE_MASK;
4996
4997                 ah->paprd_ratemask_ht40 =
4998                         le32_to_cpu(modal_hdr->papdRateMaskHt40) &
4999                         AR9300_PAPRD_RATE_MASK;
5000
5001                 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5002                 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5003                                                   ALL_TARGET_HT20_0_8_16;
5004
5005                 if (!ah->paprd_table_write_done) {
5006                         memcpy(target_power_val_t2_eep, targetPowerValT2,
5007                                sizeof(targetPowerValT2));
5008                         for (i = 0; i < 24; i++) {
5009                                 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5010                                 if (ah->paprd_ratemask & (1 << i)) {
5011                                         if (targetPowerValT2[pwr_idx] &&
5012                                             targetPowerValT2[pwr_idx] ==
5013                                             target_power_val_t2_eep[pwr_idx])
5014                                                 targetPowerValT2[pwr_idx] -=
5015                                                         paprd_scale_factor;
5016                                 }
5017                         }
5018                 }
5019                 memcpy(target_power_val_t2_eep, targetPowerValT2,
5020                        sizeof(targetPowerValT2));
5021         }
5022
5023         ar9003_hw_set_power_per_rate_table(ah, chan,
5024                                            targetPowerValT2, cfgCtl,
5025                                            twiceAntennaReduction,
5026                                            powerLimit);
5027
5028         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5029                 for (i = 0; i < ar9300RateSize; i++) {
5030                         if ((ah->paprd_ratemask & (1 << i)) &&
5031                             (abs(targetPowerValT2[i] -
5032                                 target_power_val_t2_eep[i]) >
5033                             paprd_scale_factor)) {
5034                                 ah->paprd_ratemask &= ~(1 << i);
5035                                 ath_dbg(common, EEPROM,
5036                                         "paprd disabled for mcs %d\n", i);
5037                         }
5038                 }
5039         }
5040
5041         regulatory->max_power_level = 0;
5042         for (i = 0; i < ar9300RateSize; i++) {
5043                 if (targetPowerValT2[i] > regulatory->max_power_level)
5044                         regulatory->max_power_level = targetPowerValT2[i];
5045         }
5046
5047         ath9k_hw_update_regulatory_maxpower(ah);
5048
5049         if (test)
5050                 return;
5051
5052         for (i = 0; i < ar9300RateSize; i++) {
5053                 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5054                         i, targetPowerValT2[i]);
5055         }
5056
5057         /* Write target power array to registers */
5058         ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5059         ar9003_hw_calibration_apply(ah, chan->channel);
5060
5061         if (IS_CHAN_2GHZ(chan)) {
5062                 if (IS_CHAN_HT40(chan))
5063                         i = ALL_TARGET_HT40_0_8_16;
5064                 else
5065                         i = ALL_TARGET_HT20_0_8_16;
5066         } else {
5067                 if (IS_CHAN_HT40(chan))
5068                         i = ALL_TARGET_HT40_7;
5069                 else
5070                         i = ALL_TARGET_HT20_7;
5071         }
5072         ah->paprd_target_power = targetPowerValT2[i];
5073 }
5074
5075 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5076                                             u16 i, bool is2GHz)
5077 {
5078         return AR_NO_SPUR;
5079 }
5080
5081 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5082 {
5083         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5084
5085         return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5086 }
5087
5088 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5089 {
5090         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5091
5092         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5093 }
5094
5095 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
5096 {
5097         return ar9003_modal_header(ah, is2ghz)->spurChans;
5098 }
5099
5100 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5101                                            struct ath9k_channel *chan)
5102 {
5103         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5104
5105         if (IS_CHAN_2GHZ(chan))
5106                 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5107                           AR9300_PAPRD_SCALE_1);
5108         else {
5109                 if (chan->channel >= 5700)
5110                 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5111                           AR9300_PAPRD_SCALE_1);
5112                 else if (chan->channel >= 5400)
5113                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5114                                    AR9300_PAPRD_SCALE_2);
5115                 else
5116                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5117                                   AR9300_PAPRD_SCALE_1);
5118         }
5119 }
5120
5121 const struct eeprom_ops eep_ar9300_ops = {
5122         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5123         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5124         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5125         .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5126         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5127         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5128         .set_board_values = ath9k_hw_ar9300_set_board_values,
5129         .set_addac = ath9k_hw_ar9300_set_addac,
5130         .set_txpower = ath9k_hw_ar9300_set_txpower,
5131         .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5132 };