drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20 #include "ar9003_eeprom.h"
  21
  22 #define COMP_HDR_LEN 4
  23 #define COMP_CKSUM_LEN 2
  24
  25 #define LE16(x) __constant_cpu_to_le16(x)
  26 #define LE32(x) __constant_cpu_to_le32(x)
  27
  28 /* Local defines to distinguish between extension and control CTL's */
  29 #define EXT_ADDITIVE (0x8000)
  30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  33
  34 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  35 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  36
  37 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
  38
  39 #define EEPROM_DATA_LEN_9485    1088
  40
  41 static int ar9003_hw_power_interpolate(int32_t x,
  42                                        int32_t *px, int32_t *py, u_int16_t np);
  43
  44
  45 static const struct ar9300_eeprom ar9300_default = {
  46         .eepromVersion = 2,
  47         .templateVersion = 2,
  48         .macAddr = {0, 2, 3, 4, 5, 6},
  49         .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  50                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  51         .baseEepHeader = {
  52                 .regDmn = { LE16(0), LE16(0x1f) },
  53                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
  54                 .opCapFlags = {
  55                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
  56                         .eepMisc = 0,
  57                 },
  58                 .rfSilent = 0,
  59                 .blueToothOptions = 0,
  60                 .deviceCap = 0,
  61                 .deviceType = 5, /* takes lower byte in eeprom location */
  62                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  63                 .params_for_tuning_caps = {0, 0},
  64                 .featureEnable = 0x0c,
  65                  /*
  66                   * bit0 - enable tx temp comp - disabled
  67                   * bit1 - enable tx volt comp - disabled
  68                   * bit2 - enable fastClock - enabled
  69                   * bit3 - enable doubling - enabled
  70                   * bit4 - enable internal regulator - disabled
  71                   * bit5 - enable pa predistortion - disabled
  72                   */
  73                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  74                 .eepromWriteEnableGpio = 3,
  75                 .wlanDisableGpio = 0,
  76                 .wlanLedGpio = 8,
  77                 .rxBandSelectGpio = 0xff,
  78                 .txrxgain = 0,
  79                 .swreg = 0,
  80          },
  81         .modalHeader2G = {
  82         /* ar9300_modal_eep_header  2g */
  83                 /* 4 idle,t1,t2,b(4 bits per setting) */
  84                 .antCtrlCommon = LE32(0x110),
  85                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  86                 .antCtrlCommon2 = LE32(0x22222),
  87
  88                 /*
  89                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
  90                  * rx1, rx12, b (2 bits each)
  91                  */
  92                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
  93
  94                 /*
  95                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
  96                  * for ar9280 (0xa20c/b20c 5:0)
  97                  */
  98                 .xatten1DB = {0, 0, 0},
  99
 100                 /*
 101                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 102                  * for ar9280 (0xa20c/b20c 16:12
 103                  */
 104                 .xatten1Margin = {0, 0, 0},
 105                 .tempSlope = 36,
 106                 .voltSlope = 0,
 107
 108                 /*
 109                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 110                  * channels in usual fbin coding format
 111                  */
 112                 .spurChans = {0, 0, 0, 0, 0},
 113
 114                 /*
 115                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 116                  * if the register is per chain
 117                  */
 118                 .noiseFloorThreshCh = {-1, 0, 0},
 119                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 120                 .quick_drop = 0,
 121                 .xpaBiasLvl = 0,
 122                 .txFrameToDataStart = 0x0e,
 123                 .txFrameToPaOn = 0x0e,
 124                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 125                 .antennaGain = 0,
 126                 .switchSettling = 0x2c,
 127                 .adcDesiredSize = -30,
 128                 .txEndToXpaOff = 0,
 129                 .txEndToRxOn = 0x2,
 130                 .txFrameToXpaOn = 0xe,
 131                 .thresh62 = 28,
 132                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 133                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 134                 .xlna_bias_strength = 0,
 135                 .futureModal = {
 136                         0, 0, 0, 0, 0, 0, 0,
 137                 },
 138          },
 139         .base_ext1 = {
 140                 .ant_div_control = 0,
 141                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 142         },
 143         .calFreqPier2G = {
 144                 FREQ2FBIN(2412, 1),
 145                 FREQ2FBIN(2437, 1),
 146                 FREQ2FBIN(2472, 1),
 147          },
 148         /* ar9300_cal_data_per_freq_op_loop 2g */
 149         .calPierData2G = {
 150                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 151                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 152                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 153          },
 154         .calTarget_freqbin_Cck = {
 155                 FREQ2FBIN(2412, 1),
 156                 FREQ2FBIN(2484, 1),
 157          },
 158         .calTarget_freqbin_2G = {
 159                 FREQ2FBIN(2412, 1),
 160                 FREQ2FBIN(2437, 1),
 161                 FREQ2FBIN(2472, 1)
 162          },
 163         .calTarget_freqbin_2GHT20 = {
 164                 FREQ2FBIN(2412, 1),
 165                 FREQ2FBIN(2437, 1),
 166                 FREQ2FBIN(2472, 1)
 167          },
 168         .calTarget_freqbin_2GHT40 = {
 169                 FREQ2FBIN(2412, 1),
 170                 FREQ2FBIN(2437, 1),
 171                 FREQ2FBIN(2472, 1)
 172          },
 173         .calTargetPowerCck = {
 174                  /* 1L-5L,5S,11L,11S */
 175                  { {36, 36, 36, 36} },
 176                  { {36, 36, 36, 36} },
 177         },
 178         .calTargetPower2G = {
 179                  /* 6-24,36,48,54 */
 180                  { {32, 32, 28, 24} },
 181                  { {32, 32, 28, 24} },
 182                  { {32, 32, 28, 24} },
 183         },
 184         .calTargetPower2GHT20 = {
 185                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 186                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 187                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 188         },
 189         .calTargetPower2GHT40 = {
 190                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 191                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 192                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 193         },
 194         .ctlIndex_2G =  {
 195                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 196                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 197         },
 198         .ctl_freqbin_2G = {
 199                 {
 200                         FREQ2FBIN(2412, 1),
 201                         FREQ2FBIN(2417, 1),
 202                         FREQ2FBIN(2457, 1),
 203                         FREQ2FBIN(2462, 1)
 204                 },
 205                 {
 206                         FREQ2FBIN(2412, 1),
 207                         FREQ2FBIN(2417, 1),
 208                         FREQ2FBIN(2462, 1),
 209                         0xFF,
 210                 },
 211
 212                 {
 213                         FREQ2FBIN(2412, 1),
 214                         FREQ2FBIN(2417, 1),
 215                         FREQ2FBIN(2462, 1),
 216                         0xFF,
 217                 },
 218                 {
 219                         FREQ2FBIN(2422, 1),
 220                         FREQ2FBIN(2427, 1),
 221                         FREQ2FBIN(2447, 1),
 222                         FREQ2FBIN(2452, 1)
 223                 },
 224
 225                 {
 226                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 227                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 228                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 229                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 230                 },
 231
 232                 {
 233                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 234                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 235                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 236                         0,
 237                 },
 238
 239                 {
 240                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 241                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 242                         FREQ2FBIN(2472, 1),
 243                         0,
 244                 },
 245
 246                 {
 247                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 248                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 249                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 250                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 251                 },
 252
 253                 {
 254                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 255                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 256                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 257                 },
 258
 259                 {
 260                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 261                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 262                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 263                         0
 264                 },
 265
 266                 {
 267                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 268                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 269                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 270                         0
 271                 },
 272
 273                 {
 274                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 275                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 276                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 277                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 278                 }
 279          },
 280         .ctlPowerData_2G = {
 281                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 282                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 283                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 284
 285                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 286                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 287                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 288
 289                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 290                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 291                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 292
 293                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 294                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 295                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 296          },
 297         .modalHeader5G = {
 298                 /* 4 idle,t1,t2,b (4 bits per setting) */
 299                 .antCtrlCommon = LE32(0x110),
 300                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 301                 .antCtrlCommon2 = LE32(0x22222),
 302                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 303                 .antCtrlChain = {
 304                         LE16(0x000), LE16(0x000), LE16(0x000),
 305                 },
 306                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 307                 .xatten1DB = {0, 0, 0},
 308
 309                 /*
 310                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 311                  * for merlin (0xa20c/b20c 16:12
 312                  */
 313                 .xatten1Margin = {0, 0, 0},
 314                 .tempSlope = 68,
 315                 .voltSlope = 0,
 316                 /* spurChans spur channels in usual fbin coding format */
 317                 .spurChans = {0, 0, 0, 0, 0},
 318                 /* noiseFloorThreshCh Check if the register is per chain */
 319                 .noiseFloorThreshCh = {-1, 0, 0},
 320                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 321                 .quick_drop = 0,
 322                 .xpaBiasLvl = 0,
 323                 .txFrameToDataStart = 0x0e,
 324                 .txFrameToPaOn = 0x0e,
 325                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 326                 .antennaGain = 0,
 327                 .switchSettling = 0x2d,
 328                 .adcDesiredSize = -30,
 329                 .txEndToXpaOff = 0,
 330                 .txEndToRxOn = 0x2,
 331                 .txFrameToXpaOn = 0xe,
 332                 .thresh62 = 28,
 333                 .papdRateMaskHt20 = LE32(0x0c80c080),
 334                 .papdRateMaskHt40 = LE32(0x0080c080),
 335                 .xlna_bias_strength = 0,
 336                 .futureModal = {
 337                         0, 0, 0, 0, 0, 0, 0,
 338                 },
 339          },
 340         .base_ext2 = {
 341                 .tempSlopeLow = 0,
 342                 .tempSlopeHigh = 0,
 343                 .xatten1DBLow = {0, 0, 0},
 344                 .xatten1MarginLow = {0, 0, 0},
 345                 .xatten1DBHigh = {0, 0, 0},
 346                 .xatten1MarginHigh = {0, 0, 0}
 347         },
 348         .calFreqPier5G = {
 349                 FREQ2FBIN(5180, 0),
 350                 FREQ2FBIN(5220, 0),
 351                 FREQ2FBIN(5320, 0),
 352                 FREQ2FBIN(5400, 0),
 353                 FREQ2FBIN(5500, 0),
 354                 FREQ2FBIN(5600, 0),
 355                 FREQ2FBIN(5725, 0),
 356                 FREQ2FBIN(5825, 0)
 357         },
 358         .calPierData5G = {
 359                         {
 360                                 {0, 0, 0, 0, 0},
 361                                 {0, 0, 0, 0, 0},
 362                                 {0, 0, 0, 0, 0},
 363                                 {0, 0, 0, 0, 0},
 364                                 {0, 0, 0, 0, 0},
 365                                 {0, 0, 0, 0, 0},
 366                                 {0, 0, 0, 0, 0},
 367                                 {0, 0, 0, 0, 0},
 368                         },
 369                         {
 370                                 {0, 0, 0, 0, 0},
 371                                 {0, 0, 0, 0, 0},
 372                                 {0, 0, 0, 0, 0},
 373                                 {0, 0, 0, 0, 0},
 374                                 {0, 0, 0, 0, 0},
 375                                 {0, 0, 0, 0, 0},
 376                                 {0, 0, 0, 0, 0},
 377                                 {0, 0, 0, 0, 0},
 378                         },
 379                         {
 380                                 {0, 0, 0, 0, 0},
 381                                 {0, 0, 0, 0, 0},
 382                                 {0, 0, 0, 0, 0},
 383                                 {0, 0, 0, 0, 0},
 384                                 {0, 0, 0, 0, 0},
 385                                 {0, 0, 0, 0, 0},
 386                                 {0, 0, 0, 0, 0},
 387                                 {0, 0, 0, 0, 0},
 388                         },
 389
 390         },
 391         .calTarget_freqbin_5G = {
 392                 FREQ2FBIN(5180, 0),
 393                 FREQ2FBIN(5220, 0),
 394                 FREQ2FBIN(5320, 0),
 395                 FREQ2FBIN(5400, 0),
 396                 FREQ2FBIN(5500, 0),
 397                 FREQ2FBIN(5600, 0),
 398                 FREQ2FBIN(5725, 0),
 399                 FREQ2FBIN(5825, 0)
 400         },
 401         .calTarget_freqbin_5GHT20 = {
 402                 FREQ2FBIN(5180, 0),
 403                 FREQ2FBIN(5240, 0),
 404                 FREQ2FBIN(5320, 0),
 405                 FREQ2FBIN(5500, 0),
 406                 FREQ2FBIN(5700, 0),
 407                 FREQ2FBIN(5745, 0),
 408                 FREQ2FBIN(5725, 0),
 409                 FREQ2FBIN(5825, 0)
 410         },
 411         .calTarget_freqbin_5GHT40 = {
 412                 FREQ2FBIN(5180, 0),
 413                 FREQ2FBIN(5240, 0),
 414                 FREQ2FBIN(5320, 0),
 415                 FREQ2FBIN(5500, 0),
 416                 FREQ2FBIN(5700, 0),
 417                 FREQ2FBIN(5745, 0),
 418                 FREQ2FBIN(5725, 0),
 419                 FREQ2FBIN(5825, 0)
 420          },
 421         .calTargetPower5G = {
 422                 /* 6-24,36,48,54 */
 423                 { {20, 20, 20, 10} },
 424                 { {20, 20, 20, 10} },
 425                 { {20, 20, 20, 10} },
 426                 { {20, 20, 20, 10} },
 427                 { {20, 20, 20, 10} },
 428                 { {20, 20, 20, 10} },
 429                 { {20, 20, 20, 10} },
 430                 { {20, 20, 20, 10} },
 431          },
 432         .calTargetPower5GHT20 = {
 433                 /*
 434                  * 0_8_16,1-3_9-11_17-19,
 435                  * 4,5,6,7,12,13,14,15,20,21,22,23
 436                  */
 437                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 438                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 439                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 440                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 441                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 442                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 443                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 444                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 445          },
 446         .calTargetPower5GHT40 =  {
 447                 /*
 448                  * 0_8_16,1-3_9-11_17-19,
 449                  * 4,5,6,7,12,13,14,15,20,21,22,23
 450                  */
 451                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 452                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 453                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 454                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 455                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 456                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 457                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 458                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 459          },
 460         .ctlIndex_5G =  {
 461                 0x10, 0x16, 0x18, 0x40, 0x46,
 462                 0x48, 0x30, 0x36, 0x38
 463         },
 464         .ctl_freqbin_5G =  {
 465                 {
 466                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 467                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 468                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 469                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 470                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 471                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 472                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 473                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 474                 },
 475                 {
 476                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 477                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 478                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 479                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 480                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 481                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 482                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 483                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 484                 },
 485
 486                 {
 487                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 488                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 489                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 490                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 491                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 492                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 493                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 494                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 495                 },
 496
 497                 {
 498                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 499                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 500                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 501                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 502                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 503                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 504                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 505                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 506                 },
 507
 508                 {
 509                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 510                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 511                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 512                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 513                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 514                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 515                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 516                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 517                 },
 518
 519                 {
 520                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 521                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 522                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 523                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 524                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 525                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 526                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 527                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
 528                 },
 529
 530                 {
 531                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 532                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 533                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 534                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 535                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 536                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 537                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 538                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 539                 },
 540
 541                 {
 542                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 543                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 544                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 545                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 546                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 547                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 548                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 549                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 550                 },
 551
 552                 {
 553                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 554                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 555                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 556                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 557                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 558                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 559                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 560                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 561                 }
 562          },
 563         .ctlPowerData_5G = {
 564                 {
 565                         {
 566                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 567                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 568                         }
 569                 },
 570                 {
 571                         {
 572                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 573                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 574                         }
 575                 },
 576                 {
 577                         {
 578                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 579                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 580                         }
 581                 },
 582                 {
 583                         {
 584                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 585                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 586                         }
 587                 },
 588                 {
 589                         {
 590                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 591                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 592                         }
 593                 },
 594                 {
 595                         {
 596                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 597                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 598                         }
 599                 },
 600                 {
 601                         {
 602                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 603                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 604                         }
 605                 },
 606                 {
 607                         {
 608                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 609                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 610                         }
 611                 },
 612                 {
 613                         {
 614                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
 615                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 616                         }
 617                 },
 618          }
 619 };
 620
 621 static const struct ar9300_eeprom ar9300_x113 = {
 622         .eepromVersion = 2,
 623         .templateVersion = 6,
 624         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 625         .custData = {"x113-023-f0000"},
 626         .baseEepHeader = {
 627                 .regDmn = { LE16(0), LE16(0x1f) },
 628                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 629                 .opCapFlags = {
 630                         .opFlags = AR5416_OPFLAGS_11A,
 631                         .eepMisc = 0,
 632                 },
 633                 .rfSilent = 0,
 634                 .blueToothOptions = 0,
 635                 .deviceCap = 0,
 636                 .deviceType = 5, /* takes lower byte in eeprom location */
 637                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 638                 .params_for_tuning_caps = {0, 0},
 639                 .featureEnable = 0x0d,
 640                  /*
 641                   * bit0 - enable tx temp comp - disabled
 642                   * bit1 - enable tx volt comp - disabled
 643                   * bit2 - enable fastClock - enabled
 644                   * bit3 - enable doubling - enabled
 645                   * bit4 - enable internal regulator - disabled
 646                   * bit5 - enable pa predistortion - disabled
 647                   */
 648                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 649                 .eepromWriteEnableGpio = 6,
 650                 .wlanDisableGpio = 0,
 651                 .wlanLedGpio = 8,
 652                 .rxBandSelectGpio = 0xff,
 653                 .txrxgain = 0x21,
 654                 .swreg = 0,
 655          },
 656         .modalHeader2G = {
 657         /* ar9300_modal_eep_header  2g */
 658                 /* 4 idle,t1,t2,b(4 bits per setting) */
 659                 .antCtrlCommon = LE32(0x110),
 660                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 661                 .antCtrlCommon2 = LE32(0x44444),
 662
 663                 /*
 664                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 665                  * rx1, rx12, b (2 bits each)
 666                  */
 667                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 668
 669                 /*
 670                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 671                  * for ar9280 (0xa20c/b20c 5:0)
 672                  */
 673                 .xatten1DB = {0, 0, 0},
 674
 675                 /*
 676                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 677                  * for ar9280 (0xa20c/b20c 16:12
 678                  */
 679                 .xatten1Margin = {0, 0, 0},
 680                 .tempSlope = 25,
 681                 .voltSlope = 0,
 682
 683                 /*
 684                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 685                  * channels in usual fbin coding format
 686                  */
 687                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 688
 689                 /*
 690                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 691                  * if the register is per chain
 692                  */
 693                 .noiseFloorThreshCh = {-1, 0, 0},
 694                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 695                 .quick_drop = 0,
 696                 .xpaBiasLvl = 0,
 697                 .txFrameToDataStart = 0x0e,
 698                 .txFrameToPaOn = 0x0e,
 699                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 700                 .antennaGain = 0,
 701                 .switchSettling = 0x2c,
 702                 .adcDesiredSize = -30,
 703                 .txEndToXpaOff = 0,
 704                 .txEndToRxOn = 0x2,
 705                 .txFrameToXpaOn = 0xe,
 706                 .thresh62 = 28,
 707                 .papdRateMaskHt20 = LE32(0x0c80c080),
 708                 .papdRateMaskHt40 = LE32(0x0080c080),
 709                 .xlna_bias_strength = 0,
 710                 .futureModal = {
 711                         0, 0, 0, 0, 0, 0, 0,
 712                 },
 713          },
 714          .base_ext1 = {
 715                 .ant_div_control = 0,
 716                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 717          },
 718         .calFreqPier2G = {
 719                 FREQ2FBIN(2412, 1),
 720                 FREQ2FBIN(2437, 1),
 721                 FREQ2FBIN(2472, 1),
 722          },
 723         /* ar9300_cal_data_per_freq_op_loop 2g */
 724         .calPierData2G = {
 725                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 726                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 727                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 728          },
 729         .calTarget_freqbin_Cck = {
 730                 FREQ2FBIN(2412, 1),
 731                 FREQ2FBIN(2472, 1),
 732          },
 733         .calTarget_freqbin_2G = {
 734                 FREQ2FBIN(2412, 1),
 735                 FREQ2FBIN(2437, 1),
 736                 FREQ2FBIN(2472, 1)
 737          },
 738         .calTarget_freqbin_2GHT20 = {
 739                 FREQ2FBIN(2412, 1),
 740                 FREQ2FBIN(2437, 1),
 741                 FREQ2FBIN(2472, 1)
 742          },
 743         .calTarget_freqbin_2GHT40 = {
 744                 FREQ2FBIN(2412, 1),
 745                 FREQ2FBIN(2437, 1),
 746                 FREQ2FBIN(2472, 1)
 747          },
 748         .calTargetPowerCck = {
 749                  /* 1L-5L,5S,11L,11S */
 750                  { {34, 34, 34, 34} },
 751                  { {34, 34, 34, 34} },
 752         },
 753         .calTargetPower2G = {
 754                  /* 6-24,36,48,54 */
 755                  { {34, 34, 32, 32} },
 756                  { {34, 34, 32, 32} },
 757                  { {34, 34, 32, 32} },
 758         },
 759         .calTargetPower2GHT20 = {
 760                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 761                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 762                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 763         },
 764         .calTargetPower2GHT40 = {
 765                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 766                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 767                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 768         },
 769         .ctlIndex_2G =  {
 770                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 771                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 772         },
 773         .ctl_freqbin_2G = {
 774                 {
 775                         FREQ2FBIN(2412, 1),
 776                         FREQ2FBIN(2417, 1),
 777                         FREQ2FBIN(2457, 1),
 778                         FREQ2FBIN(2462, 1)
 779                 },
 780                 {
 781                         FREQ2FBIN(2412, 1),
 782                         FREQ2FBIN(2417, 1),
 783                         FREQ2FBIN(2462, 1),
 784                         0xFF,
 785                 },
 786
 787                 {
 788                         FREQ2FBIN(2412, 1),
 789                         FREQ2FBIN(2417, 1),
 790                         FREQ2FBIN(2462, 1),
 791                         0xFF,
 792                 },
 793                 {
 794                         FREQ2FBIN(2422, 1),
 795                         FREQ2FBIN(2427, 1),
 796                         FREQ2FBIN(2447, 1),
 797                         FREQ2FBIN(2452, 1)
 798                 },
 799
 800                 {
 801                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 802                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 803                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 804                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 805                 },
 806
 807                 {
 808                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 809                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 810                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 811                         0,
 812                 },
 813
 814                 {
 815                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 816                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 817                         FREQ2FBIN(2472, 1),
 818                         0,
 819                 },
 820
 821                 {
 822                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 823                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 824                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 825                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 826                 },
 827
 828                 {
 829                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 830                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 831                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 832                 },
 833
 834                 {
 835                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 836                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 837                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 838                         0
 839                 },
 840
 841                 {
 842                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 843                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 844                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 845                         0
 846                 },
 847
 848                 {
 849                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 850                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 851                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 852                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 853                 }
 854          },
 855         .ctlPowerData_2G = {
 856                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 857                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 858                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 859
 860                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 861                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 862                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 863
 864                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 865                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 866                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 867
 868                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 869                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 870                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 871          },
 872         .modalHeader5G = {
 873                 /* 4 idle,t1,t2,b (4 bits per setting) */
 874                 .antCtrlCommon = LE32(0x220),
 875                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 876                 .antCtrlCommon2 = LE32(0x11111),
 877                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 878                 .antCtrlChain = {
 879                         LE16(0x150), LE16(0x150), LE16(0x150),
 880                 },
 881                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 882                 .xatten1DB = {0, 0, 0},
 883
 884                 /*
 885                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 886                  * for merlin (0xa20c/b20c 16:12
 887                  */
 888                 .xatten1Margin = {0, 0, 0},
 889                 .tempSlope = 68,
 890                 .voltSlope = 0,
 891                 /* spurChans spur channels in usual fbin coding format */
 892                 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 893                 /* noiseFloorThreshCh Check if the register is per chain */
 894                 .noiseFloorThreshCh = {-1, 0, 0},
 895                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 896                 .quick_drop = 0,
 897                 .xpaBiasLvl = 0xf,
 898                 .txFrameToDataStart = 0x0e,
 899                 .txFrameToPaOn = 0x0e,
 900                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 901                 .antennaGain = 0,
 902                 .switchSettling = 0x2d,
 903                 .adcDesiredSize = -30,
 904                 .txEndToXpaOff = 0,
 905                 .txEndToRxOn = 0x2,
 906                 .txFrameToXpaOn = 0xe,
 907                 .thresh62 = 28,
 908                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 909                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 910                 .xlna_bias_strength = 0,
 911                 .futureModal = {
 912                         0, 0, 0, 0, 0, 0, 0,
 913                 },
 914          },
 915         .base_ext2 = {
 916                 .tempSlopeLow = 72,
 917                 .tempSlopeHigh = 105,
 918                 .xatten1DBLow = {0, 0, 0},
 919                 .xatten1MarginLow = {0, 0, 0},
 920                 .xatten1DBHigh = {0, 0, 0},
 921                 .xatten1MarginHigh = {0, 0, 0}
 922          },
 923         .calFreqPier5G = {
 924                 FREQ2FBIN(5180, 0),
 925                 FREQ2FBIN(5240, 0),
 926                 FREQ2FBIN(5320, 0),
 927                 FREQ2FBIN(5400, 0),
 928                 FREQ2FBIN(5500, 0),
 929                 FREQ2FBIN(5600, 0),
 930                 FREQ2FBIN(5745, 0),
 931                 FREQ2FBIN(5785, 0)
 932         },
 933         .calPierData5G = {
 934                         {
 935                                 {0, 0, 0, 0, 0},
 936                                 {0, 0, 0, 0, 0},
 937                                 {0, 0, 0, 0, 0},
 938                                 {0, 0, 0, 0, 0},
 939                                 {0, 0, 0, 0, 0},
 940                                 {0, 0, 0, 0, 0},
 941                                 {0, 0, 0, 0, 0},
 942                                 {0, 0, 0, 0, 0},
 943                         },
 944                         {
 945                                 {0, 0, 0, 0, 0},
 946                                 {0, 0, 0, 0, 0},
 947                                 {0, 0, 0, 0, 0},
 948                                 {0, 0, 0, 0, 0},
 949                                 {0, 0, 0, 0, 0},
 950                                 {0, 0, 0, 0, 0},
 951                                 {0, 0, 0, 0, 0},
 952                                 {0, 0, 0, 0, 0},
 953                         },
 954                         {
 955                                 {0, 0, 0, 0, 0},
 956                                 {0, 0, 0, 0, 0},
 957                                 {0, 0, 0, 0, 0},
 958                                 {0, 0, 0, 0, 0},
 959                                 {0, 0, 0, 0, 0},
 960                                 {0, 0, 0, 0, 0},
 961                                 {0, 0, 0, 0, 0},
 962                                 {0, 0, 0, 0, 0},
 963                         },
 964
 965         },
 966         .calTarget_freqbin_5G = {
 967                 FREQ2FBIN(5180, 0),
 968                 FREQ2FBIN(5220, 0),
 969                 FREQ2FBIN(5320, 0),
 970                 FREQ2FBIN(5400, 0),
 971                 FREQ2FBIN(5500, 0),
 972                 FREQ2FBIN(5600, 0),
 973                 FREQ2FBIN(5745, 0),
 974                 FREQ2FBIN(5785, 0)
 975         },
 976         .calTarget_freqbin_5GHT20 = {
 977                 FREQ2FBIN(5180, 0),
 978                 FREQ2FBIN(5240, 0),
 979                 FREQ2FBIN(5320, 0),
 980                 FREQ2FBIN(5400, 0),
 981                 FREQ2FBIN(5500, 0),
 982                 FREQ2FBIN(5700, 0),
 983                 FREQ2FBIN(5745, 0),
 984                 FREQ2FBIN(5825, 0)
 985         },
 986         .calTarget_freqbin_5GHT40 = {
 987                 FREQ2FBIN(5190, 0),
 988                 FREQ2FBIN(5230, 0),
 989                 FREQ2FBIN(5320, 0),
 990                 FREQ2FBIN(5410, 0),
 991                 FREQ2FBIN(5510, 0),
 992                 FREQ2FBIN(5670, 0),
 993                 FREQ2FBIN(5755, 0),
 994                 FREQ2FBIN(5825, 0)
 995          },
 996         .calTargetPower5G = {
 997                 /* 6-24,36,48,54 */
 998                 { {42, 40, 40, 34} },
 999                 { {42, 40, 40, 34} },
1000                 { {42, 40, 40, 34} },
1001                 { {42, 40, 40, 34} },
1002                 { {42, 40, 40, 34} },
1003                 { {42, 40, 40, 34} },
1004                 { {42, 40, 40, 34} },
1005                 { {42, 40, 40, 34} },
1006          },
1007         .calTargetPower5GHT20 = {
1008                 /*
1009                  * 0_8_16,1-3_9-11_17-19,
1010                  * 4,5,6,7,12,13,14,15,20,21,22,23
1011                  */
1012                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1013                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1014                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1015                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1016                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1017                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1018                 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1019                 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1020          },
1021         .calTargetPower5GHT40 =  {
1022                 /*
1023                  * 0_8_16,1-3_9-11_17-19,
1024                  * 4,5,6,7,12,13,14,15,20,21,22,23
1025                  */
1026                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1027                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1028                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1029                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1030                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1031                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1032                 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1033                 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1034          },
1035         .ctlIndex_5G =  {
1036                 0x10, 0x16, 0x18, 0x40, 0x46,
1037                 0x48, 0x30, 0x36, 0x38
1038         },
1039         .ctl_freqbin_5G =  {
1040                 {
1041                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1042                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1043                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1044                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1045                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1046                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1047                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1048                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1049                 },
1050                 {
1051                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1052                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1053                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1054                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1055                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1056                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1057                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1058                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1059                 },
1060
1061                 {
1062                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1063                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1064                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1065                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1066                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1067                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1068                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1069                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1070                 },
1071
1072                 {
1073                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1074                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1075                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1076                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1077                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1078                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1079                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1080                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1081                 },
1082
1083                 {
1084                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1085                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1086                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1087                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1088                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1089                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1090                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1091                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1092                 },
1093
1094                 {
1095                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1096                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1097                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1098                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1099                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1100                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1101                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1102                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1103                 },
1104
1105                 {
1106                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1107                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1108                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1109                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1110                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1111                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1112                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1113                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1114                 },
1115
1116                 {
1117                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1118                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1119                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1120                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1121                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1122                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1123                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1124                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1125                 },
1126
1127                 {
1128                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1129                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1130                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1131                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1132                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1133                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1134                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1135                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1136                 }
1137          },
1138         .ctlPowerData_5G = {
1139                 {
1140                         {
1141                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1142                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1143                         }
1144                 },
1145                 {
1146                         {
1147                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1148                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1149                         }
1150                 },
1151                 {
1152                         {
1153                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1154                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1155                         }
1156                 },
1157                 {
1158                         {
1159                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1160                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1161                         }
1162                 },
1163                 {
1164                         {
1165                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1166                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1167                         }
1168                 },
1169                 {
1170                         {
1171                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1172                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1173                         }
1174                 },
1175                 {
1176                         {
1177                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1178                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1179                         }
1180                 },
1181                 {
1182                         {
1183                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1184                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1185                         }
1186                 },
1187                 {
1188                         {
1189                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1190                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1191                         }
1192                 },
1193          }
1194 };
1195
1196
1197 static const struct ar9300_eeprom ar9300_h112 = {
1198         .eepromVersion = 2,
1199         .templateVersion = 3,
1200         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1201         .custData = {"h112-241-f0000"},
1202         .baseEepHeader = {
1203                 .regDmn = { LE16(0), LE16(0x1f) },
1204                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1205                 .opCapFlags = {
1206                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1207                         .eepMisc = 0,
1208                 },
1209                 .rfSilent = 0,
1210                 .blueToothOptions = 0,
1211                 .deviceCap = 0,
1212                 .deviceType = 5, /* takes lower byte in eeprom location */
1213                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1214                 .params_for_tuning_caps = {0, 0},
1215                 .featureEnable = 0x0d,
1216                 /*
1217                  * bit0 - enable tx temp comp - disabled
1218                  * bit1 - enable tx volt comp - disabled
1219                  * bit2 - enable fastClock - enabled
1220                  * bit3 - enable doubling - enabled
1221                  * bit4 - enable internal regulator - disabled
1222                  * bit5 - enable pa predistortion - disabled
1223                  */
1224                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1225                 .eepromWriteEnableGpio = 6,
1226                 .wlanDisableGpio = 0,
1227                 .wlanLedGpio = 8,
1228                 .rxBandSelectGpio = 0xff,
1229                 .txrxgain = 0x10,
1230                 .swreg = 0,
1231         },
1232         .modalHeader2G = {
1233                 /* ar9300_modal_eep_header  2g */
1234                 /* 4 idle,t1,t2,b(4 bits per setting) */
1235                 .antCtrlCommon = LE32(0x110),
1236                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1237                 .antCtrlCommon2 = LE32(0x44444),
1238
1239                 /*
1240                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1241                  * rx1, rx12, b (2 bits each)
1242                  */
1243                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1244
1245                 /*
1246                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
1247                  * for ar9280 (0xa20c/b20c 5:0)
1248                  */
1249                 .xatten1DB = {0, 0, 0},
1250
1251                 /*
1252                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1253                  * for ar9280 (0xa20c/b20c 16:12
1254                  */
1255                 .xatten1Margin = {0, 0, 0},
1256                 .tempSlope = 25,
1257                 .voltSlope = 0,
1258
1259                 /*
1260                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1261                  * channels in usual fbin coding format
1262                  */
1263                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1264
1265                 /*
1266                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1267                  * if the register is per chain
1268                  */
1269                 .noiseFloorThreshCh = {-1, 0, 0},
1270                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1271                 .quick_drop = 0,
1272                 .xpaBiasLvl = 0,
1273                 .txFrameToDataStart = 0x0e,
1274                 .txFrameToPaOn = 0x0e,
1275                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1276                 .antennaGain = 0,
1277                 .switchSettling = 0x2c,
1278                 .adcDesiredSize = -30,
1279                 .txEndToXpaOff = 0,
1280                 .txEndToRxOn = 0x2,
1281                 .txFrameToXpaOn = 0xe,
1282                 .thresh62 = 28,
1283                 .papdRateMaskHt20 = LE32(0x0c80c080),
1284                 .papdRateMaskHt40 = LE32(0x0080c080),
1285                 .xlna_bias_strength = 0,
1286                 .futureModal = {
1287                         0, 0, 0, 0, 0, 0, 0,
1288                 },
1289         },
1290         .base_ext1 = {
1291                 .ant_div_control = 0,
1292                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1293         },
1294         .calFreqPier2G = {
1295                 FREQ2FBIN(2412, 1),
1296                 FREQ2FBIN(2437, 1),
1297                 FREQ2FBIN(2462, 1),
1298         },
1299         /* ar9300_cal_data_per_freq_op_loop 2g */
1300         .calPierData2G = {
1301                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1302                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1303                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1304         },
1305         .calTarget_freqbin_Cck = {
1306                 FREQ2FBIN(2412, 1),
1307                 FREQ2FBIN(2472, 1),
1308         },
1309         .calTarget_freqbin_2G = {
1310                 FREQ2FBIN(2412, 1),
1311                 FREQ2FBIN(2437, 1),
1312                 FREQ2FBIN(2472, 1)
1313         },
1314         .calTarget_freqbin_2GHT20 = {
1315                 FREQ2FBIN(2412, 1),
1316                 FREQ2FBIN(2437, 1),
1317                 FREQ2FBIN(2472, 1)
1318         },
1319         .calTarget_freqbin_2GHT40 = {
1320                 FREQ2FBIN(2412, 1),
1321                 FREQ2FBIN(2437, 1),
1322                 FREQ2FBIN(2472, 1)
1323         },
1324         .calTargetPowerCck = {
1325                 /* 1L-5L,5S,11L,11S */
1326                 { {34, 34, 34, 34} },
1327                 { {34, 34, 34, 34} },
1328         },
1329         .calTargetPower2G = {
1330                 /* 6-24,36,48,54 */
1331                 { {34, 34, 32, 32} },
1332                 { {34, 34, 32, 32} },
1333                 { {34, 34, 32, 32} },
1334         },
1335         .calTargetPower2GHT20 = {
1336                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1337                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1338                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1339         },
1340         .calTargetPower2GHT40 = {
1341                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1342                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1343                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1344         },
1345         .ctlIndex_2G =  {
1346                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1347                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1348         },
1349         .ctl_freqbin_2G = {
1350                 {
1351                         FREQ2FBIN(2412, 1),
1352                         FREQ2FBIN(2417, 1),
1353                         FREQ2FBIN(2457, 1),
1354                         FREQ2FBIN(2462, 1)
1355                 },
1356                 {
1357                         FREQ2FBIN(2412, 1),
1358                         FREQ2FBIN(2417, 1),
1359                         FREQ2FBIN(2462, 1),
1360                         0xFF,
1361                 },
1362
1363                 {
1364                         FREQ2FBIN(2412, 1),
1365                         FREQ2FBIN(2417, 1),
1366                         FREQ2FBIN(2462, 1),
1367                         0xFF,
1368                 },
1369                 {
1370                         FREQ2FBIN(2422, 1),
1371                         FREQ2FBIN(2427, 1),
1372                         FREQ2FBIN(2447, 1),
1373                         FREQ2FBIN(2452, 1)
1374                 },
1375
1376                 {
1377                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1378                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1379                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1380                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1381                 },
1382
1383                 {
1384                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1385                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1386                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1387                         0,
1388                 },
1389
1390                 {
1391                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1392                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1393                         FREQ2FBIN(2472, 1),
1394                         0,
1395                 },
1396
1397                 {
1398                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1399                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1400                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1401                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1402                 },
1403
1404                 {
1405                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1406                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1407                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1408                 },
1409
1410                 {
1411                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1412                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1413                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1414                         0
1415                 },
1416
1417                 {
1418                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1419                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1420                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1421                         0
1422                 },
1423
1424                 {
1425                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1426                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1427                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1428                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1429                 }
1430         },
1431         .ctlPowerData_2G = {
1432                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1433                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1434                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1435
1436                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1437                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1438                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1439
1440                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1441                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1442                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1443
1444                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1445                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1446                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1447         },
1448         .modalHeader5G = {
1449                 /* 4 idle,t1,t2,b (4 bits per setting) */
1450                 .antCtrlCommon = LE32(0x220),
1451                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1452                 .antCtrlCommon2 = LE32(0x44444),
1453                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1454                 .antCtrlChain = {
1455                         LE16(0x150), LE16(0x150), LE16(0x150),
1456                 },
1457                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1458                 .xatten1DB = {0, 0, 0},
1459
1460                 /*
1461                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1462                  * for merlin (0xa20c/b20c 16:12
1463                  */
1464                 .xatten1Margin = {0, 0, 0},
1465                 .tempSlope = 45,
1466                 .voltSlope = 0,
1467                 /* spurChans spur channels in usual fbin coding format */
1468                 .spurChans = {0, 0, 0, 0, 0},
1469                 /* noiseFloorThreshCh Check if the register is per chain */
1470                 .noiseFloorThreshCh = {-1, 0, 0},
1471                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1472                 .quick_drop = 0,
1473                 .xpaBiasLvl = 0,
1474                 .txFrameToDataStart = 0x0e,
1475                 .txFrameToPaOn = 0x0e,
1476                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1477                 .antennaGain = 0,
1478                 .switchSettling = 0x2d,
1479                 .adcDesiredSize = -30,
1480                 .txEndToXpaOff = 0,
1481                 .txEndToRxOn = 0x2,
1482                 .txFrameToXpaOn = 0xe,
1483                 .thresh62 = 28,
1484                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1485                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1486                 .xlna_bias_strength = 0,
1487                 .futureModal = {
1488                         0, 0, 0, 0, 0, 0, 0,
1489                 },
1490         },
1491         .base_ext2 = {
1492                 .tempSlopeLow = 40,
1493                 .tempSlopeHigh = 50,
1494                 .xatten1DBLow = {0, 0, 0},
1495                 .xatten1MarginLow = {0, 0, 0},
1496                 .xatten1DBHigh = {0, 0, 0},
1497                 .xatten1MarginHigh = {0, 0, 0}
1498         },
1499         .calFreqPier5G = {
1500                 FREQ2FBIN(5180, 0),
1501                 FREQ2FBIN(5220, 0),
1502                 FREQ2FBIN(5320, 0),
1503                 FREQ2FBIN(5400, 0),
1504                 FREQ2FBIN(5500, 0),
1505                 FREQ2FBIN(5600, 0),
1506                 FREQ2FBIN(5700, 0),
1507                 FREQ2FBIN(5785, 0)
1508         },
1509         .calPierData5G = {
1510                 {
1511                         {0, 0, 0, 0, 0},
1512                         {0, 0, 0, 0, 0},
1513                         {0, 0, 0, 0, 0},
1514                         {0, 0, 0, 0, 0},
1515                         {0, 0, 0, 0, 0},
1516                         {0, 0, 0, 0, 0},
1517                         {0, 0, 0, 0, 0},
1518                         {0, 0, 0, 0, 0},
1519                 },
1520                 {
1521                         {0, 0, 0, 0, 0},
1522                         {0, 0, 0, 0, 0},
1523                         {0, 0, 0, 0, 0},
1524                         {0, 0, 0, 0, 0},
1525                         {0, 0, 0, 0, 0},
1526                         {0, 0, 0, 0, 0},
1527                         {0, 0, 0, 0, 0},
1528                         {0, 0, 0, 0, 0},
1529                 },
1530                 {
1531                         {0, 0, 0, 0, 0},
1532                         {0, 0, 0, 0, 0},
1533                         {0, 0, 0, 0, 0},
1534                         {0, 0, 0, 0, 0},
1535                         {0, 0, 0, 0, 0},
1536                         {0, 0, 0, 0, 0},
1537                         {0, 0, 0, 0, 0},
1538                         {0, 0, 0, 0, 0},
1539                 },
1540
1541         },
1542         .calTarget_freqbin_5G = {
1543                 FREQ2FBIN(5180, 0),
1544                 FREQ2FBIN(5240, 0),
1545                 FREQ2FBIN(5320, 0),
1546                 FREQ2FBIN(5400, 0),
1547                 FREQ2FBIN(5500, 0),
1548                 FREQ2FBIN(5600, 0),
1549                 FREQ2FBIN(5700, 0),
1550                 FREQ2FBIN(5825, 0)
1551         },
1552         .calTarget_freqbin_5GHT20 = {
1553                 FREQ2FBIN(5180, 0),
1554                 FREQ2FBIN(5240, 0),
1555                 FREQ2FBIN(5320, 0),
1556                 FREQ2FBIN(5400, 0),
1557                 FREQ2FBIN(5500, 0),
1558                 FREQ2FBIN(5700, 0),
1559                 FREQ2FBIN(5745, 0),
1560                 FREQ2FBIN(5825, 0)
1561         },
1562         .calTarget_freqbin_5GHT40 = {
1563                 FREQ2FBIN(5180, 0),
1564                 FREQ2FBIN(5240, 0),
1565                 FREQ2FBIN(5320, 0),
1566                 FREQ2FBIN(5400, 0),
1567                 FREQ2FBIN(5500, 0),
1568                 FREQ2FBIN(5700, 0),
1569                 FREQ2FBIN(5745, 0),
1570                 FREQ2FBIN(5825, 0)
1571         },
1572         .calTargetPower5G = {
1573                 /* 6-24,36,48,54 */
1574                 { {30, 30, 28, 24} },
1575                 { {30, 30, 28, 24} },
1576                 { {30, 30, 28, 24} },
1577                 { {30, 30, 28, 24} },
1578                 { {30, 30, 28, 24} },
1579                 { {30, 30, 28, 24} },
1580                 { {30, 30, 28, 24} },
1581                 { {30, 30, 28, 24} },
1582         },
1583         .calTargetPower5GHT20 = {
1584                 /*
1585                  * 0_8_16,1-3_9-11_17-19,
1586                  * 4,5,6,7,12,13,14,15,20,21,22,23
1587                  */
1588                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1589                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1590                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1591                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1592                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1593                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1594                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1595                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1596         },
1597         .calTargetPower5GHT40 =  {
1598                 /*
1599                  * 0_8_16,1-3_9-11_17-19,
1600                  * 4,5,6,7,12,13,14,15,20,21,22,23
1601                  */
1602                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1603                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1604                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1605                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1606                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1607                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1608                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1609                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1610         },
1611         .ctlIndex_5G =  {
1612                 0x10, 0x16, 0x18, 0x40, 0x46,
1613                 0x48, 0x30, 0x36, 0x38
1614         },
1615         .ctl_freqbin_5G =  {
1616                 {
1617                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1618                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1619                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1620                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1621                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1622                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1623                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1624                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1625                 },
1626                 {
1627                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1628                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1629                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1630                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1631                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1632                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1633                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1634                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1635                 },
1636
1637                 {
1638                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1639                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1640                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1641                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1642                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1643                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1644                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1645                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1646                 },
1647
1648                 {
1649                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1650                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1651                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1652                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1653                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1654                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1655                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1656                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1657                 },
1658
1659                 {
1660                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1661                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1662                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1663                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1664                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1665                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1666                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1667                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1668                 },
1669
1670                 {
1671                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1672                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1673                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1674                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1675                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1676                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1677                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1678                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1679                 },
1680
1681                 {
1682                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1683                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1684                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1685                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1686                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1687                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1688                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1689                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1690                 },
1691
1692                 {
1693                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1694                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1695                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1696                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1697                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1698                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1699                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1700                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1701                 },
1702
1703                 {
1704                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1705                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1706                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1707                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1708                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1709                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1710                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1711                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1712                 }
1713         },
1714         .ctlPowerData_5G = {
1715                 {
1716                         {
1717                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1718                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1719                         }
1720                 },
1721                 {
1722                         {
1723                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1724                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1725                         }
1726                 },
1727                 {
1728                         {
1729                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1730                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1731                         }
1732                 },
1733                 {
1734                         {
1735                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1736                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1737                         }
1738                 },
1739                 {
1740                         {
1741                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1742                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1743                         }
1744                 },
1745                 {
1746                         {
1747                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1748                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1749                         }
1750                 },
1751                 {
1752                         {
1753                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1754                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1755                         }
1756                 },
1757                 {
1758                         {
1759                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1760                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1761                         }
1762                 },
1763                 {
1764                         {
1765                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1766                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1767                         }
1768                 },
1769         }
1770 };
1771
1772
1773 static const struct ar9300_eeprom ar9300_x112 = {
1774         .eepromVersion = 2,
1775         .templateVersion = 5,
1776         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1777         .custData = {"x112-041-f0000"},
1778         .baseEepHeader = {
1779                 .regDmn = { LE16(0), LE16(0x1f) },
1780                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1781                 .opCapFlags = {
1782                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1783                         .eepMisc = 0,
1784                 },
1785                 .rfSilent = 0,
1786                 .blueToothOptions = 0,
1787                 .deviceCap = 0,
1788                 .deviceType = 5, /* takes lower byte in eeprom location */
1789                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1790                 .params_for_tuning_caps = {0, 0},
1791                 .featureEnable = 0x0d,
1792                 /*
1793                  * bit0 - enable tx temp comp - disabled
1794                  * bit1 - enable tx volt comp - disabled
1795                  * bit2 - enable fastclock - enabled
1796                  * bit3 - enable doubling - enabled
1797                  * bit4 - enable internal regulator - disabled
1798                  * bit5 - enable pa predistortion - disabled
1799                  */
1800                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1801                 .eepromWriteEnableGpio = 6,
1802                 .wlanDisableGpio = 0,
1803                 .wlanLedGpio = 8,
1804                 .rxBandSelectGpio = 0xff,
1805                 .txrxgain = 0x0,
1806                 .swreg = 0,
1807         },
1808         .modalHeader2G = {
1809                 /* ar9300_modal_eep_header  2g */
1810                 /* 4 idle,t1,t2,b(4 bits per setting) */
1811                 .antCtrlCommon = LE32(0x110),
1812                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1813                 .antCtrlCommon2 = LE32(0x22222),
1814
1815                 /*
1816                  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1817                  * rx1, rx12, b (2 bits each)
1818                  */
1819                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1820
1821                 /*
1822                  * xatten1DB[AR9300_max_chains];  3 xatten1_db
1823                  * for ar9280 (0xa20c/b20c 5:0)
1824                  */
1825                 .xatten1DB = {0x1b, 0x1b, 0x1b},
1826
1827                 /*
1828                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1829                  * for ar9280 (0xa20c/b20c 16:12
1830                  */
1831                 .xatten1Margin = {0x15, 0x15, 0x15},
1832                 .tempSlope = 50,
1833                 .voltSlope = 0,
1834
1835                 /*
1836                  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1837                  * channels in usual fbin coding format
1838                  */
1839                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1840
1841                 /*
1842                  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1843                  * if the register is per chain
1844                  */
1845                 .noiseFloorThreshCh = {-1, 0, 0},
1846                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1847                 .quick_drop = 0,
1848                 .xpaBiasLvl = 0,
1849                 .txFrameToDataStart = 0x0e,
1850                 .txFrameToPaOn = 0x0e,
1851                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1852                 .antennaGain = 0,
1853                 .switchSettling = 0x2c,
1854                 .adcDesiredSize = -30,
1855                 .txEndToXpaOff = 0,
1856                 .txEndToRxOn = 0x2,
1857                 .txFrameToXpaOn = 0xe,
1858                 .thresh62 = 28,
1859                 .papdRateMaskHt20 = LE32(0x0c80c080),
1860                 .papdRateMaskHt40 = LE32(0x0080c080),
1861                 .xlna_bias_strength = 0,
1862                 .futureModal = {
1863                         0, 0, 0, 0, 0, 0, 0,
1864                 },
1865         },
1866         .base_ext1 = {
1867                 .ant_div_control = 0,
1868                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1869         },
1870         .calFreqPier2G = {
1871                 FREQ2FBIN(2412, 1),
1872                 FREQ2FBIN(2437, 1),
1873                 FREQ2FBIN(2472, 1),
1874         },
1875         /* ar9300_cal_data_per_freq_op_loop 2g */
1876         .calPierData2G = {
1877                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1878                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1879                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1880         },
1881         .calTarget_freqbin_Cck = {
1882                 FREQ2FBIN(2412, 1),
1883                 FREQ2FBIN(2472, 1),
1884         },
1885         .calTarget_freqbin_2G = {
1886                 FREQ2FBIN(2412, 1),
1887                 FREQ2FBIN(2437, 1),
1888                 FREQ2FBIN(2472, 1)
1889         },
1890         .calTarget_freqbin_2GHT20 = {
1891                 FREQ2FBIN(2412, 1),
1892                 FREQ2FBIN(2437, 1),
1893                 FREQ2FBIN(2472, 1)
1894         },
1895         .calTarget_freqbin_2GHT40 = {
1896                 FREQ2FBIN(2412, 1),
1897                 FREQ2FBIN(2437, 1),
1898                 FREQ2FBIN(2472, 1)
1899         },
1900         .calTargetPowerCck = {
1901                 /* 1L-5L,5S,11L,11s */
1902                 { {38, 38, 38, 38} },
1903                 { {38, 38, 38, 38} },
1904         },
1905         .calTargetPower2G = {
1906                 /* 6-24,36,48,54 */
1907                 { {38, 38, 36, 34} },
1908                 { {38, 38, 36, 34} },
1909                 { {38, 38, 34, 32} },
1910         },
1911         .calTargetPower2GHT20 = {
1912                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1913                 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1914                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1915         },
1916         .calTargetPower2GHT40 = {
1917                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1918                 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1919                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1920         },
1921         .ctlIndex_2G =  {
1922                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1923                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1924         },
1925         .ctl_freqbin_2G = {
1926                 {
1927                         FREQ2FBIN(2412, 1),
1928                         FREQ2FBIN(2417, 1),
1929                         FREQ2FBIN(2457, 1),
1930                         FREQ2FBIN(2462, 1)
1931                 },
1932                 {
1933                         FREQ2FBIN(2412, 1),
1934                         FREQ2FBIN(2417, 1),
1935                         FREQ2FBIN(2462, 1),
1936                         0xFF,
1937                 },
1938
1939                 {
1940                         FREQ2FBIN(2412, 1),
1941                         FREQ2FBIN(2417, 1),
1942                         FREQ2FBIN(2462, 1),
1943                         0xFF,
1944                 },
1945                 {
1946                         FREQ2FBIN(2422, 1),
1947                         FREQ2FBIN(2427, 1),
1948                         FREQ2FBIN(2447, 1),
1949                         FREQ2FBIN(2452, 1)
1950                 },
1951
1952                 {
1953                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1954                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1955                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1956                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1957                 },
1958
1959                 {
1960                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1961                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1962                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1963                         0,
1964                 },
1965
1966                 {
1967                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1968                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1969                         FREQ2FBIN(2472, 1),
1970                         0,
1971                 },
1972
1973                 {
1974                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1975                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1976                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1977                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1978                 },
1979
1980                 {
1981                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1982                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1983                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1984                 },
1985
1986                 {
1987                         /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1988                         /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1989                         /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1990                         0
1991                 },
1992
1993                 {
1994                         /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1995                         /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1996                         /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1997                         0
1998                 },
1999
2000                 {
2001                         /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2002                         /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2003                         /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2004                         /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2005                 }
2006         },
2007         .ctlPowerData_2G = {
2008                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2009                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2010                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2011
2012                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2013                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2014                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2015
2016                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2017                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2018                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2019
2020                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2021                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2022                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2023         },
2024         .modalHeader5G = {
2025                 /* 4 idle,t1,t2,b (4 bits per setting) */
2026                 .antCtrlCommon = LE32(0x110),
2027                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2028                 .antCtrlCommon2 = LE32(0x22222),
2029                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2030                 .antCtrlChain = {
2031                         LE16(0x0), LE16(0x0), LE16(0x0),
2032                 },
2033                 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2034                 .xatten1DB = {0x13, 0x19, 0x17},
2035
2036                 /*
2037                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2038                  * for merlin (0xa20c/b20c 16:12
2039                  */
2040                 .xatten1Margin = {0x19, 0x19, 0x19},
2041                 .tempSlope = 70,
2042                 .voltSlope = 15,
2043                 /* spurChans spur channels in usual fbin coding format */
2044                 .spurChans = {0, 0, 0, 0, 0},
2045                 /* noiseFloorThreshch check if the register is per chain */
2046                 .noiseFloorThreshCh = {-1, 0, 0},
2047                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2048                 .quick_drop = 0,
2049                 .xpaBiasLvl = 0,
2050                 .txFrameToDataStart = 0x0e,
2051                 .txFrameToPaOn = 0x0e,
2052                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2053                 .antennaGain = 0,
2054                 .switchSettling = 0x2d,
2055                 .adcDesiredSize = -30,
2056                 .txEndToXpaOff = 0,
2057                 .txEndToRxOn = 0x2,
2058                 .txFrameToXpaOn = 0xe,
2059                 .thresh62 = 28,
2060                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2061                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2062                 .xlna_bias_strength = 0,
2063                 .futureModal = {
2064                         0, 0, 0, 0, 0, 0, 0,
2065                 },
2066         },
2067         .base_ext2 = {
2068                 .tempSlopeLow = 72,
2069                 .tempSlopeHigh = 105,
2070                 .xatten1DBLow = {0x10, 0x14, 0x10},
2071                 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2072                 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2073                 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2074         },
2075         .calFreqPier5G = {
2076                 FREQ2FBIN(5180, 0),
2077                 FREQ2FBIN(5220, 0),
2078                 FREQ2FBIN(5320, 0),
2079                 FREQ2FBIN(5400, 0),
2080                 FREQ2FBIN(5500, 0),
2081                 FREQ2FBIN(5600, 0),
2082                 FREQ2FBIN(5700, 0),
2083                 FREQ2FBIN(5785, 0)
2084         },
2085         .calPierData5G = {
2086                 {
2087                         {0, 0, 0, 0, 0},
2088                         {0, 0, 0, 0, 0},
2089                         {0, 0, 0, 0, 0},
2090                         {0, 0, 0, 0, 0},
2091                         {0, 0, 0, 0, 0},
2092                         {0, 0, 0, 0, 0},
2093                         {0, 0, 0, 0, 0},
2094                         {0, 0, 0, 0, 0},
2095                 },
2096                 {
2097                         {0, 0, 0, 0, 0},
2098                         {0, 0, 0, 0, 0},
2099                         {0, 0, 0, 0, 0},
2100                         {0, 0, 0, 0, 0},
2101                         {0, 0, 0, 0, 0},
2102                         {0, 0, 0, 0, 0},
2103                         {0, 0, 0, 0, 0},
2104                         {0, 0, 0, 0, 0},
2105                 },
2106                 {
2107                         {0, 0, 0, 0, 0},
2108                         {0, 0, 0, 0, 0},
2109                         {0, 0, 0, 0, 0},
2110                         {0, 0, 0, 0, 0},
2111                         {0, 0, 0, 0, 0},
2112                         {0, 0, 0, 0, 0},
2113                         {0, 0, 0, 0, 0},
2114                         {0, 0, 0, 0, 0},
2115                 },
2116
2117         },
2118         .calTarget_freqbin_5G = {
2119                 FREQ2FBIN(5180, 0),
2120                 FREQ2FBIN(5220, 0),
2121                 FREQ2FBIN(5320, 0),
2122                 FREQ2FBIN(5400, 0),
2123                 FREQ2FBIN(5500, 0),
2124                 FREQ2FBIN(5600, 0),
2125                 FREQ2FBIN(5725, 0),
2126                 FREQ2FBIN(5825, 0)
2127         },
2128         .calTarget_freqbin_5GHT20 = {
2129                 FREQ2FBIN(5180, 0),
2130                 FREQ2FBIN(5220, 0),
2131                 FREQ2FBIN(5320, 0),
2132                 FREQ2FBIN(5400, 0),
2133                 FREQ2FBIN(5500, 0),
2134                 FREQ2FBIN(5600, 0),
2135                 FREQ2FBIN(5725, 0),
2136                 FREQ2FBIN(5825, 0)
2137         },
2138         .calTarget_freqbin_5GHT40 = {
2139                 FREQ2FBIN(5180, 0),
2140                 FREQ2FBIN(5220, 0),
2141                 FREQ2FBIN(5320, 0),
2142                 FREQ2FBIN(5400, 0),
2143                 FREQ2FBIN(5500, 0),
2144                 FREQ2FBIN(5600, 0),
2145                 FREQ2FBIN(5725, 0),
2146                 FREQ2FBIN(5825, 0)
2147         },
2148         .calTargetPower5G = {
2149                 /* 6-24,36,48,54 */
2150                 { {32, 32, 28, 26} },
2151                 { {32, 32, 28, 26} },
2152                 { {32, 32, 28, 26} },
2153                 { {32, 32, 26, 24} },
2154                 { {32, 32, 26, 24} },
2155                 { {32, 32, 24, 22} },
2156                 { {30, 30, 24, 22} },
2157                 { {30, 30, 24, 22} },
2158         },
2159         .calTargetPower5GHT20 = {
2160                 /*
2161                  * 0_8_16,1-3_9-11_17-19,
2162                  * 4,5,6,7,12,13,14,15,20,21,22,23
2163                  */
2164                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2165                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2166                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2167                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2168                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2169                 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2170                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2171                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2172         },
2173         .calTargetPower5GHT40 =  {
2174                 /*
2175                  * 0_8_16,1-3_9-11_17-19,
2176                  * 4,5,6,7,12,13,14,15,20,21,22,23
2177                  */
2178                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2179                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2180                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2181                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2182                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2183                 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2184                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2185                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2186         },
2187         .ctlIndex_5G =  {
2188                 0x10, 0x16, 0x18, 0x40, 0x46,
2189                 0x48, 0x30, 0x36, 0x38
2190         },
2191         .ctl_freqbin_5G =  {
2192                 {
2193                         /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2194                         /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2195                         /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2196                         /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2197                         /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2198                         /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2199                         /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2200                         /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2201                 },
2202                 {
2203                         /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2204                         /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2205                         /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2206                         /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2207                         /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2208                         /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2209                         /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2210                         /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2211                 },
2212
2213                 {
2214                         /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2215                         /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2216                         /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2217                         /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2218                         /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2219                         /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2220                         /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2221                         /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2222                 },
2223
2224                 {
2225                         /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2226                         /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2227                         /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2228                         /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2229                         /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2230                         /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2231                         /* Data[3].ctledges[6].bchannel */ 0xFF,
2232                         /* Data[3].ctledges[7].bchannel */ 0xFF,
2233                 },
2234
2235                 {
2236                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2237                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2238                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2239                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2240                         /* Data[4].ctledges[4].bchannel */ 0xFF,
2241                         /* Data[4].ctledges[5].bchannel */ 0xFF,
2242                         /* Data[4].ctledges[6].bchannel */ 0xFF,
2243                         /* Data[4].ctledges[7].bchannel */ 0xFF,
2244                 },
2245
2246                 {
2247                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2248                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2249                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2250                         /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2251                         /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2252                         /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2253                         /* Data[5].ctledges[6].bchannel */ 0xFF,
2254                         /* Data[5].ctledges[7].bchannel */ 0xFF
2255                 },
2256
2257                 {
2258                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2259                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2260                         /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2261                         /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2262                         /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2263                         /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2264                         /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2265                         /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2266                 },
2267
2268                 {
2269                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2270                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2271                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2272                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2273                         /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2274                         /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2275                         /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2276                         /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2277                 },
2278
2279                 {
2280                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2281                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2282                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2283                         /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2284                         /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2285                         /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2286                         /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2287                         /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2288                 }
2289         },
2290         .ctlPowerData_5G = {
2291                 {
2292                         {
2293                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2294                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2295                         }
2296                 },
2297                 {
2298                         {
2299                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2300                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2301                         }
2302                 },
2303                 {
2304                         {
2305                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2306                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2307                         }
2308                 },
2309                 {
2310                         {
2311                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2312                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2313                         }
2314                 },
2315                 {
2316                         {
2317                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2318                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2319                         }
2320                 },
2321                 {
2322                         {
2323                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2324                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2325                         }
2326                 },
2327                 {
2328                         {
2329                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2330                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2331                         }
2332                 },
2333                 {
2334                         {
2335                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2336                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2337                         }
2338                 },
2339                 {
2340                         {
2341                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2342                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2343                         }
2344                 },
2345         }
2346 };
2347
2348 static const struct ar9300_eeprom ar9300_h116 = {
2349         .eepromVersion = 2,
2350         .templateVersion = 4,
2351         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2352         .custData = {"h116-041-f0000"},
2353         .baseEepHeader = {
2354                 .regDmn = { LE16(0), LE16(0x1f) },
2355                 .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
2356                 .opCapFlags = {
2357                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2358                         .eepMisc = 0,
2359                 },
2360                 .rfSilent = 0,
2361                 .blueToothOptions = 0,
2362                 .deviceCap = 0,
2363                 .deviceType = 5, /* takes lower byte in eeprom location */
2364                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2365                 .params_for_tuning_caps = {0, 0},
2366                 .featureEnable = 0x0d,
2367                  /*
2368                   * bit0 - enable tx temp comp - disabled
2369                   * bit1 - enable tx volt comp - disabled
2370                   * bit2 - enable fastClock - enabled
2371                   * bit3 - enable doubling - enabled
2372                   * bit4 - enable internal regulator - disabled
2373                   * bit5 - enable pa predistortion - disabled
2374                   */
2375                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2376                 .eepromWriteEnableGpio = 6,
2377                 .wlanDisableGpio = 0,
2378                 .wlanLedGpio = 8,
2379                 .rxBandSelectGpio = 0xff,
2380                 .txrxgain = 0x10,
2381                 .swreg = 0,
2382          },
2383         .modalHeader2G = {
2384         /* ar9300_modal_eep_header  2g */
2385                 /* 4 idle,t1,t2,b(4 bits per setting) */
2386                 .antCtrlCommon = LE32(0x110),
2387                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2388                 .antCtrlCommon2 = LE32(0x44444),
2389
2390                 /*
2391                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2392                  * rx1, rx12, b (2 bits each)
2393                  */
2394                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2395
2396                 /*
2397                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
2398                  * for ar9280 (0xa20c/b20c 5:0)
2399                  */
2400                 .xatten1DB = {0x1f, 0x1f, 0x1f},
2401
2402                 /*
2403                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2404                  * for ar9280 (0xa20c/b20c 16:12
2405                  */
2406                 .xatten1Margin = {0x12, 0x12, 0x12},
2407                 .tempSlope = 25,
2408                 .voltSlope = 0,
2409
2410                 /*
2411                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2412                  * channels in usual fbin coding format
2413                  */
2414                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2415
2416                 /*
2417                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2418                  * if the register is per chain
2419                  */
2420                 .noiseFloorThreshCh = {-1, 0, 0},
2421                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2422                 .quick_drop = 0,
2423                 .xpaBiasLvl = 0,
2424                 .txFrameToDataStart = 0x0e,
2425                 .txFrameToPaOn = 0x0e,
2426                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2427                 .antennaGain = 0,
2428                 .switchSettling = 0x2c,
2429                 .adcDesiredSize = -30,
2430                 .txEndToXpaOff = 0,
2431                 .txEndToRxOn = 0x2,
2432                 .txFrameToXpaOn = 0xe,
2433                 .thresh62 = 28,
2434                 .papdRateMaskHt20 = LE32(0x0c80C080),
2435                 .papdRateMaskHt40 = LE32(0x0080C080),
2436                 .xlna_bias_strength = 0,
2437                 .futureModal = {
2438                         0, 0, 0, 0, 0, 0, 0,
2439                 },
2440          },
2441          .base_ext1 = {
2442                 .ant_div_control = 0,
2443                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2444          },
2445         .calFreqPier2G = {
2446                 FREQ2FBIN(2412, 1),
2447                 FREQ2FBIN(2437, 1),
2448                 FREQ2FBIN(2462, 1),
2449          },
2450         /* ar9300_cal_data_per_freq_op_loop 2g */
2451         .calPierData2G = {
2452                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2453                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2454                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2455          },
2456         .calTarget_freqbin_Cck = {
2457                 FREQ2FBIN(2412, 1),
2458                 FREQ2FBIN(2472, 1),
2459          },
2460         .calTarget_freqbin_2G = {
2461                 FREQ2FBIN(2412, 1),
2462                 FREQ2FBIN(2437, 1),
2463                 FREQ2FBIN(2472, 1)
2464          },
2465         .calTarget_freqbin_2GHT20 = {
2466                 FREQ2FBIN(2412, 1),
2467                 FREQ2FBIN(2437, 1),
2468                 FREQ2FBIN(2472, 1)
2469          },
2470         .calTarget_freqbin_2GHT40 = {
2471                 FREQ2FBIN(2412, 1),
2472                 FREQ2FBIN(2437, 1),
2473                 FREQ2FBIN(2472, 1)
2474          },
2475         .calTargetPowerCck = {
2476                  /* 1L-5L,5S,11L,11S */
2477                  { {34, 34, 34, 34} },
2478                  { {34, 34, 34, 34} },
2479         },
2480         .calTargetPower2G = {
2481                  /* 6-24,36,48,54 */
2482                  { {34, 34, 32, 32} },
2483                  { {34, 34, 32, 32} },
2484                  { {34, 34, 32, 32} },
2485         },
2486         .calTargetPower2GHT20 = {
2487                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2488                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2489                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2490         },
2491         .calTargetPower2GHT40 = {
2492                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2493                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2494                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2495         },
2496         .ctlIndex_2G =  {
2497                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2498                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2499         },
2500         .ctl_freqbin_2G = {
2501                 {
2502                         FREQ2FBIN(2412, 1),
2503                         FREQ2FBIN(2417, 1),
2504                         FREQ2FBIN(2457, 1),
2505                         FREQ2FBIN(2462, 1)
2506                 },
2507                 {
2508                         FREQ2FBIN(2412, 1),
2509                         FREQ2FBIN(2417, 1),
2510                         FREQ2FBIN(2462, 1),
2511                         0xFF,
2512                 },
2513
2514                 {
2515                         FREQ2FBIN(2412, 1),
2516                         FREQ2FBIN(2417, 1),
2517                         FREQ2FBIN(2462, 1),
2518                         0xFF,
2519                 },
2520                 {
2521                         FREQ2FBIN(2422, 1),
2522                         FREQ2FBIN(2427, 1),
2523                         FREQ2FBIN(2447, 1),
2524                         FREQ2FBIN(2452, 1)
2525                 },
2526
2527                 {
2528                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2529                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2530                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2531                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2532                 },
2533
2534                 {
2535                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2536                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2537                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2538                         0,
2539                 },
2540
2541                 {
2542                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2543                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2544                         FREQ2FBIN(2472, 1),
2545                         0,
2546                 },
2547
2548                 {
2549                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2550                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2551                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2552                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2553                 },
2554
2555                 {
2556                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2557                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2558                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2559                 },
2560
2561                 {
2562                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2563                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2564                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2565                         0
2566                 },
2567
2568                 {
2569                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2570                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2571                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2572                         0
2573                 },
2574
2575                 {
2576                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2577                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2578                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2579                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2580                 }
2581          },
2582         .ctlPowerData_2G = {
2583                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2584                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2585                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2586
2587                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2588                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2589                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2590
2591                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2592                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2593                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2594
2595                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2596                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2597                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2598          },
2599         .modalHeader5G = {
2600                 /* 4 idle,t1,t2,b (4 bits per setting) */
2601                 .antCtrlCommon = LE32(0x220),
2602                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2603                 .antCtrlCommon2 = LE32(0x44444),
2604                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2605                 .antCtrlChain = {
2606                         LE16(0x150), LE16(0x150), LE16(0x150),
2607                 },
2608                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2609                 .xatten1DB = {0x19, 0x19, 0x19},
2610
2611                 /*
2612                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2613                  * for merlin (0xa20c/b20c 16:12
2614                  */
2615                 .xatten1Margin = {0x14, 0x14, 0x14},
2616                 .tempSlope = 70,
2617                 .voltSlope = 0,
2618                 /* spurChans spur channels in usual fbin coding format */
2619                 .spurChans = {0, 0, 0, 0, 0},
2620                 /* noiseFloorThreshCh Check if the register is per chain */
2621                 .noiseFloorThreshCh = {-1, 0, 0},
2622                 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2623                 .quick_drop = 0,
2624                 .xpaBiasLvl = 0,
2625                 .txFrameToDataStart = 0x0e,
2626                 .txFrameToPaOn = 0x0e,
2627                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2628                 .antennaGain = 0,
2629                 .switchSettling = 0x2d,
2630                 .adcDesiredSize = -30,
2631                 .txEndToXpaOff = 0,
2632                 .txEndToRxOn = 0x2,
2633                 .txFrameToXpaOn = 0xe,
2634                 .thresh62 = 28,
2635                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2636                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2637                 .xlna_bias_strength = 0,
2638                 .futureModal = {
2639                         0, 0, 0, 0, 0, 0, 0,
2640                 },
2641          },
2642         .base_ext2 = {
2643                 .tempSlopeLow = 35,
2644                 .tempSlopeHigh = 50,
2645                 .xatten1DBLow = {0, 0, 0},
2646                 .xatten1MarginLow = {0, 0, 0},
2647                 .xatten1DBHigh = {0, 0, 0},
2648                 .xatten1MarginHigh = {0, 0, 0}
2649          },
2650         .calFreqPier5G = {
2651                 FREQ2FBIN(5160, 0),
2652                 FREQ2FBIN(5220, 0),
2653                 FREQ2FBIN(5320, 0),
2654                 FREQ2FBIN(5400, 0),
2655                 FREQ2FBIN(5500, 0),
2656                 FREQ2FBIN(5600, 0),
2657                 FREQ2FBIN(5700, 0),
2658                 FREQ2FBIN(5785, 0)
2659         },
2660         .calPierData5G = {
2661                         {
2662                                 {0, 0, 0, 0, 0},
2663                                 {0, 0, 0, 0, 0},
2664                                 {0, 0, 0, 0, 0},
2665                                 {0, 0, 0, 0, 0},
2666                                 {0, 0, 0, 0, 0},
2667                                 {0, 0, 0, 0, 0},
2668                                 {0, 0, 0, 0, 0},
2669                                 {0, 0, 0, 0, 0},
2670                         },
2671                         {
2672                                 {0, 0, 0, 0, 0},
2673                                 {0, 0, 0, 0, 0},
2674                                 {0, 0, 0, 0, 0},
2675                                 {0, 0, 0, 0, 0},
2676                                 {0, 0, 0, 0, 0},
2677                                 {0, 0, 0, 0, 0},
2678                                 {0, 0, 0, 0, 0},
2679                                 {0, 0, 0, 0, 0},
2680                         },
2681                         {
2682                                 {0, 0, 0, 0, 0},
2683                                 {0, 0, 0, 0, 0},
2684                                 {0, 0, 0, 0, 0},
2685                                 {0, 0, 0, 0, 0},
2686                                 {0, 0, 0, 0, 0},
2687                                 {0, 0, 0, 0, 0},
2688                                 {0, 0, 0, 0, 0},
2689                                 {0, 0, 0, 0, 0},
2690                         },
2691
2692         },
2693         .calTarget_freqbin_5G = {
2694                 FREQ2FBIN(5180, 0),
2695                 FREQ2FBIN(5240, 0),
2696                 FREQ2FBIN(5320, 0),
2697                 FREQ2FBIN(5400, 0),
2698                 FREQ2FBIN(5500, 0),
2699                 FREQ2FBIN(5600, 0),
2700                 FREQ2FBIN(5700, 0),
2701                 FREQ2FBIN(5825, 0)
2702         },
2703         .calTarget_freqbin_5GHT20 = {
2704                 FREQ2FBIN(5180, 0),
2705                 FREQ2FBIN(5240, 0),
2706                 FREQ2FBIN(5320, 0),
2707                 FREQ2FBIN(5400, 0),
2708                 FREQ2FBIN(5500, 0),
2709                 FREQ2FBIN(5700, 0),
2710                 FREQ2FBIN(5745, 0),
2711                 FREQ2FBIN(5825, 0)
2712         },
2713         .calTarget_freqbin_5GHT40 = {
2714                 FREQ2FBIN(5180, 0),
2715                 FREQ2FBIN(5240, 0),
2716                 FREQ2FBIN(5320, 0),
2717                 FREQ2FBIN(5400, 0),
2718                 FREQ2FBIN(5500, 0),
2719                 FREQ2FBIN(5700, 0),
2720                 FREQ2FBIN(5745, 0),
2721                 FREQ2FBIN(5825, 0)
2722          },
2723         .calTargetPower5G = {
2724                 /* 6-24,36,48,54 */
2725                 { {30, 30, 28, 24} },
2726                 { {30, 30, 28, 24} },
2727                 { {30, 30, 28, 24} },
2728                 { {30, 30, 28, 24} },
2729                 { {30, 30, 28, 24} },
2730                 { {30, 30, 28, 24} },
2731                 { {30, 30, 28, 24} },
2732                 { {30, 30, 28, 24} },
2733          },
2734         .calTargetPower5GHT20 = {
2735                 /*
2736                  * 0_8_16,1-3_9-11_17-19,
2737                  * 4,5,6,7,12,13,14,15,20,21,22,23
2738                  */
2739                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2740                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2741                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2742                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2743                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2744                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2745                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2746                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2747          },
2748         .calTargetPower5GHT40 =  {
2749                 /*
2750                  * 0_8_16,1-3_9-11_17-19,
2751                  * 4,5,6,7,12,13,14,15,20,21,22,23
2752                  */
2753                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2754                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2755                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2756                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2757                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2758                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2759                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2760                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2761          },
2762         .ctlIndex_5G =  {
2763                 0x10, 0x16, 0x18, 0x40, 0x46,
2764                 0x48, 0x30, 0x36, 0x38
2765         },
2766         .ctl_freqbin_5G =  {
2767                 {
2768                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2769                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2770                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2771                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2772                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2773                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2774                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2775                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2776                 },
2777                 {
2778                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2779                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2780                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2781                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2782                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2783                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2784                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2785                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2786                 },
2787
2788                 {
2789                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2790                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2791                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2792                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2793                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2794                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2795                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2796                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2797                 },
2798
2799                 {
2800                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2801                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2802                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2803                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2804                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2805                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2806                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2807                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2808                 },
2809
2810                 {
2811                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2812                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2813                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2814                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2815                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2816                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2817                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2818                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2819                 },
2820
2821                 {
2822                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2823                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2824                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2825                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2826                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2827                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2828                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2829                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
2830                 },
2831
2832                 {
2833                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2834                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2835                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2836                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2837                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2838                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2839                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2840                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2841                 },
2842
2843                 {
2844                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2845                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2846                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2847                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2848                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2849                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2850                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2851                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2852                 },
2853
2854                 {
2855                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2856                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2857                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2858                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2859                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2860                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2861                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2862                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2863                 }
2864          },
2865         .ctlPowerData_5G = {
2866                 {
2867                         {
2868                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2869                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2870                         }
2871                 },
2872                 {
2873                         {
2874                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2875                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2876                         }
2877                 },
2878                 {
2879                         {
2880                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2881                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2882                         }
2883                 },
2884                 {
2885                         {
2886                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2887                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2888                         }
2889                 },
2890                 {
2891                         {
2892                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2893                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2894                         }
2895                 },
2896                 {
2897                         {
2898                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2899                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2900                         }
2901                 },
2902                 {
2903                         {
2904                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2905                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2906                         }
2907                 },
2908                 {
2909                         {
2910                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2911                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2912                         }
2913                 },
2914                 {
2915                         {
2916                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2917                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2918                         }
2919                 },
2920          }
2921 };
2922
2923
2924 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2925         &ar9300_default,
2926         &ar9300_x112,
2927         &ar9300_h116,
2928         &ar9300_h112,
2929         &ar9300_x113,
2930 };
2931
2932 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2933 {
2934 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2935         int it;
2936
2937         for (it = 0; it < N_LOOP; it++)
2938                 if (ar9300_eep_templates[it]->templateVersion == id)
2939                         return ar9300_eep_templates[it];
2940         return NULL;
2941 #undef N_LOOP
2942 }
2943
2944 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2945 {
2946         return 0;
2947 }
2948
2949 static int interpolate(int x, int xa, int xb, int ya, int yb)
2950 {
2951         int bf, factor, plus;
2952
2953         bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2954         factor = bf / 2;
2955         plus = bf % 2;
2956         return ya + factor + plus;
2957 }
2958
2959 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2960                                       enum eeprom_param param)
2961 {
2962         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2963         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2964
2965         switch (param) {
2966         case EEP_MAC_LSW:
2967                 return get_unaligned_be16(eep->macAddr);
2968         case EEP_MAC_MID:
2969                 return get_unaligned_be16(eep->macAddr + 2);
2970         case EEP_MAC_MSW:
2971                 return get_unaligned_be16(eep->macAddr + 4);
2972         case EEP_REG_0:
2973                 return le16_to_cpu(pBase->regDmn[0]);
2974         case EEP_OP_CAP:
2975                 return pBase->deviceCap;
2976         case EEP_OP_MODE:
2977                 return pBase->opCapFlags.opFlags;
2978         case EEP_RF_SILENT:
2979                 return pBase->rfSilent;
2980         case EEP_TX_MASK:
2981                 return (pBase->txrxMask >> 4) & 0xf;
2982         case EEP_RX_MASK:
2983                 return pBase->txrxMask & 0xf;
2984         case EEP_PAPRD:
2985                 return !!(pBase->featureEnable & BIT(5));
2986         case EEP_CHAIN_MASK_REDUCE:
2987                 return (pBase->miscConfiguration >> 0x3) & 0x1;
2988         case EEP_ANT_DIV_CTL1:
2989                 return eep->base_ext1.ant_div_control;
2990         case EEP_ANTENNA_GAIN_5G:
2991                 return eep->modalHeader5G.antennaGain;
2992         case EEP_ANTENNA_GAIN_2G:
2993                 return eep->modalHeader2G.antennaGain;
2994         default:
2995                 return 0;
2996         }
2997 }
2998
2999 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3000                                     u8 *buffer)
3001 {
3002         u16 val;
3003
3004         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3005                 return false;
3006
3007         *buffer = (val >> (8 * (address % 2))) & 0xff;
3008         return true;
3009 }
3010
3011 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3012                                     u8 *buffer)
3013 {
3014         u16 val;
3015
3016         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3017                 return false;
3018
3019         buffer[0] = val >> 8;
3020         buffer[1] = val & 0xff;
3021
3022         return true;
3023 }
3024
3025 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3026                                int count)
3027 {
3028         struct ath_common *common = ath9k_hw_common(ah);
3029         int i;
3030
3031         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3032                 ath_dbg(common, EEPROM, "eeprom address not in range\n");
3033                 return false;
3034         }
3035
3036         /*
3037          * Since we're reading the bytes in reverse order from a little-endian
3038          * word stream, an even address means we only use the lower half of
3039          * the 16-bit word at that address
3040          */
3041         if (address % 2 == 0) {
3042                 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3043                         goto error;
3044
3045                 count--;
3046         }
3047
3048         for (i = 0; i < count / 2; i++) {
3049                 if (!ar9300_eeprom_read_word(common, address, buffer))
3050                         goto error;
3051
3052                 address -= 2;
3053                 buffer += 2;
3054         }
3055
3056         if (count % 2)
3057                 if (!ar9300_eeprom_read_byte(common, address, buffer))
3058                         goto error;
3059
3060         return true;
3061
3062 error:
3063         ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3064                 address);
3065         return false;
3066 }
3067
3068 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3069 {
3070         REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3071
3072         if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3073                            AR9300_OTP_STATUS_VALID, 1000))
3074                 return false;
3075
3076         *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3077         return true;
3078 }
3079
3080 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3081                             int count)
3082 {
3083         u32 data;
3084         int i;
3085
3086         for (i = 0; i < count; i++) {
3087                 int offset = 8 * ((address - i) % 4);
3088                 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3089                         return false;
3090
3091                 buffer[i] = (data >> offset) & 0xff;
3092         }
3093
3094         return true;
3095 }
3096
3097
3098 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3099                                    int *length, int *major, int *minor)
3100 {
3101         unsigned long value[4];
3102
3103         value[0] = best[0];
3104         value[1] = best[1];
3105         value[2] = best[2];
3106         value[3] = best[3];
3107         *code = ((value[0] >> 5) & 0x0007);
3108         *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3109         *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3110         *major = (value[2] & 0x000f);
3111         *minor = (value[3] & 0x00ff);
3112 }
3113
3114 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3115 {
3116         int it, checksum = 0;
3117
3118         for (it = 0; it < dsize; it++) {
3119                 checksum += data[it];
3120                 checksum &= 0xffff;
3121         }
3122
3123         return checksum;
3124 }
3125
3126 static bool ar9300_uncompress_block(struct ath_hw *ah,
3127                                     u8 *mptr,
3128                                     int mdataSize,
3129                                     u8 *block,
3130                                     int size)
3131 {
3132         int it;
3133         int spot;
3134         int offset;
3135         int length;
3136         struct ath_common *common = ath9k_hw_common(ah);
3137
3138         spot = 0;
3139
3140         for (it = 0; it < size; it += (length+2)) {
3141                 offset = block[it];
3142                 offset &= 0xff;
3143                 spot += offset;
3144                 length = block[it+1];
3145                 length &= 0xff;
3146
3147                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3148                         ath_dbg(common, EEPROM,
3149                                 "Restore at %d: spot=%d offset=%d length=%d\n",
3150                                 it, spot, offset, length);
3151                         memcpy(&mptr[spot], &block[it+2], length);
3152                         spot += length;
3153                 } else if (length > 0) {
3154                         ath_dbg(common, EEPROM,
3155                                 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3156                                 it, spot, offset, length);
3157                         return false;
3158                 }
3159         }
3160         return true;
3161 }
3162
3163 static int ar9300_compress_decision(struct ath_hw *ah,
3164                                     int it,
3165                                     int code,
3166                                     int reference,
3167                                     u8 *mptr,
3168                                     u8 *word, int length, int mdata_size)
3169 {
3170         struct ath_common *common = ath9k_hw_common(ah);
3171         const struct ar9300_eeprom *eep = NULL;
3172
3173         switch (code) {
3174         case _CompressNone:
3175                 if (length != mdata_size) {
3176                         ath_dbg(common, EEPROM,
3177                                 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3178                                 mdata_size, length);
3179                         return -1;
3180                 }
3181                 memcpy(mptr, word + COMP_HDR_LEN, length);
3182                 ath_dbg(common, EEPROM,
3183                         "restored eeprom %d: uncompressed, length %d\n",
3184                         it, length);
3185                 break;
3186         case _CompressBlock:
3187                 if (reference == 0) {
3188                 } else {
3189                         eep = ar9003_eeprom_struct_find_by_id(reference);
3190                         if (eep == NULL) {
3191                                 ath_dbg(common, EEPROM,
3192                                         "can't find reference eeprom struct %d\n",
3193                                         reference);
3194                                 return -1;
3195                         }
3196                         memcpy(mptr, eep, mdata_size);
3197                 }
3198                 ath_dbg(common, EEPROM,
3199                         "restore eeprom %d: block, reference %d, length %d\n",
3200                         it, reference, length);
3201                 ar9300_uncompress_block(ah, mptr, mdata_size,
3202                                         (word + COMP_HDR_LEN), length);
3203                 break;
3204         default:
3205                 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
3206                 return -1;
3207         }
3208         return 0;
3209 }
3210
3211 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3212                                int count);
3213
3214 static bool ar9300_check_header(void *data)
3215 {
3216         u32 *word = data;
3217         return !(*word == 0 || *word == ~0);
3218 }
3219
3220 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3221                                        int base_addr)
3222 {
3223         u8 header[4];
3224
3225         if (!read(ah, base_addr, header, 4))
3226                 return false;
3227
3228         return ar9300_check_header(header);
3229 }
3230
3231 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3232                                        int mdata_size)
3233 {
3234         struct ath_common *common = ath9k_hw_common(ah);
3235         u16 *data = (u16 *) mptr;
3236         int i;
3237
3238         for (i = 0; i < mdata_size / 2; i++, data++)
3239                 ath9k_hw_nvram_read(common, i, data);
3240
3241         return 0;
3242 }
3243 /*
3244  * Read the configuration data from the eeprom.
3245  * The data can be put in any specified memory buffer.
3246  *
3247  * Returns -1 on error.
3248  * Returns address of next memory location on success.
3249  */
3250 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3251                                           u8 *mptr, int mdata_size)
3252 {
3253 #define MDEFAULT 15
3254 #define MSTATE 100
3255         int cptr;
3256         u8 *word;
3257         int code;
3258         int reference, length, major, minor;
3259         int osize;
3260         int it;
3261         u16 checksum, mchecksum;
3262         struct ath_common *common = ath9k_hw_common(ah);
3263         struct ar9300_eeprom *eep;
3264         eeprom_read_op read;
3265
3266         if (ath9k_hw_use_flash(ah)) {
3267                 u8 txrx;
3268
3269                 ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3270
3271                 /* check if eeprom contains valid data */
3272                 eep = (struct ar9300_eeprom *) mptr;
3273                 txrx = eep->baseEepHeader.txrxMask;
3274                 if (txrx != 0 && txrx != 0xff)
3275                         return 0;
3276         }
3277
3278         word = kzalloc(2048, GFP_KERNEL);
3279         if (!word)
3280                 return -ENOMEM;
3281
3282         memcpy(mptr, &ar9300_default, mdata_size);
3283
3284         read = ar9300_read_eeprom;
3285         if (AR_SREV_9485(ah))
3286                 cptr = AR9300_BASE_ADDR_4K;
3287         else if (AR_SREV_9330(ah))
3288                 cptr = AR9300_BASE_ADDR_512;
3289         else
3290                 cptr = AR9300_BASE_ADDR;
3291         ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3292                 cptr);
3293         if (ar9300_check_eeprom_header(ah, read, cptr))
3294                 goto found;
3295
3296         cptr = AR9300_BASE_ADDR_512;
3297         ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3298                 cptr);
3299         if (ar9300_check_eeprom_header(ah, read, cptr))
3300                 goto found;
3301
3302         read = ar9300_read_otp;
3303         cptr = AR9300_BASE_ADDR;
3304         ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3305         if (ar9300_check_eeprom_header(ah, read, cptr))
3306                 goto found;
3307
3308         cptr = AR9300_BASE_ADDR_512;
3309         ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3310         if (ar9300_check_eeprom_header(ah, read, cptr))
3311                 goto found;
3312
3313         goto fail;
3314
3315 found:
3316         ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
3317
3318         for (it = 0; it < MSTATE; it++) {
3319                 if (!read(ah, cptr, word, COMP_HDR_LEN))
3320                         goto fail;
3321
3322                 if (!ar9300_check_header(word))
3323                         break;
3324
3325                 ar9300_comp_hdr_unpack(word, &code, &reference,
3326                                        &length, &major, &minor);
3327                 ath_dbg(common, EEPROM,
3328                         "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3329                         cptr, code, reference, length, major, minor);
3330                 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3331                     (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3332                         ath_dbg(common, EEPROM, "Skipping bad header\n");
3333                         cptr -= COMP_HDR_LEN;
3334                         continue;
3335                 }
3336
3337                 osize = length;
3338                 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3339                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3340                 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3341                 ath_dbg(common, EEPROM, "checksum %x %x\n",
3342                         checksum, mchecksum);
3343                 if (checksum == mchecksum) {
3344                         ar9300_compress_decision(ah, it, code, reference, mptr,
3345                                                  word, length, mdata_size);
3346                 } else {
3347                         ath_dbg(common, EEPROM,
3348                                 "skipping block with bad checksum\n");
3349                 }
3350                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3351         }
3352
3353         kfree(word);
3354         return cptr;
3355
3356 fail:
3357         kfree(word);
3358         return -1;
3359 }
3360
3361 /*
3362  * Restore the configuration structure by reading the eeprom.
3363  * This function destroys any existing in-memory structure
3364  * content.
3365  */
3366 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3367 {
3368         u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3369
3370         if (ar9300_eeprom_restore_internal(ah, mptr,
3371                         sizeof(struct ar9300_eeprom)) < 0)
3372                 return false;
3373
3374         return true;
3375 }
3376
3377 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3378 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3379                                     struct ar9300_modal_eep_header *modal_hdr)
3380 {
3381         PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3382         PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3383         PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3384         PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3385         PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3386         PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3387         PR_EEP("Switch Settle", modal_hdr->switchSettling);
3388         PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3389         PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3390         PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3391         PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3392         PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3393         PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3394         PR_EEP("Temp Slope", modal_hdr->tempSlope);
3395         PR_EEP("Volt Slope", modal_hdr->voltSlope);
3396         PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3397         PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3398         PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3399         PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3400         PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3401         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3402         PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3403         PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3404         PR_EEP("Quick Drop", modal_hdr->quick_drop);
3405         PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
3406         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3407         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3408         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3409         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3410         PR_EEP("txClip", modal_hdr->txClip);
3411         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3412
3413         return len;
3414 }
3415
3416 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3417                                        u8 *buf, u32 len, u32 size)
3418 {
3419         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3420         struct ar9300_base_eep_hdr *pBase;
3421
3422         if (!dump_base_hdr) {
3423                 len += snprintf(buf + len, size - len,
3424                                 "%20s :\n", "2GHz modal Header");
3425                 len = ar9003_dump_modal_eeprom(buf, len, size,
3426                                                 &eep->modalHeader2G);
3427                 len += snprintf(buf + len, size - len,
3428                                 "%20s :\n", "5GHz modal Header");
3429                 len = ar9003_dump_modal_eeprom(buf, len, size,
3430                                                 &eep->modalHeader5G);
3431                 goto out;
3432         }
3433
3434         pBase = &eep->baseEepHeader;
3435
3436         PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3437         PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3438         PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3439         PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3440         PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3441         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3442                                 AR5416_OPFLAGS_11A));
3443         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3444                                 AR5416_OPFLAGS_11G));
3445         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3446                                         AR5416_OPFLAGS_N_2G_HT20));
3447         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3448                                         AR5416_OPFLAGS_N_2G_HT40));
3449         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3450                                         AR5416_OPFLAGS_N_5G_HT20));
3451         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3452                                         AR5416_OPFLAGS_N_5G_HT40));
3453         PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3454         PR_EEP("RF Silent", pBase->rfSilent);
3455         PR_EEP("BT option", pBase->blueToothOptions);
3456         PR_EEP("Device Cap", pBase->deviceCap);
3457         PR_EEP("Device Type", pBase->deviceType);
3458         PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3459         PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3460         PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3461         PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3462         PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3463         PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3464         PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3465         PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3466         PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3467         PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3468         PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
3469         PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3470         PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3471         PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3472         PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3473         PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3474         PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3475         PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3476         PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3477
3478         len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3479                         ah->eeprom.ar9300_eep.macAddr);
3480 out:
3481         if (len > size)
3482                 len = size;
3483
3484         return len;
3485 }
3486 #else
3487 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3488                                        u8 *buf, u32 len, u32 size)
3489 {
3490         return 0;
3491 }
3492 #endif
3493
3494 /* XXX: review hardware docs */
3495 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3496 {
3497         return ah->eeprom.ar9300_eep.eepromVersion;
3498 }
3499
3500 /* XXX: could be read from the eepromVersion, not sure yet */
3501 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3502 {
3503         return 0;
3504 }
3505
3506 static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
3507                                                            bool is2ghz)
3508 {
3509         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3510
3511         if (is2ghz)
3512                 return &eep->modalHeader2G;
3513         else
3514                 return &eep->modalHeader5G;
3515 }
3516
3517 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3518 {
3519         int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
3520
3521         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3522                 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3523         else if (AR_SREV_9462(ah) || AR_SREV_9550(ah))
3524                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3525         else {
3526                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3527                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3528                                 AR_CH0_THERM_XPABIASLVL_MSB,
3529                                 bias >> 2);
3530                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3531                                 AR_CH0_THERM_XPASHORT2GND, 1);
3532         }
3533 }
3534
3535 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
3536 {
3537         return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
3538 }
3539
3540
3541 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3542 {
3543         return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
3544 }
3545
3546 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3547 {
3548         return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
3549 }
3550
3551 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
3552                                         bool is2ghz)
3553 {
3554         __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
3555         return le16_to_cpu(val);
3556 }
3557
3558 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3559 {
3560         int chain;
3561         u32 regval;
3562         u32 ant_div_ctl1;
3563         static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3564                         AR_PHY_SWITCH_CHAIN_0,
3565                         AR_PHY_SWITCH_CHAIN_1,
3566                         AR_PHY_SWITCH_CHAIN_2,
3567         };
3568
3569         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3570
3571         if (AR_SREV_9462(ah)) {
3572                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3573                                 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3574         } else if (AR_SREV_9550(ah)) {
3575                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3576                                 AR_SWITCH_TABLE_COM_AR9550_ALL, value);
3577         } else
3578                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3579                               AR_SWITCH_TABLE_COM_ALL, value);
3580
3581
3582         /*
3583          *   AR9462 defines new switch table for BT/WLAN,
3584          *       here's new field name in XXX.ref for both 2G and 5G.
3585          *   Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3586          *   15:12   R/W     SWITCH_TABLE_COM_SPDT_WLAN_RX
3587          * SWITCH_TABLE_COM_SPDT_WLAN_RX
3588          *
3589          *   11:8     R/W     SWITCH_TABLE_COM_SPDT_WLAN_TX
3590          * SWITCH_TABLE_COM_SPDT_WLAN_TX
3591          *
3592          *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3593          * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3594          */
3595         if (AR_SREV_9462_20_OR_LATER(ah)) {
3596                 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3597                 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3598                                 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3599                 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
3600         }
3601
3602         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3603         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3604
3605         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3606                 if ((ah->rxchainmask & BIT(chain)) ||
3607                     (ah->txchainmask & BIT(chain))) {
3608                         value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3609                                                              is2ghz);
3610                         REG_RMW_FIELD(ah, switch_chain_reg[chain],
3611                                       AR_SWITCH_TABLE_ALL, value);
3612                 }
3613         }
3614
3615         if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3616                 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3617                 /*
3618                  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3619                  * are the fields present
3620                  */
3621                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3622                 regval &= (~AR_ANT_DIV_CTRL_ALL);
3623                 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3624                 /* enable_lnadiv */
3625                 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3626                 regval |= ((value >> 6) & 0x1) <<
3627                                 AR_PHY_9485_ANT_DIV_LNADIV_S;
3628                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3629
3630                 /*enable fast_div */
3631                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3632                 regval &= (~AR_FAST_DIV_ENABLE);
3633                 regval |= ((value >> 7) & 0x1) <<
3634                                 AR_FAST_DIV_ENABLE_S;
3635                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3636                 ant_div_ctl1 =
3637                         ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3638                 /* check whether antenna diversity is enabled */
3639                 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3640                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3641                         /*
3642                          * clear bits 25-30 main_lnaconf, alt_lnaconf,
3643                          * main_tb, alt_tb
3644                          */
3645                         regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3646                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3647                                         AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3648                                         AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3649                         /* by default use LNA1 for the main antenna */
3650                         regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3651                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3652                         regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3653                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3654                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3655                 }
3656
3657
3658         }
3659
3660 }
3661
3662 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3663 {
3664         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3665         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3666         int drive_strength;
3667         unsigned long reg;
3668
3669         drive_strength = pBase->miscConfiguration & BIT(0);
3670         if (!drive_strength)
3671                 return;
3672
3673         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3674         reg &= ~0x00ffffc0;
3675         reg |= 0x5 << 21;
3676         reg |= 0x5 << 18;
3677         reg |= 0x5 << 15;
3678         reg |= 0x5 << 12;
3679         reg |= 0x5 << 9;
3680         reg |= 0x5 << 6;
3681         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3682
3683         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3684         reg &= ~0xffffffe0;
3685         reg |= 0x5 << 29;
3686         reg |= 0x5 << 26;
3687         reg |= 0x5 << 23;
3688         reg |= 0x5 << 20;
3689         reg |= 0x5 << 17;
3690         reg |= 0x5 << 14;
3691         reg |= 0x5 << 11;
3692         reg |= 0x5 << 8;
3693         reg |= 0x5 << 5;
3694         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3695
3696         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3697         reg &= ~0xff800000;
3698         reg |= 0x5 << 29;
3699         reg |= 0x5 << 26;
3700         reg |= 0x5 << 23;
3701         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3702 }
3703
3704 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3705                                      struct ath9k_channel *chan)
3706 {
3707         int f[3], t[3];
3708         u16 value;
3709         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3710
3711         if (chain >= 0 && chain < 3) {
3712                 if (IS_CHAN_2GHZ(chan))
3713                         return eep->modalHeader2G.xatten1DB[chain];
3714                 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3715                         t[0] = eep->base_ext2.xatten1DBLow[chain];
3716                         f[0] = 5180;
3717                         t[1] = eep->modalHeader5G.xatten1DB[chain];
3718                         f[1] = 5500;
3719                         t[2] = eep->base_ext2.xatten1DBHigh[chain];
3720                         f[2] = 5785;
3721                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3722                                                             f, t, 3);
3723                         return value;
3724                 } else
3725                         return eep->modalHeader5G.xatten1DB[chain];
3726         }
3727
3728         return 0;
3729 }
3730
3731
3732 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3733                                             struct ath9k_channel *chan)
3734 {
3735         int f[3], t[3];
3736         u16 value;
3737         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3738
3739         if (chain >= 0 && chain < 3) {
3740                 if (IS_CHAN_2GHZ(chan))
3741                         return eep->modalHeader2G.xatten1Margin[chain];
3742                 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3743                         t[0] = eep->base_ext2.xatten1MarginLow[chain];
3744                         f[0] = 5180;
3745                         t[1] = eep->modalHeader5G.xatten1Margin[chain];
3746                         f[1] = 5500;
3747                         t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3748                         f[2] = 5785;
3749                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3750                                                             f, t, 3);
3751                         return value;
3752                 } else
3753                         return eep->modalHeader5G.xatten1Margin[chain];
3754         }
3755
3756         return 0;
3757 }
3758
3759 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3760 {
3761         int i;
3762         u16 value;
3763         unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3764                                           AR_PHY_EXT_ATTEN_CTL_1,
3765                                           AR_PHY_EXT_ATTEN_CTL_2,
3766                                          };
3767
3768         /* Test value. if 0 then attenuation is unused. Don't load anything. */
3769         for (i = 0; i < 3; i++) {
3770                 if (ah->txchainmask & BIT(i)) {
3771                         value = ar9003_hw_atten_chain_get(ah, i, chan);
3772                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3773                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3774
3775                         value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3776                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3777                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3778                                       value);
3779                 }
3780         }
3781 }
3782
3783 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3784 {
3785         int timeout = 100;
3786
3787         while (pmu_set != REG_READ(ah, pmu_reg)) {
3788                 if (timeout-- == 0)
3789                         return false;
3790                 REG_WRITE(ah, pmu_reg, pmu_set);
3791                 udelay(10);
3792         }
3793
3794         return true;
3795 }
3796
3797 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3798 {
3799         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3800         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3801         u32 reg_val;
3802
3803         if (pBase->featureEnable & BIT(4)) {
3804                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3805                         int reg_pmu_set;
3806
3807                         reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3808                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3809                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3810                                 return;
3811
3812                         if (AR_SREV_9330(ah)) {
3813                                 if (ah->is_clk_25mhz) {
3814                                         reg_pmu_set = (3 << 1) | (8 << 4) |
3815                                                       (3 << 8) | (1 << 14) |
3816                                                       (6 << 17) | (1 << 20) |
3817                                                       (3 << 24);
3818                                 } else {
3819                                         reg_pmu_set = (4 << 1)  | (7 << 4) |
3820                                                       (3 << 8)  | (1 << 14) |
3821                                                       (6 << 17) | (1 << 20) |
3822                                                       (3 << 24);
3823                                 }
3824                         } else {
3825                                 reg_pmu_set = (5 << 1) | (7 << 4) |
3826                                               (2 << 8) | (2 << 14) |
3827                                               (6 << 17) | (1 << 20) |
3828                                               (3 << 24) | (1 << 28);
3829                         }
3830
3831                         REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3832                         if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3833                                 return;
3834
3835                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3836                                         | (4 << 26);
3837                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3838                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3839                                 return;
3840
3841                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3842                                         | (1 << 21);
3843                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3844                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3845                                 return;
3846                 } else if (AR_SREV_9462(ah)) {
3847                         reg_val = le32_to_cpu(pBase->swreg);
3848                         REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3849                 } else {
3850                         /* Internal regulator is ON. Write swreg register. */
3851                         reg_val = le32_to_cpu(pBase->swreg);
3852                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3853                                   REG_READ(ah, AR_RTC_REG_CONTROL1) &
3854                                   (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3855                         REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3856                         /* Set REG_CONTROL1.SWREG_PROGRAM */
3857                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3858                                   REG_READ(ah,
3859                                            AR_RTC_REG_CONTROL1) |
3860                                            AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3861                 }
3862         } else {
3863                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3864                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3865                         while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3866                                                 AR_PHY_PMU2_PGM))
3867                                 udelay(10);
3868
3869                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3870                         while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3871                                                 AR_PHY_PMU1_PWD))
3872                                 udelay(10);
3873                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3874                         while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3875                                                 AR_PHY_PMU2_PGM))
3876                                 udelay(10);
3877                 } else if (AR_SREV_9462(ah))
3878                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3879                 else {
3880                         reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3881                                 AR_RTC_FORCE_SWREG_PRD;
3882                         REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3883                 }
3884         }
3885
3886 }
3887
3888 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3889 {
3890         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3891         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3892
3893         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3894                 return;
3895
3896         if (eep->baseEepHeader.featureEnable & 0x40) {
3897                 tuning_caps_param &= 0x7f;
3898                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3899                               tuning_caps_param);
3900                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3901                               tuning_caps_param);
3902         }
3903 }
3904
3905 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3906 {
3907         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3908         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3909         int quick_drop;
3910         s32 t[3], f[3] = {5180, 5500, 5785};
3911
3912         if (!(pBase->miscConfiguration & BIT(1)))
3913                 return;
3914
3915         if (freq < 4000)
3916                 quick_drop = eep->modalHeader2G.quick_drop;
3917         else {
3918                 t[0] = eep->base_ext1.quick_drop_low;
3919                 t[1] = eep->modalHeader5G.quick_drop;
3920                 t[2] = eep->base_ext1.quick_drop_high;
3921                 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3922         }
3923         REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3924 }
3925
3926 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
3927 {
3928         u32 value;
3929
3930         value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
3931
3932         REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3933                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3934         REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3935                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3936 }
3937
3938 static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
3939 {
3940         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3941         u8 xpa_ctl;
3942
3943         if (!(eep->baseEepHeader.featureEnable & 0x80))
3944                 return;
3945
3946         if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
3947                 return;
3948
3949         xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
3950         if (is2ghz)
3951                 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3952                               AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
3953         else
3954                 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3955                               AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
3956 }
3957
3958 static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
3959 {
3960         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3961         u8 bias;
3962
3963         if (!(eep->baseEepHeader.featureEnable & 0x40))
3964                 return;
3965
3966         if (!AR_SREV_9300(ah))
3967                 return;
3968
3969         bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
3970         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3971                       bias & 0x3);
3972         bias >>= 2;
3973         REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3974                       bias & 0x3);
3975         bias >>= 2;
3976         REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3977                       bias & 0x3);
3978 }
3979
3980 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3981                                              struct ath9k_channel *chan)
3982 {
3983         bool is2ghz = IS_CHAN_2GHZ(chan);
3984         ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
3985         ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
3986         ar9003_hw_ant_ctrl_apply(ah, is2ghz);
3987         ar9003_hw_drive_strength_apply(ah);
3988         ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
3989         ar9003_hw_atten_apply(ah, chan);
3990         ar9003_hw_quick_drop_apply(ah, chan->channel);
3991         if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
3992                 ar9003_hw_internal_regulator_apply(ah);
3993         ar9003_hw_apply_tuning_caps(ah);
3994         ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
3995 }
3996
3997 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3998                                       struct ath9k_channel *chan)
3999 {
4000 }
4001
4002 /*
4003  * Returns the interpolated y value corresponding to the specified x value
4004  * from the np ordered pairs of data (px,py).
4005  * The pairs do not have to be in any order.
4006  * If the specified x value is less than any of the px,
4007  * the returned y value is equal to the py for the lowest px.
4008  * If the specified x value is greater than any of the px,
4009  * the returned y value is equal to the py for the highest px.
4010  */
4011 static int ar9003_hw_power_interpolate(int32_t x,
4012                                        int32_t *px, int32_t *py, u_int16_t np)
4013 {
4014         int ip = 0;
4015         int lx = 0, ly = 0, lhave = 0;
4016         int hx = 0, hy = 0, hhave = 0;
4017         int dx = 0;
4018         int y = 0;
4019
4020         lhave = 0;
4021         hhave = 0;
4022
4023         /* identify best lower and higher x calibration measurement */
4024         for (ip = 0; ip < np; ip++) {
4025                 dx = x - px[ip];
4026
4027                 /* this measurement is higher than our desired x */
4028                 if (dx <= 0) {
4029                         if (!hhave || dx > (x - hx)) {
4030                                 /* new best higher x measurement */
4031                                 hx = px[ip];
4032                                 hy = py[ip];
4033                                 hhave = 1;
4034                         }
4035                 }
4036                 /* this measurement is lower than our desired x */
4037                 if (dx >= 0) {
4038                         if (!lhave || dx < (x - lx)) {
4039                                 /* new best lower x measurement */
4040                                 lx = px[ip];
4041                                 ly = py[ip];
4042                                 lhave = 1;
4043                         }
4044                 }
4045         }
4046
4047         /* the low x is good */
4048         if (lhave) {
4049                 /* so is the high x */
4050                 if (hhave) {
4051                         /* they're the same, so just pick one */
4052                         if (hx == lx)
4053                                 y = ly;
4054                         else    /* interpolate  */
4055                                 y = interpolate(x, lx, hx, ly, hy);
4056                 } else          /* only low is good, use it */
4057                         y = ly;
4058         } else if (hhave)       /* only high is good, use it */
4059                 y = hy;
4060         else /* nothing is good,this should never happen unless np=0, ???? */
4061                 y = -(1 << 30);
4062         return y;
4063 }
4064
4065 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4066                                        u16 rateIndex, u16 freq, bool is2GHz)
4067 {
4068         u16 numPiers, i;
4069         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4070         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4071         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4072         struct cal_tgt_pow_legacy *pEepromTargetPwr;
4073         u8 *pFreqBin;
4074
4075         if (is2GHz) {
4076                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4077                 pEepromTargetPwr = eep->calTargetPower2G;
4078                 pFreqBin = eep->calTarget_freqbin_2G;
4079         } else {
4080                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4081                 pEepromTargetPwr = eep->calTargetPower5G;
4082                 pFreqBin = eep->calTarget_freqbin_5G;
4083         }
4084
4085         /*
4086          * create array of channels and targetpower from
4087          * targetpower piers stored on eeprom
4088          */
4089         for (i = 0; i < numPiers; i++) {
4090                 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4091                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4092         }
4093
4094         /* interpolate to get target power for given frequency */
4095         return (u8) ar9003_hw_power_interpolate((s32) freq,
4096                                                  freqArray,
4097                                                  targetPowerArray, numPiers);
4098 }
4099
4100 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4101                                             u16 rateIndex,
4102                                             u16 freq, bool is2GHz)
4103 {
4104         u16 numPiers, i;
4105         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4106         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4107         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4108         struct cal_tgt_pow_ht *pEepromTargetPwr;
4109         u8 *pFreqBin;
4110
4111         if (is2GHz) {
4112                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4113                 pEepromTargetPwr = eep->calTargetPower2GHT20;
4114                 pFreqBin = eep->calTarget_freqbin_2GHT20;
4115         } else {
4116                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4117                 pEepromTargetPwr = eep->calTargetPower5GHT20;
4118                 pFreqBin = eep->calTarget_freqbin_5GHT20;
4119         }
4120
4121         /*
4122          * create array of channels and targetpower
4123          * from targetpower piers stored on eeprom
4124          */
4125         for (i = 0; i < numPiers; i++) {
4126                 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4127                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4128         }
4129
4130         /* interpolate to get target power for given frequency */
4131         return (u8) ar9003_hw_power_interpolate((s32) freq,
4132                                                  freqArray,
4133                                                  targetPowerArray, numPiers);
4134 }
4135
4136 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4137                                             u16 rateIndex,
4138                                             u16 freq, bool is2GHz)
4139 {
4140         u16 numPiers, i;
4141         s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4142         s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4143         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4144         struct cal_tgt_pow_ht *pEepromTargetPwr;
4145         u8 *pFreqBin;
4146
4147         if (is2GHz) {
4148                 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4149                 pEepromTargetPwr = eep->calTargetPower2GHT40;
4150                 pFreqBin = eep->calTarget_freqbin_2GHT40;
4151         } else {
4152                 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4153                 pEepromTargetPwr = eep->calTargetPower5GHT40;
4154                 pFreqBin = eep->calTarget_freqbin_5GHT40;
4155         }
4156
4157         /*
4158          * create array of channels and targetpower from
4159          * targetpower piers stored on eeprom
4160          */
4161         for (i = 0; i < numPiers; i++) {
4162                 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4163                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4164         }
4165
4166         /* interpolate to get target power for given frequency */
4167         return (u8) ar9003_hw_power_interpolate((s32) freq,
4168                                                  freqArray,
4169                                                  targetPowerArray, numPiers);
4170 }
4171
4172 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4173                                            u16 rateIndex, u16 freq)
4174 {
4175         u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4176         s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4177         s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4178         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4179         struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4180         u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4181
4182         /*
4183          * create array of channels and targetpower from
4184          * targetpower piers stored on eeprom
4185          */
4186         for (i = 0; i < numPiers; i++) {
4187                 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
4188                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4189         }
4190
4191         /* interpolate to get target power for given frequency */
4192         return (u8) ar9003_hw_power_interpolate((s32) freq,
4193                                                  freqArray,
4194                                                  targetPowerArray, numPiers);
4195 }
4196
4197 /* Set tx power registers to array of values passed in */
4198 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4199 {
4200 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
4201         /* make sure forced gain is not set */
4202         REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4203
4204         /* Write the OFDM power per rate set */
4205
4206         /* 6 (LSB), 9, 12, 18 (MSB) */
4207         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4208                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4209                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4210                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4211                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4212
4213         /* 24 (LSB), 36, 48, 54 (MSB) */
4214         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4215                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4216                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4217                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4218                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4219
4220         /* Write the CCK power per rate set */
4221
4222         /* 1L (LSB), reserved, 2L, 2S (MSB) */
4223         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4224                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4225                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4226                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
4227                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4228
4229         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4230         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4231                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4232                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4233                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4234                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4235             );
4236
4237         /* Write the power for duplicated frames - HT40 */
4238
4239         /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4240         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4241                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4242                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4243                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
4244                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
4245             );
4246
4247         /* Write the HT20 power per rate set */
4248
4249         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4250         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4251                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4252                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4253                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4254                   POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4255             );
4256
4257         /* 6 (LSB), 7, 12, 13 (MSB) */
4258         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4259                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4260                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4261                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4262                   POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4263             );
4264
4265         /* 14 (LSB), 15, 20, 21 */
4266         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4267                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4268                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4269                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4270                   POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4271             );
4272
4273         /* Mixed HT20 and HT40 rates */
4274
4275         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4276         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4277                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4278                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4279                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4280                   POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4281             );
4282
4283         /*
4284          * Write the HT40 power per rate set
4285          * correct PAR difference between HT40 and HT20/LEGACY
4286          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4287          */
4288         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4289                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4290                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4291                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4292                   POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4293             );
4294
4295         /* 6 (LSB), 7, 12, 13 (MSB) */
4296         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4297                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4298                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4299                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4300                   POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4301             );
4302
4303         /* 14 (LSB), 15, 20, 21 */
4304         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4305                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4306                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4307                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4308                   POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4309             );
4310
4311         return 0;
4312 #undef POW_SM
4313 }
4314
4315 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4316                                                u8 *targetPowerValT2,
4317                                                bool is2GHz)
4318 {
4319         targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4320             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4321                                          is2GHz);
4322         targetPowerValT2[ALL_TARGET_LEGACY_36] =
4323             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4324                                          is2GHz);
4325         targetPowerValT2[ALL_TARGET_LEGACY_48] =
4326             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4327                                          is2GHz);
4328         targetPowerValT2[ALL_TARGET_LEGACY_54] =
4329             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4330                                          is2GHz);
4331 }
4332
4333 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4334                                             u8 *targetPowerValT2)
4335 {
4336         targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4337             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4338                                              freq);
4339         targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4340             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4341         targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4342             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4343         targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4344             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4345 }
4346
4347 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4348                                              u8 *targetPowerValT2, bool is2GHz)
4349 {
4350         targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4351             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4352                                               is2GHz);
4353         targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4354             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4355                                               freq, is2GHz);
4356         targetPowerValT2[ALL_TARGET_HT20_4] =
4357             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4358                                               is2GHz);
4359         targetPowerValT2[ALL_TARGET_HT20_5] =
4360             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4361                                               is2GHz);
4362         targetPowerValT2[ALL_TARGET_HT20_6] =
4363             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4364                                               is2GHz);
4365         targetPowerValT2[ALL_TARGET_HT20_7] =
4366             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4367                                               is2GHz);
4368         targetPowerValT2[ALL_TARGET_HT20_12] =
4369             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4370                                               is2GHz);
4371         targetPowerValT2[ALL_TARGET_HT20_13] =
4372             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4373                                               is2GHz);
4374         targetPowerValT2[ALL_TARGET_HT20_14] =
4375             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4376                                               is2GHz);
4377         targetPowerValT2[ALL_TARGET_HT20_15] =
4378             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4379                                               is2GHz);
4380         targetPowerValT2[ALL_TARGET_HT20_20] =
4381             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4382                                               is2GHz);
4383         targetPowerValT2[ALL_TARGET_HT20_21] =
4384             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4385                                               is2GHz);
4386         targetPowerValT2[ALL_TARGET_HT20_22] =
4387             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4388                                               is2GHz);
4389         targetPowerValT2[ALL_TARGET_HT20_23] =
4390             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4391                                               is2GHz);
4392 }
4393
4394 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4395                                                    u16 freq,
4396                                                    u8 *targetPowerValT2,
4397                                                    bool is2GHz)
4398 {
4399         /* XXX: hard code for now, need to get from eeprom struct */
4400         u8 ht40PowerIncForPdadc = 0;
4401
4402         targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4403             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4404                                               is2GHz) + ht40PowerIncForPdadc;
4405         targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4406             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4407                                               freq,
4408                                               is2GHz) + ht40PowerIncForPdadc;
4409         targetPowerValT2[ALL_TARGET_HT40_4] =
4410             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4411                                               is2GHz) + ht40PowerIncForPdadc;
4412         targetPowerValT2[ALL_TARGET_HT40_5] =
4413             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4414                                               is2GHz) + ht40PowerIncForPdadc;
4415         targetPowerValT2[ALL_TARGET_HT40_6] =
4416             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4417                                               is2GHz) + ht40PowerIncForPdadc;
4418         targetPowerValT2[ALL_TARGET_HT40_7] =
4419             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4420                                               is2GHz) + ht40PowerIncForPdadc;
4421         targetPowerValT2[ALL_TARGET_HT40_12] =
4422             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4423                                               is2GHz) + ht40PowerIncForPdadc;
4424         targetPowerValT2[ALL_TARGET_HT40_13] =
4425             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4426                                               is2GHz) + ht40PowerIncForPdadc;
4427         targetPowerValT2[ALL_TARGET_HT40_14] =
4428             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4429                                               is2GHz) + ht40PowerIncForPdadc;
4430         targetPowerValT2[ALL_TARGET_HT40_15] =
4431             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4432                                               is2GHz) + ht40PowerIncForPdadc;
4433         targetPowerValT2[ALL_TARGET_HT40_20] =
4434             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4435                                               is2GHz) + ht40PowerIncForPdadc;
4436         targetPowerValT2[ALL_TARGET_HT40_21] =
4437             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4438                                               is2GHz) + ht40PowerIncForPdadc;
4439         targetPowerValT2[ALL_TARGET_HT40_22] =
4440             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4441                                               is2GHz) + ht40PowerIncForPdadc;
4442         targetPowerValT2[ALL_TARGET_HT40_23] =
4443             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4444                                               is2GHz) + ht40PowerIncForPdadc;
4445 }
4446
4447 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4448                                               struct ath9k_channel *chan,
4449                                               u8 *targetPowerValT2)
4450 {
4451         bool is2GHz = IS_CHAN_2GHZ(chan);
4452         unsigned int i = 0;
4453         struct ath_common *common = ath9k_hw_common(ah);
4454         u16 freq = chan->channel;
4455
4456         if (is2GHz)
4457                 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4458
4459         ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4460         ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4461
4462         if (IS_CHAN_HT40(chan))
4463                 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4464                                                  is2GHz);
4465
4466         for (i = 0; i < ar9300RateSize; i++) {
4467                 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4468                         i, targetPowerValT2[i]);
4469         }
4470 }
4471
4472 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4473                                   int mode,
4474                                   int ipier,
4475                                   int ichain,
4476                                   int *pfrequency,
4477                                   int *pcorrection,
4478                                   int *ptemperature, int *pvoltage)
4479 {
4480         u8 *pCalPier;
4481         struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4482         int is2GHz;
4483         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4484         struct ath_common *common = ath9k_hw_common(ah);
4485
4486         if (ichain >= AR9300_MAX_CHAINS) {
4487                 ath_dbg(common, EEPROM,
4488                         "Invalid chain index, must be less than %d\n",
4489                         AR9300_MAX_CHAINS);
4490                 return -1;
4491         }
4492
4493         if (mode) {             /* 5GHz */
4494                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4495                         ath_dbg(common, EEPROM,
4496                                 "Invalid 5GHz cal pier index, must be less than %d\n",
4497                                 AR9300_NUM_5G_CAL_PIERS);
4498                         return -1;
4499                 }
4500                 pCalPier = &(eep->calFreqPier5G[ipier]);
4501                 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4502                 is2GHz = 0;
4503         } else {
4504                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4505                         ath_dbg(common, EEPROM,
4506                                 "Invalid 2GHz cal pier index, must be less than %d\n",
4507                                 AR9300_NUM_2G_CAL_PIERS);
4508                         return -1;
4509                 }
4510
4511                 pCalPier = &(eep->calFreqPier2G[ipier]);
4512                 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4513                 is2GHz = 1;
4514         }
4515
4516         *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz);
4517         *pcorrection = pCalPierStruct->refPower;
4518         *ptemperature = pCalPierStruct->tempMeas;
4519         *pvoltage = pCalPierStruct->voltMeas;
4520
4521         return 0;
4522 }
4523
4524 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4525                                             int frequency,
4526                                             int *correction,
4527                                             int *voltage, int *temperature)
4528 {
4529         int tempSlope = 0;
4530         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4531         int f[3], t[3];
4532
4533         REG_RMW(ah, AR_PHY_TPC_11_B0,
4534                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4535                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4536         if (ah->caps.tx_chainmask & BIT(1))
4537                 REG_RMW(ah, AR_PHY_TPC_11_B1,
4538                         (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4539                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4540         if (ah->caps.tx_chainmask & BIT(2))
4541                 REG_RMW(ah, AR_PHY_TPC_11_B2,
4542                         (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4543                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4544
4545         /* enable open loop power control on chip */
4546         REG_RMW(ah, AR_PHY_TPC_6_B0,
4547                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4548                 AR_PHY_TPC_6_ERROR_EST_MODE);
4549         if (ah->caps.tx_chainmask & BIT(1))
4550                 REG_RMW(ah, AR_PHY_TPC_6_B1,
4551                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4552                         AR_PHY_TPC_6_ERROR_EST_MODE);
4553         if (ah->caps.tx_chainmask & BIT(2))
4554                 REG_RMW(ah, AR_PHY_TPC_6_B2,
4555                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4556                         AR_PHY_TPC_6_ERROR_EST_MODE);
4557
4558         /*
4559          * enable temperature compensation
4560          * Need to use register names
4561          */
4562         if (frequency < 4000)
4563                 tempSlope = eep->modalHeader2G.tempSlope;
4564         else if (eep->base_ext2.tempSlopeLow != 0) {
4565                 t[0] = eep->base_ext2.tempSlopeLow;
4566                 f[0] = 5180;
4567                 t[1] = eep->modalHeader5G.tempSlope;
4568                 f[1] = 5500;
4569                 t[2] = eep->base_ext2.tempSlopeHigh;
4570                 f[2] = 5785;
4571                 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4572                                                         f, t, 3);
4573         } else
4574                 tempSlope = eep->modalHeader5G.tempSlope;
4575
4576         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4577
4578         if (AR_SREV_9462_20(ah))
4579                 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4580                               AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4581
4582
4583         REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4584                       temperature[0]);
4585
4586         return 0;
4587 }
4588
4589 /* Apply the recorded correction values. */
4590 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4591 {
4592         int ichain, ipier, npier;
4593         int mode;
4594         int lfrequency[AR9300_MAX_CHAINS],
4595             lcorrection[AR9300_MAX_CHAINS],
4596             ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4597         int hfrequency[AR9300_MAX_CHAINS],
4598             hcorrection[AR9300_MAX_CHAINS],
4599             htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4600         int fdiff;
4601         int correction[AR9300_MAX_CHAINS],
4602             voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4603         int pfrequency, pcorrection, ptemperature, pvoltage;
4604         struct ath_common *common = ath9k_hw_common(ah);
4605
4606         mode = (frequency >= 4000);
4607         if (mode)
4608                 npier = AR9300_NUM_5G_CAL_PIERS;
4609         else
4610                 npier = AR9300_NUM_2G_CAL_PIERS;
4611
4612         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4613                 lfrequency[ichain] = 0;
4614                 hfrequency[ichain] = 100000;
4615         }
4616         /* identify best lower and higher frequency calibration measurement */
4617         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4618                 for (ipier = 0; ipier < npier; ipier++) {
4619                         if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4620                                                     &pfrequency, &pcorrection,
4621                                                     &ptemperature, &pvoltage)) {
4622                                 fdiff = frequency - pfrequency;
4623
4624                                 /*
4625                                  * this measurement is higher than
4626                                  * our desired frequency
4627                                  */
4628                                 if (fdiff <= 0) {
4629                                         if (hfrequency[ichain] <= 0 ||
4630                                             hfrequency[ichain] >= 100000 ||
4631                                             fdiff >
4632                                             (frequency - hfrequency[ichain])) {
4633                                                 /*
4634                                                  * new best higher
4635                                                  * frequency measurement
4636                                                  */
4637                                                 hfrequency[ichain] = pfrequency;
4638                                                 hcorrection[ichain] =
4639                                                     pcorrection;
4640                                                 htemperature[ichain] =
4641                                                     ptemperature;
4642                                                 hvoltage[ichain] = pvoltage;
4643                                         }
4644                                 }
4645                                 if (fdiff >= 0) {
4646                                         if (lfrequency[ichain] <= 0
4647                                             || fdiff <
4648                                             (frequency - lfrequency[ichain])) {
4649                                                 /*
4650                                                  * new best lower
4651                                                  * frequency measurement
4652                                                  */
4653                                                 lfrequency[ichain] = pfrequency;
4654                                                 lcorrection[ichain] =
4655                                                     pcorrection;
4656                                                 ltemperature[ichain] =
4657                                                     ptemperature;
4658                                                 lvoltage[ichain] = pvoltage;
4659                                         }
4660                                 }
4661                         }
4662                 }
4663         }
4664
4665         /* interpolate  */
4666         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4667                 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
4668                         ichain, frequency, lfrequency[ichain],
4669                         lcorrection[ichain], hfrequency[ichain],
4670                         hcorrection[ichain]);
4671                 /* they're the same, so just pick one */
4672                 if (hfrequency[ichain] == lfrequency[ichain]) {
4673                         correction[ichain] = lcorrection[ichain];
4674                         voltage[ichain] = lvoltage[ichain];
4675                         temperature[ichain] = ltemperature[ichain];
4676                 }
4677                 /* the low frequency is good */
4678                 else if (frequency - lfrequency[ichain] < 1000) {
4679                         /* so is the high frequency, interpolate */
4680                         if (hfrequency[ichain] - frequency < 1000) {
4681
4682                                 correction[ichain] = interpolate(frequency,
4683                                                 lfrequency[ichain],
4684                                                 hfrequency[ichain],
4685                                                 lcorrection[ichain],
4686                                                 hcorrection[ichain]);
4687
4688                                 temperature[ichain] = interpolate(frequency,
4689                                                 lfrequency[ichain],
4690                                                 hfrequency[ichain],
4691                                                 ltemperature[ichain],
4692                                                 htemperature[ichain]);
4693
4694                                 voltage[ichain] = interpolate(frequency,
4695                                                 lfrequency[ichain],
4696                                                 hfrequency[ichain],
4697                                                 lvoltage[ichain],
4698                                                 hvoltage[ichain]);
4699                         }
4700                         /* only low is good, use it */
4701                         else {
4702                                 correction[ichain] = lcorrection[ichain];
4703                                 temperature[ichain] = ltemperature[ichain];
4704                                 voltage[ichain] = lvoltage[ichain];
4705                         }
4706                 }
4707                 /* only high is good, use it */
4708                 else if (hfrequency[ichain] - frequency < 1000) {
4709                         correction[ichain] = hcorrection[ichain];
4710                         temperature[ichain] = htemperature[ichain];
4711                         voltage[ichain] = hvoltage[ichain];
4712                 } else {        /* nothing is good, presume 0???? */
4713                         correction[ichain] = 0;
4714                         temperature[ichain] = 0;
4715                         voltage[ichain] = 0;
4716                 }
4717         }
4718
4719         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4720                                          temperature);
4721
4722         ath_dbg(common, EEPROM,
4723                 "for frequency=%d, calibration correction = %d %d %d\n",
4724                 frequency, correction[0], correction[1], correction[2]);
4725
4726         return 0;
4727 }
4728
4729 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4730                                            int idx,
4731                                            int edge,
4732                                            bool is2GHz)
4733 {
4734         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4735         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4736
4737         if (is2GHz)
4738                 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4739         else
4740                 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4741 }
4742
4743 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4744                                              int idx,
4745                                              unsigned int edge,
4746                                              u16 freq,
4747                                              bool is2GHz)
4748 {
4749         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4750         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4751
4752         u8 *ctl_freqbin = is2GHz ?
4753                 &eep->ctl_freqbin_2G[idx][0] :
4754                 &eep->ctl_freqbin_5G[idx][0];
4755
4756         if (is2GHz) {
4757                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4758                     CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4759                         return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4760         } else {
4761                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4762                     CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4763                         return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4764         }
4765
4766         return MAX_RATE_POWER;
4767 }
4768
4769 /*
4770  * Find the maximum conformance test limit for the given channel and CTL info
4771  */
4772 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4773                                         u16 freq, int idx, bool is2GHz)
4774 {
4775         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4776         u8 *ctl_freqbin = is2GHz ?
4777                 &eep->ctl_freqbin_2G[idx][0] :
4778                 &eep->ctl_freqbin_5G[idx][0];
4779         u16 num_edges = is2GHz ?
4780                 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4781         unsigned int edge;
4782
4783         /* Get the edge power */
4784         for (edge = 0;
4785              (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4786              edge++) {
4787                 /*
4788                  * If there's an exact channel match or an inband flag set
4789                  * on the lower channel use the given rdEdgePower
4790                  */
4791                 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4792                         twiceMaxEdgePower =
4793                                 ar9003_hw_get_direct_edge_power(eep, idx,
4794                                                                 edge, is2GHz);
4795                         break;
4796                 } else if ((edge > 0) &&
4797                            (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4798                                                       is2GHz))) {
4799                         twiceMaxEdgePower =
4800                                 ar9003_hw_get_indirect_edge_power(eep, idx,
4801                                                                   edge, freq,
4802                                                                   is2GHz);
4803                         /*
4804                          * Leave loop - no more affecting edges possible in
4805                          * this monotonic increasing list
4806                          */
4807                         break;
4808                 }
4809         }
4810         return twiceMaxEdgePower;
4811 }
4812
4813 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4814                                                struct ath9k_channel *chan,
4815                                                u8 *pPwrArray, u16 cfgCtl,
4816                                                u8 antenna_reduction,
4817                                                u16 powerLimit)
4818 {
4819         struct ath_common *common = ath9k_hw_common(ah);
4820         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4821         u16 twiceMaxEdgePower;
4822         int i;
4823         u16 scaledPower = 0, minCtlPower;
4824         static const u16 ctlModesFor11a[] = {
4825                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4826         };
4827         static const u16 ctlModesFor11g[] = {
4828                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4829                 CTL_11G_EXT, CTL_2GHT40
4830         };
4831         u16 numCtlModes;
4832         const u16 *pCtlMode;
4833         u16 ctlMode, freq;
4834         struct chan_centers centers;
4835         u8 *ctlIndex;
4836         u8 ctlNum;
4837         u16 twiceMinEdgePower;
4838         bool is2ghz = IS_CHAN_2GHZ(chan);
4839
4840         ath9k_hw_get_channel_centers(ah, chan, &centers);
4841         scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
4842                                                 antenna_reduction);
4843
4844         if (is2ghz) {
4845                 /* Setup for CTL modes */
4846                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4847                 numCtlModes =
4848                         ARRAY_SIZE(ctlModesFor11g) -
4849                                    SUB_NUM_CTL_MODES_AT_2G_40;
4850                 pCtlMode = ctlModesFor11g;
4851                 if (IS_CHAN_HT40(chan))
4852                         /* All 2G CTL's */
4853                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4854         } else {
4855                 /* Setup for CTL modes */
4856                 /* CTL_11A, CTL_5GHT20 */
4857                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4858                                          SUB_NUM_CTL_MODES_AT_5G_40;
4859                 pCtlMode = ctlModesFor11a;
4860                 if (IS_CHAN_HT40(chan))
4861                         /* All 5G CTL's */
4862                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4863         }
4864
4865         /*
4866          * For MIMO, need to apply regulatory caps individually across
4867          * dynamically running modes: CCK, OFDM, HT20, HT40
4868          *
4869          * The outer loop walks through each possible applicable runtime mode.
4870          * The inner loop walks through each ctlIndex entry in EEPROM.
4871          * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4872          */
4873         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4874                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4875                         (pCtlMode[ctlMode] == CTL_2GHT40);
4876                 if (isHt40CtlMode)
4877                         freq = centers.synth_center;
4878                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4879                         freq = centers.ext_center;
4880                 else
4881                         freq = centers.ctl_center;
4882
4883                 ath_dbg(common, REGULATORY,
4884                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4885                         ctlMode, numCtlModes, isHt40CtlMode,
4886                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
4887
4888                 /* walk through each CTL index stored in EEPROM */
4889                 if (is2ghz) {
4890                         ctlIndex = pEepData->ctlIndex_2G;
4891                         ctlNum = AR9300_NUM_CTLS_2G;
4892                 } else {
4893                         ctlIndex = pEepData->ctlIndex_5G;
4894                         ctlNum = AR9300_NUM_CTLS_5G;
4895                 }
4896
4897                 twiceMaxEdgePower = MAX_RATE_POWER;
4898                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4899                         ath_dbg(common, REGULATORY,
4900                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4901                                 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4902                                 chan->channel);
4903
4904                         /*
4905                          * compare test group from regulatory
4906                          * channel list with test mode from pCtlMode
4907                          * list
4908                          */
4909                         if ((((cfgCtl & ~CTL_MODE_M) |
4910                                (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4911                                 ctlIndex[i]) ||
4912                             (((cfgCtl & ~CTL_MODE_M) |
4913                                (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4914                              ((ctlIndex[i] & CTL_MODE_M) |
4915                                SD_NO_CTL))) {
4916                                 twiceMinEdgePower =
4917                                   ar9003_hw_get_max_edge_power(pEepData,
4918                                                                freq, i,
4919                                                                is2ghz);
4920
4921                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4922                                         /*
4923                                          * Find the minimum of all CTL
4924                                          * edge powers that apply to
4925                                          * this channel
4926                                          */
4927                                         twiceMaxEdgePower =
4928                                                 min(twiceMaxEdgePower,
4929                                                     twiceMinEdgePower);
4930                                 else {
4931                                         /* specific */
4932                                         twiceMaxEdgePower = twiceMinEdgePower;
4933                                         break;
4934                                 }
4935                         }
4936                 }
4937
4938                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4939
4940                 ath_dbg(common, REGULATORY,
4941                         "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4942                         ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4943                         scaledPower, minCtlPower);
4944
4945                 /* Apply ctl mode to correct target power set */
4946                 switch (pCtlMode[ctlMode]) {
4947                 case CTL_11B:
4948                         for (i = ALL_TARGET_LEGACY_1L_5L;
4949                              i <= ALL_TARGET_LEGACY_11S; i++)
4950                                 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
4951                                                        minCtlPower);
4952                         break;
4953                 case CTL_11A:
4954                 case CTL_11G:
4955                         for (i = ALL_TARGET_LEGACY_6_24;
4956                              i <= ALL_TARGET_LEGACY_54; i++)
4957                                 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
4958                                                        minCtlPower);
4959                         break;
4960                 case CTL_5GHT20:
4961                 case CTL_2GHT20:
4962                         for (i = ALL_TARGET_HT20_0_8_16;
4963                              i <= ALL_TARGET_HT20_23; i++)
4964                                 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
4965                                                        minCtlPower);
4966                         break;
4967                 case CTL_5GHT40:
4968                 case CTL_2GHT40:
4969                         for (i = ALL_TARGET_HT40_0_8_16;
4970                              i <= ALL_TARGET_HT40_23; i++)
4971                                 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
4972                                                        minCtlPower);
4973                         break;
4974                 default:
4975                         break;
4976                 }
4977         } /* end ctl mode checking */
4978 }
4979
4980 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4981 {
4982         u8 mod_idx = mcs_idx % 8;
4983
4984         if (mod_idx <= 3)
4985                 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4986         else
4987                 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4988 }
4989
4990 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4991                                         struct ath9k_channel *chan, u16 cfgCtl,
4992                                         u8 twiceAntennaReduction,
4993                                         u8 powerLimit, bool test)
4994 {
4995         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4996         struct ath_common *common = ath9k_hw_common(ah);
4997         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4998         struct ar9300_modal_eep_header *modal_hdr;
4999         u8 targetPowerValT2[ar9300RateSize];
5000         u8 target_power_val_t2_eep[ar9300RateSize];
5001         unsigned int i = 0, paprd_scale_factor = 0;
5002         u8 pwr_idx, min_pwridx = 0;
5003
5004         memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
5005
5006         /*
5007          * Get target powers from EEPROM - our baseline for TX Power
5008          */
5009         ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
5010
5011         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5012                 if (IS_CHAN_2GHZ(chan))
5013                         modal_hdr = &eep->modalHeader2G;
5014                 else
5015                         modal_hdr = &eep->modalHeader5G;
5016
5017                 ah->paprd_ratemask =
5018                         le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5019                         AR9300_PAPRD_RATE_MASK;
5020
5021                 ah->paprd_ratemask_ht40 =
5022                         le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5023                         AR9300_PAPRD_RATE_MASK;
5024
5025                 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5026                 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5027                                                   ALL_TARGET_HT20_0_8_16;
5028
5029                 if (!ah->paprd_table_write_done) {
5030                         memcpy(target_power_val_t2_eep, targetPowerValT2,
5031                                sizeof(targetPowerValT2));
5032                         for (i = 0; i < 24; i++) {
5033                                 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5034                                 if (ah->paprd_ratemask & (1 << i)) {
5035                                         if (targetPowerValT2[pwr_idx] &&
5036                                             targetPowerValT2[pwr_idx] ==
5037                                             target_power_val_t2_eep[pwr_idx])
5038                                                 targetPowerValT2[pwr_idx] -=
5039                                                         paprd_scale_factor;
5040                                 }
5041                         }
5042                 }
5043                 memcpy(target_power_val_t2_eep, targetPowerValT2,
5044                        sizeof(targetPowerValT2));
5045         }
5046
5047         ar9003_hw_set_power_per_rate_table(ah, chan,
5048                                            targetPowerValT2, cfgCtl,
5049                                            twiceAntennaReduction,
5050                                            powerLimit);
5051
5052         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5053                 for (i = 0; i < ar9300RateSize; i++) {
5054                         if ((ah->paprd_ratemask & (1 << i)) &&
5055                             (abs(targetPowerValT2[i] -
5056                                 target_power_val_t2_eep[i]) >
5057                             paprd_scale_factor)) {
5058                                 ah->paprd_ratemask &= ~(1 << i);
5059                                 ath_dbg(common, EEPROM,
5060                                         "paprd disabled for mcs %d\n", i);
5061                         }
5062                 }
5063         }
5064
5065         regulatory->max_power_level = 0;
5066         for (i = 0; i < ar9300RateSize; i++) {
5067                 if (targetPowerValT2[i] > regulatory->max_power_level)
5068                         regulatory->max_power_level = targetPowerValT2[i];
5069         }
5070
5071         ath9k_hw_update_regulatory_maxpower(ah);
5072
5073         if (test)
5074                 return;
5075
5076         for (i = 0; i < ar9300RateSize; i++) {
5077                 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5078                         i, targetPowerValT2[i]);
5079         }
5080
5081         /* Write target power array to registers */
5082         ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5083         ar9003_hw_calibration_apply(ah, chan->channel);
5084
5085         if (IS_CHAN_2GHZ(chan)) {
5086                 if (IS_CHAN_HT40(chan))
5087                         i = ALL_TARGET_HT40_0_8_16;
5088                 else
5089                         i = ALL_TARGET_HT20_0_8_16;
5090         } else {
5091                 if (IS_CHAN_HT40(chan))
5092                         i = ALL_TARGET_HT40_7;
5093                 else
5094                         i = ALL_TARGET_HT20_7;
5095         }
5096         ah->paprd_target_power = targetPowerValT2[i];
5097 }
5098
5099 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5100                                             u16 i, bool is2GHz)
5101 {
5102         return AR_NO_SPUR;
5103 }
5104
5105 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5106 {
5107         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5108
5109         return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5110 }
5111
5112 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5113 {
5114         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5115
5116         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5117 }
5118
5119 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
5120 {
5121         return ar9003_modal_header(ah, is2ghz)->spurChans;
5122 }
5123
5124 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5125                                            struct ath9k_channel *chan)
5126 {
5127         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5128
5129         if (IS_CHAN_2GHZ(chan))
5130                 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5131                           AR9300_PAPRD_SCALE_1);
5132         else {
5133                 if (chan->channel >= 5700)
5134                 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5135                           AR9300_PAPRD_SCALE_1);
5136                 else if (chan->channel >= 5400)
5137                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5138                                    AR9300_PAPRD_SCALE_2);
5139                 else
5140                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5141                                   AR9300_PAPRD_SCALE_1);
5142         }
5143 }
5144
5145 const struct eeprom_ops eep_ar9300_ops = {
5146         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5147         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5148         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5149         .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5150         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5151         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5152         .set_board_values = ath9k_hw_ar9300_set_board_values,
5153         .set_addac = ath9k_hw_ar9300_set_addac,
5154         .set_txpower = ath9k_hw_ar9300_set_txpower,
5155         .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5156 };