drivers/net/wireless/ath/ath9k/ar9003_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_mac.h"
  19 #include "ar9003_2p2_initvals.h"
  20 #include "ar9485_initvals.h"
  21 #include "ar9340_initvals.h"
  22 #include "ar9330_1p1_initvals.h"
  23 #include "ar9330_1p2_initvals.h"
  24 #include "ar955x_1p0_initvals.h"
  25 #include "ar9580_1p0_initvals.h"
  26 #include "ar9462_2p0_initvals.h"
  27 #include "ar9462_2p1_initvals.h"
  28 #include "ar9565_1p0_initvals.h"
  29 #include "ar9565_1p1_initvals.h"
  30
  31 /* General hardware code for the AR9003 hadware family */
  32
  33 /*
  34  * The AR9003 family uses a new INI format (pre, core, post
  35  * arrays per subsystem). This provides support for the
  36  * AR9003 2.2 chipsets.
  37  */
  38 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
  39 {
  40         if (AR_SREV_9330_11(ah)) {
  41                 /* mac */
  42                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  43                                 ar9331_1p1_mac_core);
  44                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  45                                 ar9331_1p1_mac_postamble);
  46
  47                 /* bb */
  48                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  49                                 ar9331_1p1_baseband_core);
  50                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  51                                 ar9331_1p1_baseband_postamble);
  52
  53                 /* radio */
  54                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  55                                 ar9331_1p1_radio_core);
  56
  57                 /* soc */
  58                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  59                                 ar9331_1p1_soc_preamble);
  60                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  61                                 ar9331_1p1_soc_postamble);
  62
  63                 /* rx/tx gain */
  64                 INIT_INI_ARRAY(&ah->iniModesRxGain,
  65                                 ar9331_common_rx_gain_1p1);
  66                 INIT_INI_ARRAY(&ah->iniModesTxGain,
  67                                 ar9331_modes_lowest_ob_db_tx_gain_1p1);
  68
  69                 /* Japan 2484 Mhz CCK */
  70                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  71                                ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
  72
  73                 /* additional clock settings */
  74                 if (ah->is_clk_25mhz)
  75                         INIT_INI_ARRAY(&ah->iniAdditional,
  76                                         ar9331_1p1_xtal_25M);
  77                 else
  78                         INIT_INI_ARRAY(&ah->iniAdditional,
  79                                         ar9331_1p1_xtal_40M);
  80         } else if (AR_SREV_9330_12(ah)) {
  81                 /* mac */
  82                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  83                                 ar9331_1p2_mac_core);
  84                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  85                                 ar9331_1p2_mac_postamble);
  86
  87                 /* bb */
  88                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  89                                 ar9331_1p2_baseband_core);
  90                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  91                                 ar9331_1p2_baseband_postamble);
  92
  93                 /* radio */
  94                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  95                                 ar9331_1p2_radio_core);
  96
  97                 /* soc */
  98                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  99                                 ar9331_1p2_soc_preamble);
 100                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 101                                 ar9331_1p2_soc_postamble);
 102
 103                 /* rx/tx gain */
 104                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 105                                 ar9331_common_rx_gain_1p2);
 106                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 107                                 ar9331_modes_lowest_ob_db_tx_gain_1p2);
 108
 109                 /* Japan 2484 Mhz CCK */
 110                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 111                                ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
 112
 113                 /* additional clock settings */
 114                 if (ah->is_clk_25mhz)
 115                         INIT_INI_ARRAY(&ah->iniAdditional,
 116                                         ar9331_1p2_xtal_25M);
 117                 else
 118                         INIT_INI_ARRAY(&ah->iniAdditional,
 119                                         ar9331_1p2_xtal_40M);
 120         } else if (AR_SREV_9340(ah)) {
 121                 /* mac */
 122                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 123                                 ar9340_1p0_mac_core);
 124                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 125                                 ar9340_1p0_mac_postamble);
 126
 127                 /* bb */
 128                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 129                                 ar9340_1p0_baseband_core);
 130                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 131                                 ar9340_1p0_baseband_postamble);
 132
 133                 /* radio */
 134                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 135                                 ar9340_1p0_radio_core);
 136                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 137                                 ar9340_1p0_radio_postamble);
 138
 139                 /* soc */
 140                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 141                                 ar9340_1p0_soc_preamble);
 142                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 143                                 ar9340_1p0_soc_postamble);
 144
 145                 /* rx/tx gain */
 146                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 147                                 ar9340Common_wo_xlna_rx_gain_table_1p0);
 148                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 149                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
 150
 151                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 152                                ar9340Modes_fast_clock_1p0);
 153                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 154                                ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
 155
 156                 if (!ah->is_clk_25mhz)
 157                         INIT_INI_ARRAY(&ah->iniAdditional,
 158                                        ar9340_1p0_radio_core_40M);
 159         } else if (AR_SREV_9485_11_OR_LATER(ah)) {
 160                 /* mac */
 161                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 162                                 ar9485_1_1_mac_core);
 163                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 164                                 ar9485_1_1_mac_postamble);
 165
 166                 /* bb */
 167                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
 168                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 169                                 ar9485_1_1_baseband_core);
 170                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 171                                 ar9485_1_1_baseband_postamble);
 172
 173                 /* radio */
 174                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 175                                 ar9485_1_1_radio_core);
 176                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 177                                 ar9485_1_1_radio_postamble);
 178
 179                 /* soc */
 180                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 181                                 ar9485_1_1_soc_preamble);
 182
 183                 /* rx/tx gain */
 184                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 185                                 ar9485Common_wo_xlna_rx_gain_1_1);
 186                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 187                                 ar9485_modes_lowest_ob_db_tx_gain_1_1);
 188
 189                 /* Japan 2484 Mhz CCK */
 190                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 191                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
 192
 193                 if (ah->config.no_pll_pwrsave) {
 194                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 195                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 196                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 197                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 198                 } else {
 199                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 200                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 201                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 202                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 203                 }
 204         } else if (AR_SREV_9462_21(ah)) {
 205                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 206                                ar9462_2p1_mac_core);
 207                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 208                                ar9462_2p1_mac_postamble);
 209                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 210                                ar9462_2p1_baseband_core);
 211                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 212                                ar9462_2p1_baseband_postamble);
 213                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 214                                ar9462_2p1_radio_core);
 215                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 216                                ar9462_2p1_radio_postamble);
 217                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 218                                ar9462_2p1_radio_postamble_sys2ant);
 219                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 220                                ar9462_2p1_soc_preamble);
 221                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 222                                ar9462_2p1_soc_postamble);
 223                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 224                                ar9462_2p1_common_rx_gain);
 225                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 226                                ar9462_2p1_modes_fast_clock);
 227                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 228                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
 229                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 230                                ar9462_2p1_pciephy_clkreq_disable_L1);
 231                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 232                                ar9462_2p1_pciephy_clkreq_disable_L1);
 233         } else if (AR_SREV_9462_20(ah)) {
 234
 235                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
 236                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 237                                 ar9462_2p0_mac_postamble);
 238
 239                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 240                                 ar9462_2p0_baseband_core);
 241                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 242                                 ar9462_2p0_baseband_postamble);
 243
 244                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 245                                 ar9462_2p0_radio_core);
 246                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 247                                 ar9462_2p0_radio_postamble);
 248                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 249                                 ar9462_2p0_radio_postamble_sys2ant);
 250
 251                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 252                                 ar9462_2p0_soc_preamble);
 253                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 254                                 ar9462_2p0_soc_postamble);
 255
 256                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 257                                 ar9462_2p0_common_rx_gain);
 258
 259                 /* Awake -> Sleep Setting */
 260                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 261                                ar9462_2p0_pciephy_clkreq_disable_L1);
 262                 /* Sleep -> Awake Setting */
 263                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 264                                ar9462_2p0_pciephy_clkreq_disable_L1);
 265
 266                 /* Fast clock modal settings */
 267                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 268                                 ar9462_2p0_modes_fast_clock);
 269
 270                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 271                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
 272         } else if (AR_SREV_9550(ah)) {
 273                 /* mac */
 274                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 275                                 ar955x_1p0_mac_core);
 276                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 277                                 ar955x_1p0_mac_postamble);
 278
 279                 /* bb */
 280                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 281                                 ar955x_1p0_baseband_core);
 282                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 283                                 ar955x_1p0_baseband_postamble);
 284
 285                 /* radio */
 286                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 287                                 ar955x_1p0_radio_core);
 288                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 289                                 ar955x_1p0_radio_postamble);
 290
 291                 /* soc */
 292                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 293                                 ar955x_1p0_soc_preamble);
 294                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 295                                 ar955x_1p0_soc_postamble);
 296
 297                 /* rx/tx gain */
 298                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 299                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 300                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 301                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 302                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 303                                 ar955x_1p0_modes_xpa_tx_gain_table);
 304
 305                 /* Fast clock modal settings */
 306                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 307                                 ar955x_1p0_modes_fast_clock);
 308         } else if (AR_SREV_9580(ah)) {
 309                 /* mac */
 310                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 311                                 ar9580_1p0_mac_core);
 312                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 313                                 ar9580_1p0_mac_postamble);
 314
 315                 /* bb */
 316                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 317                                 ar9580_1p0_baseband_core);
 318                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 319                                 ar9580_1p0_baseband_postamble);
 320
 321                 /* radio */
 322                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 323                                 ar9580_1p0_radio_core);
 324                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 325                                 ar9580_1p0_radio_postamble);
 326
 327                 /* soc */
 328                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 329                                 ar9580_1p0_soc_preamble);
 330                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 331                                 ar9580_1p0_soc_postamble);
 332
 333                 /* rx/tx gain */
 334                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 335                                 ar9580_1p0_rx_gain_table);
 336                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 337                                 ar9580_1p0_low_ob_db_tx_gain_table);
 338
 339                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 340                                ar9580_1p0_modes_fast_clock);
 341                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 342                                ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
 343         } else if (AR_SREV_9565_11_OR_LATER(ah)) {
 344                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 345                                ar9565_1p1_mac_core);
 346                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 347                                ar9565_1p1_mac_postamble);
 348
 349                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 350                                ar9565_1p1_baseband_core);
 351                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 352                                ar9565_1p1_baseband_postamble);
 353
 354                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 355                                ar9565_1p1_radio_core);
 356                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 357                                ar9565_1p1_radio_postamble);
 358
 359                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 360                                ar9565_1p1_soc_preamble);
 361                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 362                                ar9565_1p1_soc_postamble);
 363
 364                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 365                                ar9565_1p1_Common_rx_gain_table);
 366                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 367                                ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
 368
 369                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 370                                ar9565_1p1_pciephy_clkreq_disable_L1);
 371                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 372                                ar9565_1p1_pciephy_clkreq_disable_L1);
 373
 374                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 375                                 ar9565_1p1_modes_fast_clock);
 376                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 377                                ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
 378         } else if (AR_SREV_9565(ah)) {
 379                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 380                                ar9565_1p0_mac_core);
 381                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 382                                ar9565_1p0_mac_postamble);
 383
 384                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 385                                ar9565_1p0_baseband_core);
 386                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 387                                ar9565_1p0_baseband_postamble);
 388
 389                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 390                                ar9565_1p0_radio_core);
 391                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 392                                ar9565_1p0_radio_postamble);
 393
 394                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 395                                ar9565_1p0_soc_preamble);
 396                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 397                                ar9565_1p0_soc_postamble);
 398
 399                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 400                                ar9565_1p0_Common_rx_gain_table);
 401                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 402                                ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
 403
 404                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 405                                ar9565_1p0_pciephy_clkreq_disable_L1);
 406                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 407                                ar9565_1p0_pciephy_clkreq_disable_L1);
 408
 409                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 410                                 ar9565_1p0_modes_fast_clock);
 411                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 412                                ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
 413         } else {
 414                 /* mac */
 415                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 416                                 ar9300_2p2_mac_core);
 417                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 418                                 ar9300_2p2_mac_postamble);
 419
 420                 /* bb */
 421                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 422                                 ar9300_2p2_baseband_core);
 423                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 424                                 ar9300_2p2_baseband_postamble);
 425
 426                 /* radio */
 427                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 428                                 ar9300_2p2_radio_core);
 429                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 430                                 ar9300_2p2_radio_postamble);
 431
 432                 /* soc */
 433                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 434                                 ar9300_2p2_soc_preamble);
 435                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 436                                 ar9300_2p2_soc_postamble);
 437
 438                 /* rx/tx gain */
 439                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 440                                 ar9300Common_rx_gain_table_2p2);
 441                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 442                                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 443
 444                 /* Load PCIE SERDES settings from INI */
 445
 446                 /* Awake Setting */
 447
 448                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 449                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 450
 451                 /* Sleep Setting */
 452
 453                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 454                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 455
 456                 /* Fast clock modal settings */
 457                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 458                                ar9300Modes_fast_clock_2p2);
 459                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 460                                ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
 461         }
 462 }
 463
 464 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
 465 {
 466         if (AR_SREV_9330_12(ah))
 467                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 468                         ar9331_modes_lowest_ob_db_tx_gain_1p2);
 469         else if (AR_SREV_9330_11(ah))
 470                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 471                         ar9331_modes_lowest_ob_db_tx_gain_1p1);
 472         else if (AR_SREV_9340(ah))
 473                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 474                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
 475         else if (AR_SREV_9485_11_OR_LATER(ah))
 476                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 477                         ar9485_modes_lowest_ob_db_tx_gain_1_1);
 478         else if (AR_SREV_9550(ah))
 479                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 480                         ar955x_1p0_modes_xpa_tx_gain_table);
 481         else if (AR_SREV_9580(ah))
 482                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 483                         ar9580_1p0_lowest_ob_db_tx_gain_table);
 484         else if (AR_SREV_9462_21(ah))
 485                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 486                         ar9462_2p1_modes_low_ob_db_tx_gain);
 487         else if (AR_SREV_9462_20(ah))
 488                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 489                         ar9462_2p0_modes_low_ob_db_tx_gain);
 490         else if (AR_SREV_9565_11(ah))
 491                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 492                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 493         else if (AR_SREV_9565(ah))
 494                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 495                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 496         else
 497                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 498                         ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 499 }
 500
 501 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 502 {
 503         if (AR_SREV_9330_12(ah))
 504                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 505                         ar9331_modes_high_ob_db_tx_gain_1p2);
 506         else if (AR_SREV_9330_11(ah))
 507                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 508                         ar9331_modes_high_ob_db_tx_gain_1p1);
 509         else if (AR_SREV_9340(ah))
 510                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 511                         ar9340Modes_high_ob_db_tx_gain_table_1p0);
 512         else if (AR_SREV_9485_11_OR_LATER(ah))
 513                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 514                         ar9485Modes_high_ob_db_tx_gain_1_1);
 515         else if (AR_SREV_9580(ah))
 516                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 517                         ar9580_1p0_high_ob_db_tx_gain_table);
 518         else if (AR_SREV_9550(ah))
 519                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 520                         ar955x_1p0_modes_no_xpa_tx_gain_table);
 521         else if (AR_SREV_9462_21(ah))
 522                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 523                         ar9462_2p1_modes_high_ob_db_tx_gain);
 524         else if (AR_SREV_9462_20(ah))
 525                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 526                         ar9462_2p0_modes_high_ob_db_tx_gain);
 527         else if (AR_SREV_9565_11(ah))
 528                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 529                                ar9565_1p1_modes_high_ob_db_tx_gain_table);
 530         else if (AR_SREV_9565(ah))
 531                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 532                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
 533         else
 534                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 535                         ar9300Modes_high_ob_db_tx_gain_table_2p2);
 536 }
 537
 538 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 539 {
 540         if (AR_SREV_9330_12(ah))
 541                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 542                         ar9331_modes_low_ob_db_tx_gain_1p2);
 543         else if (AR_SREV_9330_11(ah))
 544                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 545                         ar9331_modes_low_ob_db_tx_gain_1p1);
 546         else if (AR_SREV_9340(ah))
 547                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 548                         ar9340Modes_low_ob_db_tx_gain_table_1p0);
 549         else if (AR_SREV_9485_11_OR_LATER(ah))
 550                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 551                         ar9485Modes_low_ob_db_tx_gain_1_1);
 552         else if (AR_SREV_9580(ah))
 553                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 554                         ar9580_1p0_low_ob_db_tx_gain_table);
 555         else if (AR_SREV_9565_11(ah))
 556                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 557                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 558         else if (AR_SREV_9565(ah))
 559                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 560                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 561         else
 562                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 563                         ar9300Modes_low_ob_db_tx_gain_table_2p2);
 564 }
 565
 566 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 567 {
 568         if (AR_SREV_9330_12(ah))
 569                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 570                         ar9331_modes_high_power_tx_gain_1p2);
 571         else if (AR_SREV_9330_11(ah))
 572                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 573                         ar9331_modes_high_power_tx_gain_1p1);
 574         else if (AR_SREV_9340(ah))
 575                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 576                         ar9340Modes_high_power_tx_gain_table_1p0);
 577         else if (AR_SREV_9485_11_OR_LATER(ah))
 578                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 579                         ar9485Modes_high_power_tx_gain_1_1);
 580         else if (AR_SREV_9580(ah))
 581                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 582                         ar9580_1p0_high_power_tx_gain_table);
 583         else if (AR_SREV_9565_11(ah))
 584                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 585                                ar9565_1p1_modes_high_power_tx_gain_table);
 586         else if (AR_SREV_9565(ah))
 587                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 588                                ar9565_1p0_modes_high_power_tx_gain_table);
 589         else
 590                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 591                         ar9300Modes_high_power_tx_gain_table_2p2);
 592 }
 593
 594 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
 595 {
 596         if (AR_SREV_9340(ah))
 597                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 598                         ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
 599         else if (AR_SREV_9580(ah))
 600                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 601                         ar9580_1p0_mixed_ob_db_tx_gain_table);
 602         else if (AR_SREV_9462_21(ah))
 603                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 604                        ar9462_2p1_modes_mix_ob_db_tx_gain);
 605         else if (AR_SREV_9462_20(ah))
 606                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 607                        ar9462_2p0_modes_mix_ob_db_tx_gain);
 608         else
 609                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 610                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
 611 }
 612
 613 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
 614 {
 615         if (AR_SREV_9485_11_OR_LATER(ah))
 616                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 617                         ar9485Modes_green_ob_db_tx_gain_1_1);
 618         else if (AR_SREV_9340(ah))
 619                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 620                         ar9340Modes_ub124_tx_gain_table_1p0);
 621         else if (AR_SREV_9580(ah))
 622                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 623                         ar9580_1p0_type5_tx_gain_table);
 624         else if (AR_SREV_9300_22(ah))
 625                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 626                         ar9300Modes_type5_tx_gain_table_2p2);
 627 }
 628
 629 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
 630 {
 631         if (AR_SREV_9340(ah))
 632                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 633                         ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
 634         else if (AR_SREV_9485_11_OR_LATER(ah))
 635                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 636                         ar9485Modes_green_spur_ob_db_tx_gain_1_1);
 637         else if (AR_SREV_9580(ah))
 638                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 639                         ar9580_1p0_type6_tx_gain_table);
 640 }
 641
 642 static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
 643 {
 644         if (AR_SREV_9340(ah))
 645                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 646                                ar9340_cus227_tx_gain_table_1p0);
 647 }
 648
 649 typedef void (*ath_txgain_tab)(struct ath_hw *ah);
 650
 651 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 652 {
 653         static const ath_txgain_tab modes[] = {
 654                 ar9003_tx_gain_table_mode0,
 655                 ar9003_tx_gain_table_mode1,
 656                 ar9003_tx_gain_table_mode2,
 657                 ar9003_tx_gain_table_mode3,
 658                 ar9003_tx_gain_table_mode4,
 659                 ar9003_tx_gain_table_mode5,
 660                 ar9003_tx_gain_table_mode6,
 661                 ar9003_tx_gain_table_mode7,
 662         };
 663         int idx = ar9003_hw_get_tx_gain_idx(ah);
 664
 665         if (idx >= ARRAY_SIZE(modes))
 666                 idx = 0;
 667
 668         modes[idx](ah);
 669 }
 670
 671 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
 672 {
 673         if (AR_SREV_9330_12(ah))
 674                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 675                                 ar9331_common_rx_gain_1p2);
 676         else if (AR_SREV_9330_11(ah))
 677                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 678                                 ar9331_common_rx_gain_1p1);
 679         else if (AR_SREV_9340(ah))
 680                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 681                                 ar9340Common_rx_gain_table_1p0);
 682         else if (AR_SREV_9485_11_OR_LATER(ah))
 683                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 684                                ar9485_common_rx_gain_1_1);
 685         else if (AR_SREV_9550(ah)) {
 686                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 687                                 ar955x_1p0_common_rx_gain_table);
 688                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 689                                 ar955x_1p0_common_rx_gain_bounds);
 690         } else if (AR_SREV_9580(ah))
 691                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 692                                 ar9580_1p0_rx_gain_table);
 693         else if (AR_SREV_9462_21(ah))
 694                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 695                                 ar9462_2p1_common_rx_gain);
 696         else if (AR_SREV_9462_20(ah))
 697                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 698                                 ar9462_2p0_common_rx_gain);
 699         else if (AR_SREV_9565_11(ah))
 700                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 701                                ar9565_1p1_Common_rx_gain_table);
 702         else if (AR_SREV_9565(ah))
 703                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 704                                ar9565_1p0_Common_rx_gain_table);
 705         else
 706                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 707                                 ar9300Common_rx_gain_table_2p2);
 708 }
 709
 710 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
 711 {
 712         if (AR_SREV_9330_12(ah))
 713                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 714                         ar9331_common_wo_xlna_rx_gain_1p2);
 715         else if (AR_SREV_9330_11(ah))
 716                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 717                         ar9331_common_wo_xlna_rx_gain_1p1);
 718         else if (AR_SREV_9340(ah))
 719                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 720                         ar9340Common_wo_xlna_rx_gain_table_1p0);
 721         else if (AR_SREV_9485_11_OR_LATER(ah))
 722                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 723                         ar9485Common_wo_xlna_rx_gain_1_1);
 724         else if (AR_SREV_9462_21(ah))
 725                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 726                         ar9462_2p1_common_wo_xlna_rx_gain);
 727         else if (AR_SREV_9462_20(ah))
 728                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 729                         ar9462_2p0_common_wo_xlna_rx_gain);
 730         else if (AR_SREV_9550(ah)) {
 731                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 732                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 733                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 734                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 735         } else if (AR_SREV_9580(ah))
 736                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 737                         ar9580_1p0_wo_xlna_rx_gain_table);
 738         else if (AR_SREV_9565_11(ah))
 739                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 740                                ar9565_1p1_common_wo_xlna_rx_gain_table);
 741         else if (AR_SREV_9565(ah))
 742                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 743                                ar9565_1p0_common_wo_xlna_rx_gain_table);
 744         else
 745                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 746                         ar9300Common_wo_xlna_rx_gain_table_2p2);
 747 }
 748
 749 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
 750 {
 751         if (AR_SREV_9462_21(ah)) {
 752                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 753                                ar9462_2p1_common_mixed_rx_gain);
 754                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 755                                ar9462_2p1_baseband_core_mix_rxgain);
 756                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 757                                ar9462_2p1_baseband_postamble_mix_rxgain);
 758                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 759                                ar9462_2p1_baseband_postamble_5g_xlna);
 760         } else if (AR_SREV_9462_20(ah)) {
 761                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 762                                ar9462_2p0_common_mixed_rx_gain);
 763                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 764                                ar9462_2p0_baseband_core_mix_rxgain);
 765                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 766                                ar9462_2p0_baseband_postamble_mix_rxgain);
 767                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 768                                ar9462_2p0_baseband_postamble_5g_xlna);
 769         }
 770 }
 771
 772 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)
 773 {
 774         if (AR_SREV_9462_21(ah)) {
 775                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 776                                ar9462_2p1_common_5g_xlna_only_rxgain);
 777                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 778                                ar9462_2p1_baseband_postamble_5g_xlna);
 779         } else if (AR_SREV_9462_20(ah)) {
 780                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 781                                ar9462_2p0_common_5g_xlna_only_rxgain);
 782                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 783                                ar9462_2p0_baseband_postamble_5g_xlna);
 784         }
 785 }
 786
 787 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 788 {
 789         switch (ar9003_hw_get_rx_gain_idx(ah)) {
 790         case 0:
 791         default:
 792                 ar9003_rx_gain_table_mode0(ah);
 793                 break;
 794         case 1:
 795                 ar9003_rx_gain_table_mode1(ah);
 796                 break;
 797         case 2:
 798                 ar9003_rx_gain_table_mode2(ah);
 799                 break;
 800         case 3:
 801                 ar9003_rx_gain_table_mode3(ah);
 802                 break;
 803         }
 804 }
 805
 806 /* set gain table pointers according to values read from the eeprom */
 807 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
 808 {
 809         ar9003_tx_gain_table_apply(ah);
 810         ar9003_rx_gain_table_apply(ah);
 811 }
 812
 813 /*
 814  * Helper for ASPM support.
 815  *
 816  * Disable PLL when in L0s as well as receiver clock when in L1.
 817  * This power saving option must be enabled through the SerDes.
 818  *
 819  * Programming the SerDes must go through the same 288 bit serial shift
 820  * register as the other analog registers.  Hence the 9 writes.
 821  */
 822 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 823                                          bool power_off)
 824 {
 825         unsigned int i;
 826         struct ar5416IniArray *array;
 827
 828         /*
 829          * Increase L1 Entry Latency. Some WB222 boards don't have
 830          * this change in eeprom/OTP.
 831          *
 832          */
 833         if (AR_SREV_9462(ah)) {
 834                 u32 val = ah->config.aspm_l1_fix;
 835                 if ((val & 0xff000000) == 0x17000000) {
 836                         val &= 0x00ffffff;
 837                         val |= 0x27000000;
 838                         REG_WRITE(ah, 0x570c, val);
 839                 }
 840         }
 841
 842         /* Nothing to do on restore for 11N */
 843         if (!power_off /* !restore */) {
 844                 /* set bit 19 to allow forcing of pcie core into L1 state */
 845                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 846                 REG_WRITE(ah, AR_WA, ah->WARegVal);
 847         }
 848
 849         /*
 850          * Configire PCIE after Ini init. SERDES values now come from ini file
 851          * This enables PCIe low power mode.
 852          */
 853         array = power_off ? &ah->iniPcieSerdes :
 854                 &ah->iniPcieSerdesLowPower;
 855
 856         for (i = 0; i < array->ia_rows; i++) {
 857                 REG_WRITE(ah,
 858                           INI_RA(array, i, 0),
 859                           INI_RA(array, i, 1));
 860         }
 861 }
 862
 863 /* Sets up the AR9003 hardware familiy callbacks */
 864 void ar9003_hw_attach_ops(struct ath_hw *ah)
 865 {
 866         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 867         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 868
 869         ar9003_hw_init_mode_regs(ah);
 870         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
 871
 872         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
 873
 874         ar9003_hw_attach_phy_ops(ah);
 875         ar9003_hw_attach_calib_ops(ah);
 876         ar9003_hw_attach_mac_ops(ah);
 877 }