2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/time.h>
21 #include <asm/unaligned.h>
26 #include "ar9003_mac.h"
27 #include "ar9003_mci.h"
28 #include "ar9003_phy.h"
32 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
39 static int __init ath9k_init(void)
43 module_init(ath9k_init);
45 static void __exit ath9k_exit(void)
49 module_exit(ath9k_exit);
51 /* Private hardware callbacks */
53 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
55 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
58 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
59 struct ath9k_channel *chan)
61 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
64 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
66 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
69 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
72 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
74 /* You will not have this callback if using the old ANI */
75 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
78 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
81 /********************/
82 /* Helper Functions */
83 /********************/
85 #ifdef CONFIG_ATH9K_DEBUGFS
87 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
89 struct ath_softc *sc = common->priv;
91 sc->debug.stats.istats.sync_cause_all++;
92 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
93 sc->debug.stats.istats.sync_rtc_irq++;
94 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
95 sc->debug.stats.istats.sync_mac_irq++;
96 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
97 sc->debug.stats.istats.eeprom_illegal_access++;
98 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
99 sc->debug.stats.istats.apb_timeout++;
100 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
101 sc->debug.stats.istats.pci_mode_conflict++;
102 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
103 sc->debug.stats.istats.host1_fatal++;
104 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
105 sc->debug.stats.istats.host1_perr++;
106 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
107 sc->debug.stats.istats.trcv_fifo_perr++;
108 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
109 sc->debug.stats.istats.radm_cpl_ep++;
110 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
111 sc->debug.stats.istats.radm_cpl_dllp_abort++;
112 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
113 sc->debug.stats.istats.radm_cpl_tlp_abort++;
114 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
115 sc->debug.stats.istats.radm_cpl_ecrc_err++;
116 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
117 sc->debug.stats.istats.radm_cpl_timeout++;
118 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
119 sc->debug.stats.istats.local_timeout++;
120 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
121 sc->debug.stats.istats.pm_access++;
122 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
123 sc->debug.stats.istats.mac_awake++;
124 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
125 sc->debug.stats.istats.mac_asleep++;
126 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
127 sc->debug.stats.istats.mac_sleep_access++;
132 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
134 struct ath_common *common = ath9k_hw_common(ah);
135 struct ath9k_channel *chan = ah->curchan;
136 unsigned int clockrate;
138 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
139 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
141 else if (!chan) /* should really check for CCK instead */
142 clockrate = ATH9K_CLOCK_RATE_CCK;
143 else if (IS_CHAN_2GHZ(chan))
144 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
145 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
146 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
148 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
151 if (IS_CHAN_HT40(chan))
153 if (IS_CHAN_HALF_RATE(chan))
155 if (IS_CHAN_QUARTER_RATE(chan))
159 common->clockrate = clockrate;
162 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
164 struct ath_common *common = ath9k_hw_common(ah);
166 return usecs * common->clockrate;
169 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
173 BUG_ON(timeout < AH_TIME_QUANTUM);
175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
176 if ((REG_READ(ah, reg) & mask) == val)
179 udelay(AH_TIME_QUANTUM);
182 ath_dbg(ath9k_hw_common(ah), ANY,
183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
184 timeout, reg, REG_READ(ah, reg), mask, val);
188 EXPORT_SYMBOL(ath9k_hw_wait);
190 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
195 if (IS_CHAN_HALF_RATE(chan))
197 else if (IS_CHAN_QUARTER_RATE(chan))
200 udelay(hw_delay + BASE_ACTIVATE_DELAY);
203 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
204 int column, unsigned int *writecnt)
208 ENABLE_REGWRITE_BUFFER(ah);
209 for (r = 0; r < array->ia_rows; r++) {
210 REG_WRITE(ah, INI_RA(array, r, 0),
211 INI_RA(array, r, column));
214 REGWRITE_BUFFER_FLUSH(ah);
217 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
222 for (i = 0, retval = 0; i < n; i++) {
223 retval = (retval << 1) | (val & 1);
229 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
231 u32 frameLen, u16 rateix,
234 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
240 case WLAN_RC_PHY_CCK:
241 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
244 numBits = frameLen << 3;
245 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
247 case WLAN_RC_PHY_OFDM:
248 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
249 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
250 numBits = OFDM_PLCP_BITS + (frameLen << 3);
251 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
252 txTime = OFDM_SIFS_TIME_QUARTER
253 + OFDM_PREAMBLE_TIME_QUARTER
254 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
255 } else if (ah->curchan &&
256 IS_CHAN_HALF_RATE(ah->curchan)) {
257 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
258 numBits = OFDM_PLCP_BITS + (frameLen << 3);
259 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
260 txTime = OFDM_SIFS_TIME_HALF +
261 OFDM_PREAMBLE_TIME_HALF
262 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
268 + (numSymbols * OFDM_SYMBOL_TIME);
272 ath_err(ath9k_hw_common(ah),
273 "Unknown phy %u (rate ix %u)\n", phy, rateix);
280 EXPORT_SYMBOL(ath9k_hw_computetxtime);
282 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
283 struct ath9k_channel *chan,
284 struct chan_centers *centers)
288 if (!IS_CHAN_HT40(chan)) {
289 centers->ctl_center = centers->ext_center =
290 centers->synth_center = chan->channel;
294 if (IS_CHAN_HT40PLUS(chan)) {
295 centers->synth_center =
296 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
299 centers->synth_center =
300 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
304 centers->ctl_center =
305 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
306 /* 25 MHz spacing is supported by hw but not on upper layers */
307 centers->ext_center =
308 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
315 static void ath9k_hw_read_revisions(struct ath_hw *ah)
319 switch (ah->hw_version.devid) {
320 case AR5416_AR9100_DEVID:
321 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
323 case AR9300_DEVID_AR9330:
324 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
325 if (ah->get_mac_revision) {
326 ah->hw_version.macRev = ah->get_mac_revision();
328 val = REG_READ(ah, AR_SREV);
329 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
332 case AR9300_DEVID_AR9340:
333 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
334 val = REG_READ(ah, AR_SREV);
335 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
337 case AR9300_DEVID_QCA955X:
338 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
342 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
345 val = REG_READ(ah, AR_SREV);
346 ah->hw_version.macVersion =
347 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
348 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
350 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
351 ah->is_pciexpress = true;
353 ah->is_pciexpress = (val &
354 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
356 if (!AR_SREV_9100(ah))
357 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
359 ah->hw_version.macRev = val & AR_SREV_REVISION;
361 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
362 ah->is_pciexpress = true;
366 /************************************/
367 /* HW Attach, Detach, Init Routines */
368 /************************************/
370 static void ath9k_hw_disablepcie(struct ath_hw *ah)
372 if (!AR_SREV_5416(ah))
375 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
376 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
377 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
378 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
379 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
385 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
388 /* This should work for all families including legacy */
389 static bool ath9k_hw_chip_test(struct ath_hw *ah)
391 struct ath_common *common = ath9k_hw_common(ah);
392 u32 regAddr[2] = { AR_STA_ID0 };
394 static const u32 patternData[4] = {
395 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
399 if (!AR_SREV_9300_20_OR_LATER(ah)) {
401 regAddr[1] = AR_PHY_BASE + (8 << 2);
405 for (i = 0; i < loop_max; i++) {
406 u32 addr = regAddr[i];
409 regHold[i] = REG_READ(ah, addr);
410 for (j = 0; j < 0x100; j++) {
411 wrData = (j << 16) | j;
412 REG_WRITE(ah, addr, wrData);
413 rdData = REG_READ(ah, addr);
414 if (rdData != wrData) {
416 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
417 addr, wrData, rdData);
421 for (j = 0; j < 4; j++) {
422 wrData = patternData[j];
423 REG_WRITE(ah, addr, wrData);
424 rdData = REG_READ(ah, addr);
425 if (wrData != rdData) {
427 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
428 addr, wrData, rdData);
432 REG_WRITE(ah, regAddr[i], regHold[i]);
439 static void ath9k_hw_init_config(struct ath_hw *ah)
443 ah->config.dma_beacon_response_time = 1;
444 ah->config.sw_beacon_response_time = 6;
445 ah->config.additional_swba_backoff = 0;
446 ah->config.ack_6mb = 0x0;
447 ah->config.cwm_ignore_extcca = 0;
448 ah->config.pcie_clock_req = 0;
449 ah->config.analog_shiftreg = 1;
451 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
452 ah->config.spurchans[i][0] = AR_NO_SPUR;
453 ah->config.spurchans[i][1] = AR_NO_SPUR;
456 ah->config.rx_intr_mitigation = true;
459 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
460 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
461 * This means we use it for all AR5416 devices, and the few
462 * minor PCI AR9280 devices out there.
464 * Serialization is required because these devices do not handle
465 * well the case of two concurrent reads/writes due to the latency
466 * involved. During one read/write another read/write can be issued
467 * on another CPU while the previous read/write may still be working
468 * on our hardware, if we hit this case the hardware poops in a loop.
469 * We prevent this by serializing reads and writes.
471 * This issue is not present on PCI-Express devices or pre-AR5416
472 * devices (legacy, 802.11abg).
474 if (num_possible_cpus() > 1)
475 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
478 static void ath9k_hw_init_defaults(struct ath_hw *ah)
480 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
482 regulatory->country_code = CTRY_DEFAULT;
483 regulatory->power_limit = MAX_RATE_POWER;
485 ah->hw_version.magic = AR5416_MAGIC;
486 ah->hw_version.subvendorid = 0;
489 ah->sta_id1_defaults =
490 AR_STA_ID1_CRPT_MIC_ENABLE |
491 AR_STA_ID1_MCAST_KSRCH;
492 if (AR_SREV_9100(ah))
493 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
494 ah->slottime = ATH9K_SLOT_TIME_9;
495 ah->globaltxtimeout = (u32) -1;
496 ah->power_mode = ATH9K_PM_UNDEFINED;
497 ah->htc_reset_init = true;
500 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
502 struct ath_common *common = ath9k_hw_common(ah);
506 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
509 for (i = 0; i < 3; i++) {
510 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
512 common->macaddr[2 * i] = eeval >> 8;
513 common->macaddr[2 * i + 1] = eeval & 0xff;
515 if (sum == 0 || sum == 0xffff * 3)
516 return -EADDRNOTAVAIL;
521 static int ath9k_hw_post_init(struct ath_hw *ah)
523 struct ath_common *common = ath9k_hw_common(ah);
526 if (common->bus_ops->ath_bus_type != ATH_USB) {
527 if (!ath9k_hw_chip_test(ah))
531 if (!AR_SREV_9300_20_OR_LATER(ah)) {
532 ecode = ar9002_hw_rf_claim(ah);
537 ecode = ath9k_hw_eeprom_init(ah);
541 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
542 ah->eep_ops->get_eeprom_ver(ah),
543 ah->eep_ops->get_eeprom_rev(ah));
545 ath9k_hw_ani_init(ah);
548 * EEPROM needs to be initialized before we do this.
549 * This is required for regulatory compliance.
551 if (AR_SREV_9300_20_OR_LATER(ah)) {
552 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
553 if ((regdmn & 0xF0) == CTL_FCC) {
554 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
555 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
562 static int ath9k_hw_attach_ops(struct ath_hw *ah)
564 if (!AR_SREV_9300_20_OR_LATER(ah))
565 return ar9002_hw_attach_ops(ah);
567 ar9003_hw_attach_ops(ah);
571 /* Called for all hardware families */
572 static int __ath9k_hw_init(struct ath_hw *ah)
574 struct ath_common *common = ath9k_hw_common(ah);
577 ath9k_hw_read_revisions(ah);
580 * Read back AR_WA into a permanent copy and set bits 14 and 17.
581 * We need to do this to avoid RMW of this register. We cannot
582 * read the reg when chip is asleep.
584 if (AR_SREV_9300_20_OR_LATER(ah)) {
585 ah->WARegVal = REG_READ(ah, AR_WA);
586 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
587 AR_WA_ASPM_TIMER_BASED_DISABLE);
590 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
591 ath_err(common, "Couldn't reset chip\n");
595 if (AR_SREV_9565(ah)) {
596 ah->WARegVal |= AR_WA_BIT22;
597 REG_WRITE(ah, AR_WA, ah->WARegVal);
600 ath9k_hw_init_defaults(ah);
601 ath9k_hw_init_config(ah);
603 r = ath9k_hw_attach_ops(ah);
607 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
608 ath_err(common, "Couldn't wakeup chip\n");
612 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
613 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
614 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
615 !ah->is_pciexpress)) {
616 ah->config.serialize_regmode =
619 ah->config.serialize_regmode =
624 ath_dbg(common, RESET, "serialize_regmode is %d\n",
625 ah->config.serialize_regmode);
627 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
628 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
630 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
632 switch (ah->hw_version.macVersion) {
633 case AR_SREV_VERSION_5416_PCI:
634 case AR_SREV_VERSION_5416_PCIE:
635 case AR_SREV_VERSION_9160:
636 case AR_SREV_VERSION_9100:
637 case AR_SREV_VERSION_9280:
638 case AR_SREV_VERSION_9285:
639 case AR_SREV_VERSION_9287:
640 case AR_SREV_VERSION_9271:
641 case AR_SREV_VERSION_9300:
642 case AR_SREV_VERSION_9330:
643 case AR_SREV_VERSION_9485:
644 case AR_SREV_VERSION_9340:
645 case AR_SREV_VERSION_9462:
646 case AR_SREV_VERSION_9550:
647 case AR_SREV_VERSION_9565:
651 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
652 ah->hw_version.macVersion, ah->hw_version.macRev);
656 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
657 AR_SREV_9330(ah) || AR_SREV_9550(ah))
658 ah->is_pciexpress = false;
660 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
661 ath9k_hw_init_cal_settings(ah);
663 ah->ani_function = ATH9K_ANI_ALL;
664 if (!AR_SREV_9300_20_OR_LATER(ah))
665 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
667 if (!ah->is_pciexpress)
668 ath9k_hw_disablepcie(ah);
670 r = ath9k_hw_post_init(ah);
674 ath9k_hw_init_mode_gain_regs(ah);
675 r = ath9k_hw_fill_cap_info(ah);
679 r = ath9k_hw_init_macaddr(ah);
681 ath_err(common, "Failed to initialize MAC address\n");
685 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
686 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
688 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
690 if (AR_SREV_9330(ah))
691 ah->bb_watchdog_timeout_ms = 85;
693 ah->bb_watchdog_timeout_ms = 25;
695 common->state = ATH_HW_INITIALIZED;
700 int ath9k_hw_init(struct ath_hw *ah)
703 struct ath_common *common = ath9k_hw_common(ah);
705 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
706 switch (ah->hw_version.devid) {
707 case AR5416_DEVID_PCI:
708 case AR5416_DEVID_PCIE:
709 case AR5416_AR9100_DEVID:
710 case AR9160_DEVID_PCI:
711 case AR9280_DEVID_PCI:
712 case AR9280_DEVID_PCIE:
713 case AR9285_DEVID_PCIE:
714 case AR9287_DEVID_PCI:
715 case AR9287_DEVID_PCIE:
716 case AR2427_DEVID_PCIE:
717 case AR9300_DEVID_PCIE:
718 case AR9300_DEVID_AR9485_PCIE:
719 case AR9300_DEVID_AR9330:
720 case AR9300_DEVID_AR9340:
721 case AR9300_DEVID_QCA955X:
722 case AR9300_DEVID_AR9580:
723 case AR9300_DEVID_AR9462:
724 case AR9485_DEVID_AR1111:
725 case AR9300_DEVID_AR9565:
728 if (common->bus_ops->ath_bus_type == ATH_USB)
730 ath_err(common, "Hardware device ID 0x%04x not supported\n",
731 ah->hw_version.devid);
735 ret = __ath9k_hw_init(ah);
738 "Unable to initialize hardware; initialization status: %d\n",
745 EXPORT_SYMBOL(ath9k_hw_init);
747 static void ath9k_hw_init_qos(struct ath_hw *ah)
749 ENABLE_REGWRITE_BUFFER(ah);
751 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
752 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
754 REG_WRITE(ah, AR_QOS_NO_ACK,
755 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
756 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
757 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
759 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
760 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
761 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
762 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
763 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
765 REGWRITE_BUFFER_FLUSH(ah);
768 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
770 struct ath_common *common = ath9k_hw_common(ah);
773 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
775 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
777 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
781 if (WARN_ON_ONCE(i >= 100)) {
782 ath_err(common, "PLL4 meaurement not done\n");
789 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
791 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
793 static void ath9k_hw_init_pll(struct ath_hw *ah,
794 struct ath9k_channel *chan)
798 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
799 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
800 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
801 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
803 AR_CH0_DPLL2_KD, 0x40);
804 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
805 AR_CH0_DPLL2_KI, 0x4);
807 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
808 AR_CH0_BB_DPLL1_REFDIV, 0x5);
809 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
810 AR_CH0_BB_DPLL1_NINI, 0x58);
811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
812 AR_CH0_BB_DPLL1_NFRAC, 0x0);
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
815 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
817 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
819 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
821 /* program BB PLL phase_shift to 0x6 */
822 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
823 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
825 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
826 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
828 } else if (AR_SREV_9330(ah)) {
829 u32 ddr_dpll2, pll_control2, kd;
831 if (ah->is_clk_25mhz) {
832 ddr_dpll2 = 0x18e82f01;
833 pll_control2 = 0xe04a3d;
836 ddr_dpll2 = 0x19e82f01;
837 pll_control2 = 0x886666;
841 /* program DDR PLL ki and kd value */
842 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
844 /* program DDR PLL phase_shift */
845 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
846 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
848 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
851 /* program refdiv, nint, frac to RTC register */
852 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
854 /* program BB PLL kd and ki value */
855 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
856 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
858 /* program BB PLL phase_shift */
859 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
860 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
861 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
862 u32 regval, pll2_divint, pll2_divfrac, refdiv;
864 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
867 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
870 if (ah->is_clk_25mhz) {
872 pll2_divfrac = 0x1eb85;
875 if (AR_SREV_9340(ah)) {
881 pll2_divfrac = 0x26666;
886 regval = REG_READ(ah, AR_PHY_PLL_MODE);
887 regval |= (0x1 << 16);
888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
891 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
892 (pll2_divint << 18) | pll2_divfrac);
895 regval = REG_READ(ah, AR_PHY_PLL_MODE);
896 if (AR_SREV_9340(ah))
897 regval = (regval & 0x80071fff) | (0x1 << 30) |
898 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
900 regval = (regval & 0x80071fff) | (0x3 << 30) |
901 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
902 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
903 REG_WRITE(ah, AR_PHY_PLL_MODE,
904 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
908 pll = ath9k_hw_compute_pll_control(ah, chan);
909 if (AR_SREV_9565(ah))
911 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
913 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
917 /* Switch the core clock for ar9271 to 117Mhz */
918 if (AR_SREV_9271(ah)) {
920 REG_WRITE(ah, 0x50040, 0x304);
923 udelay(RTC_PLL_SETTLE_DELAY);
925 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
927 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
928 if (ah->is_clk_25mhz) {
929 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
930 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
931 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
933 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
934 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
935 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
941 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
942 enum nl80211_iftype opmode)
944 u32 sync_default = AR_INTR_SYNC_DEFAULT;
945 u32 imr_reg = AR_IMR_TXERR |
951 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
952 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
954 if (AR_SREV_9300_20_OR_LATER(ah)) {
955 imr_reg |= AR_IMR_RXOK_HP;
956 if (ah->config.rx_intr_mitigation)
957 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
959 imr_reg |= AR_IMR_RXOK_LP;
962 if (ah->config.rx_intr_mitigation)
963 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
965 imr_reg |= AR_IMR_RXOK;
968 if (ah->config.tx_intr_mitigation)
969 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
971 imr_reg |= AR_IMR_TXOK;
973 ENABLE_REGWRITE_BUFFER(ah);
975 REG_WRITE(ah, AR_IMR, imr_reg);
976 ah->imrs2_reg |= AR_IMR_S2_GTT;
977 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
979 if (!AR_SREV_9100(ah)) {
980 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
981 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
982 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
985 REGWRITE_BUFFER_FLUSH(ah);
987 if (AR_SREV_9300_20_OR_LATER(ah)) {
988 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
989 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
990 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
991 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
995 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
997 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
998 val = min(val, (u32) 0xFFFF);
999 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1002 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1004 u32 val = ath9k_hw_mac_to_clks(ah, us);
1005 val = min(val, (u32) 0xFFFF);
1006 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1009 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1011 u32 val = ath9k_hw_mac_to_clks(ah, us);
1012 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1013 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1016 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1018 u32 val = ath9k_hw_mac_to_clks(ah, us);
1019 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1020 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1023 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1026 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1028 ah->globaltxtimeout = (u32) -1;
1031 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1032 ah->globaltxtimeout = tu;
1037 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1039 struct ath_common *common = ath9k_hw_common(ah);
1040 const struct ath9k_channel *chan = ah->curchan;
1041 int acktimeout, ctstimeout, ack_offset = 0;
1044 int rx_lat = 0, tx_lat = 0, eifs = 0;
1047 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1053 if (ah->misc_mode != 0)
1054 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1056 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1062 if (IS_CHAN_5GHZ(chan))
1067 if (IS_CHAN_HALF_RATE(chan)) {
1071 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1077 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1079 rx_lat = (rx_lat * 4) - 1;
1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1088 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1089 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1090 reg = AR_USEC_ASYNC_FIFO;
1092 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1094 reg = REG_READ(ah, AR_USEC);
1096 rx_lat = MS(reg, AR_USEC_RX_LAT);
1097 tx_lat = MS(reg, AR_USEC_TX_LAT);
1099 slottime = ah->slottime;
1102 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1103 slottime += 3 * ah->coverage_class;
1104 acktimeout = slottime + sifstime + ack_offset;
1105 ctstimeout = acktimeout;
1108 * Workaround for early ACK timeouts, add an offset to match the
1109 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1110 * This was initially only meant to work around an issue with delayed
1111 * BA frames in some implementations, but it has been found to fix ACK
1112 * timeout issues in other cases as well.
1114 if (IS_CHAN_2GHZ(chan) &&
1115 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1116 acktimeout += 64 - sifstime - ah->slottime;
1117 ctstimeout += 48 - sifstime - ah->slottime;
1120 ath9k_hw_set_sifs_time(ah, sifstime);
1121 ath9k_hw_setslottime(ah, slottime);
1122 ath9k_hw_set_ack_timeout(ah, acktimeout);
1123 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1124 if (ah->globaltxtimeout != (u32) -1)
1125 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1127 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1128 REG_RMW(ah, AR_USEC,
1129 (common->clockrate - 1) |
1130 SM(rx_lat, AR_USEC_RX_LAT) |
1131 SM(tx_lat, AR_USEC_TX_LAT),
1132 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1135 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1137 void ath9k_hw_deinit(struct ath_hw *ah)
1139 struct ath_common *common = ath9k_hw_common(ah);
1141 if (common->state < ATH_HW_INITIALIZED)
1144 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1146 EXPORT_SYMBOL(ath9k_hw_deinit);
1152 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1154 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1156 if (IS_CHAN_2GHZ(chan))
1164 /****************************************/
1165 /* Reset and Channel Switching Routines */
1166 /****************************************/
1168 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1170 struct ath_common *common = ath9k_hw_common(ah);
1173 ENABLE_REGWRITE_BUFFER(ah);
1176 * set AHB_MODE not to do cacheline prefetches
1178 if (!AR_SREV_9300_20_OR_LATER(ah))
1179 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1182 * let mac dma reads be in 128 byte chunks
1184 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1186 REGWRITE_BUFFER_FLUSH(ah);
1189 * Restore TX Trigger Level to its pre-reset value.
1190 * The initial value depends on whether aggregation is enabled, and is
1191 * adjusted whenever underruns are detected.
1193 if (!AR_SREV_9300_20_OR_LATER(ah))
1194 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1196 ENABLE_REGWRITE_BUFFER(ah);
1199 * let mac dma writes be in 128 byte chunks
1201 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1204 * Setup receive FIFO threshold to hold off TX activities
1206 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1208 if (AR_SREV_9300_20_OR_LATER(ah)) {
1209 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1210 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1212 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1213 ah->caps.rx_status_len);
1217 * reduce the number of usable entries in PCU TXBUF to avoid
1218 * wrap around issues.
1220 if (AR_SREV_9285(ah)) {
1221 /* For AR9285 the number of Fifos are reduced to half.
1222 * So set the usable tx buf size also to half to
1223 * avoid data/delimiter underruns
1225 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1226 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1227 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1228 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1230 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1233 if (!AR_SREV_9271(ah))
1234 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1236 REGWRITE_BUFFER_FLUSH(ah);
1238 if (AR_SREV_9300_20_OR_LATER(ah))
1239 ath9k_hw_reset_txstatus_ring(ah);
1242 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1244 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1245 u32 set = AR_STA_ID1_KSRCH_MODE;
1248 case NL80211_IFTYPE_ADHOC:
1249 set |= AR_STA_ID1_ADHOC;
1250 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1252 case NL80211_IFTYPE_MESH_POINT:
1253 case NL80211_IFTYPE_AP:
1254 set |= AR_STA_ID1_STA_AP;
1256 case NL80211_IFTYPE_STATION:
1257 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1260 if (!ah->is_monitoring)
1264 REG_RMW(ah, AR_STA_ID1, set, mask);
1267 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1268 u32 *coef_mantissa, u32 *coef_exponent)
1270 u32 coef_exp, coef_man;
1272 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1273 if ((coef_scaled >> coef_exp) & 0x1)
1276 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1278 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1280 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1281 *coef_exponent = coef_exp - 16;
1284 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1289 if (AR_SREV_9100(ah)) {
1290 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1291 AR_RTC_DERIVED_CLK_PERIOD, 1);
1292 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1295 ENABLE_REGWRITE_BUFFER(ah);
1297 if (AR_SREV_9300_20_OR_LATER(ah)) {
1298 REG_WRITE(ah, AR_WA, ah->WARegVal);
1302 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1303 AR_RTC_FORCE_WAKE_ON_INT);
1305 if (AR_SREV_9100(ah)) {
1306 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1307 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1309 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1310 if (AR_SREV_9340(ah))
1311 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1313 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1314 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1318 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1321 if (!AR_SREV_9300_20_OR_LATER(ah))
1323 REG_WRITE(ah, AR_RC, val);
1325 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1326 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1328 rst_flags = AR_RTC_RC_MAC_WARM;
1329 if (type == ATH9K_RESET_COLD)
1330 rst_flags |= AR_RTC_RC_MAC_COLD;
1333 if (AR_SREV_9330(ah)) {
1338 * call external reset function to reset WMAC if:
1339 * - doing a cold reset
1340 * - we have pending frames in the TX queues
1343 for (i = 0; i < AR_NUM_QCU; i++) {
1344 npend = ath9k_hw_numtxpending(ah, i);
1349 if (ah->external_reset &&
1350 (npend || type == ATH9K_RESET_COLD)) {
1353 ath_dbg(ath9k_hw_common(ah), RESET,
1354 "reset MAC via external reset\n");
1356 reset_err = ah->external_reset();
1358 ath_err(ath9k_hw_common(ah),
1359 "External reset failed, err=%d\n",
1364 REG_WRITE(ah, AR_RTC_RESET, 1);
1368 if (ath9k_hw_mci_is_enabled(ah))
1369 ar9003_mci_check_gpm_offset(ah);
1371 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1373 REGWRITE_BUFFER_FLUSH(ah);
1377 REG_WRITE(ah, AR_RTC_RC, 0);
1378 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1379 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1383 if (!AR_SREV_9100(ah))
1384 REG_WRITE(ah, AR_RC, 0);
1386 if (AR_SREV_9100(ah))
1392 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1394 ENABLE_REGWRITE_BUFFER(ah);
1396 if (AR_SREV_9300_20_OR_LATER(ah)) {
1397 REG_WRITE(ah, AR_WA, ah->WARegVal);
1401 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1402 AR_RTC_FORCE_WAKE_ON_INT);
1404 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1405 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1407 REG_WRITE(ah, AR_RTC_RESET, 0);
1409 REGWRITE_BUFFER_FLUSH(ah);
1411 if (!AR_SREV_9300_20_OR_LATER(ah))
1414 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1415 REG_WRITE(ah, AR_RC, 0);
1417 REG_WRITE(ah, AR_RTC_RESET, 1);
1419 if (!ath9k_hw_wait(ah,
1424 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1428 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1431 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1435 if (AR_SREV_9300_20_OR_LATER(ah)) {
1436 REG_WRITE(ah, AR_WA, ah->WARegVal);
1440 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1441 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1443 if (!ah->reset_power_on)
1444 type = ATH9K_RESET_POWER_ON;
1447 case ATH9K_RESET_POWER_ON:
1448 ret = ath9k_hw_set_reset_power_on(ah);
1450 ah->reset_power_on = true;
1452 case ATH9K_RESET_WARM:
1453 case ATH9K_RESET_COLD:
1454 ret = ath9k_hw_set_reset(ah, type);
1463 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1464 struct ath9k_channel *chan)
1466 int reset_type = ATH9K_RESET_WARM;
1468 if (AR_SREV_9280(ah)) {
1469 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1470 reset_type = ATH9K_RESET_POWER_ON;
1472 reset_type = ATH9K_RESET_COLD;
1473 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1474 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1475 reset_type = ATH9K_RESET_COLD;
1477 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1480 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1483 ah->chip_fullsleep = false;
1485 if (AR_SREV_9330(ah))
1486 ar9003_hw_internal_regulator_apply(ah);
1487 ath9k_hw_init_pll(ah, chan);
1488 ath9k_hw_set_rfmode(ah, chan);
1493 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1494 struct ath9k_channel *chan)
1496 struct ath_common *common = ath9k_hw_common(ah);
1497 struct ath9k_hw_capabilities *pCap = &ah->caps;
1498 bool band_switch = false, mode_diff = false;
1499 u8 ini_reloaded = 0;
1503 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1504 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1505 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1506 mode_diff = !!(flags_diff & ~CHANNEL_HT);
1509 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1510 if (ath9k_hw_numtxpending(ah, qnum)) {
1511 ath_dbg(common, QUEUE,
1512 "Transmit frames pending on queue %d\n", qnum);
1517 if (!ath9k_hw_rfbus_req(ah)) {
1518 ath_err(common, "Could not kill baseband RX\n");
1522 if (band_switch || mode_diff) {
1523 ath9k_hw_mark_phy_inactive(ah);
1527 ath9k_hw_init_pll(ah, chan);
1529 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1530 ath_err(common, "Failed to do fast channel change\n");
1535 ath9k_hw_set_channel_regs(ah, chan);
1537 r = ath9k_hw_rf_set_freq(ah, chan);
1539 ath_err(common, "Failed to set channel\n");
1542 ath9k_hw_set_clockrate(ah);
1543 ath9k_hw_apply_txpower(ah, chan, false);
1545 ath9k_hw_set_delta_slope(ah, chan);
1546 ath9k_hw_spur_mitigate_freq(ah, chan);
1548 if (band_switch || ini_reloaded)
1549 ah->eep_ops->set_board_values(ah, chan);
1551 ath9k_hw_init_bb(ah, chan);
1552 ath9k_hw_rfbus_done(ah);
1554 if (band_switch || ini_reloaded) {
1555 ah->ah_flags |= AH_FASTCC;
1556 ath9k_hw_init_cal(ah, chan);
1557 ah->ah_flags &= ~AH_FASTCC;
1563 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1565 u32 gpio_mask = ah->gpio_mask;
1568 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1569 if (!(gpio_mask & 1))
1572 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1573 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1577 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1578 int *hang_state, int *hang_pos)
1580 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1581 u32 chain_state, dcs_pos, i;
1583 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1584 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1585 for (i = 0; i < 3; i++) {
1586 if (chain_state == dcu_chain_state[i]) {
1587 *hang_state = chain_state;
1588 *hang_pos = dcs_pos;
1596 #define DCU_COMPLETE_STATE 1
1597 #define DCU_COMPLETE_STATE_MASK 0x3
1598 #define NUM_STATUS_READS 50
1599 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1601 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1602 u32 i, hang_pos, hang_state, num_state = 6;
1604 comp_state = REG_READ(ah, AR_DMADBG_6);
1606 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1607 ath_dbg(ath9k_hw_common(ah), RESET,
1608 "MAC Hang signature not found at DCU complete\n");
1612 chain_state = REG_READ(ah, dcs_reg);
1613 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1614 goto hang_check_iter;
1616 dcs_reg = AR_DMADBG_5;
1618 chain_state = REG_READ(ah, dcs_reg);
1619 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1620 goto hang_check_iter;
1622 ath_dbg(ath9k_hw_common(ah), RESET,
1623 "MAC Hang signature 1 not found\n");
1627 ath_dbg(ath9k_hw_common(ah), RESET,
1628 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1629 chain_state, comp_state, hang_state, hang_pos);
1631 for (i = 0; i < NUM_STATUS_READS; i++) {
1632 chain_state = REG_READ(ah, dcs_reg);
1633 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1634 comp_state = REG_READ(ah, AR_DMADBG_6);
1636 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1637 DCU_COMPLETE_STATE) ||
1638 (chain_state != hang_state))
1642 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1647 void ath9k_hw_check_nav(struct ath_hw *ah)
1649 struct ath_common *common = ath9k_hw_common(ah);
1652 val = REG_READ(ah, AR_NAV);
1653 if (val != 0xdeadbeef && val > 0x7fff) {
1654 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1655 REG_WRITE(ah, AR_NAV, 0);
1658 EXPORT_SYMBOL(ath9k_hw_check_nav);
1660 bool ath9k_hw_check_alive(struct ath_hw *ah)
1665 if (AR_SREV_9300(ah))
1666 return !ath9k_hw_detect_mac_hang(ah);
1668 if (AR_SREV_9285_12_OR_LATER(ah))
1672 reg = REG_READ(ah, AR_OBS_BUS_1);
1674 if ((reg & 0x7E7FFFEF) == 0x00702400)
1677 switch (reg & 0x7E000B00) {
1685 } while (count-- > 0);
1689 EXPORT_SYMBOL(ath9k_hw_check_alive);
1691 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1693 /* Setup MFP options for CCMP */
1694 if (AR_SREV_9280_20_OR_LATER(ah)) {
1695 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1696 * frames when constructing CCMP AAD. */
1697 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1699 ah->sw_mgmt_crypto = false;
1700 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1701 /* Disable hardware crypto for management frames */
1702 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1703 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1704 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1705 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1706 ah->sw_mgmt_crypto = true;
1708 ah->sw_mgmt_crypto = true;
1712 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1713 u32 macStaId1, u32 saveDefAntenna)
1715 struct ath_common *common = ath9k_hw_common(ah);
1717 ENABLE_REGWRITE_BUFFER(ah);
1719 REG_RMW(ah, AR_STA_ID1, macStaId1
1720 | AR_STA_ID1_RTS_USE_DEF
1721 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1722 | ah->sta_id1_defaults,
1723 ~AR_STA_ID1_SADH_MASK);
1724 ath_hw_setbssidmask(common);
1725 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1726 ath9k_hw_write_associd(ah);
1727 REG_WRITE(ah, AR_ISR, ~0);
1728 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1730 REGWRITE_BUFFER_FLUSH(ah);
1732 ath9k_hw_set_operating_mode(ah, ah->opmode);
1735 static void ath9k_hw_init_queues(struct ath_hw *ah)
1739 ENABLE_REGWRITE_BUFFER(ah);
1741 for (i = 0; i < AR_NUM_DCU; i++)
1742 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1744 REGWRITE_BUFFER_FLUSH(ah);
1747 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1748 ath9k_hw_resettxqueue(ah, i);
1752 * For big endian systems turn on swapping for descriptors
1754 static void ath9k_hw_init_desc(struct ath_hw *ah)
1756 struct ath_common *common = ath9k_hw_common(ah);
1758 if (AR_SREV_9100(ah)) {
1760 mask = REG_READ(ah, AR_CFG);
1761 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1762 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1765 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1766 REG_WRITE(ah, AR_CFG, mask);
1767 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1768 REG_READ(ah, AR_CFG));
1771 if (common->bus_ops->ath_bus_type == ATH_USB) {
1772 /* Configure AR9271 target WLAN */
1773 if (AR_SREV_9271(ah))
1774 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1776 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1779 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1781 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1783 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1789 * Fast channel change:
1790 * (Change synthesizer based on channel freq without resetting chip)
1792 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1794 struct ath_common *common = ath9k_hw_common(ah);
1795 struct ath9k_hw_capabilities *pCap = &ah->caps;
1798 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1801 if (ah->chip_fullsleep)
1807 if (chan->channel == ah->curchan->channel)
1810 if ((ah->curchan->channelFlags | chan->channelFlags) &
1811 (CHANNEL_HALF | CHANNEL_QUARTER))
1815 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1817 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1818 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1821 if (!ath9k_hw_check_alive(ah))
1825 * For AR9462, make sure that calibration data for
1826 * re-using are present.
1828 if (AR_SREV_9462(ah) && (ah->caldata &&
1829 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1830 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1831 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1834 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1835 ah->curchan->channel, chan->channel);
1837 ret = ath9k_hw_channel_change(ah, chan);
1841 if (ath9k_hw_mci_is_enabled(ah))
1842 ar9003_mci_2g5g_switch(ah, false);
1844 ath9k_hw_loadnf(ah, ah->curchan);
1845 ath9k_hw_start_nfcal(ah, true);
1847 if (AR_SREV_9271(ah))
1848 ar9002_hw_load_ani_reg(ah, chan);
1855 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1856 struct ath9k_hw_cal_data *caldata, bool fastcc)
1858 struct ath_common *common = ath9k_hw_common(ah);
1866 bool start_mci_reset = false;
1867 bool save_fullsleep = ah->chip_fullsleep;
1869 if (ath9k_hw_mci_is_enabled(ah)) {
1870 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1871 if (start_mci_reset)
1875 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1878 if (ah->curchan && !ah->chip_fullsleep)
1879 ath9k_hw_getnf(ah, ah->curchan);
1881 ah->caldata = caldata;
1882 if (caldata && (chan->channel != caldata->channel ||
1883 chan->channelFlags != caldata->channelFlags)) {
1884 /* Operating channel changed, reset channel calibration data */
1885 memset(caldata, 0, sizeof(*caldata));
1886 ath9k_init_nfcal_hist_buffer(ah, chan);
1887 } else if (caldata) {
1888 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1890 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1893 r = ath9k_hw_do_fastcc(ah, chan);
1898 if (ath9k_hw_mci_is_enabled(ah))
1899 ar9003_mci_stop_bt(ah, save_fullsleep);
1901 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1902 if (saveDefAntenna == 0)
1905 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1907 /* Save TSF before chip reset, a cold reset clears it */
1908 tsf = ath9k_hw_gettsf64(ah);
1909 getrawmonotonic(&ts);
1910 usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
1912 saveLedState = REG_READ(ah, AR_CFG_LED) &
1913 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1914 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1916 ath9k_hw_mark_phy_inactive(ah);
1918 ah->paprd_table_write_done = false;
1920 /* Only required on the first reset */
1921 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1923 AR9271_RESET_POWER_DOWN_CONTROL,
1924 AR9271_RADIO_RF_RST);
1928 if (!ath9k_hw_chip_reset(ah, chan)) {
1929 ath_err(common, "Chip reset failed\n");
1933 /* Only required on the first reset */
1934 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1935 ah->htc_reset_init = false;
1937 AR9271_RESET_POWER_DOWN_CONTROL,
1938 AR9271_GATE_MAC_CTL);
1943 getrawmonotonic(&ts);
1944 usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
1945 ath9k_hw_settsf64(ah, tsf + usec);
1947 if (AR_SREV_9280_20_OR_LATER(ah))
1948 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1950 if (!AR_SREV_9300_20_OR_LATER(ah))
1951 ar9002_hw_enable_async_fifo(ah);
1953 r = ath9k_hw_process_ini(ah, chan);
1957 if (ath9k_hw_mci_is_enabled(ah))
1958 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1961 * Some AR91xx SoC devices frequently fail to accept TSF writes
1962 * right after the chip reset. When that happens, write a new
1963 * value after the initvals have been applied, with an offset
1964 * based on measured time difference
1966 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1968 ath9k_hw_settsf64(ah, tsf);
1971 ath9k_hw_init_mfp(ah);
1973 ath9k_hw_set_delta_slope(ah, chan);
1974 ath9k_hw_spur_mitigate_freq(ah, chan);
1975 ah->eep_ops->set_board_values(ah, chan);
1977 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1979 r = ath9k_hw_rf_set_freq(ah, chan);
1983 ath9k_hw_set_clockrate(ah);
1985 ath9k_hw_init_queues(ah);
1986 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1987 ath9k_hw_ani_cache_ini_regs(ah);
1988 ath9k_hw_init_qos(ah);
1990 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1991 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1993 ath9k_hw_init_global_settings(ah);
1995 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1996 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1997 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1998 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1999 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2000 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2001 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2004 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
2006 ath9k_hw_set_dma(ah);
2008 if (!ath9k_hw_mci_is_enabled(ah))
2009 REG_WRITE(ah, AR_OBS, 8);
2011 if (ah->config.rx_intr_mitigation) {
2012 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2013 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2016 if (ah->config.tx_intr_mitigation) {
2017 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2018 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2021 ath9k_hw_init_bb(ah, chan);
2024 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2025 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
2027 if (!ath9k_hw_init_cal(ah, chan))
2030 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
2033 ENABLE_REGWRITE_BUFFER(ah);
2035 ath9k_hw_restore_chainmask(ah);
2036 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2038 REGWRITE_BUFFER_FLUSH(ah);
2040 ath9k_hw_init_desc(ah);
2042 if (ath9k_hw_btcoex_is_enabled(ah))
2043 ath9k_hw_btcoex_enable(ah);
2045 if (ath9k_hw_mci_is_enabled(ah))
2046 ar9003_mci_check_bt(ah);
2048 ath9k_hw_loadnf(ah, chan);
2049 ath9k_hw_start_nfcal(ah, true);
2051 if (AR_SREV_9300_20_OR_LATER(ah)) {
2052 ar9003_hw_bb_watchdog_config(ah);
2053 ar9003_hw_disable_phy_restart(ah);
2056 ath9k_hw_apply_gpio_override(ah);
2058 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2059 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2063 EXPORT_SYMBOL(ath9k_hw_reset);
2065 /******************************/
2066 /* Power Management (Chipset) */
2067 /******************************/
2070 * Notify Power Mgt is disabled in self-generated frames.
2071 * If requested, force chip to sleep.
2073 static void ath9k_set_power_sleep(struct ath_hw *ah)
2075 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2077 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2078 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2079 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2080 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2081 /* xxx Required for WLAN only case ? */
2082 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2087 * Clear the RTC force wake bit to allow the
2088 * mac to go to sleep.
2090 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2092 if (ath9k_hw_mci_is_enabled(ah))
2095 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2096 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2098 /* Shutdown chip. Active low */
2099 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2100 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2104 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2105 if (AR_SREV_9300_20_OR_LATER(ah))
2106 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2110 * Notify Power Management is enabled in self-generating
2111 * frames. If request, set power mode of chip to
2112 * auto/normal. Duration in units of 128us (1/8 TU).
2114 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2116 struct ath9k_hw_capabilities *pCap = &ah->caps;
2118 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2120 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2121 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2122 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2123 AR_RTC_FORCE_WAKE_ON_INT);
2126 /* When chip goes into network sleep, it could be waken
2127 * up by MCI_INT interrupt caused by BT's HW messages
2128 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2129 * rate (~100us). This will cause chip to leave and
2130 * re-enter network sleep mode frequently, which in
2131 * consequence will have WLAN MCI HW to generate lots of
2132 * SYS_WAKING and SYS_SLEEPING messages which will make
2133 * BT CPU to busy to process.
2135 if (ath9k_hw_mci_is_enabled(ah))
2136 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2137 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2139 * Clear the RTC force wake bit to allow the
2140 * mac to go to sleep.
2142 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2144 if (ath9k_hw_mci_is_enabled(ah))
2148 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2149 if (AR_SREV_9300_20_OR_LATER(ah))
2150 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2153 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2158 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2159 if (AR_SREV_9300_20_OR_LATER(ah)) {
2160 REG_WRITE(ah, AR_WA, ah->WARegVal);
2164 if ((REG_READ(ah, AR_RTC_STATUS) &
2165 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2166 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2169 if (!AR_SREV_9300_20_OR_LATER(ah))
2170 ath9k_hw_init_pll(ah, NULL);
2172 if (AR_SREV_9100(ah))
2173 REG_SET_BIT(ah, AR_RTC_RESET,
2176 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2177 AR_RTC_FORCE_WAKE_EN);
2180 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2181 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2182 if (val == AR_RTC_STATUS_ON)
2185 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2186 AR_RTC_FORCE_WAKE_EN);
2189 ath_err(ath9k_hw_common(ah),
2190 "Failed to wakeup in %uus\n",
2191 POWER_UP_TIME / 20);
2195 if (ath9k_hw_mci_is_enabled(ah))
2196 ar9003_mci_set_power_awake(ah);
2198 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2203 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2205 struct ath_common *common = ath9k_hw_common(ah);
2207 static const char *modes[] = {
2214 if (ah->power_mode == mode)
2217 ath_dbg(common, RESET, "%s -> %s\n",
2218 modes[ah->power_mode], modes[mode]);
2221 case ATH9K_PM_AWAKE:
2222 status = ath9k_hw_set_power_awake(ah);
2224 case ATH9K_PM_FULL_SLEEP:
2225 if (ath9k_hw_mci_is_enabled(ah))
2226 ar9003_mci_set_full_sleep(ah);
2228 ath9k_set_power_sleep(ah);
2229 ah->chip_fullsleep = true;
2231 case ATH9K_PM_NETWORK_SLEEP:
2232 ath9k_set_power_network_sleep(ah);
2235 ath_err(common, "Unknown power mode %u\n", mode);
2238 ah->power_mode = mode;
2241 * XXX: If this warning never comes up after a while then
2242 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2243 * ath9k_hw_setpower() return type void.
2246 if (!(ah->ah_flags & AH_UNPLUGGED))
2247 ATH_DBG_WARN_ON_ONCE(!status);
2251 EXPORT_SYMBOL(ath9k_hw_setpower);
2253 /*******************/
2254 /* Beacon Handling */
2255 /*******************/
2257 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2261 ENABLE_REGWRITE_BUFFER(ah);
2263 switch (ah->opmode) {
2264 case NL80211_IFTYPE_ADHOC:
2265 REG_SET_BIT(ah, AR_TXCFG,
2266 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2267 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2268 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2269 flags |= AR_NDP_TIMER_EN;
2270 case NL80211_IFTYPE_MESH_POINT:
2271 case NL80211_IFTYPE_AP:
2272 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2273 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2274 TU_TO_USEC(ah->config.dma_beacon_response_time));
2275 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2276 TU_TO_USEC(ah->config.sw_beacon_response_time));
2278 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2281 ath_dbg(ath9k_hw_common(ah), BEACON,
2282 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2287 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2288 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2289 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2290 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2292 REGWRITE_BUFFER_FLUSH(ah);
2294 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2296 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2298 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2299 const struct ath9k_beacon_state *bs)
2301 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2302 struct ath9k_hw_capabilities *pCap = &ah->caps;
2303 struct ath_common *common = ath9k_hw_common(ah);
2305 ENABLE_REGWRITE_BUFFER(ah);
2307 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2309 REG_WRITE(ah, AR_BEACON_PERIOD,
2310 TU_TO_USEC(bs->bs_intval));
2311 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2312 TU_TO_USEC(bs->bs_intval));
2314 REGWRITE_BUFFER_FLUSH(ah);
2316 REG_RMW_FIELD(ah, AR_RSSI_THR,
2317 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2319 beaconintval = bs->bs_intval;
2321 if (bs->bs_sleepduration > beaconintval)
2322 beaconintval = bs->bs_sleepduration;
2324 dtimperiod = bs->bs_dtimperiod;
2325 if (bs->bs_sleepduration > dtimperiod)
2326 dtimperiod = bs->bs_sleepduration;
2328 if (beaconintval == dtimperiod)
2329 nextTbtt = bs->bs_nextdtim;
2331 nextTbtt = bs->bs_nexttbtt;
2333 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2334 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2335 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2336 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2338 ENABLE_REGWRITE_BUFFER(ah);
2340 REG_WRITE(ah, AR_NEXT_DTIM,
2341 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2342 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2344 REG_WRITE(ah, AR_SLEEP1,
2345 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2346 | AR_SLEEP1_ASSUME_DTIM);
2348 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2349 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2351 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2353 REG_WRITE(ah, AR_SLEEP2,
2354 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2356 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2357 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2359 REGWRITE_BUFFER_FLUSH(ah);
2361 REG_SET_BIT(ah, AR_TIMER_MODE,
2362 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2365 /* TSF Out of Range Threshold */
2366 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2368 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2370 /*******************/
2371 /* HW Capabilities */
2372 /*******************/
2374 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2376 eeprom_chainmask &= chip_chainmask;
2377 if (eeprom_chainmask)
2378 return eeprom_chainmask;
2380 return chip_chainmask;
2384 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2385 * @ah: the atheros hardware data structure
2387 * We enable DFS support upstream on chipsets which have passed a series
2388 * of tests. The testing requirements are going to be documented. Desired
2389 * test requirements are documented at:
2391 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2393 * Once a new chipset gets properly tested an individual commit can be used
2394 * to document the testing for DFS for that chipset.
2396 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2399 switch (ah->hw_version.macVersion) {
2400 /* for temporary testing DFS with 9280 */
2401 case AR_SREV_VERSION_9280:
2402 /* AR9580 will likely be our first target to get testing on */
2403 case AR_SREV_VERSION_9580:
2410 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2412 struct ath9k_hw_capabilities *pCap = &ah->caps;
2413 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2414 struct ath_common *common = ath9k_hw_common(ah);
2415 unsigned int chip_chainmask;
2418 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2420 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2421 regulatory->current_rd = eeval;
2423 if (ah->opmode != NL80211_IFTYPE_AP &&
2424 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2425 if (regulatory->current_rd == 0x64 ||
2426 regulatory->current_rd == 0x65)
2427 regulatory->current_rd += 5;
2428 else if (regulatory->current_rd == 0x41)
2429 regulatory->current_rd = 0x43;
2430 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2431 regulatory->current_rd);
2434 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2435 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2437 "no band has been marked as supported in EEPROM\n");
2441 if (eeval & AR5416_OPFLAGS_11A)
2442 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2444 if (eeval & AR5416_OPFLAGS_11G)
2445 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2447 if (AR_SREV_9485(ah) ||
2452 else if (AR_SREV_9462(ah))
2454 else if (!AR_SREV_9280_20_OR_LATER(ah))
2456 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2461 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2463 * For AR9271 we will temporarilly uses the rx chainmax as read from
2466 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2467 !(eeval & AR5416_OPFLAGS_11A) &&
2468 !(AR_SREV_9271(ah)))
2469 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2470 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2471 else if (AR_SREV_9100(ah))
2472 pCap->rx_chainmask = 0x7;
2474 /* Use rx_chainmask from EEPROM. */
2475 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2477 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2478 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2479 ah->txchainmask = pCap->tx_chainmask;
2480 ah->rxchainmask = pCap->rx_chainmask;
2482 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2484 /* enable key search for every frame in an aggregate */
2485 if (AR_SREV_9300_20_OR_LATER(ah))
2486 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2488 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2490 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2491 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2493 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2495 if (AR_SREV_9271(ah))
2496 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2497 else if (AR_DEVID_7010(ah))
2498 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2499 else if (AR_SREV_9300_20_OR_LATER(ah))
2500 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2501 else if (AR_SREV_9287_11_OR_LATER(ah))
2502 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2503 else if (AR_SREV_9285_12_OR_LATER(ah))
2504 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2505 else if (AR_SREV_9280_20_OR_LATER(ah))
2506 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2508 pCap->num_gpio_pins = AR_NUM_GPIO;
2510 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2511 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2513 pCap->rts_aggr_limit = (8 * 1024);
2515 #ifdef CONFIG_ATH9K_RFKILL
2516 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2517 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2519 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2520 ah->rfkill_polarity =
2521 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2523 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2526 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2527 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2529 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2531 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2532 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2534 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2536 if (AR_SREV_9300_20_OR_LATER(ah)) {
2537 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2538 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
2539 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2541 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2542 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2543 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2544 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2545 pCap->txs_len = sizeof(struct ar9003_txs);
2547 pCap->tx_desc_len = sizeof(struct ath_desc);
2548 if (AR_SREV_9280_20(ah))
2549 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2552 if (AR_SREV_9300_20_OR_LATER(ah))
2553 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2555 if (AR_SREV_9300_20_OR_LATER(ah))
2556 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2558 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2559 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2561 if (AR_SREV_9285(ah)) {
2562 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2564 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2565 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2566 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2567 ath_info(common, "Enable LNA combining\n");
2572 if (AR_SREV_9300_20_OR_LATER(ah)) {
2573 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2574 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2577 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2578 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2579 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2580 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2581 ath_info(common, "Enable LNA combining\n");
2585 if (ath9k_hw_dfs_tested(ah))
2586 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2588 tx_chainmask = pCap->tx_chainmask;
2589 rx_chainmask = pCap->rx_chainmask;
2590 while (tx_chainmask || rx_chainmask) {
2591 if (tx_chainmask & BIT(0))
2592 pCap->max_txchains++;
2593 if (rx_chainmask & BIT(0))
2594 pCap->max_rxchains++;
2600 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2601 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2602 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2604 if (AR_SREV_9462_20_OR_LATER(ah))
2605 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2608 if (AR_SREV_9462(ah))
2609 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
2611 if (AR_SREV_9300_20_OR_LATER(ah) &&
2612 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2613 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2616 * Fast channel change across bands is available
2617 * only for AR9462 and AR9565.
2619 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2620 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH;
2625 /****************************/
2626 /* GPIO / RFKILL / Antennae */
2627 /****************************/
2629 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2633 u32 gpio_shift, tmp;
2636 addr = AR_GPIO_OUTPUT_MUX3;
2638 addr = AR_GPIO_OUTPUT_MUX2;
2640 addr = AR_GPIO_OUTPUT_MUX1;
2642 gpio_shift = (gpio % 6) * 5;
2644 if (AR_SREV_9280_20_OR_LATER(ah)
2645 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2646 REG_RMW(ah, addr, (type << gpio_shift),
2647 (0x1f << gpio_shift));
2649 tmp = REG_READ(ah, addr);
2650 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2651 tmp &= ~(0x1f << gpio_shift);
2652 tmp |= (type << gpio_shift);
2653 REG_WRITE(ah, addr, tmp);
2657 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2661 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2663 if (AR_DEVID_7010(ah)) {
2665 REG_RMW(ah, AR7010_GPIO_OE,
2666 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2667 (AR7010_GPIO_OE_MASK << gpio_shift));
2671 gpio_shift = gpio << 1;
2674 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2675 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2677 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2679 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2681 #define MS_REG_READ(x, y) \
2682 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2684 if (gpio >= ah->caps.num_gpio_pins)
2687 if (AR_DEVID_7010(ah)) {
2689 val = REG_READ(ah, AR7010_GPIO_IN);
2690 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2691 } else if (AR_SREV_9300_20_OR_LATER(ah))
2692 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2693 AR_GPIO_BIT(gpio)) != 0;
2694 else if (AR_SREV_9271(ah))
2695 return MS_REG_READ(AR9271, gpio) != 0;
2696 else if (AR_SREV_9287_11_OR_LATER(ah))
2697 return MS_REG_READ(AR9287, gpio) != 0;
2698 else if (AR_SREV_9285_12_OR_LATER(ah))
2699 return MS_REG_READ(AR9285, gpio) != 0;
2700 else if (AR_SREV_9280_20_OR_LATER(ah))
2701 return MS_REG_READ(AR928X, gpio) != 0;
2703 return MS_REG_READ(AR, gpio) != 0;
2705 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2707 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2712 if (AR_DEVID_7010(ah)) {
2714 REG_RMW(ah, AR7010_GPIO_OE,
2715 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2716 (AR7010_GPIO_OE_MASK << gpio_shift));
2720 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2721 gpio_shift = 2 * gpio;
2724 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2725 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2727 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2729 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2731 if (AR_DEVID_7010(ah)) {
2733 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2738 if (AR_SREV_9271(ah))
2741 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2744 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2746 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2748 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2750 EXPORT_SYMBOL(ath9k_hw_setantenna);
2752 /*********************/
2753 /* General Operation */
2754 /*********************/
2756 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2758 u32 bits = REG_READ(ah, AR_RX_FILTER);
2759 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2761 if (phybits & AR_PHY_ERR_RADAR)
2762 bits |= ATH9K_RX_FILTER_PHYRADAR;
2763 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2764 bits |= ATH9K_RX_FILTER_PHYERR;
2768 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2770 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2774 ENABLE_REGWRITE_BUFFER(ah);
2776 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2777 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2779 REG_WRITE(ah, AR_RX_FILTER, bits);
2782 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2783 phybits |= AR_PHY_ERR_RADAR;
2784 if (bits & ATH9K_RX_FILTER_PHYERR)
2785 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2786 REG_WRITE(ah, AR_PHY_ERR, phybits);
2789 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2791 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2793 REGWRITE_BUFFER_FLUSH(ah);
2795 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2797 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2799 if (ath9k_hw_mci_is_enabled(ah))
2800 ar9003_mci_bt_gain_ctrl(ah);
2802 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2805 ath9k_hw_init_pll(ah, NULL);
2806 ah->htc_reset_init = true;
2809 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2811 bool ath9k_hw_disable(struct ath_hw *ah)
2813 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2816 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2819 ath9k_hw_init_pll(ah, NULL);
2822 EXPORT_SYMBOL(ath9k_hw_disable);
2824 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2826 enum eeprom_param gain_param;
2828 if (IS_CHAN_2GHZ(chan))
2829 gain_param = EEP_ANTENNA_GAIN_2G;
2831 gain_param = EEP_ANTENNA_GAIN_5G;
2833 return ah->eep_ops->get_eeprom(ah, gain_param);
2836 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2839 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2840 struct ieee80211_channel *channel;
2841 int chan_pwr, new_pwr, max_gain;
2842 int ant_gain, ant_reduction = 0;
2847 channel = chan->chan;
2848 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2849 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2850 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2852 ant_gain = get_antenna_gain(ah, chan);
2853 if (ant_gain > max_gain)
2854 ant_reduction = ant_gain - max_gain;
2856 ah->eep_ops->set_txpower(ah, chan,
2857 ath9k_regd_get_ctl(reg, chan),
2858 ant_reduction, new_pwr, test);
2861 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2863 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2864 struct ath9k_channel *chan = ah->curchan;
2865 struct ieee80211_channel *channel = chan->chan;
2867 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2869 channel->max_power = MAX_RATE_POWER / 2;
2871 ath9k_hw_apply_txpower(ah, chan, test);
2874 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2876 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2878 void ath9k_hw_setopmode(struct ath_hw *ah)
2880 ath9k_hw_set_operating_mode(ah, ah->opmode);
2882 EXPORT_SYMBOL(ath9k_hw_setopmode);
2884 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2886 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2887 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2889 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2891 void ath9k_hw_write_associd(struct ath_hw *ah)
2893 struct ath_common *common = ath9k_hw_common(ah);
2895 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2896 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2897 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2899 EXPORT_SYMBOL(ath9k_hw_write_associd);
2901 #define ATH9K_MAX_TSF_READ 10
2903 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2905 u32 tsf_lower, tsf_upper1, tsf_upper2;
2908 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2909 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2910 tsf_lower = REG_READ(ah, AR_TSF_L32);
2911 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2912 if (tsf_upper2 == tsf_upper1)
2914 tsf_upper1 = tsf_upper2;
2917 WARN_ON( i == ATH9K_MAX_TSF_READ );
2919 return (((u64)tsf_upper1 << 32) | tsf_lower);
2921 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2923 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2925 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2926 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2928 EXPORT_SYMBOL(ath9k_hw_settsf64);
2930 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2932 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2933 AH_TSF_WRITE_TIMEOUT))
2934 ath_dbg(ath9k_hw_common(ah), RESET,
2935 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2937 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2939 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2941 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2944 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2946 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2948 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2950 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
2954 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
2955 macmode = AR_2040_JOINED_RX_CLEAR;
2959 REG_WRITE(ah, AR_2040_MODE, macmode);
2962 /* HW Generic timers configuration */
2964 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2966 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2967 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2968 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2969 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2970 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2971 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2972 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2973 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2974 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2975 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2976 AR_NDP2_TIMER_MODE, 0x0002},
2977 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2978 AR_NDP2_TIMER_MODE, 0x0004},
2979 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2980 AR_NDP2_TIMER_MODE, 0x0008},
2981 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2982 AR_NDP2_TIMER_MODE, 0x0010},
2983 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2984 AR_NDP2_TIMER_MODE, 0x0020},
2985 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2986 AR_NDP2_TIMER_MODE, 0x0040},
2987 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2988 AR_NDP2_TIMER_MODE, 0x0080}
2991 /* HW generic timer primitives */
2993 /* compute and clear index of rightmost 1 */
2994 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3004 return timer_table->gen_timer_index[b];
3007 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3009 return REG_READ(ah, AR_TSF_L32);
3011 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3013 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3014 void (*trigger)(void *),
3015 void (*overflow)(void *),
3019 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3020 struct ath_gen_timer *timer;
3022 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3026 /* allocate a hardware generic timer slot */
3027 timer_table->timers[timer_index] = timer;
3028 timer->index = timer_index;
3029 timer->trigger = trigger;
3030 timer->overflow = overflow;
3035 EXPORT_SYMBOL(ath_gen_timer_alloc);
3037 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3038 struct ath_gen_timer *timer,
3042 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3043 u32 tsf, timer_next;
3045 BUG_ON(!timer_period);
3047 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3049 tsf = ath9k_hw_gettsf32(ah);
3051 timer_next = tsf + trig_timeout;
3053 ath_dbg(ath9k_hw_common(ah), BTCOEX,
3054 "current tsf %x period %x timer_next %x\n",
3055 tsf, timer_period, timer_next);
3058 * Program generic timer registers
3060 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3062 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3064 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3065 gen_tmr_configuration[timer->index].mode_mask);
3067 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3069 * Starting from AR9462, each generic timer can select which tsf
3070 * to use. But we still follow the old rule, 0 - 7 use tsf and
3073 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3074 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3075 (1 << timer->index));
3077 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3078 (1 << timer->index));
3081 /* Enable both trigger and thresh interrupt masks */
3082 REG_SET_BIT(ah, AR_IMR_S5,
3083 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3084 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3086 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3088 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3090 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3092 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3093 (timer->index >= ATH_MAX_GEN_TIMER)) {
3097 /* Clear generic timer enable bits. */
3098 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3099 gen_tmr_configuration[timer->index].mode_mask);
3101 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3103 * Need to switch back to TSF if it was using TSF2.
3105 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3106 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3107 (1 << timer->index));
3111 /* Disable both trigger and thresh interrupt masks */
3112 REG_CLR_BIT(ah, AR_IMR_S5,
3113 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3114 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3116 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3118 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3120 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3122 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3124 /* free the hardware generic timer slot */
3125 timer_table->timers[timer->index] = NULL;
3128 EXPORT_SYMBOL(ath_gen_timer_free);
3131 * Generic Timer Interrupts handling
3133 void ath_gen_timer_isr(struct ath_hw *ah)
3135 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3136 struct ath_gen_timer *timer;
3137 struct ath_common *common = ath9k_hw_common(ah);
3138 u32 trigger_mask, thresh_mask, index;
3140 /* get hardware generic timer interrupt status */
3141 trigger_mask = ah->intr_gen_timer_trigger;
3142 thresh_mask = ah->intr_gen_timer_thresh;
3143 trigger_mask &= timer_table->timer_mask.val;
3144 thresh_mask &= timer_table->timer_mask.val;
3146 trigger_mask &= ~thresh_mask;
3148 while (thresh_mask) {
3149 index = rightmost_index(timer_table, &thresh_mask);
3150 timer = timer_table->timers[index];
3152 ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
3154 timer->overflow(timer->arg);
3157 while (trigger_mask) {
3158 index = rightmost_index(timer_table, &trigger_mask);
3159 timer = timer_table->timers[index];
3161 ath_dbg(common, BTCOEX,
3162 "Gen timer[%d] trigger\n", index);
3163 timer->trigger(timer->arg);
3166 EXPORT_SYMBOL(ath_gen_timer_isr);
3175 } ath_mac_bb_names[] = {
3176 /* Devices with external radios */
3177 { AR_SREV_VERSION_5416_PCI, "5416" },
3178 { AR_SREV_VERSION_5416_PCIE, "5418" },
3179 { AR_SREV_VERSION_9100, "9100" },
3180 { AR_SREV_VERSION_9160, "9160" },
3181 /* Single-chip solutions */
3182 { AR_SREV_VERSION_9280, "9280" },
3183 { AR_SREV_VERSION_9285, "9285" },
3184 { AR_SREV_VERSION_9287, "9287" },
3185 { AR_SREV_VERSION_9271, "9271" },
3186 { AR_SREV_VERSION_9300, "9300" },
3187 { AR_SREV_VERSION_9330, "9330" },
3188 { AR_SREV_VERSION_9340, "9340" },
3189 { AR_SREV_VERSION_9485, "9485" },
3190 { AR_SREV_VERSION_9462, "9462" },
3191 { AR_SREV_VERSION_9550, "9550" },
3192 { AR_SREV_VERSION_9565, "9565" },
3195 /* For devices with external radios */
3199 } ath_rf_names[] = {
3201 { AR_RAD5133_SREV_MAJOR, "5133" },
3202 { AR_RAD5122_SREV_MAJOR, "5122" },
3203 { AR_RAD2133_SREV_MAJOR, "2133" },
3204 { AR_RAD2122_SREV_MAJOR, "2122" }
3208 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3210 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3214 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3215 if (ath_mac_bb_names[i].version == mac_bb_version) {
3216 return ath_mac_bb_names[i].name;
3224 * Return the RF name. "????" is returned if the RF is unknown.
3225 * Used for devices with external radios.
3227 static const char *ath9k_hw_rf_name(u16 rf_version)
3231 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3232 if (ath_rf_names[i].version == rf_version) {
3233 return ath_rf_names[i].name;
3240 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3244 /* chipsets >= AR9280 are single-chip */
3245 if (AR_SREV_9280_20_OR_LATER(ah)) {
3246 used = scnprintf(hw_name, len,
3247 "Atheros AR%s Rev:%x",
3248 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3249 ah->hw_version.macRev);
3252 used = scnprintf(hw_name, len,
3253 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3254 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3255 ah->hw_version.macRev,
3256 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3257 & AR_RADIO_SREV_MAJOR)),
3258 ah->hw_version.phyRev);
3261 hw_name[used] = '\0';
3263 EXPORT_SYMBOL(ath9k_hw_name);