drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "hw-ops.h"
  23 #include "rc.h"
  24 #include "ar9003_mac.h"
  25
  26 #define ATH9K_CLOCK_RATE_CCK            22
  27 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  28 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  29 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32
  33 MODULE_AUTHOR("Atheros Communications");
  34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  36 MODULE_LICENSE("Dual BSD/GPL");
  37
  38 static int __init ath9k_init(void)
  39 {
  40         return 0;
  41 }
  42 module_init(ath9k_init);
  43
  44 static void __exit ath9k_exit(void)
  45 {
  46         return;
  47 }
  48 module_exit(ath9k_exit);
  49
  50 /* Private hardware callbacks */
  51
  52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  53 {
  54         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  55 }
  56
  57 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  58 {
  59         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  60 }
  61
  62 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  63 {
  64         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  65
  66         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  67 }
  68
  69 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  70                                         struct ath9k_channel *chan)
  71 {
  72         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  73 }
  74
  75 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  76 {
  77         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  78                 return;
  79
  80         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  81 }
  82
  83 /********************/
  84 /* Helper Functions */
  85 /********************/
  86
  87 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  88 {
  89         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  90
  91         if (!ah->curchan) /* should really check for CCK instead */
  92                 return usecs *ATH9K_CLOCK_RATE_CCK;
  93         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  94                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  95
  96         if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
  97                 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
  98         else
  99                 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
 100 }
 101
 102 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 103 {
 104         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 105
 106         if (conf_is_ht40(conf))
 107                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 108         else
 109                 return ath9k_hw_mac_clks(ah, usecs);
 110 }
 111
 112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 113 {
 114         int i;
 115
 116         BUG_ON(timeout < AH_TIME_QUANTUM);
 117
 118         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 119                 if ((REG_READ(ah, reg) & mask) == val)
 120                         return true;
 121
 122                 udelay(AH_TIME_QUANTUM);
 123         }
 124
 125         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 126                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 127                   timeout, reg, REG_READ(ah, reg), mask, val);
 128
 129         return false;
 130 }
 131 EXPORT_SYMBOL(ath9k_hw_wait);
 132
 133 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 134 {
 135         u32 retval;
 136         int i;
 137
 138         for (i = 0, retval = 0; i < n; i++) {
 139                 retval = (retval << 1) | (val & 1);
 140                 val >>= 1;
 141         }
 142         return retval;
 143 }
 144
 145 bool ath9k_get_channel_edges(struct ath_hw *ah,
 146                              u16 flags, u16 *low,
 147                              u16 *high)
 148 {
 149         struct ath9k_hw_capabilities *pCap = &ah->caps;
 150
 151         if (flags & CHANNEL_5GHZ) {
 152                 *low = pCap->low_5ghz_chan;
 153                 *high = pCap->high_5ghz_chan;
 154                 return true;
 155         }
 156         if ((flags & CHANNEL_2GHZ)) {
 157                 *low = pCap->low_2ghz_chan;
 158                 *high = pCap->high_2ghz_chan;
 159                 return true;
 160         }
 161         return false;
 162 }
 163
 164 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 165                            u8 phy, int kbps,
 166                            u32 frameLen, u16 rateix,
 167                            bool shortPreamble)
 168 {
 169         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 170
 171         if (kbps == 0)
 172                 return 0;
 173
 174         switch (phy) {
 175         case WLAN_RC_PHY_CCK:
 176                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 177                 if (shortPreamble)
 178                         phyTime >>= 1;
 179                 numBits = frameLen << 3;
 180                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 181                 break;
 182         case WLAN_RC_PHY_OFDM:
 183                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME_QUARTER
 188                                 + OFDM_PREAMBLE_TIME_QUARTER
 189                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 190                 } else if (ah->curchan &&
 191                            IS_CHAN_HALF_RATE(ah->curchan)) {
 192                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 193                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 194                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 195                         txTime = OFDM_SIFS_TIME_HALF +
 196                                 OFDM_PREAMBLE_TIME_HALF
 197                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 198                 } else {
 199                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 200                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 201                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 202                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 203                                 + (numSymbols * OFDM_SYMBOL_TIME);
 204                 }
 205                 break;
 206         default:
 207                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 208                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 209                 txTime = 0;
 210                 break;
 211         }
 212
 213         return txTime;
 214 }
 215 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 216
 217 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 218                                   struct ath9k_channel *chan,
 219                                   struct chan_centers *centers)
 220 {
 221         int8_t extoff;
 222
 223         if (!IS_CHAN_HT40(chan)) {
 224                 centers->ctl_center = centers->ext_center =
 225                         centers->synth_center = chan->channel;
 226                 return;
 227         }
 228
 229         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 230             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 231                 centers->synth_center =
 232                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 233                 extoff = 1;
 234         } else {
 235                 centers->synth_center =
 236                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 237                 extoff = -1;
 238         }
 239
 240         centers->ctl_center =
 241                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 242         /* 25 MHz spacing is supported by hw but not on upper layers */
 243         centers->ext_center =
 244                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 245 }
 246
 247 /******************/
 248 /* Chip Revisions */
 249 /******************/
 250
 251 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 252 {
 253         u32 val;
 254
 255         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 256
 257         if (val == 0xFF) {
 258                 val = REG_READ(ah, AR_SREV);
 259                 ah->hw_version.macVersion =
 260                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 261                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 262                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 263         } else {
 264                 if (!AR_SREV_9100(ah))
 265                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 266
 267                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 268
 269                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 270                         ah->is_pciexpress = true;
 271         }
 272 }
 273
 274 /************************************/
 275 /* HW Attach, Detach, Init Routines */
 276 /************************************/
 277
 278 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 279 {
 280         if (AR_SREV_9100(ah))
 281                 return;
 282
 283         ENABLE_REGWRITE_BUFFER(ah);
 284
 285         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 286         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 287         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 288         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 289         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 294
 295         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 296
 297         REGWRITE_BUFFER_FLUSH(ah);
 298         DISABLE_REGWRITE_BUFFER(ah);
 299 }
 300
 301 /* This should work for all families including legacy */
 302 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 303 {
 304         struct ath_common *common = ath9k_hw_common(ah);
 305         u32 regAddr[2] = { AR_STA_ID0 };
 306         u32 regHold[2];
 307         u32 patternData[4] = { 0x55555555,
 308                                0xaaaaaaaa,
 309                                0x66666666,
 310                                0x99999999 };
 311         int i, j, loop_max;
 312
 313         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 314                 loop_max = 2;
 315                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 316         } else
 317                 loop_max = 1;
 318
 319         for (i = 0; i < loop_max; i++) {
 320                 u32 addr = regAddr[i];
 321                 u32 wrData, rdData;
 322
 323                 regHold[i] = REG_READ(ah, addr);
 324                 for (j = 0; j < 0x100; j++) {
 325                         wrData = (j << 16) | j;
 326                         REG_WRITE(ah, addr, wrData);
 327                         rdData = REG_READ(ah, addr);
 328                         if (rdData != wrData) {
 329                                 ath_print(common, ATH_DBG_FATAL,
 330                                           "address test failed "
 331                                           "addr: 0x%08x - wr:0x%08x != "
 332                                           "rd:0x%08x\n",
 333                                           addr, wrData, rdData);
 334                                 return false;
 335                         }
 336                 }
 337                 for (j = 0; j < 4; j++) {
 338                         wrData = patternData[j];
 339                         REG_WRITE(ah, addr, wrData);
 340                         rdData = REG_READ(ah, addr);
 341                         if (wrData != rdData) {
 342                                 ath_print(common, ATH_DBG_FATAL,
 343                                           "address test failed "
 344                                           "addr: 0x%08x - wr:0x%08x != "
 345                                           "rd:0x%08x\n",
 346                                           addr, wrData, rdData);
 347                                 return false;
 348                         }
 349                 }
 350                 REG_WRITE(ah, regAddr[i], regHold[i]);
 351         }
 352         udelay(100);
 353
 354         return true;
 355 }
 356
 357 static void ath9k_hw_init_config(struct ath_hw *ah)
 358 {
 359         int i;
 360
 361         ah->config.dma_beacon_response_time = 2;
 362         ah->config.sw_beacon_response_time = 10;
 363         ah->config.additional_swba_backoff = 0;
 364         ah->config.ack_6mb = 0x0;
 365         ah->config.cwm_ignore_extcca = 0;
 366         ah->config.pcie_powersave_enable = 0;
 367         ah->config.pcie_clock_req = 0;
 368         ah->config.pcie_waen = 0;
 369         ah->config.analog_shiftreg = 1;
 370         ah->config.ofdm_trig_low = 200;
 371         ah->config.ofdm_trig_high = 500;
 372         ah->config.cck_trig_high = 200;
 373         ah->config.cck_trig_low = 100;
 374
 375         /*
 376          * For now ANI is disabled for AR9003, it is still
 377          * being tested.
 378          */
 379         if (!AR_SREV_9300_20_OR_LATER(ah))
 380                 ah->config.enable_ani = 1;
 381
 382         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 383                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 384                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 385         }
 386
 387         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 388                 ah->config.ht_enable = 1;
 389         else
 390                 ah->config.ht_enable = 0;
 391
 392         ah->config.rx_intr_mitigation = true;
 393
 394         /*
 395          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 396          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 397          * This means we use it for all AR5416 devices, and the few
 398          * minor PCI AR9280 devices out there.
 399          *
 400          * Serialization is required because these devices do not handle
 401          * well the case of two concurrent reads/writes due to the latency
 402          * involved. During one read/write another read/write can be issued
 403          * on another CPU while the previous read/write may still be working
 404          * on our hardware, if we hit this case the hardware poops in a loop.
 405          * We prevent this by serializing reads and writes.
 406          *
 407          * This issue is not present on PCI-Express devices or pre-AR5416
 408          * devices (legacy, 802.11abg).
 409          */
 410         if (num_possible_cpus() > 1)
 411                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 412 }
 413
 414 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 415 {
 416         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 417
 418         regulatory->country_code = CTRY_DEFAULT;
 419         regulatory->power_limit = MAX_RATE_POWER;
 420         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 421
 422         ah->hw_version.magic = AR5416_MAGIC;
 423         ah->hw_version.subvendorid = 0;
 424
 425         ah->ah_flags = 0;
 426         if (!AR_SREV_9100(ah))
 427                 ah->ah_flags = AH_USE_EEPROM;
 428
 429         ah->atim_window = 0;
 430         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 431         ah->beacon_interval = 100;
 432         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 433         ah->slottime = (u32) -1;
 434         ah->globaltxtimeout = (u32) -1;
 435         ah->power_mode = ATH9K_PM_UNDEFINED;
 436 }
 437
 438 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 439 {
 440         struct ath_common *common = ath9k_hw_common(ah);
 441         u32 sum;
 442         int i;
 443         u16 eeval;
 444         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 445
 446         sum = 0;
 447         for (i = 0; i < 3; i++) {
 448                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 449                 sum += eeval;
 450                 common->macaddr[2 * i] = eeval >> 8;
 451                 common->macaddr[2 * i + 1] = eeval & 0xff;
 452         }
 453         if (sum == 0 || sum == 0xffff * 3)
 454                 return -EADDRNOTAVAIL;
 455
 456         return 0;
 457 }
 458
 459 static int ath9k_hw_post_init(struct ath_hw *ah)
 460 {
 461         int ecode;
 462
 463         if (!AR_SREV_9271(ah)) {
 464                 if (!ath9k_hw_chip_test(ah))
 465                         return -ENODEV;
 466         }
 467
 468         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 469                 ecode = ar9002_hw_rf_claim(ah);
 470                 if (ecode != 0)
 471                         return ecode;
 472         }
 473
 474         ecode = ath9k_hw_eeprom_init(ah);
 475         if (ecode != 0)
 476                 return ecode;
 477
 478         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 479                   "Eeprom VER: %d, REV: %d\n",
 480                   ah->eep_ops->get_eeprom_ver(ah),
 481                   ah->eep_ops->get_eeprom_rev(ah));
 482
 483         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 484         if (ecode) {
 485                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 486                           "Failed allocating banks for "
 487                           "external radio\n");
 488                 return ecode;
 489         }
 490
 491         if (!AR_SREV_9100(ah)) {
 492                 ath9k_hw_ani_setup(ah);
 493                 ath9k_hw_ani_init(ah);
 494         }
 495
 496         return 0;
 497 }
 498
 499 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 500 {
 501         if (AR_SREV_9300_20_OR_LATER(ah))
 502                 ar9003_hw_attach_ops(ah);
 503         else
 504                 ar9002_hw_attach_ops(ah);
 505 }
 506
 507 /* Called for all hardware families */
 508 static int __ath9k_hw_init(struct ath_hw *ah)
 509 {
 510         struct ath_common *common = ath9k_hw_common(ah);
 511         int r = 0;
 512
 513         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 514                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 515
 516         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 517                 ath_print(common, ATH_DBG_FATAL,
 518                           "Couldn't reset chip\n");
 519                 return -EIO;
 520         }
 521
 522         ath9k_hw_init_defaults(ah);
 523         ath9k_hw_init_config(ah);
 524
 525         ath9k_hw_attach_ops(ah);
 526
 527         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 528                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 529                 return -EIO;
 530         }
 531
 532         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 533                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 534                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 535                         ah->config.serialize_regmode =
 536                                 SER_REG_MODE_ON;
 537                 } else {
 538                         ah->config.serialize_regmode =
 539                                 SER_REG_MODE_OFF;
 540                 }
 541         }
 542
 543         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 544                 ah->config.serialize_regmode);
 545
 546         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 547                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 548         else
 549                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 550
 551         if (!ath9k_hw_macversion_supported(ah)) {
 552                 ath_print(common, ATH_DBG_FATAL,
 553                           "Mac Chip Rev 0x%02x.%x is not supported by "
 554                           "this driver\n", ah->hw_version.macVersion,
 555                           ah->hw_version.macRev);
 556                 return -EOPNOTSUPP;
 557         }
 558
 559         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 560                 ah->is_pciexpress = false;
 561
 562         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 563         ath9k_hw_init_cal_settings(ah);
 564
 565         ah->ani_function = ATH9K_ANI_ALL;
 566         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 567                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 568
 569         ath9k_hw_init_mode_regs(ah);
 570
 571         /*
 572          * Configire PCIE after Ini init. SERDES values now come from ini file
 573          * This enables PCIe low power mode.
 574          */
 575         if (AR_SREV_9300_20_OR_LATER(ah)) {
 576                 u32 regval;
 577                 unsigned int i;
 578
 579                 /* Set Bits 16 and 17 in the AR_WA register. */
 580                 regval = REG_READ(ah, AR_WA);
 581                 regval |= 0x00030000;
 582                 REG_WRITE(ah, AR_WA, regval);
 583
 584                 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
 585                         REG_WRITE(ah,
 586                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
 587                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
 588                 }
 589         }
 590
 591         if (ah->is_pciexpress)
 592                 ath9k_hw_configpcipowersave(ah, 0, 0);
 593         else
 594                 ath9k_hw_disablepcie(ah);
 595
 596         if (!AR_SREV_9300_20_OR_LATER(ah))
 597                 ar9002_hw_cck_chan14_spread(ah);
 598
 599         r = ath9k_hw_post_init(ah);
 600         if (r)
 601                 return r;
 602
 603         ath9k_hw_init_mode_gain_regs(ah);
 604         r = ath9k_hw_fill_cap_info(ah);
 605         if (r)
 606                 return r;
 607
 608         r = ath9k_hw_init_macaddr(ah);
 609         if (r) {
 610                 ath_print(common, ATH_DBG_FATAL,
 611                           "Failed to initialize MAC address\n");
 612                 return r;
 613         }
 614
 615         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 616                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 617         else
 618                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 619
 620         if (AR_SREV_9300_20_OR_LATER(ah))
 621                 ar9003_hw_set_nf_limits(ah);
 622
 623         ath9k_init_nfcal_hist_buffer(ah);
 624         ah->bb_watchdog_timeout_ms = 25;
 625
 626         common->state = ATH_HW_INITIALIZED;
 627
 628         return 0;
 629 }
 630
 631 int ath9k_hw_init(struct ath_hw *ah)
 632 {
 633         int ret;
 634         struct ath_common *common = ath9k_hw_common(ah);
 635
 636         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 637         switch (ah->hw_version.devid) {
 638         case AR5416_DEVID_PCI:
 639         case AR5416_DEVID_PCIE:
 640         case AR5416_AR9100_DEVID:
 641         case AR9160_DEVID_PCI:
 642         case AR9280_DEVID_PCI:
 643         case AR9280_DEVID_PCIE:
 644         case AR9285_DEVID_PCIE:
 645         case AR9287_DEVID_PCI:
 646         case AR9287_DEVID_PCIE:
 647         case AR2427_DEVID_PCIE:
 648         case AR9300_DEVID_PCIE:
 649                 break;
 650         default:
 651                 if (common->bus_ops->ath_bus_type == ATH_USB)
 652                         break;
 653                 ath_print(common, ATH_DBG_FATAL,
 654                           "Hardware device ID 0x%04x not supported\n",
 655                           ah->hw_version.devid);
 656                 return -EOPNOTSUPP;
 657         }
 658
 659         ret = __ath9k_hw_init(ah);
 660         if (ret) {
 661                 ath_print(common, ATH_DBG_FATAL,
 662                           "Unable to initialize hardware; "
 663                           "initialization status: %d\n", ret);
 664                 return ret;
 665         }
 666
 667         return 0;
 668 }
 669 EXPORT_SYMBOL(ath9k_hw_init);
 670
 671 static void ath9k_hw_init_qos(struct ath_hw *ah)
 672 {
 673         ENABLE_REGWRITE_BUFFER(ah);
 674
 675         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 676         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 677
 678         REG_WRITE(ah, AR_QOS_NO_ACK,
 679                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 680                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 681                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 682
 683         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 684         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 685         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 686         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 687         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 688
 689         REGWRITE_BUFFER_FLUSH(ah);
 690         DISABLE_REGWRITE_BUFFER(ah);
 691 }
 692
 693 static void ath9k_hw_init_pll(struct ath_hw *ah,
 694                               struct ath9k_channel *chan)
 695 {
 696         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 697
 698         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 699
 700         /* Switch the core clock for ar9271 to 117Mhz */
 701         if (AR_SREV_9271(ah)) {
 702                 udelay(500);
 703                 REG_WRITE(ah, 0x50040, 0x304);
 704         }
 705
 706         udelay(RTC_PLL_SETTLE_DELAY);
 707
 708         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 709 }
 710
 711 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 712                                           enum nl80211_iftype opmode)
 713 {
 714         u32 imr_reg = AR_IMR_TXERR |
 715                 AR_IMR_TXURN |
 716                 AR_IMR_RXERR |
 717                 AR_IMR_RXORN |
 718                 AR_IMR_BCNMISC;
 719
 720         if (AR_SREV_9300_20_OR_LATER(ah)) {
 721                 imr_reg |= AR_IMR_RXOK_HP;
 722                 if (ah->config.rx_intr_mitigation)
 723                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 724                 else
 725                         imr_reg |= AR_IMR_RXOK_LP;
 726
 727         } else {
 728                 if (ah->config.rx_intr_mitigation)
 729                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 730                 else
 731                         imr_reg |= AR_IMR_RXOK;
 732         }
 733
 734         if (ah->config.tx_intr_mitigation)
 735                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 736         else
 737                 imr_reg |= AR_IMR_TXOK;
 738
 739         if (opmode == NL80211_IFTYPE_AP)
 740                 imr_reg |= AR_IMR_MIB;
 741
 742         ENABLE_REGWRITE_BUFFER(ah);
 743
 744         REG_WRITE(ah, AR_IMR, imr_reg);
 745         ah->imrs2_reg |= AR_IMR_S2_GTT;
 746         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 747
 748         if (!AR_SREV_9100(ah)) {
 749                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 750                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 751                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 752         }
 753
 754         REGWRITE_BUFFER_FLUSH(ah);
 755         DISABLE_REGWRITE_BUFFER(ah);
 756
 757         if (AR_SREV_9300_20_OR_LATER(ah)) {
 758                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 759                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 760                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 761                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 762         }
 763 }
 764
 765 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 766 {
 767         u32 val = ath9k_hw_mac_to_clks(ah, us);
 768         val = min(val, (u32) 0xFFFF);
 769         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 770 }
 771
 772 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 773 {
 774         u32 val = ath9k_hw_mac_to_clks(ah, us);
 775         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 776         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 777 }
 778
 779 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 780 {
 781         u32 val = ath9k_hw_mac_to_clks(ah, us);
 782         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 783         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 784 }
 785
 786 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 787 {
 788         if (tu > 0xFFFF) {
 789                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 790                           "bad global tx timeout %u\n", tu);
 791                 ah->globaltxtimeout = (u32) -1;
 792                 return false;
 793         } else {
 794                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 795                 ah->globaltxtimeout = tu;
 796                 return true;
 797         }
 798 }
 799
 800 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 801 {
 802         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 803         int acktimeout;
 804         int slottime;
 805         int sifstime;
 806
 807         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 808                   ah->misc_mode);
 809
 810         if (ah->misc_mode != 0)
 811                 REG_WRITE(ah, AR_PCU_MISC,
 812                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 813
 814         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 815                 sifstime = 16;
 816         else
 817                 sifstime = 10;
 818
 819         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 820         slottime = ah->slottime + 3 * ah->coverage_class;
 821         acktimeout = slottime + sifstime;
 822
 823         /*
 824          * Workaround for early ACK timeouts, add an offset to match the
 825          * initval's 64us ack timeout value.
 826          * This was initially only meant to work around an issue with delayed
 827          * BA frames in some implementations, but it has been found to fix ACK
 828          * timeout issues in other cases as well.
 829          */
 830         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 831                 acktimeout += 64 - sifstime - ah->slottime;
 832
 833         ath9k_hw_setslottime(ah, slottime);
 834         ath9k_hw_set_ack_timeout(ah, acktimeout);
 835         ath9k_hw_set_cts_timeout(ah, acktimeout);
 836         if (ah->globaltxtimeout != (u32) -1)
 837                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 838 }
 839 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 840
 841 void ath9k_hw_deinit(struct ath_hw *ah)
 842 {
 843         struct ath_common *common = ath9k_hw_common(ah);
 844
 845         if (common->state < ATH_HW_INITIALIZED)
 846                 goto free_hw;
 847
 848         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 849
 850 free_hw:
 851         ath9k_hw_rf_free_ext_banks(ah);
 852 }
 853 EXPORT_SYMBOL(ath9k_hw_deinit);
 854
 855 /*******/
 856 /* INI */
 857 /*******/
 858
 859 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 860 {
 861         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 862
 863         if (IS_CHAN_B(chan))
 864                 ctl |= CTL_11B;
 865         else if (IS_CHAN_G(chan))
 866                 ctl |= CTL_11G;
 867         else
 868                 ctl |= CTL_11A;
 869
 870         return ctl;
 871 }
 872
 873 /****************************************/
 874 /* Reset and Channel Switching Routines */
 875 /****************************************/
 876
 877 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 878 {
 879         struct ath_common *common = ath9k_hw_common(ah);
 880         u32 regval;
 881
 882         ENABLE_REGWRITE_BUFFER(ah);
 883
 884         /*
 885          * set AHB_MODE not to do cacheline prefetches
 886         */
 887         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 888                 regval = REG_READ(ah, AR_AHB_MODE);
 889                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 890         }
 891
 892         /*
 893          * let mac dma reads be in 128 byte chunks
 894          */
 895         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 896         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 897
 898         REGWRITE_BUFFER_FLUSH(ah);
 899         DISABLE_REGWRITE_BUFFER(ah);
 900
 901         /*
 902          * Restore TX Trigger Level to its pre-reset value.
 903          * The initial value depends on whether aggregation is enabled, and is
 904          * adjusted whenever underruns are detected.
 905          */
 906         if (!AR_SREV_9300_20_OR_LATER(ah))
 907                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 908
 909         ENABLE_REGWRITE_BUFFER(ah);
 910
 911         /*
 912          * let mac dma writes be in 128 byte chunks
 913          */
 914         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 915         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 916
 917         /*
 918          * Setup receive FIFO threshold to hold off TX activities
 919          */
 920         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 921
 922         if (AR_SREV_9300_20_OR_LATER(ah)) {
 923                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 924                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 925
 926                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 927                         ah->caps.rx_status_len);
 928         }
 929
 930         /*
 931          * reduce the number of usable entries in PCU TXBUF to avoid
 932          * wrap around issues.
 933          */
 934         if (AR_SREV_9285(ah)) {
 935                 /* For AR9285 the number of Fifos are reduced to half.
 936                  * So set the usable tx buf size also to half to
 937                  * avoid data/delimiter underruns
 938                  */
 939                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 940                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 941         } else if (!AR_SREV_9271(ah)) {
 942                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 943                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 944         }
 945
 946         REGWRITE_BUFFER_FLUSH(ah);
 947         DISABLE_REGWRITE_BUFFER(ah);
 948
 949         if (AR_SREV_9300_20_OR_LATER(ah))
 950                 ath9k_hw_reset_txstatus_ring(ah);
 951 }
 952
 953 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 954 {
 955         u32 val;
 956
 957         val = REG_READ(ah, AR_STA_ID1);
 958         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 959         switch (opmode) {
 960         case NL80211_IFTYPE_AP:
 961                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 962                           | AR_STA_ID1_KSRCH_MODE);
 963                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 964                 break;
 965         case NL80211_IFTYPE_ADHOC:
 966         case NL80211_IFTYPE_MESH_POINT:
 967                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 968                           | AR_STA_ID1_KSRCH_MODE);
 969                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 970                 break;
 971         case NL80211_IFTYPE_STATION:
 972         case NL80211_IFTYPE_MONITOR:
 973                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 974                 break;
 975         }
 976 }
 977
 978 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 979                                    u32 *coef_mantissa, u32 *coef_exponent)
 980 {
 981         u32 coef_exp, coef_man;
 982
 983         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 984                 if ((coef_scaled >> coef_exp) & 0x1)
 985                         break;
 986
 987         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 988
 989         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 990
 991         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 992         *coef_exponent = coef_exp - 16;
 993 }
 994
 995 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 996 {
 997         u32 rst_flags;
 998         u32 tmpReg;
 999
1000         if (AR_SREV_9100(ah)) {
1001                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1002                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1003                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1004                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1005                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1006         }
1007
1008         ENABLE_REGWRITE_BUFFER(ah);
1009
1010         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1011                   AR_RTC_FORCE_WAKE_ON_INT);
1012
1013         if (AR_SREV_9100(ah)) {
1014                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1015                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1016         } else {
1017                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1018                 if (tmpReg &
1019                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1020                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1021                         u32 val;
1022                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1023
1024                         val = AR_RC_HOSTIF;
1025                         if (!AR_SREV_9300_20_OR_LATER(ah))
1026                                 val |= AR_RC_AHB;
1027                         REG_WRITE(ah, AR_RC, val);
1028
1029                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1030                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1031
1032                 rst_flags = AR_RTC_RC_MAC_WARM;
1033                 if (type == ATH9K_RESET_COLD)
1034                         rst_flags |= AR_RTC_RC_MAC_COLD;
1035         }
1036
1037         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1038
1039         REGWRITE_BUFFER_FLUSH(ah);
1040         DISABLE_REGWRITE_BUFFER(ah);
1041
1042         udelay(50);
1043
1044         REG_WRITE(ah, AR_RTC_RC, 0);
1045         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1046                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1047                           "RTC stuck in MAC reset\n");
1048                 return false;
1049         }
1050
1051         if (!AR_SREV_9100(ah))
1052                 REG_WRITE(ah, AR_RC, 0);
1053
1054         if (AR_SREV_9100(ah))
1055                 udelay(50);
1056
1057         return true;
1058 }
1059
1060 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1061 {
1062         ENABLE_REGWRITE_BUFFER(ah);
1063
1064         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1065                   AR_RTC_FORCE_WAKE_ON_INT);
1066
1067         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1068                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1069
1070         REG_WRITE(ah, AR_RTC_RESET, 0);
1071
1072         REGWRITE_BUFFER_FLUSH(ah);
1073         DISABLE_REGWRITE_BUFFER(ah);
1074
1075         if (!AR_SREV_9300_20_OR_LATER(ah))
1076                 udelay(2);
1077
1078         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1079                 REG_WRITE(ah, AR_RC, 0);
1080
1081         REG_WRITE(ah, AR_RTC_RESET, 1);
1082
1083         if (!ath9k_hw_wait(ah,
1084                            AR_RTC_STATUS,
1085                            AR_RTC_STATUS_M,
1086                            AR_RTC_STATUS_ON,
1087                            AH_WAIT_TIMEOUT)) {
1088                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1089                           "RTC not waking up\n");
1090                 return false;
1091         }
1092
1093         ath9k_hw_read_revisions(ah);
1094
1095         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1096 }
1097
1098 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1099 {
1100         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1101                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1102
1103         switch (type) {
1104         case ATH9K_RESET_POWER_ON:
1105                 return ath9k_hw_set_reset_power_on(ah);
1106         case ATH9K_RESET_WARM:
1107         case ATH9K_RESET_COLD:
1108                 return ath9k_hw_set_reset(ah, type);
1109         default:
1110                 return false;
1111         }
1112 }
1113
1114 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1115                                 struct ath9k_channel *chan)
1116 {
1117         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1118                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1119                         return false;
1120         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1121                 return false;
1122
1123         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1124                 return false;
1125
1126         ah->chip_fullsleep = false;
1127         ath9k_hw_init_pll(ah, chan);
1128         ath9k_hw_set_rfmode(ah, chan);
1129
1130         return true;
1131 }
1132
1133 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1134                                     struct ath9k_channel *chan)
1135 {
1136         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1137         struct ath_common *common = ath9k_hw_common(ah);
1138         struct ieee80211_channel *channel = chan->chan;
1139         u32 qnum;
1140         int r;
1141
1142         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1143                 if (ath9k_hw_numtxpending(ah, qnum)) {
1144                         ath_print(common, ATH_DBG_QUEUE,
1145                                   "Transmit frames pending on "
1146                                   "queue %d\n", qnum);
1147                         return false;
1148                 }
1149         }
1150
1151         if (!ath9k_hw_rfbus_req(ah)) {
1152                 ath_print(common, ATH_DBG_FATAL,
1153                           "Could not kill baseband RX\n");
1154                 return false;
1155         }
1156
1157         ath9k_hw_set_channel_regs(ah, chan);
1158
1159         r = ath9k_hw_rf_set_freq(ah, chan);
1160         if (r) {
1161                 ath_print(common, ATH_DBG_FATAL,
1162                           "Failed to set channel\n");
1163                 return false;
1164         }
1165
1166         ah->eep_ops->set_txpower(ah, chan,
1167                              ath9k_regd_get_ctl(regulatory, chan),
1168                              channel->max_antenna_gain * 2,
1169                              channel->max_power * 2,
1170                              min((u32) MAX_RATE_POWER,
1171                              (u32) regulatory->power_limit));
1172
1173         ath9k_hw_rfbus_done(ah);
1174
1175         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1176                 ath9k_hw_set_delta_slope(ah, chan);
1177
1178         ath9k_hw_spur_mitigate_freq(ah, chan);
1179
1180         if (!chan->oneTimeCalsDone)
1181                 chan->oneTimeCalsDone = true;
1182
1183         return true;
1184 }
1185
1186 bool ath9k_hw_check_alive(struct ath_hw *ah)
1187 {
1188         int count = 50;
1189         u32 reg;
1190
1191         if (AR_SREV_9285_10_OR_LATER(ah))
1192                 return true;
1193
1194         do {
1195                 reg = REG_READ(ah, AR_OBS_BUS_1);
1196
1197                 if ((reg & 0x7E7FFFEF) == 0x00702400)
1198                         continue;
1199
1200                 switch (reg & 0x7E000B00) {
1201                 case 0x1E000000:
1202                 case 0x52000B00:
1203                 case 0x18000B00:
1204                         continue;
1205                 default:
1206                         return true;
1207                 }
1208         } while (count-- > 0);
1209
1210         return false;
1211 }
1212 EXPORT_SYMBOL(ath9k_hw_check_alive);
1213
1214 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1215                     bool bChannelChange)
1216 {
1217         struct ath_common *common = ath9k_hw_common(ah);
1218         u32 saveLedState;
1219         struct ath9k_channel *curchan = ah->curchan;
1220         u32 saveDefAntenna;
1221         u32 macStaId1;
1222         u64 tsf = 0;
1223         int i, r;
1224
1225         ah->txchainmask = common->tx_chainmask;
1226         ah->rxchainmask = common->rx_chainmask;
1227
1228         if (!ah->chip_fullsleep) {
1229                 ath9k_hw_abortpcurecv(ah);
1230                 if (!ath9k_hw_stopdmarecv(ah))
1231                         ath_print(common, ATH_DBG_XMIT,
1232                                 "Failed to stop receive dma\n");
1233         }
1234
1235         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1236                 return -EIO;
1237
1238         if (curchan && !ah->chip_fullsleep)
1239                 ath9k_hw_getnf(ah, curchan);
1240
1241         if (bChannelChange &&
1242             (ah->chip_fullsleep != true) &&
1243             (ah->curchan != NULL) &&
1244             (chan->channel != ah->curchan->channel) &&
1245             ((chan->channelFlags & CHANNEL_ALL) ==
1246              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1247             !AR_SREV_9280(ah)) {
1248
1249                 if (ath9k_hw_channel_change(ah, chan)) {
1250                         ath9k_hw_loadnf(ah, ah->curchan);
1251                         ath9k_hw_start_nfcal(ah);
1252                         return 0;
1253                 }
1254         }
1255
1256         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1257         if (saveDefAntenna == 0)
1258                 saveDefAntenna = 1;
1259
1260         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1261
1262         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1263         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1264                 tsf = ath9k_hw_gettsf64(ah);
1265
1266         saveLedState = REG_READ(ah, AR_CFG_LED) &
1267                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1268                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1269
1270         ath9k_hw_mark_phy_inactive(ah);
1271
1272         /* Only required on the first reset */
1273         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1274                 REG_WRITE(ah,
1275                           AR9271_RESET_POWER_DOWN_CONTROL,
1276                           AR9271_RADIO_RF_RST);
1277                 udelay(50);
1278         }
1279
1280         if (!ath9k_hw_chip_reset(ah, chan)) {
1281                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1282                 return -EINVAL;
1283         }
1284
1285         /* Only required on the first reset */
1286         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1287                 ah->htc_reset_init = false;
1288                 REG_WRITE(ah,
1289                           AR9271_RESET_POWER_DOWN_CONTROL,
1290                           AR9271_GATE_MAC_CTL);
1291                 udelay(50);
1292         }
1293
1294         /* Restore TSF */
1295         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1296                 ath9k_hw_settsf64(ah, tsf);
1297
1298         if (AR_SREV_9280_10_OR_LATER(ah))
1299                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1300
1301         r = ath9k_hw_process_ini(ah, chan);
1302         if (r)
1303                 return r;
1304
1305         /* Setup MFP options for CCMP */
1306         if (AR_SREV_9280_20_OR_LATER(ah)) {
1307                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1308                  * frames when constructing CCMP AAD. */
1309                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1310                               0xc7ff);
1311                 ah->sw_mgmt_crypto = false;
1312         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1313                 /* Disable hardware crypto for management frames */
1314                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1315                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1316                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1317                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1318                 ah->sw_mgmt_crypto = true;
1319         } else
1320                 ah->sw_mgmt_crypto = true;
1321
1322         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1323                 ath9k_hw_set_delta_slope(ah, chan);
1324
1325         ath9k_hw_spur_mitigate_freq(ah, chan);
1326         ah->eep_ops->set_board_values(ah, chan);
1327
1328         ath9k_hw_set_operating_mode(ah, ah->opmode);
1329
1330         ENABLE_REGWRITE_BUFFER(ah);
1331
1332         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1333         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1334                   | macStaId1
1335                   | AR_STA_ID1_RTS_USE_DEF
1336                   | (ah->config.
1337                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1338                   | ah->sta_id1_defaults);
1339         ath_hw_setbssidmask(common);
1340         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1341         ath9k_hw_write_associd(ah);
1342         REG_WRITE(ah, AR_ISR, ~0);
1343         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1344
1345         REGWRITE_BUFFER_FLUSH(ah);
1346         DISABLE_REGWRITE_BUFFER(ah);
1347
1348         r = ath9k_hw_rf_set_freq(ah, chan);
1349         if (r)
1350                 return r;
1351
1352         ENABLE_REGWRITE_BUFFER(ah);
1353
1354         for (i = 0; i < AR_NUM_DCU; i++)
1355                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1356
1357         REGWRITE_BUFFER_FLUSH(ah);
1358         DISABLE_REGWRITE_BUFFER(ah);
1359
1360         ah->intr_txqs = 0;
1361         for (i = 0; i < ah->caps.total_queues; i++)
1362                 ath9k_hw_resettxqueue(ah, i);
1363
1364         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1365         ath9k_hw_init_qos(ah);
1366
1367         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1368                 ath9k_enable_rfkill(ah);
1369
1370         ath9k_hw_init_global_settings(ah);
1371
1372         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1373                 ar9002_hw_enable_async_fifo(ah);
1374                 ar9002_hw_enable_wep_aggregation(ah);
1375         }
1376
1377         REG_WRITE(ah, AR_STA_ID1,
1378                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1379
1380         ath9k_hw_set_dma(ah);
1381
1382         REG_WRITE(ah, AR_OBS, 8);
1383
1384         if (ah->config.rx_intr_mitigation) {
1385                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1386                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1387         }
1388
1389         if (ah->config.tx_intr_mitigation) {
1390                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1391                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1392         }
1393
1394         ath9k_hw_init_bb(ah, chan);
1395
1396         if (!ath9k_hw_init_cal(ah, chan))
1397                 return -EIO;
1398
1399         ENABLE_REGWRITE_BUFFER(ah);
1400
1401         ath9k_hw_restore_chainmask(ah);
1402         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1403
1404         REGWRITE_BUFFER_FLUSH(ah);
1405         DISABLE_REGWRITE_BUFFER(ah);
1406
1407         /*
1408          * For big endian systems turn on swapping for descriptors
1409          */
1410         if (AR_SREV_9100(ah)) {
1411                 u32 mask;
1412                 mask = REG_READ(ah, AR_CFG);
1413                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1414                         ath_print(common, ATH_DBG_RESET,
1415                                 "CFG Byte Swap Set 0x%x\n", mask);
1416                 } else {
1417                         mask =
1418                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1419                         REG_WRITE(ah, AR_CFG, mask);
1420                         ath_print(common, ATH_DBG_RESET,
1421                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1422                 }
1423         } else {
1424                 /* Configure AR9271 target WLAN */
1425                 if (AR_SREV_9271(ah))
1426                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1427 #ifdef __BIG_ENDIAN
1428                 else
1429                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1430 #endif
1431         }
1432
1433         if (ah->btcoex_hw.enabled)
1434                 ath9k_hw_btcoex_enable(ah);
1435
1436         if (AR_SREV_9300_20_OR_LATER(ah)) {
1437                 ath9k_hw_loadnf(ah, curchan);
1438                 ath9k_hw_start_nfcal(ah);
1439                 ar9003_hw_bb_watchdog_config(ah);
1440         }
1441
1442         return 0;
1443 }
1444 EXPORT_SYMBOL(ath9k_hw_reset);
1445
1446 /************************/
1447 /* Key Cache Management */
1448 /************************/
1449
1450 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1451 {
1452         u32 keyType;
1453
1454         if (entry >= ah->caps.keycache_size) {
1455                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1456                           "keychache entry %u out of range\n", entry);
1457                 return false;
1458         }
1459
1460         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1461
1462         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1463         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1464         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1465         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1466         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1467         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1468         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1469         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1470
1471         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1472                 u16 micentry = entry + 64;
1473
1474                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1475                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1476                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1477                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1478
1479         }
1480
1481         return true;
1482 }
1483 EXPORT_SYMBOL(ath9k_hw_keyreset);
1484
1485 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1486 {
1487         u32 macHi, macLo;
1488
1489         if (entry >= ah->caps.keycache_size) {
1490                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1491                           "keychache entry %u out of range\n", entry);
1492                 return false;
1493         }
1494
1495         if (mac != NULL) {
1496                 macHi = (mac[5] << 8) | mac[4];
1497                 macLo = (mac[3] << 24) |
1498                         (mac[2] << 16) |
1499                         (mac[1] << 8) |
1500                         mac[0];
1501                 macLo >>= 1;
1502                 macLo |= (macHi & 1) << 31;
1503                 macHi >>= 1;
1504         } else {
1505                 macLo = macHi = 0;
1506         }
1507         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1508         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1509
1510         return true;
1511 }
1512 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1513
1514 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1515                                  const struct ath9k_keyval *k,
1516                                  const u8 *mac)
1517 {
1518         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1519         struct ath_common *common = ath9k_hw_common(ah);
1520         u32 key0, key1, key2, key3, key4;
1521         u32 keyType;
1522
1523         if (entry >= pCap->keycache_size) {
1524                 ath_print(common, ATH_DBG_FATAL,
1525                           "keycache entry %u out of range\n", entry);
1526                 return false;
1527         }
1528
1529         switch (k->kv_type) {
1530         case ATH9K_CIPHER_AES_OCB:
1531                 keyType = AR_KEYTABLE_TYPE_AES;
1532                 break;
1533         case ATH9K_CIPHER_AES_CCM:
1534                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1535                         ath_print(common, ATH_DBG_ANY,
1536                                   "AES-CCM not supported by mac rev 0x%x\n",
1537                                   ah->hw_version.macRev);
1538                         return false;
1539                 }
1540                 keyType = AR_KEYTABLE_TYPE_CCM;
1541                 break;
1542         case ATH9K_CIPHER_TKIP:
1543                 keyType = AR_KEYTABLE_TYPE_TKIP;
1544                 if (ATH9K_IS_MIC_ENABLED(ah)
1545                     && entry + 64 >= pCap->keycache_size) {
1546                         ath_print(common, ATH_DBG_ANY,
1547                                   "entry %u inappropriate for TKIP\n", entry);
1548                         return false;
1549                 }
1550                 break;
1551         case ATH9K_CIPHER_WEP:
1552                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1553                         ath_print(common, ATH_DBG_ANY,
1554                                   "WEP key length %u too small\n", k->kv_len);
1555                         return false;
1556                 }
1557                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1558                         keyType = AR_KEYTABLE_TYPE_40;
1559                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1560                         keyType = AR_KEYTABLE_TYPE_104;
1561                 else
1562                         keyType = AR_KEYTABLE_TYPE_128;
1563                 break;
1564         case ATH9K_CIPHER_CLR:
1565                 keyType = AR_KEYTABLE_TYPE_CLR;
1566                 break;
1567         default:
1568                 ath_print(common, ATH_DBG_FATAL,
1569                           "cipher %u not supported\n", k->kv_type);
1570                 return false;
1571         }
1572
1573         key0 = get_unaligned_le32(k->kv_val + 0);
1574         key1 = get_unaligned_le16(k->kv_val + 4);
1575         key2 = get_unaligned_le32(k->kv_val + 6);
1576         key3 = get_unaligned_le16(k->kv_val + 10);
1577         key4 = get_unaligned_le32(k->kv_val + 12);
1578         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1579                 key4 &= 0xff;
1580
1581         /*
1582          * Note: Key cache registers access special memory area that requires
1583          * two 32-bit writes to actually update the values in the internal
1584          * memory. Consequently, the exact order and pairs used here must be
1585          * maintained.
1586          */
1587
1588         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1589                 u16 micentry = entry + 64;
1590
1591                 /*
1592                  * Write inverted key[47:0] first to avoid Michael MIC errors
1593                  * on frames that could be sent or received at the same time.
1594                  * The correct key will be written in the end once everything
1595                  * else is ready.
1596                  */
1597                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1598                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1599
1600                 /* Write key[95:48] */
1601                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1602                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1603
1604                 /* Write key[127:96] and key type */
1605                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1606                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1607
1608                 /* Write MAC address for the entry */
1609                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1610
1611                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1612                         /*
1613                          * TKIP uses two key cache entries:
1614                          * Michael MIC TX/RX keys in the same key cache entry
1615                          * (idx = main index + 64):
1616                          * key0 [31:0] = RX key [31:0]
1617                          * key1 [15:0] = TX key [31:16]
1618                          * key1 [31:16] = reserved
1619                          * key2 [31:0] = RX key [63:32]
1620                          * key3 [15:0] = TX key [15:0]
1621                          * key3 [31:16] = reserved
1622                          * key4 [31:0] = TX key [63:32]
1623                          */
1624                         u32 mic0, mic1, mic2, mic3, mic4;
1625
1626                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1627                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1628                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1629                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1630                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1631
1632                         /* Write RX[31:0] and TX[31:16] */
1633                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1634                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1635
1636                         /* Write RX[63:32] and TX[15:0] */
1637                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1638                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1639
1640                         /* Write TX[63:32] and keyType(reserved) */
1641                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1642                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1643                                   AR_KEYTABLE_TYPE_CLR);
1644
1645                 } else {
1646                         /*
1647                          * TKIP uses four key cache entries (two for group
1648                          * keys):
1649                          * Michael MIC TX/RX keys are in different key cache
1650                          * entries (idx = main index + 64 for TX and
1651                          * main index + 32 + 96 for RX):
1652                          * key0 [31:0] = TX/RX MIC key [31:0]
1653                          * key1 [31:0] = reserved
1654                          * key2 [31:0] = TX/RX MIC key [63:32]
1655                          * key3 [31:0] = reserved
1656                          * key4 [31:0] = reserved
1657                          *
1658                          * Upper layer code will call this function separately
1659                          * for TX and RX keys when these registers offsets are
1660                          * used.
1661                          */
1662                         u32 mic0, mic2;
1663
1664                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1665                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1666
1667                         /* Write MIC key[31:0] */
1668                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1669                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1670
1671                         /* Write MIC key[63:32] */
1672                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1673                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1674
1675                         /* Write TX[63:32] and keyType(reserved) */
1676                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1677                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1678                                   AR_KEYTABLE_TYPE_CLR);
1679                 }
1680
1681                 /* MAC address registers are reserved for the MIC entry */
1682                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1683                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1684
1685                 /*
1686                  * Write the correct (un-inverted) key[47:0] last to enable
1687                  * TKIP now that all other registers are set with correct
1688                  * values.
1689                  */
1690                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1691                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1692         } else {
1693                 /* Write key[47:0] */
1694                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1695                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1696
1697                 /* Write key[95:48] */
1698                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1699                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1700
1701                 /* Write key[127:96] and key type */
1702                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1703                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1704
1705                 /* Write MAC address for the entry */
1706                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1707         }
1708
1709         return true;
1710 }
1711 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1712
1713 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1714 {
1715         if (entry < ah->caps.keycache_size) {
1716                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1717                 if (val & AR_KEYTABLE_VALID)
1718                         return true;
1719         }
1720         return false;
1721 }
1722 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1723
1724 /******************************/
1725 /* Power Management (Chipset) */
1726 /******************************/
1727
1728 /*
1729  * Notify Power Mgt is disabled in self-generated frames.
1730  * If requested, force chip to sleep.
1731  */
1732 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1733 {
1734         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1735         if (setChip) {
1736                 /*
1737                  * Clear the RTC force wake bit to allow the
1738                  * mac to go to sleep.
1739                  */
1740                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1741                             AR_RTC_FORCE_WAKE_EN);
1742                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1743                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1744
1745                 /* Shutdown chip. Active low */
1746                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1747                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1748                                     AR_RTC_RESET_EN);
1749         }
1750 }
1751
1752 /*
1753  * Notify Power Management is enabled in self-generating
1754  * frames. If request, set power mode of chip to
1755  * auto/normal.  Duration in units of 128us (1/8 TU).
1756  */
1757 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1758 {
1759         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1760         if (setChip) {
1761                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1762
1763                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1764                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1765                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1766                                   AR_RTC_FORCE_WAKE_ON_INT);
1767                 } else {
1768                         /*
1769                          * Clear the RTC force wake bit to allow the
1770                          * mac to go to sleep.
1771                          */
1772                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1773                                     AR_RTC_FORCE_WAKE_EN);
1774                 }
1775         }
1776 }
1777
1778 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1779 {
1780         u32 val;
1781         int i;
1782
1783         if (setChip) {
1784                 if ((REG_READ(ah, AR_RTC_STATUS) &
1785                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1786                         if (ath9k_hw_set_reset_reg(ah,
1787                                            ATH9K_RESET_POWER_ON) != true) {
1788                                 return false;
1789                         }
1790                         if (!AR_SREV_9300_20_OR_LATER(ah))
1791                                 ath9k_hw_init_pll(ah, NULL);
1792                 }
1793                 if (AR_SREV_9100(ah))
1794                         REG_SET_BIT(ah, AR_RTC_RESET,
1795                                     AR_RTC_RESET_EN);
1796
1797                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1798                             AR_RTC_FORCE_WAKE_EN);
1799                 udelay(50);
1800
1801                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1802                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1803                         if (val == AR_RTC_STATUS_ON)
1804                                 break;
1805                         udelay(50);
1806                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1807                                     AR_RTC_FORCE_WAKE_EN);
1808                 }
1809                 if (i == 0) {
1810                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1811                                   "Failed to wakeup in %uus\n",
1812                                   POWER_UP_TIME / 20);
1813                         return false;
1814                 }
1815         }
1816
1817         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1818
1819         return true;
1820 }
1821
1822 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1823 {
1824         struct ath_common *common = ath9k_hw_common(ah);
1825         int status = true, setChip = true;
1826         static const char *modes[] = {
1827                 "AWAKE",
1828                 "FULL-SLEEP",
1829                 "NETWORK SLEEP",
1830                 "UNDEFINED"
1831         };
1832
1833         if (ah->power_mode == mode)
1834                 return status;
1835
1836         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1837                   modes[ah->power_mode], modes[mode]);
1838
1839         switch (mode) {
1840         case ATH9K_PM_AWAKE:
1841                 status = ath9k_hw_set_power_awake(ah, setChip);
1842                 break;
1843         case ATH9K_PM_FULL_SLEEP:
1844                 ath9k_set_power_sleep(ah, setChip);
1845                 ah->chip_fullsleep = true;
1846                 break;
1847         case ATH9K_PM_NETWORK_SLEEP:
1848                 ath9k_set_power_network_sleep(ah, setChip);
1849                 break;
1850         default:
1851                 ath_print(common, ATH_DBG_FATAL,
1852                           "Unknown power mode %u\n", mode);
1853                 return false;
1854         }
1855         ah->power_mode = mode;
1856
1857         return status;
1858 }
1859 EXPORT_SYMBOL(ath9k_hw_setpower);
1860
1861 /*******************/
1862 /* Beacon Handling */
1863 /*******************/
1864
1865 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1866 {
1867         int flags = 0;
1868
1869         ah->beacon_interval = beacon_period;
1870
1871         ENABLE_REGWRITE_BUFFER(ah);
1872
1873         switch (ah->opmode) {
1874         case NL80211_IFTYPE_STATION:
1875         case NL80211_IFTYPE_MONITOR:
1876                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1877                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1878                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1879                 flags |= AR_TBTT_TIMER_EN;
1880                 break;
1881         case NL80211_IFTYPE_ADHOC:
1882         case NL80211_IFTYPE_MESH_POINT:
1883                 REG_SET_BIT(ah, AR_TXCFG,
1884                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1885                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1886                           TU_TO_USEC(next_beacon +
1887                                      (ah->atim_window ? ah->
1888                                       atim_window : 1)));
1889                 flags |= AR_NDP_TIMER_EN;
1890         case NL80211_IFTYPE_AP:
1891                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1892                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1893                           TU_TO_USEC(next_beacon -
1894                                      ah->config.
1895                                      dma_beacon_response_time));
1896                 REG_WRITE(ah, AR_NEXT_SWBA,
1897                           TU_TO_USEC(next_beacon -
1898                                      ah->config.
1899                                      sw_beacon_response_time));
1900                 flags |=
1901                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1902                 break;
1903         default:
1904                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1905                           "%s: unsupported opmode: %d\n",
1906                           __func__, ah->opmode);
1907                 return;
1908                 break;
1909         }
1910
1911         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1912         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1913         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1914         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1915
1916         REGWRITE_BUFFER_FLUSH(ah);
1917         DISABLE_REGWRITE_BUFFER(ah);
1918
1919         beacon_period &= ~ATH9K_BEACON_ENA;
1920         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1921                 ath9k_hw_reset_tsf(ah);
1922         }
1923
1924         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1925 }
1926 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1927
1928 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1929                                     const struct ath9k_beacon_state *bs)
1930 {
1931         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1932         struct ath9k_hw_capabilities *pCap = &ah->caps;
1933         struct ath_common *common = ath9k_hw_common(ah);
1934
1935         ENABLE_REGWRITE_BUFFER(ah);
1936
1937         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1938
1939         REG_WRITE(ah, AR_BEACON_PERIOD,
1940                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1941         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1942                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1943
1944         REGWRITE_BUFFER_FLUSH(ah);
1945         DISABLE_REGWRITE_BUFFER(ah);
1946
1947         REG_RMW_FIELD(ah, AR_RSSI_THR,
1948                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1949
1950         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1951
1952         if (bs->bs_sleepduration > beaconintval)
1953                 beaconintval = bs->bs_sleepduration;
1954
1955         dtimperiod = bs->bs_dtimperiod;
1956         if (bs->bs_sleepduration > dtimperiod)
1957                 dtimperiod = bs->bs_sleepduration;
1958
1959         if (beaconintval == dtimperiod)
1960                 nextTbtt = bs->bs_nextdtim;
1961         else
1962                 nextTbtt = bs->bs_nexttbtt;
1963
1964         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1965         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1966         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1967         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1968
1969         ENABLE_REGWRITE_BUFFER(ah);
1970
1971         REG_WRITE(ah, AR_NEXT_DTIM,
1972                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1973         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1974
1975         REG_WRITE(ah, AR_SLEEP1,
1976                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1977                   | AR_SLEEP1_ASSUME_DTIM);
1978
1979         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1980                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1981         else
1982                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1983
1984         REG_WRITE(ah, AR_SLEEP2,
1985                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1986
1987         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1988         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1989
1990         REGWRITE_BUFFER_FLUSH(ah);
1991         DISABLE_REGWRITE_BUFFER(ah);
1992
1993         REG_SET_BIT(ah, AR_TIMER_MODE,
1994                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1995                     AR_DTIM_TIMER_EN);
1996
1997         /* TSF Out of Range Threshold */
1998         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1999 }
2000 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2001
2002 /*******************/
2003 /* HW Capabilities */
2004 /*******************/
2005
2006 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2007 {
2008         struct ath9k_hw_capabilities *pCap = &ah->caps;
2009         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2010         struct ath_common *common = ath9k_hw_common(ah);
2011         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2012
2013         u16 capField = 0, eeval;
2014
2015         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2016         regulatory->current_rd = eeval;
2017
2018         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2019         if (AR_SREV_9285_10_OR_LATER(ah))
2020                 eeval |= AR9285_RDEXT_DEFAULT;
2021         regulatory->current_rd_ext = eeval;
2022
2023         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2024
2025         if (ah->opmode != NL80211_IFTYPE_AP &&
2026             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2027                 if (regulatory->current_rd == 0x64 ||
2028                     regulatory->current_rd == 0x65)
2029                         regulatory->current_rd += 5;
2030                 else if (regulatory->current_rd == 0x41)
2031                         regulatory->current_rd = 0x43;
2032                 ath_print(common, ATH_DBG_REGULATORY,
2033                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2034         }
2035
2036         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2037         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2038                 ath_print(common, ATH_DBG_FATAL,
2039                           "no band has been marked as supported in EEPROM.\n");
2040                 return -EINVAL;
2041         }
2042
2043         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2044
2045         if (eeval & AR5416_OPFLAGS_11A) {
2046                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2047                 if (ah->config.ht_enable) {
2048                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2049                                 set_bit(ATH9K_MODE_11NA_HT20,
2050                                         pCap->wireless_modes);
2051                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2052                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2053                                         pCap->wireless_modes);
2054                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2055                                         pCap->wireless_modes);
2056                         }
2057                 }
2058         }
2059
2060         if (eeval & AR5416_OPFLAGS_11G) {
2061                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2062                 if (ah->config.ht_enable) {
2063                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2064                                 set_bit(ATH9K_MODE_11NG_HT20,
2065                                         pCap->wireless_modes);
2066                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2067                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2068                                         pCap->wireless_modes);
2069                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2070                                         pCap->wireless_modes);
2071                         }
2072                 }
2073         }
2074
2075         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2076         /*
2077          * For AR9271 we will temporarilly uses the rx chainmax as read from
2078          * the EEPROM.
2079          */
2080         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2081             !(eeval & AR5416_OPFLAGS_11A) &&
2082             !(AR_SREV_9271(ah)))
2083                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2084                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2085         else
2086                 /* Use rx_chainmask from EEPROM. */
2087                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2088
2089         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2090                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2091
2092         pCap->low_2ghz_chan = 2312;
2093         pCap->high_2ghz_chan = 2732;
2094
2095         pCap->low_5ghz_chan = 4920;
2096         pCap->high_5ghz_chan = 6100;
2097
2098         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2099         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2100         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2101
2102         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2103         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2104         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2105
2106         if (ah->config.ht_enable)
2107                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2108         else
2109                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2110
2111         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2112         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2113         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2114         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2115
2116         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2117                 pCap->total_queues =
2118                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2119         else
2120                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2121
2122         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2123                 pCap->keycache_size =
2124                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2125         else
2126                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2127
2128         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2129
2130         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2131                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2132         else
2133                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2134
2135         if (AR_SREV_9271(ah))
2136                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2137         else if (AR_SREV_9285_10_OR_LATER(ah))
2138                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2139         else if (AR_SREV_9280_10_OR_LATER(ah))
2140                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2141         else
2142                 pCap->num_gpio_pins = AR_NUM_GPIO;
2143
2144         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2145                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2146                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2147         } else {
2148                 pCap->rts_aggr_limit = (8 * 1024);
2149         }
2150
2151         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2152
2153 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2154         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2155         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2156                 ah->rfkill_gpio =
2157                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2158                 ah->rfkill_polarity =
2159                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2160
2161                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2162         }
2163 #endif
2164         if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2165                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2166         else
2167                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2168
2169         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2170                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2171         else
2172                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2173
2174         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2175                 pCap->reg_cap =
2176                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2177                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2178                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2179                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2180         } else {
2181                 pCap->reg_cap =
2182                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2183                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2184         }
2185
2186         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2187         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2188             AR_SREV_5416(ah))
2189                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2190
2191         pCap->num_antcfg_5ghz =
2192                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2193         pCap->num_antcfg_2ghz =
2194                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2195
2196         if (AR_SREV_9280_10_OR_LATER(ah) &&
2197             ath9k_hw_btcoex_supported(ah)) {
2198                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2199                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2200
2201                 if (AR_SREV_9285(ah)) {
2202                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2203                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2204                 } else {
2205                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2206                 }
2207         } else {
2208                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2209         }
2210
2211         if (AR_SREV_9300_20_OR_LATER(ah)) {
2212                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2213                                  ATH9K_HW_CAP_FASTCLOCK;
2214                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2215                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2216                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2217                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2218                 pCap->txs_len = sizeof(struct ar9003_txs);
2219         } else {
2220                 pCap->tx_desc_len = sizeof(struct ath_desc);
2221                 if (AR_SREV_9280_20(ah) &&
2222                     ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2223                       AR5416_EEP_MINOR_VER_16) ||
2224                      ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2225                         pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2226         }
2227
2228         if (AR_SREV_9300_20_OR_LATER(ah))
2229                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2230
2231         if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
2232                 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2233
2234         return 0;
2235 }
2236
2237 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2238                             u32 capability, u32 *result)
2239 {
2240         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2241         switch (type) {
2242         case ATH9K_CAP_CIPHER:
2243                 switch (capability) {
2244                 case ATH9K_CIPHER_AES_CCM:
2245                 case ATH9K_CIPHER_AES_OCB:
2246                 case ATH9K_CIPHER_TKIP:
2247                 case ATH9K_CIPHER_WEP:
2248                 case ATH9K_CIPHER_MIC:
2249                 case ATH9K_CIPHER_CLR:
2250                         return true;
2251                 default:
2252                         return false;
2253                 }
2254         case ATH9K_CAP_TKIP_MIC:
2255                 switch (capability) {
2256                 case 0:
2257                         return true;
2258                 case 1:
2259                         return (ah->sta_id1_defaults &
2260                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2261                         false;
2262                 }
2263         case ATH9K_CAP_TKIP_SPLIT:
2264                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2265                         false : true;
2266         case ATH9K_CAP_MCAST_KEYSRCH:
2267                 switch (capability) {
2268                 case 0:
2269                         return true;
2270                 case 1:
2271                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2272                                 return false;
2273                         } else {
2274                                 return (ah->sta_id1_defaults &
2275                                         AR_STA_ID1_MCAST_KSRCH) ? true :
2276                                         false;
2277                         }
2278                 }
2279                 return false;
2280         case ATH9K_CAP_TXPOW:
2281                 switch (capability) {
2282                 case 0:
2283                         return 0;
2284                 case 1:
2285                         *result = regulatory->power_limit;
2286                         return 0;
2287                 case 2:
2288                         *result = regulatory->max_power_level;
2289                         return 0;
2290                 case 3:
2291                         *result = regulatory->tp_scale;
2292                         return 0;
2293                 }
2294                 return false;
2295         case ATH9K_CAP_DS:
2296                 return (AR_SREV_9280_20_OR_LATER(ah) &&
2297                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2298                         ? false : true;
2299         default:
2300                 return false;
2301         }
2302 }
2303 EXPORT_SYMBOL(ath9k_hw_getcapability);
2304
2305 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2306                             u32 capability, u32 setting, int *status)
2307 {
2308         switch (type) {
2309         case ATH9K_CAP_TKIP_MIC:
2310                 if (setting)
2311                         ah->sta_id1_defaults |=
2312                                 AR_STA_ID1_CRPT_MIC_ENABLE;
2313                 else
2314                         ah->sta_id1_defaults &=
2315                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2316                 return true;
2317         case ATH9K_CAP_MCAST_KEYSRCH:
2318                 if (setting)
2319                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2320                 else
2321                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2322                 return true;
2323         default:
2324                 return false;
2325         }
2326 }
2327 EXPORT_SYMBOL(ath9k_hw_setcapability);
2328
2329 /****************************/
2330 /* GPIO / RFKILL / Antennae */
2331 /****************************/
2332
2333 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2334                                          u32 gpio, u32 type)
2335 {
2336         int addr;
2337         u32 gpio_shift, tmp;
2338
2339         if (gpio > 11)
2340                 addr = AR_GPIO_OUTPUT_MUX3;
2341         else if (gpio > 5)
2342                 addr = AR_GPIO_OUTPUT_MUX2;
2343         else
2344                 addr = AR_GPIO_OUTPUT_MUX1;
2345
2346         gpio_shift = (gpio % 6) * 5;
2347
2348         if (AR_SREV_9280_20_OR_LATER(ah)
2349             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2350                 REG_RMW(ah, addr, (type << gpio_shift),
2351                         (0x1f << gpio_shift));
2352         } else {
2353                 tmp = REG_READ(ah, addr);
2354                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2355                 tmp &= ~(0x1f << gpio_shift);
2356                 tmp |= (type << gpio_shift);
2357                 REG_WRITE(ah, addr, tmp);
2358         }
2359 }
2360
2361 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2362 {
2363         u32 gpio_shift;
2364
2365         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2366
2367         gpio_shift = gpio << 1;
2368
2369         REG_RMW(ah,
2370                 AR_GPIO_OE_OUT,
2371                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2372                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2373 }
2374 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2375
2376 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2377 {
2378 #define MS_REG_READ(x, y) \
2379         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2380
2381         if (gpio >= ah->caps.num_gpio_pins)
2382                 return 0xffffffff;
2383
2384         if (AR_SREV_9300_20_OR_LATER(ah))
2385                 return MS_REG_READ(AR9300, gpio) != 0;
2386         else if (AR_SREV_9271(ah))
2387                 return MS_REG_READ(AR9271, gpio) != 0;
2388         else if (AR_SREV_9287_10_OR_LATER(ah))
2389                 return MS_REG_READ(AR9287, gpio) != 0;
2390         else if (AR_SREV_9285_10_OR_LATER(ah))
2391                 return MS_REG_READ(AR9285, gpio) != 0;
2392         else if (AR_SREV_9280_10_OR_LATER(ah))
2393                 return MS_REG_READ(AR928X, gpio) != 0;
2394         else
2395                 return MS_REG_READ(AR, gpio) != 0;
2396 }
2397 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2398
2399 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2400                          u32 ah_signal_type)
2401 {
2402         u32 gpio_shift;
2403
2404         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2405
2406         gpio_shift = 2 * gpio;
2407
2408         REG_RMW(ah,
2409                 AR_GPIO_OE_OUT,
2410                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2411                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2412 }
2413 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2414
2415 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2416 {
2417         if (AR_SREV_9271(ah))
2418                 val = ~val;
2419
2420         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2421                 AR_GPIO_BIT(gpio));
2422 }
2423 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2424
2425 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2426 {
2427         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2428 }
2429 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2430
2431 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2432 {
2433         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2434 }
2435 EXPORT_SYMBOL(ath9k_hw_setantenna);
2436
2437 /*********************/
2438 /* General Operation */
2439 /*********************/
2440
2441 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2442 {
2443         u32 bits = REG_READ(ah, AR_RX_FILTER);
2444         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2445
2446         if (phybits & AR_PHY_ERR_RADAR)
2447                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2448         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2449                 bits |= ATH9K_RX_FILTER_PHYERR;
2450
2451         return bits;
2452 }
2453 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2454
2455 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2456 {
2457         u32 phybits;
2458
2459         ENABLE_REGWRITE_BUFFER(ah);
2460
2461         REG_WRITE(ah, AR_RX_FILTER, bits);
2462
2463         phybits = 0;
2464         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2465                 phybits |= AR_PHY_ERR_RADAR;
2466         if (bits & ATH9K_RX_FILTER_PHYERR)
2467                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2468         REG_WRITE(ah, AR_PHY_ERR, phybits);
2469
2470         if (phybits)
2471                 REG_WRITE(ah, AR_RXCFG,
2472                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2473         else
2474                 REG_WRITE(ah, AR_RXCFG,
2475                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2476
2477         REGWRITE_BUFFER_FLUSH(ah);
2478         DISABLE_REGWRITE_BUFFER(ah);
2479 }
2480 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2481
2482 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2483 {
2484         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2485                 return false;
2486
2487         ath9k_hw_init_pll(ah, NULL);
2488         return true;
2489 }
2490 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2491
2492 bool ath9k_hw_disable(struct ath_hw *ah)
2493 {
2494         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2495                 return false;
2496
2497         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2498                 return false;
2499
2500         ath9k_hw_init_pll(ah, NULL);
2501         return true;
2502 }
2503 EXPORT_SYMBOL(ath9k_hw_disable);
2504
2505 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2506 {
2507         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2508         struct ath9k_channel *chan = ah->curchan;
2509         struct ieee80211_channel *channel = chan->chan;
2510
2511         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2512
2513         ah->eep_ops->set_txpower(ah, chan,
2514                                  ath9k_regd_get_ctl(regulatory, chan),
2515                                  channel->max_antenna_gain * 2,
2516                                  channel->max_power * 2,
2517                                  min((u32) MAX_RATE_POWER,
2518                                  (u32) regulatory->power_limit));
2519 }
2520 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2521
2522 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2523 {
2524         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2525 }
2526 EXPORT_SYMBOL(ath9k_hw_setmac);
2527
2528 void ath9k_hw_setopmode(struct ath_hw *ah)
2529 {
2530         ath9k_hw_set_operating_mode(ah, ah->opmode);
2531 }
2532 EXPORT_SYMBOL(ath9k_hw_setopmode);
2533
2534 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2535 {
2536         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2537         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2538 }
2539 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2540
2541 void ath9k_hw_write_associd(struct ath_hw *ah)
2542 {
2543         struct ath_common *common = ath9k_hw_common(ah);
2544
2545         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2546         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2547                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2548 }
2549 EXPORT_SYMBOL(ath9k_hw_write_associd);
2550
2551 #define ATH9K_MAX_TSF_READ 10
2552
2553 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2554 {
2555         u32 tsf_lower, tsf_upper1, tsf_upper2;
2556         int i;
2557
2558         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2559         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2560                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2561                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2562                 if (tsf_upper2 == tsf_upper1)
2563                         break;
2564                 tsf_upper1 = tsf_upper2;
2565         }
2566
2567         WARN_ON( i == ATH9K_MAX_TSF_READ );
2568
2569         return (((u64)tsf_upper1 << 32) | tsf_lower);
2570 }
2571 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2572
2573 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2574 {
2575         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2576         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2577 }
2578 EXPORT_SYMBOL(ath9k_hw_settsf64);
2579
2580 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2581 {
2582         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2583                            AH_TSF_WRITE_TIMEOUT))
2584                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2585                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2586
2587         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2588 }
2589 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2590
2591 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2592 {
2593         if (setting)
2594                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2595         else
2596                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2597 }
2598 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2599
2600 /*
2601  *  Extend 15-bit time stamp from rx descriptor to
2602  *  a full 64-bit TSF using the current h/w TSF.
2603 */
2604 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2605 {
2606         u64 tsf;
2607
2608         tsf = ath9k_hw_gettsf64(ah);
2609         if ((tsf & 0x7fff) < rstamp)
2610                 tsf -= 0x8000;
2611         return (tsf & ~0x7fff) | rstamp;
2612 }
2613 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2614
2615 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2616 {
2617         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2618         u32 macmode;
2619
2620         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2621                 macmode = AR_2040_JOINED_RX_CLEAR;
2622         else
2623                 macmode = 0;
2624
2625         REG_WRITE(ah, AR_2040_MODE, macmode);
2626 }
2627
2628 /* HW Generic timers configuration */
2629
2630 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2631 {
2632         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2633         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2634         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2635         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2636         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2637         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2638         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2639         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2640         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2641         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2642                                 AR_NDP2_TIMER_MODE, 0x0002},
2643         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2644                                 AR_NDP2_TIMER_MODE, 0x0004},
2645         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2646                                 AR_NDP2_TIMER_MODE, 0x0008},
2647         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2648                                 AR_NDP2_TIMER_MODE, 0x0010},
2649         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2650                                 AR_NDP2_TIMER_MODE, 0x0020},
2651         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2652                                 AR_NDP2_TIMER_MODE, 0x0040},
2653         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2654                                 AR_NDP2_TIMER_MODE, 0x0080}
2655 };
2656
2657 /* HW generic timer primitives */
2658
2659 /* compute and clear index of rightmost 1 */
2660 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2661 {
2662         u32 b;
2663
2664         b = *mask;
2665         b &= (0-b);
2666         *mask &= ~b;
2667         b *= debruijn32;
2668         b >>= 27;
2669
2670         return timer_table->gen_timer_index[b];
2671 }
2672
2673 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2674 {
2675         return REG_READ(ah, AR_TSF_L32);
2676 }
2677 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2678
2679 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2680                                           void (*trigger)(void *),
2681                                           void (*overflow)(void *),
2682                                           void *arg,
2683                                           u8 timer_index)
2684 {
2685         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2686         struct ath_gen_timer *timer;
2687
2688         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2689
2690         if (timer == NULL) {
2691                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2692                           "Failed to allocate memory"
2693                           "for hw timer[%d]\n", timer_index);
2694                 return NULL;
2695         }
2696
2697         /* allocate a hardware generic timer slot */
2698         timer_table->timers[timer_index] = timer;
2699         timer->index = timer_index;
2700         timer->trigger = trigger;
2701         timer->overflow = overflow;
2702         timer->arg = arg;
2703
2704         return timer;
2705 }
2706 EXPORT_SYMBOL(ath_gen_timer_alloc);
2707
2708 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2709                               struct ath_gen_timer *timer,
2710                               u32 timer_next,
2711                               u32 timer_period)
2712 {
2713         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2714         u32 tsf;
2715
2716         BUG_ON(!timer_period);
2717
2718         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2719
2720         tsf = ath9k_hw_gettsf32(ah);
2721
2722         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2723                   "curent tsf %x period %x"
2724                   "timer_next %x\n", tsf, timer_period, timer_next);
2725
2726         /*
2727          * Pull timer_next forward if the current TSF already passed it
2728          * because of software latency
2729          */
2730         if (timer_next < tsf)
2731                 timer_next = tsf + timer_period;
2732
2733         /*
2734          * Program generic timer registers
2735          */
2736         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2737                  timer_next);
2738         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2739                   timer_period);
2740         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2741                     gen_tmr_configuration[timer->index].mode_mask);
2742
2743         /* Enable both trigger and thresh interrupt masks */
2744         REG_SET_BIT(ah, AR_IMR_S5,
2745                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2746                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2747 }
2748 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2749
2750 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2751 {
2752         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2753
2754         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2755                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2756                 return;
2757         }
2758
2759         /* Clear generic timer enable bits. */
2760         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2761                         gen_tmr_configuration[timer->index].mode_mask);
2762
2763         /* Disable both trigger and thresh interrupt masks */
2764         REG_CLR_BIT(ah, AR_IMR_S5,
2765                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2766                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2767
2768         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2769 }
2770 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2771
2772 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2773 {
2774         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2775
2776         /* free the hardware generic timer slot */
2777         timer_table->timers[timer->index] = NULL;
2778         kfree(timer);
2779 }
2780 EXPORT_SYMBOL(ath_gen_timer_free);
2781
2782 /*
2783  * Generic Timer Interrupts handling
2784  */
2785 void ath_gen_timer_isr(struct ath_hw *ah)
2786 {
2787         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2788         struct ath_gen_timer *timer;
2789         struct ath_common *common = ath9k_hw_common(ah);
2790         u32 trigger_mask, thresh_mask, index;
2791
2792         /* get hardware generic timer interrupt status */
2793         trigger_mask = ah->intr_gen_timer_trigger;
2794         thresh_mask = ah->intr_gen_timer_thresh;
2795         trigger_mask &= timer_table->timer_mask.val;
2796         thresh_mask &= timer_table->timer_mask.val;
2797
2798         trigger_mask &= ~thresh_mask;
2799
2800         while (thresh_mask) {
2801                 index = rightmost_index(timer_table, &thresh_mask);
2802                 timer = timer_table->timers[index];
2803                 BUG_ON(!timer);
2804                 ath_print(common, ATH_DBG_HWTIMER,
2805                           "TSF overflow for Gen timer %d\n", index);
2806                 timer->overflow(timer->arg);
2807         }
2808
2809         while (trigger_mask) {
2810                 index = rightmost_index(timer_table, &trigger_mask);
2811                 timer = timer_table->timers[index];
2812                 BUG_ON(!timer);
2813                 ath_print(common, ATH_DBG_HWTIMER,
2814                           "Gen timer[%d] trigger\n", index);
2815                 timer->trigger(timer->arg);
2816         }
2817 }
2818 EXPORT_SYMBOL(ath_gen_timer_isr);
2819
2820 /********/
2821 /* HTC  */
2822 /********/
2823
2824 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2825 {
2826         ah->htc_reset_init = true;
2827 }
2828 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2829
2830 static struct {
2831         u32 version;
2832         const char * name;
2833 } ath_mac_bb_names[] = {
2834         /* Devices with external radios */
2835         { AR_SREV_VERSION_5416_PCI,     "5416" },
2836         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2837         { AR_SREV_VERSION_9100,         "9100" },
2838         { AR_SREV_VERSION_9160,         "9160" },
2839         /* Single-chip solutions */
2840         { AR_SREV_VERSION_9280,         "9280" },
2841         { AR_SREV_VERSION_9285,         "9285" },
2842         { AR_SREV_VERSION_9287,         "9287" },
2843         { AR_SREV_VERSION_9271,         "9271" },
2844         { AR_SREV_VERSION_9300,         "9300" },
2845 };
2846
2847 /* For devices with external radios */
2848 static struct {
2849         u16 version;
2850         const char * name;
2851 } ath_rf_names[] = {
2852         { 0,                            "5133" },
2853         { AR_RAD5133_SREV_MAJOR,        "5133" },
2854         { AR_RAD5122_SREV_MAJOR,        "5122" },
2855         { AR_RAD2133_SREV_MAJOR,        "2133" },
2856         { AR_RAD2122_SREV_MAJOR,        "2122" }
2857 };
2858
2859 /*
2860  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2861  */
2862 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2863 {
2864         int i;
2865
2866         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2867                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2868                         return ath_mac_bb_names[i].name;
2869                 }
2870         }
2871
2872         return "????";
2873 }
2874
2875 /*
2876  * Return the RF name. "????" is returned if the RF is unknown.
2877  * Used for devices with external radios.
2878  */
2879 static const char *ath9k_hw_rf_name(u16 rf_version)
2880 {
2881         int i;
2882
2883         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2884                 if (ath_rf_names[i].version == rf_version) {
2885                         return ath_rf_names[i].name;
2886                 }
2887         }
2888
2889         return "????";
2890 }
2891
2892 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2893 {
2894         int used;
2895
2896         /* chipsets >= AR9280 are single-chip */
2897         if (AR_SREV_9280_10_OR_LATER(ah)) {
2898                 used = snprintf(hw_name, len,
2899                                "Atheros AR%s Rev:%x",
2900                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2901                                ah->hw_version.macRev);
2902         }
2903         else {
2904                 used = snprintf(hw_name, len,
2905                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2906                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2907                                ah->hw_version.macRev,
2908                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2909                                                 AR_RADIO_SREV_MAJOR)),
2910                                ah->hw_version.phyRev);
2911         }
2912
2913         hw_name[used] = '\0';
2914 }
2915 EXPORT_SYMBOL(ath9k_hw_name);