2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
23 #include <linux/firmware.h>
36 #define ATHEROS_VENDOR_ID 0x168c
38 #define AR5416_DEVID_PCI 0x0023
39 #define AR5416_DEVID_PCIE 0x0024
40 #define AR9160_DEVID_PCI 0x0027
41 #define AR9280_DEVID_PCI 0x0029
42 #define AR9280_DEVID_PCIE 0x002a
43 #define AR9285_DEVID_PCIE 0x002b
44 #define AR2427_DEVID_PCIE 0x002c
45 #define AR9287_DEVID_PCI 0x002d
46 #define AR9287_DEVID_PCIE 0x002e
47 #define AR9300_DEVID_PCIE 0x0030
48 #define AR9300_DEVID_AR9340 0x0031
49 #define AR9300_DEVID_AR9485_PCIE 0x0032
50 #define AR9300_DEVID_AR9580 0x0033
51 #define AR9300_DEVID_AR9462 0x0034
52 #define AR9300_DEVID_AR9330 0x0035
53 #define AR9300_DEVID_QCA955X 0x0038
54 #define AR9485_DEVID_AR1111 0x0037
55 #define AR9300_DEVID_AR9565 0x0036
56 #define AR9300_DEVID_AR953X 0x003d
58 #define AR5416_AR9100_DEVID 0x000b
60 #define AR_SUBVENDOR_ID_NOG 0x0e11
61 #define AR_SUBVENDOR_ID_NEW_A 0x7065
62 #define AR5416_MAGIC 0x19641014
64 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
65 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
66 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
68 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
70 #define ATH_DEFAULT_NOISE_FLOOR -95
72 #define ATH9K_RSSI_BAD -128
74 #define ATH9K_NUM_CHANNELS 38
76 /* Register read/write primitives */
77 #define REG_WRITE(_ah, _reg, _val) \
78 (_ah)->reg_ops.write((_ah), (_val), (_reg))
80 #define REG_READ(_ah, _reg) \
81 (_ah)->reg_ops.read((_ah), (_reg))
83 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
84 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
86 #define REG_RMW(_ah, _reg, _set, _clr) \
87 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
89 #define ENABLE_REGWRITE_BUFFER(_ah) \
91 if ((_ah)->reg_ops.enable_write_buffer) \
92 (_ah)->reg_ops.enable_write_buffer((_ah)); \
95 #define REGWRITE_BUFFER_FLUSH(_ah) \
97 if ((_ah)->reg_ops.write_flush) \
98 (_ah)->reg_ops.write_flush((_ah)); \
101 #define PR_EEP(_s, _val) \
103 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
107 #define SM(_v, _f) (((_v) << _f##_S) & _f)
108 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
109 #define REG_RMW_FIELD(_a, _r, _f, _v) \
110 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
111 #define REG_READ_FIELD(_a, _r, _f) \
112 (((REG_READ(_a, _r) & _f) >> _f##_S))
113 #define REG_SET_BIT(_a, _r, _f) \
114 REG_RMW(_a, _r, (_f), 0)
115 #define REG_CLR_BIT(_a, _r, _f) \
116 REG_RMW(_a, _r, 0, (_f))
118 #define DO_DELAY(x) do { \
119 if (((++(x) % 64) == 0) && \
120 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
125 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
126 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
128 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
129 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
130 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
131 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
132 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
133 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
134 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
137 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
138 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
139 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
140 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
141 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
142 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
143 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
144 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
146 #define AR_GPIOD_MASK 0x00001FFF
147 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
149 #define BASE_ACTIVATE_DELAY 100
150 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
151 #define COEF_SCALE_S 24
152 #define HT40_CHANNEL_CENTER_SHIFT 10
154 #define ATH9K_ANTENNA0_CHAINMASK 0x1
155 #define ATH9K_ANTENNA1_CHAINMASK 0x2
157 #define ATH9K_NUM_DMA_DEBUG_REGS 8
158 #define ATH9K_NUM_QUEUES 10
160 #define MAX_RATE_POWER 63
161 #define AH_WAIT_TIMEOUT 100000 /* (us) */
162 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
163 #define AH_TIME_QUANTUM 10
164 #define AR_KEYTABLE_SIZE 128
165 #define POWER_UP_TIME 10000
166 #define SPUR_RSSI_THRESH 40
167 #define UPPER_5G_SUB_BAND_START 5700
168 #define MID_5G_SUB_BAND_START 5400
170 #define CAB_TIMEOUT_VAL 10
171 #define BEACON_TIMEOUT_VAL 10
172 #define MIN_BEACON_TIMEOUT_VAL 1
173 #define SLEEP_SLOP TU_TO_USEC(3)
175 #define INIT_CONFIG_STATUS 0x00000000
176 #define INIT_RSSI_THR 0x00000700
177 #define INIT_BCON_CNTRL_REG 0x00000000
179 #define TU_TO_USEC(_tu) ((_tu) << 10)
181 #define ATH9K_HW_RX_HP_QDEPTH 16
182 #define ATH9K_HW_RX_LP_QDEPTH 128
184 #define PAPRD_GAIN_TABLE_ENTRIES 32
185 #define PAPRD_TABLE_SZ 24
186 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
192 /* Keep Alive Frame */
193 #define KAL_FRAME_LEN 28
194 #define KAL_FRAME_TYPE 0x2 /* data frame */
195 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
196 #define KAL_DURATION_ID 0x3d
197 #define KAL_NUM_DATA_WORDS 6
198 #define KAL_NUM_DESC_WORDS 12
199 #define KAL_ANTENNA_MODE 1
201 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */
202 #define KAL_TIMEOUT 900
204 #define MAX_PATTERN_SIZE 256
205 #define MAX_PATTERN_MASK_SIZE 32
206 #define MAX_NUM_PATTERN 8
207 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
208 deauthenticate packets */
211 * WoW trigger mapping to hardware code
214 #define AH_WOW_USER_PATTERN_EN BIT(0)
215 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
216 #define AH_WOW_LINK_CHANGE BIT(2)
217 #define AH_WOW_BEACON_MISS BIT(3)
219 enum ath_hw_txq_subtype {
226 enum ath_ini_subsys {
234 ATH9K_HW_CAP_HT = BIT(0),
235 ATH9K_HW_CAP_RFSILENT = BIT(1),
236 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
237 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
238 ATH9K_HW_CAP_EDMA = BIT(4),
239 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
240 ATH9K_HW_CAP_LDPC = BIT(6),
241 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
242 ATH9K_HW_CAP_SGI_20 = BIT(8),
243 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
244 ATH9K_HW_CAP_2GHZ = BIT(11),
245 ATH9K_HW_CAP_5GHZ = BIT(12),
246 ATH9K_HW_CAP_APM = BIT(13),
247 #ifdef CONFIG_ATH9K_PCOEM
248 ATH9K_HW_CAP_RTT = BIT(14),
249 ATH9K_HW_CAP_MCI = BIT(15),
250 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(16),
251 ATH9K_HW_CAP_BT_ANT_DIV = BIT(17),
253 ATH9K_HW_CAP_RTT = 0,
254 ATH9K_HW_CAP_MCI = 0,
255 ATH9K_HW_WOW_DEVICE_CAPABLE = 0,
256 ATH9K_HW_CAP_BT_ANT_DIV = 0,
258 ATH9K_HW_CAP_DFS = BIT(18),
259 ATH9K_HW_CAP_PAPRD = BIT(19),
260 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20),
264 * WoW device capabilities
265 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
266 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
267 * an exact user defined pattern or de-authentication/disassoc pattern.
268 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
269 * bytes of the pattern for user defined pattern, de-authentication and
270 * disassociation patterns for all types of possible frames recieved
274 struct ath9k_hw_capabilities {
275 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
290 #define AR_NO_SPUR 0x8000
291 #define AR_BASE_FREQ_2GHZ 2300
292 #define AR_BASE_FREQ_5GHZ 4900
293 #define AR_SPUR_FEEQ_BOUND_HT40 19
294 #define AR_SPUR_FEEQ_BOUND_HT20 10
296 enum ath9k_hw_hang_checks {
297 HW_BB_WATCHDOG = BIT(0),
298 HW_PHYRESTART_CLC_WAR = BIT(1),
299 HW_BB_RIFS_HANG = BIT(2),
300 HW_BB_DFS_HANG = BIT(3),
301 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4),
302 HW_MAC_HANG = BIT(5),
305 struct ath9k_ops_config {
306 int dma_beacon_response_time;
307 int sw_beacon_response_time;
308 u32 cwm_ignore_extcca;
316 int serialize_regmode;
317 bool rx_intr_mitigation;
318 bool tx_intr_mitigation;
320 u16 ani_poll_interval; /* ANI poll interval in ms */
325 /* Platform specific config */
328 u32 ant_ctrl_comm2g_switch_enable;
329 bool xatten_margin_cfg;
332 bool tx_gain_buffalo;
333 bool led_active_high;
337 ATH9K_INT_RX = 0x00000001,
338 ATH9K_INT_RXDESC = 0x00000002,
339 ATH9K_INT_RXHP = 0x00000001,
340 ATH9K_INT_RXLP = 0x00000002,
341 ATH9K_INT_RXNOFRM = 0x00000008,
342 ATH9K_INT_RXEOL = 0x00000010,
343 ATH9K_INT_RXORN = 0x00000020,
344 ATH9K_INT_TX = 0x00000040,
345 ATH9K_INT_TXDESC = 0x00000080,
346 ATH9K_INT_TIM_TIMER = 0x00000100,
347 ATH9K_INT_MCI = 0x00000200,
348 ATH9K_INT_BB_WATCHDOG = 0x00000400,
349 ATH9K_INT_TXURN = 0x00000800,
350 ATH9K_INT_MIB = 0x00001000,
351 ATH9K_INT_RXPHY = 0x00004000,
352 ATH9K_INT_RXKCM = 0x00008000,
353 ATH9K_INT_SWBA = 0x00010000,
354 ATH9K_INT_BMISS = 0x00040000,
355 ATH9K_INT_BNR = 0x00100000,
356 ATH9K_INT_TIM = 0x00200000,
357 ATH9K_INT_DTIM = 0x00400000,
358 ATH9K_INT_DTIMSYNC = 0x00800000,
359 ATH9K_INT_GPIO = 0x01000000,
360 ATH9K_INT_CABEND = 0x02000000,
361 ATH9K_INT_TSFOOR = 0x04000000,
362 ATH9K_INT_GENTIMER = 0x08000000,
363 ATH9K_INT_CST = 0x10000000,
364 ATH9K_INT_GTT = 0x20000000,
365 ATH9K_INT_FATAL = 0x40000000,
366 ATH9K_INT_GLOBAL = 0x80000000,
367 ATH9K_INT_BMISC = ATH9K_INT_TIM |
372 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
384 ATH9K_INT_NOCARD = 0xffffffff
387 #define MAX_RTT_TABLE_ENTRY 6
388 #define MAX_IQCAL_MEASUREMENT 8
389 #define MAX_CL_TAB_ENTRY 16
390 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
392 enum ath9k_cal_flags {
403 struct ath9k_hw_cal_data {
406 unsigned long cal_flags;
411 u16 small_signal_gain[AR9300_MAX_CHAINS];
412 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
413 u32 num_measures[AR9300_MAX_CHAINS];
414 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
415 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
416 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
417 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
420 struct ath9k_channel {
421 struct ieee80211_channel *chan;
427 #define CHANNEL_5GHZ BIT(0)
428 #define CHANNEL_HALF BIT(1)
429 #define CHANNEL_QUARTER BIT(2)
430 #define CHANNEL_HT BIT(3)
431 #define CHANNEL_HT40PLUS BIT(4)
432 #define CHANNEL_HT40MINUS BIT(5)
434 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
435 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
437 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
438 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
439 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
440 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
442 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
444 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
446 #define IS_CHAN_HT40(_c) \
447 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
449 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
450 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
452 enum ath9k_power_mode {
455 ATH9K_PM_NETWORK_SLEEP,
460 SER_REG_MODE_OFF = 0,
462 SER_REG_MODE_AUTO = 2,
465 enum ath9k_rx_qtype {
471 struct ath9k_beacon_state {
475 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
477 u16 bs_bmissthreshold;
478 u32 bs_sleepduration;
479 u32 bs_tsfoor_threshold;
482 struct chan_centers {
489 ATH9K_RESET_POWER_ON,
494 struct ath9k_hw_version {
503 enum ath_usb_dev usbdev;
506 /* Generic TSF timer definitions */
508 #define ATH_MAX_GEN_TIMER 16
510 #define AR_GENTMR_BIT(_index) (1 << (_index))
512 struct ath_gen_timer_configuration {
519 struct ath_gen_timer {
520 void (*trigger)(void *arg);
521 void (*overflow)(void *arg);
526 struct ath_gen_timer_table {
527 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
532 struct ath_hw_antcomb_conf {
539 int lna1_lna2_switch_delta;
544 * struct ath_hw_radar_conf - radar detection initialization parameters
546 * @pulse_inband: threshold for checking the ratio of in-band power
547 * to total power for short radar pulses (half dB steps)
548 * @pulse_inband_step: threshold for checking an in-band power to total
549 * power ratio increase for short radar pulses (half dB steps)
550 * @pulse_height: threshold for detecting the beginning of a short
551 * radar pulse (dB step)
552 * @pulse_rssi: threshold for detecting if a short radar pulse is
554 * @pulse_maxlen: maximum pulse length (0.8 us steps)
556 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
557 * @radar_inband: threshold for checking the ratio of in-band power
558 * to total power for long radar pulses (half dB steps)
559 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
561 * @ext_channel: enable extension channel radar detection
563 struct ath_hw_radar_conf {
564 unsigned int pulse_inband;
565 unsigned int pulse_inband_step;
566 unsigned int pulse_height;
567 unsigned int pulse_rssi;
568 unsigned int pulse_maxlen;
570 unsigned int radar_rssi;
571 unsigned int radar_inband;
578 * struct ath_hw_private_ops - callbacks used internally by hardware code
580 * This structure contains private callbacks designed to only be used internally
581 * by the hardware core.
583 * @init_cal_settings: setup types of calibrations supported
584 * @init_cal: starts actual calibration
586 * @init_mode_gain_regs: Initialize TX/RX gain registers
588 * @rf_set_freq: change frequency
589 * @spur_mitigate_freq: spur mitigation
591 * @compute_pll_control: compute the PLL control value to use for
592 * AR_RTC_PLL_CONTROL for a given channel
593 * @setup_calibration: set up calibration
594 * @iscal_supported: used to query if a type of calibration is supported
596 * @ani_cache_ini_regs: cache the values for ANI from the initial
597 * register settings through the register initialization.
599 struct ath_hw_private_ops {
600 void (*init_hang_checks)(struct ath_hw *ah);
601 bool (*detect_mac_hang)(struct ath_hw *ah);
602 bool (*detect_bb_hang)(struct ath_hw *ah);
604 /* Calibration ops */
605 void (*init_cal_settings)(struct ath_hw *ah);
606 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
608 void (*init_mode_gain_regs)(struct ath_hw *ah);
609 void (*setup_calibration)(struct ath_hw *ah,
610 struct ath9k_cal_list *currCal);
613 int (*rf_set_freq)(struct ath_hw *ah,
614 struct ath9k_channel *chan);
615 void (*spur_mitigate_freq)(struct ath_hw *ah,
616 struct ath9k_channel *chan);
617 bool (*set_rf_regs)(struct ath_hw *ah,
618 struct ath9k_channel *chan,
620 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
621 void (*init_bb)(struct ath_hw *ah,
622 struct ath9k_channel *chan);
623 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
624 void (*olc_init)(struct ath_hw *ah);
625 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
626 void (*mark_phy_inactive)(struct ath_hw *ah);
627 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
628 bool (*rfbus_req)(struct ath_hw *ah);
629 void (*rfbus_done)(struct ath_hw *ah);
630 void (*restore_chainmask)(struct ath_hw *ah);
631 u32 (*compute_pll_control)(struct ath_hw *ah,
632 struct ath9k_channel *chan);
633 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
635 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
636 void (*set_radar_params)(struct ath_hw *ah,
637 struct ath_hw_radar_conf *conf);
638 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
642 void (*ani_cache_ini_regs)(struct ath_hw *ah);
646 * struct ath_spec_scan - parameters for Atheros spectral scan
648 * @enabled: enable/disable spectral scan
649 * @short_repeat: controls whether the chip is in spectral scan mode
650 * for 4 usec (enabled) or 204 usec (disabled)
651 * @count: number of scan results requested. There are special meanings
652 * in some chip revisions:
653 * AR92xx: highest bit set (>=128) for endless mode
654 * (spectral scan won't stopped until explicitly disabled)
655 * AR9300 and newer: 0 for endless mode
656 * @endless: true if endless mode is intended. Otherwise, count value is
657 * corrected to the next possible value.
658 * @period: time duration between successive spectral scan entry points
659 * (period*256*Tclk). Tclk = ath_common->clockrate
660 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
662 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
663 * Typically it's 44MHz in 2/5GHz on later chips, but there's
664 * a "fast clock" check for this in 5GHz.
667 struct ath_spec_scan {
677 * struct ath_hw_ops - callbacks used by hardware code and driver code
679 * This structure contains callbacks designed to to be used internally by
680 * hardware code and also by the lower level driver.
682 * @config_pci_powersave:
683 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
685 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
686 * @spectral_scan_trigger: trigger a spectral scan run
687 * @spectral_scan_wait: wait for a spectral scan run to finish
690 void (*config_pci_powersave)(struct ath_hw *ah,
692 void (*rx_enable)(struct ath_hw *ah);
693 void (*set_desc_link)(void *ds, u32 link);
694 int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan,
695 u8 rxchainmask, bool longcal);
696 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
698 void (*set_txdesc)(struct ath_hw *ah, void *ds,
699 struct ath_tx_info *i);
700 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
701 struct ath_tx_status *ts);
702 int (*get_duration)(struct ath_hw *ah, const void *ds, int index);
703 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
704 struct ath_hw_antcomb_conf *antconf);
705 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
706 struct ath_hw_antcomb_conf *antconf);
707 void (*spectral_scan_config)(struct ath_hw *ah,
708 struct ath_spec_scan *param);
709 void (*spectral_scan_trigger)(struct ath_hw *ah);
710 void (*spectral_scan_wait)(struct ath_hw *ah);
712 void (*tx99_start)(struct ath_hw *ah, u32 qnum);
713 void (*tx99_stop)(struct ath_hw *ah);
714 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
716 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
717 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
721 struct ath_nf_limits {
729 TX_IQ_ON_AGC_CAL = BIT(1),
734 #define AH_USE_EEPROM 0x1
735 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
736 #define AH_FASTCC 0x4
737 #define AH_NO_EEP_SWAP 0x8 /* Do not swap EEPROM data */
740 struct ath_ops reg_ops;
743 struct ieee80211_hw *hw;
744 struct ath_common common;
745 struct ath9k_hw_version hw_version;
746 struct ath9k_ops_config config;
747 struct ath9k_hw_capabilities caps;
748 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
749 struct ath9k_channel *curchan;
752 struct ar5416_eeprom_def def;
753 struct ar5416_eeprom_4k map4k;
754 struct ar9287_eeprom map9287;
755 struct ar9300_eeprom ar9300_eep;
757 const struct eeprom_ops *eep_ops;
759 bool sw_mgmt_crypto_tx;
760 bool sw_mgmt_crypto_rx;
764 bool need_an_top2_fixup;
768 struct ath_nf_limits nf_2g;
769 struct ath_nf_limits nf_5g;
778 enum nl80211_iftype opmode;
779 enum ath9k_power_mode power_mode;
782 struct ath9k_hw_cal_data *caldata;
783 struct ath9k_pacal_info pacal_info;
784 struct ar5416Stats stats;
785 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
787 enum ath9k_int imask;
789 u32 txok_interrupt_mask;
790 u32 txerr_interrupt_mask;
791 u32 txdesc_interrupt_mask;
792 u32 txeol_interrupt_mask;
793 u32 txurn_interrupt_mask;
794 atomic_t intr_ref_cnt;
800 struct ath9k_cal_list iq_caldata;
801 struct ath9k_cal_list adcgain_caldata;
802 struct ath9k_cal_list adcdc_caldata;
803 struct ath9k_cal_list *cal_list;
804 struct ath9k_cal_list *cal_list_last;
805 struct ath9k_cal_list *cal_list_curr;
806 #define totalPowerMeasI meas0.unsign
807 #define totalPowerMeasQ meas1.unsign
808 #define totalIqCorrMeas meas2.sign
809 #define totalAdcIOddPhase meas0.unsign
810 #define totalAdcIEvenPhase meas1.unsign
811 #define totalAdcQOddPhase meas2.unsign
812 #define totalAdcQEvenPhase meas3.unsign
813 #define totalAdcDcOffsetIOddPhase meas0.sign
814 #define totalAdcDcOffsetIEvenPhase meas1.sign
815 #define totalAdcDcOffsetQOddPhase meas2.sign
816 #define totalAdcDcOffsetQEvenPhase meas3.sign
818 u32 unsign[AR5416_MAX_CHAINS];
819 int32_t sign[AR5416_MAX_CHAINS];
822 u32 unsign[AR5416_MAX_CHAINS];
823 int32_t sign[AR5416_MAX_CHAINS];
826 u32 unsign[AR5416_MAX_CHAINS];
827 int32_t sign[AR5416_MAX_CHAINS];
830 u32 unsign[AR5416_MAX_CHAINS];
831 int32_t sign[AR5416_MAX_CHAINS];
836 u32 sta_id1_defaults;
839 /* Private to hardware code */
840 struct ath_hw_private_ops private_ops;
841 /* Accessed by the lower level driver */
842 struct ath_hw_ops ops;
844 /* Used to program the radio on non single-chip devices */
845 u32 *analogBank6Data;
853 enum ath9k_ani_cmd ani_function;
855 struct ar5416AniState ani;
857 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
858 struct ath_btcoex_hw btcoex_hw;
865 struct ath_hw_radar_conf radar_conf;
867 u32 originalGain[22];
874 struct ar5416IniArray ini_dfs;
875 struct ar5416IniArray iniModes;
876 struct ar5416IniArray iniCommon;
877 struct ar5416IniArray iniBB_RfGain;
878 struct ar5416IniArray iniBank6;
879 struct ar5416IniArray iniAddac;
880 struct ar5416IniArray iniPcieSerdes;
881 struct ar5416IniArray iniPcieSerdesLowPower;
882 struct ar5416IniArray iniModesFastClock;
883 struct ar5416IniArray iniAdditional;
884 struct ar5416IniArray iniModesRxGain;
885 struct ar5416IniArray ini_modes_rx_gain_bounds;
886 struct ar5416IniArray iniModesTxGain;
887 struct ar5416IniArray iniCckfirNormal;
888 struct ar5416IniArray iniCckfirJapan2484;
889 struct ar5416IniArray iniModes_9271_ANI_reg;
890 struct ar5416IniArray ini_radio_post_sys2ant;
891 struct ar5416IniArray ini_modes_rxgain_5g_xlna;
892 struct ar5416IniArray ini_modes_rxgain_bb_core;
893 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
895 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
896 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
897 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
898 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
900 u32 intr_gen_timer_trigger;
901 u32 intr_gen_timer_thresh;
902 struct ath_gen_timer_table hw_gen_timers;
904 struct ar9003_txs *ts_ring;
910 u32 bb_watchdog_last_status;
911 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
912 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
914 unsigned int paprd_target_power;
915 unsigned int paprd_training_power;
916 unsigned int paprd_ratemask;
917 unsigned int paprd_ratemask_ht40;
918 bool paprd_table_write_done;
919 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
920 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
922 * Store the permanent value of Reg 0x4004in WARegVal
923 * so we dont have to R/M/W. We should not be reading
924 * this register when in sleep states.
928 /* Enterprise mode cap */
931 #ifdef CONFIG_ATH9K_WOW
935 int (*get_mac_revision)(void);
936 int (*external_reset)(void);
940 const struct firmware *eeprom_blob;
942 struct ath_dynack dynack;
946 enum ath_bus_type ath_bus_type;
947 void (*read_cachesize)(struct ath_common *common, int *csz);
948 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
949 void (*bt_coex_prep)(struct ath_common *common);
950 void (*aspm_init)(struct ath_common *common);
953 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
958 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
960 return &(ath9k_hw_common(ah)->regulatory);
963 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
965 return &ah->private_ops;
968 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
973 static inline u8 get_streams(int mask)
975 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
978 /* Initialization, Detach, Reset */
979 void ath9k_hw_deinit(struct ath_hw *ah);
980 int ath9k_hw_init(struct ath_hw *ah);
981 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
982 struct ath9k_hw_cal_data *caldata, bool fastcc);
983 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
984 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
986 /* GPIO / RFKILL / Antennae */
987 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
988 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
989 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
991 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
992 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
994 /* General Operation */
995 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
997 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
998 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
999 int column, unsigned int *writecnt);
1000 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1001 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1003 u32 frameLen, u16 rateix, bool shortPreamble);
1004 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1005 struct ath9k_channel *chan,
1006 struct chan_centers *centers);
1007 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1008 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1009 bool ath9k_hw_phy_disable(struct ath_hw *ah);
1010 bool ath9k_hw_disable(struct ath_hw *ah);
1011 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1012 void ath9k_hw_setopmode(struct ath_hw *ah);
1013 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1014 void ath9k_hw_write_associd(struct ath_hw *ah);
1015 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1016 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1017 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1018 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1019 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur);
1020 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1021 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1022 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1023 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
1024 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1025 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1026 const struct ath9k_beacon_state *bs);
1027 void ath9k_hw_check_nav(struct ath_hw *ah);
1028 bool ath9k_hw_check_alive(struct ath_hw *ah);
1030 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1032 /* Generic hw timer primitives */
1033 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1034 void (*trigger)(void *),
1035 void (*overflow)(void *),
1038 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1039 struct ath_gen_timer *timer,
1042 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah);
1043 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1045 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1046 void ath_gen_timer_isr(struct ath_hw *hw);
1048 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1051 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1052 u32 *coef_mantissa, u32 *coef_exponent);
1053 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1057 * Code Specific to AR5008, AR9001 or AR9002,
1058 * we stuff these here to avoid callbacks for AR9003.
1060 int ar9002_hw_rf_claim(struct ath_hw *ah);
1061 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1064 * Code specific to AR9003, we stuff these here to avoid callbacks
1065 * for older families
1067 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah);
1068 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1069 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1070 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1071 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1072 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1073 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1074 struct ath9k_hw_cal_data *caldata,
1076 int ar9003_paprd_create_curve(struct ath_hw *ah,
1077 struct ath9k_hw_cal_data *caldata, int chain);
1078 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1079 int ar9003_paprd_init_table(struct ath_hw *ah);
1080 bool ar9003_paprd_is_done(struct ath_hw *ah);
1081 bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1082 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1084 /* Hardware family op attach helpers */
1085 int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1086 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1087 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1089 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1090 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1092 int ar9002_hw_attach_ops(struct ath_hw *ah);
1093 void ar9003_hw_attach_ops(struct ath_hw *ah);
1095 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1097 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1098 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1100 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us);
1101 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us);
1102 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
1104 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1105 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1107 return ah->btcoex_hw.enabled;
1109 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1111 return ah->common.btcoex_enabled &&
1112 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1115 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1116 static inline enum ath_btcoex_scheme
1117 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1119 return ah->btcoex_hw.scheme;
1122 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1126 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1130 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1133 static inline enum ath_btcoex_scheme
1134 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1136 return ATH_BTCOEX_CFG_NONE;
1138 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1141 #ifdef CONFIG_ATH9K_WOW
1142 const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1143 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1144 u8 *user_mask, int pattern_count,
1146 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1147 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1149 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event)
1153 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1160 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1164 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1169 #define ATH9K_CLOCK_RATE_CCK 22
1170 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1171 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1172 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44