2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/nl80211.h>
20 #include <linux/pci.h>
21 #include <linux/pci-aspm.h>
22 #include <linux/ath9k_platform.h>
23 #include <linux/module.h>
26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
30 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
31 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
32 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
33 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
34 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
36 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
39 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
43 .driver_data = ATH9K_PCI_CUS198 },
44 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
48 .driver_data = ATH9K_PCI_CUS198 },
49 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
53 .driver_data = ATH9K_PCI_CUS198 },
56 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
60 .driver_data = ATH9K_PCI_CUS230 },
61 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
63 PCI_VENDOR_ID_FOXCONN,
65 .driver_data = ATH9K_PCI_CUS230 },
67 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
68 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
69 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
70 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */
71 { PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E AR9565 */
76 /* return bus cachesize in 4B word units */
77 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
79 struct ath_softc *sc = (struct ath_softc *) common->priv;
82 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
86 * This check was put in to avoid "unpleasant" consequences if
87 * the bootrom has not fully initialized all PCI devices.
88 * Sometimes the cache line size register is not set
92 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
95 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
97 struct ath_softc *sc = (struct ath_softc *) common->priv;
98 struct ath9k_platform_data *pdata = sc->dev->platform_data;
101 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
103 "%s: eeprom read failed, offset %08x is out of range\n",
107 *data = pdata->eeprom_data[off];
109 struct ath_hw *ah = (struct ath_hw *) common->ah;
111 common->ops->read(ah, AR5416_EEPROM_OFFSET +
112 (off << AR5416_EEPROM_S));
114 if (!ath9k_hw_wait(ah,
115 AR_EEPROM_STATUS_DATA,
116 AR_EEPROM_STATUS_DATA_BUSY |
117 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
122 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
123 AR_EEPROM_STATUS_DATA_VAL);
129 /* Need to be called after we discover btcoex capabilities */
130 static void ath_pci_aspm_init(struct ath_common *common)
132 struct ath_softc *sc = (struct ath_softc *) common->priv;
133 struct ath_hw *ah = sc->sc_ah;
134 struct pci_dev *pdev = to_pci_dev(sc->dev);
135 struct pci_dev *parent;
138 if (!ah->is_pciexpress)
141 parent = pdev->bus->self;
145 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
146 (AR_SREV_9285(ah))) {
147 /* Bluetooth coexistence requires disabling ASPM. */
148 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
149 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
152 * Both upstream and downstream PCIe components should
153 * have the same ASPM settings.
155 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
156 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
158 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
162 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
163 if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
164 ah->aspm_enabled = true;
165 /* Initialize PCIe PM and SERDES registers. */
166 ath9k_hw_configpcipowersave(ah, false);
167 ath_info(common, "ASPM enabled: 0x%x\n", aspm);
171 static const struct ath_bus_ops ath_pci_bus_ops = {
172 .ath_bus_type = ATH_PCI,
173 .read_cachesize = ath_pci_read_cachesize,
174 .eeprom_read = ath_pci_eeprom_read,
175 .aspm_init = ath_pci_aspm_init,
178 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
180 struct ath_softc *sc;
181 struct ieee80211_hw *hw;
187 if (pcim_enable_device(pdev))
190 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
192 pr_err("32-bit DMA not available\n");
196 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
198 pr_err("32-bit DMA consistent DMA enable failed\n");
203 * Cache line size is used to size and align various
204 * structures used to communicate with the hardware.
206 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
209 * Linux 2.4.18 (at least) writes the cache line size
210 * register as a 16-bit wide register which is wrong.
211 * We must have this setup properly for rx buffer
212 * DMA to work so force a reasonable value here if it
215 csz = L1_CACHE_BYTES / sizeof(u32);
216 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
219 * The default setting of latency timer yields poor results,
220 * set it to the value used by other systems. It may be worth
221 * tweaking this setting more.
223 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
225 pci_set_master(pdev);
228 * Disable the RETRY_TIMEOUT register (0x41) to keep
229 * PCI Tx retries from interfering with C3 CPU state.
231 pci_read_config_dword(pdev, 0x40, &val);
232 if ((val & 0x0000ff00) != 0)
233 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
235 ret = pcim_iomap_regions(pdev, BIT(0), "ath9k");
237 dev_err(&pdev->dev, "PCI memory region reserve error\n");
241 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
243 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
247 SET_IEEE80211_DEV(hw, &pdev->dev);
248 pci_set_drvdata(pdev, hw);
252 sc->dev = &pdev->dev;
253 sc->mem = pcim_iomap_table(pdev)[0];
254 sc->driver_data = id->driver_data;
256 /* Will be cleared in ath9k_start() */
257 set_bit(SC_OP_INVALID, &sc->sc_flags);
259 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
261 dev_err(&pdev->dev, "request_irq failed\n");
267 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
269 dev_err(&pdev->dev, "Failed to initialize device\n");
273 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
274 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
275 hw_name, (unsigned long)sc->mem, pdev->irq);
280 free_irq(sc->irq, sc);
282 ieee80211_free_hw(hw);
286 static void ath_pci_remove(struct pci_dev *pdev)
288 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
289 struct ath_softc *sc = hw->priv;
291 if (!is_ath9k_unloaded)
292 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
293 ath9k_deinit_device(sc);
294 free_irq(sc->irq, sc);
295 ieee80211_free_hw(sc->hw);
298 #ifdef CONFIG_PM_SLEEP
300 static int ath_pci_suspend(struct device *device)
302 struct pci_dev *pdev = to_pci_dev(device);
303 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
304 struct ath_softc *sc = hw->priv;
309 /* The device has to be moved to FULLSLEEP forcibly.
310 * Otherwise the chip never moved to full sleep,
311 * when no interface is up.
313 ath9k_stop_btcoex(sc);
314 ath9k_hw_disable(sc->sc_ah);
315 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
320 static int ath_pci_resume(struct device *device)
322 struct pci_dev *pdev = to_pci_dev(device);
323 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
324 struct ath_softc *sc = hw->priv;
325 struct ath_hw *ah = sc->sc_ah;
326 struct ath_common *common = ath9k_hw_common(ah);
330 * Suspend/Resume resets the PCI configuration space, so we have to
331 * re-disable the RETRY_TIMEOUT register (0x41) to keep
332 * PCI Tx retries from interfering with C3 CPU state
334 pci_read_config_dword(pdev, 0x40, &val);
335 if ((val & 0x0000ff00) != 0)
336 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
338 ath_pci_aspm_init(common);
339 ah->reset_power_on = false;
344 static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume);
346 #define ATH9K_PM_OPS (&ath9k_pm_ops)
348 #else /* !CONFIG_PM_SLEEP */
350 #define ATH9K_PM_OPS NULL
352 #endif /* !CONFIG_PM_SLEEP */
355 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
357 static struct pci_driver ath_pci_driver = {
359 .id_table = ath_pci_id_table,
360 .probe = ath_pci_probe,
361 .remove = ath_pci_remove,
362 .driver.pm = ATH9K_PM_OPS,
365 int ath_pci_init(void)
367 return pci_register_driver(&ath_pci_driver);
370 void ath_pci_exit(void)
372 pci_unregister_driver(&ath_pci_driver);