2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
76 /*********************/
77 /* Aggregation logic */
78 /*********************/
80 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
81 __acquires(&txq->axq_lock)
83 spin_lock_bh(&txq->axq_lock);
86 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
87 __releases(&txq->axq_lock)
89 spin_unlock_bh(&txq->axq_lock);
92 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
93 __releases(&txq->axq_lock)
95 struct sk_buff_head q;
98 __skb_queue_head_init(&q);
99 skb_queue_splice_init(&txq->complete_q, &q);
100 spin_unlock_bh(&txq->axq_lock);
102 while ((skb = __skb_dequeue(&q)))
103 ieee80211_tx_status(sc->hw, skb);
106 static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq,
107 struct ath_atx_tid *tid)
109 struct ath_atx_ac *ac = tid->ac;
110 struct list_head *list;
111 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
112 struct ath_chanctx *ctx = avp->chanctx;
121 list_add_tail(&tid->list, &ac->tid_q);
128 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
129 list_add_tail(&ac->list, list);
132 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
134 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
135 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
136 sizeof(tx_info->rate_driver_data));
137 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
140 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
145 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
146 seqno << IEEE80211_SEQ_SEQ_SHIFT);
149 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
152 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
153 ARRAY_SIZE(bf->rates));
156 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
159 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
160 struct ath_frame_info *fi = get_frame_info(skb);
166 txq = sc->tx.txq_map[q];
167 if (WARN_ON(--txq->pending_frames < 0))
168 txq->pending_frames = 0;
171 txq->pending_frames < sc->tx.txq_max_pending[q]) {
172 if (ath9k_is_chanctx_enabled())
173 ieee80211_wake_queue(sc->hw, info->hw_queue);
175 ieee80211_wake_queue(sc->hw, q);
176 txq->stopped = false;
180 static struct ath_atx_tid *
181 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
183 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
184 return ATH_AN_2_TID(an, tidno);
187 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
189 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
192 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
196 skb = __skb_dequeue(&tid->retry_q);
198 skb = __skb_dequeue(&tid->buf_q);
204 * ath_tx_tid_change_state:
205 * - clears a-mpdu flag of previous session
206 * - force sequence number allocation to fix next BlockAck Window
209 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
211 struct ath_txq *txq = tid->ac->txq;
212 struct ieee80211_tx_info *tx_info;
213 struct sk_buff *skb, *tskb;
215 struct ath_frame_info *fi;
217 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
218 fi = get_frame_info(skb);
221 tx_info = IEEE80211_SKB_CB(skb);
222 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
227 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
229 __skb_unlink(skb, &tid->buf_q);
230 ath_txq_skb_done(sc, txq, skb);
231 ieee80211_free_txskb(sc->hw, skb);
238 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
240 struct ath_txq *txq = tid->ac->txq;
243 struct list_head bf_head;
244 struct ath_tx_status ts;
245 struct ath_frame_info *fi;
246 bool sendbar = false;
248 INIT_LIST_HEAD(&bf_head);
250 memset(&ts, 0, sizeof(ts));
252 while ((skb = __skb_dequeue(&tid->retry_q))) {
253 fi = get_frame_info(skb);
256 ath_txq_skb_done(sc, txq, skb);
257 ieee80211_free_txskb(sc->hw, skb);
261 if (fi->baw_tracked) {
262 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
266 list_add_tail(&bf->list, &bf_head);
267 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
271 ath_txq_unlock(sc, txq);
272 ath_send_bar(tid, tid->seq_start);
273 ath_txq_lock(sc, txq);
277 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
282 index = ATH_BA_INDEX(tid->seq_start, seqno);
283 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
285 __clear_bit(cindex, tid->tx_buf);
287 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
288 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
289 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
290 if (tid->bar_index >= 0)
295 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
298 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
299 u16 seqno = bf->bf_state.seqno;
302 index = ATH_BA_INDEX(tid->seq_start, seqno);
303 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
304 __set_bit(cindex, tid->tx_buf);
307 if (index >= ((tid->baw_tail - tid->baw_head) &
308 (ATH_TID_MAX_BUFS - 1))) {
309 tid->baw_tail = cindex;
310 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
314 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
315 struct ath_atx_tid *tid)
320 struct list_head bf_head;
321 struct ath_tx_status ts;
322 struct ath_frame_info *fi;
324 memset(&ts, 0, sizeof(ts));
325 INIT_LIST_HEAD(&bf_head);
327 while ((skb = ath_tid_dequeue(tid))) {
328 fi = get_frame_info(skb);
332 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
336 list_add_tail(&bf->list, &bf_head);
337 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
341 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
342 struct sk_buff *skb, int count)
344 struct ath_frame_info *fi = get_frame_info(skb);
345 struct ath_buf *bf = fi->bf;
346 struct ieee80211_hdr *hdr;
347 int prev = fi->retries;
349 TX_STAT_INC(txq->axq_qnum, a_retries);
350 fi->retries += count;
355 hdr = (struct ieee80211_hdr *)skb->data;
356 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
357 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
358 sizeof(*hdr), DMA_TO_DEVICE);
361 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
363 struct ath_buf *bf = NULL;
365 spin_lock_bh(&sc->tx.txbuflock);
367 if (unlikely(list_empty(&sc->tx.txbuf))) {
368 spin_unlock_bh(&sc->tx.txbuflock);
372 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
375 spin_unlock_bh(&sc->tx.txbuflock);
380 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
382 spin_lock_bh(&sc->tx.txbuflock);
383 list_add_tail(&bf->list, &sc->tx.txbuf);
384 spin_unlock_bh(&sc->tx.txbuflock);
387 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
391 tbf = ath_tx_get_buffer(sc);
395 ATH_TXBUF_RESET(tbf);
397 tbf->bf_mpdu = bf->bf_mpdu;
398 tbf->bf_buf_addr = bf->bf_buf_addr;
399 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
400 tbf->bf_state = bf->bf_state;
401 tbf->bf_state.stale = false;
406 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
407 struct ath_tx_status *ts, int txok,
408 int *nframes, int *nbad)
410 struct ath_frame_info *fi;
412 u32 ba[WME_BA_BMP_SIZE >> 5];
419 isaggr = bf_isaggr(bf);
421 seq_st = ts->ts_seqnum;
422 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
426 fi = get_frame_info(bf->bf_mpdu);
427 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
430 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
438 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
439 struct ath_buf *bf, struct list_head *bf_q,
440 struct ath_tx_status *ts, int txok)
442 struct ath_node *an = NULL;
444 struct ieee80211_sta *sta;
445 struct ieee80211_hw *hw = sc->hw;
446 struct ieee80211_hdr *hdr;
447 struct ieee80211_tx_info *tx_info;
448 struct ath_atx_tid *tid = NULL;
449 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
450 struct list_head bf_head;
451 struct sk_buff_head bf_pending;
452 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
453 u32 ba[WME_BA_BMP_SIZE >> 5];
454 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
455 bool rc_update = true, isba;
456 struct ieee80211_tx_rate rates[4];
457 struct ath_frame_info *fi;
459 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
464 hdr = (struct ieee80211_hdr *)skb->data;
466 tx_info = IEEE80211_SKB_CB(skb);
468 memcpy(rates, bf->rates, sizeof(rates));
470 retries = ts->ts_longretry + 1;
471 for (i = 0; i < ts->ts_rateindex; i++)
472 retries += rates[i].count;
476 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
480 INIT_LIST_HEAD(&bf_head);
482 bf_next = bf->bf_next;
484 if (!bf->bf_state.stale || bf_next != NULL)
485 list_move_tail(&bf->list, &bf_head);
487 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
494 an = (struct ath_node *)sta->drv_priv;
495 tid = ath_get_skb_tid(sc, an, skb);
496 seq_first = tid->seq_start;
497 isba = ts->ts_flags & ATH9K_TX_BA;
500 * The hardware occasionally sends a tx status for the wrong TID.
501 * In this case, the BA status cannot be considered valid and all
502 * subframes need to be retransmitted
504 * Only BlockAcks have a TID and therefore normal Acks cannot be
507 if (isba && tid->tidno != ts->tid)
510 isaggr = bf_isaggr(bf);
511 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
513 if (isaggr && txok) {
514 if (ts->ts_flags & ATH9K_TX_BA) {
515 seq_st = ts->ts_seqnum;
516 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
519 * AR5416 can become deaf/mute when BA
520 * issue happens. Chip needs to be reset.
521 * But AP code may have sychronization issues
522 * when perform internal reset in this routine.
523 * Only enable reset in STA mode for now.
525 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
530 __skb_queue_head_init(&bf_pending);
532 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
534 u16 seqno = bf->bf_state.seqno;
536 txfail = txpending = sendbar = 0;
537 bf_next = bf->bf_next;
540 tx_info = IEEE80211_SKB_CB(skb);
541 fi = get_frame_info(skb);
543 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
546 * Outside of the current BlockAck window,
547 * maybe part of a previous session
550 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
551 /* transmit completion, subframe is
552 * acked by block ack */
554 } else if (!isaggr && txok) {
555 /* transmit completion */
559 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
560 if (txok || !an->sleeping)
561 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
568 bar_index = max_t(int, bar_index,
569 ATH_BA_INDEX(seq_first, seqno));
573 * Make sure the last desc is reclaimed if it
574 * not a holding desc.
576 INIT_LIST_HEAD(&bf_head);
577 if (bf_next != NULL || !bf_last->bf_state.stale)
578 list_move_tail(&bf->list, &bf_head);
582 * complete the acked-ones/xretried ones; update
585 ath_tx_update_baw(sc, tid, seqno);
587 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
588 memcpy(tx_info->control.rates, rates, sizeof(rates));
589 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
591 if (bf == bf->bf_lastbf)
592 ath_dynack_sample_tx_ts(sc->sc_ah,
597 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
600 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
601 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
602 ieee80211_sta_eosp(sta);
604 /* retry the un-acked ones */
605 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
608 tbf = ath_clone_txbuf(sc, bf_last);
610 * Update tx baw and complete the
611 * frame with failed status if we
615 ath_tx_update_baw(sc, tid, seqno);
617 ath_tx_complete_buf(sc, bf, txq,
619 bar_index = max_t(int, bar_index,
620 ATH_BA_INDEX(seq_first, seqno));
628 * Put this buffer to the temporary pending
629 * queue to retain ordering
631 __skb_queue_tail(&bf_pending, skb);
637 /* prepend un-acked frames to the beginning of the pending frame queue */
638 if (!skb_queue_empty(&bf_pending)) {
640 ieee80211_sta_set_buffered(sta, tid->tidno, true);
642 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
644 ath_tx_queue_tid(sc, txq, tid);
646 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
647 tid->ac->clear_ps_filter = true;
651 if (bar_index >= 0) {
652 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
654 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
655 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
657 ath_txq_unlock(sc, txq);
658 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
659 ath_txq_lock(sc, txq);
665 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
668 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
671 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
674 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
675 struct ath_tx_status *ts, struct ath_buf *bf,
676 struct list_head *bf_head)
678 struct ieee80211_tx_info *info;
681 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
682 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
683 txq->axq_tx_inprogress = false;
686 if (bf_is_ampdu_not_probing(bf))
687 txq->axq_ampdu_depth--;
689 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
691 if (!bf_isampdu(bf)) {
693 info = IEEE80211_SKB_CB(bf->bf_mpdu);
694 memcpy(info->control.rates, bf->rates,
695 sizeof(info->control.rates));
696 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
697 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts);
699 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
701 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
704 ath_txq_schedule(sc, txq);
707 static bool ath_lookup_legacy(struct ath_buf *bf)
710 struct ieee80211_tx_info *tx_info;
711 struct ieee80211_tx_rate *rates;
715 tx_info = IEEE80211_SKB_CB(skb);
716 rates = tx_info->control.rates;
718 for (i = 0; i < 4; i++) {
719 if (!rates[i].count || rates[i].idx < 0)
722 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
729 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
730 struct ath_atx_tid *tid)
733 struct ieee80211_tx_info *tx_info;
734 struct ieee80211_tx_rate *rates;
735 u32 max_4ms_framelen, frmlen;
736 u16 aggr_limit, bt_aggr_limit, legacy = 0;
737 int q = tid->ac->txq->mac80211_qnum;
741 tx_info = IEEE80211_SKB_CB(skb);
745 * Find the lowest frame length among the rate series that will have a
746 * 4ms (or TXOP limited) transmit duration.
748 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
750 for (i = 0; i < 4; i++) {
756 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
761 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
766 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
769 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
770 max_4ms_framelen = min(max_4ms_framelen, frmlen);
774 * limit aggregate size by the minimum rate if rate selected is
775 * not a probe rate, if rate selected is a probe rate then
776 * avoid aggregation of this packet.
778 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
781 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
784 * Override the default aggregation limit for BTCOEX.
786 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
788 aggr_limit = bt_aggr_limit;
790 if (tid->an->maxampdu)
791 aggr_limit = min(aggr_limit, tid->an->maxampdu);
797 * Returns the number of delimiters to be added to
798 * meet the minimum required mpdudensity.
800 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
801 struct ath_buf *bf, u16 frmlen,
804 #define FIRST_DESC_NDELIMS 60
805 u32 nsymbits, nsymbols;
808 int width, streams, half_gi, ndelim, mindelim;
809 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
811 /* Select standard number of delimiters based on frame length alone */
812 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
815 * If encryption enabled, hardware requires some more padding between
817 * TODO - this could be improved to be dependent on the rate.
818 * The hardware can keep up at lower rates, but not higher rates
820 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
821 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
822 ndelim += ATH_AGGR_ENCRYPTDELIM;
825 * Add delimiter when using RTS/CTS with aggregation
826 * and non enterprise AR9003 card
828 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
829 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
830 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
833 * Convert desired mpdu density from microeconds to bytes based
834 * on highest rate in rate series (i.e. first rate) to determine
835 * required minimum length for subframe. Take into account
836 * whether high rate is 20 or 40Mhz and half or full GI.
838 * If there is no mpdu density restriction, no further calculation
842 if (tid->an->mpdudensity == 0)
845 rix = bf->rates[0].idx;
846 flags = bf->rates[0].flags;
847 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
848 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
851 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
853 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
858 streams = HT_RC_2_STREAMS(rix);
859 nsymbits = bits_per_symbol[rix % 8][width] * streams;
860 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
862 if (frmlen < minlen) {
863 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
864 ndelim = max(mindelim, ndelim);
870 static struct ath_buf *
871 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
872 struct ath_atx_tid *tid, struct sk_buff_head **q)
874 struct ieee80211_tx_info *tx_info;
875 struct ath_frame_info *fi;
882 if (skb_queue_empty(*q))
889 fi = get_frame_info(skb);
892 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
894 bf->bf_state.stale = false;
897 __skb_unlink(skb, *q);
898 ath_txq_skb_done(sc, txq, skb);
899 ieee80211_free_txskb(sc->hw, skb);
906 tx_info = IEEE80211_SKB_CB(skb);
907 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
910 * No aggregation session is running, but there may be frames
911 * from a previous session or a failed attempt in the queue.
912 * Send them out as normal data frames
915 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
917 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
918 bf->bf_state.bf_type = 0;
922 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
923 seqno = bf->bf_state.seqno;
925 /* do not step over block-ack window */
926 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
929 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
930 struct ath_tx_status ts = {};
931 struct list_head bf_head;
933 INIT_LIST_HEAD(&bf_head);
934 list_add(&bf->list, &bf_head);
935 __skb_unlink(skb, *q);
936 ath_tx_update_baw(sc, tid, seqno);
937 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
948 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
949 struct ath_atx_tid *tid, struct list_head *bf_q,
950 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
953 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
954 struct ath_buf *bf = bf_first, *bf_prev = NULL;
955 int nframes = 0, ndelim;
956 u16 aggr_limit = 0, al = 0, bpad = 0,
957 al_delta, h_baw = tid->baw_size / 2;
958 struct ieee80211_tx_info *tx_info;
959 struct ath_frame_info *fi;
964 aggr_limit = ath_lookup_rate(sc, bf, tid);
968 fi = get_frame_info(skb);
970 /* do not exceed aggregation limit */
971 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
973 if (aggr_limit < al + bpad + al_delta ||
974 ath_lookup_legacy(bf) || nframes >= h_baw)
977 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
978 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
979 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
983 /* add padding for previous frame to aggregation length */
984 al += bpad + al_delta;
987 * Get the delimiters needed to meet the MPDU
988 * density for this node.
990 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
992 bpad = PADBYTES(al_delta) + (ndelim << 2);
997 /* link buffers of this frame to the aggregate */
998 if (!fi->baw_tracked)
999 ath_tx_addto_baw(sc, tid, bf);
1000 bf->bf_state.ndelim = ndelim;
1002 __skb_unlink(skb, tid_q);
1003 list_add_tail(&bf->list, bf_q);
1005 bf_prev->bf_next = bf;
1009 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1014 } while (ath_tid_has_buffered(tid));
1017 bf->bf_lastbf = bf_prev;
1019 if (bf == bf_prev) {
1020 al = get_frame_info(bf->bf_mpdu)->framelen;
1021 bf->bf_state.bf_type = BUF_AMPDU;
1023 TX_STAT_INC(txq->axq_qnum, a_aggr);
1034 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1035 * width - 0 for 20 MHz, 1 for 40 MHz
1036 * half_gi - to use 4us v/s 3.6 us for symbol time
1038 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1039 int width, int half_gi, bool shortPreamble)
1041 u32 nbits, nsymbits, duration, nsymbols;
1044 /* find number of symbols: PLCP + data */
1045 streams = HT_RC_2_STREAMS(rix);
1046 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1047 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1048 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1051 duration = SYMBOL_TIME(nsymbols);
1053 duration = SYMBOL_TIME_HALFGI(nsymbols);
1055 /* addup duration for legacy/ht training and signal fields */
1056 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1061 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1063 int streams = HT_RC_2_STREAMS(mcs);
1067 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1068 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1069 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1070 bits -= OFDM_PLCP_BITS;
1078 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1080 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1083 /* 4ms is the default (and maximum) duration */
1084 if (!txop || txop > 4096)
1087 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1088 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1089 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1090 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1091 for (mcs = 0; mcs < 32; mcs++) {
1092 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1093 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1094 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1095 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1099 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1100 u8 rateidx, bool is_40, bool is_cck)
1103 struct sk_buff *skb;
1104 struct ath_frame_info *fi;
1105 struct ieee80211_tx_info *info;
1106 struct ieee80211_vif *vif;
1107 struct ath_hw *ah = sc->sc_ah;
1109 if (sc->tx99_state || !ah->tpc_enabled)
1110 return MAX_RATE_POWER;
1113 info = IEEE80211_SKB_CB(skb);
1114 vif = info->control.vif;
1117 max_power = sc->cur_chan->cur_txpower;
1121 if (vif->bss_conf.txpower_type != NL80211_TX_POWER_LIMITED) {
1122 max_power = min_t(u8, sc->cur_chan->cur_txpower,
1123 2 * vif->bss_conf.txpower);
1127 fi = get_frame_info(skb);
1129 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1130 int txpower = fi->tx_power;
1134 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1136 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
1138 struct modal_eep_header *pmodal;
1140 is_2ghz = info->band == IEEE80211_BAND_2GHZ;
1141 pmodal = &eep->modalHeader[is_2ghz];
1142 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1144 power_ht40delta = 2;
1146 txpower += power_ht40delta;
1149 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1151 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1152 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1155 power_offset = ah->eep_ops->get_eeprom(ah,
1156 EEP_PWR_TABLE_OFFSET);
1157 txpower -= 2 * power_offset;
1160 if (OLC_FOR_AR9280_20_LATER && is_cck)
1163 txpower = max(txpower, 0);
1164 max_power = min_t(u8, ah->tx_power[rateidx],
1165 2 * vif->bss_conf.txpower);
1166 max_power = min_t(u8, max_power, txpower);
1167 } else if (!bf->bf_state.bfs_paprd) {
1168 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1169 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1170 2 * vif->bss_conf.txpower);
1172 max_power = min_t(u8, ah->tx_power[rateidx],
1173 2 * vif->bss_conf.txpower);
1174 max_power = min(max_power, fi->tx_power);
1176 max_power = ah->paprd_training_power;
1179 /* XXX: clamp minimum TX power at 1 for AR9160 since if max_power
1180 * is set to 0, frames are transmitted at max TX power
1182 return (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) ? 1 : max_power;
1185 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1186 struct ath_tx_info *info, int len, bool rts)
1188 struct ath_hw *ah = sc->sc_ah;
1189 struct ath_common *common = ath9k_hw_common(ah);
1190 struct sk_buff *skb;
1191 struct ieee80211_tx_info *tx_info;
1192 struct ieee80211_tx_rate *rates;
1193 const struct ieee80211_rate *rate;
1194 struct ieee80211_hdr *hdr;
1195 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1196 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1201 tx_info = IEEE80211_SKB_CB(skb);
1203 hdr = (struct ieee80211_hdr *)skb->data;
1205 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1206 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1207 info->rtscts_rate = fi->rtscts_rate;
1209 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1210 bool is_40, is_sgi, is_sp, is_cck;
1213 if (!rates[i].count || (rates[i].idx < 0))
1217 info->rates[i].Tries = rates[i].count;
1220 * Handle RTS threshold for unaggregated HT frames.
1222 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1223 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1224 unlikely(rts_thresh != (u32) -1)) {
1225 if (!rts_thresh || (len > rts_thresh))
1229 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1230 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1231 info->flags |= ATH9K_TXDESC_RTSENA;
1232 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1233 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1234 info->flags |= ATH9K_TXDESC_CTSENA;
1237 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1238 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1239 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1240 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1242 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1243 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1244 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1246 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1248 info->rates[i].Rate = rix | 0x80;
1249 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1250 ah->txchainmask, info->rates[i].Rate);
1251 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1252 is_40, is_sgi, is_sp);
1253 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1254 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1256 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1262 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1263 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1264 !(rate->flags & IEEE80211_RATE_ERP_G))
1265 phy = WLAN_RC_PHY_CCK;
1267 phy = WLAN_RC_PHY_OFDM;
1269 info->rates[i].Rate = rate->hw_value;
1270 if (rate->hw_value_short) {
1271 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1272 info->rates[i].Rate |= rate->hw_value_short;
1277 if (bf->bf_state.bfs_paprd)
1278 info->rates[i].ChSel = ah->txchainmask;
1280 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1281 ah->txchainmask, info->rates[i].Rate);
1283 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1284 phy, rate->bitrate * 100, len, rix, is_sp);
1286 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1287 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1291 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1292 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1293 info->flags &= ~ATH9K_TXDESC_RTSENA;
1295 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1296 if (info->flags & ATH9K_TXDESC_RTSENA)
1297 info->flags &= ~ATH9K_TXDESC_CTSENA;
1300 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1302 struct ieee80211_hdr *hdr;
1303 enum ath9k_pkt_type htype;
1306 hdr = (struct ieee80211_hdr *)skb->data;
1307 fc = hdr->frame_control;
1309 if (ieee80211_is_beacon(fc))
1310 htype = ATH9K_PKT_TYPE_BEACON;
1311 else if (ieee80211_is_probe_resp(fc))
1312 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1313 else if (ieee80211_is_atim(fc))
1314 htype = ATH9K_PKT_TYPE_ATIM;
1315 else if (ieee80211_is_pspoll(fc))
1316 htype = ATH9K_PKT_TYPE_PSPOLL;
1318 htype = ATH9K_PKT_TYPE_NORMAL;
1323 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1324 struct ath_txq *txq, int len)
1326 struct ath_hw *ah = sc->sc_ah;
1327 struct ath_buf *bf_first = NULL;
1328 struct ath_tx_info info;
1329 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1332 memset(&info, 0, sizeof(info));
1333 info.is_first = true;
1334 info.is_last = true;
1335 info.qcu = txq->axq_qnum;
1338 struct sk_buff *skb = bf->bf_mpdu;
1339 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1340 struct ath_frame_info *fi = get_frame_info(skb);
1341 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1343 info.type = get_hw_packet_type(skb);
1345 info.link = bf->bf_next->bf_daddr;
1347 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1352 if (!sc->tx99_state)
1353 info.flags = ATH9K_TXDESC_INTREQ;
1354 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1355 txq == sc->tx.uapsdq)
1356 info.flags |= ATH9K_TXDESC_CLRDMASK;
1358 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1359 info.flags |= ATH9K_TXDESC_NOACK;
1360 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1361 info.flags |= ATH9K_TXDESC_LDPC;
1363 if (bf->bf_state.bfs_paprd)
1364 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1365 ATH9K_TXDESC_PAPRD_S;
1368 * mac80211 doesn't handle RTS threshold for HT because
1369 * the decision has to be taken based on AMPDU length
1370 * and aggregation is done entirely inside ath9k.
1371 * Set the RTS/CTS flag for the first subframe based
1374 if (aggr && (bf == bf_first) &&
1375 unlikely(rts_thresh != (u32) -1)) {
1377 * "len" is the size of the entire AMPDU.
1379 if (!rts_thresh || (len > rts_thresh))
1386 ath_buf_set_rate(sc, bf, &info, len, rts);
1389 info.buf_addr[0] = bf->bf_buf_addr;
1390 info.buf_len[0] = skb->len;
1391 info.pkt_len = fi->framelen;
1392 info.keyix = fi->keyix;
1393 info.keytype = fi->keytype;
1397 info.aggr = AGGR_BUF_FIRST;
1398 else if (bf == bf_first->bf_lastbf)
1399 info.aggr = AGGR_BUF_LAST;
1401 info.aggr = AGGR_BUF_MIDDLE;
1403 info.ndelim = bf->bf_state.ndelim;
1404 info.aggr_len = len;
1407 if (bf == bf_first->bf_lastbf)
1410 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1416 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1417 struct ath_atx_tid *tid, struct list_head *bf_q,
1418 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1420 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1421 struct sk_buff *skb;
1425 struct ieee80211_tx_info *tx_info;
1429 __skb_unlink(skb, tid_q);
1430 list_add_tail(&bf->list, bf_q);
1432 bf_prev->bf_next = bf;
1438 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1442 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1443 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1446 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1450 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1451 struct ath_atx_tid *tid, bool *stop)
1454 struct ieee80211_tx_info *tx_info;
1455 struct sk_buff_head *tid_q;
1456 struct list_head bf_q;
1458 bool aggr, last = true;
1460 if (!ath_tid_has_buffered(tid))
1463 INIT_LIST_HEAD(&bf_q);
1465 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1469 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1470 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1471 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1472 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1477 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1479 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1482 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1484 if (list_empty(&bf_q))
1487 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1488 tid->ac->clear_ps_filter = false;
1489 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1492 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1493 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1497 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1500 struct ath_atx_tid *txtid;
1501 struct ath_txq *txq;
1502 struct ath_node *an;
1505 an = (struct ath_node *)sta->drv_priv;
1506 txtid = ATH_AN_2_TID(an, tid);
1507 txq = txtid->ac->txq;
1509 ath_txq_lock(sc, txq);
1511 /* update ampdu factor/density, they may have changed. This may happen
1512 * in HT IBSS when a beacon with HT-info is received after the station
1513 * has already been added.
1515 if (sta->ht_cap.ht_supported) {
1516 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1517 sta->ht_cap.ampdu_factor)) - 1;
1518 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1519 an->mpdudensity = density;
1522 /* force sequence number allocation for pending frames */
1523 ath_tx_tid_change_state(sc, txtid);
1525 txtid->active = true;
1526 *ssn = txtid->seq_start = txtid->seq_next;
1527 txtid->bar_index = -1;
1529 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1530 txtid->baw_head = txtid->baw_tail = 0;
1532 ath_txq_unlock_complete(sc, txq);
1537 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1539 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1540 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1541 struct ath_txq *txq = txtid->ac->txq;
1543 ath_txq_lock(sc, txq);
1544 txtid->active = false;
1545 ath_tx_flush_tid(sc, txtid);
1546 ath_tx_tid_change_state(sc, txtid);
1547 ath_txq_unlock_complete(sc, txq);
1550 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1551 struct ath_node *an)
1553 struct ath_atx_tid *tid;
1554 struct ath_atx_ac *ac;
1555 struct ath_txq *txq;
1559 for (tidno = 0, tid = &an->tid[tidno];
1560 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1565 ath_txq_lock(sc, txq);
1568 ath_txq_unlock(sc, txq);
1572 buffered = ath_tid_has_buffered(tid);
1575 list_del(&tid->list);
1579 list_del(&ac->list);
1582 ath_txq_unlock(sc, txq);
1584 ieee80211_sta_set_buffered(sta, tidno, buffered);
1588 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1590 struct ath_atx_tid *tid;
1591 struct ath_atx_ac *ac;
1592 struct ath_txq *txq;
1595 for (tidno = 0, tid = &an->tid[tidno];
1596 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1601 ath_txq_lock(sc, txq);
1602 ac->clear_ps_filter = true;
1604 if (ath_tid_has_buffered(tid)) {
1605 ath_tx_queue_tid(sc, txq, tid);
1606 ath_txq_schedule(sc, txq);
1609 ath_txq_unlock_complete(sc, txq);
1613 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1616 struct ath_atx_tid *tid;
1617 struct ath_node *an;
1618 struct ath_txq *txq;
1620 an = (struct ath_node *)sta->drv_priv;
1621 tid = ATH_AN_2_TID(an, tidno);
1624 ath_txq_lock(sc, txq);
1626 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1628 if (ath_tid_has_buffered(tid)) {
1629 ath_tx_queue_tid(sc, txq, tid);
1630 ath_txq_schedule(sc, txq);
1633 ath_txq_unlock_complete(sc, txq);
1636 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1637 struct ieee80211_sta *sta,
1638 u16 tids, int nframes,
1639 enum ieee80211_frame_release_type reason,
1642 struct ath_softc *sc = hw->priv;
1643 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1644 struct ath_txq *txq = sc->tx.uapsdq;
1645 struct ieee80211_tx_info *info;
1646 struct list_head bf_q;
1647 struct ath_buf *bf_tail = NULL, *bf;
1648 struct sk_buff_head *tid_q;
1652 INIT_LIST_HEAD(&bf_q);
1653 for (i = 0; tids && nframes; i++, tids >>= 1) {
1654 struct ath_atx_tid *tid;
1659 tid = ATH_AN_2_TID(an, i);
1661 ath_txq_lock(sc, tid->ac->txq);
1662 while (nframes > 0) {
1663 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1667 __skb_unlink(bf->bf_mpdu, tid_q);
1668 list_add_tail(&bf->list, &bf_q);
1669 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1670 if (bf_isampdu(bf)) {
1671 ath_tx_addto_baw(sc, tid, bf);
1672 bf->bf_state.bf_type &= ~BUF_AGGR;
1675 bf_tail->bf_next = bf;
1680 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1682 if (an->sta && !ath_tid_has_buffered(tid))
1683 ieee80211_sta_set_buffered(an->sta, i, false);
1685 ath_txq_unlock_complete(sc, tid->ac->txq);
1688 if (list_empty(&bf_q))
1691 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1692 info->flags |= IEEE80211_TX_STATUS_EOSP;
1694 bf = list_first_entry(&bf_q, struct ath_buf, list);
1695 ath_txq_lock(sc, txq);
1696 ath_tx_fill_desc(sc, bf, txq, 0);
1697 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1698 ath_txq_unlock(sc, txq);
1701 /********************/
1702 /* Queue Management */
1703 /********************/
1705 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1707 struct ath_hw *ah = sc->sc_ah;
1708 struct ath9k_tx_queue_info qi;
1709 static const int subtype_txq_to_hwq[] = {
1710 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1711 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1712 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1713 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1717 memset(&qi, 0, sizeof(qi));
1718 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1719 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1720 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1721 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1722 qi.tqi_physCompBuf = 0;
1725 * Enable interrupts only for EOL and DESC conditions.
1726 * We mark tx descriptors to receive a DESC interrupt
1727 * when a tx queue gets deep; otherwise waiting for the
1728 * EOL to reap descriptors. Note that this is done to
1729 * reduce interrupt load and this only defers reaping
1730 * descriptors, never transmitting frames. Aside from
1731 * reducing interrupts this also permits more concurrency.
1732 * The only potential downside is if the tx queue backs
1733 * up in which case the top half of the kernel may backup
1734 * due to a lack of tx descriptors.
1736 * The UAPSD queue is an exception, since we take a desc-
1737 * based intr on the EOSP frames.
1739 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1740 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1742 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1743 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1745 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1746 TXQ_FLAG_TXDESCINT_ENABLE;
1748 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1749 if (axq_qnum == -1) {
1751 * NB: don't print a message, this happens
1752 * normally on parts with too few tx queues
1756 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1757 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1759 txq->axq_qnum = axq_qnum;
1760 txq->mac80211_qnum = -1;
1761 txq->axq_link = NULL;
1762 __skb_queue_head_init(&txq->complete_q);
1763 INIT_LIST_HEAD(&txq->axq_q);
1764 spin_lock_init(&txq->axq_lock);
1766 txq->axq_ampdu_depth = 0;
1767 txq->axq_tx_inprogress = false;
1768 sc->tx.txqsetup |= 1<<axq_qnum;
1770 txq->txq_headidx = txq->txq_tailidx = 0;
1771 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1772 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1774 return &sc->tx.txq[axq_qnum];
1777 int ath_txq_update(struct ath_softc *sc, int qnum,
1778 struct ath9k_tx_queue_info *qinfo)
1780 struct ath_hw *ah = sc->sc_ah;
1782 struct ath9k_tx_queue_info qi;
1784 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1786 ath9k_hw_get_txq_props(ah, qnum, &qi);
1787 qi.tqi_aifs = qinfo->tqi_aifs;
1788 qi.tqi_cwmin = qinfo->tqi_cwmin;
1789 qi.tqi_cwmax = qinfo->tqi_cwmax;
1790 qi.tqi_burstTime = qinfo->tqi_burstTime;
1791 qi.tqi_readyTime = qinfo->tqi_readyTime;
1793 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1794 ath_err(ath9k_hw_common(sc->sc_ah),
1795 "Unable to update hardware queue %u!\n", qnum);
1798 ath9k_hw_resettxqueue(ah, qnum);
1804 int ath_cabq_update(struct ath_softc *sc)
1806 struct ath9k_tx_queue_info qi;
1807 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1808 int qnum = sc->beacon.cabq->axq_qnum;
1810 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1812 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1813 ATH_CABQ_READY_TIME) / 100;
1814 ath_txq_update(sc, qnum, &qi);
1819 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1820 struct list_head *list)
1822 struct ath_buf *bf, *lastbf;
1823 struct list_head bf_head;
1824 struct ath_tx_status ts;
1826 memset(&ts, 0, sizeof(ts));
1827 ts.ts_status = ATH9K_TX_FLUSH;
1828 INIT_LIST_HEAD(&bf_head);
1830 while (!list_empty(list)) {
1831 bf = list_first_entry(list, struct ath_buf, list);
1833 if (bf->bf_state.stale) {
1834 list_del(&bf->list);
1836 ath_tx_return_buffer(sc, bf);
1840 lastbf = bf->bf_lastbf;
1841 list_cut_position(&bf_head, list, &lastbf->list);
1842 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1847 * Drain a given TX queue (could be Beacon or Data)
1849 * This assumes output has been stopped and
1850 * we do not need to block ath_tx_tasklet.
1852 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1854 ath_txq_lock(sc, txq);
1856 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1857 int idx = txq->txq_tailidx;
1859 while (!list_empty(&txq->txq_fifo[idx])) {
1860 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1862 INCR(idx, ATH_TXFIFO_DEPTH);
1864 txq->txq_tailidx = idx;
1867 txq->axq_link = NULL;
1868 txq->axq_tx_inprogress = false;
1869 ath_drain_txq_list(sc, txq, &txq->axq_q);
1871 ath_txq_unlock_complete(sc, txq);
1874 bool ath_drain_all_txq(struct ath_softc *sc)
1876 struct ath_hw *ah = sc->sc_ah;
1877 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1878 struct ath_txq *txq;
1882 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1885 ath9k_hw_abort_tx_dma(ah);
1887 /* Check if any queue remains active */
1888 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1889 if (!ATH_TXQ_SETUP(sc, i))
1892 if (!sc->tx.txq[i].axq_depth)
1895 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1900 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1902 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1903 if (!ATH_TXQ_SETUP(sc, i))
1907 * The caller will resume queues with ieee80211_wake_queues.
1908 * Mark the queue as not stopped to prevent ath_tx_complete
1909 * from waking the queue too early.
1911 txq = &sc->tx.txq[i];
1912 txq->stopped = false;
1913 ath_draintxq(sc, txq);
1919 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1921 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1922 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1925 /* For each acq entry, for each tid, try to schedule packets
1926 * for transmit until ampdu_depth has reached min Q depth.
1928 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1930 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1931 struct ath_atx_ac *ac, *last_ac;
1932 struct ath_atx_tid *tid, *last_tid;
1933 struct list_head *ac_list;
1936 if (txq->mac80211_qnum < 0)
1939 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1942 spin_lock_bh(&sc->chan_lock);
1943 ac_list = &sc->cur_chan->acq[txq->mac80211_qnum];
1945 if (list_empty(ac_list)) {
1946 spin_unlock_bh(&sc->chan_lock);
1952 last_ac = list_entry(ac_list->prev, struct ath_atx_ac, list);
1953 while (!list_empty(ac_list)) {
1956 if (sc->cur_chan->stopped)
1959 ac = list_first_entry(ac_list, struct ath_atx_ac, list);
1960 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1961 list_del(&ac->list);
1964 while (!list_empty(&ac->tid_q)) {
1966 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1968 list_del(&tid->list);
1971 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1975 * add tid to round-robin queue if more frames
1976 * are pending for the tid
1978 if (ath_tid_has_buffered(tid))
1979 ath_tx_queue_tid(sc, txq, tid);
1981 if (stop || tid == last_tid)
1985 if (!list_empty(&ac->tid_q) && !ac->sched) {
1987 list_add_tail(&ac->list, ac_list);
1993 if (ac == last_ac) {
1998 last_ac = list_entry(ac_list->prev,
1999 struct ath_atx_ac, list);
2004 spin_unlock_bh(&sc->chan_lock);
2007 void ath_txq_schedule_all(struct ath_softc *sc)
2009 struct ath_txq *txq;
2012 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2013 txq = sc->tx.txq_map[i];
2015 spin_lock_bh(&txq->axq_lock);
2016 ath_txq_schedule(sc, txq);
2017 spin_unlock_bh(&txq->axq_lock);
2026 * Insert a chain of ath_buf (descriptors) on a txq and
2027 * assume the descriptors are already chained together by caller.
2029 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
2030 struct list_head *head, bool internal)
2032 struct ath_hw *ah = sc->sc_ah;
2033 struct ath_common *common = ath9k_hw_common(ah);
2034 struct ath_buf *bf, *bf_last;
2035 bool puttxbuf = false;
2039 * Insert the frame on the outbound list and
2040 * pass it on to the hardware.
2043 if (list_empty(head))
2046 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2047 bf = list_first_entry(head, struct ath_buf, list);
2048 bf_last = list_entry(head->prev, struct ath_buf, list);
2050 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2051 txq->axq_qnum, txq->axq_depth);
2053 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2054 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2055 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2058 list_splice_tail_init(head, &txq->axq_q);
2060 if (txq->axq_link) {
2061 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2062 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2063 txq->axq_qnum, txq->axq_link,
2064 ito64(bf->bf_daddr), bf->bf_desc);
2068 txq->axq_link = bf_last->bf_desc;
2072 TX_STAT_INC(txq->axq_qnum, puttxbuf);
2073 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2074 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2075 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2078 if (!edma || sc->tx99_state) {
2079 TX_STAT_INC(txq->axq_qnum, txstart);
2080 ath9k_hw_txstart(ah, txq->axq_qnum);
2086 if (bf_is_ampdu_not_probing(bf))
2087 txq->axq_ampdu_depth++;
2089 bf_last = bf->bf_lastbf;
2090 bf = bf_last->bf_next;
2091 bf_last->bf_next = NULL;
2096 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2097 struct ath_atx_tid *tid, struct sk_buff *skb)
2099 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2100 struct ath_frame_info *fi = get_frame_info(skb);
2101 struct list_head bf_head;
2102 struct ath_buf *bf = fi->bf;
2104 INIT_LIST_HEAD(&bf_head);
2105 list_add_tail(&bf->list, &bf_head);
2106 bf->bf_state.bf_type = 0;
2107 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2108 bf->bf_state.bf_type = BUF_AMPDU;
2109 ath_tx_addto_baw(sc, tid, bf);
2114 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2115 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2116 TX_STAT_INC(txq->axq_qnum, queued);
2119 static void setup_frame_info(struct ieee80211_hw *hw,
2120 struct ieee80211_sta *sta,
2121 struct sk_buff *skb,
2124 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2125 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2126 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2127 const struct ieee80211_rate *rate;
2128 struct ath_frame_info *fi = get_frame_info(skb);
2129 struct ath_node *an = NULL;
2130 enum ath9k_key_type keytype;
2131 bool short_preamble = false;
2134 * We check if Short Preamble is needed for the CTS rate by
2135 * checking the BSS's global flag.
2136 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2138 if (tx_info->control.vif &&
2139 tx_info->control.vif->bss_conf.use_short_preamble)
2140 short_preamble = true;
2142 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2143 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2146 an = (struct ath_node *) sta->drv_priv;
2148 memset(fi, 0, sizeof(*fi));
2151 fi->keyix = hw_key->hw_key_idx;
2152 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2153 fi->keyix = an->ps_key;
2155 fi->keyix = ATH9K_TXKEYIX_INVALID;
2156 fi->keytype = keytype;
2157 fi->framelen = framelen;
2158 fi->tx_power = MAX_RATE_POWER;
2162 fi->rtscts_rate = rate->hw_value;
2164 fi->rtscts_rate |= rate->hw_value_short;
2167 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2169 struct ath_hw *ah = sc->sc_ah;
2170 struct ath9k_channel *curchan = ah->curchan;
2172 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2173 (chainmask == 0x7) && (rate < 0x90))
2175 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2183 * Assign a descriptor (and sequence number if necessary,
2184 * and map buffer for DMA. Frees skb on error
2186 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2187 struct ath_txq *txq,
2188 struct ath_atx_tid *tid,
2189 struct sk_buff *skb)
2191 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2192 struct ath_frame_info *fi = get_frame_info(skb);
2193 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2198 bf = ath_tx_get_buffer(sc);
2200 ath_dbg(common, XMIT, "TX buffers are full\n");
2204 ATH_TXBUF_RESET(bf);
2206 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2207 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2208 seqno = tid->seq_next;
2209 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2212 hdr->seq_ctrl |= cpu_to_le16(fragno);
2214 if (!ieee80211_has_morefrags(hdr->frame_control))
2215 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2217 bf->bf_state.seqno = seqno;
2222 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2223 skb->len, DMA_TO_DEVICE);
2224 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2226 bf->bf_buf_addr = 0;
2227 ath_err(ath9k_hw_common(sc->sc_ah),
2228 "dma_mapping_error() on TX\n");
2229 ath_tx_return_buffer(sc, bf);
2238 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2240 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2241 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2242 struct ieee80211_vif *vif = info->control.vif;
2243 struct ath_vif *avp;
2245 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2251 avp = (struct ath_vif *)vif->drv_priv;
2253 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2254 avp->seq_no += 0x10;
2256 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2257 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2260 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2261 struct ath_tx_control *txctl)
2263 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2264 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2265 struct ieee80211_sta *sta = txctl->sta;
2266 struct ieee80211_vif *vif = info->control.vif;
2267 struct ath_vif *avp;
2268 struct ath_softc *sc = hw->priv;
2269 int frmlen = skb->len + FCS_LEN;
2270 int padpos, padsize;
2272 /* NOTE: sta can be NULL according to net/mac80211.h */
2274 txctl->an = (struct ath_node *)sta->drv_priv;
2275 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2276 avp = (void *)vif->drv_priv;
2277 txctl->an = &avp->mcast_node;
2280 if (info->control.hw_key)
2281 frmlen += info->control.hw_key->icv_len;
2283 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2285 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2286 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2287 !ieee80211_is_data(hdr->frame_control))
2288 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2290 /* Add the padding after the header if this is not already done */
2291 padpos = ieee80211_hdrlen(hdr->frame_control);
2292 padsize = padpos & 3;
2293 if (padsize && skb->len > padpos) {
2294 if (skb_headroom(skb) < padsize)
2297 skb_push(skb, padsize);
2298 memmove(skb->data, skb->data + padsize, padpos);
2301 setup_frame_info(hw, sta, skb, frmlen);
2306 /* Upon failure caller should free skb */
2307 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2308 struct ath_tx_control *txctl)
2310 struct ieee80211_hdr *hdr;
2311 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2312 struct ieee80211_sta *sta = txctl->sta;
2313 struct ieee80211_vif *vif = info->control.vif;
2314 struct ath_frame_info *fi = get_frame_info(skb);
2315 struct ath_vif *avp = NULL;
2316 struct ath_softc *sc = hw->priv;
2317 struct ath_txq *txq = txctl->txq;
2318 struct ath_atx_tid *tid = NULL;
2320 bool queue, skip_uapsd = false, ps_resp;
2324 avp = (void *)vif->drv_priv;
2326 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
2327 txctl->force_channel = true;
2329 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2331 ret = ath_tx_prepare(hw, skb, txctl);
2335 hdr = (struct ieee80211_hdr *) skb->data;
2337 * At this point, the vif, hw_key and sta pointers in the tx control
2338 * info are no longer valid (overwritten by the ath_frame_info data.
2341 q = skb_get_queue_mapping(skb);
2343 ath_txq_lock(sc, txq);
2344 if (txq == sc->tx.txq_map[q]) {
2346 if (++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2348 if (ath9k_is_chanctx_enabled())
2349 ieee80211_stop_queue(sc->hw, info->hw_queue);
2351 ieee80211_stop_queue(sc->hw, q);
2352 txq->stopped = true;
2356 queue = ieee80211_is_data_present(hdr->frame_control);
2358 /* Force queueing of all frames that belong to a virtual interface on
2359 * a different channel context, to ensure that they are sent on the
2362 if (((avp && avp->chanctx != sc->cur_chan) ||
2363 sc->cur_chan->stopped) && !txctl->force_channel) {
2365 txctl->an = &avp->mcast_node;
2370 if (txctl->an && queue)
2371 tid = ath_get_skb_tid(sc, txctl->an, skb);
2373 if (!skip_uapsd && ps_resp) {
2374 ath_txq_unlock(sc, txq);
2375 txq = sc->tx.uapsdq;
2376 ath_txq_lock(sc, txq);
2377 } else if (txctl->an && queue) {
2378 WARN_ON(tid->ac->txq != txctl->txq);
2380 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2381 tid->ac->clear_ps_filter = true;
2384 * Add this frame to software queue for scheduling later
2387 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2388 __skb_queue_tail(&tid->buf_q, skb);
2389 if (!txctl->an->sleeping)
2390 ath_tx_queue_tid(sc, txq, tid);
2392 ath_txq_schedule(sc, txq);
2396 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2398 ath_txq_skb_done(sc, txq, skb);
2400 dev_kfree_skb_any(skb);
2402 ieee80211_free_txskb(sc->hw, skb);
2406 bf->bf_state.bfs_paprd = txctl->paprd;
2409 bf->bf_state.bfs_paprd_timestamp = jiffies;
2411 ath_set_rates(vif, sta, bf);
2412 ath_tx_send_normal(sc, txq, tid, skb);
2415 ath_txq_unlock(sc, txq);
2420 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2421 struct sk_buff *skb)
2423 struct ath_softc *sc = hw->priv;
2424 struct ath_tx_control txctl = {
2425 .txq = sc->beacon.cabq
2427 struct ath_tx_info info = {};
2428 struct ieee80211_hdr *hdr;
2429 struct ath_buf *bf_tail = NULL;
2436 sc->cur_chan->beacon.beacon_interval * 1000 *
2437 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2440 struct ath_frame_info *fi = get_frame_info(skb);
2442 if (ath_tx_prepare(hw, skb, &txctl))
2445 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2450 ath_set_rates(vif, NULL, bf);
2451 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2452 duration += info.rates[0].PktDuration;
2454 bf_tail->bf_next = bf;
2456 list_add_tail(&bf->list, &bf_q);
2460 if (duration > max_duration)
2463 skb = ieee80211_get_buffered_bc(hw, vif);
2467 ieee80211_free_txskb(hw, skb);
2469 if (list_empty(&bf_q))
2472 bf = list_first_entry(&bf_q, struct ath_buf, list);
2473 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2475 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2476 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2477 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2478 sizeof(*hdr), DMA_TO_DEVICE);
2481 ath_txq_lock(sc, txctl.txq);
2482 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2483 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2484 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2485 ath_txq_unlock(sc, txctl.txq);
2492 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2493 int tx_flags, struct ath_txq *txq)
2495 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2496 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2497 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2498 int padpos, padsize;
2499 unsigned long flags;
2501 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2503 if (sc->sc_ah->caldata)
2504 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2506 if (!(tx_flags & ATH_TX_ERROR)) {
2507 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2508 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2510 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2513 padpos = ieee80211_hdrlen(hdr->frame_control);
2514 padsize = padpos & 3;
2515 if (padsize && skb->len>padpos+padsize) {
2517 * Remove MAC header padding before giving the frame back to
2520 memmove(skb->data + padsize, skb->data, padpos);
2521 skb_pull(skb, padsize);
2524 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2525 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2526 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2528 "Going back to sleep after having received TX status (0x%lx)\n",
2529 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2531 PS_WAIT_FOR_PSPOLL_DATA |
2532 PS_WAIT_FOR_TX_ACK));
2534 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2536 __skb_queue_tail(&txq->complete_q, skb);
2537 ath_txq_skb_done(sc, txq, skb);
2540 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2541 struct ath_txq *txq, struct list_head *bf_q,
2542 struct ath_tx_status *ts, int txok)
2544 struct sk_buff *skb = bf->bf_mpdu;
2545 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2546 unsigned long flags;
2550 tx_flags |= ATH_TX_ERROR;
2552 if (ts->ts_status & ATH9K_TXERR_FILT)
2553 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2555 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2556 bf->bf_buf_addr = 0;
2558 goto skip_tx_complete;
2560 if (bf->bf_state.bfs_paprd) {
2561 if (time_after(jiffies,
2562 bf->bf_state.bfs_paprd_timestamp +
2563 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2564 dev_kfree_skb_any(skb);
2566 complete(&sc->paprd_complete);
2568 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2569 ath_tx_complete(sc, skb, tx_flags, txq);
2572 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2573 * accidentally reference it later.
2578 * Return the list of ath_buf of this mpdu to free queue
2580 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2581 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2582 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2585 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2586 struct ath_tx_status *ts, int nframes, int nbad,
2589 struct sk_buff *skb = bf->bf_mpdu;
2590 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2591 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2592 struct ieee80211_hw *hw = sc->hw;
2593 struct ath_hw *ah = sc->sc_ah;
2597 tx_info->status.ack_signal = ts->ts_rssi;
2599 tx_rateindex = ts->ts_rateindex;
2600 WARN_ON(tx_rateindex >= hw->max_rates);
2602 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2603 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2605 BUG_ON(nbad > nframes);
2607 tx_info->status.ampdu_len = nframes;
2608 tx_info->status.ampdu_ack_len = nframes - nbad;
2610 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2611 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2613 * If an underrun error is seen assume it as an excessive
2614 * retry only if max frame trigger level has been reached
2615 * (2 KB for single stream, and 4 KB for dual stream).
2616 * Adjust the long retry as if the frame was tried
2617 * hw->max_rate_tries times to affect how rate control updates
2618 * PER for the failed rate.
2619 * In case of congestion on the bus penalizing this type of
2620 * underruns should help hardware actually transmit new frames
2621 * successfully by eventually preferring slower rates.
2622 * This itself should also alleviate congestion on the bus.
2624 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2625 ATH9K_TX_DELIM_UNDERRUN)) &&
2626 ieee80211_is_data(hdr->frame_control) &&
2627 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2628 tx_info->status.rates[tx_rateindex].count =
2632 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2633 tx_info->status.rates[i].count = 0;
2634 tx_info->status.rates[i].idx = -1;
2637 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2640 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2642 struct ath_hw *ah = sc->sc_ah;
2643 struct ath_common *common = ath9k_hw_common(ah);
2644 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2645 struct list_head bf_head;
2646 struct ath_desc *ds;
2647 struct ath_tx_status ts;
2650 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2651 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2654 ath_txq_lock(sc, txq);
2656 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2659 if (list_empty(&txq->axq_q)) {
2660 txq->axq_link = NULL;
2661 ath_txq_schedule(sc, txq);
2664 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2667 * There is a race condition that a BH gets scheduled
2668 * after sw writes TxE and before hw re-load the last
2669 * descriptor to get the newly chained one.
2670 * Software must keep the last DONE descriptor as a
2671 * holding descriptor - software does so by marking
2672 * it with the STALE flag.
2675 if (bf->bf_state.stale) {
2677 if (list_is_last(&bf_held->list, &txq->axq_q))
2680 bf = list_entry(bf_held->list.next, struct ath_buf,
2684 lastbf = bf->bf_lastbf;
2685 ds = lastbf->bf_desc;
2687 memset(&ts, 0, sizeof(ts));
2688 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2689 if (status == -EINPROGRESS)
2692 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2695 * Remove ath_buf's of the same transmit unit from txq,
2696 * however leave the last descriptor back as the holding
2697 * descriptor for hw.
2699 lastbf->bf_state.stale = true;
2700 INIT_LIST_HEAD(&bf_head);
2701 if (!list_is_singular(&lastbf->list))
2702 list_cut_position(&bf_head,
2703 &txq->axq_q, lastbf->list.prev);
2706 list_del(&bf_held->list);
2707 ath_tx_return_buffer(sc, bf_held);
2710 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2712 ath_txq_unlock_complete(sc, txq);
2715 void ath_tx_tasklet(struct ath_softc *sc)
2717 struct ath_hw *ah = sc->sc_ah;
2718 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2721 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2722 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2723 ath_tx_processq(sc, &sc->tx.txq[i]);
2727 void ath_tx_edma_tasklet(struct ath_softc *sc)
2729 struct ath_tx_status ts;
2730 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2731 struct ath_hw *ah = sc->sc_ah;
2732 struct ath_txq *txq;
2733 struct ath_buf *bf, *lastbf;
2734 struct list_head bf_head;
2735 struct list_head *fifo_list;
2739 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2742 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2743 if (status == -EINPROGRESS)
2745 if (status == -EIO) {
2746 ath_dbg(common, XMIT, "Error processing tx status\n");
2750 /* Process beacon completions separately */
2751 if (ts.qid == sc->beacon.beaconq) {
2752 sc->beacon.tx_processed = true;
2753 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2755 if (ath9k_is_chanctx_enabled()) {
2756 ath_chanctx_event(sc, NULL,
2757 ATH_CHANCTX_EVENT_BEACON_SENT);
2760 ath9k_csa_update(sc);
2764 txq = &sc->tx.txq[ts.qid];
2766 ath_txq_lock(sc, txq);
2768 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2770 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2771 if (list_empty(fifo_list)) {
2772 ath_txq_unlock(sc, txq);
2776 bf = list_first_entry(fifo_list, struct ath_buf, list);
2777 if (bf->bf_state.stale) {
2778 list_del(&bf->list);
2779 ath_tx_return_buffer(sc, bf);
2780 bf = list_first_entry(fifo_list, struct ath_buf, list);
2783 lastbf = bf->bf_lastbf;
2785 INIT_LIST_HEAD(&bf_head);
2786 if (list_is_last(&lastbf->list, fifo_list)) {
2787 list_splice_tail_init(fifo_list, &bf_head);
2788 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2790 if (!list_empty(&txq->axq_q)) {
2791 struct list_head bf_q;
2793 INIT_LIST_HEAD(&bf_q);
2794 txq->axq_link = NULL;
2795 list_splice_tail_init(&txq->axq_q, &bf_q);
2796 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2799 lastbf->bf_state.stale = true;
2801 list_cut_position(&bf_head, fifo_list,
2805 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2806 ath_txq_unlock_complete(sc, txq);
2814 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2816 struct ath_descdma *dd = &sc->txsdma;
2817 u8 txs_len = sc->sc_ah->caps.txs_len;
2819 dd->dd_desc_len = size * txs_len;
2820 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2821 &dd->dd_desc_paddr, GFP_KERNEL);
2828 static int ath_tx_edma_init(struct ath_softc *sc)
2832 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2834 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2835 sc->txsdma.dd_desc_paddr,
2836 ATH_TXSTATUS_RING_SIZE);
2841 int ath_tx_init(struct ath_softc *sc, int nbufs)
2843 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2846 spin_lock_init(&sc->tx.txbuflock);
2848 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2852 "Failed to allocate tx descriptors: %d\n", error);
2856 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2857 "beacon", ATH_BCBUF, 1, 1);
2860 "Failed to allocate beacon descriptors: %d\n", error);
2864 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2866 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2867 error = ath_tx_edma_init(sc);
2872 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2874 struct ath_atx_tid *tid;
2875 struct ath_atx_ac *ac;
2878 for (tidno = 0, tid = &an->tid[tidno];
2879 tidno < IEEE80211_NUM_TIDS;
2883 tid->seq_start = tid->seq_next = 0;
2884 tid->baw_size = WME_MAX_BA;
2885 tid->baw_head = tid->baw_tail = 0;
2887 tid->active = false;
2888 __skb_queue_head_init(&tid->buf_q);
2889 __skb_queue_head_init(&tid->retry_q);
2890 acno = TID_TO_WME_AC(tidno);
2891 tid->ac = &an->ac[acno];
2894 for (acno = 0, ac = &an->ac[acno];
2895 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2897 ac->clear_ps_filter = true;
2898 ac->txq = sc->tx.txq_map[acno];
2899 INIT_LIST_HEAD(&ac->tid_q);
2903 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2905 struct ath_atx_ac *ac;
2906 struct ath_atx_tid *tid;
2907 struct ath_txq *txq;
2910 for (tidno = 0, tid = &an->tid[tidno];
2911 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2916 ath_txq_lock(sc, txq);
2919 list_del(&tid->list);
2924 list_del(&ac->list);
2925 tid->ac->sched = false;
2928 ath_tid_drain(sc, txq, tid);
2929 tid->active = false;
2931 ath_txq_unlock(sc, txq);
2935 #ifdef CONFIG_ATH9K_TX99
2937 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2938 struct ath_tx_control *txctl)
2940 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2941 struct ath_frame_info *fi = get_frame_info(skb);
2942 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2944 int padpos, padsize;
2946 padpos = ieee80211_hdrlen(hdr->frame_control);
2947 padsize = padpos & 3;
2949 if (padsize && skb->len > padpos) {
2950 if (skb_headroom(skb) < padsize) {
2951 ath_dbg(common, XMIT,
2952 "tx99 padding failed\n");
2956 skb_push(skb, padsize);
2957 memmove(skb->data, skb->data + padsize, padpos);
2960 fi->keyix = ATH9K_TXKEYIX_INVALID;
2961 fi->framelen = skb->len + FCS_LEN;
2962 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2964 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2966 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2970 ath_set_rates(sc->tx99_vif, NULL, bf);
2972 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2973 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2975 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2980 #endif /* CONFIG_ATH9K_TX99 */