2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
76 /*********************/
77 /* Aggregation logic */
78 /*********************/
80 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
81 __acquires(&txq->axq_lock)
83 spin_lock_bh(&txq->axq_lock);
86 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
87 __releases(&txq->axq_lock)
89 spin_unlock_bh(&txq->axq_lock);
92 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
93 __releases(&txq->axq_lock)
95 struct sk_buff_head q;
98 __skb_queue_head_init(&q);
99 skb_queue_splice_init(&txq->complete_q, &q);
100 spin_unlock_bh(&txq->axq_lock);
102 while ((skb = __skb_dequeue(&q)))
103 ieee80211_tx_status(sc->hw, skb);
106 static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq,
107 struct ath_atx_tid *tid)
109 struct ath_atx_ac *ac = tid->ac;
110 struct list_head *list;
111 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
112 struct ath_chanctx *ctx = avp->chanctx;
121 list_add_tail(&tid->list, &ac->tid_q);
128 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
129 list_add_tail(&ac->list, list);
132 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
134 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
135 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
136 sizeof(tx_info->rate_driver_data));
137 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
140 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
145 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
146 seqno << IEEE80211_SEQ_SEQ_SHIFT);
149 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
152 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
153 ARRAY_SIZE(bf->rates));
156 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
159 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
160 struct ath_frame_info *fi = get_frame_info(skb);
167 txq = sc->tx.txq_map[q];
168 if (WARN_ON(--txq->pending_frames < 0))
169 txq->pending_frames = 0;
171 hw_queue = (info->hw_queue >= sc->hw->queues - 2) ? q : info->hw_queue;
173 txq->pending_frames < sc->tx.txq_max_pending[q]) {
174 ieee80211_wake_queue(sc->hw, hw_queue);
175 txq->stopped = false;
179 static struct ath_atx_tid *
180 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
182 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
183 return ATH_AN_2_TID(an, tidno);
186 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
188 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
191 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
195 skb = __skb_dequeue(&tid->retry_q);
197 skb = __skb_dequeue(&tid->buf_q);
203 * ath_tx_tid_change_state:
204 * - clears a-mpdu flag of previous session
205 * - force sequence number allocation to fix next BlockAck Window
208 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
210 struct ath_txq *txq = tid->ac->txq;
211 struct ieee80211_tx_info *tx_info;
212 struct sk_buff *skb, *tskb;
214 struct ath_frame_info *fi;
216 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
217 fi = get_frame_info(skb);
220 tx_info = IEEE80211_SKB_CB(skb);
221 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
226 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
228 __skb_unlink(skb, &tid->buf_q);
229 ath_txq_skb_done(sc, txq, skb);
230 ieee80211_free_txskb(sc->hw, skb);
237 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
239 struct ath_txq *txq = tid->ac->txq;
242 struct list_head bf_head;
243 struct ath_tx_status ts;
244 struct ath_frame_info *fi;
245 bool sendbar = false;
247 INIT_LIST_HEAD(&bf_head);
249 memset(&ts, 0, sizeof(ts));
251 while ((skb = __skb_dequeue(&tid->retry_q))) {
252 fi = get_frame_info(skb);
255 ath_txq_skb_done(sc, txq, skb);
256 ieee80211_free_txskb(sc->hw, skb);
260 if (fi->baw_tracked) {
261 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
265 list_add_tail(&bf->list, &bf_head);
266 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
270 ath_txq_unlock(sc, txq);
271 ath_send_bar(tid, tid->seq_start);
272 ath_txq_lock(sc, txq);
276 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
281 index = ATH_BA_INDEX(tid->seq_start, seqno);
282 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
284 __clear_bit(cindex, tid->tx_buf);
286 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
287 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
288 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
289 if (tid->bar_index >= 0)
294 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
297 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
298 u16 seqno = bf->bf_state.seqno;
301 index = ATH_BA_INDEX(tid->seq_start, seqno);
302 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
303 __set_bit(cindex, tid->tx_buf);
306 if (index >= ((tid->baw_tail - tid->baw_head) &
307 (ATH_TID_MAX_BUFS - 1))) {
308 tid->baw_tail = cindex;
309 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
313 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
314 struct ath_atx_tid *tid)
319 struct list_head bf_head;
320 struct ath_tx_status ts;
321 struct ath_frame_info *fi;
323 memset(&ts, 0, sizeof(ts));
324 INIT_LIST_HEAD(&bf_head);
326 while ((skb = ath_tid_dequeue(tid))) {
327 fi = get_frame_info(skb);
331 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
335 list_add_tail(&bf->list, &bf_head);
336 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
340 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
341 struct sk_buff *skb, int count)
343 struct ath_frame_info *fi = get_frame_info(skb);
344 struct ath_buf *bf = fi->bf;
345 struct ieee80211_hdr *hdr;
346 int prev = fi->retries;
348 TX_STAT_INC(txq->axq_qnum, a_retries);
349 fi->retries += count;
354 hdr = (struct ieee80211_hdr *)skb->data;
355 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
356 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
357 sizeof(*hdr), DMA_TO_DEVICE);
360 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
362 struct ath_buf *bf = NULL;
364 spin_lock_bh(&sc->tx.txbuflock);
366 if (unlikely(list_empty(&sc->tx.txbuf))) {
367 spin_unlock_bh(&sc->tx.txbuflock);
371 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
374 spin_unlock_bh(&sc->tx.txbuflock);
379 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
381 spin_lock_bh(&sc->tx.txbuflock);
382 list_add_tail(&bf->list, &sc->tx.txbuf);
383 spin_unlock_bh(&sc->tx.txbuflock);
386 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
390 tbf = ath_tx_get_buffer(sc);
394 ATH_TXBUF_RESET(tbf);
396 tbf->bf_mpdu = bf->bf_mpdu;
397 tbf->bf_buf_addr = bf->bf_buf_addr;
398 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
399 tbf->bf_state = bf->bf_state;
400 tbf->bf_state.stale = false;
405 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
406 struct ath_tx_status *ts, int txok,
407 int *nframes, int *nbad)
409 struct ath_frame_info *fi;
411 u32 ba[WME_BA_BMP_SIZE >> 5];
418 isaggr = bf_isaggr(bf);
420 seq_st = ts->ts_seqnum;
421 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
425 fi = get_frame_info(bf->bf_mpdu);
426 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
429 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
437 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
438 struct ath_buf *bf, struct list_head *bf_q,
439 struct ath_tx_status *ts, int txok)
441 struct ath_node *an = NULL;
443 struct ieee80211_sta *sta;
444 struct ieee80211_hw *hw = sc->hw;
445 struct ieee80211_hdr *hdr;
446 struct ieee80211_tx_info *tx_info;
447 struct ath_atx_tid *tid = NULL;
448 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
449 struct list_head bf_head;
450 struct sk_buff_head bf_pending;
451 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
452 u32 ba[WME_BA_BMP_SIZE >> 5];
453 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
454 bool rc_update = true, isba;
455 struct ieee80211_tx_rate rates[4];
456 struct ath_frame_info *fi;
458 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
463 hdr = (struct ieee80211_hdr *)skb->data;
465 tx_info = IEEE80211_SKB_CB(skb);
467 memcpy(rates, bf->rates, sizeof(rates));
469 retries = ts->ts_longretry + 1;
470 for (i = 0; i < ts->ts_rateindex; i++)
471 retries += rates[i].count;
475 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
479 INIT_LIST_HEAD(&bf_head);
481 bf_next = bf->bf_next;
483 if (!bf->bf_state.stale || bf_next != NULL)
484 list_move_tail(&bf->list, &bf_head);
486 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
493 an = (struct ath_node *)sta->drv_priv;
494 tid = ath_get_skb_tid(sc, an, skb);
495 seq_first = tid->seq_start;
496 isba = ts->ts_flags & ATH9K_TX_BA;
499 * The hardware occasionally sends a tx status for the wrong TID.
500 * In this case, the BA status cannot be considered valid and all
501 * subframes need to be retransmitted
503 * Only BlockAcks have a TID and therefore normal Acks cannot be
506 if (isba && tid->tidno != ts->tid)
509 isaggr = bf_isaggr(bf);
510 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
512 if (isaggr && txok) {
513 if (ts->ts_flags & ATH9K_TX_BA) {
514 seq_st = ts->ts_seqnum;
515 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
518 * AR5416 can become deaf/mute when BA
519 * issue happens. Chip needs to be reset.
520 * But AP code may have sychronization issues
521 * when perform internal reset in this routine.
522 * Only enable reset in STA mode for now.
524 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
529 __skb_queue_head_init(&bf_pending);
531 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
533 u16 seqno = bf->bf_state.seqno;
535 txfail = txpending = sendbar = 0;
536 bf_next = bf->bf_next;
539 tx_info = IEEE80211_SKB_CB(skb);
540 fi = get_frame_info(skb);
542 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
545 * Outside of the current BlockAck window,
546 * maybe part of a previous session
549 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
550 /* transmit completion, subframe is
551 * acked by block ack */
553 } else if (!isaggr && txok) {
554 /* transmit completion */
558 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
559 if (txok || !an->sleeping)
560 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
567 bar_index = max_t(int, bar_index,
568 ATH_BA_INDEX(seq_first, seqno));
572 * Make sure the last desc is reclaimed if it
573 * not a holding desc.
575 INIT_LIST_HEAD(&bf_head);
576 if (bf_next != NULL || !bf_last->bf_state.stale)
577 list_move_tail(&bf->list, &bf_head);
581 * complete the acked-ones/xretried ones; update
584 ath_tx_update_baw(sc, tid, seqno);
586 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
587 memcpy(tx_info->control.rates, rates, sizeof(rates));
588 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
592 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
595 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
596 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
597 ieee80211_sta_eosp(sta);
599 /* retry the un-acked ones */
600 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
603 tbf = ath_clone_txbuf(sc, bf_last);
605 * Update tx baw and complete the
606 * frame with failed status if we
610 ath_tx_update_baw(sc, tid, seqno);
612 ath_tx_complete_buf(sc, bf, txq,
614 bar_index = max_t(int, bar_index,
615 ATH_BA_INDEX(seq_first, seqno));
623 * Put this buffer to the temporary pending
624 * queue to retain ordering
626 __skb_queue_tail(&bf_pending, skb);
632 /* prepend un-acked frames to the beginning of the pending frame queue */
633 if (!skb_queue_empty(&bf_pending)) {
635 ieee80211_sta_set_buffered(sta, tid->tidno, true);
637 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
639 ath_tx_queue_tid(sc, txq, tid);
641 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
642 tid->ac->clear_ps_filter = true;
646 if (bar_index >= 0) {
647 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
649 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
650 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
652 ath_txq_unlock(sc, txq);
653 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
654 ath_txq_lock(sc, txq);
660 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
663 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
665 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
666 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
669 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
670 struct ath_tx_status *ts, struct ath_buf *bf,
671 struct list_head *bf_head)
673 struct ieee80211_tx_info *info;
676 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
677 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
678 txq->axq_tx_inprogress = false;
681 if (bf_is_ampdu_not_probing(bf))
682 txq->axq_ampdu_depth--;
684 if (!bf_isampdu(bf)) {
686 info = IEEE80211_SKB_CB(bf->bf_mpdu);
687 memcpy(info->control.rates, bf->rates,
688 sizeof(info->control.rates));
689 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
691 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
693 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
696 ath_txq_schedule(sc, txq);
699 static bool ath_lookup_legacy(struct ath_buf *bf)
702 struct ieee80211_tx_info *tx_info;
703 struct ieee80211_tx_rate *rates;
707 tx_info = IEEE80211_SKB_CB(skb);
708 rates = tx_info->control.rates;
710 for (i = 0; i < 4; i++) {
711 if (!rates[i].count || rates[i].idx < 0)
714 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
721 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
722 struct ath_atx_tid *tid)
725 struct ieee80211_tx_info *tx_info;
726 struct ieee80211_tx_rate *rates;
727 u32 max_4ms_framelen, frmlen;
728 u16 aggr_limit, bt_aggr_limit, legacy = 0;
729 int q = tid->ac->txq->mac80211_qnum;
733 tx_info = IEEE80211_SKB_CB(skb);
737 * Find the lowest frame length among the rate series that will have a
738 * 4ms (or TXOP limited) transmit duration.
740 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
742 for (i = 0; i < 4; i++) {
748 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
753 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
758 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
761 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
762 max_4ms_framelen = min(max_4ms_framelen, frmlen);
766 * limit aggregate size by the minimum rate if rate selected is
767 * not a probe rate, if rate selected is a probe rate then
768 * avoid aggregation of this packet.
770 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
773 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
776 * Override the default aggregation limit for BTCOEX.
778 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
780 aggr_limit = bt_aggr_limit;
782 if (tid->an->maxampdu)
783 aggr_limit = min(aggr_limit, tid->an->maxampdu);
789 * Returns the number of delimiters to be added to
790 * meet the minimum required mpdudensity.
792 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
793 struct ath_buf *bf, u16 frmlen,
796 #define FIRST_DESC_NDELIMS 60
797 u32 nsymbits, nsymbols;
800 int width, streams, half_gi, ndelim, mindelim;
801 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
803 /* Select standard number of delimiters based on frame length alone */
804 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
807 * If encryption enabled, hardware requires some more padding between
809 * TODO - this could be improved to be dependent on the rate.
810 * The hardware can keep up at lower rates, but not higher rates
812 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
813 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
814 ndelim += ATH_AGGR_ENCRYPTDELIM;
817 * Add delimiter when using RTS/CTS with aggregation
818 * and non enterprise AR9003 card
820 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
821 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
822 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
825 * Convert desired mpdu density from microeconds to bytes based
826 * on highest rate in rate series (i.e. first rate) to determine
827 * required minimum length for subframe. Take into account
828 * whether high rate is 20 or 40Mhz and half or full GI.
830 * If there is no mpdu density restriction, no further calculation
834 if (tid->an->mpdudensity == 0)
837 rix = bf->rates[0].idx;
838 flags = bf->rates[0].flags;
839 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
840 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
843 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
845 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
850 streams = HT_RC_2_STREAMS(rix);
851 nsymbits = bits_per_symbol[rix % 8][width] * streams;
852 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
854 if (frmlen < minlen) {
855 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
856 ndelim = max(mindelim, ndelim);
862 static struct ath_buf *
863 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
864 struct ath_atx_tid *tid, struct sk_buff_head **q)
866 struct ieee80211_tx_info *tx_info;
867 struct ath_frame_info *fi;
874 if (skb_queue_empty(*q))
881 fi = get_frame_info(skb);
884 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
886 bf->bf_state.stale = false;
889 __skb_unlink(skb, *q);
890 ath_txq_skb_done(sc, txq, skb);
891 ieee80211_free_txskb(sc->hw, skb);
898 tx_info = IEEE80211_SKB_CB(skb);
899 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
902 * No aggregation session is running, but there may be frames
903 * from a previous session or a failed attempt in the queue.
904 * Send them out as normal data frames
907 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
909 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
910 bf->bf_state.bf_type = 0;
914 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
915 seqno = bf->bf_state.seqno;
917 /* do not step over block-ack window */
918 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
921 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
922 struct ath_tx_status ts = {};
923 struct list_head bf_head;
925 INIT_LIST_HEAD(&bf_head);
926 list_add(&bf->list, &bf_head);
927 __skb_unlink(skb, *q);
928 ath_tx_update_baw(sc, tid, seqno);
929 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
940 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
941 struct ath_atx_tid *tid, struct list_head *bf_q,
942 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
945 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
946 struct ath_buf *bf = bf_first, *bf_prev = NULL;
947 int nframes = 0, ndelim;
948 u16 aggr_limit = 0, al = 0, bpad = 0,
949 al_delta, h_baw = tid->baw_size / 2;
950 struct ieee80211_tx_info *tx_info;
951 struct ath_frame_info *fi;
956 aggr_limit = ath_lookup_rate(sc, bf, tid);
960 fi = get_frame_info(skb);
962 /* do not exceed aggregation limit */
963 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
965 if (aggr_limit < al + bpad + al_delta ||
966 ath_lookup_legacy(bf) || nframes >= h_baw)
969 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
970 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
971 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
975 /* add padding for previous frame to aggregation length */
976 al += bpad + al_delta;
979 * Get the delimiters needed to meet the MPDU
980 * density for this node.
982 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
984 bpad = PADBYTES(al_delta) + (ndelim << 2);
989 /* link buffers of this frame to the aggregate */
990 if (!fi->baw_tracked)
991 ath_tx_addto_baw(sc, tid, bf);
992 bf->bf_state.ndelim = ndelim;
994 __skb_unlink(skb, tid_q);
995 list_add_tail(&bf->list, bf_q);
997 bf_prev->bf_next = bf;
1001 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1006 } while (ath_tid_has_buffered(tid));
1009 bf->bf_lastbf = bf_prev;
1011 if (bf == bf_prev) {
1012 al = get_frame_info(bf->bf_mpdu)->framelen;
1013 bf->bf_state.bf_type = BUF_AMPDU;
1015 TX_STAT_INC(txq->axq_qnum, a_aggr);
1026 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1027 * width - 0 for 20 MHz, 1 for 40 MHz
1028 * half_gi - to use 4us v/s 3.6 us for symbol time
1030 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1031 int width, int half_gi, bool shortPreamble)
1033 u32 nbits, nsymbits, duration, nsymbols;
1036 /* find number of symbols: PLCP + data */
1037 streams = HT_RC_2_STREAMS(rix);
1038 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1039 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1040 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1043 duration = SYMBOL_TIME(nsymbols);
1045 duration = SYMBOL_TIME_HALFGI(nsymbols);
1047 /* addup duration for legacy/ht training and signal fields */
1048 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1053 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1055 int streams = HT_RC_2_STREAMS(mcs);
1059 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1060 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1061 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1062 bits -= OFDM_PLCP_BITS;
1070 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1072 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1075 /* 4ms is the default (and maximum) duration */
1076 if (!txop || txop > 4096)
1079 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1080 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1081 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1082 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1083 for (mcs = 0; mcs < 32; mcs++) {
1084 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1085 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1086 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1087 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1091 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1092 struct ath_tx_info *info, int len, bool rts)
1094 struct ath_hw *ah = sc->sc_ah;
1095 struct ath_common *common = ath9k_hw_common(ah);
1096 struct sk_buff *skb;
1097 struct ieee80211_tx_info *tx_info;
1098 struct ieee80211_tx_rate *rates;
1099 const struct ieee80211_rate *rate;
1100 struct ieee80211_hdr *hdr;
1101 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1102 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1107 tx_info = IEEE80211_SKB_CB(skb);
1109 hdr = (struct ieee80211_hdr *)skb->data;
1111 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1112 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1113 info->rtscts_rate = fi->rtscts_rate;
1115 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1116 bool is_40, is_sgi, is_sp;
1119 if (!rates[i].count || (rates[i].idx < 0))
1123 info->rates[i].Tries = rates[i].count;
1126 * Handle RTS threshold for unaggregated HT frames.
1128 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1129 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1130 unlikely(rts_thresh != (u32) -1)) {
1131 if (!rts_thresh || (len > rts_thresh))
1135 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1136 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1137 info->flags |= ATH9K_TXDESC_RTSENA;
1138 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1139 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1140 info->flags |= ATH9K_TXDESC_CTSENA;
1143 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1144 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1145 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1146 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1148 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1149 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1150 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1152 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1154 info->rates[i].Rate = rix | 0x80;
1155 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1156 ah->txchainmask, info->rates[i].Rate);
1157 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1158 is_40, is_sgi, is_sp);
1159 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1160 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1165 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1166 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1167 !(rate->flags & IEEE80211_RATE_ERP_G))
1168 phy = WLAN_RC_PHY_CCK;
1170 phy = WLAN_RC_PHY_OFDM;
1172 info->rates[i].Rate = rate->hw_value;
1173 if (rate->hw_value_short) {
1174 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1175 info->rates[i].Rate |= rate->hw_value_short;
1180 if (bf->bf_state.bfs_paprd)
1181 info->rates[i].ChSel = ah->txchainmask;
1183 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1184 ah->txchainmask, info->rates[i].Rate);
1186 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1187 phy, rate->bitrate * 100, len, rix, is_sp);
1190 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1191 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1192 info->flags &= ~ATH9K_TXDESC_RTSENA;
1194 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1195 if (info->flags & ATH9K_TXDESC_RTSENA)
1196 info->flags &= ~ATH9K_TXDESC_CTSENA;
1199 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1201 struct ieee80211_hdr *hdr;
1202 enum ath9k_pkt_type htype;
1205 hdr = (struct ieee80211_hdr *)skb->data;
1206 fc = hdr->frame_control;
1208 if (ieee80211_is_beacon(fc))
1209 htype = ATH9K_PKT_TYPE_BEACON;
1210 else if (ieee80211_is_probe_resp(fc))
1211 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1212 else if (ieee80211_is_atim(fc))
1213 htype = ATH9K_PKT_TYPE_ATIM;
1214 else if (ieee80211_is_pspoll(fc))
1215 htype = ATH9K_PKT_TYPE_PSPOLL;
1217 htype = ATH9K_PKT_TYPE_NORMAL;
1222 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1223 struct ath_txq *txq, int len)
1225 struct ath_hw *ah = sc->sc_ah;
1226 struct ath_buf *bf_first = NULL;
1227 struct ath_tx_info info;
1228 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1231 memset(&info, 0, sizeof(info));
1232 info.is_first = true;
1233 info.is_last = true;
1234 info.txpower = MAX_RATE_POWER;
1235 info.qcu = txq->axq_qnum;
1238 struct sk_buff *skb = bf->bf_mpdu;
1239 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1240 struct ath_frame_info *fi = get_frame_info(skb);
1241 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1243 info.type = get_hw_packet_type(skb);
1245 info.link = bf->bf_next->bf_daddr;
1247 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1252 if (!sc->tx99_state)
1253 info.flags = ATH9K_TXDESC_INTREQ;
1254 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1255 txq == sc->tx.uapsdq)
1256 info.flags |= ATH9K_TXDESC_CLRDMASK;
1258 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1259 info.flags |= ATH9K_TXDESC_NOACK;
1260 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1261 info.flags |= ATH9K_TXDESC_LDPC;
1263 if (bf->bf_state.bfs_paprd)
1264 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1265 ATH9K_TXDESC_PAPRD_S;
1268 * mac80211 doesn't handle RTS threshold for HT because
1269 * the decision has to be taken based on AMPDU length
1270 * and aggregation is done entirely inside ath9k.
1271 * Set the RTS/CTS flag for the first subframe based
1274 if (aggr && (bf == bf_first) &&
1275 unlikely(rts_thresh != (u32) -1)) {
1277 * "len" is the size of the entire AMPDU.
1279 if (!rts_thresh || (len > rts_thresh))
1286 ath_buf_set_rate(sc, bf, &info, len, rts);
1289 info.buf_addr[0] = bf->bf_buf_addr;
1290 info.buf_len[0] = skb->len;
1291 info.pkt_len = fi->framelen;
1292 info.keyix = fi->keyix;
1293 info.keytype = fi->keytype;
1297 info.aggr = AGGR_BUF_FIRST;
1298 else if (bf == bf_first->bf_lastbf)
1299 info.aggr = AGGR_BUF_LAST;
1301 info.aggr = AGGR_BUF_MIDDLE;
1303 info.ndelim = bf->bf_state.ndelim;
1304 info.aggr_len = len;
1307 if (bf == bf_first->bf_lastbf)
1310 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1316 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1317 struct ath_atx_tid *tid, struct list_head *bf_q,
1318 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1320 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1321 struct sk_buff *skb;
1325 struct ieee80211_tx_info *tx_info;
1329 __skb_unlink(skb, tid_q);
1330 list_add_tail(&bf->list, bf_q);
1332 bf_prev->bf_next = bf;
1338 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1342 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1343 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1346 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1350 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1351 struct ath_atx_tid *tid, bool *stop)
1354 struct ieee80211_tx_info *tx_info;
1355 struct sk_buff_head *tid_q;
1356 struct list_head bf_q;
1358 bool aggr, last = true;
1360 if (!ath_tid_has_buffered(tid))
1363 INIT_LIST_HEAD(&bf_q);
1365 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1369 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1370 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1371 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1372 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1377 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1379 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1382 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1384 if (list_empty(&bf_q))
1387 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1388 tid->ac->clear_ps_filter = false;
1389 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1392 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1393 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1397 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1400 struct ath_atx_tid *txtid;
1401 struct ath_txq *txq;
1402 struct ath_node *an;
1405 an = (struct ath_node *)sta->drv_priv;
1406 txtid = ATH_AN_2_TID(an, tid);
1407 txq = txtid->ac->txq;
1409 ath_txq_lock(sc, txq);
1411 /* update ampdu factor/density, they may have changed. This may happen
1412 * in HT IBSS when a beacon with HT-info is received after the station
1413 * has already been added.
1415 if (sta->ht_cap.ht_supported) {
1416 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1417 sta->ht_cap.ampdu_factor)) - 1;
1418 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1419 an->mpdudensity = density;
1422 /* force sequence number allocation for pending frames */
1423 ath_tx_tid_change_state(sc, txtid);
1425 txtid->active = true;
1426 *ssn = txtid->seq_start = txtid->seq_next;
1427 txtid->bar_index = -1;
1429 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1430 txtid->baw_head = txtid->baw_tail = 0;
1432 ath_txq_unlock_complete(sc, txq);
1437 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1439 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1440 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1441 struct ath_txq *txq = txtid->ac->txq;
1443 ath_txq_lock(sc, txq);
1444 txtid->active = false;
1445 ath_tx_flush_tid(sc, txtid);
1446 ath_tx_tid_change_state(sc, txtid);
1447 ath_txq_unlock_complete(sc, txq);
1450 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1451 struct ath_node *an)
1453 struct ath_atx_tid *tid;
1454 struct ath_atx_ac *ac;
1455 struct ath_txq *txq;
1459 for (tidno = 0, tid = &an->tid[tidno];
1460 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1465 ath_txq_lock(sc, txq);
1468 ath_txq_unlock(sc, txq);
1472 buffered = ath_tid_has_buffered(tid);
1475 list_del(&tid->list);
1479 list_del(&ac->list);
1482 ath_txq_unlock(sc, txq);
1484 ieee80211_sta_set_buffered(sta, tidno, buffered);
1488 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1490 struct ath_atx_tid *tid;
1491 struct ath_atx_ac *ac;
1492 struct ath_txq *txq;
1495 for (tidno = 0, tid = &an->tid[tidno];
1496 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1501 ath_txq_lock(sc, txq);
1502 ac->clear_ps_filter = true;
1504 if (ath_tid_has_buffered(tid)) {
1505 ath_tx_queue_tid(sc, txq, tid);
1506 ath_txq_schedule(sc, txq);
1509 ath_txq_unlock_complete(sc, txq);
1513 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1516 struct ath_atx_tid *tid;
1517 struct ath_node *an;
1518 struct ath_txq *txq;
1520 an = (struct ath_node *)sta->drv_priv;
1521 tid = ATH_AN_2_TID(an, tidno);
1524 ath_txq_lock(sc, txq);
1526 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1528 if (ath_tid_has_buffered(tid)) {
1529 ath_tx_queue_tid(sc, txq, tid);
1530 ath_txq_schedule(sc, txq);
1533 ath_txq_unlock_complete(sc, txq);
1536 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1537 struct ieee80211_sta *sta,
1538 u16 tids, int nframes,
1539 enum ieee80211_frame_release_type reason,
1542 struct ath_softc *sc = hw->priv;
1543 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1544 struct ath_txq *txq = sc->tx.uapsdq;
1545 struct ieee80211_tx_info *info;
1546 struct list_head bf_q;
1547 struct ath_buf *bf_tail = NULL, *bf;
1548 struct sk_buff_head *tid_q;
1552 INIT_LIST_HEAD(&bf_q);
1553 for (i = 0; tids && nframes; i++, tids >>= 1) {
1554 struct ath_atx_tid *tid;
1559 tid = ATH_AN_2_TID(an, i);
1561 ath_txq_lock(sc, tid->ac->txq);
1562 while (nframes > 0) {
1563 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1567 __skb_unlink(bf->bf_mpdu, tid_q);
1568 list_add_tail(&bf->list, &bf_q);
1569 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1570 if (bf_isampdu(bf)) {
1571 ath_tx_addto_baw(sc, tid, bf);
1572 bf->bf_state.bf_type &= ~BUF_AGGR;
1575 bf_tail->bf_next = bf;
1580 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1582 if (an->sta && !ath_tid_has_buffered(tid))
1583 ieee80211_sta_set_buffered(an->sta, i, false);
1585 ath_txq_unlock_complete(sc, tid->ac->txq);
1588 if (list_empty(&bf_q))
1591 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1592 info->flags |= IEEE80211_TX_STATUS_EOSP;
1594 bf = list_first_entry(&bf_q, struct ath_buf, list);
1595 ath_txq_lock(sc, txq);
1596 ath_tx_fill_desc(sc, bf, txq, 0);
1597 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1598 ath_txq_unlock(sc, txq);
1601 /********************/
1602 /* Queue Management */
1603 /********************/
1605 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1607 struct ath_hw *ah = sc->sc_ah;
1608 struct ath9k_tx_queue_info qi;
1609 static const int subtype_txq_to_hwq[] = {
1610 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1611 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1612 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1613 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1617 memset(&qi, 0, sizeof(qi));
1618 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1619 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1620 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1621 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1622 qi.tqi_physCompBuf = 0;
1625 * Enable interrupts only for EOL and DESC conditions.
1626 * We mark tx descriptors to receive a DESC interrupt
1627 * when a tx queue gets deep; otherwise waiting for the
1628 * EOL to reap descriptors. Note that this is done to
1629 * reduce interrupt load and this only defers reaping
1630 * descriptors, never transmitting frames. Aside from
1631 * reducing interrupts this also permits more concurrency.
1632 * The only potential downside is if the tx queue backs
1633 * up in which case the top half of the kernel may backup
1634 * due to a lack of tx descriptors.
1636 * The UAPSD queue is an exception, since we take a desc-
1637 * based intr on the EOSP frames.
1639 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1640 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1642 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1643 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1645 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1646 TXQ_FLAG_TXDESCINT_ENABLE;
1648 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1649 if (axq_qnum == -1) {
1651 * NB: don't print a message, this happens
1652 * normally on parts with too few tx queues
1656 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1657 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1659 txq->axq_qnum = axq_qnum;
1660 txq->mac80211_qnum = -1;
1661 txq->axq_link = NULL;
1662 __skb_queue_head_init(&txq->complete_q);
1663 INIT_LIST_HEAD(&txq->axq_q);
1664 spin_lock_init(&txq->axq_lock);
1666 txq->axq_ampdu_depth = 0;
1667 txq->axq_tx_inprogress = false;
1668 sc->tx.txqsetup |= 1<<axq_qnum;
1670 txq->txq_headidx = txq->txq_tailidx = 0;
1671 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1672 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1674 return &sc->tx.txq[axq_qnum];
1677 int ath_txq_update(struct ath_softc *sc, int qnum,
1678 struct ath9k_tx_queue_info *qinfo)
1680 struct ath_hw *ah = sc->sc_ah;
1682 struct ath9k_tx_queue_info qi;
1684 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1686 ath9k_hw_get_txq_props(ah, qnum, &qi);
1687 qi.tqi_aifs = qinfo->tqi_aifs;
1688 qi.tqi_cwmin = qinfo->tqi_cwmin;
1689 qi.tqi_cwmax = qinfo->tqi_cwmax;
1690 qi.tqi_burstTime = qinfo->tqi_burstTime;
1691 qi.tqi_readyTime = qinfo->tqi_readyTime;
1693 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1694 ath_err(ath9k_hw_common(sc->sc_ah),
1695 "Unable to update hardware queue %u!\n", qnum);
1698 ath9k_hw_resettxqueue(ah, qnum);
1704 int ath_cabq_update(struct ath_softc *sc)
1706 struct ath9k_tx_queue_info qi;
1707 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1708 int qnum = sc->beacon.cabq->axq_qnum;
1710 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1712 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1713 ATH_CABQ_READY_TIME) / 100;
1714 ath_txq_update(sc, qnum, &qi);
1719 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1720 struct list_head *list)
1722 struct ath_buf *bf, *lastbf;
1723 struct list_head bf_head;
1724 struct ath_tx_status ts;
1726 memset(&ts, 0, sizeof(ts));
1727 ts.ts_status = ATH9K_TX_FLUSH;
1728 INIT_LIST_HEAD(&bf_head);
1730 while (!list_empty(list)) {
1731 bf = list_first_entry(list, struct ath_buf, list);
1733 if (bf->bf_state.stale) {
1734 list_del(&bf->list);
1736 ath_tx_return_buffer(sc, bf);
1740 lastbf = bf->bf_lastbf;
1741 list_cut_position(&bf_head, list, &lastbf->list);
1742 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1747 * Drain a given TX queue (could be Beacon or Data)
1749 * This assumes output has been stopped and
1750 * we do not need to block ath_tx_tasklet.
1752 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1754 ath_txq_lock(sc, txq);
1756 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1757 int idx = txq->txq_tailidx;
1759 while (!list_empty(&txq->txq_fifo[idx])) {
1760 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1762 INCR(idx, ATH_TXFIFO_DEPTH);
1764 txq->txq_tailidx = idx;
1767 txq->axq_link = NULL;
1768 txq->axq_tx_inprogress = false;
1769 ath_drain_txq_list(sc, txq, &txq->axq_q);
1771 ath_txq_unlock_complete(sc, txq);
1774 bool ath_drain_all_txq(struct ath_softc *sc)
1776 struct ath_hw *ah = sc->sc_ah;
1777 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1778 struct ath_txq *txq;
1782 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1785 ath9k_hw_abort_tx_dma(ah);
1787 /* Check if any queue remains active */
1788 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1789 if (!ATH_TXQ_SETUP(sc, i))
1792 if (!sc->tx.txq[i].axq_depth)
1795 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1800 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1802 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1803 if (!ATH_TXQ_SETUP(sc, i))
1807 * The caller will resume queues with ieee80211_wake_queues.
1808 * Mark the queue as not stopped to prevent ath_tx_complete
1809 * from waking the queue too early.
1811 txq = &sc->tx.txq[i];
1812 txq->stopped = false;
1813 ath_draintxq(sc, txq);
1819 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1821 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1822 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1825 /* For each acq entry, for each tid, try to schedule packets
1826 * for transmit until ampdu_depth has reached min Q depth.
1828 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1830 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1831 struct ath_atx_ac *ac, *last_ac;
1832 struct ath_atx_tid *tid, *last_tid;
1833 struct list_head *ac_list;
1836 if (txq->mac80211_qnum < 0)
1839 spin_lock_bh(&sc->chan_lock);
1840 ac_list = &sc->cur_chan->acq[txq->mac80211_qnum];
1841 spin_unlock_bh(&sc->chan_lock);
1843 if (test_bit(ATH_OP_HW_RESET, &common->op_flags) ||
1844 list_empty(ac_list))
1847 spin_lock_bh(&sc->chan_lock);
1850 last_ac = list_entry(ac_list->prev, struct ath_atx_ac, list);
1851 while (!list_empty(ac_list)) {
1854 if (sc->cur_chan->stopped)
1857 ac = list_first_entry(ac_list, struct ath_atx_ac, list);
1858 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1859 list_del(&ac->list);
1862 while (!list_empty(&ac->tid_q)) {
1864 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1866 list_del(&tid->list);
1869 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1873 * add tid to round-robin queue if more frames
1874 * are pending for the tid
1876 if (ath_tid_has_buffered(tid))
1877 ath_tx_queue_tid(sc, txq, tid);
1879 if (stop || tid == last_tid)
1883 if (!list_empty(&ac->tid_q) && !ac->sched) {
1885 list_add_tail(&ac->list, ac_list);
1891 if (ac == last_ac) {
1896 last_ac = list_entry(ac_list->prev,
1897 struct ath_atx_ac, list);
1902 spin_unlock_bh(&sc->chan_lock);
1905 void ath_txq_schedule_all(struct ath_softc *sc)
1907 struct ath_txq *txq;
1910 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1911 txq = sc->tx.txq_map[i];
1913 spin_lock_bh(&txq->axq_lock);
1914 ath_txq_schedule(sc, txq);
1915 spin_unlock_bh(&txq->axq_lock);
1924 * Insert a chain of ath_buf (descriptors) on a txq and
1925 * assume the descriptors are already chained together by caller.
1927 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1928 struct list_head *head, bool internal)
1930 struct ath_hw *ah = sc->sc_ah;
1931 struct ath_common *common = ath9k_hw_common(ah);
1932 struct ath_buf *bf, *bf_last;
1933 bool puttxbuf = false;
1937 * Insert the frame on the outbound list and
1938 * pass it on to the hardware.
1941 if (list_empty(head))
1944 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1945 bf = list_first_entry(head, struct ath_buf, list);
1946 bf_last = list_entry(head->prev, struct ath_buf, list);
1948 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1949 txq->axq_qnum, txq->axq_depth);
1951 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1952 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1953 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1956 list_splice_tail_init(head, &txq->axq_q);
1958 if (txq->axq_link) {
1959 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1960 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1961 txq->axq_qnum, txq->axq_link,
1962 ito64(bf->bf_daddr), bf->bf_desc);
1966 txq->axq_link = bf_last->bf_desc;
1970 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1971 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1972 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1973 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1976 if (!edma || sc->tx99_state) {
1977 TX_STAT_INC(txq->axq_qnum, txstart);
1978 ath9k_hw_txstart(ah, txq->axq_qnum);
1984 if (bf_is_ampdu_not_probing(bf))
1985 txq->axq_ampdu_depth++;
1987 bf_last = bf->bf_lastbf;
1988 bf = bf_last->bf_next;
1989 bf_last->bf_next = NULL;
1994 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1995 struct ath_atx_tid *tid, struct sk_buff *skb)
1997 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1998 struct ath_frame_info *fi = get_frame_info(skb);
1999 struct list_head bf_head;
2000 struct ath_buf *bf = fi->bf;
2002 INIT_LIST_HEAD(&bf_head);
2003 list_add_tail(&bf->list, &bf_head);
2004 bf->bf_state.bf_type = 0;
2005 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2006 bf->bf_state.bf_type = BUF_AMPDU;
2007 ath_tx_addto_baw(sc, tid, bf);
2012 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2013 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2014 TX_STAT_INC(txq->axq_qnum, queued);
2017 static void setup_frame_info(struct ieee80211_hw *hw,
2018 struct ieee80211_sta *sta,
2019 struct sk_buff *skb,
2022 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2023 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2024 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2025 const struct ieee80211_rate *rate;
2026 struct ath_frame_info *fi = get_frame_info(skb);
2027 struct ath_node *an = NULL;
2028 enum ath9k_key_type keytype;
2029 bool short_preamble = false;
2032 * We check if Short Preamble is needed for the CTS rate by
2033 * checking the BSS's global flag.
2034 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2036 if (tx_info->control.vif &&
2037 tx_info->control.vif->bss_conf.use_short_preamble)
2038 short_preamble = true;
2040 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2041 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2044 an = (struct ath_node *) sta->drv_priv;
2046 memset(fi, 0, sizeof(*fi));
2049 fi->keyix = hw_key->hw_key_idx;
2050 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2051 fi->keyix = an->ps_key;
2053 fi->keyix = ATH9K_TXKEYIX_INVALID;
2054 fi->keytype = keytype;
2055 fi->framelen = framelen;
2059 fi->rtscts_rate = rate->hw_value;
2061 fi->rtscts_rate |= rate->hw_value_short;
2064 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2066 struct ath_hw *ah = sc->sc_ah;
2067 struct ath9k_channel *curchan = ah->curchan;
2069 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2070 (chainmask == 0x7) && (rate < 0x90))
2072 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2080 * Assign a descriptor (and sequence number if necessary,
2081 * and map buffer for DMA. Frees skb on error
2083 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2084 struct ath_txq *txq,
2085 struct ath_atx_tid *tid,
2086 struct sk_buff *skb)
2088 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2089 struct ath_frame_info *fi = get_frame_info(skb);
2090 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2095 bf = ath_tx_get_buffer(sc);
2097 ath_dbg(common, XMIT, "TX buffers are full\n");
2101 ATH_TXBUF_RESET(bf);
2103 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2104 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2105 seqno = tid->seq_next;
2106 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2109 hdr->seq_ctrl |= cpu_to_le16(fragno);
2111 if (!ieee80211_has_morefrags(hdr->frame_control))
2112 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2114 bf->bf_state.seqno = seqno;
2119 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2120 skb->len, DMA_TO_DEVICE);
2121 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2123 bf->bf_buf_addr = 0;
2124 ath_err(ath9k_hw_common(sc->sc_ah),
2125 "dma_mapping_error() on TX\n");
2126 ath_tx_return_buffer(sc, bf);
2135 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2136 struct ath_tx_control *txctl)
2138 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2139 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2140 struct ieee80211_sta *sta = txctl->sta;
2141 struct ieee80211_vif *vif = info->control.vif;
2142 struct ath_vif *avp;
2143 struct ath_softc *sc = hw->priv;
2144 int frmlen = skb->len + FCS_LEN;
2145 int padpos, padsize;
2147 /* NOTE: sta can be NULL according to net/mac80211.h */
2149 txctl->an = (struct ath_node *)sta->drv_priv;
2150 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2151 avp = (void *)vif->drv_priv;
2152 txctl->an = &avp->mcast_node;
2155 if (info->control.hw_key)
2156 frmlen += info->control.hw_key->icv_len;
2159 * As a temporary workaround, assign seq# here; this will likely need
2160 * to be cleaned up to work better with Beacon transmission and virtual
2163 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2164 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2165 sc->tx.seq_no += 0x10;
2166 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2167 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2170 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2171 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2172 !ieee80211_is_data(hdr->frame_control))
2173 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2175 /* Add the padding after the header if this is not already done */
2176 padpos = ieee80211_hdrlen(hdr->frame_control);
2177 padsize = padpos & 3;
2178 if (padsize && skb->len > padpos) {
2179 if (skb_headroom(skb) < padsize)
2182 skb_push(skb, padsize);
2183 memmove(skb->data, skb->data + padsize, padpos);
2186 setup_frame_info(hw, sta, skb, frmlen);
2191 /* Upon failure caller should free skb */
2192 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2193 struct ath_tx_control *txctl)
2195 struct ieee80211_hdr *hdr;
2196 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2197 struct ieee80211_sta *sta = txctl->sta;
2198 struct ieee80211_vif *vif = info->control.vif;
2199 struct ath_frame_info *fi = get_frame_info(skb);
2200 struct ath_vif *avp = NULL;
2201 struct ath_softc *sc = hw->priv;
2202 struct ath_txq *txq = txctl->txq;
2203 struct ath_atx_tid *tid = NULL;
2210 avp = (void *)vif->drv_priv;
2212 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
2213 txctl->force_channel = true;
2215 ret = ath_tx_prepare(hw, skb, txctl);
2219 hdr = (struct ieee80211_hdr *) skb->data;
2221 * At this point, the vif, hw_key and sta pointers in the tx control
2222 * info are no longer valid (overwritten by the ath_frame_info data.
2225 q = skb_get_queue_mapping(skb);
2226 hw_queue = (info->hw_queue >= sc->hw->queues - 2) ? q : info->hw_queue;
2228 ath_txq_lock(sc, txq);
2229 if (txq == sc->tx.txq_map[q]) {
2231 if (++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2233 ieee80211_stop_queue(sc->hw, hw_queue);
2234 txq->stopped = true;
2238 queue = ieee80211_is_data_present(hdr->frame_control);
2240 /* Force queueing of all frames that belong to a virtual interface on
2241 * a different channel context, to ensure that they are sent on the
2244 if (((avp && avp->chanctx != sc->cur_chan) ||
2245 sc->cur_chan->stopped) && !txctl->force_channel) {
2247 txctl->an = &avp->mcast_node;
2248 info->flags &= ~IEEE80211_TX_CTL_PS_RESPONSE;
2252 if (txctl->an && queue)
2253 tid = ath_get_skb_tid(sc, txctl->an, skb);
2255 if (info->flags & (IEEE80211_TX_CTL_PS_RESPONSE |
2256 IEEE80211_TX_CTL_TX_OFFCHAN)) {
2257 ath_txq_unlock(sc, txq);
2258 txq = sc->tx.uapsdq;
2259 ath_txq_lock(sc, txq);
2260 } else if (txctl->an && queue) {
2261 WARN_ON(tid->ac->txq != txctl->txq);
2263 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2264 tid->ac->clear_ps_filter = true;
2267 * Add this frame to software queue for scheduling later
2270 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2271 __skb_queue_tail(&tid->buf_q, skb);
2272 if (!txctl->an->sleeping)
2273 ath_tx_queue_tid(sc, txq, tid);
2275 ath_txq_schedule(sc, txq);
2279 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2281 ath_txq_skb_done(sc, txq, skb);
2283 dev_kfree_skb_any(skb);
2285 ieee80211_free_txskb(sc->hw, skb);
2289 bf->bf_state.bfs_paprd = txctl->paprd;
2292 bf->bf_state.bfs_paprd_timestamp = jiffies;
2294 ath_set_rates(vif, sta, bf);
2295 ath_tx_send_normal(sc, txq, tid, skb);
2298 ath_txq_unlock(sc, txq);
2303 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2304 struct sk_buff *skb)
2306 struct ath_softc *sc = hw->priv;
2307 struct ath_tx_control txctl = {
2308 .txq = sc->beacon.cabq
2310 struct ath_tx_info info = {};
2311 struct ieee80211_hdr *hdr;
2312 struct ath_buf *bf_tail = NULL;
2319 sc->cur_chan->beacon.beacon_interval * 1000 *
2320 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2323 struct ath_frame_info *fi = get_frame_info(skb);
2325 if (ath_tx_prepare(hw, skb, &txctl))
2328 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2333 ath_set_rates(vif, NULL, bf);
2334 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2335 duration += info.rates[0].PktDuration;
2337 bf_tail->bf_next = bf;
2339 list_add_tail(&bf->list, &bf_q);
2343 if (duration > max_duration)
2346 skb = ieee80211_get_buffered_bc(hw, vif);
2350 ieee80211_free_txskb(hw, skb);
2352 if (list_empty(&bf_q))
2355 bf = list_first_entry(&bf_q, struct ath_buf, list);
2356 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2358 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2359 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2360 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2361 sizeof(*hdr), DMA_TO_DEVICE);
2364 ath_txq_lock(sc, txctl.txq);
2365 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2366 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2367 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2368 ath_txq_unlock(sc, txctl.txq);
2375 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2376 int tx_flags, struct ath_txq *txq)
2378 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2379 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2380 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2381 int padpos, padsize;
2382 unsigned long flags;
2384 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2386 if (sc->sc_ah->caldata)
2387 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2389 if (!(tx_flags & ATH_TX_ERROR))
2390 /* Frame was ACKed */
2391 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2393 padpos = ieee80211_hdrlen(hdr->frame_control);
2394 padsize = padpos & 3;
2395 if (padsize && skb->len>padpos+padsize) {
2397 * Remove MAC header padding before giving the frame back to
2400 memmove(skb->data + padsize, skb->data, padpos);
2401 skb_pull(skb, padsize);
2404 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2405 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2406 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2408 "Going back to sleep after having received TX status (0x%lx)\n",
2409 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2411 PS_WAIT_FOR_PSPOLL_DATA |
2412 PS_WAIT_FOR_TX_ACK));
2414 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2416 __skb_queue_tail(&txq->complete_q, skb);
2417 ath_txq_skb_done(sc, txq, skb);
2420 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2421 struct ath_txq *txq, struct list_head *bf_q,
2422 struct ath_tx_status *ts, int txok)
2424 struct sk_buff *skb = bf->bf_mpdu;
2425 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2426 unsigned long flags;
2430 tx_flags |= ATH_TX_ERROR;
2432 if (ts->ts_status & ATH9K_TXERR_FILT)
2433 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2435 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2436 bf->bf_buf_addr = 0;
2438 goto skip_tx_complete;
2440 if (bf->bf_state.bfs_paprd) {
2441 if (time_after(jiffies,
2442 bf->bf_state.bfs_paprd_timestamp +
2443 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2444 dev_kfree_skb_any(skb);
2446 complete(&sc->paprd_complete);
2448 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2449 ath_tx_complete(sc, skb, tx_flags, txq);
2452 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2453 * accidentally reference it later.
2458 * Return the list of ath_buf of this mpdu to free queue
2460 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2461 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2462 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2465 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2466 struct ath_tx_status *ts, int nframes, int nbad,
2469 struct sk_buff *skb = bf->bf_mpdu;
2470 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2471 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2472 struct ieee80211_hw *hw = sc->hw;
2473 struct ath_hw *ah = sc->sc_ah;
2477 tx_info->status.ack_signal = ts->ts_rssi;
2479 tx_rateindex = ts->ts_rateindex;
2480 WARN_ON(tx_rateindex >= hw->max_rates);
2482 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2483 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2485 BUG_ON(nbad > nframes);
2487 tx_info->status.ampdu_len = nframes;
2488 tx_info->status.ampdu_ack_len = nframes - nbad;
2490 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2491 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2493 * If an underrun error is seen assume it as an excessive
2494 * retry only if max frame trigger level has been reached
2495 * (2 KB for single stream, and 4 KB for dual stream).
2496 * Adjust the long retry as if the frame was tried
2497 * hw->max_rate_tries times to affect how rate control updates
2498 * PER for the failed rate.
2499 * In case of congestion on the bus penalizing this type of
2500 * underruns should help hardware actually transmit new frames
2501 * successfully by eventually preferring slower rates.
2502 * This itself should also alleviate congestion on the bus.
2504 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2505 ATH9K_TX_DELIM_UNDERRUN)) &&
2506 ieee80211_is_data(hdr->frame_control) &&
2507 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2508 tx_info->status.rates[tx_rateindex].count =
2512 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2513 tx_info->status.rates[i].count = 0;
2514 tx_info->status.rates[i].idx = -1;
2517 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2520 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2522 struct ath_hw *ah = sc->sc_ah;
2523 struct ath_common *common = ath9k_hw_common(ah);
2524 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2525 struct list_head bf_head;
2526 struct ath_desc *ds;
2527 struct ath_tx_status ts;
2530 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2531 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2534 ath_txq_lock(sc, txq);
2536 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2539 if (list_empty(&txq->axq_q)) {
2540 txq->axq_link = NULL;
2541 ath_txq_schedule(sc, txq);
2544 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2547 * There is a race condition that a BH gets scheduled
2548 * after sw writes TxE and before hw re-load the last
2549 * descriptor to get the newly chained one.
2550 * Software must keep the last DONE descriptor as a
2551 * holding descriptor - software does so by marking
2552 * it with the STALE flag.
2555 if (bf->bf_state.stale) {
2557 if (list_is_last(&bf_held->list, &txq->axq_q))
2560 bf = list_entry(bf_held->list.next, struct ath_buf,
2564 lastbf = bf->bf_lastbf;
2565 ds = lastbf->bf_desc;
2567 memset(&ts, 0, sizeof(ts));
2568 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2569 if (status == -EINPROGRESS)
2572 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2575 * Remove ath_buf's of the same transmit unit from txq,
2576 * however leave the last descriptor back as the holding
2577 * descriptor for hw.
2579 lastbf->bf_state.stale = true;
2580 INIT_LIST_HEAD(&bf_head);
2581 if (!list_is_singular(&lastbf->list))
2582 list_cut_position(&bf_head,
2583 &txq->axq_q, lastbf->list.prev);
2586 list_del(&bf_held->list);
2587 ath_tx_return_buffer(sc, bf_held);
2590 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2592 ath_txq_unlock_complete(sc, txq);
2595 void ath_tx_tasklet(struct ath_softc *sc)
2597 struct ath_hw *ah = sc->sc_ah;
2598 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2601 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2602 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2603 ath_tx_processq(sc, &sc->tx.txq[i]);
2607 void ath_tx_edma_tasklet(struct ath_softc *sc)
2609 struct ath_tx_status ts;
2610 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2611 struct ath_hw *ah = sc->sc_ah;
2612 struct ath_txq *txq;
2613 struct ath_buf *bf, *lastbf;
2614 struct list_head bf_head;
2615 struct list_head *fifo_list;
2619 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2622 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2623 if (status == -EINPROGRESS)
2625 if (status == -EIO) {
2626 ath_dbg(common, XMIT, "Error processing tx status\n");
2630 /* Process beacon completions separately */
2631 if (ts.qid == sc->beacon.beaconq) {
2632 sc->beacon.tx_processed = true;
2633 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2635 ath_chanctx_event(sc, NULL,
2636 ATH_CHANCTX_EVENT_BEACON_SENT);
2637 ath9k_csa_update(sc);
2641 txq = &sc->tx.txq[ts.qid];
2643 ath_txq_lock(sc, txq);
2645 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2647 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2648 if (list_empty(fifo_list)) {
2649 ath_txq_unlock(sc, txq);
2653 bf = list_first_entry(fifo_list, struct ath_buf, list);
2654 if (bf->bf_state.stale) {
2655 list_del(&bf->list);
2656 ath_tx_return_buffer(sc, bf);
2657 bf = list_first_entry(fifo_list, struct ath_buf, list);
2660 lastbf = bf->bf_lastbf;
2662 INIT_LIST_HEAD(&bf_head);
2663 if (list_is_last(&lastbf->list, fifo_list)) {
2664 list_splice_tail_init(fifo_list, &bf_head);
2665 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2667 if (!list_empty(&txq->axq_q)) {
2668 struct list_head bf_q;
2670 INIT_LIST_HEAD(&bf_q);
2671 txq->axq_link = NULL;
2672 list_splice_tail_init(&txq->axq_q, &bf_q);
2673 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2676 lastbf->bf_state.stale = true;
2678 list_cut_position(&bf_head, fifo_list,
2682 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2683 ath_txq_unlock_complete(sc, txq);
2691 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2693 struct ath_descdma *dd = &sc->txsdma;
2694 u8 txs_len = sc->sc_ah->caps.txs_len;
2696 dd->dd_desc_len = size * txs_len;
2697 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2698 &dd->dd_desc_paddr, GFP_KERNEL);
2705 static int ath_tx_edma_init(struct ath_softc *sc)
2709 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2711 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2712 sc->txsdma.dd_desc_paddr,
2713 ATH_TXSTATUS_RING_SIZE);
2718 int ath_tx_init(struct ath_softc *sc, int nbufs)
2720 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2723 spin_lock_init(&sc->tx.txbuflock);
2725 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2729 "Failed to allocate tx descriptors: %d\n", error);
2733 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2734 "beacon", ATH_BCBUF, 1, 1);
2737 "Failed to allocate beacon descriptors: %d\n", error);
2741 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2743 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2744 error = ath_tx_edma_init(sc);
2749 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2751 struct ath_atx_tid *tid;
2752 struct ath_atx_ac *ac;
2755 for (tidno = 0, tid = &an->tid[tidno];
2756 tidno < IEEE80211_NUM_TIDS;
2760 tid->seq_start = tid->seq_next = 0;
2761 tid->baw_size = WME_MAX_BA;
2762 tid->baw_head = tid->baw_tail = 0;
2764 tid->active = false;
2765 __skb_queue_head_init(&tid->buf_q);
2766 __skb_queue_head_init(&tid->retry_q);
2767 acno = TID_TO_WME_AC(tidno);
2768 tid->ac = &an->ac[acno];
2771 for (acno = 0, ac = &an->ac[acno];
2772 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2774 ac->clear_ps_filter = true;
2775 ac->txq = sc->tx.txq_map[acno];
2776 INIT_LIST_HEAD(&ac->tid_q);
2780 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2782 struct ath_atx_ac *ac;
2783 struct ath_atx_tid *tid;
2784 struct ath_txq *txq;
2787 for (tidno = 0, tid = &an->tid[tidno];
2788 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2793 ath_txq_lock(sc, txq);
2796 list_del(&tid->list);
2801 list_del(&ac->list);
2802 tid->ac->sched = false;
2805 ath_tid_drain(sc, txq, tid);
2806 tid->active = false;
2808 ath_txq_unlock(sc, txq);
2812 #ifdef CONFIG_ATH9K_TX99
2814 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2815 struct ath_tx_control *txctl)
2817 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2818 struct ath_frame_info *fi = get_frame_info(skb);
2819 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2821 int padpos, padsize;
2823 padpos = ieee80211_hdrlen(hdr->frame_control);
2824 padsize = padpos & 3;
2826 if (padsize && skb->len > padpos) {
2827 if (skb_headroom(skb) < padsize) {
2828 ath_dbg(common, XMIT,
2829 "tx99 padding failed\n");
2833 skb_push(skb, padsize);
2834 memmove(skb->data, skb->data + padsize, padpos);
2837 fi->keyix = ATH9K_TXKEYIX_INVALID;
2838 fi->framelen = skb->len + FCS_LEN;
2839 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2841 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2843 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2847 ath_set_rates(sc->tx99_vif, NULL, bf);
2849 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2850 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2852 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2857 #endif /* CONFIG_ATH9K_TX99 */