drivers/net/wireless/ath/wil6210/interrupt.c

   1 /*
   2  * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/interrupt.h>
  18
  19 #include "wil6210.h"
  20 #include "trace.h"
  21
  22 /**
  23  * Theory of operation:
  24  *
  25  * There is ISR pseudo-cause register,
  26  * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
  27  * Its bits represents OR'ed bits from 3 real ISR registers:
  28  * TX, RX, and MISC.
  29  *
  30  * Registers may be configured to either "write 1 to clear" or
  31  * "clear on read" mode
  32  *
  33  * When handling interrupt, one have to mask/unmask interrupts for the
  34  * real ISR registers, or hardware may malfunction.
  35  *
  36  */
  37
  38 #define WIL6210_IRQ_DISABLE             (0xFFFFFFFFUL)
  39 #define WIL6210_IRQ_DISABLE_NO_HALP     (0xF7FFFFFFUL)
  40 #define WIL6210_IMC_RX          (BIT_DMA_EP_RX_ICR_RX_DONE | \
  41                                  BIT_DMA_EP_RX_ICR_RX_HTRSH)
  42 #define WIL6210_IMC_RX_NO_RX_HTRSH (WIL6210_IMC_RX & \
  43                                     (~(BIT_DMA_EP_RX_ICR_RX_HTRSH)))
  44 #define WIL6210_IMC_TX          (BIT_DMA_EP_TX_ICR_TX_DONE | \
  45                                 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
  46 #define WIL6210_IMC_MISC_NO_HALP        (ISR_MISC_FW_READY | \
  47                                          ISR_MISC_MBOX_EVT | \
  48                                          ISR_MISC_FW_ERROR)
  49 #define WIL6210_IMC_MISC                (WIL6210_IMC_MISC_NO_HALP | \
  50                                          BIT_DMA_EP_MISC_ICR_HALP)
  51 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
  52                                         BIT_DMA_PSEUDO_CAUSE_TX | \
  53                                         BIT_DMA_PSEUDO_CAUSE_MISC))
  54
  55 #if defined(CONFIG_WIL6210_ISR_COR)
  56 /* configure to Clear-On-Read mode */
  57 #define WIL_ICR_ICC_VALUE       (0xFFFFFFFFUL)
  58 #define WIL_ICR_ICC_MISC_VALUE  (0xF7FFFFFFUL)
  59
  60 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  61 {
  62 }
  63 #else /* defined(CONFIG_WIL6210_ISR_COR) */
  64 /* configure to Write-1-to-Clear mode */
  65 #define WIL_ICR_ICC_VALUE       (0UL)
  66 #define WIL_ICR_ICC_MISC_VALUE  (0UL)
  67
  68 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  69 {
  70         writel(x, addr);
  71 }
  72 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
  73
  74 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
  75 {
  76         u32 x = readl(addr);
  77
  78         wil_icr_clear(x, addr);
  79
  80         return x;
  81 }
  82
  83 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
  84 {
  85         wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),
  86               WIL6210_IRQ_DISABLE);
  87 }
  88
  89 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
  90 {
  91         wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),
  92               WIL6210_IRQ_DISABLE);
  93 }
  94
  95 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp)
  96 {
  97         wil_dbg_irq(wil, "%s: mask_halp(%s)\n", __func__,
  98                     mask_halp ? "true" : "false");
  99
 100         wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
 101               mask_halp ? WIL6210_IRQ_DISABLE : WIL6210_IRQ_DISABLE_NO_HALP);
 102 }
 103
 104 void wil6210_mask_halp(struct wil6210_priv *wil)
 105 {
 106         wil_dbg_irq(wil, "%s()\n", __func__);
 107
 108         wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
 109               BIT_DMA_EP_MISC_ICR_HALP);
 110 }
 111
 112 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
 113 {
 114         wil_dbg_irq(wil, "%s()\n", __func__);
 115
 116         wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);
 117
 118         clear_bit(wil_status_irqen, wil->status);
 119 }
 120
 121 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
 122 {
 123         wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),
 124               WIL6210_IMC_TX);
 125 }
 126
 127 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
 128 {
 129         bool unmask_rx_htrsh = test_bit(wil_status_fwconnected, wil->status);
 130
 131         wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),
 132               unmask_rx_htrsh ? WIL6210_IMC_RX : WIL6210_IMC_RX_NO_RX_HTRSH);
 133 }
 134
 135 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp)
 136 {
 137         wil_dbg_irq(wil, "%s: unmask_halp(%s)\n", __func__,
 138                     unmask_halp ? "true" : "false");
 139
 140         wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
 141               unmask_halp ? WIL6210_IMC_MISC : WIL6210_IMC_MISC_NO_HALP);
 142 }
 143
 144 static void wil6210_unmask_halp(struct wil6210_priv *wil)
 145 {
 146         wil_dbg_irq(wil, "%s()\n", __func__);
 147
 148         wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
 149               BIT_DMA_EP_MISC_ICR_HALP);
 150 }
 151
 152 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
 153 {
 154         wil_dbg_irq(wil, "%s()\n", __func__);
 155
 156         set_bit(wil_status_irqen, wil->status);
 157
 158         wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);
 159 }
 160
 161 void wil_mask_irq(struct wil6210_priv *wil)
 162 {
 163         wil_dbg_irq(wil, "%s()\n", __func__);
 164
 165         wil6210_mask_irq_tx(wil);
 166         wil6210_mask_irq_rx(wil);
 167         wil6210_mask_irq_misc(wil, true);
 168         wil6210_mask_irq_pseudo(wil);
 169 }
 170
 171 void wil_unmask_irq(struct wil6210_priv *wil)
 172 {
 173         wil_dbg_irq(wil, "%s()\n", __func__);
 174
 175         wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),
 176               WIL_ICR_ICC_VALUE);
 177         wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
 178               WIL_ICR_ICC_VALUE);
 179         wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
 180               WIL_ICR_ICC_MISC_VALUE);
 181
 182         wil6210_unmask_irq_pseudo(wil);
 183         wil6210_unmask_irq_tx(wil);
 184         wil6210_unmask_irq_rx(wil);
 185         wil6210_unmask_irq_misc(wil, true);
 186 }
 187
 188 void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
 189 {
 190         wil_dbg_irq(wil, "%s()\n", __func__);
 191
 192         /* disable interrupt moderation for monitor
 193          * to get better timestamp precision
 194          */
 195         if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR)
 196                 return;
 197
 198         /* Disable and clear tx counter before (re)configuration */
 199         wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
 200         wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
 201         wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
 202                  wil->tx_max_burst_duration);
 203         /* Configure TX max burst duration timer to use usec units */
 204         wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,
 205               BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL);
 206
 207         /* Disable and clear tx idle counter before (re)configuration */
 208         wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
 209         wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
 210         wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
 211                  wil->tx_interframe_timeout);
 212         /* Configure TX max burst duration timer to use usec units */
 213         wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
 214               BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL);
 215
 216         /* Disable and clear rx counter before (re)configuration */
 217         wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
 218         wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
 219         wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
 220                  wil->rx_max_burst_duration);
 221         /* Configure TX max burst duration timer to use usec units */
 222         wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,
 223               BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL);
 224
 225         /* Disable and clear rx idle counter before (re)configuration */
 226         wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
 227         wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
 228         wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
 229                  wil->rx_interframe_timeout);
 230         /* Configure TX max burst duration timer to use usec units */
 231         wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
 232               BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL);
 233 }
 234
 235 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
 236 {
 237         struct wil6210_priv *wil = cookie;
 238         u32 isr = wil_ioread32_and_clear(wil->csr +
 239                                          HOSTADDR(RGF_DMA_EP_RX_ICR) +
 240                                          offsetof(struct RGF_ICR, ICR));
 241         bool need_unmask = true;
 242
 243         trace_wil6210_irq_rx(isr);
 244         wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
 245
 246         if (unlikely(!isr)) {
 247                 wil_err(wil, "spurious IRQ: RX\n");
 248                 return IRQ_NONE;
 249         }
 250
 251         wil6210_mask_irq_rx(wil);
 252
 253         /* RX_DONE and RX_HTRSH interrupts are the same if interrupt
 254          * moderation is not used. Interrupt moderation may cause RX
 255          * buffer overflow while RX_DONE is delayed. The required
 256          * action is always the same - should empty the accumulated
 257          * packets from the RX ring.
 258          */
 259         if (likely(isr & (BIT_DMA_EP_RX_ICR_RX_DONE |
 260                           BIT_DMA_EP_RX_ICR_RX_HTRSH))) {
 261                 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n",
 262                             isr);
 263
 264                 isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE |
 265                          BIT_DMA_EP_RX_ICR_RX_HTRSH);
 266                 if (likely(test_bit(wil_status_fwready, wil->status))) {
 267                         if (likely(test_bit(wil_status_napi_en, wil->status))) {
 268                                 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
 269                                 need_unmask = false;
 270                                 napi_schedule(&wil->napi_rx);
 271                         } else {
 272                                 wil_err(wil,
 273                                         "Got Rx interrupt while stopping interface\n");
 274                         }
 275                 } else {
 276                         wil_err(wil, "Got Rx interrupt while in reset\n");
 277                 }
 278         }
 279
 280         if (unlikely(isr))
 281                 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
 282
 283         /* Rx IRQ will be enabled when NAPI processing finished */
 284
 285         atomic_inc(&wil->isr_count_rx);
 286
 287         if (unlikely(need_unmask))
 288                 wil6210_unmask_irq_rx(wil);
 289
 290         return IRQ_HANDLED;
 291 }
 292
 293 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
 294 {
 295         struct wil6210_priv *wil = cookie;
 296         u32 isr = wil_ioread32_and_clear(wil->csr +
 297                                          HOSTADDR(RGF_DMA_EP_TX_ICR) +
 298                                          offsetof(struct RGF_ICR, ICR));
 299         bool need_unmask = true;
 300
 301         trace_wil6210_irq_tx(isr);
 302         wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
 303
 304         if (unlikely(!isr)) {
 305                 wil_err(wil, "spurious IRQ: TX\n");
 306                 return IRQ_NONE;
 307         }
 308
 309         wil6210_mask_irq_tx(wil);
 310
 311         if (likely(isr & BIT_DMA_EP_TX_ICR_TX_DONE)) {
 312                 wil_dbg_irq(wil, "TX done\n");
 313                 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
 314                 /* clear also all VRING interrupts */
 315                 isr &= ~(BIT(25) - 1UL);
 316                 if (likely(test_bit(wil_status_fwready, wil->status))) {
 317                         wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
 318                         need_unmask = false;
 319                         napi_schedule(&wil->napi_tx);
 320                 } else {
 321                         wil_err(wil, "Got Tx interrupt while in reset\n");
 322                 }
 323         }
 324
 325         if (unlikely(isr))
 326                 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
 327
 328         /* Tx IRQ will be enabled when NAPI processing finished */
 329
 330         atomic_inc(&wil->isr_count_tx);
 331
 332         if (unlikely(need_unmask))
 333                 wil6210_unmask_irq_tx(wil);
 334
 335         return IRQ_HANDLED;
 336 }
 337
 338 static void wil_notify_fw_error(struct wil6210_priv *wil)
 339 {
 340         struct device *dev = &wil_to_ndev(wil)->dev;
 341         char *envp[3] = {
 342                 [0] = "SOURCE=wil6210",
 343                 [1] = "EVENT=FW_ERROR",
 344                 [2] = NULL,
 345         };
 346         wil_err(wil, "Notify about firmware error\n");
 347         kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
 348 }
 349
 350 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
 351 {
 352         /* make shadow copy of registers that should not change on run time */
 353         wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
 354                              sizeof(struct wil6210_mbox_ctl));
 355         wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
 356         wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
 357 }
 358
 359 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
 360 {
 361         struct wil6210_priv *wil = cookie;
 362         u32 isr = wil_ioread32_and_clear(wil->csr +
 363                                          HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 364                                          offsetof(struct RGF_ICR, ICR));
 365
 366         trace_wil6210_irq_misc(isr);
 367         wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
 368
 369         if (!isr) {
 370                 wil_err(wil, "spurious IRQ: MISC\n");
 371                 return IRQ_NONE;
 372         }
 373
 374         wil6210_mask_irq_misc(wil, false);
 375
 376         if (isr & ISR_MISC_FW_ERROR) {
 377                 u32 fw_assert_code = wil_r(wil, RGF_FW_ASSERT_CODE);
 378                 u32 ucode_assert_code = wil_r(wil, RGF_UCODE_ASSERT_CODE);
 379
 380                 wil_err(wil,
 381                         "Firmware error detected, assert codes FW 0x%08x, UCODE 0x%08x\n",
 382                         fw_assert_code, ucode_assert_code);
 383                 clear_bit(wil_status_fwready, wil->status);
 384                 /*
 385                  * do not clear @isr here - we do 2-nd part in thread
 386                  * there, user space get notified, and it should be done
 387                  * in non-atomic context
 388                  */
 389         }
 390
 391         if (isr & ISR_MISC_FW_READY) {
 392                 wil_dbg_irq(wil, "IRQ: FW ready\n");
 393                 wil_cache_mbox_regs(wil);
 394                 set_bit(wil_status_mbox_ready, wil->status);
 395                 /**
 396                  * Actual FW ready indicated by the
 397                  * WMI_FW_READY_EVENTID
 398                  */
 399                 isr &= ~ISR_MISC_FW_READY;
 400         }
 401
 402         if (isr & BIT_DMA_EP_MISC_ICR_HALP) {
 403                 wil_dbg_irq(wil, "%s: HALP IRQ invoked\n", __func__);
 404                 wil6210_mask_halp(wil);
 405                 isr &= ~BIT_DMA_EP_MISC_ICR_HALP;
 406                 complete(&wil->halp.comp);
 407         }
 408
 409         wil->isr_misc = isr;
 410
 411         if (isr) {
 412                 return IRQ_WAKE_THREAD;
 413         } else {
 414                 wil6210_unmask_irq_misc(wil, false);
 415                 return IRQ_HANDLED;
 416         }
 417 }
 418
 419 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
 420 {
 421         struct wil6210_priv *wil = cookie;
 422         u32 isr = wil->isr_misc;
 423
 424         trace_wil6210_irq_misc_thread(isr);
 425         wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
 426
 427         if (isr & ISR_MISC_FW_ERROR) {
 428                 wil->recovery_state = fw_recovery_pending;
 429                 wil_fw_core_dump(wil);
 430                 wil_notify_fw_error(wil);
 431                 isr &= ~ISR_MISC_FW_ERROR;
 432                 if (wil->platform_ops.notify) {
 433                         wil_err(wil, "notify platform driver about FW crash");
 434                         wil->platform_ops.notify(wil->platform_handle,
 435                                                  WIL_PLATFORM_EVT_FW_CRASH);
 436                 } else {
 437                         wil_fw_error_recovery(wil);
 438                 }
 439         }
 440         if (isr & ISR_MISC_MBOX_EVT) {
 441                 wil_dbg_irq(wil, "MBOX event\n");
 442                 wmi_recv_cmd(wil);
 443                 isr &= ~ISR_MISC_MBOX_EVT;
 444         }
 445
 446         if (isr)
 447                 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
 448
 449         wil->isr_misc = 0;
 450
 451         wil6210_unmask_irq_misc(wil, false);
 452
 453         return IRQ_HANDLED;
 454 }
 455
 456 /**
 457  * thread IRQ handler
 458  */
 459 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
 460 {
 461         struct wil6210_priv *wil = cookie;
 462
 463         wil_dbg_irq(wil, "Thread IRQ\n");
 464         /* Discover real IRQ cause */
 465         if (wil->isr_misc)
 466                 wil6210_irq_misc_thread(irq, cookie);
 467
 468         wil6210_unmask_irq_pseudo(wil);
 469
 470         return IRQ_HANDLED;
 471 }
 472
 473 /* DEBUG
 474  * There is subtle bug in hardware that causes IRQ to raise when it should be
 475  * masked. It is quite rare and hard to debug.
 476  *
 477  * Catch irq issue if it happens and print all I can.
 478  */
 479 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
 480 {
 481         if (!test_bit(wil_status_irqen, wil->status)) {
 482                 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
 483                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 484                                 offsetof(struct RGF_ICR, ICM));
 485                 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
 486                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 487                                 offsetof(struct RGF_ICR, ICR));
 488                 u32 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR +
 489                                    offsetof(struct RGF_ICR, IMV));
 490                 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
 491                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 492                                 offsetof(struct RGF_ICR, ICM));
 493                 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
 494                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 495                                 offsetof(struct RGF_ICR, ICR));
 496                 u32 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR +
 497                                    offsetof(struct RGF_ICR, IMV));
 498                 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
 499                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 500                                 offsetof(struct RGF_ICR, ICM));
 501                 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
 502                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 503                                 offsetof(struct RGF_ICR, ICR));
 504                 u32 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR +
 505                                      offsetof(struct RGF_ICR, IMV));
 506
 507                 /* HALP interrupt can be unmasked when misc interrupts are
 508                  * masked
 509                  */
 510                 if (icr_misc & BIT_DMA_EP_MISC_ICR_HALP)
 511                         return 0;
 512
 513                 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
 514                                 "Rx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 515                                 "Tx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 516                                 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
 517                                 pseudo_cause,
 518                                 icm_rx, icr_rx, imv_rx,
 519                                 icm_tx, icr_tx, imv_tx,
 520                                 icm_misc, icr_misc, imv_misc);
 521
 522                 return -EINVAL;
 523         }
 524
 525         return 0;
 526 }
 527
 528 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
 529 {
 530         irqreturn_t rc = IRQ_HANDLED;
 531         struct wil6210_priv *wil = cookie;
 532         u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE);
 533
 534         /**
 535          * pseudo_cause is Clear-On-Read, no need to ACK
 536          */
 537         if (unlikely((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff)))
 538                 return IRQ_NONE;
 539
 540         /* FIXME: IRQ mask debug */
 541         if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause)))
 542                 return IRQ_NONE;
 543
 544         trace_wil6210_irq_pseudo(pseudo_cause);
 545         wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
 546
 547         wil6210_mask_irq_pseudo(wil);
 548
 549         /* Discover real IRQ cause
 550          * There are 2 possible phases for every IRQ:
 551          * - hard IRQ handler called right here
 552          * - threaded handler called later
 553          *
 554          * Hard IRQ handler reads and clears ISR.
 555          *
 556          * If threaded handler requested, hard IRQ handler
 557          * returns IRQ_WAKE_THREAD and saves ISR register value
 558          * for the threaded handler use.
 559          *
 560          * voting for wake thread - need at least 1 vote
 561          */
 562         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
 563             (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
 564                 rc = IRQ_WAKE_THREAD;
 565
 566         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
 567             (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
 568                 rc = IRQ_WAKE_THREAD;
 569
 570         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
 571             (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
 572                 rc = IRQ_WAKE_THREAD;
 573
 574         /* if thread is requested, it will unmask IRQ */
 575         if (rc != IRQ_WAKE_THREAD)
 576                 wil6210_unmask_irq_pseudo(wil);
 577
 578         return rc;
 579 }
 580
 581 /* can't use wil_ioread32_and_clear because ICC value is not set yet */
 582 static inline void wil_clear32(void __iomem *addr)
 583 {
 584         u32 x = readl(addr);
 585
 586         writel(x, addr);
 587 }
 588
 589 void wil6210_clear_irq(struct wil6210_priv *wil)
 590 {
 591         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
 592                     offsetof(struct RGF_ICR, ICR));
 593         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
 594                     offsetof(struct RGF_ICR, ICR));
 595         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 596                     offsetof(struct RGF_ICR, ICR));
 597         wmb(); /* make sure write completed */
 598 }
 599
 600 void wil6210_set_halp(struct wil6210_priv *wil)
 601 {
 602         wil_dbg_irq(wil, "%s()\n", __func__);
 603
 604         wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),
 605               BIT_DMA_EP_MISC_ICR_HALP);
 606 }
 607
 608 void wil6210_clear_halp(struct wil6210_priv *wil)
 609 {
 610         wil_dbg_irq(wil, "%s()\n", __func__);
 611
 612         wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),
 613               BIT_DMA_EP_MISC_ICR_HALP);
 614         wil6210_unmask_halp(wil);
 615 }
 616
 617 int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi)
 618 {
 619         int rc;
 620
 621         wil_dbg_misc(wil, "%s(%s)\n", __func__, use_msi ? "MSI" : "INTx");
 622
 623         rc = request_threaded_irq(irq, wil6210_hardirq,
 624                                   wil6210_thread_irq,
 625                                   use_msi ? 0 : IRQF_SHARED,
 626                                   WIL_NAME, wil);
 627         return rc;
 628 }
 629
 630 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
 631 {
 632         wil_dbg_misc(wil, "%s()\n", __func__);
 633
 634         wil_mask_irq(wil);
 635         free_irq(irq, wil);
 636 }