2 * Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/netdevice.h>
21 #include <linux/wireless.h>
22 #include <net/cfg80211.h>
23 #include <linux/timex.h>
24 #include "wil_platform.h"
26 extern bool no_fw_recovery;
27 extern unsigned int mtu_max;
30 #define WIL_NAME "wil6210"
31 #define WIL_FW_NAME "wil6210.fw"
33 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */
36 * extract bits [@b0:@b1] (inclusive) from the value @x
37 * it should be @b0 <= @b1, or result is incorrect
39 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
41 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1);
44 #define WIL6210_MEM_SIZE (2*1024*1024UL)
46 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (9)
47 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (9)
48 /* limit ring size in range [32..32k] */
49 #define WIL_RING_SIZE_ORDER_MIN (5)
50 #define WIL_RING_SIZE_ORDER_MAX (15)
51 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */
52 #define WIL6210_MAX_CID (8) /* HW limit */
53 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */
54 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */
55 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */
56 /* Hardware offload block adds the following:
57 * 26 bytes - 3-address QoS data header
58 * 8 bytes - IV + EIV (for GCMP)
60 * 16 bytes - MIC (for GCMP)
63 #define WIL_MAX_MPDU_OVERHEAD (62)
65 /* Calculate MAC buffer size for the firmware. It includes all overhead,
66 * as it will go over the air, and need to be 8 byte aligned
68 static inline u32 wil_mtu2macbuf(u32 mtu)
70 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8);
73 /* MTU for Ethernet need to take into account 8-byte SNAP header
74 * to be added when encapsulating Ethernet frame into 802.11
76 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8)
77 /* Max supported by wil6210 value for interrupt threshold is 5sec. */
78 #define WIL6210_ITR_TRSH_MAX (5000000)
79 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (15) /* usec */
80 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (15) /* usec */
81 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
82 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
83 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */
84 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000)
85 #define WIL6210_SCAN_TO msecs_to_jiffies(10000)
87 /* Hardware definitions begin */
91 * RGF File | Host addr | FW addr
93 * user_rgf | 0x000000 | 0x880000
94 * dma_rgf | 0x001000 | 0x881000
95 * pcie_rgf | 0x002000 | 0x882000
99 /* Where various structures placed in host address space */
100 #define WIL6210_FW_HOST_OFF (0x880000UL)
102 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF)
105 * Interrupt control registers block
107 * each interrupt controlled by the same bit in all registers
110 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */
111 u32 ICR; /* Cause, W1C/COR depending on ICC */
112 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
113 u32 ICS; /* Cause Set, WO */
114 u32 IMV; /* Mask, RW+S/C */
115 u32 IMS; /* Mask Set, write 1 to set */
116 u32 IMC; /* Mask Clear, write 1 to clear */
119 /* registers - FW addresses */
120 #define RGF_USER_USAGE_1 (0x880004)
121 #define RGF_USER_USAGE_6 (0x880018)
122 #define RGF_USER_HW_MACHINE_STATE (0x8801dc)
123 #define HW_MACHINE_BOOT_DONE (0x3fffffd)
124 #define RGF_USER_USER_CPU_0 (0x8801e0)
125 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */
126 #define RGF_USER_MAC_CPU_0 (0x8801fc)
127 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */
128 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc)
129 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */
130 #define RGF_USER_CLKS_CTL_0 (0x880abc)
131 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */
132 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */
133 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04)
134 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08)
135 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c)
136 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10)
137 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)
138 #define BIT_HPAL_PERST_FROM_PAD BIT(6)
139 #define BIT_CAR_PERST_RST BIT(7)
140 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */
141 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18)
142 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18)
143 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c)
144 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */
145 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2)
147 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */
148 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0)
149 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */
150 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */
151 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0)
152 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1)
153 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */
154 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0)
155 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1)
156 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */
158 /* Legacy interrupt moderation control (before Sparrow v2)*/
159 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c)
160 #define RGF_DMA_ITR_CNT_DATA (0x881c60)
161 #define RGF_DMA_ITR_CNT_CRL (0x881c64)
162 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0)
163 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1)
164 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2)
165 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3)
166 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4)
168 /* New (sparrow v2+) interrupt moderation control */
169 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40)
170 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34)
171 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38)
172 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c)
173 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0)
174 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1)
175 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2)
176 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3)
177 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4)
178 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5)
179 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6)
180 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60)
181 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64)
182 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68)
183 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0)
184 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1)
185 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2)
186 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3)
187 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4)
188 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50)
189 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44)
190 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48)
191 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c)
192 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0)
193 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1)
194 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2)
195 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3)
196 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4)
197 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5)
198 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6)
199 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54)
200 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58)
201 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c)
202 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0)
203 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1)
204 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2)
205 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3)
206 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4)
208 #define RGF_DMA_PSEUDO_CAUSE (0x881c68)
209 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c)
210 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70)
211 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0)
212 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1)
213 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2)
215 #define RGF_HP_CTRL (0x88265c)
216 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4)
218 /* MAC timer, usec, for packet lifetime */
219 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8)
221 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */
222 #define RGF_CAF_OSC_CONTROL (0x88afa4)
223 #define BIT_CAF_OSC_XTAL_EN BIT(0)
224 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec)
225 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0)
227 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */
228 #define JTAG_DEV_ID_MARLON_B0 (0x0612072f)
229 #define JTAG_DEV_ID_SPARROW_A0 (0x0632072f)
230 #define JTAG_DEV_ID_SPARROW_A1 (0x1632072f)
231 #define JTAG_DEV_ID_SPARROW_B0 (0x2632072f)
235 HW_VER_MARLON_B0, /* JTAG_DEV_ID_MARLON_B0 */
236 HW_VER_SPARROW_A0, /* JTAG_DEV_ID_SPARROW_A0 */
237 HW_VER_SPARROW_A1, /* JTAG_DEV_ID_SPARROW_A1 */
238 HW_VER_SPARROW_B0, /* JTAG_DEV_ID_SPARROW_B0 */
241 /* popular locations */
242 #define HOST_MBOX HOSTADDR(RGF_USER_USER_SCRATCH_PAD)
243 #define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \
244 offsetof(struct RGF_ICR, ICS))
245 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
247 /* ISR register bits */
248 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0)
249 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1)
250 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3)
252 /* Hardware definitions end */
254 u32 from; /* linker address - from, inclusive */
255 u32 to; /* linker address - to, exclusive */
256 u32 host; /* PCI/Host address - BAR0 + 0x880000 */
257 const char *name; /* for debugfs */
260 /* array size should be in sync with actual definition in the wmi.c */
261 extern const struct fw_map fw_mapping[7];
264 * mk_cidxtid - construct @cidxtid field
268 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
270 static inline u8 mk_cidxtid(u8 cid, u8 tid)
272 return ((tid & 0xf) << 4) | (cid & 0xf);
276 * parse_cidxtid - parse @cidxtid field
277 * @cid: store CID value here
278 * @tid: store TID value here
280 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
282 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid)
284 *cid = cidxtid & 0xf;
285 *tid = (cidxtid >> 4) & 0xf;
288 struct wil6210_mbox_ring {
290 u16 entry_size; /* max. size of mbox entry, incl. all headers */
296 struct wil6210_mbox_ring_desc {
301 /* at HOST_OFF_WIL6210_MBOX_CTL */
302 struct wil6210_mbox_ctl {
303 struct wil6210_mbox_ring tx;
304 struct wil6210_mbox_ring rx;
307 struct wil6210_mbox_hdr {
309 __le16 len; /* payload, bytes after this header */
315 #define WIL_MBOX_HDR_TYPE_WMI (0)
317 /* max. value for wil6210_mbox_hdr.len */
318 #define MAX_MBOXITEM_SIZE (240)
321 * struct wil6210_mbox_hdr_wmi - WMI header
324 * 00 - default, created by FW
325 * 01..0f - WiFi ports, driver to create
328 * @id: command/event ID
329 * @timestamp: FW fills for events, free-running msec timer
331 struct wil6210_mbox_hdr_wmi {
338 struct pending_wmi_event {
339 struct list_head list;
341 struct wil6210_mbox_hdr hdr;
342 struct wil6210_mbox_hdr_wmi wmi;
347 enum { /* for wil_ctx.mapped_as */
348 wil_mapped_as_none = 0,
349 wil_mapped_as_single = 1,
350 wil_mapped_as_page = 2,
354 * struct wil_ctx - software context for Vring descriptor
366 volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */
367 u16 size; /* number of vring_desc elements */
370 u32 hwtail; /* write here to inform hw */
371 struct wil_ctx *ctx; /* ctx[size] - software context */
375 * Additional data for Tx Vring
377 struct vring_tx_data {
379 cycles_t idle, last_idle, begin;
380 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */
383 bool addba_in_progress; /* if set, agg_xxx is for request in progress */
386 enum { /* for wil6210_priv.status */
387 wil_status_fwready = 0,
388 wil_status_fwconnecting,
389 wil_status_fwconnected,
391 wil_status_reset_done,
392 wil_status_irqen, /* FIXME: interrupts enabled - for debug */
393 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */
394 wil_status_last /* keep last */
400 * struct tid_ampdu_rx - TID aggregation information (Rx).
402 * @reorder_buf: buffer to reorder incoming aggregated MPDUs
403 * @reorder_time: jiffies when skb was added
404 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value)
405 * @reorder_timer: releases expired frames from the reorder buffer.
406 * @last_rx: jiffies of last rx activity
407 * @head_seq_num: head sequence number in reordering buffer.
408 * @stored_mpdu_num: number of MPDUs in reordering buffer
409 * @ssn: Starting Sequence Number expected to be aggregated.
410 * @buf_size: buffer size for incoming A-MPDUs
411 * @timeout: reset timer value (in TUs).
412 * @dialog_token: dialog token for aggregation session
413 * @rcu_head: RCU head used for freeing this struct
415 * This structure's lifetime is managed by RCU, assignments to
416 * the array holding it must hold the aggregation mutex.
419 struct wil_tid_ampdu_rx {
420 struct sk_buff **reorder_buf;
421 unsigned long *reorder_time;
422 struct timer_list session_timer;
423 struct timer_list reorder_timer;
424 unsigned long last_rx;
432 bool first_time; /* is it 1-st time this buffer used? */
435 enum wil_sta_status {
437 wil_sta_conn_pending = 1,
438 wil_sta_connected = 2,
441 #define WIL_STA_TID_NUM (16)
443 struct wil_net_stats {
444 unsigned long rx_packets;
445 unsigned long tx_packets;
446 unsigned long rx_bytes;
447 unsigned long tx_bytes;
448 unsigned long tx_errors;
449 unsigned long rx_dropped;
454 * struct wil_sta_info - data for peer
456 * Peer identified by its CID (connection ID)
457 * NIC performs beam forming for each peer;
458 * if no beam forming done, frame exchange is not
461 struct wil_sta_info {
463 enum wil_sta_status status;
464 struct wil_net_stats stats;
465 bool data_port_open; /* can send any data, not only EAPOL */
467 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM];
468 spinlock_t tid_rx_lock; /* guarding tid_rx array */
469 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)];
470 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)];
474 fw_recovery_idle = 0,
475 fw_recovery_pending = 1,
476 fw_recovery_running = 2,
480 hw_capability_reset_v2 = 0,
481 hw_capability_advanced_itr_moderation = 1,
486 struct list_head list;
487 /* request params, converted to CPU byte order - what we asked for */
496 struct list_head list;
497 /* request params, converted to CPU byte order - what we asked for */
503 struct wil6210_priv {
504 struct pci_dev *pdev;
506 struct wireless_dev *wdev;
508 DECLARE_BITMAP(status, wil_status_last);
512 DECLARE_BITMAP(hw_capabilities, hw_capability_last);
513 u8 n_mids; /* number of additional MIDs as reported by FW */
514 u32 recovery_count; /* num of FW recovery attempts in a short time */
515 u32 recovery_state; /* FW recovery state machine */
516 unsigned long last_fw_recovery; /* jiffies of last fw recovery */
517 wait_queue_head_t wq; /* for all wait_event() use */
520 u32 secure_pcp; /* create secure PCP? */
522 /* interrupt moderation */
523 u32 tx_max_burst_duration;
524 u32 tx_interframe_timeout;
525 u32 rx_max_burst_duration;
526 u32 rx_interframe_timeout;
527 /* cached ISR registers */
529 /* mailbox related */
530 struct mutex wmi_mutex;
531 struct wil6210_mbox_ctl mbox_ctl;
532 struct completion wmi_ready;
533 struct completion wmi_call;
535 u16 reply_id; /**< wait for this WMI event */
538 struct workqueue_struct *wmi_wq; /* for deferred calls */
539 struct work_struct wmi_event_worker;
540 struct workqueue_struct *wq_service;
541 struct work_struct connect_worker;
542 struct work_struct disconnect_worker;
543 struct work_struct fw_error_worker; /* for FW error recovery */
544 struct timer_list connect_timer;
545 struct timer_list scan_timer; /* detect scan timeout */
546 int pending_connect_cid;
547 struct list_head pending_wmi_ev;
549 * protect pending_wmi_ev
550 * - fill in IRQ from wil6210_irq_misc,
551 * - consumed in thread by wmi_event_worker
553 spinlock_t wmi_ev_lock;
554 struct napi_struct napi_rx;
555 struct napi_struct napi_tx;
557 struct list_head back_rx_pending;
558 struct mutex back_rx_mutex; /* protect @back_rx_pending */
559 struct work_struct back_rx_worker;
560 struct list_head back_tx_pending;
561 struct mutex back_tx_mutex; /* protect @back_tx_pending */
562 struct work_struct back_tx_worker;
564 struct vring vring_rx;
565 struct vring vring_tx[WIL6210_MAX_TX_RINGS];
566 struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS];
567 u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */
568 struct wil_sta_info sta[WIL6210_MAX_CID];
570 struct cfg80211_scan_request *scan_request;
572 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
574 atomic_t isr_count_rx, isr_count_tx;
576 struct dentry *debug;
577 struct debugfs_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)];
579 void *platform_handle;
580 struct wil_platform_ops platform_ops;
583 #define wil_to_wiphy(i) (i->wdev->wiphy)
584 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
585 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
586 #define wil_to_wdev(i) (i->wdev)
587 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
588 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev)
589 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
592 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...);
594 void wil_err(struct wil6210_priv *wil, const char *fmt, ...);
596 void wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...);
598 void wil_info(struct wil6210_priv *wil, const char *fmt, ...);
599 #define wil_dbg(wil, fmt, arg...) do { \
600 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \
601 wil_dbg_trace(wil, fmt, ##arg); \
604 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
605 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
606 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
607 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
609 #if defined(CONFIG_DYNAMIC_DEBUG)
610 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \
611 groupsize, buf, len, ascii) \
612 print_hex_dump_debug("DBG[TXRX]" prefix_str,\
613 prefix_type, rowsize, \
614 groupsize, buf, len, ascii)
616 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \
617 groupsize, buf, len, ascii) \
618 print_hex_dump_debug("DBG[ WMI]" prefix_str,\
619 prefix_type, rowsize, \
620 groupsize, buf, len, ascii)
621 #else /* defined(CONFIG_DYNAMIC_DEBUG) */
623 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize,
624 int groupsize, const void *buf, size_t len, bool ascii)
629 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize,
630 int groupsize, const void *buf, size_t len, bool ascii)
633 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */
635 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
637 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
640 void *wil_if_alloc(struct device *dev, void __iomem *csr);
641 void wil_if_free(struct wil6210_priv *wil);
642 int wil_if_add(struct wil6210_priv *wil);
643 void wil_if_remove(struct wil6210_priv *wil);
644 int wil_priv_init(struct wil6210_priv *wil);
645 void wil_priv_deinit(struct wil6210_priv *wil);
646 int wil_reset(struct wil6210_priv *wil);
647 void wil_fw_error_recovery(struct wil6210_priv *wil);
648 void wil_set_recovery_state(struct wil6210_priv *wil, int state);
649 void wil_link_on(struct wil6210_priv *wil);
650 void wil_link_off(struct wil6210_priv *wil);
651 int wil_up(struct wil6210_priv *wil);
652 int __wil_up(struct wil6210_priv *wil);
653 int wil_down(struct wil6210_priv *wil);
654 int __wil_down(struct wil6210_priv *wil);
655 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r);
656 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac);
657 void wil_set_ethtoolops(struct net_device *ndev);
659 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr);
660 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr);
661 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr,
662 struct wil6210_mbox_hdr *hdr);
663 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len);
664 void wmi_recv_cmd(struct wil6210_priv *wil);
665 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len,
666 u16 reply_id, void *reply, u8 reply_size, int to_msec);
667 void wmi_event_worker(struct work_struct *work);
668 void wmi_event_flush(struct wil6210_priv *wil);
669 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid);
670 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid);
671 int wmi_set_channel(struct wil6210_priv *wil, int channel);
672 int wmi_get_channel(struct wil6210_priv *wil, int *channel);
673 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index,
674 const void *mac_addr);
675 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index,
676 const void *mac_addr, int key_len, const void *key);
677 int wmi_echo(struct wil6210_priv *wil);
678 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie);
679 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring);
680 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel);
681 int wmi_rxon(struct wil6210_priv *wil, bool on);
682 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r);
683 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason);
684 int wmi_addba(struct wil6210_priv *wil, u8 ringid, u8 size, u16 timeout);
685 int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason);
686 int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason);
687 int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token,
688 u16 status, bool amsdu, u16 agg_wsize, u16 timeout);
689 int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid,
690 u8 dialog_token, __le16 ba_param_set,
691 __le16 ba_timeout, __le16 ba_seq_ctrl);
692 void wil_back_rx_worker(struct work_struct *work);
693 void wil_back_rx_flush(struct wil6210_priv *wil);
694 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize);
695 void wil_back_tx_worker(struct work_struct *work);
696 void wil_back_tx_flush(struct wil6210_priv *wil);
698 void wil6210_clear_irq(struct wil6210_priv *wil);
699 int wil6210_init_irq(struct wil6210_priv *wil, int irq);
700 void wil6210_fini_irq(struct wil6210_priv *wil, int irq);
701 void wil_mask_irq(struct wil6210_priv *wil);
702 void wil_unmask_irq(struct wil6210_priv *wil);
703 void wil_configure_interrupt_moderation(struct wil6210_priv *wil);
704 void wil_disable_irq(struct wil6210_priv *wil);
705 void wil_enable_irq(struct wil6210_priv *wil);
706 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
707 struct cfg80211_mgmt_tx_params *params,
710 int wil6210_debugfs_init(struct wil6210_priv *wil);
711 void wil6210_debugfs_remove(struct wil6210_priv *wil);
712 int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid,
713 struct station_info *sinfo);
715 struct wireless_dev *wil_cfg80211_init(struct device *dev);
716 void wil_wdev_free(struct wil6210_priv *wil);
718 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr);
719 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan);
720 int wmi_pcp_stop(struct wil6210_priv *wil);
721 void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid,
722 u16 reason_code, bool from_event);
724 int wil_rx_init(struct wil6210_priv *wil, u16 size);
725 void wil_rx_fini(struct wil6210_priv *wil);
728 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size,
730 void wil_vring_fini_tx(struct wil6210_priv *wil, int id);
732 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev);
733 int wil_tx_complete(struct wil6210_priv *wil, int ringid);
734 void wil6210_unmask_irq_tx(struct wil6210_priv *wil);
737 void wil_rx_handle(struct wil6210_priv *wil, int *quota);
738 void wil6210_unmask_irq_rx(struct wil6210_priv *wil);
740 int wil_iftype_nl2wmi(enum nl80211_iftype type);
742 int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd);
743 int wil_request_firmware(struct wil6210_priv *wil, const char *name);
745 #endif /* __WIL6210_H__ */