3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
61 #include <linux/mmc/sdio_func.h>
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
116 static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
117 module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
118 MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
120 #ifdef CONFIG_B43_BCMA
121 static const struct bcma_device_id b43_bcma_tbl[] = {
122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
126 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
127 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
128 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
129 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
132 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
135 #ifdef CONFIG_B43_SSB
136 static const struct ssb_device_id b43_ssb_tbl[] = {
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
143 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
144 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
145 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
146 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
149 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
152 /* Channel and ratetables are shared for all devices.
153 * They can't be const, because ieee80211 puts some precalculated
154 * data in there. This data is the same for all devices, so we don't
155 * get concurrency issues */
156 #define RATETAB_ENT(_rateid, _flags) \
158 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
159 .hw_value = (_rateid), \
164 * NOTE: When changing this, sync with xmit.c's
165 * b43_plcp_get_bitrate_idx_* functions!
167 static struct ieee80211_rate __b43_ratetable[] = {
168 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
169 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
170 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
171 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
172 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
176 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
177 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
178 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
179 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
182 #define b43_a_ratetable (__b43_ratetable + 4)
183 #define b43_a_ratetable_size 8
184 #define b43_b_ratetable (__b43_ratetable + 0)
185 #define b43_b_ratetable_size 4
186 #define b43_g_ratetable (__b43_ratetable + 0)
187 #define b43_g_ratetable_size 12
189 #define CHAN2G(_channel, _freq, _flags) { \
190 .band = IEEE80211_BAND_2GHZ, \
191 .center_freq = (_freq), \
192 .hw_value = (_channel), \
194 .max_antenna_gain = 0, \
197 static struct ieee80211_channel b43_2ghz_chantable[] = {
214 /* No support for the last 3 channels (12, 13, 14) */
215 #define b43_2ghz_chantable_limited_size 11
218 #define CHAN4G(_channel, _flags) { \
219 .band = IEEE80211_BAND_5GHZ, \
220 .center_freq = 4000 + (5 * (_channel)), \
221 .hw_value = (_channel), \
223 .max_antenna_gain = 0, \
226 #define CHAN5G(_channel, _flags) { \
227 .band = IEEE80211_BAND_5GHZ, \
228 .center_freq = 5000 + (5 * (_channel)), \
229 .hw_value = (_channel), \
231 .max_antenna_gain = 0, \
234 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
235 CHAN4G(184, 0), CHAN4G(186, 0),
236 CHAN4G(188, 0), CHAN4G(190, 0),
237 CHAN4G(192, 0), CHAN4G(194, 0),
238 CHAN4G(196, 0), CHAN4G(198, 0),
239 CHAN4G(200, 0), CHAN4G(202, 0),
240 CHAN4G(204, 0), CHAN4G(206, 0),
241 CHAN4G(208, 0), CHAN4G(210, 0),
242 CHAN4G(212, 0), CHAN4G(214, 0),
243 CHAN4G(216, 0), CHAN4G(218, 0),
244 CHAN4G(220, 0), CHAN4G(222, 0),
245 CHAN4G(224, 0), CHAN4G(226, 0),
247 CHAN5G(32, 0), CHAN5G(34, 0),
248 CHAN5G(36, 0), CHAN5G(38, 0),
249 CHAN5G(40, 0), CHAN5G(42, 0),
250 CHAN5G(44, 0), CHAN5G(46, 0),
251 CHAN5G(48, 0), CHAN5G(50, 0),
252 CHAN5G(52, 0), CHAN5G(54, 0),
253 CHAN5G(56, 0), CHAN5G(58, 0),
254 CHAN5G(60, 0), CHAN5G(62, 0),
255 CHAN5G(64, 0), CHAN5G(66, 0),
256 CHAN5G(68, 0), CHAN5G(70, 0),
257 CHAN5G(72, 0), CHAN5G(74, 0),
258 CHAN5G(76, 0), CHAN5G(78, 0),
259 CHAN5G(80, 0), CHAN5G(82, 0),
260 CHAN5G(84, 0), CHAN5G(86, 0),
261 CHAN5G(88, 0), CHAN5G(90, 0),
262 CHAN5G(92, 0), CHAN5G(94, 0),
263 CHAN5G(96, 0), CHAN5G(98, 0),
264 CHAN5G(100, 0), CHAN5G(102, 0),
265 CHAN5G(104, 0), CHAN5G(106, 0),
266 CHAN5G(108, 0), CHAN5G(110, 0),
267 CHAN5G(112, 0), CHAN5G(114, 0),
268 CHAN5G(116, 0), CHAN5G(118, 0),
269 CHAN5G(120, 0), CHAN5G(122, 0),
270 CHAN5G(124, 0), CHAN5G(126, 0),
271 CHAN5G(128, 0), CHAN5G(130, 0),
272 CHAN5G(132, 0), CHAN5G(134, 0),
273 CHAN5G(136, 0), CHAN5G(138, 0),
274 CHAN5G(140, 0), CHAN5G(142, 0),
275 CHAN5G(144, 0), CHAN5G(145, 0),
276 CHAN5G(146, 0), CHAN5G(147, 0),
277 CHAN5G(148, 0), CHAN5G(149, 0),
278 CHAN5G(150, 0), CHAN5G(151, 0),
279 CHAN5G(152, 0), CHAN5G(153, 0),
280 CHAN5G(154, 0), CHAN5G(155, 0),
281 CHAN5G(156, 0), CHAN5G(157, 0),
282 CHAN5G(158, 0), CHAN5G(159, 0),
283 CHAN5G(160, 0), CHAN5G(161, 0),
284 CHAN5G(162, 0), CHAN5G(163, 0),
285 CHAN5G(164, 0), CHAN5G(165, 0),
286 CHAN5G(166, 0), CHAN5G(168, 0),
287 CHAN5G(170, 0), CHAN5G(172, 0),
288 CHAN5G(174, 0), CHAN5G(176, 0),
289 CHAN5G(178, 0), CHAN5G(180, 0),
293 static struct ieee80211_channel b43_5ghz_nphy_chantable_limited[] = {
294 CHAN5G(36, 0), CHAN5G(40, 0),
295 CHAN5G(44, 0), CHAN5G(48, 0),
296 CHAN5G(149, 0), CHAN5G(153, 0),
297 CHAN5G(157, 0), CHAN5G(161, 0),
301 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
302 CHAN5G(34, 0), CHAN5G(36, 0),
303 CHAN5G(38, 0), CHAN5G(40, 0),
304 CHAN5G(42, 0), CHAN5G(44, 0),
305 CHAN5G(46, 0), CHAN5G(48, 0),
306 CHAN5G(52, 0), CHAN5G(56, 0),
307 CHAN5G(60, 0), CHAN5G(64, 0),
308 CHAN5G(100, 0), CHAN5G(104, 0),
309 CHAN5G(108, 0), CHAN5G(112, 0),
310 CHAN5G(116, 0), CHAN5G(120, 0),
311 CHAN5G(124, 0), CHAN5G(128, 0),
312 CHAN5G(132, 0), CHAN5G(136, 0),
313 CHAN5G(140, 0), CHAN5G(149, 0),
314 CHAN5G(153, 0), CHAN5G(157, 0),
315 CHAN5G(161, 0), CHAN5G(165, 0),
316 CHAN5G(184, 0), CHAN5G(188, 0),
317 CHAN5G(192, 0), CHAN5G(196, 0),
318 CHAN5G(200, 0), CHAN5G(204, 0),
319 CHAN5G(208, 0), CHAN5G(212, 0),
325 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
326 .band = IEEE80211_BAND_5GHZ,
327 .channels = b43_5ghz_nphy_chantable,
328 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
329 .bitrates = b43_a_ratetable,
330 .n_bitrates = b43_a_ratetable_size,
333 static struct ieee80211_supported_band b43_band_5GHz_nphy_limited = {
334 .band = IEEE80211_BAND_5GHZ,
335 .channels = b43_5ghz_nphy_chantable_limited,
336 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable_limited),
337 .bitrates = b43_a_ratetable,
338 .n_bitrates = b43_a_ratetable_size,
341 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
342 .band = IEEE80211_BAND_5GHZ,
343 .channels = b43_5ghz_aphy_chantable,
344 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
345 .bitrates = b43_a_ratetable,
346 .n_bitrates = b43_a_ratetable_size,
349 static struct ieee80211_supported_band b43_band_2GHz = {
350 .band = IEEE80211_BAND_2GHZ,
351 .channels = b43_2ghz_chantable,
352 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
353 .bitrates = b43_g_ratetable,
354 .n_bitrates = b43_g_ratetable_size,
357 static struct ieee80211_supported_band b43_band_2ghz_limited = {
358 .band = IEEE80211_BAND_2GHZ,
359 .channels = b43_2ghz_chantable,
360 .n_channels = b43_2ghz_chantable_limited_size,
361 .bitrates = b43_g_ratetable,
362 .n_bitrates = b43_g_ratetable_size,
365 static void b43_wireless_core_exit(struct b43_wldev *dev);
366 static int b43_wireless_core_init(struct b43_wldev *dev);
367 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
368 static int b43_wireless_core_start(struct b43_wldev *dev);
369 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
370 struct ieee80211_vif *vif,
371 struct ieee80211_bss_conf *conf,
374 static int b43_ratelimit(struct b43_wl *wl)
376 if (!wl || !wl->current_dev)
378 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
380 /* We are up and running.
381 * Ratelimit the messages to avoid DoS over the net. */
382 return net_ratelimit();
385 void b43info(struct b43_wl *wl, const char *fmt, ...)
387 struct va_format vaf;
390 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
392 if (!b43_ratelimit(wl))
400 printk(KERN_INFO "b43-%s: %pV",
401 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
406 void b43err(struct b43_wl *wl, const char *fmt, ...)
408 struct va_format vaf;
411 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
413 if (!b43_ratelimit(wl))
421 printk(KERN_ERR "b43-%s ERROR: %pV",
422 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
427 void b43warn(struct b43_wl *wl, const char *fmt, ...)
429 struct va_format vaf;
432 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
434 if (!b43_ratelimit(wl))
442 printk(KERN_WARNING "b43-%s warning: %pV",
443 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
448 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
450 struct va_format vaf;
453 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
461 printk(KERN_DEBUG "b43-%s debug: %pV",
462 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
467 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
471 B43_WARN_ON(offset % 4 != 0);
473 macctl = b43_read32(dev, B43_MMIO_MACCTL);
474 if (macctl & B43_MACCTL_BE)
477 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
479 b43_write32(dev, B43_MMIO_RAM_DATA, val);
482 static inline void b43_shm_control_word(struct b43_wldev *dev,
483 u16 routing, u16 offset)
487 /* "offset" is the WORD offset. */
491 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
494 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
498 if (routing == B43_SHM_SHARED) {
499 B43_WARN_ON(offset & 0x0001);
500 if (offset & 0x0003) {
501 /* Unaligned access */
502 b43_shm_control_word(dev, routing, offset >> 2);
503 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
505 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
511 b43_shm_control_word(dev, routing, offset);
512 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
517 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
521 if (routing == B43_SHM_SHARED) {
522 B43_WARN_ON(offset & 0x0001);
523 if (offset & 0x0003) {
524 /* Unaligned access */
525 b43_shm_control_word(dev, routing, offset >> 2);
526 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
532 b43_shm_control_word(dev, routing, offset);
533 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
538 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
540 if (routing == B43_SHM_SHARED) {
541 B43_WARN_ON(offset & 0x0001);
542 if (offset & 0x0003) {
543 /* Unaligned access */
544 b43_shm_control_word(dev, routing, offset >> 2);
545 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
547 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
548 b43_write16(dev, B43_MMIO_SHM_DATA,
549 (value >> 16) & 0xFFFF);
554 b43_shm_control_word(dev, routing, offset);
555 b43_write32(dev, B43_MMIO_SHM_DATA, value);
558 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
560 if (routing == B43_SHM_SHARED) {
561 B43_WARN_ON(offset & 0x0001);
562 if (offset & 0x0003) {
563 /* Unaligned access */
564 b43_shm_control_word(dev, routing, offset >> 2);
565 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
570 b43_shm_control_word(dev, routing, offset);
571 b43_write16(dev, B43_MMIO_SHM_DATA, value);
575 u64 b43_hf_read(struct b43_wldev *dev)
579 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
581 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
583 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
588 /* Write HostFlags */
589 void b43_hf_write(struct b43_wldev *dev, u64 value)
593 lo = (value & 0x00000000FFFFULL);
594 mi = (value & 0x0000FFFF0000ULL) >> 16;
595 hi = (value & 0xFFFF00000000ULL) >> 32;
596 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
597 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
598 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
601 /* Read the firmware capabilities bitmask (Opensource firmware only) */
602 static u16 b43_fwcapa_read(struct b43_wldev *dev)
604 B43_WARN_ON(!dev->fw.opensource);
605 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
608 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
612 B43_WARN_ON(dev->dev->core_rev < 3);
614 /* The hardware guarantees us an atomic read, if we
615 * read the low register first. */
616 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
617 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
624 static void b43_time_lock(struct b43_wldev *dev)
626 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
627 /* Commit the write */
628 b43_read32(dev, B43_MMIO_MACCTL);
631 static void b43_time_unlock(struct b43_wldev *dev)
633 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
634 /* Commit the write */
635 b43_read32(dev, B43_MMIO_MACCTL);
638 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
642 B43_WARN_ON(dev->dev->core_rev < 3);
646 /* The hardware guarantees us an atomic write, if we
647 * write the low register first. */
648 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
650 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
654 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
657 b43_tsf_write_locked(dev, tsf);
658 b43_time_unlock(dev);
662 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
664 static const u8 zero_addr[ETH_ALEN] = { 0 };
671 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
675 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
678 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
681 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
684 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
688 u8 mac_bssid[ETH_ALEN * 2];
692 bssid = dev->wl->bssid;
693 mac = dev->wl->mac_addr;
695 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
697 memcpy(mac_bssid, mac, ETH_ALEN);
698 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
700 /* Write our MAC address and BSSID to template ram */
701 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
702 tmp = (u32) (mac_bssid[i + 0]);
703 tmp |= (u32) (mac_bssid[i + 1]) << 8;
704 tmp |= (u32) (mac_bssid[i + 2]) << 16;
705 tmp |= (u32) (mac_bssid[i + 3]) << 24;
706 b43_ram_write(dev, 0x20 + i, tmp);
710 static void b43_upload_card_macaddress(struct b43_wldev *dev)
712 b43_write_mac_bssid_templates(dev);
713 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
716 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
718 /* slot_time is in usec. */
719 /* This test used to exit for all but a G PHY. */
720 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
722 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
723 /* Shared memory location 0x0010 is the slot time and should be
724 * set to slot_time; however, this register is initially 0 and changing
725 * the value adversely affects the transmit rate for BCM4311
726 * devices. Until this behavior is unterstood, delete this step
728 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
732 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
734 b43_set_slot_time(dev, 9);
737 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
739 b43_set_slot_time(dev, 20);
742 /* DummyTransmission function, as documented on
743 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
745 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
747 struct b43_phy *phy = &dev->phy;
748 unsigned int i, max_loop;
760 buffer[0] = 0x000201CC;
763 buffer[0] = 0x000B846E;
766 for (i = 0; i < 5; i++)
767 b43_ram_write(dev, i * 4, buffer[i]);
769 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
771 if (dev->dev->core_rev < 11)
772 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
774 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
776 value = (ofdm ? 0x41 : 0x40);
777 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
778 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
779 phy->type == B43_PHYTYPE_LCN)
780 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
782 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
783 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
785 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
786 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
787 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
788 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
790 if (!pa_on && phy->type == B43_PHYTYPE_N)
791 ; /*b43_nphy_pa_override(dev, false) */
795 case B43_PHYTYPE_LCN:
796 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
799 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
802 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
804 b43_read16(dev, B43_MMIO_TXE0_AUX);
806 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
807 b43_radio_write16(dev, 0x0051, 0x0017);
808 for (i = 0x00; i < max_loop; i++) {
809 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
814 for (i = 0x00; i < 0x0A; i++) {
815 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
820 for (i = 0x00; i < 0x19; i++) {
821 value = b43_read16(dev, B43_MMIO_IFSSTAT);
822 if (!(value & 0x0100))
826 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
827 b43_radio_write16(dev, 0x0051, 0x0037);
830 static void key_write(struct b43_wldev *dev,
831 u8 index, u8 algorithm, const u8 *key)
838 /* Key index/algo block */
839 kidx = b43_kidx_to_fw(dev, index);
840 value = ((kidx << 4) | algorithm);
841 b43_shm_write16(dev, B43_SHM_SHARED,
842 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
844 /* Write the key to the Key Table Pointer offset */
845 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
846 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
848 value |= (u16) (key[i + 1]) << 8;
849 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
853 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
855 u32 addrtmp[2] = { 0, 0, };
856 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
858 if (b43_new_kidx_api(dev))
859 pairwise_keys_start = B43_NR_GROUP_KEYS;
861 B43_WARN_ON(index < pairwise_keys_start);
862 /* We have four default TX keys and possibly four default RX keys.
863 * Physical mac 0 is mapped to physical key 4 or 8, depending
864 * on the firmware version.
865 * So we must adjust the index here.
867 index -= pairwise_keys_start;
868 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
871 addrtmp[0] = addr[0];
872 addrtmp[0] |= ((u32) (addr[1]) << 8);
873 addrtmp[0] |= ((u32) (addr[2]) << 16);
874 addrtmp[0] |= ((u32) (addr[3]) << 24);
875 addrtmp[1] = addr[4];
876 addrtmp[1] |= ((u32) (addr[5]) << 8);
879 /* Receive match transmitter address (RCMTA) mechanism */
880 b43_shm_write32(dev, B43_SHM_RCMTA,
881 (index * 2) + 0, addrtmp[0]);
882 b43_shm_write16(dev, B43_SHM_RCMTA,
883 (index * 2) + 1, addrtmp[1]);
886 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
887 * When a packet is received, the iv32 is checked.
888 * - if it doesn't the packet is returned without modification (and software
889 * decryption can be done). That's what happen when iv16 wrap.
890 * - if it does, the rc4 key is computed, and decryption is tried.
891 * Either it will success and B43_RX_MAC_DEC is returned,
892 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
893 * and the packet is not usable (it got modified by the ucode).
894 * So in order to never have B43_RX_MAC_DECERR, we should provide
895 * a iv32 and phase1key that match. Because we drop packets in case of
896 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
897 * packets will be lost without higher layer knowing (ie no resync possible
900 * NOTE : this should support 50 key like RCMTA because
901 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
903 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
908 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
910 if (!modparam_hwtkip)
913 if (b43_new_kidx_api(dev))
914 pairwise_keys_start = B43_NR_GROUP_KEYS;
916 B43_WARN_ON(index < pairwise_keys_start);
917 /* We have four default TX keys and possibly four default RX keys.
918 * Physical mac 0 is mapped to physical key 4 or 8, depending
919 * on the firmware version.
920 * So we must adjust the index here.
922 index -= pairwise_keys_start;
923 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
925 if (b43_debug(dev, B43_DBG_KEYS)) {
926 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
929 /* Write the key to the RX tkip shared mem */
930 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
931 for (i = 0; i < 10; i += 2) {
932 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
933 phase1key ? phase1key[i / 2] : 0);
935 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
936 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
939 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
940 struct ieee80211_vif *vif,
941 struct ieee80211_key_conf *keyconf,
942 struct ieee80211_sta *sta,
943 u32 iv32, u16 *phase1key)
945 struct b43_wl *wl = hw_to_b43_wl(hw);
946 struct b43_wldev *dev;
947 int index = keyconf->hw_key_idx;
949 if (B43_WARN_ON(!modparam_hwtkip))
952 /* This is only called from the RX path through mac80211, where
953 * our mutex is already locked. */
954 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
955 dev = wl->current_dev;
956 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
958 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
960 rx_tkip_phase1_write(dev, index, iv32, phase1key);
961 /* only pairwise TKIP keys are supported right now */
964 keymac_write(dev, index, sta->addr);
967 static void do_key_write(struct b43_wldev *dev,
968 u8 index, u8 algorithm,
969 const u8 *key, size_t key_len, const u8 *mac_addr)
971 u8 buf[B43_SEC_KEYSIZE] = { 0, };
972 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
974 if (b43_new_kidx_api(dev))
975 pairwise_keys_start = B43_NR_GROUP_KEYS;
977 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
978 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
980 if (index >= pairwise_keys_start)
981 keymac_write(dev, index, NULL); /* First zero out mac. */
982 if (algorithm == B43_SEC_ALGO_TKIP) {
984 * We should provide an initial iv32, phase1key pair.
985 * We could start with iv32=0 and compute the corresponding
986 * phase1key, but this means calling ieee80211_get_tkip_key
987 * with a fake skb (or export other tkip function).
988 * Because we are lazy we hope iv32 won't start with
989 * 0xffffffff and let's b43_op_update_tkip_key provide a
992 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
993 } else if (index >= pairwise_keys_start) /* clear it */
994 rx_tkip_phase1_write(dev, index, 0, NULL);
996 memcpy(buf, key, key_len);
997 key_write(dev, index, algorithm, buf);
998 if (index >= pairwise_keys_start)
999 keymac_write(dev, index, mac_addr);
1001 dev->key[index].algorithm = algorithm;
1004 static int b43_key_write(struct b43_wldev *dev,
1005 int index, u8 algorithm,
1006 const u8 *key, size_t key_len,
1008 struct ieee80211_key_conf *keyconf)
1011 int pairwise_keys_start;
1013 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
1014 * - Temporal Encryption Key (128 bits)
1015 * - Temporal Authenticator Tx MIC Key (64 bits)
1016 * - Temporal Authenticator Rx MIC Key (64 bits)
1018 * Hardware only store TEK
1020 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
1022 if (key_len > B43_SEC_KEYSIZE)
1024 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
1025 /* Check that we don't already have this key. */
1026 B43_WARN_ON(dev->key[i].keyconf == keyconf);
1029 /* Pairwise key. Get an empty slot for the key. */
1030 if (b43_new_kidx_api(dev))
1031 pairwise_keys_start = B43_NR_GROUP_KEYS;
1033 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1034 for (i = pairwise_keys_start;
1035 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
1037 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
1038 if (!dev->key[i].keyconf) {
1045 b43warn(dev->wl, "Out of hardware key memory\n");
1049 B43_WARN_ON(index > 3);
1051 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1052 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1053 /* Default RX key */
1054 B43_WARN_ON(mac_addr);
1055 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1057 keyconf->hw_key_idx = index;
1058 dev->key[index].keyconf = keyconf;
1063 static int b43_key_clear(struct b43_wldev *dev, int index)
1065 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1067 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1068 NULL, B43_SEC_KEYSIZE, NULL);
1069 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1070 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1071 NULL, B43_SEC_KEYSIZE, NULL);
1073 dev->key[index].keyconf = NULL;
1078 static void b43_clear_keys(struct b43_wldev *dev)
1082 if (b43_new_kidx_api(dev))
1083 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1085 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1086 for (i = 0; i < count; i++)
1087 b43_key_clear(dev, i);
1090 static void b43_dump_keymemory(struct b43_wldev *dev)
1092 unsigned int i, index, count, offset, pairwise_keys_start;
1098 struct b43_key *key;
1100 if (!b43_debug(dev, B43_DBG_KEYS))
1103 hf = b43_hf_read(dev);
1104 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1105 !!(hf & B43_HF_USEDEFKEYS));
1106 if (b43_new_kidx_api(dev)) {
1107 pairwise_keys_start = B43_NR_GROUP_KEYS;
1108 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1110 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1111 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1113 for (index = 0; index < count; index++) {
1114 key = &(dev->key[index]);
1115 printk(KERN_DEBUG "Key slot %02u: %s",
1116 index, (key->keyconf == NULL) ? " " : "*");
1117 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1118 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1119 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1120 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1123 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1124 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1125 printk(" Algo: %04X/%02X", algo, key->algorithm);
1127 if (index >= pairwise_keys_start) {
1128 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1130 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1131 for (i = 0; i < 14; i += 2) {
1132 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1133 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1136 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1137 ((index - pairwise_keys_start) * 2) + 0);
1138 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1139 ((index - pairwise_keys_start) * 2) + 1);
1140 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1141 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1142 printk(" MAC: %pM", mac);
1144 printk(" DEFAULT KEY");
1149 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1157 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1158 (ps_flags & B43_PS_DISABLED));
1159 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1161 if (ps_flags & B43_PS_ENABLED) {
1163 } else if (ps_flags & B43_PS_DISABLED) {
1166 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1167 // and thus is not an AP and we are associated, set bit 25
1169 if (ps_flags & B43_PS_AWAKE) {
1171 } else if (ps_flags & B43_PS_ASLEEP) {
1174 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1175 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1176 // successful, set bit26
1179 /* FIXME: For now we force awake-on and hwps-off */
1183 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1185 macctl |= B43_MACCTL_HWPS;
1187 macctl &= ~B43_MACCTL_HWPS;
1189 macctl |= B43_MACCTL_AWAKE;
1191 macctl &= ~B43_MACCTL_AWAKE;
1192 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1194 b43_read32(dev, B43_MMIO_MACCTL);
1195 if (awake && dev->dev->core_rev >= 5) {
1196 /* Wait for the microcode to wake up. */
1197 for (i = 0; i < 100; i++) {
1198 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1199 B43_SHM_SH_UCODESTAT);
1200 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1207 /* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */
1208 void b43_wireless_core_phy_pll_reset(struct b43_wldev *dev)
1210 struct bcma_drv_cc *bcma_cc __maybe_unused;
1211 struct ssb_chipcommon *ssb_cc __maybe_unused;
1213 switch (dev->dev->bus_type) {
1214 #ifdef CONFIG_B43_BCMA
1216 bcma_cc = &dev->dev->bdev->bus->drv_cc;
1218 bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
1219 bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
1220 bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
1221 bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
1224 #ifdef CONFIG_B43_SSB
1226 ssb_cc = &dev->dev->sdev->bus->chipco;
1228 chipco_write32(ssb_cc, SSB_CHIPCO_CHIPCTL_ADDR, 0);
1229 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1230 chipco_set32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, 0x4);
1231 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1237 #ifdef CONFIG_B43_BCMA
1238 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1242 /* Put PHY into reset */
1243 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1244 flags |= B43_BCMA_IOCTL_PHY_RESET;
1245 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1246 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1249 b43_phy_take_out_of_reset(dev);
1252 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1254 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1255 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1256 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1257 B43_BCMA_CLKCTLST_PHY_PLL_ST;
1260 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1262 flags |= B43_BCMA_IOCTL_GMODE;
1263 b43_device_enable(dev, flags);
1265 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1266 b43_bcma_phy_reset(dev);
1267 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
1271 #ifdef CONFIG_B43_SSB
1272 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1277 flags |= B43_TMSLOW_GMODE;
1278 flags |= B43_TMSLOW_PHYCLKEN;
1279 flags |= B43_TMSLOW_PHYRESET;
1280 if (dev->phy.type == B43_PHYTYPE_N)
1281 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1282 b43_device_enable(dev, flags);
1283 msleep(2); /* Wait for the PLL to turn on. */
1285 b43_phy_take_out_of_reset(dev);
1289 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1293 switch (dev->dev->bus_type) {
1294 #ifdef CONFIG_B43_BCMA
1296 b43_bcma_wireless_core_reset(dev, gmode);
1299 #ifdef CONFIG_B43_SSB
1301 b43_ssb_wireless_core_reset(dev, gmode);
1306 /* Turn Analog ON, but only if we already know the PHY-type.
1307 * This protects against very early setup where we don't know the
1308 * PHY-type, yet. wireless_core_reset will be called once again later,
1309 * when we know the PHY-type. */
1311 dev->phy.ops->switch_analog(dev, 1);
1313 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1314 macctl &= ~B43_MACCTL_GMODE;
1316 macctl |= B43_MACCTL_GMODE;
1317 macctl |= B43_MACCTL_IHR_ENABLED;
1318 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1321 static void handle_irq_transmit_status(struct b43_wldev *dev)
1325 struct b43_txstatus stat;
1328 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1329 if (!(v0 & 0x00000001))
1331 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1333 stat.cookie = (v0 >> 16);
1334 stat.seq = (v1 & 0x0000FFFF);
1335 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1336 tmp = (v0 & 0x0000FFFF);
1337 stat.frame_count = ((tmp & 0xF000) >> 12);
1338 stat.rts_count = ((tmp & 0x0F00) >> 8);
1339 stat.supp_reason = ((tmp & 0x001C) >> 2);
1340 stat.pm_indicated = !!(tmp & 0x0080);
1341 stat.intermediate = !!(tmp & 0x0040);
1342 stat.for_ampdu = !!(tmp & 0x0020);
1343 stat.acked = !!(tmp & 0x0002);
1345 b43_handle_txstatus(dev, &stat);
1349 static void drain_txstatus_queue(struct b43_wldev *dev)
1353 if (dev->dev->core_rev < 5)
1355 /* Read all entries from the microcode TXstatus FIFO
1356 * and throw them away.
1359 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1360 if (!(dummy & 0x00000001))
1362 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1366 static u32 b43_jssi_read(struct b43_wldev *dev)
1370 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
1372 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
1377 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1379 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1380 (jssi & 0x0000FFFF));
1381 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1382 (jssi & 0xFFFF0000) >> 16);
1385 static void b43_generate_noise_sample(struct b43_wldev *dev)
1387 b43_jssi_write(dev, 0x7F7F7F7F);
1388 b43_write32(dev, B43_MMIO_MACCMD,
1389 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1392 static void b43_calculate_link_quality(struct b43_wldev *dev)
1394 /* Top half of Link Quality calculation. */
1396 if (dev->phy.type != B43_PHYTYPE_G)
1398 if (dev->noisecalc.calculation_running)
1400 dev->noisecalc.calculation_running = true;
1401 dev->noisecalc.nr_samples = 0;
1403 b43_generate_noise_sample(dev);
1406 static void handle_irq_noise(struct b43_wldev *dev)
1408 struct b43_phy_g *phy = dev->phy.g;
1414 /* Bottom half of Link Quality calculation. */
1416 if (dev->phy.type != B43_PHYTYPE_G)
1419 /* Possible race condition: It might be possible that the user
1420 * changed to a different channel in the meantime since we
1421 * started the calculation. We ignore that fact, since it's
1422 * not really that much of a problem. The background noise is
1423 * an estimation only anyway. Slightly wrong results will get damped
1424 * by the averaging of the 8 sample rounds. Additionally the
1425 * value is shortlived. So it will be replaced by the next noise
1426 * calculation round soon. */
1428 B43_WARN_ON(!dev->noisecalc.calculation_running);
1429 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1430 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1431 noise[2] == 0x7F || noise[3] == 0x7F)
1434 /* Get the noise samples. */
1435 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1436 i = dev->noisecalc.nr_samples;
1437 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1438 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1439 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1440 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1441 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1442 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1443 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1444 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1445 dev->noisecalc.nr_samples++;
1446 if (dev->noisecalc.nr_samples == 8) {
1447 /* Calculate the Link Quality by the noise samples. */
1449 for (i = 0; i < 8; i++) {
1450 for (j = 0; j < 4; j++)
1451 average += dev->noisecalc.samples[i][j];
1457 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1458 tmp = (tmp / 128) & 0x1F;
1468 dev->stats.link_noise = average;
1469 dev->noisecalc.calculation_running = false;
1473 b43_generate_noise_sample(dev);
1476 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1478 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1481 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1482 b43_power_saving_ctl_bits(dev, 0);
1484 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1485 dev->dfq_valid = true;
1488 static void handle_irq_atim_end(struct b43_wldev *dev)
1490 if (dev->dfq_valid) {
1491 b43_write32(dev, B43_MMIO_MACCMD,
1492 b43_read32(dev, B43_MMIO_MACCMD)
1493 | B43_MACCMD_DFQ_VALID);
1494 dev->dfq_valid = false;
1498 static void handle_irq_pmq(struct b43_wldev *dev)
1505 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1506 if (!(tmp & 0x00000008))
1509 /* 16bit write is odd, but correct. */
1510 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1513 static void b43_write_template_common(struct b43_wldev *dev,
1514 const u8 *data, u16 size,
1516 u16 shm_size_offset, u8 rate)
1519 struct b43_plcp_hdr4 plcp;
1522 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1523 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1524 ram_offset += sizeof(u32);
1525 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1526 * So leave the first two bytes of the next write blank.
1528 tmp = (u32) (data[0]) << 16;
1529 tmp |= (u32) (data[1]) << 24;
1530 b43_ram_write(dev, ram_offset, tmp);
1531 ram_offset += sizeof(u32);
1532 for (i = 2; i < size; i += sizeof(u32)) {
1533 tmp = (u32) (data[i + 0]);
1535 tmp |= (u32) (data[i + 1]) << 8;
1537 tmp |= (u32) (data[i + 2]) << 16;
1539 tmp |= (u32) (data[i + 3]) << 24;
1540 b43_ram_write(dev, ram_offset + i - 2, tmp);
1542 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1543 size + sizeof(struct b43_plcp_hdr6));
1546 /* Check if the use of the antenna that ieee80211 told us to
1547 * use is possible. This will fall back to DEFAULT.
1548 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1549 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1554 if (antenna_nr == 0) {
1555 /* Zero means "use default antenna". That's always OK. */
1559 /* Get the mask of available antennas. */
1561 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1563 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1565 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1566 /* This antenna is not available. Fall back to default. */
1573 /* Convert a b43 antenna number value to the PHY TX control value. */
1574 static u16 b43_antenna_to_phyctl(int antenna)
1578 return B43_TXH_PHY_ANT0;
1580 return B43_TXH_PHY_ANT1;
1582 return B43_TXH_PHY_ANT2;
1584 return B43_TXH_PHY_ANT3;
1585 case B43_ANTENNA_AUTO0:
1586 case B43_ANTENNA_AUTO1:
1587 return B43_TXH_PHY_ANT01AUTO;
1593 static void b43_write_beacon_template(struct b43_wldev *dev,
1595 u16 shm_size_offset)
1597 unsigned int i, len, variable_len;
1598 const struct ieee80211_mgmt *bcn;
1600 bool tim_found = false;
1604 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1606 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1607 len = min_t(size_t, dev->wl->current_beacon->len,
1608 0x200 - sizeof(struct b43_plcp_hdr6));
1609 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1611 b43_write_template_common(dev, (const u8 *)bcn,
1612 len, ram_offset, shm_size_offset, rate);
1614 /* Write the PHY TX control parameters. */
1615 antenna = B43_ANTENNA_DEFAULT;
1616 antenna = b43_antenna_to_phyctl(antenna);
1617 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1618 /* We can't send beacons with short preamble. Would get PHY errors. */
1619 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1620 ctl &= ~B43_TXH_PHY_ANT;
1621 ctl &= ~B43_TXH_PHY_ENC;
1623 if (b43_is_cck_rate(rate))
1624 ctl |= B43_TXH_PHY_ENC_CCK;
1626 ctl |= B43_TXH_PHY_ENC_OFDM;
1627 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1629 /* Find the position of the TIM and the DTIM_period value
1630 * and write them to SHM. */
1631 ie = bcn->u.beacon.variable;
1632 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1633 for (i = 0; i < variable_len - 2; ) {
1634 uint8_t ie_id, ie_len;
1641 /* This is the TIM Information Element */
1643 /* Check whether the ie_len is in the beacon data range. */
1644 if (variable_len < ie_len + 2 + i)
1646 /* A valid TIM is at least 4 bytes long. */
1651 tim_position = sizeof(struct b43_plcp_hdr6);
1652 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1655 dtim_period = ie[i + 3];
1657 b43_shm_write16(dev, B43_SHM_SHARED,
1658 B43_SHM_SH_TIMBPOS, tim_position);
1659 b43_shm_write16(dev, B43_SHM_SHARED,
1660 B43_SHM_SH_DTIMPER, dtim_period);
1667 * If ucode wants to modify TIM do it behind the beacon, this
1668 * will happen, for example, when doing mesh networking.
1670 b43_shm_write16(dev, B43_SHM_SHARED,
1672 len + sizeof(struct b43_plcp_hdr6));
1673 b43_shm_write16(dev, B43_SHM_SHARED,
1674 B43_SHM_SH_DTIMPER, 0);
1676 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1679 static void b43_upload_beacon0(struct b43_wldev *dev)
1681 struct b43_wl *wl = dev->wl;
1683 if (wl->beacon0_uploaded)
1685 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
1686 wl->beacon0_uploaded = true;
1689 static void b43_upload_beacon1(struct b43_wldev *dev)
1691 struct b43_wl *wl = dev->wl;
1693 if (wl->beacon1_uploaded)
1695 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
1696 wl->beacon1_uploaded = true;
1699 static void handle_irq_beacon(struct b43_wldev *dev)
1701 struct b43_wl *wl = dev->wl;
1702 u32 cmd, beacon0_valid, beacon1_valid;
1704 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1705 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1706 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1709 /* This is the bottom half of the asynchronous beacon update. */
1711 /* Ignore interrupt in the future. */
1712 dev->irq_mask &= ~B43_IRQ_BEACON;
1714 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1715 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1716 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1718 /* Schedule interrupt manually, if busy. */
1719 if (beacon0_valid && beacon1_valid) {
1720 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1721 dev->irq_mask |= B43_IRQ_BEACON;
1725 if (unlikely(wl->beacon_templates_virgin)) {
1726 /* We never uploaded a beacon before.
1727 * Upload both templates now, but only mark one valid. */
1728 wl->beacon_templates_virgin = false;
1729 b43_upload_beacon0(dev);
1730 b43_upload_beacon1(dev);
1731 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1732 cmd |= B43_MACCMD_BEACON0_VALID;
1733 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1735 if (!beacon0_valid) {
1736 b43_upload_beacon0(dev);
1737 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1738 cmd |= B43_MACCMD_BEACON0_VALID;
1739 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1740 } else if (!beacon1_valid) {
1741 b43_upload_beacon1(dev);
1742 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1743 cmd |= B43_MACCMD_BEACON1_VALID;
1744 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1749 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1751 u32 old_irq_mask = dev->irq_mask;
1753 /* update beacon right away or defer to irq */
1754 handle_irq_beacon(dev);
1755 if (old_irq_mask != dev->irq_mask) {
1756 /* The handler updated the IRQ mask. */
1757 B43_WARN_ON(!dev->irq_mask);
1758 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1759 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1761 /* Device interrupts are currently disabled. That means
1762 * we just ran the hardirq handler and scheduled the
1763 * IRQ thread. The thread will write the IRQ mask when
1764 * it finished, so there's nothing to do here. Writing
1765 * the mask _here_ would incorrectly re-enable IRQs. */
1770 static void b43_beacon_update_trigger_work(struct work_struct *work)
1772 struct b43_wl *wl = container_of(work, struct b43_wl,
1773 beacon_update_trigger);
1774 struct b43_wldev *dev;
1776 mutex_lock(&wl->mutex);
1777 dev = wl->current_dev;
1778 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1779 if (b43_bus_host_is_sdio(dev->dev)) {
1780 /* wl->mutex is enough. */
1781 b43_do_beacon_update_trigger_work(dev);
1784 spin_lock_irq(&wl->hardirq_lock);
1785 b43_do_beacon_update_trigger_work(dev);
1787 spin_unlock_irq(&wl->hardirq_lock);
1790 mutex_unlock(&wl->mutex);
1793 /* Asynchronously update the packet templates in template RAM.
1794 * Locking: Requires wl->mutex to be locked. */
1795 static void b43_update_templates(struct b43_wl *wl)
1797 struct sk_buff *beacon;
1799 /* This is the top half of the ansynchronous beacon update.
1800 * The bottom half is the beacon IRQ.
1801 * Beacon update must be asynchronous to avoid sending an
1802 * invalid beacon. This can happen for example, if the firmware
1803 * transmits a beacon while we are updating it. */
1805 /* We could modify the existing beacon and set the aid bit in
1806 * the TIM field, but that would probably require resizing and
1807 * moving of data within the beacon template.
1808 * Simply request a new beacon and let mac80211 do the hard work. */
1809 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1810 if (unlikely(!beacon))
1813 if (wl->current_beacon)
1814 dev_kfree_skb_any(wl->current_beacon);
1815 wl->current_beacon = beacon;
1816 wl->beacon0_uploaded = false;
1817 wl->beacon1_uploaded = false;
1818 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1821 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1824 if (dev->dev->core_rev >= 3) {
1825 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1826 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1828 b43_write16(dev, 0x606, (beacon_int >> 6));
1829 b43_write16(dev, 0x610, beacon_int);
1831 b43_time_unlock(dev);
1832 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1835 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1839 /* Read the register that contains the reason code for the panic. */
1840 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1841 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1845 b43dbg(dev->wl, "The panic reason is unknown.\n");
1847 case B43_FWPANIC_DIE:
1848 /* Do not restart the controller or firmware.
1849 * The device is nonfunctional from now on.
1850 * Restarting would result in this panic to trigger again,
1851 * so we avoid that recursion. */
1853 case B43_FWPANIC_RESTART:
1854 b43_controller_restart(dev, "Microcode panic");
1859 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1861 unsigned int i, cnt;
1862 u16 reason, marker_id, marker_line;
1865 /* The proprietary firmware doesn't have this IRQ. */
1866 if (!dev->fw.opensource)
1869 /* Read the register that contains the reason code for this IRQ. */
1870 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1873 case B43_DEBUGIRQ_PANIC:
1874 b43_handle_firmware_panic(dev);
1876 case B43_DEBUGIRQ_DUMP_SHM:
1878 break; /* Only with driver debugging enabled. */
1879 buf = kmalloc(4096, GFP_ATOMIC);
1881 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1884 for (i = 0; i < 4096; i += 2) {
1885 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1886 buf[i / 2] = cpu_to_le16(tmp);
1888 b43info(dev->wl, "Shared memory dump:\n");
1889 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1890 16, 2, buf, 4096, 1);
1893 case B43_DEBUGIRQ_DUMP_REGS:
1895 break; /* Only with driver debugging enabled. */
1896 b43info(dev->wl, "Microcode register dump:\n");
1897 for (i = 0, cnt = 0; i < 64; i++) {
1898 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1901 printk("r%02u: 0x%04X ", i, tmp);
1910 case B43_DEBUGIRQ_MARKER:
1912 break; /* Only with driver debugging enabled. */
1913 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1915 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1916 B43_MARKER_LINE_REG);
1917 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1918 "at line number %u\n",
1919 marker_id, marker_line);
1922 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1926 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1927 b43_shm_write16(dev, B43_SHM_SCRATCH,
1928 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1931 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1934 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1935 u32 merged_dma_reason = 0;
1938 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1941 reason = dev->irq_reason;
1942 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1943 dma_reason[i] = dev->dma_reason[i];
1944 merged_dma_reason |= dma_reason[i];
1947 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1948 b43err(dev->wl, "MAC transmission error\n");
1950 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1951 b43err(dev->wl, "PHY transmission error\n");
1953 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1954 atomic_set(&dev->phy.txerr_cnt,
1955 B43_PHY_TX_BADNESS_LIMIT);
1956 b43err(dev->wl, "Too many PHY TX errors, "
1957 "restarting the controller\n");
1958 b43_controller_restart(dev, "PHY TX errors");
1962 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
1964 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1965 dma_reason[0], dma_reason[1],
1966 dma_reason[2], dma_reason[3],
1967 dma_reason[4], dma_reason[5]);
1968 b43err(dev->wl, "This device does not support DMA "
1969 "on your system. It will now be switched to PIO.\n");
1970 /* Fall back to PIO transfers if we get fatal DMA errors! */
1971 dev->use_pio = true;
1972 b43_controller_restart(dev, "DMA error");
1976 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1977 handle_irq_ucode_debug(dev);
1978 if (reason & B43_IRQ_TBTT_INDI)
1979 handle_irq_tbtt_indication(dev);
1980 if (reason & B43_IRQ_ATIM_END)
1981 handle_irq_atim_end(dev);
1982 if (reason & B43_IRQ_BEACON)
1983 handle_irq_beacon(dev);
1984 if (reason & B43_IRQ_PMQ)
1985 handle_irq_pmq(dev);
1986 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1988 if (reason & B43_IRQ_NOISESAMPLE_OK)
1989 handle_irq_noise(dev);
1991 /* Check the DMA reason registers for received data. */
1992 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
1994 b43warn(dev->wl, "RX descriptor underrun\n");
1995 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
1997 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1998 if (b43_using_pio_transfers(dev))
1999 b43_pio_rx(dev->pio.rx_queue);
2001 b43_dma_rx(dev->dma.rx_ring);
2003 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
2004 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
2005 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
2006 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
2007 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
2009 if (reason & B43_IRQ_TX_OK)
2010 handle_irq_transmit_status(dev);
2012 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
2013 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2016 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2018 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2019 if (reason & (1 << i))
2020 dev->irq_bit_count[i]++;
2026 /* Interrupt thread handler. Handles device interrupts in thread context. */
2027 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
2029 struct b43_wldev *dev = dev_id;
2031 mutex_lock(&dev->wl->mutex);
2032 b43_do_interrupt_thread(dev);
2034 mutex_unlock(&dev->wl->mutex);
2039 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
2043 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
2044 * On SDIO, this runs under wl->mutex. */
2046 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2047 if (reason == 0xffffffff) /* shared IRQ */
2049 reason &= dev->irq_mask;
2053 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
2055 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2057 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2059 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2061 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2064 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2068 /* ACK the interrupt. */
2069 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2070 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2071 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2072 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2073 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2074 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2076 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2079 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2080 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2081 /* Save the reason bitmasks for the IRQ thread handler. */
2082 dev->irq_reason = reason;
2084 return IRQ_WAKE_THREAD;
2087 /* Interrupt handler top-half. This runs with interrupts disabled. */
2088 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2090 struct b43_wldev *dev = dev_id;
2093 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2096 spin_lock(&dev->wl->hardirq_lock);
2097 ret = b43_do_interrupt(dev);
2099 spin_unlock(&dev->wl->hardirq_lock);
2104 /* SDIO interrupt handler. This runs in process context. */
2105 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2107 struct b43_wl *wl = dev->wl;
2110 mutex_lock(&wl->mutex);
2112 ret = b43_do_interrupt(dev);
2113 if (ret == IRQ_WAKE_THREAD)
2114 b43_do_interrupt_thread(dev);
2116 mutex_unlock(&wl->mutex);
2119 void b43_do_release_fw(struct b43_firmware_file *fw)
2121 release_firmware(fw->data);
2123 fw->filename = NULL;
2126 static void b43_release_firmware(struct b43_wldev *dev)
2128 complete(&dev->fw_load_complete);
2129 b43_do_release_fw(&dev->fw.ucode);
2130 b43_do_release_fw(&dev->fw.pcm);
2131 b43_do_release_fw(&dev->fw.initvals);
2132 b43_do_release_fw(&dev->fw.initvals_band);
2135 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2139 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2140 "and download the correct firmware for this driver version. " \
2141 "Please carefully read all instructions on this website.\n";
2149 static void b43_fw_cb(const struct firmware *firmware, void *context)
2151 struct b43_request_fw_context *ctx = context;
2153 ctx->blob = firmware;
2154 complete(&ctx->dev->fw_load_complete);
2157 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2159 struct b43_firmware_file *fw, bool async)
2161 struct b43_fw_header *hdr;
2166 /* Don't fetch anything. Free possibly cached firmware. */
2167 /* FIXME: We should probably keep it anyway, to save some headache
2168 * on suspend/resume with multiband devices. */
2169 b43_do_release_fw(fw);
2173 if ((fw->type == ctx->req_type) &&
2174 (strcmp(fw->filename, name) == 0))
2175 return 0; /* Already have this fw. */
2176 /* Free the cached firmware first. */
2177 /* FIXME: We should probably do this later after we successfully
2178 * got the new fw. This could reduce headache with multiband devices.
2179 * We could also redesign this to cache the firmware for all possible
2180 * bands all the time. */
2181 b43_do_release_fw(fw);
2184 switch (ctx->req_type) {
2185 case B43_FWTYPE_PROPRIETARY:
2186 snprintf(ctx->fwname, sizeof(ctx->fwname),
2188 modparam_fwpostfix, name);
2190 case B43_FWTYPE_OPENSOURCE:
2191 snprintf(ctx->fwname, sizeof(ctx->fwname),
2193 modparam_fwpostfix, name);
2200 /* do this part asynchronously */
2201 init_completion(&ctx->dev->fw_load_complete);
2202 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2203 ctx->dev->dev->dev, GFP_KERNEL,
2206 pr_err("Unable to load firmware\n");
2209 wait_for_completion(&ctx->dev->fw_load_complete);
2212 /* On some ARM systems, the async request will fail, but the next sync
2213 * request works. For this reason, we fall through here
2216 err = request_firmware(&ctx->blob, ctx->fwname,
2217 ctx->dev->dev->dev);
2218 if (err == -ENOENT) {
2219 snprintf(ctx->errors[ctx->req_type],
2220 sizeof(ctx->errors[ctx->req_type]),
2221 "Firmware file \"%s\" not found\n",
2225 snprintf(ctx->errors[ctx->req_type],
2226 sizeof(ctx->errors[ctx->req_type]),
2227 "Firmware file \"%s\" request failed (err=%d)\n",
2232 if (ctx->blob->size < sizeof(struct b43_fw_header))
2234 hdr = (struct b43_fw_header *)(ctx->blob->data);
2235 switch (hdr->type) {
2236 case B43_FW_TYPE_UCODE:
2237 case B43_FW_TYPE_PCM:
2238 size = be32_to_cpu(hdr->size);
2239 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
2242 case B43_FW_TYPE_IV:
2250 fw->data = ctx->blob;
2251 fw->filename = name;
2252 fw->type = ctx->req_type;
2257 snprintf(ctx->errors[ctx->req_type],
2258 sizeof(ctx->errors[ctx->req_type]),
2259 "Firmware file \"%s\" format error.\n", ctx->fwname);
2260 release_firmware(ctx->blob);
2265 /* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
2266 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2268 struct b43_wldev *dev = ctx->dev;
2269 struct b43_firmware *fw = &ctx->dev->fw;
2270 struct b43_phy *phy = &dev->phy;
2271 const u8 rev = ctx->dev->dev->core_rev;
2272 const char *filename;
2279 if (phy->type == B43_PHYTYPE_AC)
2280 filename = "ucode42";
2283 if (phy->type == B43_PHYTYPE_AC)
2284 filename = "ucode40";
2287 if (phy->type == B43_PHYTYPE_LCN40)
2288 filename = "ucode33_lcn40";
2291 if (phy->type == B43_PHYTYPE_N)
2292 filename = "ucode30_mimo";
2295 if (phy->type == B43_PHYTYPE_HT)
2296 filename = "ucode29_mimo";
2299 if (phy->type == B43_PHYTYPE_HT)
2300 filename = "ucode26_mimo";
2304 if (phy->type == B43_PHYTYPE_N)
2305 filename = "ucode25_mimo";
2306 else if (phy->type == B43_PHYTYPE_LCN)
2307 filename = "ucode25_lcn";
2310 if (phy->type == B43_PHYTYPE_LCN)
2311 filename = "ucode24_lcn";
2314 if (phy->type == B43_PHYTYPE_N)
2315 filename = "ucode16_mimo";
2318 if (phy->type == B43_PHYTYPE_N)
2319 filename = "ucode16_mimo";
2320 else if (phy->type == B43_PHYTYPE_LP)
2321 filename = "ucode16_lp";
2324 filename = "ucode15";
2327 filename = "ucode14";
2330 filename = "ucode13";
2333 filename = "ucode11";
2336 filename = "ucode5";
2341 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
2346 if ((rev >= 5) && (rev <= 10))
2352 fw->pcm_request_failed = false;
2353 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
2354 if (err == -ENOENT) {
2355 /* We did not find a PCM file? Not fatal, but
2356 * core rev <= 10 must do without hwcrypto then. */
2357 fw->pcm_request_failed = true;
2363 switch (dev->phy.type) {
2366 filename = "b0g0initvals13";
2367 else if (rev >= 5 && rev <= 10)
2368 filename = "b0g0initvals5";
2372 filename = "n16initvals30";
2373 else if (rev == 28 || rev == 25)
2374 filename = "n0initvals25";
2376 filename = "n0initvals24";
2378 filename = "n0initvals16"; /* What about n0initvals22? */
2379 else if (rev >= 16 && rev <= 18)
2380 filename = "n0initvals16";
2381 else if (rev >= 11 && rev <= 12)
2382 filename = "n0initvals11";
2384 case B43_PHYTYPE_LP:
2385 if (rev >= 16 && rev <= 18)
2386 filename = "lp0initvals16";
2388 filename = "lp0initvals15";
2390 filename = "lp0initvals14";
2392 filename = "lp0initvals13";
2394 case B43_PHYTYPE_HT:
2396 filename = "ht0initvals29";
2398 filename = "ht0initvals26";
2400 case B43_PHYTYPE_LCN:
2402 filename = "lcn0initvals24";
2404 case B43_PHYTYPE_LCN40:
2406 filename = "lcn400initvals33";
2408 case B43_PHYTYPE_AC:
2410 filename = "ac1initvals42";
2412 filename = "ac0initvals40";
2416 goto err_no_initvals;
2417 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
2421 /* Get bandswitch initvals */
2423 switch (dev->phy.type) {
2426 filename = "b0g0bsinitvals13";
2427 else if (rev >= 5 && rev <= 10)
2428 filename = "b0g0bsinitvals5";
2432 filename = "n16bsinitvals30";
2433 else if (rev == 28 || rev == 25)
2434 filename = "n0bsinitvals25";
2436 filename = "n0bsinitvals24";
2438 filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
2439 else if (rev >= 16 && rev <= 18)
2440 filename = "n0bsinitvals16";
2441 else if (rev >= 11 && rev <= 12)
2442 filename = "n0bsinitvals11";
2444 case B43_PHYTYPE_LP:
2445 if (rev >= 16 && rev <= 18)
2446 filename = "lp0bsinitvals16";
2448 filename = "lp0bsinitvals15";
2450 filename = "lp0bsinitvals14";
2452 filename = "lp0bsinitvals13";
2454 case B43_PHYTYPE_HT:
2456 filename = "ht0bsinitvals29";
2458 filename = "ht0bsinitvals26";
2460 case B43_PHYTYPE_LCN:
2462 filename = "lcn0bsinitvals24";
2464 case B43_PHYTYPE_LCN40:
2466 filename = "lcn400bsinitvals33";
2468 case B43_PHYTYPE_AC:
2470 filename = "ac1bsinitvals42";
2472 filename = "ac0bsinitvals40";
2476 goto err_no_initvals;
2477 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
2481 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2486 err = ctx->fatal_failure = -EOPNOTSUPP;
2487 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2488 "is required for your device (wl-core rev %u)\n", rev);
2492 err = ctx->fatal_failure = -EOPNOTSUPP;
2493 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2494 "is required for your device (wl-core rev %u)\n", rev);
2498 err = ctx->fatal_failure = -EOPNOTSUPP;
2499 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2500 "is required for your device (wl-core rev %u)\n", rev);
2504 /* We failed to load this firmware image. The error message
2505 * already is in ctx->errors. Return and let our caller decide
2510 b43_release_firmware(dev);
2514 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2515 static void b43_one_core_detach(struct b43_bus_dev *dev);
2516 static int b43_rng_init(struct b43_wl *wl);
2518 static void b43_request_firmware(struct work_struct *work)
2520 struct b43_wl *wl = container_of(work,
2521 struct b43_wl, firmware_load);
2522 struct b43_wldev *dev = wl->current_dev;
2523 struct b43_request_fw_context *ctx;
2528 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2533 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2534 err = b43_try_request_fw(ctx);
2536 goto start_ieee80211; /* Successfully loaded it. */
2537 /* Was fw version known? */
2538 if (ctx->fatal_failure)
2541 /* proprietary fw not found, try open source */
2542 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2543 err = b43_try_request_fw(ctx);
2545 goto start_ieee80211; /* Successfully loaded it. */
2546 if(ctx->fatal_failure)
2549 /* Could not find a usable firmware. Print the errors. */
2550 for (i = 0; i < B43_NR_FWTYPES; i++) {
2551 errmsg = ctx->errors[i];
2553 b43err(dev->wl, "%s", errmsg);
2555 b43_print_fw_helptext(dev->wl, 1);
2559 wl->hw->queues = B43_QOS_QUEUE_NUM;
2560 if (!modparam_qos || dev->fw.opensource)
2563 err = ieee80211_register_hw(wl->hw);
2565 goto err_one_core_detach;
2566 wl->hw_registred = true;
2567 b43_leds_register(wl->current_dev);
2569 /* Register HW RNG driver */
2574 err_one_core_detach:
2575 b43_one_core_detach(dev->dev);
2581 static int b43_upload_microcode(struct b43_wldev *dev)
2583 struct wiphy *wiphy = dev->wl->hw->wiphy;
2584 const size_t hdr_len = sizeof(struct b43_fw_header);
2586 unsigned int i, len;
2587 u16 fwrev, fwpatch, fwdate, fwtime;
2591 /* Jump the microcode PSM to offset 0 */
2592 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2593 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2594 macctl |= B43_MACCTL_PSM_JMP0;
2595 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2596 /* Zero out all microcode PSM registers and shared memory. */
2597 for (i = 0; i < 64; i++)
2598 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2599 for (i = 0; i < 4096; i += 2)
2600 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2602 /* Upload Microcode. */
2603 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2604 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2605 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2606 for (i = 0; i < len; i++) {
2607 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2611 if (dev->fw.pcm.data) {
2612 /* Upload PCM data. */
2613 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2614 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2615 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2616 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2617 /* No need for autoinc bit in SHM_HW */
2618 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2619 for (i = 0; i < len; i++) {
2620 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2625 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2627 /* Start the microcode PSM */
2628 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2629 B43_MACCTL_PSM_RUN);
2631 /* Wait for the microcode to load and respond */
2634 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2635 if (tmp == B43_IRQ_MAC_SUSPENDED)
2639 b43err(dev->wl, "Microcode not responding\n");
2640 b43_print_fw_helptext(dev->wl, 1);
2646 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2648 /* Get and check the revisions. */
2649 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2650 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2651 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2652 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2654 if (fwrev <= 0x128) {
2655 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2656 "binary drivers older than version 4.x is unsupported. "
2657 "You must upgrade your firmware files.\n");
2658 b43_print_fw_helptext(dev->wl, 1);
2662 dev->fw.rev = fwrev;
2663 dev->fw.patch = fwpatch;
2664 if (dev->fw.rev >= 598)
2665 dev->fw.hdr_format = B43_FW_HDR_598;
2666 else if (dev->fw.rev >= 410)
2667 dev->fw.hdr_format = B43_FW_HDR_410;
2669 dev->fw.hdr_format = B43_FW_HDR_351;
2670 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
2672 dev->qos_enabled = dev->wl->hw->queues > 1;
2673 /* Default to firmware/hardware crypto acceleration. */
2674 dev->hwcrypto_enabled = true;
2676 if (dev->fw.opensource) {
2679 /* Patchlevel info is encoded in the "time" field. */
2680 dev->fw.patch = fwtime;
2681 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2682 dev->fw.rev, dev->fw.patch);
2684 fwcapa = b43_fwcapa_read(dev);
2685 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2686 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2687 /* Disable hardware crypto and fall back to software crypto. */
2688 dev->hwcrypto_enabled = false;
2690 /* adding QoS support should use an offline discovery mechanism */
2691 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
2693 b43info(dev->wl, "Loading firmware version %u.%u "
2694 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2696 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2697 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2698 if (dev->fw.pcm_request_failed) {
2699 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2700 "Hardware accelerated cryptography is disabled.\n");
2701 b43_print_fw_helptext(dev->wl, 0);
2705 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2706 dev->fw.rev, dev->fw.patch);
2707 wiphy->hw_version = dev->dev->core_id;
2709 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2710 /* We're over the deadline, but we keep support for old fw
2711 * until it turns out to be in major conflict with something new. */
2712 b43warn(dev->wl, "You are using an old firmware image. "
2713 "Support for old firmware will be removed soon "
2714 "(official deadline was July 2008).\n");
2715 b43_print_fw_helptext(dev->wl, 0);
2721 /* Stop the microcode PSM. */
2722 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2723 B43_MACCTL_PSM_JMP0);
2728 static int b43_write_initvals(struct b43_wldev *dev,
2729 const struct b43_iv *ivals,
2733 const struct b43_iv *iv;
2738 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2740 for (i = 0; i < count; i++) {
2741 if (array_size < sizeof(iv->offset_size))
2743 array_size -= sizeof(iv->offset_size);
2744 offset = be16_to_cpu(iv->offset_size);
2745 bit32 = !!(offset & B43_IV_32BIT);
2746 offset &= B43_IV_OFFSET_MASK;
2747 if (offset >= 0x1000)
2752 if (array_size < sizeof(iv->data.d32))
2754 array_size -= sizeof(iv->data.d32);
2756 value = get_unaligned_be32(&iv->data.d32);
2757 b43_write32(dev, offset, value);
2759 iv = (const struct b43_iv *)((const uint8_t *)iv +
2765 if (array_size < sizeof(iv->data.d16))
2767 array_size -= sizeof(iv->data.d16);
2769 value = be16_to_cpu(iv->data.d16);
2770 b43_write16(dev, offset, value);
2772 iv = (const struct b43_iv *)((const uint8_t *)iv +
2783 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2784 b43_print_fw_helptext(dev->wl, 1);
2789 static int b43_upload_initvals(struct b43_wldev *dev)
2791 const size_t hdr_len = sizeof(struct b43_fw_header);
2792 const struct b43_fw_header *hdr;
2793 struct b43_firmware *fw = &dev->fw;
2794 const struct b43_iv *ivals;
2797 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2798 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2799 count = be32_to_cpu(hdr->size);
2800 return b43_write_initvals(dev, ivals, count,
2801 fw->initvals.data->size - hdr_len);
2804 static int b43_upload_initvals_band(struct b43_wldev *dev)
2806 const size_t hdr_len = sizeof(struct b43_fw_header);
2807 const struct b43_fw_header *hdr;
2808 struct b43_firmware *fw = &dev->fw;
2809 const struct b43_iv *ivals;
2812 if (!fw->initvals_band.data)
2815 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2816 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2817 count = be32_to_cpu(hdr->size);
2818 return b43_write_initvals(dev, ivals, count,
2819 fw->initvals_band.data->size - hdr_len);
2822 /* Initialize the GPIOs
2823 * http://bcm-specs.sipsolutions.net/GPIO
2826 #ifdef CONFIG_B43_SSB
2827 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2829 struct ssb_bus *bus = dev->dev->sdev->bus;
2831 #ifdef CONFIG_SSB_DRIVER_PCICORE
2832 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2834 return bus->chipco.dev;
2839 static int b43_gpio_init(struct b43_wldev *dev)
2841 #ifdef CONFIG_B43_SSB
2842 struct ssb_device *gpiodev;
2846 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2847 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2851 if (dev->dev->chip_id == 0x4301) {
2854 } else if (dev->dev->chip_id == 0x5354) {
2855 /* Don't allow overtaking buttons GPIOs */
2856 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
2859 if (0 /* FIXME: conditional unknown */ ) {
2860 b43_write16(dev, B43_MMIO_GPIO_MASK,
2861 b43_read16(dev, B43_MMIO_GPIO_MASK)
2863 /* BT Coexistance Input */
2866 /* BT Coexistance Out */
2870 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2871 /* PA is controlled by gpio 9, let ucode handle it */
2872 b43_write16(dev, B43_MMIO_GPIO_MASK,
2873 b43_read16(dev, B43_MMIO_GPIO_MASK)
2879 switch (dev->dev->bus_type) {
2880 #ifdef CONFIG_B43_BCMA
2882 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
2885 #ifdef CONFIG_B43_SSB
2887 gpiodev = b43_ssb_gpio_dev(dev);
2889 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2890 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2899 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2900 static void b43_gpio_cleanup(struct b43_wldev *dev)
2902 #ifdef CONFIG_B43_SSB
2903 struct ssb_device *gpiodev;
2906 switch (dev->dev->bus_type) {
2907 #ifdef CONFIG_B43_BCMA
2909 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
2912 #ifdef CONFIG_B43_SSB
2914 gpiodev = b43_ssb_gpio_dev(dev);
2916 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2922 /* http://bcm-specs.sipsolutions.net/EnableMac */
2923 void b43_mac_enable(struct b43_wldev *dev)
2925 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2928 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2929 B43_SHM_SH_UCODESTAT);
2930 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2931 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2932 b43err(dev->wl, "b43_mac_enable(): The firmware "
2933 "should be suspended, but current state is %u\n",
2938 dev->mac_suspended--;
2939 B43_WARN_ON(dev->mac_suspended < 0);
2940 if (dev->mac_suspended == 0) {
2941 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2942 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2943 B43_IRQ_MAC_SUSPENDED);
2945 b43_read32(dev, B43_MMIO_MACCTL);
2946 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2947 b43_power_saving_ctl_bits(dev, 0);
2951 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2952 void b43_mac_suspend(struct b43_wldev *dev)
2958 B43_WARN_ON(dev->mac_suspended < 0);
2960 if (dev->mac_suspended == 0) {
2961 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2962 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2963 /* force pci to flush the write */
2964 b43_read32(dev, B43_MMIO_MACCTL);
2965 for (i = 35; i; i--) {
2966 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2967 if (tmp & B43_IRQ_MAC_SUSPENDED)
2971 /* Hm, it seems this will take some time. Use msleep(). */
2972 for (i = 40; i; i--) {
2973 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2974 if (tmp & B43_IRQ_MAC_SUSPENDED)
2978 b43err(dev->wl, "MAC suspend failed\n");
2981 dev->mac_suspended++;
2984 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2985 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2989 switch (dev->dev->bus_type) {
2990 #ifdef CONFIG_B43_BCMA
2992 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2994 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2996 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2997 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3000 #ifdef CONFIG_B43_SSB
3002 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3004 tmp |= B43_TMSLOW_MACPHYCLKEN;
3006 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
3007 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3013 /* brcms_b_switch_macfreq */
3014 void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode)
3016 u16 chip_id = dev->dev->chip_id;
3018 if (chip_id == BCMA_CHIP_ID_BCM4331) {
3020 case 2: /* 168 Mhz: 2^26/168 = 0x61862 */
3021 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x1862);
3022 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3024 case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */
3025 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x3e70);
3026 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3028 default: /* 160 Mhz: 2^26/160 = 0x66666 */
3029 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x6666);
3030 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3033 } else if (chip_id == BCMA_CHIP_ID_BCM43131 ||
3034 chip_id == BCMA_CHIP_ID_BCM43217 ||
3035 chip_id == BCMA_CHIP_ID_BCM43222 ||
3036 chip_id == BCMA_CHIP_ID_BCM43224 ||
3037 chip_id == BCMA_CHIP_ID_BCM43225 ||
3038 chip_id == BCMA_CHIP_ID_BCM43227 ||
3039 chip_id == BCMA_CHIP_ID_BCM43228) {
3041 case 2: /* 126 Mhz */
3042 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082);
3043 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3045 case 1: /* 123 Mhz */
3046 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341);
3047 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3049 default: /* 120 Mhz */
3050 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889);
3051 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3054 } else if (dev->phy.type == B43_PHYTYPE_LCN) {
3056 case 1: /* 82 Mhz */
3057 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0);
3058 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3060 default: /* 80 Mhz */
3061 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD);
3062 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3068 static void b43_adjust_opmode(struct b43_wldev *dev)
3070 struct b43_wl *wl = dev->wl;
3074 ctl = b43_read32(dev, B43_MMIO_MACCTL);
3075 /* Reset status to STA infrastructure mode. */
3076 ctl &= ~B43_MACCTL_AP;
3077 ctl &= ~B43_MACCTL_KEEP_CTL;
3078 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
3079 ctl &= ~B43_MACCTL_KEEP_BAD;
3080 ctl &= ~B43_MACCTL_PROMISC;
3081 ctl &= ~B43_MACCTL_BEACPROMISC;
3082 ctl |= B43_MACCTL_INFRA;
3084 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3085 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
3086 ctl |= B43_MACCTL_AP;
3087 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
3088 ctl &= ~B43_MACCTL_INFRA;
3090 if (wl->filter_flags & FIF_CONTROL)
3091 ctl |= B43_MACCTL_KEEP_CTL;
3092 if (wl->filter_flags & FIF_FCSFAIL)
3093 ctl |= B43_MACCTL_KEEP_BAD;
3094 if (wl->filter_flags & FIF_PLCPFAIL)
3095 ctl |= B43_MACCTL_KEEP_BADPLCP;
3096 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
3097 ctl |= B43_MACCTL_PROMISC;
3098 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
3099 ctl |= B43_MACCTL_BEACPROMISC;
3101 /* Workaround: On old hardware the HW-MAC-address-filter
3102 * doesn't work properly, so always run promisc in filter
3103 * it in software. */
3104 if (dev->dev->core_rev <= 4)
3105 ctl |= B43_MACCTL_PROMISC;
3107 b43_write32(dev, B43_MMIO_MACCTL, ctl);
3110 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
3111 if (dev->dev->chip_id == 0x4306 &&
3112 dev->dev->chip_rev == 3)
3117 b43_write16(dev, 0x612, cfp_pretbtt);
3119 /* FIXME: We don't currently implement the PMQ mechanism,
3120 * so always disable it. If we want to implement PMQ,
3121 * we need to enable it here (clear DISCPMQ) in AP mode.
3123 if (0 /* ctl & B43_MACCTL_AP */)
3124 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3126 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
3129 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3135 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
3138 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
3140 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3141 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3144 static void b43_rate_memory_init(struct b43_wldev *dev)
3146 switch (dev->phy.type) {
3150 case B43_PHYTYPE_LP:
3151 case B43_PHYTYPE_HT:
3152 case B43_PHYTYPE_LCN:
3153 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3154 b43_rate_memory_write(dev, B43_OFDM_RATE_9MB, 1);
3155 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3156 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3157 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3158 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3159 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3160 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3161 if (dev->phy.type == B43_PHYTYPE_A)
3165 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3166 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3167 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3168 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3175 /* Set the default values for the PHY TX Control Words. */
3176 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3180 ctl |= B43_TXH_PHY_ENC_CCK;
3181 ctl |= B43_TXH_PHY_ANT01AUTO;
3182 ctl |= B43_TXH_PHY_TXPWR;
3184 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3185 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3186 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3189 /* Set the TX-Antenna for management frames sent by firmware. */
3190 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3195 ant = b43_antenna_to_phyctl(antenna);
3198 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3199 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3200 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3201 /* For Probe Resposes */
3202 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3203 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3204 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3207 /* This is the opposite of b43_chip_init() */
3208 static void b43_chip_exit(struct b43_wldev *dev)
3211 b43_gpio_cleanup(dev);
3212 /* firmware is released later */
3215 /* Initialize the chip
3216 * http://bcm-specs.sipsolutions.net/ChipInit
3218 static int b43_chip_init(struct b43_wldev *dev)
3220 struct b43_phy *phy = &dev->phy;
3225 /* Initialize the MAC control */
3226 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3228 macctl |= B43_MACCTL_GMODE;
3229 macctl |= B43_MACCTL_INFRA;
3230 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3232 err = b43_upload_microcode(dev);
3234 goto out; /* firmware is released later */
3236 err = b43_gpio_init(dev);
3238 goto out; /* firmware is released later */
3240 err = b43_upload_initvals(dev);
3242 goto err_gpio_clean;
3244 err = b43_upload_initvals_band(dev);
3246 goto err_gpio_clean;
3248 /* Turn the Analog on and initialize the PHY. */
3249 phy->ops->switch_analog(dev, 1);
3250 err = b43_phy_init(dev);
3252 goto err_gpio_clean;
3254 /* Disable Interference Mitigation. */
3255 if (phy->ops->interf_mitigation)
3256 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3258 /* Select the antennae */
3259 if (phy->ops->set_rx_antenna)
3260 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3261 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3263 if (phy->type == B43_PHYTYPE_B) {
3264 value16 = b43_read16(dev, 0x005E);
3266 b43_write16(dev, 0x005E, value16);
3268 b43_write32(dev, 0x0100, 0x01000000);
3269 if (dev->dev->core_rev < 5)
3270 b43_write32(dev, 0x010C, 0x01000000);
3272 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3273 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3275 /* Probe Response Timeout value */
3276 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3277 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
3279 /* Initially set the wireless operation mode. */
3280 b43_adjust_opmode(dev);
3282 if (dev->dev->core_rev < 3) {
3283 b43_write16(dev, 0x060E, 0x0000);
3284 b43_write16(dev, 0x0610, 0x8000);
3285 b43_write16(dev, 0x0604, 0x0000);
3286 b43_write16(dev, 0x0606, 0x0200);
3288 b43_write32(dev, 0x0188, 0x80000000);
3289 b43_write32(dev, 0x018C, 0x02000000);
3291 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3292 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
3293 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3294 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3295 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3296 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3297 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3299 b43_mac_phy_clock_set(dev, true);
3301 switch (dev->dev->bus_type) {
3302 #ifdef CONFIG_B43_BCMA
3304 /* FIXME: 0xE74 is quite common, but should be read from CC */
3305 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3308 #ifdef CONFIG_B43_SSB
3310 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3311 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3317 b43dbg(dev->wl, "Chip initialized\n");
3322 b43_gpio_cleanup(dev);
3326 static void b43_periodic_every60sec(struct b43_wldev *dev)
3328 const struct b43_phy_operations *ops = dev->phy.ops;
3330 if (ops->pwork_60sec)
3331 ops->pwork_60sec(dev);
3333 /* Force check the TX power emission now. */
3334 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3337 static void b43_periodic_every30sec(struct b43_wldev *dev)
3339 /* Update device statistics. */
3340 b43_calculate_link_quality(dev);
3343 static void b43_periodic_every15sec(struct b43_wldev *dev)
3345 struct b43_phy *phy = &dev->phy;
3348 if (dev->fw.opensource) {
3349 /* Check if the firmware is still alive.
3350 * It will reset the watchdog counter to 0 in its idle loop. */
3351 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3352 if (unlikely(wdr)) {
3353 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3354 b43_controller_restart(dev, "Firmware watchdog");
3357 b43_shm_write16(dev, B43_SHM_SCRATCH,
3358 B43_WATCHDOG_REG, 1);
3362 if (phy->ops->pwork_15sec)
3363 phy->ops->pwork_15sec(dev);
3365 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3369 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3372 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3373 dev->irq_count / 15,
3375 dev->rx_count / 15);
3379 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3380 if (dev->irq_bit_count[i]) {
3381 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3382 dev->irq_bit_count[i] / 15, i, (1 << i));
3383 dev->irq_bit_count[i] = 0;
3390 static void do_periodic_work(struct b43_wldev *dev)
3394 state = dev->periodic_state;
3396 b43_periodic_every60sec(dev);
3398 b43_periodic_every30sec(dev);
3399 b43_periodic_every15sec(dev);
3402 /* Periodic work locking policy:
3403 * The whole periodic work handler is protected by
3404 * wl->mutex. If another lock is needed somewhere in the
3405 * pwork callchain, it's acquired in-place, where it's needed.
3407 static void b43_periodic_work_handler(struct work_struct *work)
3409 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3410 periodic_work.work);
3411 struct b43_wl *wl = dev->wl;
3412 unsigned long delay;
3414 mutex_lock(&wl->mutex);
3416 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3418 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3421 do_periodic_work(dev);
3423 dev->periodic_state++;
3425 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3426 delay = msecs_to_jiffies(50);
3428 delay = round_jiffies_relative(HZ * 15);
3429 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3431 mutex_unlock(&wl->mutex);
3434 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3436 struct delayed_work *work = &dev->periodic_work;
3438 dev->periodic_state = 0;
3439 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3440 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3443 /* Check if communication with the device works correctly. */
3444 static int b43_validate_chipaccess(struct b43_wldev *dev)
3446 u32 v, backup0, backup4;
3448 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3449 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3451 /* Check for read/write and endianness problems. */
3452 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3453 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3455 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3456 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3459 /* Check if unaligned 32bit SHM_SHARED access works properly.
3460 * However, don't bail out on failure, because it's noncritical. */
3461 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3462 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3463 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3464 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3465 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3466 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3467 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3468 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3469 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3470 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3471 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3472 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3474 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3475 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3477 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3478 /* The 32bit register shadows the two 16bit registers
3479 * with update sideeffects. Validate this. */
3480 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3481 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3482 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3484 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3487 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3489 v = b43_read32(dev, B43_MMIO_MACCTL);
3490 v |= B43_MACCTL_GMODE;
3491 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3496 b43err(dev->wl, "Failed to validate the chipaccess\n");
3500 static void b43_security_init(struct b43_wldev *dev)
3502 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3503 /* KTP is a word address, but we address SHM bytewise.
3504 * So multiply by two.
3507 /* Number of RCMTA address slots */
3508 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3509 /* Clear the key memory. */
3510 b43_clear_keys(dev);
3513 #ifdef CONFIG_B43_HWRNG
3514 static int b43_rng_read(struct hwrng *rng, u32 *data)
3516 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3517 struct b43_wldev *dev;
3518 int count = -ENODEV;
3520 mutex_lock(&wl->mutex);
3521 dev = wl->current_dev;
3522 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3523 *data = b43_read16(dev, B43_MMIO_RNG);
3524 count = sizeof(u16);
3526 mutex_unlock(&wl->mutex);
3530 #endif /* CONFIG_B43_HWRNG */
3532 static void b43_rng_exit(struct b43_wl *wl)
3534 #ifdef CONFIG_B43_HWRNG
3535 if (wl->rng_initialized)
3536 hwrng_unregister(&wl->rng);
3537 #endif /* CONFIG_B43_HWRNG */
3540 static int b43_rng_init(struct b43_wl *wl)
3544 #ifdef CONFIG_B43_HWRNG
3545 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3546 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3547 wl->rng.name = wl->rng_name;
3548 wl->rng.data_read = b43_rng_read;
3549 wl->rng.priv = (unsigned long)wl;
3550 wl->rng_initialized = true;
3551 err = hwrng_register(&wl->rng);
3553 wl->rng_initialized = false;
3554 b43err(wl, "Failed to register the random "
3555 "number generator (%d)\n", err);
3557 #endif /* CONFIG_B43_HWRNG */
3562 static void b43_tx_work(struct work_struct *work)
3564 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3565 struct b43_wldev *dev;
3566 struct sk_buff *skb;
3570 mutex_lock(&wl->mutex);
3571 dev = wl->current_dev;
3572 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3573 mutex_unlock(&wl->mutex);
3577 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3578 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3579 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3580 if (b43_using_pio_transfers(dev))
3581 err = b43_pio_tx(dev, skb);
3583 err = b43_dma_tx(dev, skb);
3584 if (err == -ENOSPC) {
3585 wl->tx_queue_stopped[queue_num] = 1;
3586 ieee80211_stop_queue(wl->hw, queue_num);
3587 skb_queue_head(&wl->tx_queue[queue_num], skb);
3591 ieee80211_free_txskb(wl->hw, skb);
3596 wl->tx_queue_stopped[queue_num] = 0;
3602 mutex_unlock(&wl->mutex);
3605 static void b43_op_tx(struct ieee80211_hw *hw,
3606 struct ieee80211_tx_control *control,
3607 struct sk_buff *skb)
3609 struct b43_wl *wl = hw_to_b43_wl(hw);
3611 if (unlikely(skb->len < 2 + 2 + 6)) {
3612 /* Too short, this can't be a valid frame. */
3613 ieee80211_free_txskb(hw, skb);
3616 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3618 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3619 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3620 ieee80211_queue_work(wl->hw, &wl->tx_work);
3622 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3626 static void b43_qos_params_upload(struct b43_wldev *dev,
3627 const struct ieee80211_tx_queue_params *p,
3630 u16 params[B43_NR_QOSPARAMS];
3634 if (!dev->qos_enabled)
3637 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3639 memset(¶ms, 0, sizeof(params));
3641 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3642 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3643 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3644 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3645 params[B43_QOSPARAM_AIFS] = p->aifs;
3646 params[B43_QOSPARAM_BSLOTS] = bslots;
3647 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3649 for (i = 0; i < ARRAY_SIZE(params); i++) {
3650 if (i == B43_QOSPARAM_STATUS) {
3651 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3652 shm_offset + (i * 2));
3653 /* Mark the parameters as updated. */
3655 b43_shm_write16(dev, B43_SHM_SHARED,
3656 shm_offset + (i * 2),
3659 b43_shm_write16(dev, B43_SHM_SHARED,
3660 shm_offset + (i * 2),
3666 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3667 static const u16 b43_qos_shm_offsets[] = {
3668 /* [mac80211-queue-nr] = SHM_OFFSET, */
3669 [0] = B43_QOS_VOICE,
3670 [1] = B43_QOS_VIDEO,
3671 [2] = B43_QOS_BESTEFFORT,
3672 [3] = B43_QOS_BACKGROUND,
3675 /* Update all QOS parameters in hardware. */
3676 static void b43_qos_upload_all(struct b43_wldev *dev)
3678 struct b43_wl *wl = dev->wl;
3679 struct b43_qos_params *params;
3682 if (!dev->qos_enabled)
3685 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3686 ARRAY_SIZE(wl->qos_params));
3688 b43_mac_suspend(dev);
3689 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3690 params = &(wl->qos_params[i]);
3691 b43_qos_params_upload(dev, &(params->p),
3692 b43_qos_shm_offsets[i]);
3694 b43_mac_enable(dev);
3697 static void b43_qos_clear(struct b43_wl *wl)
3699 struct b43_qos_params *params;
3702 /* Initialize QoS parameters to sane defaults. */
3704 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3705 ARRAY_SIZE(wl->qos_params));
3707 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3708 params = &(wl->qos_params[i]);
3710 switch (b43_qos_shm_offsets[i]) {
3714 params->p.cw_min = 0x0001;
3715 params->p.cw_max = 0x0001;
3720 params->p.cw_min = 0x0001;
3721 params->p.cw_max = 0x0001;
3723 case B43_QOS_BESTEFFORT:
3726 params->p.cw_min = 0x0001;
3727 params->p.cw_max = 0x03FF;
3729 case B43_QOS_BACKGROUND:
3732 params->p.cw_min = 0x0001;
3733 params->p.cw_max = 0x03FF;
3741 /* Initialize the core's QOS capabilities */
3742 static void b43_qos_init(struct b43_wldev *dev)
3744 if (!dev->qos_enabled) {
3745 /* Disable QOS support. */
3746 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3747 b43_write16(dev, B43_MMIO_IFSCTL,
3748 b43_read16(dev, B43_MMIO_IFSCTL)
3749 & ~B43_MMIO_IFSCTL_USE_EDCF);
3750 b43dbg(dev->wl, "QoS disabled\n");
3754 /* Upload the current QOS parameters. */
3755 b43_qos_upload_all(dev);
3757 /* Enable QOS support. */
3758 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3759 b43_write16(dev, B43_MMIO_IFSCTL,
3760 b43_read16(dev, B43_MMIO_IFSCTL)
3761 | B43_MMIO_IFSCTL_USE_EDCF);
3762 b43dbg(dev->wl, "QoS enabled\n");
3765 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3766 struct ieee80211_vif *vif, u16 _queue,
3767 const struct ieee80211_tx_queue_params *params)
3769 struct b43_wl *wl = hw_to_b43_wl(hw);
3770 struct b43_wldev *dev;
3771 unsigned int queue = (unsigned int)_queue;
3774 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3775 /* Queue not available or don't support setting
3776 * params on this queue. Return success to not
3777 * confuse mac80211. */
3780 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3781 ARRAY_SIZE(wl->qos_params));
3783 mutex_lock(&wl->mutex);
3784 dev = wl->current_dev;
3785 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3788 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3789 b43_mac_suspend(dev);
3790 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3791 b43_qos_shm_offsets[queue]);
3792 b43_mac_enable(dev);
3796 mutex_unlock(&wl->mutex);
3801 static int b43_op_get_stats(struct ieee80211_hw *hw,
3802 struct ieee80211_low_level_stats *stats)
3804 struct b43_wl *wl = hw_to_b43_wl(hw);
3806 mutex_lock(&wl->mutex);
3807 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3808 mutex_unlock(&wl->mutex);
3813 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3815 struct b43_wl *wl = hw_to_b43_wl(hw);
3816 struct b43_wldev *dev;
3819 mutex_lock(&wl->mutex);
3820 dev = wl->current_dev;
3822 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3823 b43_tsf_read(dev, &tsf);
3827 mutex_unlock(&wl->mutex);
3832 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3833 struct ieee80211_vif *vif, u64 tsf)
3835 struct b43_wl *wl = hw_to_b43_wl(hw);
3836 struct b43_wldev *dev;
3838 mutex_lock(&wl->mutex);
3839 dev = wl->current_dev;
3841 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3842 b43_tsf_write(dev, tsf);
3844 mutex_unlock(&wl->mutex);
3847 static const char *band_to_string(enum ieee80211_band band)
3850 case IEEE80211_BAND_5GHZ:
3852 case IEEE80211_BAND_2GHZ:
3861 /* Expects wl->mutex locked */
3862 static int b43_switch_band(struct b43_wldev *dev,
3863 struct ieee80211_channel *chan)
3865 struct b43_phy *phy = &dev->phy;
3869 switch (chan->band) {
3870 case IEEE80211_BAND_5GHZ:
3873 case IEEE80211_BAND_2GHZ:
3881 if (!((gmode && phy->supports_2ghz) ||
3882 (!gmode && phy->supports_5ghz))) {
3883 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
3884 band_to_string(chan->band));
3888 if (!!phy->gmode == !!gmode) {
3889 /* This device is already running. */
3893 b43dbg(dev->wl, "Switching to %s GHz band\n",
3894 band_to_string(chan->band));
3896 /* Some new devices don't need disabling radio for band switching */
3897 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
3898 b43_software_rfkill(dev, true);
3901 b43_phy_put_into_reset(dev);
3902 switch (dev->dev->bus_type) {
3903 #ifdef CONFIG_B43_BCMA
3905 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3907 tmp |= B43_BCMA_IOCTL_GMODE;
3909 tmp &= ~B43_BCMA_IOCTL_GMODE;
3910 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3913 #ifdef CONFIG_B43_SSB
3915 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3917 tmp |= B43_TMSLOW_GMODE;
3919 tmp &= ~B43_TMSLOW_GMODE;
3920 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3924 b43_phy_take_out_of_reset(dev);
3926 b43_upload_initvals_band(dev);
3933 static void b43_set_beacon_listen_interval(struct b43_wldev *dev, u16 interval)
3935 interval = min_t(u16, interval, (u16)0xFF);
3936 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BCN_LI, interval);
3939 /* Write the short and long frame retry limit values. */
3940 static void b43_set_retry_limits(struct b43_wldev *dev,
3941 unsigned int short_retry,
3942 unsigned int long_retry)
3944 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3945 * the chip-internal counter. */
3946 short_retry = min(short_retry, (unsigned int)0xF);
3947 long_retry = min(long_retry, (unsigned int)0xF);
3949 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3951 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3955 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3957 struct b43_wl *wl = hw_to_b43_wl(hw);
3958 struct b43_wldev *dev = wl->current_dev;
3959 struct b43_phy *phy = &dev->phy;
3960 struct ieee80211_conf *conf = &hw->conf;
3964 mutex_lock(&wl->mutex);
3965 b43_mac_suspend(dev);
3967 if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL)
3968 b43_set_beacon_listen_interval(dev, conf->listen_interval);
3970 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3971 phy->chandef = &conf->chandef;
3972 phy->channel = conf->chandef.chan->hw_value;
3974 /* Switch the band (if necessary). */
3975 err = b43_switch_band(dev, conf->chandef.chan);
3977 goto out_mac_enable;
3979 /* Switch to the requested channel.
3980 * The firmware takes care of races with the TX handler.
3982 b43_switch_channel(dev, phy->channel);
3985 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3986 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3987 conf->long_frame_max_tx_count);
3988 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3990 goto out_mac_enable;
3992 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3994 /* Adjust the desired TX power level. */
3995 if (conf->power_level != 0) {
3996 if (conf->power_level != phy->desired_txpower) {
3997 phy->desired_txpower = conf->power_level;
3998 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3999 B43_TXPWR_IGNORE_TSSI);
4003 /* Antennas for RX and management frame TX. */
4004 antenna = B43_ANTENNA_DEFAULT;
4005 b43_mgmtframe_txantenna(dev, antenna);
4006 antenna = B43_ANTENNA_DEFAULT;
4007 if (phy->ops->set_rx_antenna)
4008 phy->ops->set_rx_antenna(dev, antenna);
4010 if (wl->radio_enabled != phy->radio_on) {
4011 if (wl->radio_enabled) {
4012 b43_software_rfkill(dev, false);
4013 b43info(dev->wl, "Radio turned on by software\n");
4014 if (!dev->radio_hw_enable) {
4015 b43info(dev->wl, "The hardware RF-kill button "
4016 "still turns the radio physically off. "
4017 "Press the button to turn it on.\n");
4020 b43_software_rfkill(dev, true);
4021 b43info(dev->wl, "Radio turned off by software\n");
4026 b43_mac_enable(dev);
4027 mutex_unlock(&wl->mutex);
4032 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
4034 struct ieee80211_supported_band *sband =
4035 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
4036 struct ieee80211_rate *rate;
4038 u16 basic, direct, offset, basic_offset, rateptr;
4040 for (i = 0; i < sband->n_bitrates; i++) {
4041 rate = &sband->bitrates[i];
4043 if (b43_is_cck_rate(rate->hw_value)) {
4044 direct = B43_SHM_SH_CCKDIRECT;
4045 basic = B43_SHM_SH_CCKBASIC;
4046 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4049 direct = B43_SHM_SH_OFDMDIRECT;
4050 basic = B43_SHM_SH_OFDMBASIC;
4051 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4055 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
4057 if (b43_is_cck_rate(rate->hw_value)) {
4058 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4059 basic_offset &= 0xF;
4061 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4062 basic_offset &= 0xF;
4066 * Get the pointer that we need to point to
4067 * from the direct map
4069 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
4070 direct + 2 * basic_offset);
4071 /* and write it to the basic map */
4072 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
4077 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
4078 struct ieee80211_vif *vif,
4079 struct ieee80211_bss_conf *conf,
4082 struct b43_wl *wl = hw_to_b43_wl(hw);
4083 struct b43_wldev *dev;
4085 mutex_lock(&wl->mutex);
4087 dev = wl->current_dev;
4088 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4089 goto out_unlock_mutex;
4091 B43_WARN_ON(wl->vif != vif);
4093 if (changed & BSS_CHANGED_BSSID) {
4095 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
4097 memset(wl->bssid, 0, ETH_ALEN);
4100 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
4101 if (changed & BSS_CHANGED_BEACON &&
4102 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4103 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4104 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
4105 b43_update_templates(wl);
4107 if (changed & BSS_CHANGED_BSSID)
4108 b43_write_mac_bssid_templates(dev);
4111 b43_mac_suspend(dev);
4113 /* Update templates for AP/mesh mode. */
4114 if (changed & BSS_CHANGED_BEACON_INT &&
4115 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4116 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4117 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4119 b43_set_beacon_int(dev, conf->beacon_int);
4121 if (changed & BSS_CHANGED_BASIC_RATES)
4122 b43_update_basic_rates(dev, conf->basic_rates);
4124 if (changed & BSS_CHANGED_ERP_SLOT) {
4125 if (conf->use_short_slot)
4126 b43_short_slot_timing_enable(dev);
4128 b43_short_slot_timing_disable(dev);
4131 b43_mac_enable(dev);
4133 mutex_unlock(&wl->mutex);
4136 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4137 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4138 struct ieee80211_key_conf *key)
4140 struct b43_wl *wl = hw_to_b43_wl(hw);
4141 struct b43_wldev *dev;
4145 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4147 if (modparam_nohwcrypt)
4148 return -ENOSPC; /* User disabled HW-crypto */
4150 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4151 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4152 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4153 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4154 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4156 * For now, disable hw crypto for the RSN IBSS group keys. This
4157 * could be optimized in the future, but until that gets
4158 * implemented, use of software crypto for group addressed
4159 * frames is a acceptable to allow RSN IBSS to be used.
4164 mutex_lock(&wl->mutex);
4166 dev = wl->current_dev;
4168 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4171 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4172 /* We don't have firmware for the crypto engine.
4173 * Must use software-crypto. */
4179 switch (key->cipher) {
4180 case WLAN_CIPHER_SUITE_WEP40:
4181 algorithm = B43_SEC_ALGO_WEP40;
4183 case WLAN_CIPHER_SUITE_WEP104:
4184 algorithm = B43_SEC_ALGO_WEP104;
4186 case WLAN_CIPHER_SUITE_TKIP:
4187 algorithm = B43_SEC_ALGO_TKIP;
4189 case WLAN_CIPHER_SUITE_CCMP:
4190 algorithm = B43_SEC_ALGO_AES;
4196 index = (u8) (key->keyidx);
4202 if (algorithm == B43_SEC_ALGO_TKIP &&
4203 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4204 !modparam_hwtkip)) {
4205 /* We support only pairwise key */
4210 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4211 if (WARN_ON(!sta)) {
4215 /* Pairwise key with an assigned MAC address. */
4216 err = b43_key_write(dev, -1, algorithm,
4217 key->key, key->keylen,
4221 err = b43_key_write(dev, index, algorithm,
4222 key->key, key->keylen, NULL, key);
4227 if (algorithm == B43_SEC_ALGO_WEP40 ||
4228 algorithm == B43_SEC_ALGO_WEP104) {
4229 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4232 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4234 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4235 if (algorithm == B43_SEC_ALGO_TKIP)
4236 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4239 err = b43_key_clear(dev, key->hw_key_idx);
4250 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4252 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4253 sta ? sta->addr : bcast_addr);
4254 b43_dump_keymemory(dev);
4256 mutex_unlock(&wl->mutex);
4261 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4262 unsigned int changed, unsigned int *fflags,
4265 struct b43_wl *wl = hw_to_b43_wl(hw);
4266 struct b43_wldev *dev;
4268 mutex_lock(&wl->mutex);
4269 dev = wl->current_dev;
4275 *fflags &= FIF_PROMISC_IN_BSS |
4281 FIF_BCN_PRBRESP_PROMISC;
4283 changed &= FIF_PROMISC_IN_BSS |
4289 FIF_BCN_PRBRESP_PROMISC;
4291 wl->filter_flags = *fflags;
4293 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4294 b43_adjust_opmode(dev);
4297 mutex_unlock(&wl->mutex);
4300 /* Locking: wl->mutex
4301 * Returns the current dev. This might be different from the passed in dev,
4302 * because the core might be gone away while we unlocked the mutex. */
4303 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4306 struct b43_wldev *orig_dev;
4314 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4317 /* Cancel work. Unlock to avoid deadlocks. */
4318 mutex_unlock(&wl->mutex);
4319 cancel_delayed_work_sync(&dev->periodic_work);
4320 cancel_work_sync(&wl->tx_work);
4321 mutex_lock(&wl->mutex);
4322 dev = wl->current_dev;
4323 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4324 /* Whoops, aliens ate up the device while we were unlocked. */
4328 /* Disable interrupts on the device. */
4329 b43_set_status(dev, B43_STAT_INITIALIZED);
4330 if (b43_bus_host_is_sdio(dev->dev)) {
4331 /* wl->mutex is locked. That is enough. */
4332 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4333 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4335 spin_lock_irq(&wl->hardirq_lock);
4336 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4337 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4338 spin_unlock_irq(&wl->hardirq_lock);
4340 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4342 mutex_unlock(&wl->mutex);
4343 if (b43_bus_host_is_sdio(dev->dev)) {
4344 b43_sdio_free_irq(dev);
4346 synchronize_irq(dev->dev->irq);
4347 free_irq(dev->dev->irq, dev);
4349 mutex_lock(&wl->mutex);
4350 dev = wl->current_dev;
4353 if (dev != orig_dev) {
4354 if (b43_status(dev) >= B43_STAT_STARTED)
4358 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4359 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4361 /* Drain all TX queues. */
4362 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4363 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4364 struct sk_buff *skb;
4366 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4367 ieee80211_free_txskb(wl->hw, skb);
4371 b43_mac_suspend(dev);
4373 b43dbg(wl, "Wireless interface stopped\n");
4378 /* Locking: wl->mutex */
4379 static int b43_wireless_core_start(struct b43_wldev *dev)
4383 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4385 drain_txstatus_queue(dev);
4386 if (b43_bus_host_is_sdio(dev->dev)) {
4387 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4389 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4393 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4394 b43_interrupt_thread_handler,
4395 IRQF_SHARED, KBUILD_MODNAME, dev);
4397 b43err(dev->wl, "Cannot request IRQ-%d\n",
4403 /* We are ready to run. */
4404 ieee80211_wake_queues(dev->wl->hw);
4405 b43_set_status(dev, B43_STAT_STARTED);
4407 /* Start data flow (TX/RX). */
4408 b43_mac_enable(dev);
4409 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4411 /* Start maintenance work */
4412 b43_periodic_tasks_setup(dev);
4416 b43dbg(dev->wl, "Wireless interface started\n");
4421 static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4432 case B43_PHYTYPE_LP:
4434 case B43_PHYTYPE_SSLPN:
4436 case B43_PHYTYPE_HT:
4438 case B43_PHYTYPE_LCN:
4440 case B43_PHYTYPE_LCNXN:
4442 case B43_PHYTYPE_LCN40:
4444 case B43_PHYTYPE_AC:
4450 /* Get PHY and RADIO versioning numbers */
4451 static int b43_phy_versioning(struct b43_wldev *dev)
4453 struct b43_phy *phy = &dev->phy;
4454 const u8 core_rev = dev->dev->core_rev;
4463 int unsupported = 0;
4465 /* Get PHY versioning */
4466 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4467 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4468 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4469 phy_rev = (tmp & B43_PHYVER_VERSION);
4471 /* LCNXN is continuation of N which run out of revisions */
4472 if (phy_type == B43_PHYTYPE_LCNXN) {
4473 phy_type = B43_PHYTYPE_N;
4478 #ifdef CONFIG_B43_PHY_G
4484 #ifdef CONFIG_B43_PHY_N
4490 #ifdef CONFIG_B43_PHY_LP
4491 case B43_PHYTYPE_LP:
4496 #ifdef CONFIG_B43_PHY_HT
4497 case B43_PHYTYPE_HT:
4502 #ifdef CONFIG_B43_PHY_LCN
4503 case B43_PHYTYPE_LCN:
4512 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4513 analog_type, phy_type, b43_phy_name(dev, phy_type),
4517 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4518 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
4520 /* Get RADIO versioning */
4521 if (core_rev == 40 || core_rev == 42) {
4522 radio_manuf = 0x17F;
4524 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0);
4525 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4527 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1);
4528 radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4530 radio_ver = 0; /* Is there version somewhere? */
4531 } else if (core_rev >= 24) {
4534 for (tmp = 0; tmp < 3; tmp++) {
4535 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4536 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4539 radio_manuf = 0x17F;
4540 radio_id = (radio24[2] << 8) | radio24[1];
4541 radio_rev = (radio24[0] & 0xF);
4542 radio_ver = (radio24[0] & 0xF0) >> 4;
4544 if (dev->dev->chip_id == 0x4317) {
4545 if (dev->dev->chip_rev == 0)
4547 else if (dev->dev->chip_rev == 1)
4552 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4554 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4555 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4557 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4559 radio_manuf = (tmp & 0x00000FFF);
4560 radio_id = (tmp & 0x0FFFF000) >> 12;
4561 radio_rev = (tmp & 0xF0000000) >> 28;
4562 radio_ver = 0; /* Probably not available on old hw */
4565 if (radio_manuf != 0x17F /* Broadcom */)
4569 if (radio_id != 0x2060)
4573 if (radio_manuf != 0x17F)
4577 if ((radio_id & 0xFFF0) != 0x2050)
4581 if (radio_id != 0x2050)
4585 if (radio_id != 0x2055 && radio_id != 0x2056 &&
4588 if (radio_id == 0x2057 &&
4589 !(radio_rev == 9 || radio_rev == 14))
4592 case B43_PHYTYPE_LP:
4593 if (radio_id != 0x2062 && radio_id != 0x2063)
4596 case B43_PHYTYPE_HT:
4597 if (radio_id != 0x2059)
4600 case B43_PHYTYPE_LCN:
4601 if (radio_id != 0x2064)
4609 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n",
4610 radio_manuf, radio_id, radio_rev, radio_ver);
4614 "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n",
4615 radio_manuf, radio_id, radio_rev, radio_ver);
4617 /* FIXME: b43 treats "id" as "ver" and ignores the real "ver" */
4618 phy->radio_manuf = radio_manuf;
4619 phy->radio_ver = radio_id;
4620 phy->radio_rev = radio_rev;
4622 phy->analog = analog_type;
4623 phy->type = phy_type;
4629 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4630 struct b43_phy *phy)
4632 phy->hardware_power_control = !!modparam_hwpctl;
4633 phy->next_txpwr_check_time = jiffies;
4634 /* PHY TX errors counter. */
4635 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4638 phy->phy_locked = false;
4639 phy->radio_locked = false;
4643 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4645 dev->dfq_valid = false;
4647 /* Assume the radio is enabled. If it's not enabled, the state will
4648 * immediately get fixed on the first periodic work run. */
4649 dev->radio_hw_enable = true;
4652 memset(&dev->stats, 0, sizeof(dev->stats));
4654 setup_struct_phy_for_init(dev, &dev->phy);
4656 /* IRQ related flags */
4657 dev->irq_reason = 0;
4658 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4659 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4660 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4661 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4663 dev->mac_suspended = 1;
4665 /* Noise calculation context */
4666 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4669 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4671 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4674 if (!modparam_btcoex)
4676 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4678 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4681 hf = b43_hf_read(dev);
4682 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4683 hf |= B43_HF_BTCOEXALT;
4685 hf |= B43_HF_BTCOEX;
4686 b43_hf_write(dev, hf);
4689 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4691 if (!modparam_btcoex)
4696 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4698 struct ssb_bus *bus;
4701 #ifdef CONFIG_B43_SSB
4702 if (dev->dev->bus_type != B43_BUS_SSB)
4708 bus = dev->dev->sdev->bus;
4710 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4711 (bus->chip_id == 0x4312)) {
4712 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4713 tmp &= ~SSB_IMCFGLO_REQTO;
4714 tmp &= ~SSB_IMCFGLO_SERTO;
4716 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4717 ssb_commit_settings(bus);
4721 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4725 /* The time value is in microseconds. */
4726 if (dev->phy.type == B43_PHYTYPE_A)
4730 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4732 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4733 pu_delay = max(pu_delay, (u16)2400);
4735 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4738 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4739 static void b43_set_pretbtt(struct b43_wldev *dev)
4743 /* The time value is in microseconds. */
4744 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4747 if (dev->phy.type == B43_PHYTYPE_A)
4752 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4753 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4756 /* Shutdown a wireless core */
4757 /* Locking: wl->mutex */
4758 static void b43_wireless_core_exit(struct b43_wldev *dev)
4760 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4761 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4764 b43_set_status(dev, B43_STAT_UNINIT);
4766 /* Stop the microcode PSM. */
4767 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4768 B43_MACCTL_PSM_JMP0);
4770 switch (dev->dev->bus_type) {
4771 #ifdef CONFIG_B43_BCMA
4773 bcma_core_pci_down(dev->dev->bdev->bus);
4776 #ifdef CONFIG_B43_SSB
4786 dev->phy.ops->switch_analog(dev, 0);
4787 if (dev->wl->current_beacon) {
4788 dev_kfree_skb_any(dev->wl->current_beacon);
4789 dev->wl->current_beacon = NULL;
4792 b43_device_disable(dev, 0);
4793 b43_bus_may_powerdown(dev);
4796 /* Initialize a wireless core */
4797 static int b43_wireless_core_init(struct b43_wldev *dev)
4799 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4800 struct b43_phy *phy = &dev->phy;
4804 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4806 err = b43_bus_powerup(dev, 0);
4809 if (!b43_device_is_enabled(dev))
4810 b43_wireless_core_reset(dev, phy->gmode);
4812 /* Reset all data structures. */
4813 setup_struct_wldev_for_init(dev);
4814 phy->ops->prepare_structs(dev);
4816 /* Enable IRQ routing to this device. */
4817 switch (dev->dev->bus_type) {
4818 #ifdef CONFIG_B43_BCMA
4820 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
4821 dev->dev->bdev, true);
4822 bcma_core_pci_up(dev->dev->bdev->bus);
4825 #ifdef CONFIG_B43_SSB
4827 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4833 b43_imcfglo_timeouts_workaround(dev);
4834 b43_bluetooth_coext_disable(dev);
4835 if (phy->ops->prepare_hardware) {
4836 err = phy->ops->prepare_hardware(dev);
4840 err = b43_chip_init(dev);
4843 b43_shm_write16(dev, B43_SHM_SHARED,
4844 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4845 hf = b43_hf_read(dev);
4846 if (phy->type == B43_PHYTYPE_G) {
4850 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4851 hf |= B43_HF_OFDMPABOOST;
4853 if (phy->radio_ver == 0x2050) {
4854 if (phy->radio_rev == 6)
4855 hf |= B43_HF_4318TSSI;
4856 if (phy->radio_rev < 6)
4857 hf |= B43_HF_VCORECALC;
4859 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4860 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4861 #if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
4862 if (dev->dev->bus_type == B43_BUS_SSB &&
4863 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4864 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4865 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4867 hf &= ~B43_HF_SKCFPUP;
4868 b43_hf_write(dev, hf);
4870 /* tell the ucode MAC capabilities */
4871 if (dev->dev->core_rev >= 13) {
4872 u32 mac_hw_cap = b43_read32(dev, B43_MMIO_MAC_HW_CAP);
4874 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_L,
4875 mac_hw_cap & 0xffff);
4876 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_H,
4877 (mac_hw_cap >> 16) & 0xffff);
4880 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4881 B43_DEFAULT_LONG_RETRY_LIMIT);
4882 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4883 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4885 /* Disable sending probe responses from firmware.
4886 * Setting the MaxTime to one usec will always trigger
4887 * a timeout, so we never send any probe resp.
4888 * A timeout of zero is infinite. */
4889 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4891 b43_rate_memory_init(dev);
4892 b43_set_phytxctl_defaults(dev);
4894 /* Minimum Contention Window */
4895 if (phy->type == B43_PHYTYPE_B)
4896 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4898 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4899 /* Maximum Contention Window */
4900 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4902 /* write phytype and phyvers */
4903 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYTYPE, phy->type);
4904 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYVER, phy->rev);
4906 if (b43_bus_host_is_pcmcia(dev->dev) ||
4907 b43_bus_host_is_sdio(dev->dev)) {
4908 dev->__using_pio_transfers = true;
4909 err = b43_pio_init(dev);
4910 } else if (dev->use_pio) {
4911 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4912 "This should not be needed and will result in lower "
4914 dev->__using_pio_transfers = true;
4915 err = b43_pio_init(dev);
4917 dev->__using_pio_transfers = false;
4918 err = b43_dma_init(dev);
4923 b43_set_synth_pu_delay(dev, 1);
4924 b43_bluetooth_coext_enable(dev);
4926 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4927 b43_upload_card_macaddress(dev);
4928 b43_security_init(dev);
4930 ieee80211_wake_queues(dev->wl->hw);
4932 b43_set_status(dev, B43_STAT_INITIALIZED);
4940 b43_bus_may_powerdown(dev);
4941 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4945 static int b43_op_add_interface(struct ieee80211_hw *hw,
4946 struct ieee80211_vif *vif)
4948 struct b43_wl *wl = hw_to_b43_wl(hw);
4949 struct b43_wldev *dev;
4950 int err = -EOPNOTSUPP;
4952 /* TODO: allow WDS/AP devices to coexist */
4954 if (vif->type != NL80211_IFTYPE_AP &&
4955 vif->type != NL80211_IFTYPE_MESH_POINT &&
4956 vif->type != NL80211_IFTYPE_STATION &&
4957 vif->type != NL80211_IFTYPE_WDS &&
4958 vif->type != NL80211_IFTYPE_ADHOC)
4961 mutex_lock(&wl->mutex);
4963 goto out_mutex_unlock;
4965 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4967 dev = wl->current_dev;
4968 wl->operating = true;
4970 wl->if_type = vif->type;
4971 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4973 b43_adjust_opmode(dev);
4974 b43_set_pretbtt(dev);
4975 b43_set_synth_pu_delay(dev, 0);
4976 b43_upload_card_macaddress(dev);
4980 mutex_unlock(&wl->mutex);
4983 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4988 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4989 struct ieee80211_vif *vif)
4991 struct b43_wl *wl = hw_to_b43_wl(hw);
4992 struct b43_wldev *dev = wl->current_dev;
4994 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4996 mutex_lock(&wl->mutex);
4998 B43_WARN_ON(!wl->operating);
4999 B43_WARN_ON(wl->vif != vif);
5002 wl->operating = false;
5004 b43_adjust_opmode(dev);
5005 memset(wl->mac_addr, 0, ETH_ALEN);
5006 b43_upload_card_macaddress(dev);
5008 mutex_unlock(&wl->mutex);
5011 static int b43_op_start(struct ieee80211_hw *hw)
5013 struct b43_wl *wl = hw_to_b43_wl(hw);
5014 struct b43_wldev *dev = wl->current_dev;
5018 /* Kill all old instance specific information to make sure
5019 * the card won't use it in the short timeframe between start
5020 * and mac80211 reconfiguring it. */
5021 memset(wl->bssid, 0, ETH_ALEN);
5022 memset(wl->mac_addr, 0, ETH_ALEN);
5023 wl->filter_flags = 0;
5024 wl->radiotap_enabled = false;
5026 wl->beacon0_uploaded = false;
5027 wl->beacon1_uploaded = false;
5028 wl->beacon_templates_virgin = true;
5029 wl->radio_enabled = true;
5031 mutex_lock(&wl->mutex);
5033 if (b43_status(dev) < B43_STAT_INITIALIZED) {
5034 err = b43_wireless_core_init(dev);
5036 goto out_mutex_unlock;
5040 if (b43_status(dev) < B43_STAT_STARTED) {
5041 err = b43_wireless_core_start(dev);
5044 b43_wireless_core_exit(dev);
5045 goto out_mutex_unlock;
5049 /* XXX: only do if device doesn't support rfkill irq */
5050 wiphy_rfkill_start_polling(hw->wiphy);
5053 mutex_unlock(&wl->mutex);
5056 * Configuration may have been overwritten during initialization.
5057 * Reload the configuration, but only if initialization was
5058 * successful. Reloading the configuration after a failed init
5059 * may hang the system.
5062 b43_op_config(hw, ~0);
5067 static void b43_op_stop(struct ieee80211_hw *hw)
5069 struct b43_wl *wl = hw_to_b43_wl(hw);
5070 struct b43_wldev *dev = wl->current_dev;
5072 cancel_work_sync(&(wl->beacon_update_trigger));
5077 mutex_lock(&wl->mutex);
5078 if (b43_status(dev) >= B43_STAT_STARTED) {
5079 dev = b43_wireless_core_stop(dev);
5083 b43_wireless_core_exit(dev);
5084 wl->radio_enabled = false;
5087 mutex_unlock(&wl->mutex);
5089 cancel_work_sync(&(wl->txpower_adjust_work));
5092 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
5093 struct ieee80211_sta *sta, bool set)
5095 struct b43_wl *wl = hw_to_b43_wl(hw);
5097 /* FIXME: add locking */
5098 b43_update_templates(wl);
5103 static void b43_op_sta_notify(struct ieee80211_hw *hw,
5104 struct ieee80211_vif *vif,
5105 enum sta_notify_cmd notify_cmd,
5106 struct ieee80211_sta *sta)
5108 struct b43_wl *wl = hw_to_b43_wl(hw);
5110 B43_WARN_ON(!vif || wl->vif != vif);
5113 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
5115 struct b43_wl *wl = hw_to_b43_wl(hw);
5116 struct b43_wldev *dev;
5118 mutex_lock(&wl->mutex);
5119 dev = wl->current_dev;
5120 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5121 /* Disable CFP update during scan on other channels. */
5122 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
5124 mutex_unlock(&wl->mutex);
5127 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
5129 struct b43_wl *wl = hw_to_b43_wl(hw);
5130 struct b43_wldev *dev;
5132 mutex_lock(&wl->mutex);
5133 dev = wl->current_dev;
5134 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5135 /* Re-enable CFP update. */
5136 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
5138 mutex_unlock(&wl->mutex);
5141 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
5142 struct survey_info *survey)
5144 struct b43_wl *wl = hw_to_b43_wl(hw);
5145 struct b43_wldev *dev = wl->current_dev;
5146 struct ieee80211_conf *conf = &hw->conf;
5151 survey->channel = conf->chandef.chan;
5152 survey->filled = SURVEY_INFO_NOISE_DBM;
5153 survey->noise = dev->stats.link_noise;
5158 static const struct ieee80211_ops b43_hw_ops = {
5160 .conf_tx = b43_op_conf_tx,
5161 .add_interface = b43_op_add_interface,
5162 .remove_interface = b43_op_remove_interface,
5163 .config = b43_op_config,
5164 .bss_info_changed = b43_op_bss_info_changed,
5165 .configure_filter = b43_op_configure_filter,
5166 .set_key = b43_op_set_key,
5167 .update_tkip_key = b43_op_update_tkip_key,
5168 .get_stats = b43_op_get_stats,
5169 .get_tsf = b43_op_get_tsf,
5170 .set_tsf = b43_op_set_tsf,
5171 .start = b43_op_start,
5172 .stop = b43_op_stop,
5173 .set_tim = b43_op_beacon_set_tim,
5174 .sta_notify = b43_op_sta_notify,
5175 .sw_scan_start = b43_op_sw_scan_start_notifier,
5176 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
5177 .get_survey = b43_op_get_survey,
5178 .rfkill_poll = b43_rfkill_poll,
5181 /* Hard-reset the chip. Do not call this directly.
5182 * Use b43_controller_restart()
5184 static void b43_chip_reset(struct work_struct *work)
5186 struct b43_wldev *dev =
5187 container_of(work, struct b43_wldev, restart_work);
5188 struct b43_wl *wl = dev->wl;
5192 mutex_lock(&wl->mutex);
5194 prev_status = b43_status(dev);
5195 /* Bring the device down... */
5196 if (prev_status >= B43_STAT_STARTED) {
5197 dev = b43_wireless_core_stop(dev);
5203 if (prev_status >= B43_STAT_INITIALIZED)
5204 b43_wireless_core_exit(dev);
5206 /* ...and up again. */
5207 if (prev_status >= B43_STAT_INITIALIZED) {
5208 err = b43_wireless_core_init(dev);
5212 if (prev_status >= B43_STAT_STARTED) {
5213 err = b43_wireless_core_start(dev);
5215 b43_wireless_core_exit(dev);
5221 wl->current_dev = NULL; /* Failed to init the dev. */
5222 mutex_unlock(&wl->mutex);
5225 b43err(wl, "Controller restart FAILED\n");
5229 /* reload configuration */
5230 b43_op_config(wl->hw, ~0);
5232 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5234 b43info(wl, "Controller restarted\n");
5237 static int b43_setup_bands(struct b43_wldev *dev,
5238 bool have_2ghz_phy, bool have_5ghz_phy)
5240 struct ieee80211_hw *hw = dev->wl->hw;
5241 struct b43_phy *phy = &dev->phy;
5245 /* We don't support all 2 GHz channels on some devices */
5246 limited_2g = phy->radio_ver == 0x2057 &&
5247 (phy->radio_rev == 9 || phy->radio_rev == 14);
5248 limited_5g = phy->radio_ver == 0x2057 &&
5249 phy->radio_rev == 9;
5252 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = limited_2g ?
5253 &b43_band_2ghz_limited : &b43_band_2GHz;
5254 if (dev->phy.type == B43_PHYTYPE_N) {
5256 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = limited_5g ?
5257 &b43_band_5GHz_nphy_limited :
5258 &b43_band_5GHz_nphy;
5261 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5264 dev->phy.supports_2ghz = have_2ghz_phy;
5265 dev->phy.supports_5ghz = have_5ghz_phy;
5270 static void b43_wireless_core_detach(struct b43_wldev *dev)
5272 /* We release firmware that late to not be required to re-request
5273 * is all the time when we reinit the core. */
5274 b43_release_firmware(dev);
5278 static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5279 bool *have_5ghz_phy)
5283 #ifdef CONFIG_B43_BCMA
5284 if (dev->dev->bus_type == B43_BUS_BCMA &&
5285 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5286 dev_id = dev->dev->bdev->bus->host_pci->device;
5288 #ifdef CONFIG_B43_SSB
5289 if (dev->dev->bus_type == B43_BUS_SSB &&
5290 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5291 dev_id = dev->dev->sdev->bus->host_pci->device;
5293 /* Override with SPROM value if available */
5294 if (dev->dev->bus_sprom->dev_id)
5295 dev_id = dev->dev->bus_sprom->dev_id;
5297 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5299 case 0x4324: /* BCM4306 */
5300 case 0x4312: /* BCM4311 */
5301 case 0x4319: /* BCM4318 */
5302 case 0x4328: /* BCM4321 */
5303 case 0x432b: /* BCM4322 */
5304 case 0x4350: /* BCM43222 */
5305 case 0x4353: /* BCM43224 */
5306 case 0x0576: /* BCM43224 */
5307 case 0x435f: /* BCM6362 */
5308 case 0x4331: /* BCM4331 */
5309 case 0x4359: /* BCM43228 */
5310 case 0x43a0: /* BCM4360 */
5311 case 0x43b1: /* BCM4352 */
5312 /* Dual band devices */
5313 *have_2ghz_phy = true;
5314 *have_5ghz_phy = true;
5316 case 0x4321: /* BCM4306 */
5317 case 0x4313: /* BCM4311 */
5318 case 0x431a: /* BCM4318 */
5319 case 0x432a: /* BCM4321 */
5320 case 0x432d: /* BCM4322 */
5321 case 0x4352: /* BCM43222 */
5322 case 0x4333: /* BCM4331 */
5323 case 0x43a2: /* BCM4360 */
5324 case 0x43b3: /* BCM4352 */
5325 /* 5 GHz only devices */
5326 *have_2ghz_phy = false;
5327 *have_5ghz_phy = true;
5331 /* As a fallback, try to guess using PHY type */
5332 switch (dev->phy.type) {
5334 *have_2ghz_phy = false;
5335 *have_5ghz_phy = true;
5339 case B43_PHYTYPE_LP:
5340 case B43_PHYTYPE_HT:
5341 case B43_PHYTYPE_LCN:
5342 *have_2ghz_phy = true;
5343 *have_5ghz_phy = false;
5350 static int b43_wireless_core_attach(struct b43_wldev *dev)
5352 struct b43_wl *wl = dev->wl;
5353 struct b43_phy *phy = &dev->phy;
5356 bool have_2ghz_phy = false, have_5ghz_phy = false;
5358 /* Do NOT do any device initialization here.
5359 * Do it in wireless_core_init() instead.
5360 * This function is for gathering basic information about the HW, only.
5361 * Also some structs may be set up here. But most likely you want to have
5362 * that in core_init(), too.
5365 err = b43_bus_powerup(dev, 0);
5367 b43err(wl, "Bus powerup failed\n");
5371 phy->do_full_init = true;
5373 /* Try to guess supported bands for the first init needs */
5374 switch (dev->dev->bus_type) {
5375 #ifdef CONFIG_B43_BCMA
5377 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5378 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5379 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5382 #ifdef CONFIG_B43_SSB
5384 if (dev->dev->core_rev >= 5) {
5385 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5386 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5387 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5394 dev->phy.gmode = have_2ghz_phy;
5395 b43_wireless_core_reset(dev, dev->phy.gmode);
5397 /* Get the PHY type. */
5398 err = b43_phy_versioning(dev);
5402 /* Get real info about supported bands */
5403 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5405 /* We don't support 5 GHz on some PHYs yet */
5406 if (have_5ghz_phy) {
5407 switch (dev->phy.type) {
5410 case B43_PHYTYPE_LP:
5411 case B43_PHYTYPE_HT:
5412 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
5413 have_5ghz_phy = false;
5417 if (!have_2ghz_phy && !have_5ghz_phy) {
5418 b43err(wl, "b43 can't support any band on this device\n");
5423 err = b43_phy_allocate(dev);
5427 dev->phy.gmode = have_2ghz_phy;
5428 b43_wireless_core_reset(dev, dev->phy.gmode);
5430 err = b43_validate_chipaccess(dev);
5433 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5437 /* Now set some default "current_dev" */
5438 if (!wl->current_dev)
5439 wl->current_dev = dev;
5440 INIT_WORK(&dev->restart_work, b43_chip_reset);
5442 dev->phy.ops->switch_analog(dev, 0);
5443 b43_device_disable(dev, 0);
5444 b43_bus_may_powerdown(dev);
5452 b43_bus_may_powerdown(dev);
5456 static void b43_one_core_detach(struct b43_bus_dev *dev)
5458 struct b43_wldev *wldev;
5461 /* Do not cancel ieee80211-workqueue based work here.
5462 * See comment in b43_remove(). */
5464 wldev = b43_bus_get_wldev(dev);
5466 b43_debugfs_remove_device(wldev);
5467 b43_wireless_core_detach(wldev);
5468 list_del(&wldev->list);
5469 b43_bus_set_wldev(dev, NULL);
5473 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5475 struct b43_wldev *wldev;
5478 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5482 wldev->use_pio = b43_modparam_pio;
5485 b43_set_status(wldev, B43_STAT_UNINIT);
5486 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5487 INIT_LIST_HEAD(&wldev->list);
5489 err = b43_wireless_core_attach(wldev);
5491 goto err_kfree_wldev;
5493 b43_bus_set_wldev(dev, wldev);
5494 b43_debugfs_add_device(wldev);
5504 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5505 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5506 (pdev->device == _device) && \
5507 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5508 (pdev->subsystem_device == _subdevice) )
5510 #ifdef CONFIG_B43_SSB
5511 static void b43_sprom_fixup(struct ssb_bus *bus)
5513 struct pci_dev *pdev;
5515 /* boardflags workarounds */
5516 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5517 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
5518 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5519 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5520 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
5521 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5522 if (bus->bustype == SSB_BUSTYPE_PCI) {
5523 pdev = bus->host_pci;
5524 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5525 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5526 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5527 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5528 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5529 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5530 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5531 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5535 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5537 struct ieee80211_hw *hw = wl->hw;
5539 ssb_set_devtypedata(dev->sdev, NULL);
5540 ieee80211_free_hw(hw);
5544 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5546 struct ssb_sprom *sprom = dev->bus_sprom;
5547 struct ieee80211_hw *hw;
5552 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5554 b43err(NULL, "Could not allocate ieee80211 device\n");
5555 return ERR_PTR(-ENOMEM);
5557 wl = hw_to_b43_wl(hw);
5560 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5561 IEEE80211_HW_SIGNAL_DBM;
5563 hw->wiphy->interface_modes =
5564 BIT(NL80211_IFTYPE_AP) |
5565 BIT(NL80211_IFTYPE_MESH_POINT) |
5566 BIT(NL80211_IFTYPE_STATION) |
5567 BIT(NL80211_IFTYPE_WDS) |
5568 BIT(NL80211_IFTYPE_ADHOC);
5570 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5572 wl->hw_registred = false;
5574 SET_IEEE80211_DEV(hw, dev->dev);
5575 if (is_valid_ether_addr(sprom->et1mac))
5576 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5578 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5580 /* Initialize struct b43_wl */
5582 mutex_init(&wl->mutex);
5583 spin_lock_init(&wl->hardirq_lock);
5584 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5585 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5586 INIT_WORK(&wl->tx_work, b43_tx_work);
5588 /* Initialize queues and flags. */
5589 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5590 skb_queue_head_init(&wl->tx_queue[queue_num]);
5591 wl->tx_queue_stopped[queue_num] = 0;
5594 snprintf(chip_name, ARRAY_SIZE(chip_name),
5595 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5596 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5601 #ifdef CONFIG_B43_BCMA
5602 static int b43_bcma_probe(struct bcma_device *core)
5604 struct b43_bus_dev *dev;
5608 if (!modparam_allhwsupport &&
5609 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5610 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5614 dev = b43_bus_dev_bcma_init(core);
5618 wl = b43_wireless_init(dev);
5624 err = b43_one_core_attach(dev, wl);
5626 goto bcma_err_wireless_exit;
5628 /* setup and start work to load firmware */
5629 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5630 schedule_work(&wl->firmware_load);
5635 bcma_err_wireless_exit:
5636 ieee80211_free_hw(wl->hw);
5640 static void b43_bcma_remove(struct bcma_device *core)
5642 struct b43_wldev *wldev = bcma_get_drvdata(core);
5643 struct b43_wl *wl = wldev->wl;
5645 /* We must cancel any work here before unregistering from ieee80211,
5646 * as the ieee80211 unreg will destroy the workqueue. */
5647 cancel_work_sync(&wldev->restart_work);
5648 cancel_work_sync(&wl->firmware_load);
5651 if (!wldev->fw.ucode.data)
5652 return; /* NULL if firmware never loaded */
5653 if (wl->current_dev == wldev && wl->hw_registred) {
5654 b43_leds_stop(wldev);
5655 ieee80211_unregister_hw(wl->hw);
5658 b43_one_core_detach(wldev->dev);
5660 /* Unregister HW RNG driver */
5663 b43_leds_unregister(wl);
5665 ieee80211_free_hw(wl->hw);
5668 static struct bcma_driver b43_bcma_driver = {
5669 .name = KBUILD_MODNAME,
5670 .id_table = b43_bcma_tbl,
5671 .probe = b43_bcma_probe,
5672 .remove = b43_bcma_remove,
5676 #ifdef CONFIG_B43_SSB
5678 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5680 struct b43_bus_dev *dev;
5684 dev = b43_bus_dev_ssb_init(sdev);
5688 wl = ssb_get_devtypedata(sdev);
5690 b43err(NULL, "Dual-core devices are not supported\n");
5692 goto err_ssb_kfree_dev;
5695 b43_sprom_fixup(sdev->bus);
5697 wl = b43_wireless_init(dev);
5700 goto err_ssb_kfree_dev;
5702 ssb_set_devtypedata(sdev, wl);
5703 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5705 err = b43_one_core_attach(dev, wl);
5707 goto err_ssb_wireless_exit;
5709 /* setup and start work to load firmware */
5710 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5711 schedule_work(&wl->firmware_load);
5715 err_ssb_wireless_exit:
5716 b43_wireless_exit(dev, wl);
5722 static void b43_ssb_remove(struct ssb_device *sdev)
5724 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5725 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5726 struct b43_bus_dev *dev = wldev->dev;
5728 /* We must cancel any work here before unregistering from ieee80211,
5729 * as the ieee80211 unreg will destroy the workqueue. */
5730 cancel_work_sync(&wldev->restart_work);
5731 cancel_work_sync(&wl->firmware_load);
5734 if (!wldev->fw.ucode.data)
5735 return; /* NULL if firmware never loaded */
5736 if (wl->current_dev == wldev && wl->hw_registred) {
5737 b43_leds_stop(wldev);
5738 ieee80211_unregister_hw(wl->hw);
5741 b43_one_core_detach(dev);
5743 /* Unregister HW RNG driver */
5746 b43_leds_unregister(wl);
5747 b43_wireless_exit(dev, wl);
5750 static struct ssb_driver b43_ssb_driver = {
5751 .name = KBUILD_MODNAME,
5752 .id_table = b43_ssb_tbl,
5753 .probe = b43_ssb_probe,
5754 .remove = b43_ssb_remove,
5756 #endif /* CONFIG_B43_SSB */
5758 /* Perform a hardware reset. This can be called from any context. */
5759 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5761 /* Must avoid requeueing, if we are in shutdown. */
5762 if (b43_status(dev) < B43_STAT_INITIALIZED)
5764 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5765 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5768 static void b43_print_driverinfo(void)
5770 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5771 *feat_leds = "", *feat_sdio = "";
5773 #ifdef CONFIG_B43_PCI_AUTOSELECT
5776 #ifdef CONFIG_B43_PCMCIA
5779 #ifdef CONFIG_B43_PHY_N
5782 #ifdef CONFIG_B43_LEDS
5785 #ifdef CONFIG_B43_SDIO
5788 printk(KERN_INFO "Broadcom 43xx driver loaded "
5789 "[ Features: %s%s%s%s%s ]\n",
5790 feat_pci, feat_pcmcia, feat_nphy,
5791 feat_leds, feat_sdio);
5794 static int __init b43_init(void)
5799 err = b43_pcmcia_init();
5802 err = b43_sdio_init();
5804 goto err_pcmcia_exit;
5805 #ifdef CONFIG_B43_BCMA
5806 err = bcma_driver_register(&b43_bcma_driver);
5810 #ifdef CONFIG_B43_SSB
5811 err = ssb_driver_register(&b43_ssb_driver);
5813 goto err_bcma_driver_exit;
5815 b43_print_driverinfo();
5819 #ifdef CONFIG_B43_SSB
5820 err_bcma_driver_exit:
5822 #ifdef CONFIG_B43_BCMA
5823 bcma_driver_unregister(&b43_bcma_driver);
5834 static void __exit b43_exit(void)
5836 #ifdef CONFIG_B43_SSB
5837 ssb_driver_unregister(&b43_ssb_driver);
5839 #ifdef CONFIG_B43_BCMA
5840 bcma_driver_unregister(&b43_bcma_driver);
5847 module_init(b43_init)
5848 module_exit(b43_exit)