3 Broadcom B43 wireless driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
29 #include "phy_common.h"
40 int b43_phy_allocate(struct b43_wldev *dev)
42 struct b43_phy *phy = &(dev->phy);
49 #ifdef CONFIG_B43_PHY_G
50 phy->ops = &b43_phyops_g;
54 #ifdef CONFIG_B43_PHY_N
55 phy->ops = &b43_phyops_n;
59 #ifdef CONFIG_B43_PHY_LP
60 phy->ops = &b43_phyops_lp;
64 #ifdef CONFIG_B43_PHY_HT
65 phy->ops = &b43_phyops_ht;
69 #ifdef CONFIG_B43_PHY_LCN
70 phy->ops = &b43_phyops_lcn;
74 if (B43_WARN_ON(!phy->ops))
77 err = phy->ops->allocate(dev);
84 void b43_phy_free(struct b43_wldev *dev)
86 dev->phy.ops->free(dev);
90 int b43_phy_init(struct b43_wldev *dev)
92 struct b43_phy *phy = &dev->phy;
93 const struct b43_phy_operations *ops = phy->ops;
96 /* During PHY init we need to use some channel. On the first init this
97 * function is called *before* b43_op_config, so our pointer is NULL.
100 phy->chandef = &dev->wl->hw->conf.chandef;
101 phy->channel = phy->chandef->chan->hw_value;
104 phy->ops->switch_analog(dev, true);
105 b43_software_rfkill(dev, false);
107 err = ops->init(dev);
109 b43err(dev->wl, "PHY init failed\n");
112 phy->do_full_init = false;
114 err = b43_switch_channel(dev, phy->channel);
116 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
123 phy->do_full_init = true;
127 b43_software_rfkill(dev, true);
132 void b43_phy_exit(struct b43_wldev *dev)
134 const struct b43_phy_operations *ops = dev->phy.ops;
136 b43_software_rfkill(dev, true);
137 dev->phy.do_full_init = true;
142 bool b43_has_hardware_pctl(struct b43_wldev *dev)
144 if (!dev->phy.hardware_power_control)
146 if (!dev->phy.ops->supports_hwpctl)
148 return dev->phy.ops->supports_hwpctl(dev);
151 void b43_radio_lock(struct b43_wldev *dev)
156 B43_WARN_ON(dev->phy.radio_locked);
157 dev->phy.radio_locked = true;
160 macctl = b43_read32(dev, B43_MMIO_MACCTL);
161 macctl |= B43_MACCTL_RADIOLOCK;
162 b43_write32(dev, B43_MMIO_MACCTL, macctl);
163 /* Commit the write and wait for the firmware
164 * to finish any radio register access. */
165 b43_read32(dev, B43_MMIO_MACCTL);
169 void b43_radio_unlock(struct b43_wldev *dev)
174 B43_WARN_ON(!dev->phy.radio_locked);
175 dev->phy.radio_locked = false;
178 /* Commit any write */
179 b43_read16(dev, B43_MMIO_PHY_VER);
181 macctl = b43_read32(dev, B43_MMIO_MACCTL);
182 macctl &= ~B43_MACCTL_RADIOLOCK;
183 b43_write32(dev, B43_MMIO_MACCTL, macctl);
186 void b43_phy_lock(struct b43_wldev *dev)
189 B43_WARN_ON(dev->phy.phy_locked);
190 dev->phy.phy_locked = true;
192 B43_WARN_ON(dev->dev->core_rev < 3);
194 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
195 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
198 void b43_phy_unlock(struct b43_wldev *dev)
201 B43_WARN_ON(!dev->phy.phy_locked);
202 dev->phy.phy_locked = false;
204 B43_WARN_ON(dev->dev->core_rev < 3);
206 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
207 b43_power_saving_ctl_bits(dev, 0);
210 static inline void assert_mac_suspended(struct b43_wldev *dev)
214 if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
215 (dev->mac_suspended <= 0)) {
216 b43dbg(dev->wl, "PHY/RADIO register access with "
222 u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
224 assert_mac_suspended(dev);
225 dev->phy.writes_counter = 0;
226 return dev->phy.ops->radio_read(dev, reg);
229 void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
231 assert_mac_suspended(dev);
232 if (b43_bus_host_is_pci(dev->dev) &&
233 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
234 b43_read32(dev, B43_MMIO_MACCTL);
235 dev->phy.writes_counter = 1;
237 dev->phy.ops->radio_write(dev, reg, value);
240 void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
242 b43_radio_write16(dev, offset,
243 b43_radio_read16(dev, offset) & mask);
246 void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
248 b43_radio_write16(dev, offset,
249 b43_radio_read16(dev, offset) | set);
252 void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
254 b43_radio_write16(dev, offset,
255 (b43_radio_read16(dev, offset) & mask) | set);
258 bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
259 u16 value, int delay, int timeout)
264 for (i = 0; i < timeout; i += delay) {
265 val = b43_radio_read(dev, offset);
266 if ((val & mask) == value)
273 u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
275 assert_mac_suspended(dev);
276 dev->phy.writes_counter = 0;
278 if (dev->phy.ops->phy_read)
279 return dev->phy.ops->phy_read(dev, reg);
281 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
282 return b43_read16(dev, B43_MMIO_PHY_DATA);
285 void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
287 assert_mac_suspended(dev);
288 if (b43_bus_host_is_pci(dev->dev) &&
289 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
290 b43_read16(dev, B43_MMIO_PHY_VER);
291 dev->phy.writes_counter = 1;
294 if (dev->phy.ops->phy_write)
295 return dev->phy.ops->phy_write(dev, reg, value);
297 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
298 b43_write16(dev, B43_MMIO_PHY_DATA, value);
301 void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
303 assert_mac_suspended(dev);
304 dev->phy.ops->phy_write(dev, destreg,
305 dev->phy.ops->phy_read(dev, srcreg));
308 void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
310 if (dev->phy.ops->phy_maskset) {
311 assert_mac_suspended(dev);
312 dev->phy.ops->phy_maskset(dev, offset, mask, 0);
314 b43_phy_write(dev, offset,
315 b43_phy_read(dev, offset) & mask);
319 void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
321 if (dev->phy.ops->phy_maskset) {
322 assert_mac_suspended(dev);
323 dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
325 b43_phy_write(dev, offset,
326 b43_phy_read(dev, offset) | set);
330 void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
332 if (dev->phy.ops->phy_maskset) {
333 assert_mac_suspended(dev);
334 dev->phy.ops->phy_maskset(dev, offset, mask, set);
336 b43_phy_write(dev, offset,
337 (b43_phy_read(dev, offset) & mask) | set);
341 void b43_phy_put_into_reset(struct b43_wldev *dev)
345 switch (dev->dev->bus_type) {
346 #ifdef CONFIG_B43_BCMA
348 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
349 tmp &= ~B43_BCMA_IOCTL_GMODE;
350 tmp |= B43_BCMA_IOCTL_PHY_RESET;
351 tmp |= BCMA_IOCTL_FGC;
352 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
355 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
356 tmp &= ~BCMA_IOCTL_FGC;
357 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
361 #ifdef CONFIG_B43_SSB
363 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
364 tmp &= ~B43_TMSLOW_GMODE;
365 tmp |= B43_TMSLOW_PHYRESET;
366 tmp |= SSB_TMSLOW_FGC;
367 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
368 usleep_range(1000, 2000);
370 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
371 tmp &= ~SSB_TMSLOW_FGC;
372 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
373 usleep_range(1000, 2000);
380 void b43_phy_take_out_of_reset(struct b43_wldev *dev)
384 switch (dev->dev->bus_type) {
385 #ifdef CONFIG_B43_BCMA
387 /* Unset reset bit (with forcing clock) */
388 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
389 tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
390 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
391 tmp |= BCMA_IOCTL_FGC;
392 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
395 /* Do not force clock anymore */
396 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
397 tmp &= ~BCMA_IOCTL_FGC;
398 tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
399 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
403 #ifdef CONFIG_B43_SSB
405 /* Unset reset bit (with forcing clock) */
406 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
407 tmp &= ~B43_TMSLOW_PHYRESET;
408 tmp &= ~B43_TMSLOW_PHYCLKEN;
409 tmp |= SSB_TMSLOW_FGC;
410 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
411 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
412 usleep_range(1000, 2000);
414 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
415 tmp &= ~SSB_TMSLOW_FGC;
416 tmp |= B43_TMSLOW_PHYCLKEN;
417 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
418 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
419 usleep_range(1000, 2000);
425 int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
427 struct b43_phy *phy = &(dev->phy);
428 u16 channelcookie, savedcookie;
431 /* First we set the channel radio code to prevent the
432 * firmware from sending ghost packets.
434 channelcookie = new_channel;
435 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
436 channelcookie |= B43_SHM_SH_CHAN_5GHZ;
437 /* FIXME: set 40Mhz flag if required */
439 channelcookie |= B43_SHM_SH_CHAN_40MHZ;
440 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
441 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
443 /* Now try to switch the PHY hardware channel. */
444 err = phy->ops->switch_channel(dev, new_channel);
446 goto err_restore_cookie;
448 /* Wait for the radio to tune to the channel and stabilize. */
454 b43_shm_write16(dev, B43_SHM_SHARED,
455 B43_SHM_SH_CHAN, savedcookie);
460 void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
462 struct b43_phy *phy = &dev->phy;
464 b43_mac_suspend(dev);
465 phy->ops->software_rfkill(dev, blocked);
466 phy->radio_on = !blocked;
471 * b43_phy_txpower_adjust_work - TX power workqueue.
473 * Workqueue for updating the TX power parameters in hardware.
475 void b43_phy_txpower_adjust_work(struct work_struct *work)
477 struct b43_wl *wl = container_of(work, struct b43_wl,
478 txpower_adjust_work);
479 struct b43_wldev *dev;
481 mutex_lock(&wl->mutex);
482 dev = wl->current_dev;
484 if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
485 dev->phy.ops->adjust_txpower(dev);
487 mutex_unlock(&wl->mutex);
490 void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
492 struct b43_phy *phy = &dev->phy;
493 unsigned long now = jiffies;
494 enum b43_txpwr_result result;
496 if (!(flags & B43_TXPWR_IGNORE_TIME)) {
497 /* Check if it's time for a TXpower check. */
498 if (time_before(now, phy->next_txpwr_check_time))
499 return; /* Not yet */
501 /* The next check will be needed in two seconds, or later. */
502 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
504 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
505 (dev->dev->board_type == SSB_BOARD_BU4306))
506 return; /* No software txpower adjustment needed */
508 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
509 if (result == B43_TXPWR_RES_DONE)
510 return; /* We are done. */
511 B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
512 B43_WARN_ON(phy->ops->adjust_txpower == NULL);
514 /* We must adjust the transmission power in hardware.
515 * Schedule b43_phy_txpower_adjust_work(). */
516 ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
519 int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
521 const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
522 unsigned int a, b, c, d;
523 unsigned int average;
526 tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
528 b = (tmp >> 8) & 0xFF;
529 c = (tmp >> 16) & 0xFF;
530 d = (tmp >> 24) & 0xFF;
531 if (a == 0 || a == B43_TSSI_MAX ||
532 b == 0 || b == B43_TSSI_MAX ||
533 c == 0 || c == B43_TSSI_MAX ||
534 d == 0 || d == B43_TSSI_MAX)
536 /* The values are OK. Clear them. */
537 tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
538 (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
539 b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
548 /* Get the average of the values with 0.5 added to each value. */
549 average = (a + b + c + d + 2) / 4;
551 /* Adjust for CCK-boost */
552 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
554 average = (average >= 13) ? (average - 13) : 0;
560 void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
562 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
566 bool b43_is_40mhz(struct b43_wldev *dev)
568 return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
571 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
572 void b43_phy_force_clock(struct b43_wldev *dev, bool force)
576 WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
577 dev->phy.type != B43_PHYTYPE_HT);
579 switch (dev->dev->bus_type) {
580 #ifdef CONFIG_B43_BCMA
582 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
584 tmp |= BCMA_IOCTL_FGC;
586 tmp &= ~BCMA_IOCTL_FGC;
587 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
590 #ifdef CONFIG_B43_SSB
592 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
594 tmp |= SSB_TMSLOW_FGC;
596 tmp &= ~SSB_TMSLOW_FGC;
597 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
603 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
604 struct b43_c32 b43_cordic(int theta)
606 static const u32 arctg[] = {
607 2949120, 1740967, 919879, 466945, 234379, 117304,
608 58666, 29335, 14668, 7334, 3667, 1833,
609 917, 458, 229, 115, 57, 29,
615 struct b43_c32 ret = { .i = 39797, .q = 0, };
617 while (theta > (180 << 16))
618 theta -= (360 << 16);
619 while (theta < -(180 << 16))
620 theta += (360 << 16);
622 if (theta > (90 << 16)) {
623 theta -= (180 << 16);
625 } else if (theta < -(90 << 16)) {
626 theta += (180 << 16);
630 for (i = 0; i <= 17; i++) {
632 tmp = ret.i - (ret.q >> i);
637 tmp = ret.i + (ret.q >> i);