drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/types.h>
  28
  29 #include "b43.h"
  30 #include "phy_n.h"
  31 #include "tables_nphy.h"
  32 #include "main.h"
  33
  34 struct nphy_txgains {
  35         u16 txgm[2];
  36         u16 pga[2];
  37         u16 pad[2];
  38         u16 ipa[2];
  39 };
  40
  41 struct nphy_iqcal_params {
  42         u16 txgm;
  43         u16 pga;
  44         u16 pad;
  45         u16 ipa;
  46         u16 cal_gain;
  47         u16 ncorr[5];
  48 };
  49
  50 struct nphy_iq_est {
  51         s32 iq0_prod;
  52         u32 i0_pwr;
  53         u32 q0_pwr;
  54         s32 iq1_prod;
  55         u32 i1_pwr;
  56         u32 q1_pwr;
  57 };
  58
  59 enum b43_nphy_rf_sequence {
  60         B43_RFSEQ_RX2TX,
  61         B43_RFSEQ_TX2RX,
  62         B43_RFSEQ_RESET2RX,
  63         B43_RFSEQ_UPDATE_GAINH,
  64         B43_RFSEQ_UPDATE_GAINL,
  65         B43_RFSEQ_UPDATE_GAINU,
  66 };
  67
  68 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  69                                         u8 *events, u8 *delays, u8 length);
  70 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  71                                        enum b43_nphy_rf_sequence seq);
  72 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  73                                                 u16 value, u8 core, bool off);
  74 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  75                                                 u16 value, u8 core);
  76
  77 static inline bool b43_channel_type_is_40mhz(
  78                                         enum nl80211_channel_type channel_type)
  79 {
  80         return (channel_type == NL80211_CHAN_HT40MINUS ||
  81                 channel_type == NL80211_CHAN_HT40PLUS);
  82 }
  83
  84 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  85 {//TODO
  86 }
  87
  88 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  89 {//TODO
  90 }
  91
  92 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  93                                                         bool ignore_tssi)
  94 {//TODO
  95         return B43_TXPWR_RES_DONE;
  96 }
  97
  98 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  99                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 100 {
 101         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 102         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 103         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 104         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 105         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 106
 107         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 108         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 109         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 110         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 111         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 112
 113         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 114         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 115         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 116         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 117         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 118
 119         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 120         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 121         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 122         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 123         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 124
 125         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 126         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 127         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 128         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 129         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 130
 131         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 132         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 133 }
 134
 135 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 136                                    const struct b43_phy_n_sfo_cfg *e)
 137 {
 138         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 139         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 140         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 141         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 142         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 143         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 144 }
 145
 146 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 147 {
 148         //TODO
 149 }
 150
 151
 152 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 153 static void b43_radio_2055_setup(struct b43_wldev *dev,
 154                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 155 {
 156         B43_WARN_ON(dev->phy.rev >= 3);
 157
 158         b43_chantab_radio_upload(dev, e);
 159         udelay(50);
 160         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 161         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 162         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 163         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 164         udelay(300);
 165 }
 166
 167 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 168 {
 169         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 170                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 171         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 172                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 173                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 174         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 175                     B43_NPHY_RFCTL_CMD_PORFORCE);
 176 }
 177
 178 static void b43_radio_init2055_post(struct b43_wldev *dev)
 179 {
 180         struct b43_phy_n *nphy = dev->phy.n;
 181         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 182         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 183         int i;
 184         u16 val;
 185         bool workaround = false;
 186
 187         if (sprom->revision < 4)
 188                 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
 189                                 binfo->type != 0x46D ||
 190                                 binfo->rev < 0x41);
 191         else
 192                 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0);
 193
 194         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 195         if (workaround) {
 196                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 197                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 198         }
 199         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 200         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 201         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 202         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 203         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 204         msleep(1);
 205         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 206         for (i = 0; i < 200; i++) {
 207                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 208                 if (val & 0x80) {
 209                         i = 0;
 210                         break;
 211                 }
 212                 udelay(10);
 213         }
 214         if (i)
 215                 b43err(dev->wl, "radio post init timeout\n");
 216         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 217         b43_switch_channel(dev, dev->phy.channel);
 218         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 219         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 220         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 221         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 222         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 223         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 224         if (!nphy->gain_boost) {
 225                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 226                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 227         } else {
 228                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 229                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 230         }
 231         udelay(2);
 232 }
 233
 234 /*
 235  * Initialize a Broadcom 2055 N-radio
 236  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 237  */
 238 static void b43_radio_init2055(struct b43_wldev *dev)
 239 {
 240         b43_radio_init2055_pre(dev);
 241         if (b43_status(dev) < B43_STAT_INITIALIZED)
 242                 b2055_upload_inittab(dev, 0, 1);
 243         else
 244                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 245         b43_radio_init2055_post(dev);
 246 }
 247
 248 /*
 249  * Initialize a Broadcom 2056 N-radio
 250  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 251  */
 252 static void b43_radio_init2056(struct b43_wldev *dev)
 253 {
 254         /* TODO */
 255 }
 256
 257
 258 /*
 259  * Upload the N-PHY tables.
 260  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 261  */
 262 static void b43_nphy_tables_init(struct b43_wldev *dev)
 263 {
 264         if (dev->phy.rev < 3)
 265                 b43_nphy_rev0_1_2_tables_init(dev);
 266         else
 267                 b43_nphy_rev3plus_tables_init(dev);
 268 }
 269
 270 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 271 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 272 {
 273         struct b43_phy_n *nphy = dev->phy.n;
 274         enum ieee80211_band band;
 275         u16 tmp;
 276
 277         if (!enable) {
 278                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 279                                                        B43_NPHY_RFCTL_INTC1);
 280                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 281                                                        B43_NPHY_RFCTL_INTC2);
 282                 band = b43_current_band(dev->wl);
 283                 if (dev->phy.rev >= 3) {
 284                         if (band == IEEE80211_BAND_5GHZ)
 285                                 tmp = 0x600;
 286                         else
 287                                 tmp = 0x480;
 288                 } else {
 289                         if (band == IEEE80211_BAND_5GHZ)
 290                                 tmp = 0x180;
 291                         else
 292                                 tmp = 0x120;
 293                 }
 294                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 295                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 296         } else {
 297                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 298                                 nphy->rfctrl_intc1_save);
 299                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 300                                 nphy->rfctrl_intc2_save);
 301         }
 302 }
 303
 304 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 305 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 306 {
 307         struct b43_phy_n *nphy = dev->phy.n;
 308         u16 tmp;
 309         enum ieee80211_band band = b43_current_band(dev->wl);
 310         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 311                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 312
 313         if (dev->phy.rev >= 3) {
 314                 if (ipa) {
 315                         tmp = 4;
 316                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 317                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 318                 }
 319
 320                 tmp = 1;
 321                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 322                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 323         }
 324 }
 325
 326 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 327 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 328 {
 329         u32 tmslow;
 330
 331         if (dev->phy.type != B43_PHYTYPE_N)
 332                 return;
 333
 334         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 335         if (force)
 336                 tmslow |= SSB_TMSLOW_FGC;
 337         else
 338                 tmslow &= ~SSB_TMSLOW_FGC;
 339         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 340 }
 341
 342 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 343 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 344 {
 345         u16 bbcfg;
 346
 347         b43_nphy_bmac_clock_fgc(dev, 1);
 348         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 349         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 350         udelay(1);
 351         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 352         b43_nphy_bmac_clock_fgc(dev, 0);
 353         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 354 }
 355
 356 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 357 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 358 {
 359         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 360
 361         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 362         if (preamble == 1)
 363                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 364         else
 365                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 366
 367         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 368 }
 369
 370 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 371 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 372 {
 373         struct b43_phy_n *nphy = dev->phy.n;
 374
 375         bool override = false;
 376         u16 chain = 0x33;
 377
 378         if (nphy->txrx_chain == 0) {
 379                 chain = 0x11;
 380                 override = true;
 381         } else if (nphy->txrx_chain == 1) {
 382                 chain = 0x22;
 383                 override = true;
 384         }
 385
 386         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 387                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 388                         chain);
 389
 390         if (override)
 391                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 392                                 B43_NPHY_RFSEQMODE_CAOVER);
 393         else
 394                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 395                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 396 }
 397
 398 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 399 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 400                                 u16 samps, u8 time, bool wait)
 401 {
 402         int i;
 403         u16 tmp;
 404
 405         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 406         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 407         if (wait)
 408                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 409         else
 410                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 411
 412         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 413
 414         for (i = 1000; i; i--) {
 415                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 416                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 417                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 418                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 419                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 420                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 421                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 422                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 423
 424                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 425                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 426                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 427                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 428                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 429                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 430                         return;
 431                 }
 432                 udelay(10);
 433         }
 434         memset(est, 0, sizeof(*est));
 435 }
 436
 437 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 438 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 439                                         struct b43_phy_n_iq_comp *pcomp)
 440 {
 441         if (write) {
 442                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 443                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 444                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 445                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 446         } else {
 447                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 448                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 449                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 450                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 451         }
 452 }
 453
 454 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 455 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 456 {
 457         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 458
 459         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 460         if (core == 0) {
 461                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 462                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 463         } else {
 464                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 465                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 466         }
 467         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 468         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 469         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 470         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 471         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 472         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 473         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 474         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 475 }
 476
 477 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 478 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 479 {
 480         u8 rxval, txval;
 481         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 482
 483         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 484         if (core == 0) {
 485                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 486                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 487         } else {
 488                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 489                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 490         }
 491         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 492         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 493         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 494         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 495         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 496         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 497         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 498         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 499
 500         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 501         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 502
 503         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 504                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
 505                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 506         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 507                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 508         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 509                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 510         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 511                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 512
 513         if (core == 0) {
 514                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 515                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 516         } else {
 517                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 518                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 519         }
 520
 521         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 522         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 523         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 524
 525         if (core == 0) {
 526                 rxval = 1;
 527                 txval = 8;
 528         } else {
 529                 rxval = 4;
 530                 txval = 2;
 531         }
 532         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 533         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 534 }
 535
 536 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 537 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 538 {
 539         int i;
 540         s32 iq;
 541         u32 ii;
 542         u32 qq;
 543         int iq_nbits, qq_nbits;
 544         int arsh, brsh;
 545         u16 tmp, a, b;
 546
 547         struct nphy_iq_est est;
 548         struct b43_phy_n_iq_comp old;
 549         struct b43_phy_n_iq_comp new = { };
 550         bool error = false;
 551
 552         if (mask == 0)
 553                 return;
 554
 555         b43_nphy_rx_iq_coeffs(dev, false, &old);
 556         b43_nphy_rx_iq_coeffs(dev, true, &new);
 557         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 558         new = old;
 559
 560         for (i = 0; i < 2; i++) {
 561                 if (i == 0 && (mask & 1)) {
 562                         iq = est.iq0_prod;
 563                         ii = est.i0_pwr;
 564                         qq = est.q0_pwr;
 565                 } else if (i == 1 && (mask & 2)) {
 566                         iq = est.iq1_prod;
 567                         ii = est.i1_pwr;
 568                         qq = est.q1_pwr;
 569                 } else {
 570                         B43_WARN_ON(1);
 571                         continue;
 572                 }
 573
 574                 if (ii + qq < 2) {
 575                         error = true;
 576                         break;
 577                 }
 578
 579                 iq_nbits = fls(abs(iq));
 580                 qq_nbits = fls(qq);
 581
 582                 arsh = iq_nbits - 20;
 583                 if (arsh >= 0) {
 584                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 585                         tmp = ii >> arsh;
 586                 } else {
 587                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 588                         tmp = ii << -arsh;
 589                 }
 590                 if (tmp == 0) {
 591                         error = true;
 592                         break;
 593                 }
 594                 a /= tmp;
 595
 596                 brsh = qq_nbits - 11;
 597                 if (brsh >= 0) {
 598                         b = (qq << (31 - qq_nbits));
 599                         tmp = ii >> brsh;
 600                 } else {
 601                         b = (qq << (31 - qq_nbits));
 602                         tmp = ii << -brsh;
 603                 }
 604                 if (tmp == 0) {
 605                         error = true;
 606                         break;
 607                 }
 608                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 609
 610                 if (i == 0 && (mask & 0x1)) {
 611                         if (dev->phy.rev >= 3) {
 612                                 new.a0 = a & 0x3FF;
 613                                 new.b0 = b & 0x3FF;
 614                         } else {
 615                                 new.a0 = b & 0x3FF;
 616                                 new.b0 = a & 0x3FF;
 617                         }
 618                 } else if (i == 1 && (mask & 0x2)) {
 619                         if (dev->phy.rev >= 3) {
 620                                 new.a1 = a & 0x3FF;
 621                                 new.b1 = b & 0x3FF;
 622                         } else {
 623                                 new.a1 = b & 0x3FF;
 624                                 new.b1 = a & 0x3FF;
 625                         }
 626                 }
 627         }
 628
 629         if (error)
 630                 new = old;
 631
 632         b43_nphy_rx_iq_coeffs(dev, true, &new);
 633 }
 634
 635 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 636 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 637 {
 638         u16 array[4];
 639         int i;
 640
 641         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 642         for (i = 0; i < 4; i++)
 643                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 644
 645         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 646         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 647         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 648         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 649 }
 650
 651 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 652 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 653 {
 654         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 655         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 656 }
 657
 658 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 659 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 660 {
 661         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 662         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 663 }
 664
 665 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 666 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 667 {
 668         if (dev->phy.rev >= 3) {
 669                 if (!init)
 670                         return;
 671                 if (0 /* FIXME */) {
 672                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 673                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 674                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 675                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 676                 }
 677         } else {
 678                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 679                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 680
 681                 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
 682                                         0xFC00);
 683                 b43_write32(dev, B43_MMIO_MACCTL,
 684                         b43_read32(dev, B43_MMIO_MACCTL) &
 685                         ~B43_MACCTL_GPOUTSMSK);
 686                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 687                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 688                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 689                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 690
 691                 if (init) {
 692                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 693                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 694                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 695                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 696                 }
 697         }
 698 }
 699
 700 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 701 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 702 {
 703         u16 tmp;
 704
 705         if (dev->dev->id.revision == 16)
 706                 b43_mac_suspend(dev);
 707
 708         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 709         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 710                 B43_NPHY_CLASSCTL_WAITEDEN);
 711         tmp &= ~mask;
 712         tmp |= (val & mask);
 713         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 714
 715         if (dev->dev->id.revision == 16)
 716                 b43_mac_enable(dev);
 717
 718         return tmp;
 719 }
 720
 721 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 722 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 723 {
 724         struct b43_phy *phy = &dev->phy;
 725         struct b43_phy_n *nphy = phy->n;
 726
 727         if (enable) {
 728                 u16 clip[] = { 0xFFFF, 0xFFFF };
 729                 if (nphy->deaf_count++ == 0) {
 730                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 731                         b43_nphy_classifier(dev, 0x7, 0);
 732                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 733                         b43_nphy_write_clip_detection(dev, clip);
 734                 }
 735                 b43_nphy_reset_cca(dev);
 736         } else {
 737                 if (--nphy->deaf_count == 0) {
 738                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 739                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 740                 }
 741         }
 742 }
 743
 744 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 745 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 746 {
 747         struct b43_phy_n *nphy = dev->phy.n;
 748         u16 tmp;
 749
 750         if (nphy->hang_avoid)
 751                 b43_nphy_stay_in_carrier_search(dev, 1);
 752
 753         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 754         if (tmp & 0x1)
 755                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 756         else if (tmp & 0x2)
 757                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
 758
 759         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 760
 761         if (nphy->bb_mult_save & 0x80000000) {
 762                 tmp = nphy->bb_mult_save & 0xFFFF;
 763                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 764                 nphy->bb_mult_save = 0;
 765         }
 766
 767         if (nphy->hang_avoid)
 768                 b43_nphy_stay_in_carrier_search(dev, 0);
 769 }
 770
 771 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 772 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 773 {
 774         struct b43_phy_n *nphy = dev->phy.n;
 775
 776         u8 channel = dev->phy.channel;
 777         int tone[2] = { 57, 58 };
 778         u32 noise[2] = { 0x3FF, 0x3FF };
 779
 780         B43_WARN_ON(dev->phy.rev < 3);
 781
 782         if (nphy->hang_avoid)
 783                 b43_nphy_stay_in_carrier_search(dev, 1);
 784
 785         if (nphy->gband_spurwar_en) {
 786                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 787                 if (channel == 11 && dev->phy.is_40mhz)
 788                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 789                 else
 790                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 791                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 792         }
 793
 794         if (nphy->aband_spurwar_en) {
 795                 if (channel == 54) {
 796                         tone[0] = 0x20;
 797                         noise[0] = 0x25F;
 798                 } else if (channel == 38 || channel == 102 || channel == 118) {
 799                         if (0 /* FIXME */) {
 800                                 tone[0] = 0x20;
 801                                 noise[0] = 0x21F;
 802                         } else {
 803                                 tone[0] = 0;
 804                                 noise[0] = 0;
 805                         }
 806                 } else if (channel == 134) {
 807                         tone[0] = 0x20;
 808                         noise[0] = 0x21F;
 809                 } else if (channel == 151) {
 810                         tone[0] = 0x10;
 811                         noise[0] = 0x23F;
 812                 } else if (channel == 153 || channel == 161) {
 813                         tone[0] = 0x30;
 814                         noise[0] = 0x23F;
 815                 } else {
 816                         tone[0] = 0;
 817                         noise[0] = 0;
 818                 }
 819
 820                 if (!tone[0] && !noise[0])
 821                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 822                 else
 823                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 824         }
 825
 826         if (nphy->hang_avoid)
 827                 b43_nphy_stay_in_carrier_search(dev, 0);
 828 }
 829
 830 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 831 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 832 {
 833         struct b43_phy_n *nphy = dev->phy.n;
 834
 835         u8 i;
 836         s16 tmp;
 837         u16 data[4];
 838         s16 gain[2];
 839         u16 minmax[2];
 840         u16 lna_gain[4] = { -2, 10, 19, 25 };
 841
 842         if (nphy->hang_avoid)
 843                 b43_nphy_stay_in_carrier_search(dev, 1);
 844
 845         if (nphy->gain_boost) {
 846                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 847                         gain[0] = 6;
 848                         gain[1] = 6;
 849                 } else {
 850                         tmp = 40370 - 315 * dev->phy.channel;
 851                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 852                         tmp = 23242 - 224 * dev->phy.channel;
 853                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 854                 }
 855         } else {
 856                 gain[0] = 0;
 857                 gain[1] = 0;
 858         }
 859
 860         for (i = 0; i < 2; i++) {
 861                 if (nphy->elna_gain_config) {
 862                         data[0] = 19 + gain[i];
 863                         data[1] = 25 + gain[i];
 864                         data[2] = 25 + gain[i];
 865                         data[3] = 25 + gain[i];
 866                 } else {
 867                         data[0] = lna_gain[0] + gain[i];
 868                         data[1] = lna_gain[1] + gain[i];
 869                         data[2] = lna_gain[2] + gain[i];
 870                         data[3] = lna_gain[3] + gain[i];
 871                 }
 872                 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data);
 873
 874                 minmax[i] = 23 + gain[i];
 875         }
 876
 877         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 878                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 879         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 880                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 881
 882         if (nphy->hang_avoid)
 883                 b43_nphy_stay_in_carrier_search(dev, 0);
 884 }
 885
 886 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 887 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
 888 {
 889         struct b43_phy_n *nphy = dev->phy.n;
 890         u8 i, j;
 891         u8 code;
 892
 893         /* TODO: for PHY >= 3
 894         s8 *lna1_gain, *lna2_gain;
 895         u8 *gain_db, *gain_bits;
 896         u16 *rfseq_init;
 897         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 898         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 899         */
 900
 901         u8 rfseq_events[3] = { 6, 8, 7 };
 902         u8 rfseq_delays[3] = { 10, 30, 1 };
 903
 904         if (dev->phy.rev >= 3) {
 905                 /* TODO */
 906         } else {
 907                 /* Set Clip 2 detect */
 908                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 909                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 910                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 911                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 912
 913                 /* Set narrowband clip threshold */
 914                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 915                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 916
 917                 if (!dev->phy.is_40mhz) {
 918                         /* Set dwell lengths */
 919                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 920                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 921                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 922                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 923                 }
 924
 925                 /* Set wideband clip 2 threshold */
 926                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 927                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 928                                 21);
 929                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 930                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 931                                 21);
 932
 933                 if (!dev->phy.is_40mhz) {
 934                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 935                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 936                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 937                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 938                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 939                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 940                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 941                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 942                 }
 943
 944                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 945
 946                 if (nphy->gain_boost) {
 947                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 948                             dev->phy.is_40mhz)
 949                                 code = 4;
 950                         else
 951                                 code = 5;
 952                 } else {
 953                         code = dev->phy.is_40mhz ? 6 : 7;
 954                 }
 955
 956                 /* Set HPVGA2 index */
 957                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 958                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 959                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 960                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 961                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 962                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 963
 964                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 965                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 966                                         (code << 8 | 0x7C));
 967                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 968                                         (code << 8 | 0x7C));
 969
 970                 b43_nphy_adjust_lna_gain_table(dev);
 971
 972                 if (nphy->elna_gain_config) {
 973                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 974                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 975                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 976                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 977                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 978
 979                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 980                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 981                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 982                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 983                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 984
 985                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 986                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 987                                         (code << 8 | 0x74));
 988                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 989                                         (code << 8 | 0x74));
 990                 }
 991
 992                 if (dev->phy.rev == 2) {
 993                         for (i = 0; i < 4; i++) {
 994                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 995                                                 (0x0400 * i) + 0x0020);
 996                                 for (j = 0; j < 21; j++)
 997                                         b43_phy_write(dev,
 998                                                 B43_NPHY_TABLE_DATALO, 3 * j);
 999                         }
1000
1001                         b43_nphy_set_rf_sequence(dev, 5,
1002                                         rfseq_events, rfseq_delays, 3);
1003                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1004                                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1005                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1006
1007                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1008                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1009                                                 0xFF80, 4);
1010                 }
1011         }
1012 }
1013
1014 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1015 static void b43_nphy_workarounds(struct b43_wldev *dev)
1016 {
1017         struct ssb_bus *bus = dev->dev->bus;
1018         struct b43_phy *phy = &dev->phy;
1019         struct b43_phy_n *nphy = phy->n;
1020
1021         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1022         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1023
1024         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1025         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1026
1027         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1028                 b43_nphy_classifier(dev, 1, 0);
1029         else
1030                 b43_nphy_classifier(dev, 1, 1);
1031
1032         if (nphy->hang_avoid)
1033                 b43_nphy_stay_in_carrier_search(dev, 1);
1034
1035         b43_phy_set(dev, B43_NPHY_IQFLIP,
1036                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1037
1038         if (dev->phy.rev >= 3) {
1039                 /* TODO */
1040         } else {
1041                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1042                     nphy->band5g_pwrgain) {
1043                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1044                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1045                 } else {
1046                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1047                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1048                 }
1049
1050                 /* TODO: convert to b43_ntab_write? */
1051                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1052                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1053                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1054                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1055                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1056                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1057                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1058                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1059
1060                 if (dev->phy.rev < 2) {
1061                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1062                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1063                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1064                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1065                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1066                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1067                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1068                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1069                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1070                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1071                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1072                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1073                 }
1074
1075                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1076                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1077                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1078                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1079
1080                 if (bus->sprom.boardflags2_lo & 0x100 &&
1081                     bus->boardinfo.type == 0x8B) {
1082                         delays1[0] = 0x1;
1083                         delays1[5] = 0x14;
1084                 }
1085                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1086                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1087
1088                 b43_nphy_gain_ctrl_workarounds(dev);
1089
1090                 if (dev->phy.rev < 2) {
1091                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1092                                 b43_hf_write(dev, b43_hf_read(dev) |
1093                                                 B43_HF_MLADVW);
1094                 } else if (dev->phy.rev == 2) {
1095                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1096                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1097                 }
1098
1099                 if (dev->phy.rev < 2)
1100                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1101                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1102
1103                 /* Set phase track alpha and beta */
1104                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1105                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1106                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1107                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1108                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1109                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1110
1111                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1112                                 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1113                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1114                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1115                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1116
1117                 if (dev->phy.rev == 2)
1118                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1119                                         B43_NPHY_FINERX2_CGC_DECGC);
1120         }
1121
1122         if (nphy->hang_avoid)
1123                 b43_nphy_stay_in_carrier_search(dev, 0);
1124 }
1125
1126 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1127 static int b43_nphy_load_samples(struct b43_wldev *dev,
1128                                         struct b43_c32 *samples, u16 len) {
1129         struct b43_phy_n *nphy = dev->phy.n;
1130         u16 i;
1131         u32 *data;
1132
1133         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1134         if (!data) {
1135                 b43err(dev->wl, "allocation for samples loading failed\n");
1136                 return -ENOMEM;
1137         }
1138         if (nphy->hang_avoid)
1139                 b43_nphy_stay_in_carrier_search(dev, 1);
1140
1141         for (i = 0; i < len; i++) {
1142                 data[i] = (samples[i].i & 0x3FF << 10);
1143                 data[i] |= samples[i].q & 0x3FF;
1144         }
1145         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1146
1147         kfree(data);
1148         if (nphy->hang_avoid)
1149                 b43_nphy_stay_in_carrier_search(dev, 0);
1150         return 0;
1151 }
1152
1153 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1154 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1155                                         bool test)
1156 {
1157         int i;
1158         u16 bw, len, rot, angle;
1159         struct b43_c32 *samples;
1160
1161
1162         bw = (dev->phy.is_40mhz) ? 40 : 20;
1163         len = bw << 3;
1164
1165         if (test) {
1166                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1167                         bw = 82;
1168                 else
1169                         bw = 80;
1170
1171                 if (dev->phy.is_40mhz)
1172                         bw <<= 1;
1173
1174                 len = bw << 1;
1175         }
1176
1177         samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1178         if (!samples) {
1179                 b43err(dev->wl, "allocation for samples generation failed\n");
1180                 return 0;
1181         }
1182         rot = (((freq * 36) / bw) << 16) / 100;
1183         angle = 0;
1184
1185         for (i = 0; i < len; i++) {
1186                 samples[i] = b43_cordic(angle);
1187                 angle += rot;
1188                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1189                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1190         }
1191
1192         i = b43_nphy_load_samples(dev, samples, len);
1193         kfree(samples);
1194         return (i < 0) ? 0 : len;
1195 }
1196
1197 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1198 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1199                                         u16 wait, bool iqmode, bool dac_test)
1200 {
1201         struct b43_phy_n *nphy = dev->phy.n;
1202         int i;
1203         u16 seq_mode;
1204         u32 tmp;
1205
1206         if (nphy->hang_avoid)
1207                 b43_nphy_stay_in_carrier_search(dev, true);
1208
1209         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1210                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1211                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1212         }
1213
1214         if (!dev->phy.is_40mhz)
1215                 tmp = 0x6464;
1216         else
1217                 tmp = 0x4747;
1218         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1219
1220         if (nphy->hang_avoid)
1221                 b43_nphy_stay_in_carrier_search(dev, false);
1222
1223         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1224
1225         if (loops != 0xFFFF)
1226                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1227         else
1228                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1229
1230         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1231
1232         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1233
1234         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1235         if (iqmode) {
1236                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1237                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1238         } else {
1239                 if (dac_test)
1240                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1241                 else
1242                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1243         }
1244         for (i = 0; i < 100; i++) {
1245                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1246                         i = 0;
1247                         break;
1248                 }
1249                 udelay(10);
1250         }
1251         if (i)
1252                 b43err(dev->wl, "run samples timeout\n");
1253
1254         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1255 }
1256
1257 /*
1258  * Transmits a known value for LO calibration
1259  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1260  */
1261 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1262                                 bool iqmode, bool dac_test)
1263 {
1264         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1265         if (samp == 0)
1266                 return -1;
1267         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1268         return 0;
1269 }
1270
1271 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1272 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1273 {
1274         struct b43_phy_n *nphy = dev->phy.n;
1275         int i, j;
1276         u32 tmp;
1277         u32 cur_real, cur_imag, real_part, imag_part;
1278
1279         u16 buffer[7];
1280
1281         if (nphy->hang_avoid)
1282                 b43_nphy_stay_in_carrier_search(dev, true);
1283
1284         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1285
1286         for (i = 0; i < 2; i++) {
1287                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1288                         (buffer[i * 2 + 1] & 0x3FF);
1289                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1290                                 (((i + 26) << 10) | 320));
1291                 for (j = 0; j < 128; j++) {
1292                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1293                                         ((tmp >> 16) & 0xFFFF));
1294                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1295                                         (tmp & 0xFFFF));
1296                 }
1297         }
1298
1299         for (i = 0; i < 2; i++) {
1300                 tmp = buffer[5 + i];
1301                 real_part = (tmp >> 8) & 0xFF;
1302                 imag_part = (tmp & 0xFF);
1303                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1304                                 (((i + 26) << 10) | 448));
1305
1306                 if (dev->phy.rev >= 3) {
1307                         cur_real = real_part;
1308                         cur_imag = imag_part;
1309                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1310                 }
1311
1312                 for (j = 0; j < 128; j++) {
1313                         if (dev->phy.rev < 3) {
1314                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1315                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1316                                 tmp = ((cur_real & 0xFF) << 8) |
1317                                         (cur_imag & 0xFF);
1318                         }
1319                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1320                                         ((tmp >> 16) & 0xFFFF));
1321                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1322                                         (tmp & 0xFFFF));
1323                 }
1324         }
1325
1326         if (dev->phy.rev >= 3) {
1327                 b43_shm_write16(dev, B43_SHM_SHARED,
1328                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1329                 b43_shm_write16(dev, B43_SHM_SHARED,
1330                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1331         }
1332
1333         if (nphy->hang_avoid)
1334                 b43_nphy_stay_in_carrier_search(dev, false);
1335 }
1336
1337 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1338 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1339                                         u8 *events, u8 *delays, u8 length)
1340 {
1341         struct b43_phy_n *nphy = dev->phy.n;
1342         u8 i;
1343         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1344         u16 offset1 = cmd << 4;
1345         u16 offset2 = offset1 + 0x80;
1346
1347         if (nphy->hang_avoid)
1348                 b43_nphy_stay_in_carrier_search(dev, true);
1349
1350         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1351         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1352
1353         for (i = length; i < 16; i++) {
1354                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1355                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1356         }
1357
1358         if (nphy->hang_avoid)
1359                 b43_nphy_stay_in_carrier_search(dev, false);
1360 }
1361
1362 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1363 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1364                                        enum b43_nphy_rf_sequence seq)
1365 {
1366         static const u16 trigger[] = {
1367                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1368                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1369                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1370                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1371                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1372                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1373         };
1374         int i;
1375         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1376
1377         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1378
1379         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1380                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1381         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1382         for (i = 0; i < 200; i++) {
1383                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1384                         goto ok;
1385                 msleep(1);
1386         }
1387         b43err(dev->wl, "RF sequence status timeout\n");
1388 ok:
1389         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1390 }
1391
1392 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1393 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1394                                                 u16 value, u8 core, bool off)
1395 {
1396         int i;
1397         u8 index = fls(field);
1398         u8 addr, en_addr, val_addr;
1399         /* we expect only one bit set */
1400         B43_WARN_ON(field & (~(1 << (index - 1))));
1401
1402         if (dev->phy.rev >= 3) {
1403                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1404                 for (i = 0; i < 2; i++) {
1405                         if (index == 0 || index == 16) {
1406                                 b43err(dev->wl,
1407                                         "Unsupported RF Ctrl Override call\n");
1408                                 return;
1409                         }
1410
1411                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1412                         en_addr = B43_PHY_N((i == 0) ?
1413                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1414                         val_addr = B43_PHY_N((i == 0) ?
1415                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1416
1417                         if (off) {
1418                                 b43_phy_mask(dev, en_addr, ~(field));
1419                                 b43_phy_mask(dev, val_addr,
1420                                                 ~(rf_ctrl->val_mask));
1421                         } else {
1422                                 if (core == 0 || ((1 << core) & i) != 0) {
1423                                         b43_phy_set(dev, en_addr, field);
1424                                         b43_phy_maskset(dev, val_addr,
1425                                                 ~(rf_ctrl->val_mask),
1426                                                 (value << rf_ctrl->val_shift));
1427                                 }
1428                         }
1429                 }
1430         } else {
1431                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1432                 if (off) {
1433                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1434                         value = 0;
1435                 } else {
1436                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1437                 }
1438
1439                 for (i = 0; i < 2; i++) {
1440                         if (index <= 1 || index == 16) {
1441                                 b43err(dev->wl,
1442                                         "Unsupported RF Ctrl Override call\n");
1443                                 return;
1444                         }
1445
1446                         if (index == 2 || index == 10 ||
1447                             (index >= 13 && index <= 15)) {
1448                                 core = 1;
1449                         }
1450
1451                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1452                         addr = B43_PHY_N((i == 0) ?
1453                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1454
1455                         if ((core & (1 << i)) != 0)
1456                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1457                                                 (value << rf_ctrl->shift));
1458
1459                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1460                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1461                                         B43_NPHY_RFCTL_CMD_START);
1462                         udelay(1);
1463                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1464                 }
1465         }
1466 }
1467
1468 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1469 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1470                                                 u16 value, u8 core)
1471 {
1472         u8 i, j;
1473         u16 reg, tmp, val;
1474
1475         B43_WARN_ON(dev->phy.rev < 3);
1476         B43_WARN_ON(field > 4);
1477
1478         for (i = 0; i < 2; i++) {
1479                 if ((core == 1 && i == 1) || (core == 2 && !i))
1480                         continue;
1481
1482                 reg = (i == 0) ?
1483                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1484                 b43_phy_mask(dev, reg, 0xFBFF);
1485
1486                 switch (field) {
1487                 case 0:
1488                         b43_phy_write(dev, reg, 0);
1489                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1490                         break;
1491                 case 1:
1492                         if (!i) {
1493                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1494                                                 0xFC3F, (value << 6));
1495                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1496                                                 0xFFFE, 1);
1497                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1498                                                 B43_NPHY_RFCTL_CMD_START);
1499                                 for (j = 0; j < 100; j++) {
1500                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1501                                                 j = 0;
1502                                                 break;
1503                                         }
1504                                         udelay(10);
1505                                 }
1506                                 if (j)
1507                                         b43err(dev->wl,
1508                                                 "intc override timeout\n");
1509                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1510                                                 0xFFFE);
1511                         } else {
1512                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1513                                                 0xFC3F, (value << 6));
1514                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1515                                                 0xFFFE, 1);
1516                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1517                                                 B43_NPHY_RFCTL_CMD_RXTX);
1518                                 for (j = 0; j < 100; j++) {
1519                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1520                                                 j = 0;
1521                                                 break;
1522                                         }
1523                                         udelay(10);
1524                                 }
1525                                 if (j)
1526                                         b43err(dev->wl,
1527                                                 "intc override timeout\n");
1528                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1529                                                 0xFFFE);
1530                         }
1531                         break;
1532                 case 2:
1533                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1534                                 tmp = 0x0020;
1535                                 val = value << 5;
1536                         } else {
1537                                 tmp = 0x0010;
1538                                 val = value << 4;
1539                         }
1540                         b43_phy_maskset(dev, reg, ~tmp, val);
1541                         break;
1542                 case 3:
1543                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1544                                 tmp = 0x0001;
1545                                 val = value;
1546                         } else {
1547                                 tmp = 0x0004;
1548                                 val = value << 2;
1549                         }
1550                         b43_phy_maskset(dev, reg, ~tmp, val);
1551                         break;
1552                 case 4:
1553                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1554                                 tmp = 0x0002;
1555                                 val = value << 1;
1556                         } else {
1557                                 tmp = 0x0008;
1558                                 val = value << 3;
1559                         }
1560                         b43_phy_maskset(dev, reg, ~tmp, val);
1561                         break;
1562                 }
1563         }
1564 }
1565
1566 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1567 {
1568         unsigned int i;
1569         u16 val;
1570
1571         val = 0x1E1F;
1572         for (i = 0; i < 14; i++) {
1573                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1574                 val -= 0x202;
1575         }
1576         val = 0x3E3F;
1577         for (i = 0; i < 16; i++) {
1578                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1579                 val -= 0x202;
1580         }
1581         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1582 }
1583
1584 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1585 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1586                                        s8 offset, u8 core, u8 rail, u8 type)
1587 {
1588         u16 tmp;
1589         bool core1or5 = (core == 1) || (core == 5);
1590         bool core2or5 = (core == 2) || (core == 5);
1591
1592         offset = clamp_val(offset, -32, 31);
1593         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1594
1595         if (core1or5 && (rail == 0) && (type == 2))
1596                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1597         if (core1or5 && (rail == 1) && (type == 2))
1598                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1599         if (core2or5 && (rail == 0) && (type == 2))
1600                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1601         if (core2or5 && (rail == 1) && (type == 2))
1602                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1603         if (core1or5 && (rail == 0) && (type == 0))
1604                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1605         if (core1or5 && (rail == 1) && (type == 0))
1606                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1607         if (core2or5 && (rail == 0) && (type == 0))
1608                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1609         if (core2or5 && (rail == 1) && (type == 0))
1610                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1611         if (core1or5 && (rail == 0) && (type == 1))
1612                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1613         if (core1or5 && (rail == 1) && (type == 1))
1614                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1615         if (core2or5 && (rail == 0) && (type == 1))
1616                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1617         if (core2or5 && (rail == 1) && (type == 1))
1618                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1619         if (core1or5 && (rail == 0) && (type == 6))
1620                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1621         if (core1or5 && (rail == 1) && (type == 6))
1622                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1623         if (core2or5 && (rail == 0) && (type == 6))
1624                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1625         if (core2or5 && (rail == 1) && (type == 6))
1626                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1627         if (core1or5 && (rail == 0) && (type == 3))
1628                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1629         if (core1or5 && (rail == 1) && (type == 3))
1630                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1631         if (core2or5 && (rail == 0) && (type == 3))
1632                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1633         if (core2or5 && (rail == 1) && (type == 3))
1634                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1635         if (core1or5 && (type == 4))
1636                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1637         if (core2or5 && (type == 4))
1638                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1639         if (core1or5 && (type == 5))
1640                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1641         if (core2or5 && (type == 5))
1642                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1643 }
1644
1645 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1646 {
1647         u16 val;
1648
1649         if (type < 3)
1650                 val = 0;
1651         else if (type == 6)
1652                 val = 1;
1653         else if (type == 3)
1654                 val = 2;
1655         else
1656                 val = 3;
1657
1658         val = (val << 12) | (val << 14);
1659         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1660         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1661
1662         if (type < 3) {
1663                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1664                                 (type + 1) << 4);
1665                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1666                                 (type + 1) << 4);
1667         }
1668
1669         /* TODO use some definitions */
1670         if (code == 0) {
1671                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1672                 if (type < 3) {
1673                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1674                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1675                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1676                         udelay(20);
1677                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1678                 }
1679         } else {
1680                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1681                                 0x3000);
1682                 if (type < 3) {
1683                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1684                                         0xFEC7, 0x0180);
1685                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1686                                         0xEFDC, (code << 1 | 0x1021));
1687                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1688                         udelay(20);
1689                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1690                 }
1691         }
1692 }
1693
1694 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1695 {
1696         struct b43_phy_n *nphy = dev->phy.n;
1697         u8 i;
1698         u16 reg, val;
1699
1700         if (code == 0) {
1701                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1702                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1703                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1704                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1705                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1706                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1707                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1708                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1709         } else {
1710                 for (i = 0; i < 2; i++) {
1711                         if ((code == 1 && i == 1) || (code == 2 && !i))
1712                                 continue;
1713
1714                         reg = (i == 0) ?
1715                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1716                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1717
1718                         if (type < 3) {
1719                                 reg = (i == 0) ?
1720                                         B43_NPHY_AFECTL_C1 :
1721                                         B43_NPHY_AFECTL_C2;
1722                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1723
1724                                 reg = (i == 0) ?
1725                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1726                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1727                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1728
1729                                 if (type == 0)
1730                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1731                                 else if (type == 1)
1732                                         val = 16;
1733                                 else
1734                                         val = 32;
1735                                 b43_phy_set(dev, reg, val);
1736
1737                                 reg = (i == 0) ?
1738                                         B43_NPHY_TXF_40CO_B1S0 :
1739                                         B43_NPHY_TXF_40CO_B32S1;
1740                                 b43_phy_set(dev, reg, 0x0020);
1741                         } else {
1742                                 if (type == 6)
1743                                         val = 0x0100;
1744                                 else if (type == 3)
1745                                         val = 0x0200;
1746                                 else
1747                                         val = 0x0300;
1748
1749                                 reg = (i == 0) ?
1750                                         B43_NPHY_AFECTL_C1 :
1751                                         B43_NPHY_AFECTL_C2;
1752
1753                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1754                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1755
1756                                 if (type != 3 && type != 6) {
1757                                         enum ieee80211_band band =
1758                                                 b43_current_band(dev->wl);
1759
1760                                         if ((nphy->ipa2g_on &&
1761                                                 band == IEEE80211_BAND_2GHZ) ||
1762                                                 (nphy->ipa5g_on &&
1763                                                 band == IEEE80211_BAND_5GHZ))
1764                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1765                                         else
1766                                                 val = 0x11;
1767                                         reg = (i == 0) ? 0x2000 : 0x3000;
1768                                         reg |= B2055_PADDRV;
1769                                         b43_radio_write16(dev, reg, val);
1770
1771                                         reg = (i == 0) ?
1772                                                 B43_NPHY_AFECTL_OVER1 :
1773                                                 B43_NPHY_AFECTL_OVER;
1774                                         b43_phy_set(dev, reg, 0x0200);
1775                                 }
1776                         }
1777                 }
1778         }
1779 }
1780
1781 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1782 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1783 {
1784         if (dev->phy.rev >= 3)
1785                 b43_nphy_rev3_rssi_select(dev, code, type);
1786         else
1787                 b43_nphy_rev2_rssi_select(dev, code, type);
1788 }
1789
1790 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1791 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1792 {
1793         int i;
1794         for (i = 0; i < 2; i++) {
1795                 if (type == 2) {
1796                         if (i == 0) {
1797                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1798                                                   0xFC, buf[0]);
1799                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1800                                                   0xFC, buf[1]);
1801                         } else {
1802                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1803                                                   0xFC, buf[2 * i]);
1804                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1805                                                   0xFC, buf[2 * i + 1]);
1806                         }
1807                 } else {
1808                         if (i == 0)
1809                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1810                                                   0xF3, buf[0] << 2);
1811                         else
1812                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1813                                                   0xF3, buf[2 * i + 1] << 2);
1814                 }
1815         }
1816 }
1817
1818 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1819 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1820                                 u8 nsamp)
1821 {
1822         int i;
1823         int out;
1824         u16 save_regs_phy[9];
1825         u16 s[2];
1826
1827         if (dev->phy.rev >= 3) {
1828                 save_regs_phy[0] = b43_phy_read(dev,
1829                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1830                 save_regs_phy[1] = b43_phy_read(dev,
1831                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1832                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1833                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1834                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1835                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1836                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1837                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1838         }
1839
1840         b43_nphy_rssi_select(dev, 5, type);
1841
1842         if (dev->phy.rev < 2) {
1843                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1844                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1845         }
1846
1847         for (i = 0; i < 4; i++)
1848                 buf[i] = 0;
1849
1850         for (i = 0; i < nsamp; i++) {
1851                 if (dev->phy.rev < 2) {
1852                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1853                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1854                 } else {
1855                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1856                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1857                 }
1858
1859                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1860                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1861                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1862                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1863         }
1864         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1865                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1866
1867         if (dev->phy.rev < 2)
1868                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1869
1870         if (dev->phy.rev >= 3) {
1871                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1872                                 save_regs_phy[0]);
1873                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1874                                 save_regs_phy[1]);
1875                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1876                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1877                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1878                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1879                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1880                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1881         }
1882
1883         return out;
1884 }
1885
1886 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1887 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1888 {
1889         int i, j;
1890         u8 state[4];
1891         u8 code, val;
1892         u16 class, override;
1893         u8 regs_save_radio[2];
1894         u16 regs_save_phy[2];
1895         s8 offset[4];
1896
1897         u16 clip_state[2];
1898         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1899         s32 results_min[4] = { };
1900         u8 vcm_final[4] = { };
1901         s32 results[4][4] = { };
1902         s32 miniq[4][2] = { };
1903
1904         if (type == 2) {
1905                 code = 0;
1906                 val = 6;
1907         } else if (type < 2) {
1908                 code = 25;
1909                 val = 4;
1910         } else {
1911                 B43_WARN_ON(1);
1912                 return;
1913         }
1914
1915         class = b43_nphy_classifier(dev, 0, 0);
1916         b43_nphy_classifier(dev, 7, 4);
1917         b43_nphy_read_clip_detection(dev, clip_state);
1918         b43_nphy_write_clip_detection(dev, clip_off);
1919
1920         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1921                 override = 0x140;
1922         else
1923                 override = 0x110;
1924
1925         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1926         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1927         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1928         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1929
1930         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1931         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1932         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1933         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1934
1935         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1936         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1937         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1938         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1939         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1940         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1941
1942         b43_nphy_rssi_select(dev, 5, type);
1943         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1944         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1945
1946         for (i = 0; i < 4; i++) {
1947                 u8 tmp[4];
1948                 for (j = 0; j < 4; j++)
1949                         tmp[j] = i;
1950                 if (type != 1)
1951                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1952                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1953                 if (type < 2)
1954                         for (j = 0; j < 2; j++)
1955                                 miniq[i][j] = min(results[i][2 * j],
1956                                                 results[i][2 * j + 1]);
1957         }
1958
1959         for (i = 0; i < 4; i++) {
1960                 s32 mind = 40;
1961                 u8 minvcm = 0;
1962                 s32 minpoll = 249;
1963                 s32 curr;
1964                 for (j = 0; j < 4; j++) {
1965                         if (type == 2)
1966                                 curr = abs(results[j][i]);
1967                         else
1968                                 curr = abs(miniq[j][i / 2] - code * 8);
1969
1970                         if (curr < mind) {
1971                                 mind = curr;
1972                                 minvcm = j;
1973                         }
1974
1975                         if (results[j][i] < minpoll)
1976                                 minpoll = results[j][i];
1977                 }
1978                 results_min[i] = minpoll;
1979                 vcm_final[i] = minvcm;
1980         }
1981
1982         if (type != 1)
1983                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1984
1985         for (i = 0; i < 4; i++) {
1986                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1987
1988                 if (offset[i] < 0)
1989                         offset[i] = -((abs(offset[i]) + 4) / 8);
1990                 else
1991                         offset[i] = (offset[i] + 4) / 8;
1992
1993                 if (results_min[i] == 248)
1994                         offset[i] = code - 32;
1995
1996                 if (i % 2 == 0)
1997                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1998                                                         type);
1999                 else
2000                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
2001                                                         type);
2002         }
2003
2004         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2005         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
2006
2007         switch (state[2]) {
2008         case 1:
2009                 b43_nphy_rssi_select(dev, 1, 2);
2010                 break;
2011         case 4:
2012                 b43_nphy_rssi_select(dev, 1, 0);
2013                 break;
2014         case 2:
2015                 b43_nphy_rssi_select(dev, 1, 1);
2016                 break;
2017         default:
2018                 b43_nphy_rssi_select(dev, 1, 1);
2019                 break;
2020         }
2021
2022         switch (state[3]) {
2023         case 1:
2024                 b43_nphy_rssi_select(dev, 2, 2);
2025                 break;
2026         case 4:
2027                 b43_nphy_rssi_select(dev, 2, 0);
2028                 break;
2029         default:
2030                 b43_nphy_rssi_select(dev, 2, 1);
2031                 break;
2032         }
2033
2034         b43_nphy_rssi_select(dev, 0, type);
2035
2036         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2037         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2038         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2039         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2040
2041         b43_nphy_classifier(dev, 7, class);
2042         b43_nphy_write_clip_detection(dev, clip_state);
2043 }
2044
2045 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2046 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2047 {
2048         /* TODO */
2049 }
2050
2051 /*
2052  * RSSI Calibration
2053  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2054  */
2055 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2056 {
2057         if (dev->phy.rev >= 3) {
2058                 b43_nphy_rev3_rssi_cal(dev);
2059         } else {
2060                 b43_nphy_rev2_rssi_cal(dev, 2);
2061                 b43_nphy_rev2_rssi_cal(dev, 0);
2062                 b43_nphy_rev2_rssi_cal(dev, 1);
2063         }
2064 }
2065
2066 /*
2067  * Restore RSSI Calibration
2068  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2069  */
2070 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2071 {
2072         struct b43_phy_n *nphy = dev->phy.n;
2073
2074         u16 *rssical_radio_regs = NULL;
2075         u16 *rssical_phy_regs = NULL;
2076
2077         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2078                 if (!nphy->rssical_chanspec_2G.center_freq)
2079                         return;
2080                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2081                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2082         } else {
2083                 if (!nphy->rssical_chanspec_5G.center_freq)
2084                         return;
2085                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2086                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2087         }
2088
2089         /* TODO use some definitions */
2090         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2091         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2092
2093         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2094         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2095         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2096         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2097
2098         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2099         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2100         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2101         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2102
2103         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2104         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2105         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2106         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2107 }
2108
2109 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2110 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2111 {
2112         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2113                 if (dev->phy.rev >= 6) {
2114                         /* TODO If the chip is 47162
2115                                 return txpwrctrl_tx_gain_ipa_rev5 */
2116                         return txpwrctrl_tx_gain_ipa_rev6;
2117                 } else if (dev->phy.rev >= 5) {
2118                         return txpwrctrl_tx_gain_ipa_rev5;
2119                 } else {
2120                         return txpwrctrl_tx_gain_ipa;
2121                 }
2122         } else {
2123                 return txpwrctrl_tx_gain_ipa_5g;
2124         }
2125 }
2126
2127 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2128 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2129 {
2130         struct b43_phy_n *nphy = dev->phy.n;
2131         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2132         u16 tmp;
2133         u8 offset, i;
2134
2135         if (dev->phy.rev >= 3) {
2136             for (i = 0; i < 2; i++) {
2137                 tmp = (i == 0) ? 0x2000 : 0x3000;
2138                 offset = i * 11;
2139
2140                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2141                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2142                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2143                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2144                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2145                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2146                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2147                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2148                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2149                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2150                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2151
2152                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2153                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2154                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2155                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2156                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2157                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2158                         if (nphy->ipa5g_on) {
2159                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2160                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2161                         } else {
2162                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2163                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2164                         }
2165                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2166                 } else {
2167                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2168                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2169                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2170                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2171                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2172                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2173                         if (nphy->ipa2g_on) {
2174                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2175                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2176                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2177                         } else {
2178                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2179                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2180                         }
2181                 }
2182                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2183                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2184                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2185             }
2186         } else {
2187                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2188                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2189
2190                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2191                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2192
2193                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2194                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2195
2196                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2197                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2198
2199                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2200                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2201
2202                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2203                     B43_NPHY_BANDCTL_5GHZ)) {
2204                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2205                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2206                 } else {
2207                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2208                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2209                 }
2210
2211                 if (dev->phy.rev < 2) {
2212                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2213                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2214                 } else {
2215                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2216                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2217                 }
2218         }
2219 }
2220
2221 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2222 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2223                                         struct nphy_txgains target,
2224                                         struct nphy_iqcal_params *params)
2225 {
2226         int i, j, indx;
2227         u16 gain;
2228
2229         if (dev->phy.rev >= 3) {
2230                 params->txgm = target.txgm[core];
2231                 params->pga = target.pga[core];
2232                 params->pad = target.pad[core];
2233                 params->ipa = target.ipa[core];
2234                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2235                                         (params->pad << 4) | (params->ipa);
2236                 for (j = 0; j < 5; j++)
2237                         params->ncorr[j] = 0x79;
2238         } else {
2239                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2240                         (target.txgm[core] << 8);
2241
2242                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2243                         1 : 0;
2244                 for (i = 0; i < 9; i++)
2245                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2246                                 break;
2247                 i = min(i, 8);
2248
2249                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2250                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2251                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2252                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2253                                         (params->pad << 2);
2254                 for (j = 0; j < 4; j++)
2255                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2256         }
2257 }
2258
2259 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2260 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2261 {
2262         struct b43_phy_n *nphy = dev->phy.n;
2263         int i;
2264         u16 scale, entry;
2265
2266         u16 tmp = nphy->txcal_bbmult;
2267         if (core == 0)
2268                 tmp >>= 8;
2269         tmp &= 0xff;
2270
2271         for (i = 0; i < 18; i++) {
2272                 scale = (ladder_lo[i].percent * tmp) / 100;
2273                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2274                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2275
2276                 scale = (ladder_iq[i].percent * tmp) / 100;
2277                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2278                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2279         }
2280 }
2281
2282 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2283 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2284 {
2285         int i;
2286         for (i = 0; i < 15; i++)
2287                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2288                                 tbl_tx_filter_coef_rev4[2][i]);
2289 }
2290
2291 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2292 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2293 {
2294         int i, j;
2295         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2296         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2297
2298         for (i = 0; i < 3; i++)
2299                 for (j = 0; j < 15; j++)
2300                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2301                                         tbl_tx_filter_coef_rev4[i][j]);
2302
2303         if (dev->phy.is_40mhz) {
2304                 for (j = 0; j < 15; j++)
2305                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2306                                         tbl_tx_filter_coef_rev4[3][j]);
2307         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2308                 for (j = 0; j < 15; j++)
2309                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2310                                         tbl_tx_filter_coef_rev4[5][j]);
2311         }
2312
2313         if (dev->phy.channel == 14)
2314                 for (j = 0; j < 15; j++)
2315                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2316                                         tbl_tx_filter_coef_rev4[6][j]);
2317 }
2318
2319 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2320 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2321 {
2322         struct b43_phy_n *nphy = dev->phy.n;
2323
2324         u16 curr_gain[2];
2325         struct nphy_txgains target;
2326         const u32 *table = NULL;
2327
2328         if (nphy->txpwrctrl == 0) {
2329                 int i;
2330
2331                 if (nphy->hang_avoid)
2332                         b43_nphy_stay_in_carrier_search(dev, true);
2333                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2334                 if (nphy->hang_avoid)
2335                         b43_nphy_stay_in_carrier_search(dev, false);
2336
2337                 for (i = 0; i < 2; ++i) {
2338                         if (dev->phy.rev >= 3) {
2339                                 target.ipa[i] = curr_gain[i] & 0x000F;
2340                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2341                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2342                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2343                         } else {
2344                                 target.ipa[i] = curr_gain[i] & 0x0003;
2345                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2346                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2347                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2348                         }
2349                 }
2350         } else {
2351                 int i;
2352                 u16 index[2];
2353                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2354                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2355                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2356                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2357                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2358                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2359
2360                 for (i = 0; i < 2; ++i) {
2361                         if (dev->phy.rev >= 3) {
2362                                 enum ieee80211_band band =
2363                                         b43_current_band(dev->wl);
2364
2365                                 if ((nphy->ipa2g_on &&
2366                                      band == IEEE80211_BAND_2GHZ) ||
2367                                     (nphy->ipa5g_on &&
2368                                      band == IEEE80211_BAND_5GHZ)) {
2369                                         table = b43_nphy_get_ipa_gain_table(dev);
2370                                 } else {
2371                                         if (band == IEEE80211_BAND_5GHZ) {
2372                                                 if (dev->phy.rev == 3)
2373                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2374                                                 else if (dev->phy.rev == 4)
2375                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2376                                                 else
2377                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2378                                         } else {
2379                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2380                                         }
2381                                 }
2382
2383                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2384                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2385                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2386                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2387                         } else {
2388                                 table = b43_ntab_tx_gain_rev0_1_2;
2389
2390                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2391                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2392                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2393                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2394                         }
2395                 }
2396         }
2397
2398         return target;
2399 }
2400
2401 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2402 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2403 {
2404         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2405
2406         if (dev->phy.rev >= 3) {
2407                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2408                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2409                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2410                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2411                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2412                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2413                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2414                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2415                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2416                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2417                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2418                 b43_nphy_reset_cca(dev);
2419         } else {
2420                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2421                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2422                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2423                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2424                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2425                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2426                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2427         }
2428 }
2429
2430 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2431 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2432 {
2433         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2434         u16 tmp;
2435
2436         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2437         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2438         if (dev->phy.rev >= 3) {
2439                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2440                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2441
2442                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2443                 regs[2] = tmp;
2444                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2445
2446                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2447                 regs[3] = tmp;
2448                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2449
2450                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2451                 b43_phy_mask(dev, B43_NPHY_BBCFG,
2452                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2453
2454                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2455                 regs[5] = tmp;
2456                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2457
2458                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2459                 regs[6] = tmp;
2460                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2461                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2462                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2463
2464                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2465                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2466                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2467
2468                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2469                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2470                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2471                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2472         } else {
2473                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2474                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2475                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2476                 regs[2] = tmp;
2477                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2478                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2479                 regs[3] = tmp;
2480                 tmp |= 0x2000;
2481                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2482                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2483                 regs[4] = tmp;
2484                 tmp |= 0x2000;
2485                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2486                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2487                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2488                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2489                         tmp = 0x0180;
2490                 else
2491                         tmp = 0x0120;
2492                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2493                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2494         }
2495 }
2496
2497 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2498 static void b43_nphy_save_cal(struct b43_wldev *dev)
2499 {
2500         struct b43_phy_n *nphy = dev->phy.n;
2501
2502         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2503         u16 *txcal_radio_regs = NULL;
2504         struct b43_chanspec *iqcal_chanspec;
2505         u16 *table = NULL;
2506
2507         if (nphy->hang_avoid)
2508                 b43_nphy_stay_in_carrier_search(dev, 1);
2509
2510         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2511                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2512                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2513                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2514                 table = nphy->cal_cache.txcal_coeffs_2G;
2515         } else {
2516                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2517                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2518                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2519                 table = nphy->cal_cache.txcal_coeffs_5G;
2520         }
2521
2522         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2523         /* TODO use some definitions */
2524         if (dev->phy.rev >= 3) {
2525                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2526                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2527                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2528                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2529                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2530                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2531                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2532                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2533         } else {
2534                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2535                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2536                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2537                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2538         }
2539         iqcal_chanspec->center_freq = dev->phy.channel_freq;
2540         iqcal_chanspec->channel_type = dev->phy.channel_type;
2541         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2542
2543         if (nphy->hang_avoid)
2544                 b43_nphy_stay_in_carrier_search(dev, 0);
2545 }
2546
2547 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2548 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2549 {
2550         struct b43_phy_n *nphy = dev->phy.n;
2551
2552         u16 coef[4];
2553         u16 *loft = NULL;
2554         u16 *table = NULL;
2555
2556         int i;
2557         u16 *txcal_radio_regs = NULL;
2558         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2559
2560         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2561                 if (!nphy->iqcal_chanspec_2G.center_freq)
2562                         return;
2563                 table = nphy->cal_cache.txcal_coeffs_2G;
2564                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2565         } else {
2566                 if (!nphy->iqcal_chanspec_5G.center_freq)
2567                         return;
2568                 table = nphy->cal_cache.txcal_coeffs_5G;
2569                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2570         }
2571
2572         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2573
2574         for (i = 0; i < 4; i++) {
2575                 if (dev->phy.rev >= 3)
2576                         table[i] = coef[i];
2577                 else
2578                         coef[i] = 0;
2579         }
2580
2581         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2582         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2583         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2584
2585         if (dev->phy.rev < 2)
2586                 b43_nphy_tx_iq_workaround(dev);
2587
2588         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2589                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2590                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2591         } else {
2592                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2593                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2594         }
2595
2596         /* TODO use some definitions */
2597         if (dev->phy.rev >= 3) {
2598                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2599                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2600                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2601                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2602                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2603                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2604                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2605                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2606         } else {
2607                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2608                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2609                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2610                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2611         }
2612         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2613 }
2614
2615 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2616 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2617                                 struct nphy_txgains target,
2618                                 bool full, bool mphase)
2619 {
2620         struct b43_phy_n *nphy = dev->phy.n;
2621         int i;
2622         int error = 0;
2623         int freq;
2624         bool avoid = false;
2625         u8 length;
2626         u16 tmp, core, type, count, max, numb, last, cmd;
2627         const u16 *table;
2628         bool phy6or5x;
2629
2630         u16 buffer[11];
2631         u16 diq_start = 0;
2632         u16 save[2];
2633         u16 gain[2];
2634         struct nphy_iqcal_params params[2];
2635         bool updated[2] = { };
2636
2637         b43_nphy_stay_in_carrier_search(dev, true);
2638
2639         if (dev->phy.rev >= 4) {
2640                 avoid = nphy->hang_avoid;
2641                 nphy->hang_avoid = 0;
2642         }
2643
2644         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2645
2646         for (i = 0; i < 2; i++) {
2647                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2648                 gain[i] = params[i].cal_gain;
2649         }
2650
2651         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2652
2653         b43_nphy_tx_cal_radio_setup(dev);
2654         b43_nphy_tx_cal_phy_setup(dev);
2655
2656         phy6or5x = dev->phy.rev >= 6 ||
2657                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2658                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2659         if (phy6or5x) {
2660                 if (dev->phy.is_40mhz) {
2661                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2662                                         tbl_tx_iqlo_cal_loft_ladder_40);
2663                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2664                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2665                 } else {
2666                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2667                                         tbl_tx_iqlo_cal_loft_ladder_20);
2668                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2669                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2670                 }
2671         }
2672
2673         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2674
2675         if (!dev->phy.is_40mhz)
2676                 freq = 2500;
2677         else
2678                 freq = 5000;
2679
2680         if (nphy->mphase_cal_phase_id > 2)
2681                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2682                                         0xFFFF, 0, true, false);
2683         else
2684                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2685
2686         if (error == 0) {
2687                 if (nphy->mphase_cal_phase_id > 2) {
2688                         table = nphy->mphase_txcal_bestcoeffs;
2689                         length = 11;
2690                         if (dev->phy.rev < 3)
2691                                 length -= 2;
2692                 } else {
2693                         if (!full && nphy->txiqlocal_coeffsvalid) {
2694                                 table = nphy->txiqlocal_bestc;
2695                                 length = 11;
2696                                 if (dev->phy.rev < 3)
2697                                         length -= 2;
2698                         } else {
2699                                 full = true;
2700                                 if (dev->phy.rev >= 3) {
2701                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2702                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2703                                 } else {
2704                                         table = tbl_tx_iqlo_cal_startcoefs;
2705                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2706                                 }
2707                         }
2708                 }
2709
2710                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2711
2712                 if (full) {
2713                         if (dev->phy.rev >= 3)
2714                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2715                         else
2716                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2717                 } else {
2718                         if (dev->phy.rev >= 3)
2719                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2720                         else
2721                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2722                 }
2723
2724                 if (mphase) {
2725                         count = nphy->mphase_txcal_cmdidx;
2726                         numb = min(max,
2727                                 (u16)(count + nphy->mphase_txcal_numcmds));
2728                 } else {
2729                         count = 0;
2730                         numb = max;
2731                 }
2732
2733                 for (; count < numb; count++) {
2734                         if (full) {
2735                                 if (dev->phy.rev >= 3)
2736                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2737                                 else
2738                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2739                         } else {
2740                                 if (dev->phy.rev >= 3)
2741                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2742                                 else
2743                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2744                         }
2745
2746                         core = (cmd & 0x3000) >> 12;
2747                         type = (cmd & 0x0F00) >> 8;
2748
2749                         if (phy6or5x && updated[core] == 0) {
2750                                 b43_nphy_update_tx_cal_ladder(dev, core);
2751                                 updated[core] = 1;
2752                         }
2753
2754                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2755                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2756
2757                         if (type == 1 || type == 3 || type == 4) {
2758                                 buffer[0] = b43_ntab_read(dev,
2759                                                 B43_NTAB16(15, 69 + core));
2760                                 diq_start = buffer[0];
2761                                 buffer[0] = 0;
2762                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2763                                                 0);
2764                         }
2765
2766                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2767                         for (i = 0; i < 2000; i++) {
2768                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2769                                 if (tmp & 0xC000)
2770                                         break;
2771                                 udelay(10);
2772                         }
2773
2774                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2775                                                 buffer);
2776                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2777                                                 buffer);
2778
2779                         if (type == 1 || type == 3 || type == 4)
2780                                 buffer[0] = diq_start;
2781                 }
2782
2783                 if (mphase)
2784                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2785
2786                 last = (dev->phy.rev < 3) ? 6 : 7;
2787
2788                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2789                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2790                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2791                         if (dev->phy.rev < 3) {
2792                                 buffer[0] = 0;
2793                                 buffer[1] = 0;
2794                                 buffer[2] = 0;
2795                                 buffer[3] = 0;
2796                         }
2797                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2798                                                 buffer);
2799                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2800                                                 buffer);
2801                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2802                                                 buffer);
2803                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2804                                                 buffer);
2805                         length = 11;
2806                         if (dev->phy.rev < 3)
2807                                 length -= 2;
2808                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2809                                                 nphy->txiqlocal_bestc);
2810                         nphy->txiqlocal_coeffsvalid = true;
2811                         nphy->txiqlocal_chanspec.center_freq =
2812                                                         dev->phy.channel_freq;
2813                         nphy->txiqlocal_chanspec.channel_type =
2814                                                         dev->phy.channel_type;
2815                 } else {
2816                         length = 11;
2817                         if (dev->phy.rev < 3)
2818                                 length -= 2;
2819                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2820                                                 nphy->mphase_txcal_bestcoeffs);
2821                 }
2822
2823                 b43_nphy_stop_playback(dev);
2824                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2825         }
2826
2827         b43_nphy_tx_cal_phy_cleanup(dev);
2828         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2829
2830         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2831                 b43_nphy_tx_iq_workaround(dev);
2832
2833         if (dev->phy.rev >= 4)
2834                 nphy->hang_avoid = avoid;
2835
2836         b43_nphy_stay_in_carrier_search(dev, false);
2837
2838         return error;
2839 }
2840
2841 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2842 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2843 {
2844         struct b43_phy_n *nphy = dev->phy.n;
2845         u8 i;
2846         u16 buffer[7];
2847         bool equal = true;
2848
2849         if (!nphy->txiqlocal_coeffsvalid ||
2850             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
2851             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
2852                 return;
2853
2854         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2855         for (i = 0; i < 4; i++) {
2856                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2857                         equal = false;
2858                         break;
2859                 }
2860         }
2861
2862         if (!equal) {
2863                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2864                                         nphy->txiqlocal_bestc);
2865                 for (i = 0; i < 4; i++)
2866                         buffer[i] = 0;
2867                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2868                                         buffer);
2869                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2870                                         &nphy->txiqlocal_bestc[5]);
2871                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2872                                         &nphy->txiqlocal_bestc[5]);
2873         }
2874 }
2875
2876 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2877 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2878                         struct nphy_txgains target, u8 type, bool debug)
2879 {
2880         struct b43_phy_n *nphy = dev->phy.n;
2881         int i, j, index;
2882         u8 rfctl[2];
2883         u8 afectl_core;
2884         u16 tmp[6];
2885         u16 cur_hpf1, cur_hpf2, cur_lna;
2886         u32 real, imag;
2887         enum ieee80211_band band;
2888
2889         u8 use;
2890         u16 cur_hpf;
2891         u16 lna[3] = { 3, 3, 1 };
2892         u16 hpf1[3] = { 7, 2, 0 };
2893         u16 hpf2[3] = { 2, 0, 0 };
2894         u32 power[3] = { };
2895         u16 gain_save[2];
2896         u16 cal_gain[2];
2897         struct nphy_iqcal_params cal_params[2];
2898         struct nphy_iq_est est;
2899         int ret = 0;
2900         bool playtone = true;
2901         int desired = 13;
2902
2903         b43_nphy_stay_in_carrier_search(dev, 1);
2904
2905         if (dev->phy.rev < 2)
2906                 b43_nphy_reapply_tx_cal_coeffs(dev);
2907         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2908         for (i = 0; i < 2; i++) {
2909                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2910                 cal_gain[i] = cal_params[i].cal_gain;
2911         }
2912         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2913
2914         for (i = 0; i < 2; i++) {
2915                 if (i == 0) {
2916                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2917                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2918                         afectl_core = B43_NPHY_AFECTL_C1;
2919                 } else {
2920                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2921                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2922                         afectl_core = B43_NPHY_AFECTL_C2;
2923                 }
2924
2925                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2926                 tmp[2] = b43_phy_read(dev, afectl_core);
2927                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2928                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2929                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2930
2931                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2932                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
2933                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2934                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2935                                 (1 - i));
2936                 b43_phy_set(dev, afectl_core, 0x0006);
2937                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2938
2939                 band = b43_current_band(dev->wl);
2940
2941                 if (nphy->rxcalparams & 0xFF000000) {
2942                         if (band == IEEE80211_BAND_5GHZ)
2943                                 b43_phy_write(dev, rfctl[0], 0x140);
2944                         else
2945                                 b43_phy_write(dev, rfctl[0], 0x110);
2946                 } else {
2947                         if (band == IEEE80211_BAND_5GHZ)
2948                                 b43_phy_write(dev, rfctl[0], 0x180);
2949                         else
2950                                 b43_phy_write(dev, rfctl[0], 0x120);
2951                 }
2952
2953                 if (band == IEEE80211_BAND_5GHZ)
2954                         b43_phy_write(dev, rfctl[1], 0x148);
2955                 else
2956                         b43_phy_write(dev, rfctl[1], 0x114);
2957
2958                 if (nphy->rxcalparams & 0x10000) {
2959                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2960                                         (i + 1));
2961                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2962                                         (2 - i));
2963                 }
2964
2965                 for (j = 0; i < 4; j++) {
2966                         if (j < 3) {
2967                                 cur_lna = lna[j];
2968                                 cur_hpf1 = hpf1[j];
2969                                 cur_hpf2 = hpf2[j];
2970                         } else {
2971                                 if (power[1] > 10000) {
2972                                         use = 1;
2973                                         cur_hpf = cur_hpf1;
2974                                         index = 2;
2975                                 } else {
2976                                         if (power[0] > 10000) {
2977                                                 use = 1;
2978                                                 cur_hpf = cur_hpf1;
2979                                                 index = 1;
2980                                         } else {
2981                                                 index = 0;
2982                                                 use = 2;
2983                                                 cur_hpf = cur_hpf2;
2984                                         }
2985                                 }
2986                                 cur_lna = lna[index];
2987                                 cur_hpf1 = hpf1[index];
2988                                 cur_hpf2 = hpf2[index];
2989                                 cur_hpf += desired - hweight32(power[index]);
2990                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2991                                 if (use == 1)
2992                                         cur_hpf1 = cur_hpf;
2993                                 else
2994                                         cur_hpf2 = cur_hpf;
2995                         }
2996
2997                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2998                                         (cur_lna << 2));
2999                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3000                                                                         false);
3001                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3002                         b43_nphy_stop_playback(dev);
3003
3004                         if (playtone) {
3005                                 ret = b43_nphy_tx_tone(dev, 4000,
3006                                                 (nphy->rxcalparams & 0xFFFF),
3007                                                 false, false);
3008                                 playtone = false;
3009                         } else {
3010                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3011                                                         false, false);
3012                         }
3013
3014                         if (ret == 0) {
3015                                 if (j < 3) {
3016                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3017                                                                         false);
3018                                         if (i == 0) {
3019                                                 real = est.i0_pwr;
3020                                                 imag = est.q0_pwr;
3021                                         } else {
3022                                                 real = est.i1_pwr;
3023                                                 imag = est.q1_pwr;
3024                                         }
3025                                         power[i] = ((real + imag) / 1024) + 1;
3026                                 } else {
3027                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3028                                 }
3029                                 b43_nphy_stop_playback(dev);
3030                         }
3031
3032                         if (ret != 0)
3033                                 break;
3034                 }
3035
3036                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3037                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3038                 b43_phy_write(dev, rfctl[1], tmp[5]);
3039                 b43_phy_write(dev, rfctl[0], tmp[4]);
3040                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3041                 b43_phy_write(dev, afectl_core, tmp[2]);
3042                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3043
3044                 if (ret != 0)
3045                         break;
3046         }
3047
3048         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3049         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3050         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3051
3052         b43_nphy_stay_in_carrier_search(dev, 0);
3053
3054         return ret;
3055 }
3056
3057 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3058                         struct nphy_txgains target, u8 type, bool debug)
3059 {
3060         return -1;
3061 }
3062
3063 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3064 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3065                         struct nphy_txgains target, u8 type, bool debug)
3066 {
3067         if (dev->phy.rev >= 3)
3068                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3069         else
3070                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3071 }
3072
3073 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3074 static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3075 {
3076         u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3077         if (on)
3078                 tmslow |= SSB_TMSLOW_PHYCLK;
3079         else
3080                 tmslow &= ~SSB_TMSLOW_PHYCLK;
3081         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3082 }
3083
3084 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3085 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3086 {
3087         struct b43_phy *phy = &dev->phy;
3088         struct b43_phy_n *nphy = phy->n;
3089         u16 buf[16];
3090
3091         nphy->phyrxchain = mask;
3092
3093         if (0 /* FIXME clk */)
3094                 return;
3095
3096         b43_mac_suspend(dev);
3097
3098         if (nphy->hang_avoid)
3099                 b43_nphy_stay_in_carrier_search(dev, true);
3100
3101         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3102                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3103
3104         if ((mask & 0x3) != 0x3) {
3105                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3106                 if (dev->phy.rev >= 3) {
3107                         /* TODO */
3108                 }
3109         } else {
3110                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3111                 if (dev->phy.rev >= 3) {
3112                         /* TODO */
3113                 }
3114         }
3115
3116         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3117
3118         if (nphy->hang_avoid)
3119                 b43_nphy_stay_in_carrier_search(dev, false);
3120
3121         b43_mac_enable(dev);
3122 }
3123
3124 /*
3125  * Init N-PHY
3126  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3127  */
3128 int b43_phy_initn(struct b43_wldev *dev)
3129 {
3130         struct ssb_bus *bus = dev->dev->bus;
3131         struct b43_phy *phy = &dev->phy;
3132         struct b43_phy_n *nphy = phy->n;
3133         u8 tx_pwr_state;
3134         struct nphy_txgains target;
3135         u16 tmp;
3136         enum ieee80211_band tmp2;
3137         bool do_rssi_cal;
3138
3139         u16 clip[2];
3140         bool do_cal = false;
3141
3142         if ((dev->phy.rev >= 3) &&
3143            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3144            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3145                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3146         }
3147         nphy->deaf_count = 0;
3148         b43_nphy_tables_init(dev);
3149         nphy->crsminpwr_adjusted = false;
3150         nphy->noisevars_adjusted = false;
3151
3152         /* Clear all overrides */
3153         if (dev->phy.rev >= 3) {
3154                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3155                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3156                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3157                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3158         } else {
3159                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3160         }
3161         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3162         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3163         if (dev->phy.rev < 6) {
3164                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3165                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3166         }
3167         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3168                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3169                        B43_NPHY_RFSEQMODE_TROVER));
3170         if (dev->phy.rev >= 3)
3171                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3172         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3173
3174         if (dev->phy.rev <= 2) {
3175                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3176                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3177                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3178                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3179         }
3180         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3181         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3182
3183         if (bus->sprom.boardflags2_lo & 0x100 ||
3184             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3185              bus->boardinfo.type == 0x8B))
3186                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3187         else
3188                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3189         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3190         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3191         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3192
3193         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3194         b43_nphy_update_txrx_chain(dev);
3195
3196         if (phy->rev < 2) {
3197                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3198                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3199         }
3200
3201         tmp2 = b43_current_band(dev->wl);
3202         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3203             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3204                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3205                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3206                                 nphy->papd_epsilon_offset[0] << 7);
3207                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3208                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3209                                 nphy->papd_epsilon_offset[1] << 7);
3210                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3211         } else if (phy->rev >= 5) {
3212                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3213         }
3214
3215         b43_nphy_workarounds(dev);
3216
3217         /* Reset CCA, in init code it differs a little from standard way */
3218         b43_nphy_bmac_clock_fgc(dev, 1);
3219         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3220         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3221         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3222         b43_nphy_bmac_clock_fgc(dev, 0);
3223
3224         b43_nphy_mac_phy_clock_set(dev, true);
3225
3226         b43_nphy_pa_override(dev, false);
3227         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3228         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3229         b43_nphy_pa_override(dev, true);
3230
3231         b43_nphy_classifier(dev, 0, 0);
3232         b43_nphy_read_clip_detection(dev, clip);
3233         tx_pwr_state = nphy->txpwrctrl;
3234         /* TODO N PHY TX power control with argument 0
3235                 (turning off power control) */
3236         /* TODO Fix the TX Power Settings */
3237         /* TODO N PHY TX Power Control Idle TSSI */
3238         /* TODO N PHY TX Power Control Setup */
3239
3240         if (phy->rev >= 3) {
3241                 /* TODO */
3242         } else {
3243                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3244                                         b43_ntab_tx_gain_rev0_1_2);
3245                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3246                                         b43_ntab_tx_gain_rev0_1_2);
3247         }
3248
3249         if (nphy->phyrxchain != 3)
3250                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3251         if (nphy->mphase_cal_phase_id > 0)
3252                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3253
3254         do_rssi_cal = false;
3255         if (phy->rev >= 3) {
3256                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3257                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3258                 else
3259                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3260
3261                 if (do_rssi_cal)
3262                         b43_nphy_rssi_cal(dev);
3263                 else
3264                         b43_nphy_restore_rssi_cal(dev);
3265         } else {
3266                 b43_nphy_rssi_cal(dev);
3267         }
3268
3269         if (!((nphy->measure_hold & 0x6) != 0)) {
3270                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3271                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3272                 else
3273                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3274
3275                 if (nphy->mute)
3276                         do_cal = false;
3277
3278                 if (do_cal) {
3279                         target = b43_nphy_get_tx_gains(dev);
3280
3281                         if (nphy->antsel_type == 2)
3282                                 b43_nphy_superswitch_init(dev, true);
3283                         if (nphy->perical != 2) {
3284                                 b43_nphy_rssi_cal(dev);
3285                                 if (phy->rev >= 3) {
3286                                         nphy->cal_orig_pwr_idx[0] =
3287                                             nphy->txpwrindex[0].index_internal;
3288                                         nphy->cal_orig_pwr_idx[1] =
3289                                             nphy->txpwrindex[1].index_internal;
3290                                         /* TODO N PHY Pre Calibrate TX Gain */
3291                                         target = b43_nphy_get_tx_gains(dev);
3292                                 }
3293                         }
3294                 }
3295         }
3296
3297         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3298                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3299                         b43_nphy_save_cal(dev);
3300                 else if (nphy->mphase_cal_phase_id == 0)
3301                         ;/* N PHY Periodic Calibration with argument 3 */
3302         } else {
3303                 b43_nphy_restore_cal(dev);
3304         }
3305
3306         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3307         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3308         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3309         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3310         if (phy->rev >= 3 && phy->rev <= 6)
3311                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3312         b43_nphy_tx_lp_fbw(dev);
3313         if (phy->rev >= 3)
3314                 b43_nphy_spur_workaround(dev);
3315
3316         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3317         return 0;
3318 }
3319
3320 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3321 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3322                                 const struct b43_phy_n_sfo_cfg *e,
3323                                 struct ieee80211_channel *new_channel)
3324 {
3325         struct b43_phy *phy = &dev->phy;
3326         struct b43_phy_n *nphy = dev->phy.n;
3327
3328         u16 old_band_5ghz;
3329         u32 tmp32;
3330
3331         old_band_5ghz =
3332                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3333         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3334                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3335                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3336                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3337                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3338                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3339         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3340                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3341                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3342                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3343                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3344                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3345         }
3346
3347         b43_chantab_phy_upload(dev, e);
3348
3349         if (new_channel->hw_value == 14) {
3350                 b43_nphy_classifier(dev, 2, 0);
3351                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3352         } else {
3353                 b43_nphy_classifier(dev, 2, 2);
3354                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3355                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3356         }
3357
3358         if (nphy->txpwrctrl)
3359                 b43_nphy_tx_power_fix(dev);
3360
3361         if (dev->phy.rev < 3)
3362                 b43_nphy_adjust_lna_gain_table(dev);
3363
3364         b43_nphy_tx_lp_fbw(dev);
3365
3366         if (dev->phy.rev >= 3 && 0) {
3367                 /* TODO */
3368         }
3369
3370         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3371
3372         if (phy->rev >= 3)
3373                 b43_nphy_spur_workaround(dev);
3374 }
3375
3376 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3377 static int b43_nphy_set_channel(struct b43_wldev *dev,
3378                                 struct ieee80211_channel *channel,
3379                                 enum nl80211_channel_type channel_type)
3380 {
3381         struct b43_phy *phy = &dev->phy;
3382         struct b43_phy_n *nphy = dev->phy.n;
3383
3384         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3385         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
3386
3387         u8 tmp;
3388
3389         if (dev->phy.rev >= 3) {
3390                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3391                                                         channel->center_freq);
3392                 tabent_r3 = NULL;
3393                 if (!tabent_r3)
3394                         return -ESRCH;
3395         } else {
3396                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3397                                                         channel->hw_value);
3398                 if (!tabent_r2)
3399                         return -ESRCH;
3400         }
3401
3402         /* Channel is set later in common code, but we need to set it on our
3403            own to let this function's subcalls work properly. */
3404         phy->channel = channel->hw_value;
3405         phy->channel_freq = channel->center_freq;
3406
3407         if (b43_channel_type_is_40mhz(phy->channel_type) !=
3408                 b43_channel_type_is_40mhz(channel_type))
3409                 ; /* TODO: BMAC BW Set (channel_type) */
3410
3411         if (channel_type == NL80211_CHAN_HT40PLUS)
3412                 b43_phy_set(dev, B43_NPHY_RXCTL,
3413                                 B43_NPHY_RXCTL_BSELU20);
3414         else if (channel_type == NL80211_CHAN_HT40MINUS)
3415                 b43_phy_mask(dev, B43_NPHY_RXCTL,
3416                                 ~B43_NPHY_RXCTL_BSELU20);
3417
3418         if (dev->phy.rev >= 3) {
3419                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3420                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3421                 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
3422                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3423         } else {
3424                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3425                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3426                 b43_radio_2055_setup(dev, tabent_r2);
3427                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3428         }
3429
3430         return 0;
3431 }
3432
3433 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3434 {
3435         struct b43_phy_n *nphy;
3436
3437         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3438         if (!nphy)
3439                 return -ENOMEM;
3440         dev->phy.n = nphy;
3441
3442         return 0;
3443 }
3444
3445 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3446 {
3447         struct b43_phy *phy = &dev->phy;
3448         struct b43_phy_n *nphy = phy->n;
3449
3450         memset(nphy, 0, sizeof(*nphy));
3451
3452         //TODO init struct b43_phy_n
3453 }
3454
3455 static void b43_nphy_op_free(struct b43_wldev *dev)
3456 {
3457         struct b43_phy *phy = &dev->phy;
3458         struct b43_phy_n *nphy = phy->n;
3459
3460         kfree(nphy);
3461         phy->n = NULL;
3462 }
3463
3464 static int b43_nphy_op_init(struct b43_wldev *dev)
3465 {
3466         return b43_phy_initn(dev);
3467 }
3468
3469 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3470 {
3471 #if B43_DEBUG
3472         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3473                 /* OFDM registers are onnly available on A/G-PHYs */
3474                 b43err(dev->wl, "Invalid OFDM PHY access at "
3475                        "0x%04X on N-PHY\n", offset);
3476                 dump_stack();
3477         }
3478         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3479                 /* Ext-G registers are only available on G-PHYs */
3480                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3481                        "0x%04X on N-PHY\n", offset);
3482                 dump_stack();
3483         }
3484 #endif /* B43_DEBUG */
3485 }
3486
3487 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3488 {
3489         check_phyreg(dev, reg);
3490         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3491         return b43_read16(dev, B43_MMIO_PHY_DATA);
3492 }
3493
3494 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3495 {
3496         check_phyreg(dev, reg);
3497         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3498         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3499 }
3500
3501 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3502 {
3503         /* Register 1 is a 32-bit register. */
3504         B43_WARN_ON(reg == 1);
3505         /* N-PHY needs 0x100 for read access */
3506         reg |= 0x100;
3507
3508         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3509         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3510 }
3511
3512 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3513 {
3514         /* Register 1 is a 32-bit register. */
3515         B43_WARN_ON(reg == 1);
3516
3517         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3518         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3519 }
3520
3521 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3522 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3523                                         bool blocked)
3524 {
3525         struct b43_phy_n *nphy = dev->phy.n;
3526
3527         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3528                 b43err(dev->wl, "MAC not suspended\n");
3529
3530         if (blocked) {
3531                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3532                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3533                 if (dev->phy.rev >= 3) {
3534                         b43_radio_mask(dev, 0x09, ~0x2);
3535
3536                         b43_radio_write(dev, 0x204D, 0);
3537                         b43_radio_write(dev, 0x2053, 0);
3538                         b43_radio_write(dev, 0x2058, 0);
3539                         b43_radio_write(dev, 0x205E, 0);
3540                         b43_radio_mask(dev, 0x2062, ~0xF0);
3541                         b43_radio_write(dev, 0x2064, 0);
3542
3543                         b43_radio_write(dev, 0x304D, 0);
3544                         b43_radio_write(dev, 0x3053, 0);
3545                         b43_radio_write(dev, 0x3058, 0);
3546                         b43_radio_write(dev, 0x305E, 0);
3547                         b43_radio_mask(dev, 0x3062, ~0xF0);
3548                         b43_radio_write(dev, 0x3064, 0);
3549                 }
3550         } else {
3551                 if (dev->phy.rev >= 3) {
3552                         b43_radio_init2056(dev);
3553                         b43_switch_channel(dev, dev->phy.channel);
3554                 } else {
3555                         b43_radio_init2055(dev);
3556                 }
3557         }
3558 }
3559
3560 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3561 {
3562         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3563                       on ? 0 : 0x7FFF);
3564 }
3565
3566 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3567                                       unsigned int new_channel)
3568 {
3569         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
3570         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
3571
3572         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3573                 if ((new_channel < 1) || (new_channel > 14))
3574                         return -EINVAL;
3575         } else {
3576                 if (new_channel > 200)
3577                         return -EINVAL;
3578         }
3579
3580         return b43_nphy_set_channel(dev, channel, channel_type);
3581 }
3582
3583 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3584 {
3585         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3586                 return 1;
3587         return 36;
3588 }
3589
3590 const struct b43_phy_operations b43_phyops_n = {
3591         .allocate               = b43_nphy_op_allocate,
3592         .free                   = b43_nphy_op_free,
3593         .prepare_structs        = b43_nphy_op_prepare_structs,
3594         .init                   = b43_nphy_op_init,
3595         .phy_read               = b43_nphy_op_read,
3596         .phy_write              = b43_nphy_op_write,
3597         .radio_read             = b43_nphy_op_radio_read,
3598         .radio_write            = b43_nphy_op_radio_write,
3599         .software_rfkill        = b43_nphy_op_software_rfkill,
3600         .switch_analog          = b43_nphy_op_switch_analog,
3601         .switch_channel         = b43_nphy_op_switch_channel,
3602         .get_default_chan       = b43_nphy_op_get_default_chan,
3603         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3604         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3605 };