drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "main.h"
  36
  37 struct nphy_txgains {
  38         u16 txgm[2];
  39         u16 pga[2];
  40         u16 pad[2];
  41         u16 ipa[2];
  42 };
  43
  44 struct nphy_iqcal_params {
  45         u16 txgm;
  46         u16 pga;
  47         u16 pad;
  48         u16 ipa;
  49         u16 cal_gain;
  50         u16 ncorr[5];
  51 };
  52
  53 struct nphy_iq_est {
  54         s32 iq0_prod;
  55         u32 i0_pwr;
  56         u32 q0_pwr;
  57         s32 iq1_prod;
  58         u32 i1_pwr;
  59         u32 q1_pwr;
  60 };
  61
  62 enum b43_nphy_rf_sequence {
  63         B43_RFSEQ_RX2TX,
  64         B43_RFSEQ_TX2RX,
  65         B43_RFSEQ_RESET2RX,
  66         B43_RFSEQ_UPDATE_GAINH,
  67         B43_RFSEQ_UPDATE_GAINL,
  68         B43_RFSEQ_UPDATE_GAINU,
  69 };
  70
  71 enum b43_nphy_rssi_type {
  72         B43_NPHY_RSSI_X = 0,
  73         B43_NPHY_RSSI_Y,
  74         B43_NPHY_RSSI_Z,
  75         B43_NPHY_RSSI_PWRDET,
  76         B43_NPHY_RSSI_TSSI_I,
  77         B43_NPHY_RSSI_TSSI_Q,
  78         B43_NPHY_RSSI_TBD,
  79 };
  80
  81 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
  82 {
  83         enum ieee80211_band band = b43_current_band(dev->wl);
  84         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  85                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
  86 }
  87
  88 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
  89 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
  90 {
  91         return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
  92                 B43_NPHY_RFSEQCA_RXEN_SHIFT;
  93 }
  94
  95 /**************************************************
  96  * RF (just without b43_nphy_rf_control_intc_override)
  97  **************************************************/
  98
  99 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
 100 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 101                                        enum b43_nphy_rf_sequence seq)
 102 {
 103         static const u16 trigger[] = {
 104                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 105                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 106                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 107                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 108                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 109                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 110         };
 111         int i;
 112         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
 113
 114         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 115
 116         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 117                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 118         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 119         for (i = 0; i < 200; i++) {
 120                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 121                         goto ok;
 122                 msleep(1);
 123         }
 124         b43err(dev->wl, "RF sequence status timeout\n");
 125 ok:
 126         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
 127 }
 128
 129 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
 130 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
 131                                                 u16 value, u8 core, bool off)
 132 {
 133         int i;
 134         u8 index = fls(field);
 135         u8 addr, en_addr, val_addr;
 136         /* we expect only one bit set */
 137         B43_WARN_ON(field & (~(1 << (index - 1))));
 138
 139         if (dev->phy.rev >= 3) {
 140                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
 141                 for (i = 0; i < 2; i++) {
 142                         if (index == 0 || index == 16) {
 143                                 b43err(dev->wl,
 144                                         "Unsupported RF Ctrl Override call\n");
 145                                 return;
 146                         }
 147
 148                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
 149                         en_addr = B43_PHY_N((i == 0) ?
 150                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
 151                         val_addr = B43_PHY_N((i == 0) ?
 152                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
 153
 154                         if (off) {
 155                                 b43_phy_mask(dev, en_addr, ~(field));
 156                                 b43_phy_mask(dev, val_addr,
 157                                                 ~(rf_ctrl->val_mask));
 158                         } else {
 159                                 if (core == 0 || ((1 << i) & core)) {
 160                                         b43_phy_set(dev, en_addr, field);
 161                                         b43_phy_maskset(dev, val_addr,
 162                                                 ~(rf_ctrl->val_mask),
 163                                                 (value << rf_ctrl->val_shift));
 164                                 }
 165                         }
 166                 }
 167         } else {
 168                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
 169                 if (off) {
 170                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
 171                         value = 0;
 172                 } else {
 173                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
 174                 }
 175
 176                 for (i = 0; i < 2; i++) {
 177                         if (index <= 1 || index == 16) {
 178                                 b43err(dev->wl,
 179                                         "Unsupported RF Ctrl Override call\n");
 180                                 return;
 181                         }
 182
 183                         if (index == 2 || index == 10 ||
 184                             (index >= 13 && index <= 15)) {
 185                                 core = 1;
 186                         }
 187
 188                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
 189                         addr = B43_PHY_N((i == 0) ?
 190                                 rf_ctrl->addr0 : rf_ctrl->addr1);
 191
 192                         if ((1 << i) & core)
 193                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
 194                                                 (value << rf_ctrl->shift));
 195
 196                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
 197                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 198                                         B43_NPHY_RFCTL_CMD_START);
 199                         udelay(1);
 200                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
 201                 }
 202         }
 203 }
 204
 205 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
 206 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
 207                                                 u16 value, u8 core)
 208 {
 209         u8 i, j;
 210         u16 reg, tmp, val;
 211
 212         B43_WARN_ON(dev->phy.rev < 3);
 213         B43_WARN_ON(field > 4);
 214
 215         for (i = 0; i < 2; i++) {
 216                 if ((core == 1 && i == 1) || (core == 2 && !i))
 217                         continue;
 218
 219                 reg = (i == 0) ?
 220                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
 221                 b43_phy_set(dev, reg, 0x400);
 222
 223                 switch (field) {
 224                 case 0:
 225                         b43_phy_write(dev, reg, 0);
 226                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 227                         break;
 228                 case 1:
 229                         if (!i) {
 230                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
 231                                                 0xFC3F, (value << 6));
 232                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
 233                                                 0xFFFE, 1);
 234                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 235                                                 B43_NPHY_RFCTL_CMD_START);
 236                                 for (j = 0; j < 100; j++) {
 237                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
 238                                                 j = 0;
 239                                                 break;
 240                                         }
 241                                         udelay(10);
 242                                 }
 243                                 if (j)
 244                                         b43err(dev->wl,
 245                                                 "intc override timeout\n");
 246                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
 247                                                 0xFFFE);
 248                         } else {
 249                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
 250                                                 0xFC3F, (value << 6));
 251                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 252                                                 0xFFFE, 1);
 253                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 254                                                 B43_NPHY_RFCTL_CMD_RXTX);
 255                                 for (j = 0; j < 100; j++) {
 256                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
 257                                                 j = 0;
 258                                                 break;
 259                                         }
 260                                         udelay(10);
 261                                 }
 262                                 if (j)
 263                                         b43err(dev->wl,
 264                                                 "intc override timeout\n");
 265                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
 266                                                 0xFFFE);
 267                         }
 268                         break;
 269                 case 2:
 270                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 271                                 tmp = 0x0020;
 272                                 val = value << 5;
 273                         } else {
 274                                 tmp = 0x0010;
 275                                 val = value << 4;
 276                         }
 277                         b43_phy_maskset(dev, reg, ~tmp, val);
 278                         break;
 279                 case 3:
 280                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 281                                 tmp = 0x0001;
 282                                 val = value;
 283                         } else {
 284                                 tmp = 0x0004;
 285                                 val = value << 2;
 286                         }
 287                         b43_phy_maskset(dev, reg, ~tmp, val);
 288                         break;
 289                 case 4:
 290                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 291                                 tmp = 0x0002;
 292                                 val = value << 1;
 293                         } else {
 294                                 tmp = 0x0008;
 295                                 val = value << 3;
 296                         }
 297                         b43_phy_maskset(dev, reg, ~tmp, val);
 298                         break;
 299                 }
 300         }
 301 }
 302
 303 /**************************************************
 304  * Various PHY ops
 305  **************************************************/
 306
 307 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 308 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 309                                           const u16 *clip_st)
 310 {
 311         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 312         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 313 }
 314
 315 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 316 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 317 {
 318         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 319         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 320 }
 321
 322 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 323 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 324 {
 325         u16 tmp;
 326
 327         if (dev->dev->core_rev == 16)
 328                 b43_mac_suspend(dev);
 329
 330         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 331         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 332                 B43_NPHY_CLASSCTL_WAITEDEN);
 333         tmp &= ~mask;
 334         tmp |= (val & mask);
 335         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 336
 337         if (dev->dev->core_rev == 16)
 338                 b43_mac_enable(dev);
 339
 340         return tmp;
 341 }
 342
 343 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 344 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 345 {
 346         u16 bbcfg;
 347
 348         b43_phy_force_clock(dev, 1);
 349         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 350         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 351         udelay(1);
 352         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 353         b43_phy_force_clock(dev, 0);
 354         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 355 }
 356
 357 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 358 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 359 {
 360         struct b43_phy *phy = &dev->phy;
 361         struct b43_phy_n *nphy = phy->n;
 362
 363         if (enable) {
 364                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
 365                 if (nphy->deaf_count++ == 0) {
 366                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 367                         b43_nphy_classifier(dev, 0x7, 0);
 368                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 369                         b43_nphy_write_clip_detection(dev, clip);
 370                 }
 371                 b43_nphy_reset_cca(dev);
 372         } else {
 373                 if (--nphy->deaf_count == 0) {
 374                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 375                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 376                 }
 377         }
 378 }
 379
 380 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 381 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 382 {
 383         struct b43_phy_n *nphy = dev->phy.n;
 384
 385         u8 i;
 386         s16 tmp;
 387         u16 data[4];
 388         s16 gain[2];
 389         u16 minmax[2];
 390         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
 391
 392         if (nphy->hang_avoid)
 393                 b43_nphy_stay_in_carrier_search(dev, 1);
 394
 395         if (nphy->gain_boost) {
 396                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 397                         gain[0] = 6;
 398                         gain[1] = 6;
 399                 } else {
 400                         tmp = 40370 - 315 * dev->phy.channel;
 401                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 402                         tmp = 23242 - 224 * dev->phy.channel;
 403                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 404                 }
 405         } else {
 406                 gain[0] = 0;
 407                 gain[1] = 0;
 408         }
 409
 410         for (i = 0; i < 2; i++) {
 411                 if (nphy->elna_gain_config) {
 412                         data[0] = 19 + gain[i];
 413                         data[1] = 25 + gain[i];
 414                         data[2] = 25 + gain[i];
 415                         data[3] = 25 + gain[i];
 416                 } else {
 417                         data[0] = lna_gain[0] + gain[i];
 418                         data[1] = lna_gain[1] + gain[i];
 419                         data[2] = lna_gain[2] + gain[i];
 420                         data[3] = lna_gain[3] + gain[i];
 421                 }
 422                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
 423
 424                 minmax[i] = 23 + gain[i];
 425         }
 426
 427         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 428                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 429         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 430                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 431
 432         if (nphy->hang_avoid)
 433                 b43_nphy_stay_in_carrier_search(dev, 0);
 434 }
 435
 436 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
 437 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
 438                                         u8 *events, u8 *delays, u8 length)
 439 {
 440         struct b43_phy_n *nphy = dev->phy.n;
 441         u8 i;
 442         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
 443         u16 offset1 = cmd << 4;
 444         u16 offset2 = offset1 + 0x80;
 445
 446         if (nphy->hang_avoid)
 447                 b43_nphy_stay_in_carrier_search(dev, true);
 448
 449         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
 450         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
 451
 452         for (i = length; i < 16; i++) {
 453                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
 454                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
 455         }
 456
 457         if (nphy->hang_avoid)
 458                 b43_nphy_stay_in_carrier_search(dev, false);
 459 }
 460
 461 /**************************************************
 462  * Radio 0x2056
 463  **************************************************/
 464
 465 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 466                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 467 {
 468         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 469         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 470         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 471         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 472         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 473         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 474                                         e->radio_syn_pll_loopfilter1);
 475         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 476                                         e->radio_syn_pll_loopfilter2);
 477         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 478                                         e->radio_syn_pll_loopfilter3);
 479         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 480                                         e->radio_syn_pll_loopfilter4);
 481         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 482                                         e->radio_syn_pll_loopfilter5);
 483         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 484                                         e->radio_syn_reserved_addr27);
 485         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 486                                         e->radio_syn_reserved_addr28);
 487         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 488                                         e->radio_syn_reserved_addr29);
 489         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 490                                         e->radio_syn_logen_vcobuf1);
 491         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 492         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 493         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 494
 495         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 496                                         e->radio_rx0_lnaa_tune);
 497         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 498                                         e->radio_rx0_lnag_tune);
 499
 500         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 501                                         e->radio_tx0_intpaa_boost_tune);
 502         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 503                                         e->radio_tx0_intpag_boost_tune);
 504         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 505                                         e->radio_tx0_pada_boost_tune);
 506         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 507                                         e->radio_tx0_padg_boost_tune);
 508         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 509                                         e->radio_tx0_pgaa_boost_tune);
 510         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 511                                         e->radio_tx0_pgag_boost_tune);
 512         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 513                                         e->radio_tx0_mixa_boost_tune);
 514         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 515                                         e->radio_tx0_mixg_boost_tune);
 516
 517         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 518                                         e->radio_rx1_lnaa_tune);
 519         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 520                                         e->radio_rx1_lnag_tune);
 521
 522         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 523                                         e->radio_tx1_intpaa_boost_tune);
 524         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 525                                         e->radio_tx1_intpag_boost_tune);
 526         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 527                                         e->radio_tx1_pada_boost_tune);
 528         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 529                                         e->radio_tx1_padg_boost_tune);
 530         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 531                                         e->radio_tx1_pgaa_boost_tune);
 532         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 533                                         e->radio_tx1_pgag_boost_tune);
 534         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 535                                         e->radio_tx1_mixa_boost_tune);
 536         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 537                                         e->radio_tx1_mixg_boost_tune);
 538 }
 539
 540 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 541 static void b43_radio_2056_setup(struct b43_wldev *dev,
 542                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 543 {
 544         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 545         enum ieee80211_band band = b43_current_band(dev->wl);
 546         u16 offset;
 547         u8 i;
 548         u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
 549
 550         B43_WARN_ON(dev->phy.rev < 3);
 551
 552         b43_chantab_radio_2056_upload(dev, e);
 553         b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
 554
 555         if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
 556             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 557                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 558                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 559                 if (dev->dev->chip_id == 0x4716) {
 560                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
 561                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
 562                 } else {
 563                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
 564                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
 565                 }
 566         }
 567         if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
 568             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 569                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 570                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 571                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
 572                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
 573         }
 574
 575         if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
 576                 for (i = 0; i < 2; i++) {
 577                         offset = i ? B2056_TX1 : B2056_TX0;
 578                         if (dev->phy.rev >= 5) {
 579                                 b43_radio_write(dev,
 580                                         offset | B2056_TX_PADG_IDAC, 0xcc);
 581
 582                                 if (dev->dev->chip_id == 0x4716) {
 583                                         bias = 0x40;
 584                                         cbias = 0x45;
 585                                         pag_boost = 0x5;
 586                                         pgag_boost = 0x33;
 587                                         mixg_boost = 0x55;
 588                                 } else {
 589                                         bias = 0x25;
 590                                         cbias = 0x20;
 591                                         pag_boost = 0x4;
 592                                         pgag_boost = 0x03;
 593                                         mixg_boost = 0x65;
 594                                 }
 595                                 padg_boost = 0x77;
 596
 597                                 b43_radio_write(dev,
 598                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 599                                         bias);
 600                                 b43_radio_write(dev,
 601                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 602                                         bias);
 603                                 b43_radio_write(dev,
 604                                         offset | B2056_TX_INTPAG_CASCBIAS,
 605                                         cbias);
 606                                 b43_radio_write(dev,
 607                                         offset | B2056_TX_INTPAG_BOOST_TUNE,
 608                                         pag_boost);
 609                                 b43_radio_write(dev,
 610                                         offset | B2056_TX_PGAG_BOOST_TUNE,
 611                                         pgag_boost);
 612                                 b43_radio_write(dev,
 613                                         offset | B2056_TX_PADG_BOOST_TUNE,
 614                                         padg_boost);
 615                                 b43_radio_write(dev,
 616                                         offset | B2056_TX_MIXG_BOOST_TUNE,
 617                                         mixg_boost);
 618                         } else {
 619                                 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
 620                                 b43_radio_write(dev,
 621                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 622                                         bias);
 623                                 b43_radio_write(dev,
 624                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 625                                         bias);
 626                                 b43_radio_write(dev,
 627                                         offset | B2056_TX_INTPAG_CASCBIAS,
 628                                         0x30);
 629                         }
 630                         b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
 631                 }
 632         } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
 633                 /* TODO */
 634         }
 635
 636         udelay(50);
 637         /* VCO calibration */
 638         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 639         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 640         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 641         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 642         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 643         udelay(300);
 644 }
 645
 646 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 647 {
 648         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 649                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 650         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 651         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 652                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 653         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 654                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 655         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 656                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 657 }
 658
 659 static void b43_radio_init2056_post(struct b43_wldev *dev)
 660 {
 661         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 662         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 663         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 664         msleep(1);
 665         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 666         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 667         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 668         /*
 669         if (nphy->init_por)
 670                 Call Radio 2056 Recalibrate
 671         */
 672 }
 673
 674 /*
 675  * Initialize a Broadcom 2056 N-radio
 676  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 677  */
 678 static void b43_radio_init2056(struct b43_wldev *dev)
 679 {
 680         b43_radio_init2056_pre(dev);
 681         b2056_upload_inittabs(dev, 0, 0);
 682         b43_radio_init2056_post(dev);
 683 }
 684
 685 /**************************************************
 686  * Radio 0x2055
 687  **************************************************/
 688
 689 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 690                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 691 {
 692         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 693         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 694         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 695         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 696         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 697
 698         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 699         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 700         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 701         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 702         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 703
 704         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 705         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 706         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 707         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 708         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 709
 710         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 711         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 712         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 713         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 714         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 715
 716         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 717         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 718         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 719         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 720         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 721
 722         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 723         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 724 }
 725
 726 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 727 static void b43_radio_2055_setup(struct b43_wldev *dev,
 728                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 729 {
 730         B43_WARN_ON(dev->phy.rev >= 3);
 731
 732         b43_chantab_radio_upload(dev, e);
 733         udelay(50);
 734         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 735         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 736         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 737         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 738         udelay(300);
 739 }
 740
 741 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 742 {
 743         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 744                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 745         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 746                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 747                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 748         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 749                     B43_NPHY_RFCTL_CMD_PORFORCE);
 750 }
 751
 752 static void b43_radio_init2055_post(struct b43_wldev *dev)
 753 {
 754         struct b43_phy_n *nphy = dev->phy.n;
 755         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 756         int i;
 757         u16 val;
 758         bool workaround = false;
 759
 760         if (sprom->revision < 4)
 761                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
 762                               && dev->dev->board_type == 0x46D
 763                               && dev->dev->board_rev >= 0x41);
 764         else
 765                 workaround =
 766                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 767
 768         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 769         if (workaround) {
 770                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 771                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 772         }
 773         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 774         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 775         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 776         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 777         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 778         msleep(1);
 779         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 780         for (i = 0; i < 200; i++) {
 781                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 782                 if (val & 0x80) {
 783                         i = 0;
 784                         break;
 785                 }
 786                 udelay(10);
 787         }
 788         if (i)
 789                 b43err(dev->wl, "radio post init timeout\n");
 790         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 791         b43_switch_channel(dev, dev->phy.channel);
 792         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 793         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 794         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 795         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 796         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 797         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 798         if (!nphy->gain_boost) {
 799                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 800                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 801         } else {
 802                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 803                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 804         }
 805         udelay(2);
 806 }
 807
 808 /*
 809  * Initialize a Broadcom 2055 N-radio
 810  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 811  */
 812 static void b43_radio_init2055(struct b43_wldev *dev)
 813 {
 814         b43_radio_init2055_pre(dev);
 815         if (b43_status(dev) < B43_STAT_INITIALIZED) {
 816                 /* Follow wl, not specs. Do not force uploading all regs */
 817                 b2055_upload_inittab(dev, 0, 0);
 818         } else {
 819                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 820                 b2055_upload_inittab(dev, ghz5, 0);
 821         }
 822         b43_radio_init2055_post(dev);
 823 }
 824
 825 /**************************************************
 826  * Samples
 827  **************************************************/
 828
 829 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
 830 static int b43_nphy_load_samples(struct b43_wldev *dev,
 831                                         struct b43_c32 *samples, u16 len) {
 832         struct b43_phy_n *nphy = dev->phy.n;
 833         u16 i;
 834         u32 *data;
 835
 836         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
 837         if (!data) {
 838                 b43err(dev->wl, "allocation for samples loading failed\n");
 839                 return -ENOMEM;
 840         }
 841         if (nphy->hang_avoid)
 842                 b43_nphy_stay_in_carrier_search(dev, 1);
 843
 844         for (i = 0; i < len; i++) {
 845                 data[i] = (samples[i].i & 0x3FF << 10);
 846                 data[i] |= samples[i].q & 0x3FF;
 847         }
 848         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
 849
 850         kfree(data);
 851         if (nphy->hang_avoid)
 852                 b43_nphy_stay_in_carrier_search(dev, 0);
 853         return 0;
 854 }
 855
 856 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
 857 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
 858                                         bool test)
 859 {
 860         int i;
 861         u16 bw, len, rot, angle;
 862         struct b43_c32 *samples;
 863
 864
 865         bw = (dev->phy.is_40mhz) ? 40 : 20;
 866         len = bw << 3;
 867
 868         if (test) {
 869                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
 870                         bw = 82;
 871                 else
 872                         bw = 80;
 873
 874                 if (dev->phy.is_40mhz)
 875                         bw <<= 1;
 876
 877                 len = bw << 1;
 878         }
 879
 880         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
 881         if (!samples) {
 882                 b43err(dev->wl, "allocation for samples generation failed\n");
 883                 return 0;
 884         }
 885         rot = (((freq * 36) / bw) << 16) / 100;
 886         angle = 0;
 887
 888         for (i = 0; i < len; i++) {
 889                 samples[i] = b43_cordic(angle);
 890                 angle += rot;
 891                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
 892                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
 893         }
 894
 895         i = b43_nphy_load_samples(dev, samples, len);
 896         kfree(samples);
 897         return (i < 0) ? 0 : len;
 898 }
 899
 900 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
 901 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
 902                                         u16 wait, bool iqmode, bool dac_test)
 903 {
 904         struct b43_phy_n *nphy = dev->phy.n;
 905         int i;
 906         u16 seq_mode;
 907         u32 tmp;
 908
 909         if (nphy->hang_avoid)
 910                 b43_nphy_stay_in_carrier_search(dev, true);
 911
 912         if ((nphy->bb_mult_save & 0x80000000) == 0) {
 913                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
 914                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
 915         }
 916
 917         if (!dev->phy.is_40mhz)
 918                 tmp = 0x6464;
 919         else
 920                 tmp = 0x4747;
 921         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 922
 923         if (nphy->hang_avoid)
 924                 b43_nphy_stay_in_carrier_search(dev, false);
 925
 926         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
 927
 928         if (loops != 0xFFFF)
 929                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
 930         else
 931                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
 932
 933         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
 934
 935         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
 936
 937         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
 938         if (iqmode) {
 939                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
 940                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
 941         } else {
 942                 if (dac_test)
 943                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
 944                 else
 945                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
 946         }
 947         for (i = 0; i < 100; i++) {
 948                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
 949                         i = 0;
 950                         break;
 951                 }
 952                 udelay(10);
 953         }
 954         if (i)
 955                 b43err(dev->wl, "run samples timeout\n");
 956
 957         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
 958 }
 959
 960 /**************************************************
 961  * RSSI
 962  **************************************************/
 963
 964 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
 965 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
 966                                         s8 offset, u8 core, u8 rail,
 967                                         enum b43_nphy_rssi_type type)
 968 {
 969         u16 tmp;
 970         bool core1or5 = (core == 1) || (core == 5);
 971         bool core2or5 = (core == 2) || (core == 5);
 972
 973         offset = clamp_val(offset, -32, 31);
 974         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
 975
 976         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
 977                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
 978         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
 979                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
 980         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
 981                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
 982         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
 983                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
 984
 985         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
 986                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
 987         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
 988                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
 989         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
 990                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
 991         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
 992                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
 993
 994         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
 995                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
 996         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
 997                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
 998         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
 999                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1000         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1001                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1002
1003         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1004                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1005         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1006                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1007         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1008                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1009         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1010                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1011
1012         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1013                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1014         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1015                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1016         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1017                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1018         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1019                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1020
1021         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
1022                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1023         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
1024                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1025
1026         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1027                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1028         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1029                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1030 }
1031
1032 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1033 {
1034         u8 i;
1035         u16 reg, val;
1036
1037         if (code == 0) {
1038                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1039                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1040                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1041                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1042                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1043                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1044                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1045                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1046         } else {
1047                 for (i = 0; i < 2; i++) {
1048                         if ((code == 1 && i == 1) || (code == 2 && !i))
1049                                 continue;
1050
1051                         reg = (i == 0) ?
1052                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1053                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1054
1055                         if (type < 3) {
1056                                 reg = (i == 0) ?
1057                                         B43_NPHY_AFECTL_C1 :
1058                                         B43_NPHY_AFECTL_C2;
1059                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1060
1061                                 reg = (i == 0) ?
1062                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1063                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1064                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1065
1066                                 if (type == 0)
1067                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1068                                 else if (type == 1)
1069                                         val = 16;
1070                                 else
1071                                         val = 32;
1072                                 b43_phy_set(dev, reg, val);
1073
1074                                 reg = (i == 0) ?
1075                                         B43_NPHY_TXF_40CO_B1S0 :
1076                                         B43_NPHY_TXF_40CO_B32S1;
1077                                 b43_phy_set(dev, reg, 0x0020);
1078                         } else {
1079                                 if (type == 6)
1080                                         val = 0x0100;
1081                                 else if (type == 3)
1082                                         val = 0x0200;
1083                                 else
1084                                         val = 0x0300;
1085
1086                                 reg = (i == 0) ?
1087                                         B43_NPHY_AFECTL_C1 :
1088                                         B43_NPHY_AFECTL_C2;
1089
1090                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1091                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1092
1093                                 if (type != 3 && type != 6) {
1094                                         enum ieee80211_band band =
1095                                                 b43_current_band(dev->wl);
1096
1097                                         if (b43_nphy_ipa(dev))
1098                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1099                                         else
1100                                                 val = 0x11;
1101                                         reg = (i == 0) ? 0x2000 : 0x3000;
1102                                         reg |= B2055_PADDRV;
1103                                         b43_radio_write16(dev, reg, val);
1104
1105                                         reg = (i == 0) ?
1106                                                 B43_NPHY_AFECTL_OVER1 :
1107                                                 B43_NPHY_AFECTL_OVER;
1108                                         b43_phy_set(dev, reg, 0x0200);
1109                                 }
1110                         }
1111                 }
1112         }
1113 }
1114
1115 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1116 {
1117         u16 val;
1118
1119         if (type < 3)
1120                 val = 0;
1121         else if (type == 6)
1122                 val = 1;
1123         else if (type == 3)
1124                 val = 2;
1125         else
1126                 val = 3;
1127
1128         val = (val << 12) | (val << 14);
1129         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1130         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1131
1132         if (type < 3) {
1133                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1134                                 (type + 1) << 4);
1135                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1136                                 (type + 1) << 4);
1137         }
1138
1139         if (code == 0) {
1140                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1141                 if (type < 3) {
1142                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1143                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1144                                   B43_NPHY_RFCTL_CMD_CORESEL));
1145                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1146                                 ~(0x1 << 12 |
1147                                   0x1 << 5 |
1148                                   0x1 << 1 |
1149                                   0x1));
1150                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1151                                 ~B43_NPHY_RFCTL_CMD_START);
1152                         udelay(20);
1153                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1154                 }
1155         } else {
1156                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1157                 if (type < 3) {
1158                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1159                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1160                                   B43_NPHY_RFCTL_CMD_CORESEL),
1161                                 (B43_NPHY_RFCTL_CMD_RXEN |
1162                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1163                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1164                                 (0x1 << 12 |
1165                                   0x1 << 5 |
1166                                   0x1 << 1 |
1167                                   0x1));
1168                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1169                                 B43_NPHY_RFCTL_CMD_START);
1170                         udelay(20);
1171                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1172                 }
1173         }
1174 }
1175
1176 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1177 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1178 {
1179         if (dev->phy.rev >= 3)
1180                 b43_nphy_rev3_rssi_select(dev, code, type);
1181         else
1182                 b43_nphy_rev2_rssi_select(dev, code, type);
1183 }
1184
1185 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1186 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1187 {
1188         int i;
1189         for (i = 0; i < 2; i++) {
1190                 if (type == 2) {
1191                         if (i == 0) {
1192                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1193                                                   0xFC, buf[0]);
1194                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1195                                                   0xFC, buf[1]);
1196                         } else {
1197                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1198                                                   0xFC, buf[2 * i]);
1199                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1200                                                   0xFC, buf[2 * i + 1]);
1201                         }
1202                 } else {
1203                         if (i == 0)
1204                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1205                                                   0xF3, buf[0] << 2);
1206                         else
1207                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1208                                                   0xF3, buf[2 * i + 1] << 2);
1209                 }
1210         }
1211 }
1212
1213 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1214 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1215                                 u8 nsamp)
1216 {
1217         int i;
1218         int out;
1219         u16 save_regs_phy[9];
1220         u16 s[2];
1221
1222         if (dev->phy.rev >= 3) {
1223                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1224                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1225                 save_regs_phy[2] = b43_phy_read(dev,
1226                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1227                 save_regs_phy[3] = b43_phy_read(dev,
1228                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1229                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1230                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1231                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1232                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1233                 save_regs_phy[8] = 0;
1234         } else {
1235                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1236                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1237                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1238                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1239                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1240                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1241                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1242                 save_regs_phy[7] = 0;
1243                 save_regs_phy[8] = 0;
1244         }
1245
1246         b43_nphy_rssi_select(dev, 5, type);
1247
1248         if (dev->phy.rev < 2) {
1249                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1250                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1251         }
1252
1253         for (i = 0; i < 4; i++)
1254                 buf[i] = 0;
1255
1256         for (i = 0; i < nsamp; i++) {
1257                 if (dev->phy.rev < 2) {
1258                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1259                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1260                 } else {
1261                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1262                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1263                 }
1264
1265                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1266                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1267                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1268                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1269         }
1270         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1271                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1272
1273         if (dev->phy.rev < 2)
1274                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1275
1276         if (dev->phy.rev >= 3) {
1277                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1278                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1279                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1280                                 save_regs_phy[2]);
1281                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1282                                 save_regs_phy[3]);
1283                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1284                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1285                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1286                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1287         } else {
1288                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1289                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1290                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1291                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1292                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1293                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1294                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1295         }
1296
1297         return out;
1298 }
1299
1300 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1301 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1302 {
1303         struct b43_phy_n *nphy = dev->phy.n;
1304
1305         u16 saved_regs_phy_rfctl[2];
1306         u16 saved_regs_phy[13];
1307         u16 regs_to_store[] = {
1308                 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1309                 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1310                 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1311                 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1312                 B43_NPHY_RFCTL_CMD,
1313                 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1314                 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1315         };
1316
1317         u16 class;
1318
1319         u16 clip_state[2];
1320         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1321
1322         u8 vcm_final = 0;
1323         s8 offset[4];
1324         s32 results[8][4] = { };
1325         s32 results_min[4] = { };
1326         s32 poll_results[4] = { };
1327
1328         u16 *rssical_radio_regs = NULL;
1329         u16 *rssical_phy_regs = NULL;
1330
1331         u16 r; /* routing */
1332         u8 rx_core_state;
1333         u8 core, i, j;
1334
1335         class = b43_nphy_classifier(dev, 0, 0);
1336         b43_nphy_classifier(dev, 7, 4);
1337         b43_nphy_read_clip_detection(dev, clip_state);
1338         b43_nphy_write_clip_detection(dev, clip_off);
1339
1340         saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1341         saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1342         for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1343                 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1344
1345         b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
1346         b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
1347         b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
1348         b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
1349         b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
1350         b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
1351
1352         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1353                 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
1354                 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
1355         } else {
1356                 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
1357                 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
1358         }
1359
1360         rx_core_state = b43_nphy_get_rx_core_state(dev);
1361         for (core = 0; core < 2; core++) {
1362                 if (!(rx_core_state & (1 << core)))
1363                         continue;
1364                 r = core ? B2056_RX1 : B2056_RX0;
1365                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, 2);
1366                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, 2);
1367                 for (i = 0; i < 8; i++) {
1368                         b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1369                                         i << 2);
1370                         b43_nphy_poll_rssi(dev, 2, results[i], 8);
1371                 }
1372                 for (i = 0; i < 4; i += 2) {
1373                         s32 curr;
1374                         s32 mind = 40;
1375                         s32 minpoll = 249;
1376                         u8 minvcm = 0;
1377                         if (2 * core != i)
1378                                 continue;
1379                         for (j = 0; j < 8; j++) {
1380                                 curr = results[j][i] * results[j][i] +
1381                                         results[j][i + 1] * results[j][i];
1382                                 if (curr < mind) {
1383                                         mind = curr;
1384                                         minvcm = j;
1385                                 }
1386                                 if (results[j][i] < minpoll)
1387                                         minpoll = results[j][i];
1388                         }
1389                         vcm_final = minvcm;
1390                         results_min[i] = minpoll;
1391                 }
1392                 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1393                                   vcm_final << 2);
1394                 for (i = 0; i < 4; i++) {
1395                         if (core != i / 2)
1396                                 continue;
1397                         offset[i] = -results[vcm_final][i];
1398                         if (offset[i] < 0)
1399                                 offset[i] = -((abs(offset[i]) + 4) / 8);
1400                         else
1401                                 offset[i] = (offset[i] + 4) / 8;
1402                         if (results_min[i] == 248)
1403                                 offset[i] = -32;
1404                         b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1405                                                    (i / 2 == 0) ? 1 : 2,
1406                                                    (i % 2 == 0) ? 0 : 1,
1407                                                    2);
1408                 }
1409         }
1410         for (core = 0; core < 2; core++) {
1411                 if (!(rx_core_state & (1 << core)))
1412                         continue;
1413                 for (i = 0; i < 2; i++) {
1414                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, i);
1415                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, i);
1416                         b43_nphy_poll_rssi(dev, i, poll_results, 8);
1417                         for (j = 0; j < 4; j++) {
1418                                 if (j / 2 == core) {
1419                                         offset[j] = 232 - poll_results[j];
1420                                         if (offset[j] < 0)
1421                                                 offset[j] = -(abs(offset[j] + 4) / 8);
1422                                         else
1423                                                 offset[j] = (offset[j] + 4) / 8;
1424                                         b43_nphy_scale_offset_rssi(dev, 0,
1425                                                 offset[2 * core], core + 1, j % 2, i);
1426                                 }
1427                         }
1428                 }
1429         }
1430
1431         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1432         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1433
1434         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1435
1436         b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1437         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1438         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1439
1440         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1441         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1442         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1443
1444         for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1445                 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1446
1447         /* Store for future configuration */
1448         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1449                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1450                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1451         } else {
1452                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1453                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1454         }
1455         rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
1456         rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
1457         rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1458         rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1459         rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1460         rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1461         rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1462         rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1463         rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1464         rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1465         rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1466         rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1467         rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1468         rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1469
1470         /* Remember for which channel we store configuration */
1471         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1472                 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1473         else
1474                 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1475
1476         /* End of calibration, restore configuration */
1477         b43_nphy_classifier(dev, 7, class);
1478         b43_nphy_write_clip_detection(dev, clip_state);
1479 }
1480
1481 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1482 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1483 {
1484         int i, j;
1485         u8 state[4];
1486         u8 code, val;
1487         u16 class, override;
1488         u8 regs_save_radio[2];
1489         u16 regs_save_phy[2];
1490
1491         s8 offset[4];
1492         u8 core;
1493         u8 rail;
1494
1495         u16 clip_state[2];
1496         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1497         s32 results_min[4] = { };
1498         u8 vcm_final[4] = { };
1499         s32 results[4][4] = { };
1500         s32 miniq[4][2] = { };
1501
1502         if (type == 2) {
1503                 code = 0;
1504                 val = 6;
1505         } else if (type < 2) {
1506                 code = 25;
1507                 val = 4;
1508         } else {
1509                 B43_WARN_ON(1);
1510                 return;
1511         }
1512
1513         class = b43_nphy_classifier(dev, 0, 0);
1514         b43_nphy_classifier(dev, 7, 4);
1515         b43_nphy_read_clip_detection(dev, clip_state);
1516         b43_nphy_write_clip_detection(dev, clip_off);
1517
1518         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1519                 override = 0x140;
1520         else
1521                 override = 0x110;
1522
1523         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1524         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1525         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1526         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1527
1528         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1529         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1530         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1531         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1532
1533         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1534         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1535         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1536         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1537         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1538         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1539
1540         b43_nphy_rssi_select(dev, 5, type);
1541         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1542         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1543
1544         for (i = 0; i < 4; i++) {
1545                 u8 tmp[4];
1546                 for (j = 0; j < 4; j++)
1547                         tmp[j] = i;
1548                 if (type != 1)
1549                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1550                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1551                 if (type < 2)
1552                         for (j = 0; j < 2; j++)
1553                                 miniq[i][j] = min(results[i][2 * j],
1554                                                 results[i][2 * j + 1]);
1555         }
1556
1557         for (i = 0; i < 4; i++) {
1558                 s32 mind = 40;
1559                 u8 minvcm = 0;
1560                 s32 minpoll = 249;
1561                 s32 curr;
1562                 for (j = 0; j < 4; j++) {
1563                         if (type == 2)
1564                                 curr = abs(results[j][i]);
1565                         else
1566                                 curr = abs(miniq[j][i / 2] - code * 8);
1567
1568                         if (curr < mind) {
1569                                 mind = curr;
1570                                 minvcm = j;
1571                         }
1572
1573                         if (results[j][i] < minpoll)
1574                                 minpoll = results[j][i];
1575                 }
1576                 results_min[i] = minpoll;
1577                 vcm_final[i] = minvcm;
1578         }
1579
1580         if (type != 1)
1581                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1582
1583         for (i = 0; i < 4; i++) {
1584                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1585
1586                 if (offset[i] < 0)
1587                         offset[i] = -((abs(offset[i]) + 4) / 8);
1588                 else
1589                         offset[i] = (offset[i] + 4) / 8;
1590
1591                 if (results_min[i] == 248)
1592                         offset[i] = code - 32;
1593
1594                 core = (i / 2) ? 2 : 1;
1595                 rail = (i % 2) ? 1 : 0;
1596
1597                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1598                                                 type);
1599         }
1600
1601         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1602         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1603
1604         switch (state[2]) {
1605         case 1:
1606                 b43_nphy_rssi_select(dev, 1, 2);
1607                 break;
1608         case 4:
1609                 b43_nphy_rssi_select(dev, 1, 0);
1610                 break;
1611         case 2:
1612                 b43_nphy_rssi_select(dev, 1, 1);
1613                 break;
1614         default:
1615                 b43_nphy_rssi_select(dev, 1, 1);
1616                 break;
1617         }
1618
1619         switch (state[3]) {
1620         case 1:
1621                 b43_nphy_rssi_select(dev, 2, 2);
1622                 break;
1623         case 4:
1624                 b43_nphy_rssi_select(dev, 2, 0);
1625                 break;
1626         default:
1627                 b43_nphy_rssi_select(dev, 2, 1);
1628                 break;
1629         }
1630
1631         b43_nphy_rssi_select(dev, 0, type);
1632
1633         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1634         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1635         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1636         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1637
1638         b43_nphy_classifier(dev, 7, class);
1639         b43_nphy_write_clip_detection(dev, clip_state);
1640         /* Specs don't say about reset here, but it makes wl and b43 dumps
1641            identical, it really seems wl performs this */
1642         b43_nphy_reset_cca(dev);
1643 }
1644
1645 /*
1646  * RSSI Calibration
1647  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1648  */
1649 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1650 {
1651         if (dev->phy.rev >= 3) {
1652                 b43_nphy_rev3_rssi_cal(dev);
1653         } else {
1654                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
1655                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
1656                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
1657         }
1658 }
1659
1660 /**************************************************
1661  * Workarounds
1662  **************************************************/
1663
1664 static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1665 {
1666         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1667
1668         bool ghz5;
1669         bool ext_lna;
1670         u16 rssi_gain;
1671         struct nphy_gain_ctl_workaround_entry *e;
1672         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1673         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1674
1675         /* Prepare values */
1676         ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1677                 & B43_NPHY_BANDCTL_5GHZ;
1678         ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1679                 sprom->boardflags_lo & B43_BFL_EXTLNA;
1680         e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1681         if (ghz5 && dev->phy.rev >= 5)
1682                 rssi_gain = 0x90;
1683         else
1684                 rssi_gain = 0x50;
1685
1686         b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1687
1688         /* Set Clip 2 detect */
1689         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1690                         B43_NPHY_C1_CGAINI_CL2DETECT);
1691         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1692                         B43_NPHY_C2_CGAINI_CL2DETECT);
1693
1694         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1695                         0x17);
1696         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1697                         0x17);
1698         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1699         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1700         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1701         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1702         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1703                         rssi_gain);
1704         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1705                         rssi_gain);
1706         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1707                         0x17);
1708         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1709                         0x17);
1710         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1711         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1712
1713         b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1714         b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1715         b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1716         b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1717         b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1718         b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1719         b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1720         b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1721         b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1722         b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1723         b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1724         b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1725
1726         b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1727         b43_phy_write(dev, 0x2A7, e->init_gain);
1728         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1729                                 e->rfseq_init);
1730
1731         /* TODO: check defines. Do not match variables names */
1732         b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1733         b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1734         b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1735         b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1736         b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1737         b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1738
1739         b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1740         b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1741         b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1742         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1743         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1744         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1745                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1746         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1747                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1748         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1749 }
1750
1751 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
1752 {
1753         struct b43_phy_n *nphy = dev->phy.n;
1754
1755         u8 i, j;
1756         u8 code;
1757         u16 tmp;
1758         u8 rfseq_events[3] = { 6, 8, 7 };
1759         u8 rfseq_delays[3] = { 10, 30, 1 };
1760
1761         /* Set Clip 2 detect */
1762         b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1763         b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
1764
1765         /* Set narrowband clip threshold */
1766         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1767         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1768
1769         if (!dev->phy.is_40mhz) {
1770                 /* Set dwell lengths */
1771                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1772                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1773                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1774                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1775         }
1776
1777         /* Set wideband clip 2 threshold */
1778         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1779                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
1780         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1781                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
1782
1783         if (!dev->phy.is_40mhz) {
1784                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1785                         ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1786                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1787                         ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1788                 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1789                         ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1790                 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1791                         ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1792         }
1793
1794         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1795
1796         if (nphy->gain_boost) {
1797                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1798                         dev->phy.is_40mhz)
1799                         code = 4;
1800                 else
1801                         code = 5;
1802         } else {
1803                 code = dev->phy.is_40mhz ? 6 : 7;
1804         }
1805
1806         /* Set HPVGA2 index */
1807         b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
1808                         code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1809         b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
1810                         code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1811
1812         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1813         /* specs say about 2 loops, but wl does 4 */
1814         for (i = 0; i < 4; i++)
1815                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
1816
1817         b43_nphy_adjust_lna_gain_table(dev);
1818
1819         if (nphy->elna_gain_config) {
1820                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1821                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1822                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1823                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1824                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1825
1826                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1827                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1828                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1829                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1830                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1831
1832                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1833                 /* specs say about 2 loops, but wl does 4 */
1834                 for (i = 0; i < 4; i++)
1835                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1836                                                 (code << 8 | 0x74));
1837         }
1838
1839         if (dev->phy.rev == 2) {
1840                 for (i = 0; i < 4; i++) {
1841                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1842                                         (0x0400 * i) + 0x0020);
1843                         for (j = 0; j < 21; j++) {
1844                                 tmp = j * (i < 2 ? 3 : 1);
1845                                 b43_phy_write(dev,
1846                                         B43_NPHY_TABLE_DATALO, tmp);
1847                         }
1848                 }
1849         }
1850
1851         b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
1852         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1853                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1854                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1855
1856         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1857                 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
1858 }
1859
1860 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1861 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
1862 {
1863         if (dev->phy.rev >= 3)
1864                 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
1865         else
1866                 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
1867 }
1868
1869 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1870 {
1871         struct b43_phy_n *nphy = dev->phy.n;
1872         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1873
1874         /* TX to RX */
1875         u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
1876         u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
1877         /* RX to TX */
1878         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
1879                                         0x1F };
1880         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
1881         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
1882         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
1883
1884         u16 tmp16;
1885         u32 tmp32;
1886
1887         b43_phy_write(dev, 0x23f, 0x1f8);
1888         b43_phy_write(dev, 0x240, 0x1f8);
1889
1890         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1891         tmp32 &= 0xffffff;
1892         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1893
1894         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1895         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1896         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1897         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1898         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1899         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1900
1901         b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1902         b43_phy_write(dev, 0x2AE, 0x000C);
1903
1904         /* TX to RX */
1905         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
1906                                  ARRAY_SIZE(tx2rx_events));
1907
1908         /* RX to TX */
1909         if (b43_nphy_ipa(dev))
1910                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
1911                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
1912         if (nphy->hw_phyrxchain != 3 &&
1913             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
1914                 if (b43_nphy_ipa(dev)) {
1915                         rx2tx_delays[5] = 59;
1916                         rx2tx_delays[6] = 1;
1917                         rx2tx_events[7] = 0x1F;
1918                 }
1919                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
1920                                          ARRAY_SIZE(rx2tx_events));
1921         }
1922
1923         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1924                 0x2 : 0x9C40;
1925         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1926
1927         b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1928
1929         if (!dev->phy.is_40mhz) {
1930                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1931                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1932         } else {
1933                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
1934                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
1935         }
1936
1937         b43_nphy_gain_ctl_workarounds(dev);
1938
1939         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
1940         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
1941
1942         /* TODO */
1943
1944         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1945         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1946         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1947         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1948         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1949         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1950         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1951         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1952         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1953         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1954         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1955         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1956
1957         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1958
1959         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1960              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1961             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1962              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1963                 tmp32 = 0x00088888;
1964         else
1965                 tmp32 = 0x88888888;
1966         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1967         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1968         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1969
1970         if (dev->phy.rev == 4 &&
1971             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1972                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1973                                 0x70);
1974                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1975                                 0x70);
1976         }
1977
1978         /* Dropped probably-always-true condition */
1979         b43_phy_write(dev, 0x224, 0x03eb);
1980         b43_phy_write(dev, 0x225, 0x03eb);
1981         b43_phy_write(dev, 0x226, 0x0341);
1982         b43_phy_write(dev, 0x227, 0x0341);
1983         b43_phy_write(dev, 0x228, 0x042b);
1984         b43_phy_write(dev, 0x229, 0x042b);
1985         b43_phy_write(dev, 0x22a, 0x0381);
1986         b43_phy_write(dev, 0x22b, 0x0381);
1987         b43_phy_write(dev, 0x22c, 0x042b);
1988         b43_phy_write(dev, 0x22d, 0x042b);
1989         b43_phy_write(dev, 0x22e, 0x0381);
1990         b43_phy_write(dev, 0x22f, 0x0381);
1991
1992         if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
1993                 ; /* TODO: 0x0080000000000000 HF */
1994 }
1995
1996 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
1997 {
1998         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1999         struct b43_phy *phy = &dev->phy;
2000         struct b43_phy_n *nphy = phy->n;
2001
2002         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2003         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
2004
2005         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2006         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2007
2008         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2009             dev->dev->board_type == 0x8B) {
2010                 delays1[0] = 0x1;
2011                 delays1[5] = 0x14;
2012         }
2013
2014         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2015             nphy->band5g_pwrgain) {
2016                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2017                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2018         } else {
2019                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2020                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2021         }
2022
2023         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2024         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2025         if (dev->phy.rev < 3) {
2026                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2027                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2028         }
2029
2030         if (dev->phy.rev < 2) {
2031                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2032                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2033                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2034                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2035                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2036                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2037         }
2038
2039         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2040         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2041         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2042         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2043
2044         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2045         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2046
2047         b43_nphy_gain_ctl_workarounds(dev);
2048
2049         if (dev->phy.rev < 2) {
2050                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2051                         b43_hf_write(dev, b43_hf_read(dev) |
2052                                         B43_HF_MLADVW);
2053         } else if (dev->phy.rev == 2) {
2054                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2055                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2056         }
2057
2058         if (dev->phy.rev < 2)
2059                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2060                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2061
2062         /* Set phase track alpha and beta */
2063         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2064         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2065         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2066         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2067         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2068         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2069
2070         if (dev->phy.rev < 3) {
2071                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2072                              ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2073                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2074                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2075                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2076         }
2077
2078         if (dev->phy.rev == 2)
2079                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2080                                 B43_NPHY_FINERX2_CGC_DECGC);
2081 }
2082
2083 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2084 static void b43_nphy_workarounds(struct b43_wldev *dev)
2085 {
2086         struct b43_phy *phy = &dev->phy;
2087         struct b43_phy_n *nphy = phy->n;
2088
2089         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2090                 b43_nphy_classifier(dev, 1, 0);
2091         else
2092                 b43_nphy_classifier(dev, 1, 1);
2093
2094         if (nphy->hang_avoid)
2095                 b43_nphy_stay_in_carrier_search(dev, 1);
2096
2097         b43_phy_set(dev, B43_NPHY_IQFLIP,
2098                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2099
2100         if (dev->phy.rev >= 3)
2101                 b43_nphy_workarounds_rev3plus(dev);
2102         else
2103                 b43_nphy_workarounds_rev1_2(dev);
2104
2105         if (nphy->hang_avoid)
2106                 b43_nphy_stay_in_carrier_search(dev, 0);
2107 }
2108
2109 /**************************************************
2110  * Tx/Rx common
2111  **************************************************/
2112
2113 /*
2114  * Transmits a known value for LO calibration
2115  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2116  */
2117 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2118                                 bool iqmode, bool dac_test)
2119 {
2120         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2121         if (samp == 0)
2122                 return -1;
2123         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2124         return 0;
2125 }
2126
2127 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2128 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2129 {
2130         struct b43_phy_n *nphy = dev->phy.n;
2131
2132         bool override = false;
2133         u16 chain = 0x33;
2134
2135         if (nphy->txrx_chain == 0) {
2136                 chain = 0x11;
2137                 override = true;
2138         } else if (nphy->txrx_chain == 1) {
2139                 chain = 0x22;
2140                 override = true;
2141         }
2142
2143         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2144                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2145                         chain);
2146
2147         if (override)
2148                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2149                                 B43_NPHY_RFSEQMODE_CAOVER);
2150         else
2151                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2152                                 ~B43_NPHY_RFSEQMODE_CAOVER);
2153 }
2154
2155 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2156 static void b43_nphy_stop_playback(struct b43_wldev *dev)
2157 {
2158         struct b43_phy_n *nphy = dev->phy.n;
2159         u16 tmp;
2160
2161         if (nphy->hang_avoid)
2162                 b43_nphy_stay_in_carrier_search(dev, 1);
2163
2164         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2165         if (tmp & 0x1)
2166                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2167         else if (tmp & 0x2)
2168                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2169
2170         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2171
2172         if (nphy->bb_mult_save & 0x80000000) {
2173                 tmp = nphy->bb_mult_save & 0xFFFF;
2174                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2175                 nphy->bb_mult_save = 0;
2176         }
2177
2178         if (nphy->hang_avoid)
2179                 b43_nphy_stay_in_carrier_search(dev, 0);
2180 }
2181
2182 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2183 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2184                                         struct nphy_txgains target,
2185                                         struct nphy_iqcal_params *params)
2186 {
2187         int i, j, indx;
2188         u16 gain;
2189
2190         if (dev->phy.rev >= 3) {
2191                 params->txgm = target.txgm[core];
2192                 params->pga = target.pga[core];
2193                 params->pad = target.pad[core];
2194                 params->ipa = target.ipa[core];
2195                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2196                                         (params->pad << 4) | (params->ipa);
2197                 for (j = 0; j < 5; j++)
2198                         params->ncorr[j] = 0x79;
2199         } else {
2200                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2201                         (target.txgm[core] << 8);
2202
2203                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2204                         1 : 0;
2205                 for (i = 0; i < 9; i++)
2206                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2207                                 break;
2208                 i = min(i, 8);
2209
2210                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2211                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2212                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2213                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2214                                         (params->pad << 2);
2215                 for (j = 0; j < 4; j++)
2216                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2217         }
2218 }
2219
2220 /**************************************************
2221  * Tx and Rx
2222  **************************************************/
2223
2224 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
2225 {//TODO
2226 }
2227
2228 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2229 {//TODO
2230 }
2231
2232 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2233                                                         bool ignore_tssi)
2234 {//TODO
2235         return B43_TXPWR_RES_DONE;
2236 }
2237
2238 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2239 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2240 {
2241         struct b43_phy_n *nphy = dev->phy.n;
2242         u8 i;
2243         u16 bmask, val, tmp;
2244         enum ieee80211_band band = b43_current_band(dev->wl);
2245
2246         if (nphy->hang_avoid)
2247                 b43_nphy_stay_in_carrier_search(dev, 1);
2248
2249         nphy->txpwrctrl = enable;
2250         if (!enable) {
2251                 if (dev->phy.rev >= 3 &&
2252                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2253                      (B43_NPHY_TXPCTL_CMD_COEFF |
2254                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2255                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2256                         /* We disable enabled TX pwr ctl, save it's state */
2257                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2258                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2259                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2260                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2261                 }
2262
2263                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2264                 for (i = 0; i < 84; i++)
2265                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2266
2267                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2268                 for (i = 0; i < 84; i++)
2269                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2270
2271                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2272                 if (dev->phy.rev >= 3)
2273                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2274                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
2275
2276                 if (dev->phy.rev >= 3) {
2277                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2278                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2279                 } else {
2280                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2281                 }
2282
2283                 if (dev->phy.rev == 2)
2284                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2285                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2286                 else if (dev->phy.rev < 2)
2287                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2288                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
2289
2290                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2291                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
2292         } else {
2293                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2294                                     nphy->adj_pwr_tbl);
2295                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2296                                     nphy->adj_pwr_tbl);
2297
2298                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2299                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2300                 /* wl does useless check for "enable" param here */
2301                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2302                 if (dev->phy.rev >= 3) {
2303                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2304                         if (val)
2305                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2306                 }
2307                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
2308
2309                 if (band == IEEE80211_BAND_5GHZ) {
2310                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2311                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2312                         if (dev->phy.rev > 1)
2313                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2314                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2315                                                 0x64);
2316                 }
2317
2318                 if (dev->phy.rev >= 3) {
2319                         if (nphy->tx_pwr_idx[0] != 128 &&
2320                             nphy->tx_pwr_idx[1] != 128) {
2321                                 /* Recover TX pwr ctl state */
2322                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2323                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
2324                                                 nphy->tx_pwr_idx[0]);
2325                                 if (dev->phy.rev > 1)
2326                                         b43_phy_maskset(dev,
2327                                                 B43_NPHY_TXPCTL_INIT,
2328                                                 ~0xff, nphy->tx_pwr_idx[1]);
2329                         }
2330                 }
2331
2332                 if (dev->phy.rev >= 3) {
2333                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2334                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2335                 } else {
2336                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2337                 }
2338
2339                 if (dev->phy.rev == 2)
2340                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2341                 else if (dev->phy.rev < 2)
2342                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
2343
2344                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2345                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
2346
2347                 if (b43_nphy_ipa(dev)) {
2348                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2349                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
2350                 }
2351         }
2352
2353         if (nphy->hang_avoid)
2354                 b43_nphy_stay_in_carrier_search(dev, 0);
2355 }
2356
2357 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
2358 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
2359 {
2360         struct b43_phy_n *nphy = dev->phy.n;
2361         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2362
2363         u8 txpi[2], bbmult, i;
2364         u16 tmp, radio_gain, dac_gain;
2365         u16 freq = dev->phy.channel_freq;
2366         u32 txgain;
2367         /* u32 gaintbl; rev3+ */
2368
2369         if (nphy->hang_avoid)
2370                 b43_nphy_stay_in_carrier_search(dev, 1);
2371
2372         if (dev->phy.rev >= 7) {
2373                 txpi[0] = txpi[1] = 30;
2374         } else if (dev->phy.rev >= 3) {
2375                 txpi[0] = 40;
2376                 txpi[1] = 40;
2377         } else if (sprom->revision < 4) {
2378                 txpi[0] = 72;
2379                 txpi[1] = 72;
2380         } else {
2381                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2382                         txpi[0] = sprom->txpid2g[0];
2383                         txpi[1] = sprom->txpid2g[1];
2384                 } else if (freq >= 4900 && freq < 5100) {
2385                         txpi[0] = sprom->txpid5gl[0];
2386                         txpi[1] = sprom->txpid5gl[1];
2387                 } else if (freq >= 5100 && freq < 5500) {
2388                         txpi[0] = sprom->txpid5g[0];
2389                         txpi[1] = sprom->txpid5g[1];
2390                 } else if (freq >= 5500) {
2391                         txpi[0] = sprom->txpid5gh[0];
2392                         txpi[1] = sprom->txpid5gh[1];
2393                 } else {
2394                         txpi[0] = 91;
2395                         txpi[1] = 91;
2396                 }
2397         }
2398         if (dev->phy.rev < 7 &&
2399             (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
2400                 txpi[0] = txpi[1] = 91;
2401
2402         /*
2403         for (i = 0; i < 2; i++) {
2404                 nphy->txpwrindex[i].index_internal = txpi[i];
2405                 nphy->txpwrindex[i].index_internal_save = txpi[i];
2406         }
2407         */
2408
2409         for (i = 0; i < 2; i++) {
2410                 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
2411
2412                 if (dev->phy.rev >= 3)
2413                         radio_gain = (txgain >> 16) & 0x1FFFF;
2414                 else
2415                         radio_gain = (txgain >> 16) & 0x1FFF;
2416
2417                 if (dev->phy.rev >= 7)
2418                         dac_gain = (txgain >> 8) & 0x7;
2419                 else
2420                         dac_gain = (txgain >> 8) & 0x3F;
2421                 bbmult = txgain & 0xFF;
2422
2423                 if (dev->phy.rev >= 3) {
2424                         if (i == 0)
2425                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2426                         else
2427                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2428                 } else {
2429                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2430                 }
2431
2432                 if (i == 0)
2433                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
2434                 else
2435                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
2436
2437                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
2438
2439                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
2440                 if (i == 0)
2441                         tmp = (tmp & 0x00FF) | (bbmult << 8);
2442                 else
2443                         tmp = (tmp & 0xFF00) | bbmult;
2444                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
2445
2446                 if (b43_nphy_ipa(dev)) {
2447                         u32 tmp32;
2448                         u16 reg = (i == 0) ?
2449                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
2450                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
2451                                                               576 + txpi[i]));
2452                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
2453                         b43_phy_set(dev, reg, 0x4);
2454                 }
2455         }
2456
2457         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
2458
2459         if (nphy->hang_avoid)
2460                 b43_nphy_stay_in_carrier_search(dev, 0);
2461 }
2462
2463 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
2464 {
2465         struct b43_phy *phy = &dev->phy;
2466
2467         u8 core;
2468         u16 r; /* routing */
2469
2470         if (phy->rev >= 7) {
2471                 for (core = 0; core < 2; core++) {
2472                         r = core ? 0x190 : 0x170;
2473                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2474                                 b43_radio_write(dev, r + 0x5, 0x5);
2475                                 b43_radio_write(dev, r + 0x9, 0xE);
2476                                 if (phy->rev != 5)
2477                                         b43_radio_write(dev, r + 0xA, 0);
2478                                 if (phy->rev != 7)
2479                                         b43_radio_write(dev, r + 0xB, 1);
2480                                 else
2481                                         b43_radio_write(dev, r + 0xB, 0x31);
2482                         } else {
2483                                 b43_radio_write(dev, r + 0x5, 0x9);
2484                                 b43_radio_write(dev, r + 0x9, 0xC);
2485                                 b43_radio_write(dev, r + 0xB, 0x0);
2486                                 if (phy->rev != 5)
2487                                         b43_radio_write(dev, r + 0xA, 1);
2488                                 else
2489                                         b43_radio_write(dev, r + 0xA, 0x31);
2490                         }
2491                         b43_radio_write(dev, r + 0x6, 0);
2492                         b43_radio_write(dev, r + 0x7, 0);
2493                         b43_radio_write(dev, r + 0x8, 3);
2494                         b43_radio_write(dev, r + 0xC, 0);
2495                 }
2496         } else {
2497                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2498                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
2499                 else
2500                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
2501                 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
2502                 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
2503
2504                 for (core = 0; core < 2; core++) {
2505                         r = core ? B2056_TX1 : B2056_TX0;
2506
2507                         b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
2508                         b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
2509                         b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
2510                         b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
2511                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
2512                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
2513                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
2514                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2515                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
2516                                                 0x5);
2517                                 if (phy->rev != 5)
2518                                         b43_radio_write(dev, r | B2056_TX_TSSIA,
2519                                                         0x00);
2520                                 if (phy->rev >= 5)
2521                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
2522                                                         0x31);
2523                                 else
2524                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
2525                                                         0x11);
2526                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
2527                                                 0xE);
2528                         } else {
2529                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
2530                                                 0x9);
2531                                 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
2532                                 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
2533                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
2534                                                 0xC);
2535                         }
2536                 }
2537         }
2538 }
2539
2540 /*
2541  * Stop radio and transmit known signal. Then check received signal strength to
2542  * get TSSI (Transmit Signal Strength Indicator).
2543  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
2544  */
2545 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
2546 {
2547         struct b43_phy *phy = &dev->phy;
2548         struct b43_phy_n *nphy = dev->phy.n;
2549
2550         u32 tmp;
2551         s32 rssi[4] = { };
2552
2553         /* TODO: check if we can transmit */
2554
2555         if (b43_nphy_ipa(dev))
2556                 b43_nphy_ipa_internal_tssi_setup(dev);
2557
2558         if (phy->rev >= 7)
2559                 ; /* TODO: Override Rev7 with 0x2000, 0, 3, 0, 0 as arguments */
2560         else if (phy->rev >= 3)
2561                 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
2562
2563         b43_nphy_stop_playback(dev);
2564         b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
2565         udelay(20);
2566         tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1);
2567         b43_nphy_stop_playback(dev);
2568         b43_nphy_rssi_select(dev, 0, 0);
2569
2570         if (phy->rev >= 7)
2571                 ; /* TODO: Override Rev7 with 0x2000, 0, 3, 1, 0 as arguments */
2572         else if (phy->rev >= 3)
2573                 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
2574
2575         if (phy->rev >= 3) {
2576                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
2577                 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
2578         } else {
2579                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
2580                 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
2581         }
2582         nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
2583         nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
2584 }
2585
2586 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
2587 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
2588 {
2589         struct b43_phy_n *nphy = dev->phy.n;
2590
2591         u8 idx, delta;
2592         u8 i, stf_mode;
2593
2594         for (i = 0; i < 4; i++)
2595                 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
2596
2597         for (stf_mode = 0; stf_mode < 4; stf_mode++) {
2598                 delta = 0;
2599                 switch (stf_mode) {
2600                 case 0:
2601                         if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
2602                                 idx = 68;
2603                         } else {
2604                                 delta = 1;
2605                                 idx = dev->phy.is_40mhz ? 52 : 4;
2606                         }
2607                         break;
2608                 case 1:
2609                         idx = dev->phy.is_40mhz ? 76 : 28;
2610                         break;
2611                 case 2:
2612                         idx = dev->phy.is_40mhz ? 84 : 36;
2613                         break;
2614                 case 3:
2615                         idx = dev->phy.is_40mhz ? 92 : 44;
2616                         break;
2617                 }
2618
2619                 for (i = 0; i < 20; i++) {
2620                         nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
2621                                 nphy->tx_power_offset[idx];
2622                         if (i == 0)
2623                                 idx += delta;
2624                         if (i == 14)
2625                                 idx += 1 - delta;
2626                         if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
2627                             i == 13)
2628                                 idx += 1;
2629                 }
2630         }
2631 }
2632
2633 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
2634 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
2635 {
2636         struct b43_phy_n *nphy = dev->phy.n;
2637         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2638
2639         s16 a1[2], b0[2], b1[2];
2640         u8 idle[2];
2641         s8 target[2];
2642         s32 num, den, pwr;
2643         u32 regval[64];
2644
2645         u16 freq = dev->phy.channel_freq;
2646         u16 tmp;
2647         u16 r; /* routing */
2648         u8 i, c;
2649
2650         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
2651                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
2652                 b43_read32(dev, B43_MMIO_MACCTL);
2653                 udelay(1);
2654         }
2655
2656         if (nphy->hang_avoid)
2657                 b43_nphy_stay_in_carrier_search(dev, true);
2658
2659         b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
2660         if (dev->phy.rev >= 3)
2661                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
2662                              ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
2663         else
2664                 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
2665                             B43_NPHY_TXPCTL_CMD_PCTLEN);
2666
2667         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
2668                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
2669
2670         if (sprom->revision < 4) {
2671                 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
2672                 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
2673                 target[0] = target[1] = 52;
2674                 a1[0] = a1[1] = -424;
2675                 b0[0] = b0[1] = 5612;
2676                 b1[0] = b1[1] = -1393;
2677         } else {
2678                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2679                         for (c = 0; c < 2; c++) {
2680                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
2681                                 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
2682                                 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
2683                                 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
2684                                 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
2685                         }
2686                 } else if (freq >= 4900 && freq < 5100) {
2687                         for (c = 0; c < 2; c++) {
2688                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
2689                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
2690                                 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
2691                                 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
2692                                 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
2693                         }
2694                 } else if (freq >= 5100 && freq < 5500) {
2695                         for (c = 0; c < 2; c++) {
2696                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
2697                                 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
2698                                 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
2699                                 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
2700                                 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
2701                         }
2702                 } else if (freq >= 5500) {
2703                         for (c = 0; c < 2; c++) {
2704                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
2705                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
2706                                 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
2707                                 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
2708                                 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
2709                         }
2710                 } else {
2711                         idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
2712                         idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
2713                         target[0] = target[1] = 52;
2714                         a1[0] = a1[1] = -424;
2715                         b0[0] = b0[1] = 5612;
2716                         b1[0] = b1[1] = -1393;
2717                 }
2718         }
2719         /* target[0] = target[1] = nphy->tx_power_max; */
2720
2721         if (dev->phy.rev >= 3) {
2722                 if (sprom->fem.ghz2.tssipos)
2723                         b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
2724                 if (dev->phy.rev >= 7) {
2725                         for (c = 0; c < 2; c++) {
2726                                 r = c ? 0x190 : 0x170;
2727                                 if (b43_nphy_ipa(dev))
2728                                         b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
2729                         }
2730                 } else {
2731                         if (b43_nphy_ipa(dev)) {
2732                                 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2733                                 b43_radio_write(dev,
2734                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
2735                                 b43_radio_write(dev,
2736                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
2737                         } else {
2738                                 b43_radio_write(dev,
2739                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
2740                                 b43_radio_write(dev,
2741                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
2742                         }
2743                 }
2744         }
2745
2746         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
2747                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
2748                 b43_read32(dev, B43_MMIO_MACCTL);
2749                 udelay(1);
2750         }
2751
2752         if (dev->phy.rev >= 7) {
2753                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2754                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
2755                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2756                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
2757         } else {
2758                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2759                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
2760                 if (dev->phy.rev > 1)
2761                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2762                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
2763         }
2764
2765         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
2766                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
2767
2768         b43_phy_write(dev, B43_NPHY_TXPCTL_N,
2769                       0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
2770                       3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
2771         b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
2772                       idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
2773                       idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
2774                       B43_NPHY_TXPCTL_ITSSI_BINF);
2775         b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
2776                       target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
2777                       target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
2778
2779         for (c = 0; c < 2; c++) {
2780                 for (i = 0; i < 64; i++) {
2781                         num = 8 * (16 * b0[c] + b1[c] * i);
2782                         den = 32768 + a1[c] * i;
2783                         pwr = max((4 * num + den / 2) / den, -8);
2784                         if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
2785                                 pwr = max(pwr, target[c] + 1);
2786                         regval[i] = pwr;
2787                 }
2788                 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
2789         }
2790
2791         b43_nphy_tx_prepare_adjusted_power_table(dev);
2792         /*
2793         b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
2794         b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
2795         */
2796
2797         if (nphy->hang_avoid)
2798                 b43_nphy_stay_in_carrier_search(dev, false);
2799 }
2800
2801 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
2802 {
2803         struct b43_phy *phy = &dev->phy;
2804
2805         const u32 *table = NULL;
2806         u32 rfpwr_offset;
2807         u8 pga_gain;
2808         int i;
2809
2810         table = b43_nphy_get_tx_gain_table(dev);
2811         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
2812         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
2813
2814         if (phy->rev >= 3) {
2815 #if 0
2816                 nphy->gmval = (table[0] >> 16) & 0x7000;
2817 #endif
2818
2819                 for (i = 0; i < 128; i++) {
2820                         pga_gain = (table[i] >> 24) & 0xF;
2821                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2822                                 rfpwr_offset =
2823                                  b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
2824                         else
2825                                 rfpwr_offset =
2826                                  0; /* FIXME */
2827                         b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
2828                                        rfpwr_offset);
2829                         b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
2830                                        rfpwr_offset);
2831                 }
2832         }
2833 }
2834
2835 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
2836 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
2837 {
2838         struct b43_phy_n *nphy = dev->phy.n;
2839         enum ieee80211_band band;
2840         u16 tmp;
2841
2842         if (!enable) {
2843                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
2844                                                        B43_NPHY_RFCTL_INTC1);
2845                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
2846                                                        B43_NPHY_RFCTL_INTC2);
2847                 band = b43_current_band(dev->wl);
2848                 if (dev->phy.rev >= 3) {
2849                         if (band == IEEE80211_BAND_5GHZ)
2850                                 tmp = 0x600;
2851                         else
2852                                 tmp = 0x480;
2853                 } else {
2854                         if (band == IEEE80211_BAND_5GHZ)
2855                                 tmp = 0x180;
2856                         else
2857                                 tmp = 0x120;
2858                 }
2859                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2860                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2861         } else {
2862                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
2863                                 nphy->rfctrl_intc1_save);
2864                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
2865                                 nphy->rfctrl_intc2_save);
2866         }
2867 }
2868
2869 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
2870 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
2871 {
2872         u16 tmp;
2873
2874         if (dev->phy.rev >= 3) {
2875                 if (b43_nphy_ipa(dev)) {
2876                         tmp = 4;
2877                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
2878                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
2879                 }
2880
2881                 tmp = 1;
2882                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
2883                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
2884         }
2885 }
2886
2887 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
2888 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
2889                                 u16 samps, u8 time, bool wait)
2890 {
2891         int i;
2892         u16 tmp;
2893
2894         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
2895         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
2896         if (wait)
2897                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
2898         else
2899                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
2900
2901         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
2902
2903         for (i = 1000; i; i--) {
2904                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
2905                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
2906                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
2907                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
2908                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
2909                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
2910                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
2911                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
2912
2913                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
2914                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
2915                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
2916                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
2917                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
2918                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
2919                         return;
2920                 }
2921                 udelay(10);
2922         }
2923         memset(est, 0, sizeof(*est));
2924 }
2925
2926 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
2927 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
2928                                         struct b43_phy_n_iq_comp *pcomp)
2929 {
2930         if (write) {
2931                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
2932                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
2933                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
2934                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
2935         } else {
2936                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
2937                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
2938                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
2939                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
2940         }
2941 }
2942
2943 #if 0
2944 /* Ready but not used anywhere */
2945 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
2946 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
2947 {
2948         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2949
2950         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
2951         if (core == 0) {
2952                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
2953                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2954         } else {
2955                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2956                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2957         }
2958         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
2959         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
2960         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
2961         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
2962         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
2963         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
2964         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2965         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2966 }
2967
2968 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
2969 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
2970 {
2971         u8 rxval, txval;
2972         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2973
2974         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2975         if (core == 0) {
2976                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2977                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2978         } else {
2979                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2980                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2981         }
2982         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2983         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2984         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2985         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2986         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
2987         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2988         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2989         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2990
2991         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2992         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2993
2994         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2995                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
2996                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2997         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2998                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
2999         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3000                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3001         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3002                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
3003
3004         if (core == 0) {
3005                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3006                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3007         } else {
3008                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3009                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3010         }
3011
3012         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
3013         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
3014         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3015
3016         if (core == 0) {
3017                 rxval = 1;
3018                 txval = 8;
3019         } else {
3020                 rxval = 4;
3021                 txval = 2;
3022         }
3023         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
3024         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
3025 }
3026 #endif
3027
3028 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3029 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
3030 {
3031         int i;
3032         s32 iq;
3033         u32 ii;
3034         u32 qq;
3035         int iq_nbits, qq_nbits;
3036         int arsh, brsh;
3037         u16 tmp, a, b;
3038
3039         struct nphy_iq_est est;
3040         struct b43_phy_n_iq_comp old;
3041         struct b43_phy_n_iq_comp new = { };
3042         bool error = false;
3043
3044         if (mask == 0)
3045                 return;
3046
3047         b43_nphy_rx_iq_coeffs(dev, false, &old);
3048         b43_nphy_rx_iq_coeffs(dev, true, &new);
3049         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3050         new = old;
3051
3052         for (i = 0; i < 2; i++) {
3053                 if (i == 0 && (mask & 1)) {
3054                         iq = est.iq0_prod;
3055                         ii = est.i0_pwr;
3056                         qq = est.q0_pwr;
3057                 } else if (i == 1 && (mask & 2)) {
3058                         iq = est.iq1_prod;
3059                         ii = est.i1_pwr;
3060                         qq = est.q1_pwr;
3061                 } else {
3062                         continue;
3063                 }
3064
3065                 if (ii + qq < 2) {
3066                         error = true;
3067                         break;
3068                 }
3069
3070                 iq_nbits = fls(abs(iq));
3071                 qq_nbits = fls(qq);
3072
3073                 arsh = iq_nbits - 20;
3074                 if (arsh >= 0) {
3075                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3076                         tmp = ii >> arsh;
3077                 } else {
3078                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3079                         tmp = ii << -arsh;
3080                 }
3081                 if (tmp == 0) {
3082                         error = true;
3083                         break;
3084                 }
3085                 a /= tmp;
3086
3087                 brsh = qq_nbits - 11;
3088                 if (brsh >= 0) {
3089                         b = (qq << (31 - qq_nbits));
3090                         tmp = ii >> brsh;
3091                 } else {
3092                         b = (qq << (31 - qq_nbits));
3093                         tmp = ii << -brsh;
3094                 }
3095                 if (tmp == 0) {
3096                         error = true;
3097                         break;
3098                 }
3099                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
3100
3101                 if (i == 0 && (mask & 0x1)) {
3102                         if (dev->phy.rev >= 3) {
3103                                 new.a0 = a & 0x3FF;
3104                                 new.b0 = b & 0x3FF;
3105                         } else {
3106                                 new.a0 = b & 0x3FF;
3107                                 new.b0 = a & 0x3FF;
3108                         }
3109                 } else if (i == 1 && (mask & 0x2)) {
3110                         if (dev->phy.rev >= 3) {
3111                                 new.a1 = a & 0x3FF;
3112                                 new.b1 = b & 0x3FF;
3113                         } else {
3114                                 new.a1 = b & 0x3FF;
3115                                 new.b1 = a & 0x3FF;
3116                         }
3117                 }
3118         }
3119
3120         if (error)
3121                 new = old;
3122
3123         b43_nphy_rx_iq_coeffs(dev, true, &new);
3124 }
3125
3126 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3127 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3128 {
3129         u16 array[4];
3130         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
3131
3132         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3133         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3134         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3135         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
3136 }
3137
3138 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3139 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3140 {
3141         struct b43_phy_n *nphy = dev->phy.n;
3142
3143         u8 channel = dev->phy.channel;
3144         int tone[2] = { 57, 58 };
3145         u32 noise[2] = { 0x3FF, 0x3FF };
3146
3147         B43_WARN_ON(dev->phy.rev < 3);
3148
3149         if (nphy->hang_avoid)
3150                 b43_nphy_stay_in_carrier_search(dev, 1);
3151
3152         if (nphy->gband_spurwar_en) {
3153                 /* TODO: N PHY Adjust Analog Pfbw (7) */
3154                 if (channel == 11 && dev->phy.is_40mhz)
3155                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3156                 else
3157                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3158                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
3159         }
3160
3161         if (nphy->aband_spurwar_en) {
3162                 if (channel == 54) {
3163                         tone[0] = 0x20;
3164                         noise[0] = 0x25F;
3165                 } else if (channel == 38 || channel == 102 || channel == 118) {
3166                         if (0 /* FIXME */) {
3167                                 tone[0] = 0x20;
3168                                 noise[0] = 0x21F;
3169                         } else {
3170                                 tone[0] = 0;
3171                                 noise[0] = 0;
3172                         }
3173                 } else if (channel == 134) {
3174                         tone[0] = 0x20;
3175                         noise[0] = 0x21F;
3176                 } else if (channel == 151) {
3177                         tone[0] = 0x10;
3178                         noise[0] = 0x23F;
3179                 } else if (channel == 153 || channel == 161) {
3180                         tone[0] = 0x30;
3181                         noise[0] = 0x23F;
3182                 } else {
3183                         tone[0] = 0;
3184                         noise[0] = 0;
3185                 }
3186
3187                 if (!tone[0] && !noise[0])
3188                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
3189                 else
3190                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3191         }
3192
3193         if (nphy->hang_avoid)
3194                 b43_nphy_stay_in_carrier_search(dev, 0);
3195 }
3196
3197 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3198 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3199 {
3200         struct b43_phy_n *nphy = dev->phy.n;
3201         int i, j;
3202         u32 tmp;
3203         u32 cur_real, cur_imag, real_part, imag_part;
3204
3205         u16 buffer[7];
3206
3207         if (nphy->hang_avoid)
3208                 b43_nphy_stay_in_carrier_search(dev, true);
3209
3210         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3211
3212         for (i = 0; i < 2; i++) {
3213                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3214                         (buffer[i * 2 + 1] & 0x3FF);
3215                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3216                                 (((i + 26) << 10) | 320));
3217                 for (j = 0; j < 128; j++) {
3218                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3219                                         ((tmp >> 16) & 0xFFFF));
3220                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3221                                         (tmp & 0xFFFF));
3222                 }
3223         }
3224
3225         for (i = 0; i < 2; i++) {
3226                 tmp = buffer[5 + i];
3227                 real_part = (tmp >> 8) & 0xFF;
3228                 imag_part = (tmp & 0xFF);
3229                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3230                                 (((i + 26) << 10) | 448));
3231
3232                 if (dev->phy.rev >= 3) {
3233                         cur_real = real_part;
3234                         cur_imag = imag_part;
3235                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3236                 }
3237
3238                 for (j = 0; j < 128; j++) {
3239                         if (dev->phy.rev < 3) {
3240                                 cur_real = (real_part * loscale[j] + 128) >> 8;
3241                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3242                                 tmp = ((cur_real & 0xFF) << 8) |
3243                                         (cur_imag & 0xFF);
3244                         }
3245                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3246                                         ((tmp >> 16) & 0xFFFF));
3247                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3248                                         (tmp & 0xFFFF));
3249                 }
3250         }
3251
3252         if (dev->phy.rev >= 3) {
3253                 b43_shm_write16(dev, B43_SHM_SHARED,
3254                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3255                 b43_shm_write16(dev, B43_SHM_SHARED,
3256                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
3257         }
3258
3259         if (nphy->hang_avoid)
3260                 b43_nphy_stay_in_carrier_search(dev, false);
3261 }
3262
3263 /*
3264  * Restore RSSI Calibration
3265  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3266  */
3267 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3268 {
3269         struct b43_phy_n *nphy = dev->phy.n;
3270
3271         u16 *rssical_radio_regs = NULL;
3272         u16 *rssical_phy_regs = NULL;
3273
3274         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3275                 if (!nphy->rssical_chanspec_2G.center_freq)
3276                         return;
3277                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3278                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3279         } else {
3280                 if (!nphy->rssical_chanspec_5G.center_freq)
3281                         return;
3282                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3283                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3284         }
3285
3286         /* TODO use some definitions */
3287         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
3288         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
3289
3290         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3291         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3292         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3293         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3294
3295         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3296         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3297         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3298         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3299
3300         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3301         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3302         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3303         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3304 }
3305
3306 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
3307 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3308 {
3309         struct b43_phy_n *nphy = dev->phy.n;
3310         u16 *save = nphy->tx_rx_cal_radio_saveregs;
3311         u16 tmp;
3312         u8 offset, i;
3313
3314         if (dev->phy.rev >= 3) {
3315             for (i = 0; i < 2; i++) {
3316                 tmp = (i == 0) ? 0x2000 : 0x3000;
3317                 offset = i * 11;
3318
3319                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
3320                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
3321                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
3322                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
3323                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
3324                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
3325                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
3326                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
3327                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
3328                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
3329                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
3330
3331                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3332                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3333                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3334                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3335                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3336                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3337                         if (nphy->ipa5g_on) {
3338                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
3339                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
3340                         } else {
3341                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3342                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
3343                         }
3344                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3345                 } else {
3346                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3347                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3348                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3349                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3350                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3351                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
3352                         if (nphy->ipa2g_on) {
3353                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
3354                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
3355                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
3356                         } else {
3357                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3358                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3359                         }
3360                 }
3361                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
3362                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
3363                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
3364             }
3365         } else {
3366                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
3367                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3368
3369                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
3370                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3371
3372                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
3373                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3374
3375                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
3376                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3377
3378                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
3379                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
3380
3381                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3382                     B43_NPHY_BANDCTL_5GHZ)) {
3383                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
3384                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
3385                 } else {
3386                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
3387                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
3388                 }
3389
3390                 if (dev->phy.rev < 2) {
3391                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
3392                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
3393                 } else {
3394                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
3395                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
3396                 }
3397         }
3398 }
3399
3400 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3401 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3402 {
3403         struct b43_phy_n *nphy = dev->phy.n;
3404         int i;
3405         u16 scale, entry;
3406
3407         u16 tmp = nphy->txcal_bbmult;
3408         if (core == 0)
3409                 tmp >>= 8;
3410         tmp &= 0xff;
3411
3412         for (i = 0; i < 18; i++) {
3413                 scale = (ladder_lo[i].percent * tmp) / 100;
3414                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
3415                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
3416
3417                 scale = (ladder_iq[i].percent * tmp) / 100;
3418                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
3419                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
3420         }
3421 }
3422
3423 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
3424 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
3425 {
3426         int i;
3427         for (i = 0; i < 15; i++)
3428                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
3429                                 tbl_tx_filter_coef_rev4[2][i]);
3430 }
3431
3432 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
3433 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
3434 {
3435         int i, j;
3436         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
3437         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
3438
3439         for (i = 0; i < 3; i++)
3440                 for (j = 0; j < 15; j++)
3441                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
3442                                         tbl_tx_filter_coef_rev4[i][j]);
3443
3444         if (dev->phy.is_40mhz) {
3445                 for (j = 0; j < 15; j++)
3446                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3447                                         tbl_tx_filter_coef_rev4[3][j]);
3448         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3449                 for (j = 0; j < 15; j++)
3450                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3451                                         tbl_tx_filter_coef_rev4[5][j]);
3452         }
3453
3454         if (dev->phy.channel == 14)
3455                 for (j = 0; j < 15; j++)
3456                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3457                                         tbl_tx_filter_coef_rev4[6][j]);
3458 }
3459
3460 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
3461 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
3462 {
3463         struct b43_phy_n *nphy = dev->phy.n;
3464
3465         u16 curr_gain[2];
3466         struct nphy_txgains target;
3467         const u32 *table = NULL;
3468
3469         if (!nphy->txpwrctrl) {
3470                 int i;
3471
3472                 if (nphy->hang_avoid)
3473                         b43_nphy_stay_in_carrier_search(dev, true);
3474                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
3475                 if (nphy->hang_avoid)
3476                         b43_nphy_stay_in_carrier_search(dev, false);
3477
3478                 for (i = 0; i < 2; ++i) {
3479                         if (dev->phy.rev >= 3) {
3480                                 target.ipa[i] = curr_gain[i] & 0x000F;
3481                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
3482                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
3483                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
3484                         } else {
3485                                 target.ipa[i] = curr_gain[i] & 0x0003;
3486                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
3487                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
3488                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
3489                         }
3490                 }
3491         } else {
3492                 int i;
3493                 u16 index[2];
3494                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
3495                         B43_NPHY_TXPCTL_STAT_BIDX) >>
3496                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3497                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
3498                         B43_NPHY_TXPCTL_STAT_BIDX) >>
3499                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3500
3501                 for (i = 0; i < 2; ++i) {
3502                         table = b43_nphy_get_tx_gain_table(dev);
3503                         if (dev->phy.rev >= 3) {
3504                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3505                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3506                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3507                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3508                         } else {
3509                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3510                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3511                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3512                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3513                         }
3514                 }
3515         }
3516
3517         return target;
3518 }
3519
3520 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3521 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3522 {
3523         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3524
3525         if (dev->phy.rev >= 3) {
3526                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3527                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3528                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3529                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3530                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
3531                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3532                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
3533                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3534                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3535                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3536                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3537                 b43_nphy_reset_cca(dev);
3538         } else {
3539                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3540                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3541                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3542                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3543                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
3544                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3545                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3546         }
3547 }
3548
3549 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3550 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3551 {
3552         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3553         u16 tmp;
3554
3555         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3556         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3557         if (dev->phy.rev >= 3) {
3558                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3559                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3560
3561                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3562                 regs[2] = tmp;
3563                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3564
3565                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3566                 regs[3] = tmp;
3567                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3568
3569                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
3570                 b43_phy_mask(dev, B43_NPHY_BBCFG,
3571                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
3572
3573                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
3574                 regs[5] = tmp;
3575                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
3576
3577                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
3578                 regs[6] = tmp;
3579                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
3580                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3581                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3582
3583                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3584                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3585                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
3586
3587                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3588                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3589                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3590                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3591         } else {
3592                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3593                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3594                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3595                 regs[2] = tmp;
3596                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
3597                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
3598                 regs[3] = tmp;
3599                 tmp |= 0x2000;
3600                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
3601                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
3602                 regs[4] = tmp;
3603                 tmp |= 0x2000;
3604                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
3605                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3606                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3607                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3608                         tmp = 0x0180;
3609                 else
3610                         tmp = 0x0120;
3611                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3612                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3613         }
3614 }
3615
3616 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3617 static void b43_nphy_save_cal(struct b43_wldev *dev)
3618 {
3619         struct b43_phy_n *nphy = dev->phy.n;
3620
3621         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3622         u16 *txcal_radio_regs = NULL;
3623         struct b43_chanspec *iqcal_chanspec;
3624         u16 *table = NULL;
3625
3626         if (nphy->hang_avoid)
3627                 b43_nphy_stay_in_carrier_search(dev, 1);
3628
3629         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3630                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3631                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3632                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3633                 table = nphy->cal_cache.txcal_coeffs_2G;
3634         } else {
3635                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3636                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3637                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3638                 table = nphy->cal_cache.txcal_coeffs_5G;
3639         }
3640
3641         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3642         /* TODO use some definitions */
3643         if (dev->phy.rev >= 3) {
3644                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3645                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3646                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3647                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3648                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3649                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3650                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3651                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3652         } else {
3653                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3654                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3655                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3656                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3657         }
3658         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3659         iqcal_chanspec->channel_type = dev->phy.channel_type;
3660         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3661
3662         if (nphy->hang_avoid)
3663                 b43_nphy_stay_in_carrier_search(dev, 0);
3664 }
3665
3666 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3667 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3668 {
3669         struct b43_phy_n *nphy = dev->phy.n;
3670
3671         u16 coef[4];
3672         u16 *loft = NULL;
3673         u16 *table = NULL;
3674
3675         int i;
3676         u16 *txcal_radio_regs = NULL;
3677         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3678
3679         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3680                 if (!nphy->iqcal_chanspec_2G.center_freq)
3681                         return;
3682                 table = nphy->cal_cache.txcal_coeffs_2G;
3683                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3684         } else {
3685                 if (!nphy->iqcal_chanspec_5G.center_freq)
3686                         return;
3687                 table = nphy->cal_cache.txcal_coeffs_5G;
3688                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3689         }
3690
3691         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3692
3693         for (i = 0; i < 4; i++) {
3694                 if (dev->phy.rev >= 3)
3695                         table[i] = coef[i];
3696                 else
3697                         coef[i] = 0;
3698         }
3699
3700         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3701         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3702         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3703
3704         if (dev->phy.rev < 2)
3705                 b43_nphy_tx_iq_workaround(dev);
3706
3707         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3708                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3709                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3710         } else {
3711                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3712                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3713         }
3714
3715         /* TODO use some definitions */
3716         if (dev->phy.rev >= 3) {
3717                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3718                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3719                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3720                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3721                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3722                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3723                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3724                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3725         } else {
3726                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3727                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3728                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3729                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3730         }
3731         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3732 }
3733
3734 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3735 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3736                                 struct nphy_txgains target,
3737                                 bool full, bool mphase)
3738 {
3739         struct b43_phy_n *nphy = dev->phy.n;
3740         int i;
3741         int error = 0;
3742         int freq;
3743         bool avoid = false;
3744         u8 length;
3745         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3746         const u16 *table;
3747         bool phy6or5x;
3748
3749         u16 buffer[11];
3750         u16 diq_start = 0;
3751         u16 save[2];
3752         u16 gain[2];
3753         struct nphy_iqcal_params params[2];
3754         bool updated[2] = { };
3755
3756         b43_nphy_stay_in_carrier_search(dev, true);
3757
3758         if (dev->phy.rev >= 4) {
3759                 avoid = nphy->hang_avoid;
3760                 nphy->hang_avoid = false;
3761         }
3762
3763         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3764
3765         for (i = 0; i < 2; i++) {
3766                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3767                 gain[i] = params[i].cal_gain;
3768         }
3769
3770         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3771
3772         b43_nphy_tx_cal_radio_setup(dev);
3773         b43_nphy_tx_cal_phy_setup(dev);
3774
3775         phy6or5x = dev->phy.rev >= 6 ||
3776                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3777                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3778         if (phy6or5x) {
3779                 if (dev->phy.is_40mhz) {
3780                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3781                                         tbl_tx_iqlo_cal_loft_ladder_40);
3782                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3783                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3784                 } else {
3785                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3786                                         tbl_tx_iqlo_cal_loft_ladder_20);
3787                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3788                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3789                 }
3790         }
3791
3792         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3793
3794         if (!dev->phy.is_40mhz)
3795                 freq = 2500;
3796         else
3797                 freq = 5000;
3798
3799         if (nphy->mphase_cal_phase_id > 2)
3800                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3801                                         0xFFFF, 0, true, false);
3802         else
3803                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3804
3805         if (error == 0) {
3806                 if (nphy->mphase_cal_phase_id > 2) {
3807                         table = nphy->mphase_txcal_bestcoeffs;
3808                         length = 11;
3809                         if (dev->phy.rev < 3)
3810                                 length -= 2;
3811                 } else {
3812                         if (!full && nphy->txiqlocal_coeffsvalid) {
3813                                 table = nphy->txiqlocal_bestc;
3814                                 length = 11;
3815                                 if (dev->phy.rev < 3)
3816                                         length -= 2;
3817                         } else {
3818                                 full = true;
3819                                 if (dev->phy.rev >= 3) {
3820                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3821                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3822                                 } else {
3823                                         table = tbl_tx_iqlo_cal_startcoefs;
3824                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3825                                 }
3826                         }
3827                 }
3828
3829                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3830
3831                 if (full) {
3832                         if (dev->phy.rev >= 3)
3833                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3834                         else
3835                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3836                 } else {
3837                         if (dev->phy.rev >= 3)
3838                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3839                         else
3840                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3841                 }
3842
3843                 if (mphase) {
3844                         count = nphy->mphase_txcal_cmdidx;
3845                         numb = min(max,
3846                                 (u16)(count + nphy->mphase_txcal_numcmds));
3847                 } else {
3848                         count = 0;
3849                         numb = max;
3850                 }
3851
3852                 for (; count < numb; count++) {
3853                         if (full) {
3854                                 if (dev->phy.rev >= 3)
3855                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3856                                 else
3857                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3858                         } else {
3859                                 if (dev->phy.rev >= 3)
3860                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3861                                 else
3862                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3863                         }
3864
3865                         core = (cmd & 0x3000) >> 12;
3866                         type = (cmd & 0x0F00) >> 8;
3867
3868                         if (phy6or5x && updated[core] == 0) {
3869                                 b43_nphy_update_tx_cal_ladder(dev, core);
3870                                 updated[core] = true;
3871                         }
3872
3873                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3874                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3875
3876                         if (type == 1 || type == 3 || type == 4) {
3877                                 buffer[0] = b43_ntab_read(dev,
3878                                                 B43_NTAB16(15, 69 + core));
3879                                 diq_start = buffer[0];
3880                                 buffer[0] = 0;
3881                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3882                                                 0);
3883                         }
3884
3885                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3886                         for (i = 0; i < 2000; i++) {
3887                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3888                                 if (tmp & 0xC000)
3889                                         break;
3890                                 udelay(10);
3891                         }
3892
3893                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3894                                                 buffer);
3895                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3896                                                 buffer);
3897
3898                         if (type == 1 || type == 3 || type == 4)
3899                                 buffer[0] = diq_start;
3900                 }
3901
3902                 if (mphase)
3903                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3904
3905                 last = (dev->phy.rev < 3) ? 6 : 7;
3906
3907                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3908                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3909                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3910                         if (dev->phy.rev < 3) {
3911                                 buffer[0] = 0;
3912                                 buffer[1] = 0;
3913                                 buffer[2] = 0;
3914                                 buffer[3] = 0;
3915                         }
3916                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3917                                                 buffer);
3918                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3919                                                 buffer);
3920                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3921                                                 buffer);
3922                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3923                                                 buffer);
3924                         length = 11;
3925                         if (dev->phy.rev < 3)
3926                                 length -= 2;
3927                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3928                                                 nphy->txiqlocal_bestc);
3929                         nphy->txiqlocal_coeffsvalid = true;
3930                         nphy->txiqlocal_chanspec.center_freq =
3931                                                         dev->phy.channel_freq;
3932                         nphy->txiqlocal_chanspec.channel_type =
3933                                                         dev->phy.channel_type;
3934                 } else {
3935                         length = 11;
3936                         if (dev->phy.rev < 3)
3937                                 length -= 2;
3938                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3939                                                 nphy->mphase_txcal_bestcoeffs);
3940                 }
3941
3942                 b43_nphy_stop_playback(dev);
3943                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3944         }
3945
3946         b43_nphy_tx_cal_phy_cleanup(dev);
3947         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3948
3949         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3950                 b43_nphy_tx_iq_workaround(dev);
3951
3952         if (dev->phy.rev >= 4)
3953                 nphy->hang_avoid = avoid;
3954
3955         b43_nphy_stay_in_carrier_search(dev, false);
3956
3957         return error;
3958 }
3959
3960 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3961 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3962 {
3963         struct b43_phy_n *nphy = dev->phy.n;
3964         u8 i;
3965         u16 buffer[7];
3966         bool equal = true;
3967
3968         if (!nphy->txiqlocal_coeffsvalid ||
3969             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3970             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3971                 return;
3972
3973         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3974         for (i = 0; i < 4; i++) {
3975                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3976                         equal = false;
3977                         break;
3978                 }
3979         }
3980
3981         if (!equal) {
3982                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3983                                         nphy->txiqlocal_bestc);
3984                 for (i = 0; i < 4; i++)
3985                         buffer[i] = 0;
3986                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3987                                         buffer);
3988                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3989                                         &nphy->txiqlocal_bestc[5]);
3990                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3991                                         &nphy->txiqlocal_bestc[5]);
3992         }
3993 }
3994
3995 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3996 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3997                         struct nphy_txgains target, u8 type, bool debug)
3998 {
3999         struct b43_phy_n *nphy = dev->phy.n;
4000         int i, j, index;
4001         u8 rfctl[2];
4002         u8 afectl_core;
4003         u16 tmp[6];
4004         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
4005         u32 real, imag;
4006         enum ieee80211_band band;
4007
4008         u8 use;
4009         u16 cur_hpf;
4010         u16 lna[3] = { 3, 3, 1 };
4011         u16 hpf1[3] = { 7, 2, 0 };
4012         u16 hpf2[3] = { 2, 0, 0 };
4013         u32 power[3] = { };
4014         u16 gain_save[2];
4015         u16 cal_gain[2];
4016         struct nphy_iqcal_params cal_params[2];
4017         struct nphy_iq_est est;
4018         int ret = 0;
4019         bool playtone = true;
4020         int desired = 13;
4021
4022         b43_nphy_stay_in_carrier_search(dev, 1);
4023
4024         if (dev->phy.rev < 2)
4025                 b43_nphy_reapply_tx_cal_coeffs(dev);
4026         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4027         for (i = 0; i < 2; i++) {
4028                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4029                 cal_gain[i] = cal_params[i].cal_gain;
4030         }
4031         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
4032
4033         for (i = 0; i < 2; i++) {
4034                 if (i == 0) {
4035                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
4036                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
4037                         afectl_core = B43_NPHY_AFECTL_C1;
4038                 } else {
4039                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
4040                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
4041                         afectl_core = B43_NPHY_AFECTL_C2;
4042                 }
4043
4044                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4045                 tmp[2] = b43_phy_read(dev, afectl_core);
4046                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4047                 tmp[4] = b43_phy_read(dev, rfctl[0]);
4048                 tmp[5] = b43_phy_read(dev, rfctl[1]);
4049
4050                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4051                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4052                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4053                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4054                                 (1 - i));
4055                 b43_phy_set(dev, afectl_core, 0x0006);
4056                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4057
4058                 band = b43_current_band(dev->wl);
4059
4060                 if (nphy->rxcalparams & 0xFF000000) {
4061                         if (band == IEEE80211_BAND_5GHZ)
4062                                 b43_phy_write(dev, rfctl[0], 0x140);
4063                         else
4064                                 b43_phy_write(dev, rfctl[0], 0x110);
4065                 } else {
4066                         if (band == IEEE80211_BAND_5GHZ)
4067                                 b43_phy_write(dev, rfctl[0], 0x180);
4068                         else
4069                                 b43_phy_write(dev, rfctl[0], 0x120);
4070                 }
4071
4072                 if (band == IEEE80211_BAND_5GHZ)
4073                         b43_phy_write(dev, rfctl[1], 0x148);
4074                 else
4075                         b43_phy_write(dev, rfctl[1], 0x114);
4076
4077                 if (nphy->rxcalparams & 0x10000) {
4078                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4079                                         (i + 1));
4080                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4081                                         (2 - i));
4082                 }
4083
4084                 for (j = 0; j < 4; j++) {
4085                         if (j < 3) {
4086                                 cur_lna = lna[j];
4087                                 cur_hpf1 = hpf1[j];
4088                                 cur_hpf2 = hpf2[j];
4089                         } else {
4090                                 if (power[1] > 10000) {
4091                                         use = 1;
4092                                         cur_hpf = cur_hpf1;
4093                                         index = 2;
4094                                 } else {
4095                                         if (power[0] > 10000) {
4096                                                 use = 1;
4097                                                 cur_hpf = cur_hpf1;
4098                                                 index = 1;
4099                                         } else {
4100                                                 index = 0;
4101                                                 use = 2;
4102                                                 cur_hpf = cur_hpf2;
4103                                         }
4104                                 }
4105                                 cur_lna = lna[index];
4106                                 cur_hpf1 = hpf1[index];
4107                                 cur_hpf2 = hpf2[index];
4108                                 cur_hpf += desired - hweight32(power[index]);
4109                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
4110                                 if (use == 1)
4111                                         cur_hpf1 = cur_hpf;
4112                                 else
4113                                         cur_hpf2 = cur_hpf;
4114                         }
4115
4116                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4117                                         (cur_lna << 2));
4118                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
4119                                                                         false);
4120                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4121                         b43_nphy_stop_playback(dev);
4122
4123                         if (playtone) {
4124                                 ret = b43_nphy_tx_tone(dev, 4000,
4125                                                 (nphy->rxcalparams & 0xFFFF),
4126                                                 false, false);
4127                                 playtone = false;
4128                         } else {
4129                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4130                                                         false, false);
4131                         }
4132
4133                         if (ret == 0) {
4134                                 if (j < 3) {
4135                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4136                                                                         false);
4137                                         if (i == 0) {
4138                                                 real = est.i0_pwr;
4139                                                 imag = est.q0_pwr;
4140                                         } else {
4141                                                 real = est.i1_pwr;
4142                                                 imag = est.q1_pwr;
4143                                         }
4144                                         power[i] = ((real + imag) / 1024) + 1;
4145                                 } else {
4146                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4147                                 }
4148                                 b43_nphy_stop_playback(dev);
4149                         }
4150
4151                         if (ret != 0)
4152                                 break;
4153                 }
4154
4155                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4156                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4157                 b43_phy_write(dev, rfctl[1], tmp[5]);
4158                 b43_phy_write(dev, rfctl[0], tmp[4]);
4159                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4160                 b43_phy_write(dev, afectl_core, tmp[2]);
4161                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4162
4163                 if (ret != 0)
4164                         break;
4165         }
4166
4167         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
4168         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4169         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4170
4171         b43_nphy_stay_in_carrier_search(dev, 0);
4172
4173         return ret;
4174 }
4175
4176 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4177                         struct nphy_txgains target, u8 type, bool debug)
4178 {
4179         return -1;
4180 }
4181
4182 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4183 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4184                         struct nphy_txgains target, u8 type, bool debug)
4185 {
4186         if (dev->phy.rev >= 3)
4187                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4188         else
4189                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4190 }
4191
4192 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4193 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4194 {
4195         struct b43_phy *phy = &dev->phy;
4196         struct b43_phy_n *nphy = phy->n;
4197         /* u16 buf[16]; it's rev3+ */
4198
4199         nphy->phyrxchain = mask;
4200
4201         if (0 /* FIXME clk */)
4202                 return;
4203
4204         b43_mac_suspend(dev);
4205
4206         if (nphy->hang_avoid)
4207                 b43_nphy_stay_in_carrier_search(dev, true);
4208
4209         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4210                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4211
4212         if ((mask & 0x3) != 0x3) {
4213                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4214                 if (dev->phy.rev >= 3) {
4215                         /* TODO */
4216                 }
4217         } else {
4218                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4219                 if (dev->phy.rev >= 3) {
4220                         /* TODO */
4221                 }
4222         }
4223
4224         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4225
4226         if (nphy->hang_avoid)
4227                 b43_nphy_stay_in_carrier_search(dev, false);
4228
4229         b43_mac_enable(dev);
4230 }
4231
4232 /**************************************************
4233  * N-PHY init
4234  **************************************************/
4235
4236 /*
4237  * Upload the N-PHY tables.
4238  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
4239  */
4240 static void b43_nphy_tables_init(struct b43_wldev *dev)
4241 {
4242         if (dev->phy.rev < 3)
4243                 b43_nphy_rev0_1_2_tables_init(dev);
4244         else
4245                 b43_nphy_rev3plus_tables_init(dev);
4246 }
4247
4248 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4249 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4250 {
4251         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4252
4253         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4254         if (preamble == 1)
4255                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4256         else
4257                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4258
4259         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4260 }
4261
4262 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4263 static void b43_nphy_bphy_init(struct b43_wldev *dev)
4264 {
4265         unsigned int i;
4266         u16 val;
4267
4268         val = 0x1E1F;
4269         for (i = 0; i < 16; i++) {
4270                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4271                 val -= 0x202;
4272         }
4273         val = 0x3E3F;
4274         for (i = 0; i < 16; i++) {
4275                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4276                 val -= 0x202;
4277         }
4278         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4279 }
4280
4281 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4282 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4283 {
4284         if (dev->phy.rev >= 3) {
4285                 if (!init)
4286                         return;
4287                 if (0 /* FIXME */) {
4288                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4289                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4290                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4291                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4292                 }
4293         } else {
4294                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4295                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4296
4297                 switch (dev->dev->bus_type) {
4298 #ifdef CONFIG_B43_BCMA
4299                 case B43_BUS_BCMA:
4300                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4301                                                  0xFC00, 0xFC00);
4302                         break;
4303 #endif
4304 #ifdef CONFIG_B43_SSB
4305                 case B43_BUS_SSB:
4306                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4307                                                 0xFC00, 0xFC00);
4308                         break;
4309 #endif
4310                 }
4311
4312                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4313                 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4314                 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4315                               0);
4316
4317                 if (init) {
4318                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4319                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4320                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4321                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4322                 }
4323         }
4324 }
4325
4326 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
4327 int b43_phy_initn(struct b43_wldev *dev)
4328 {
4329         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4330         struct b43_phy *phy = &dev->phy;
4331         struct b43_phy_n *nphy = phy->n;
4332         u8 tx_pwr_state;
4333         struct nphy_txgains target;
4334         u16 tmp;
4335         enum ieee80211_band tmp2;
4336         bool do_rssi_cal;
4337
4338         u16 clip[2];
4339         bool do_cal = false;
4340
4341         if ((dev->phy.rev >= 3) &&
4342            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
4343            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
4344                 switch (dev->dev->bus_type) {
4345 #ifdef CONFIG_B43_BCMA
4346                 case B43_BUS_BCMA:
4347                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4348                                       BCMA_CC_CHIPCTL, 0x40);
4349                         break;
4350 #endif
4351 #ifdef CONFIG_B43_SSB
4352                 case B43_BUS_SSB:
4353                         chipco_set32(&dev->dev->sdev->bus->chipco,
4354                                      SSB_CHIPCO_CHIPCTL, 0x40);
4355                         break;
4356 #endif
4357                 }
4358         }
4359         nphy->deaf_count = 0;
4360         b43_nphy_tables_init(dev);
4361         nphy->crsminpwr_adjusted = false;
4362         nphy->noisevars_adjusted = false;
4363
4364         /* Clear all overrides */
4365         if (dev->phy.rev >= 3) {
4366                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4367                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4368                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4369                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4370         } else {
4371                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4372         }
4373         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4374         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
4375         if (dev->phy.rev < 6) {
4376                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4377                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4378         }
4379         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4380                      ~(B43_NPHY_RFSEQMODE_CAOVER |
4381                        B43_NPHY_RFSEQMODE_TROVER));
4382         if (dev->phy.rev >= 3)
4383                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
4384         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4385
4386         if (dev->phy.rev <= 2) {
4387                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
4388                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
4389                                 ~B43_NPHY_BPHY_CTL3_SCALE,
4390                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
4391         }
4392         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
4393         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
4394
4395         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
4396             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4397              dev->dev->board_type == 0x8B))
4398                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
4399         else
4400                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
4401         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
4402         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
4403         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
4404
4405         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4406         b43_nphy_update_txrx_chain(dev);
4407
4408         if (phy->rev < 2) {
4409                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
4410                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
4411         }
4412
4413         tmp2 = b43_current_band(dev->wl);
4414         if (b43_nphy_ipa(dev)) {
4415                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
4416                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
4417                                 nphy->papd_epsilon_offset[0] << 7);
4418                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
4419                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
4420                                 nphy->papd_epsilon_offset[1] << 7);
4421                 b43_nphy_int_pa_set_tx_dig_filters(dev);
4422         } else if (phy->rev >= 5) {
4423                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
4424         }
4425
4426         b43_nphy_workarounds(dev);
4427
4428         /* Reset CCA, in init code it differs a little from standard way */
4429         b43_phy_force_clock(dev, 1);
4430         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
4431         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
4432         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
4433         b43_phy_force_clock(dev, 0);
4434
4435         b43_mac_phy_clock_set(dev, true);
4436
4437         b43_nphy_pa_override(dev, false);
4438         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
4439         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4440         b43_nphy_pa_override(dev, true);
4441
4442         b43_nphy_classifier(dev, 0, 0);
4443         b43_nphy_read_clip_detection(dev, clip);
4444         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4445                 b43_nphy_bphy_init(dev);
4446
4447         tx_pwr_state = nphy->txpwrctrl;
4448         b43_nphy_tx_power_ctrl(dev, false);
4449         b43_nphy_tx_power_fix(dev);
4450         b43_nphy_tx_power_ctl_idle_tssi(dev);
4451         b43_nphy_tx_power_ctl_setup(dev);
4452         b43_nphy_tx_gain_table_upload(dev);
4453
4454         if (nphy->phyrxchain != 3)
4455                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
4456         if (nphy->mphase_cal_phase_id > 0)
4457                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
4458
4459         do_rssi_cal = false;
4460         if (phy->rev >= 3) {
4461                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4462                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
4463                 else
4464                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
4465
4466                 if (do_rssi_cal)
4467                         b43_nphy_rssi_cal(dev);
4468                 else
4469                         b43_nphy_restore_rssi_cal(dev);
4470         } else {
4471                 b43_nphy_rssi_cal(dev);
4472         }
4473
4474         if (!((nphy->measure_hold & 0x6) != 0)) {
4475                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4476                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
4477                 else
4478                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
4479
4480                 if (nphy->mute)
4481                         do_cal = false;
4482
4483                 if (do_cal) {
4484                         target = b43_nphy_get_tx_gains(dev);
4485
4486                         if (nphy->antsel_type == 2)
4487                                 b43_nphy_superswitch_init(dev, true);
4488                         if (nphy->perical != 2) {
4489                                 b43_nphy_rssi_cal(dev);
4490                                 if (phy->rev >= 3) {
4491                                         nphy->cal_orig_pwr_idx[0] =
4492                                             nphy->txpwrindex[0].index_internal;
4493                                         nphy->cal_orig_pwr_idx[1] =
4494                                             nphy->txpwrindex[1].index_internal;
4495                                         /* TODO N PHY Pre Calibrate TX Gain */
4496                                         target = b43_nphy_get_tx_gains(dev);
4497                                 }
4498                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
4499                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
4500                                                 b43_nphy_save_cal(dev);
4501                         } else if (nphy->mphase_cal_phase_id == 0)
4502                                 ;/* N PHY Periodic Calibration with arg 3 */
4503                 } else {
4504                         b43_nphy_restore_cal(dev);
4505                 }
4506         }
4507
4508         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
4509         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
4510         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
4511         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
4512         if (phy->rev >= 3 && phy->rev <= 6)
4513                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
4514         b43_nphy_tx_lp_fbw(dev);
4515         if (phy->rev >= 3)
4516                 b43_nphy_spur_workaround(dev);
4517
4518         return 0;
4519 }
4520
4521 /**************************************************
4522  * Channel switching ops.
4523  **************************************************/
4524
4525 static void b43_chantab_phy_upload(struct b43_wldev *dev,
4526                                    const struct b43_phy_n_sfo_cfg *e)
4527 {
4528         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
4529         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
4530         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
4531         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
4532         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
4533         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
4534 }
4535
4536 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
4537 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
4538 {
4539         struct bcma_drv_cc __maybe_unused *cc;
4540         u32 __maybe_unused pmu_ctl;
4541
4542         switch (dev->dev->bus_type) {
4543 #ifdef CONFIG_B43_BCMA
4544         case B43_BUS_BCMA:
4545                 cc = &dev->dev->bdev->bus->drv_cc;
4546                 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
4547                         if (avoid) {
4548                                 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
4549                                 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
4550                                 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
4551                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4552                                 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
4553                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4554                         } else {
4555                                 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
4556                                 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
4557                                 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
4558                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4559                                 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4560                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4561                         }
4562                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4563                 } else if (dev->dev->chip_id == 0x4716) {
4564                         if (avoid) {
4565                                 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
4566                                 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
4567                                 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
4568                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4569                                 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
4570                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4571                         } else {
4572                                 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
4573                                 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
4574                                 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
4575                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4576                                 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4577                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4578                         }
4579                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
4580                                   BCMA_CC_PMU_CTL_NOILPONW;
4581                 } else if (dev->dev->chip_id == 0x4322 ||
4582                            dev->dev->chip_id == 0x4340 ||
4583                            dev->dev->chip_id == 0x4341) {
4584                         bcma_chipco_pll_write(cc, 0x0, 0x11100070);
4585                         bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
4586                         bcma_chipco_pll_write(cc, 0x5, 0x88888854);
4587                         if (avoid)
4588                                 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
4589                         else
4590                                 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
4591                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4592                 } else {
4593                         return;
4594                 }
4595                 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
4596                 break;
4597 #endif
4598 #ifdef CONFIG_B43_SSB
4599         case B43_BUS_SSB:
4600                 /* FIXME */
4601                 break;
4602 #endif
4603         }
4604 }
4605
4606 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
4607 static void b43_nphy_channel_setup(struct b43_wldev *dev,
4608                                 const struct b43_phy_n_sfo_cfg *e,
4609                                 struct ieee80211_channel *new_channel)
4610 {
4611         struct b43_phy *phy = &dev->phy;
4612         struct b43_phy_n *nphy = dev->phy.n;
4613         int ch = new_channel->hw_value;
4614
4615         u16 old_band_5ghz;
4616         u32 tmp32;
4617
4618         old_band_5ghz =
4619                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
4620         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
4621                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4622                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4623                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
4624                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4625                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
4626         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
4627                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
4628                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4629                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4630                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
4631                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4632         }
4633
4634         b43_chantab_phy_upload(dev, e);
4635
4636         if (new_channel->hw_value == 14) {
4637                 b43_nphy_classifier(dev, 2, 0);
4638                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
4639         } else {
4640                 b43_nphy_classifier(dev, 2, 2);
4641                 if (new_channel->band == IEEE80211_BAND_2GHZ)
4642                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
4643         }
4644
4645         if (!nphy->txpwrctrl)
4646                 b43_nphy_tx_power_fix(dev);
4647
4648         if (dev->phy.rev < 3)
4649                 b43_nphy_adjust_lna_gain_table(dev);
4650
4651         b43_nphy_tx_lp_fbw(dev);
4652
4653         if (dev->phy.rev >= 3 &&
4654             dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
4655                 bool avoid = false;
4656                 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
4657                         avoid = true;
4658                 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
4659                         if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
4660                                 avoid = true;
4661                 } else { /* 40MHz */
4662                         if (nphy->aband_spurwar_en &&
4663                             (ch == 38 || ch == 102 || ch == 118))
4664                                 avoid = dev->dev->chip_id == 0x4716;
4665                 }
4666
4667                 b43_nphy_pmu_spur_avoid(dev, avoid);
4668
4669                 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
4670                     dev->dev->chip_id == 43225) {
4671                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
4672                                     avoid ? 0x5341 : 0x8889);
4673                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
4674                 }
4675
4676                 if (dev->phy.rev == 3 || dev->phy.rev == 4)
4677                         ; /* TODO: reset PLL */
4678
4679                 if (avoid)
4680                         b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
4681                 else
4682                         b43_phy_mask(dev, B43_NPHY_BBCFG,
4683                                      ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4684
4685                 b43_nphy_reset_cca(dev);
4686
4687                 /* wl sets useless phy_isspuravoid here */
4688         }
4689
4690         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
4691
4692         if (phy->rev >= 3)
4693                 b43_nphy_spur_workaround(dev);
4694 }
4695
4696 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
4697 static int b43_nphy_set_channel(struct b43_wldev *dev,
4698                                 struct ieee80211_channel *channel,
4699                                 enum nl80211_channel_type channel_type)
4700 {
4701         struct b43_phy *phy = &dev->phy;
4702
4703         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
4704         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
4705
4706         u8 tmp;
4707
4708         if (dev->phy.rev >= 3) {
4709                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4710                                                         channel->center_freq);
4711                 if (!tabent_r3)
4712                         return -ESRCH;
4713         } else {
4714                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4715                                                         channel->hw_value);
4716                 if (!tabent_r2)
4717                         return -ESRCH;
4718         }
4719
4720         /* Channel is set later in common code, but we need to set it on our
4721            own to let this function's subcalls work properly. */
4722         phy->channel = channel->hw_value;
4723         phy->channel_freq = channel->center_freq;
4724
4725         if (b43_channel_type_is_40mhz(phy->channel_type) !=
4726                 b43_channel_type_is_40mhz(channel_type))
4727                 ; /* TODO: BMAC BW Set (channel_type) */
4728
4729         if (channel_type == NL80211_CHAN_HT40PLUS)
4730                 b43_phy_set(dev, B43_NPHY_RXCTL,
4731                                 B43_NPHY_RXCTL_BSELU20);
4732         else if (channel_type == NL80211_CHAN_HT40MINUS)
4733                 b43_phy_mask(dev, B43_NPHY_RXCTL,
4734                                 ~B43_NPHY_RXCTL_BSELU20);
4735
4736         if (dev->phy.rev >= 3) {
4737                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
4738                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
4739                 b43_radio_2056_setup(dev, tabent_r3);
4740                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
4741         } else {
4742                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
4743                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
4744                 b43_radio_2055_setup(dev, tabent_r2);
4745                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
4746         }
4747
4748         return 0;
4749 }
4750
4751 /**************************************************
4752  * Basic PHY ops.
4753  **************************************************/
4754
4755 static int b43_nphy_op_allocate(struct b43_wldev *dev)
4756 {
4757         struct b43_phy_n *nphy;
4758
4759         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4760         if (!nphy)
4761                 return -ENOMEM;
4762         dev->phy.n = nphy;
4763
4764         return 0;
4765 }
4766
4767 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
4768 {
4769         struct b43_phy *phy = &dev->phy;
4770         struct b43_phy_n *nphy = phy->n;
4771         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4772
4773         memset(nphy, 0, sizeof(*nphy));
4774
4775         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
4776         nphy->spur_avoid = (phy->rev >= 3) ?
4777                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
4778         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4779         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4780         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
4781         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
4782         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4783          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4784         nphy->tx_pwr_idx[0] = 128;
4785         nphy->tx_pwr_idx[1] = 128;
4786
4787         /* Hardware TX power control and 5GHz power gain */
4788         nphy->txpwrctrl = false;
4789         nphy->pwg_gain_5ghz = false;
4790         if (dev->phy.rev >= 3 ||
4791             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4792              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
4793                 nphy->txpwrctrl = true;
4794                 nphy->pwg_gain_5ghz = true;
4795         } else if (sprom->revision >= 4) {
4796                 if (dev->phy.rev >= 2 &&
4797                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
4798                         nphy->txpwrctrl = true;
4799 #ifdef CONFIG_B43_SSB
4800                         if (dev->dev->bus_type == B43_BUS_SSB &&
4801                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
4802                                 struct pci_dev *pdev =
4803                                         dev->dev->sdev->bus->host_pci;
4804                                 if (pdev->device == 0x4328 ||
4805                                     pdev->device == 0x432a)
4806                                         nphy->pwg_gain_5ghz = true;
4807                         }
4808 #endif
4809                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
4810                         nphy->pwg_gain_5ghz = true;
4811                 }
4812         }
4813
4814         if (dev->phy.rev >= 3) {
4815                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4816                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4817         }
4818 }
4819
4820 static void b43_nphy_op_free(struct b43_wldev *dev)
4821 {
4822         struct b43_phy *phy = &dev->phy;
4823         struct b43_phy_n *nphy = phy->n;
4824
4825         kfree(nphy);
4826         phy->n = NULL;
4827 }
4828
4829 static int b43_nphy_op_init(struct b43_wldev *dev)
4830 {
4831         return b43_phy_initn(dev);
4832 }
4833
4834 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4835 {
4836 #if B43_DEBUG
4837         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4838                 /* OFDM registers are onnly available on A/G-PHYs */
4839                 b43err(dev->wl, "Invalid OFDM PHY access at "
4840                        "0x%04X on N-PHY\n", offset);
4841                 dump_stack();
4842         }
4843         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4844                 /* Ext-G registers are only available on G-PHYs */
4845                 b43err(dev->wl, "Invalid EXT-G PHY access at "
4846                        "0x%04X on N-PHY\n", offset);
4847                 dump_stack();
4848         }
4849 #endif /* B43_DEBUG */
4850 }
4851
4852 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4853 {
4854         check_phyreg(dev, reg);
4855         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4856         return b43_read16(dev, B43_MMIO_PHY_DATA);
4857 }
4858
4859 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4860 {
4861         check_phyreg(dev, reg);
4862         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4863         b43_write16(dev, B43_MMIO_PHY_DATA, value);
4864 }
4865
4866 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4867                                  u16 set)
4868 {
4869         check_phyreg(dev, reg);
4870         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4871         b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
4872 }
4873
4874 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4875 {
4876         /* Register 1 is a 32-bit register. */
4877         B43_WARN_ON(reg == 1);
4878         /* N-PHY needs 0x100 for read access */
4879         reg |= 0x100;
4880
4881         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4882         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4883 }
4884
4885 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4886 {
4887         /* Register 1 is a 32-bit register. */
4888         B43_WARN_ON(reg == 1);
4889
4890         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4891         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4892 }
4893
4894 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4895 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4896                                         bool blocked)
4897 {
4898         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4899                 b43err(dev->wl, "MAC not suspended\n");
4900
4901         if (blocked) {
4902                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4903                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4904                 if (dev->phy.rev >= 3) {
4905                         b43_radio_mask(dev, 0x09, ~0x2);
4906
4907                         b43_radio_write(dev, 0x204D, 0);
4908                         b43_radio_write(dev, 0x2053, 0);
4909                         b43_radio_write(dev, 0x2058, 0);
4910                         b43_radio_write(dev, 0x205E, 0);
4911                         b43_radio_mask(dev, 0x2062, ~0xF0);
4912                         b43_radio_write(dev, 0x2064, 0);
4913
4914                         b43_radio_write(dev, 0x304D, 0);
4915                         b43_radio_write(dev, 0x3053, 0);
4916                         b43_radio_write(dev, 0x3058, 0);
4917                         b43_radio_write(dev, 0x305E, 0);
4918                         b43_radio_mask(dev, 0x3062, ~0xF0);
4919                         b43_radio_write(dev, 0x3064, 0);
4920                 }
4921         } else {
4922                 if (dev->phy.rev >= 3) {
4923                         b43_radio_init2056(dev);
4924                         b43_switch_channel(dev, dev->phy.channel);
4925                 } else {
4926                         b43_radio_init2055(dev);
4927                 }
4928         }
4929 }
4930
4931 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4932 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4933 {
4934         u16 override = on ? 0x0 : 0x7FFF;
4935         u16 core = on ? 0xD : 0x00FD;
4936
4937         if (dev->phy.rev >= 3) {
4938                 if (on) {
4939                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4940                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4941                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4942                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4943                 } else {
4944                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4945                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4946                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4947                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4948                 }
4949         } else {
4950                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4951         }
4952 }
4953
4954 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4955                                       unsigned int new_channel)
4956 {
4957         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4958         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4959
4960         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4961                 if ((new_channel < 1) || (new_channel > 14))
4962                         return -EINVAL;
4963         } else {
4964                 if (new_channel > 200)
4965                         return -EINVAL;
4966         }
4967
4968         return b43_nphy_set_channel(dev, channel, channel_type);
4969 }
4970
4971 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4972 {
4973         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4974                 return 1;
4975         return 36;
4976 }
4977
4978 const struct b43_phy_operations b43_phyops_n = {
4979         .allocate               = b43_nphy_op_allocate,
4980         .free                   = b43_nphy_op_free,
4981         .prepare_structs        = b43_nphy_op_prepare_structs,
4982         .init                   = b43_nphy_op_init,
4983         .phy_read               = b43_nphy_op_read,
4984         .phy_write              = b43_nphy_op_write,
4985         .phy_maskset            = b43_nphy_op_maskset,
4986         .radio_read             = b43_nphy_op_radio_read,
4987         .radio_write            = b43_nphy_op_radio_write,
4988         .software_rfkill        = b43_nphy_op_software_rfkill,
4989         .switch_analog          = b43_nphy_op_switch_analog,
4990         .switch_channel         = b43_nphy_op_switch_channel,
4991         .get_default_chan       = b43_nphy_op_get_default_chan,
4992         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4993         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4994 };