3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
25 #include <linux/delay.h>
26 #include <linux/types.h>
30 #include "tables_nphy.h"
40 struct nphy_iqcal_params {
58 enum b43_nphy_rf_sequence {
62 B43_RFSEQ_UPDATE_GAINH,
63 B43_RFSEQ_UPDATE_GAINL,
64 B43_RFSEQ_UPDATE_GAINU,
67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
68 u8 *events, u8 *delays, u8 length);
69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
70 enum b43_nphy_rf_sequence seq);
71 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
72 u16 value, u8 core, bool off);
73 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
76 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
80 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
84 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
87 return B43_TXPWR_RES_DONE;
90 static void b43_chantab_radio_upload(struct b43_wldev *dev,
91 const struct b43_nphy_channeltab_entry *e)
93 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
94 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
95 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
96 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
97 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
99 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
100 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
101 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
102 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
103 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
105 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
106 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
107 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
108 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
109 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
111 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
112 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
113 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
114 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
115 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
117 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
118 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
119 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
120 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
121 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
123 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
124 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
127 static void b43_chantab_phy_upload(struct b43_wldev *dev,
128 const struct b43_nphy_channeltab_entry *e)
130 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
131 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
132 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
133 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
134 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
135 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
138 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
143 /* Tune the hardware to a new channel. */
144 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
146 const struct b43_nphy_channeltab_entry *tabent;
148 tabent = b43_nphy_get_chantabent(dev, channel);
152 //FIXME enable/disable band select upper20 in RXCTL
153 if (0 /*FIXME 5Ghz*/)
154 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
156 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
157 b43_chantab_radio_upload(dev, tabent);
159 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
160 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
161 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
163 if (0 /*FIXME 5Ghz*/)
164 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
166 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
167 b43_chantab_phy_upload(dev, tabent);
168 b43_nphy_tx_power_fix(dev);
173 static void b43_radio_init2055_pre(struct b43_wldev *dev)
175 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
176 ~B43_NPHY_RFCTL_CMD_PORFORCE);
177 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
178 B43_NPHY_RFCTL_CMD_CHIP0PU |
179 B43_NPHY_RFCTL_CMD_OEPORFORCE);
180 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
181 B43_NPHY_RFCTL_CMD_PORFORCE);
184 static void b43_radio_init2055_post(struct b43_wldev *dev)
186 struct b43_phy_n *nphy = dev->phy.n;
187 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
188 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
191 bool workaround = false;
193 if (sprom->revision < 4)
194 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
195 binfo->type != 0x46D ||
198 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0);
200 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
202 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
203 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
205 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
206 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
207 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
208 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
209 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
211 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
212 for (i = 0; i < 200; i++) {
213 val = b43_radio_read(dev, B2055_CAL_COUT2);
221 b43err(dev->wl, "radio post init timeout\n");
222 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
223 nphy_channel_switch(dev, dev->phy.channel);
224 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
225 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
226 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
227 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
228 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
229 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
230 if (!nphy->gain_boost) {
231 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
232 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
234 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
235 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
241 * Initialize a Broadcom 2055 N-radio
242 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
244 static void b43_radio_init2055(struct b43_wldev *dev)
246 b43_radio_init2055_pre(dev);
247 if (b43_status(dev) < B43_STAT_INITIALIZED)
248 b2055_upload_inittab(dev, 0, 1);
250 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
251 b43_radio_init2055_post(dev);
255 * Upload the N-PHY tables.
256 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
258 static void b43_nphy_tables_init(struct b43_wldev *dev)
260 if (dev->phy.rev < 3)
261 b43_nphy_rev0_1_2_tables_init(dev);
263 b43_nphy_rev3plus_tables_init(dev);
266 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
267 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
269 struct b43_phy_n *nphy = dev->phy.n;
270 enum ieee80211_band band;
274 nphy->rfctrl_intc1_save = b43_phy_read(dev,
275 B43_NPHY_RFCTL_INTC1);
276 nphy->rfctrl_intc2_save = b43_phy_read(dev,
277 B43_NPHY_RFCTL_INTC2);
278 band = b43_current_band(dev->wl);
279 if (dev->phy.rev >= 3) {
280 if (band == IEEE80211_BAND_5GHZ)
285 if (band == IEEE80211_BAND_5GHZ)
290 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
291 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
293 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
294 nphy->rfctrl_intc1_save);
295 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
296 nphy->rfctrl_intc2_save);
300 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
301 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
303 struct b43_phy_n *nphy = dev->phy.n;
305 enum ieee80211_band band = b43_current_band(dev->wl);
306 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
307 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
309 if (dev->phy.rev >= 3) {
312 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
313 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
317 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
318 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
322 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
323 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
327 if (dev->phy.type != B43_PHYTYPE_N)
330 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
332 tmslow |= SSB_TMSLOW_FGC;
334 tmslow &= ~SSB_TMSLOW_FGC;
335 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
338 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
339 static void b43_nphy_reset_cca(struct b43_wldev *dev)
343 b43_nphy_bmac_clock_fgc(dev, 1);
344 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
345 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
347 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
348 b43_nphy_bmac_clock_fgc(dev, 0);
349 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
352 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
353 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
355 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
357 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
359 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
361 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
363 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
366 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
367 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
369 struct b43_phy_n *nphy = dev->phy.n;
371 bool override = false;
374 if (nphy->txrx_chain == 0) {
377 } else if (nphy->txrx_chain == 1) {
382 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
383 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
387 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
388 B43_NPHY_RFSEQMODE_CAOVER);
390 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
391 ~B43_NPHY_RFSEQMODE_CAOVER);
394 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
395 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
396 u16 samps, u8 time, bool wait)
401 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
402 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
404 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
406 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
408 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
410 for (i = 1000; i; i--) {
411 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
412 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
413 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
414 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
415 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
416 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
417 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
418 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
420 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
421 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
422 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
423 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
424 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
425 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
430 memset(est, 0, sizeof(*est));
433 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
434 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
435 struct b43_phy_n_iq_comp *pcomp)
438 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
439 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
440 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
441 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
443 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
444 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
445 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
446 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
450 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
451 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
453 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
455 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
457 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
458 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
460 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
461 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
463 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
464 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
465 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
466 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
467 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
468 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
469 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
470 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
473 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
474 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
477 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
479 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
481 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
482 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
484 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
485 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
487 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
488 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
489 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
490 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
491 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
492 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
493 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
494 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
496 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
497 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
499 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
500 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
501 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
502 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
503 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
504 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
505 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
506 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
509 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
510 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
512 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
513 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
516 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
517 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
518 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
527 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
528 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
531 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
532 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
538 int iq_nbits, qq_nbits;
542 struct nphy_iq_est est;
543 struct b43_phy_n_iq_comp old;
544 struct b43_phy_n_iq_comp new = { };
550 b43_nphy_rx_iq_coeffs(dev, false, &old);
551 b43_nphy_rx_iq_coeffs(dev, true, &new);
552 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
555 for (i = 0; i < 2; i++) {
556 if (i == 0 && (mask & 1)) {
560 } else if (i == 1 && (mask & 2)) {
574 iq_nbits = fls(abs(iq));
577 arsh = iq_nbits - 20;
579 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
582 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
591 brsh = qq_nbits - 11;
593 b = (qq << (31 - qq_nbits));
596 b = (qq << (31 - qq_nbits));
603 b = int_sqrt(b / tmp - a * a) - (1 << 10);
605 if (i == 0 && (mask & 0x1)) {
606 if (dev->phy.rev >= 3) {
613 } else if (i == 1 && (mask & 0x2)) {
614 if (dev->phy.rev >= 3) {
627 b43_nphy_rx_iq_coeffs(dev, true, &new);
630 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
631 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
636 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
637 for (i = 0; i < 4; i++)
638 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
640 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
641 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
642 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
643 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
646 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
647 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
649 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
650 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
653 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
654 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
656 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
657 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
660 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
661 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
663 if (dev->phy.rev >= 3) {
667 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
668 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
669 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
670 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
673 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
674 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
676 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
678 b43_write32(dev, B43_MMIO_MACCTL,
679 b43_read32(dev, B43_MMIO_MACCTL) &
680 ~B43_MACCTL_GPOUTSMSK);
681 b43_write16(dev, B43_MMIO_GPIO_MASK,
682 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
683 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
684 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
687 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
688 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
689 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
690 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
695 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
696 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
700 if (dev->dev->id.revision == 16)
701 b43_mac_suspend(dev);
703 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
704 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
705 B43_NPHY_CLASSCTL_WAITEDEN);
708 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
710 if (dev->dev->id.revision == 16)
716 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
717 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
719 struct b43_phy *phy = &dev->phy;
720 struct b43_phy_n *nphy = phy->n;
723 u16 clip[] = { 0xFFFF, 0xFFFF };
724 if (nphy->deaf_count++ == 0) {
725 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
726 b43_nphy_classifier(dev, 0x7, 0);
727 b43_nphy_read_clip_detection(dev, nphy->clip_state);
728 b43_nphy_write_clip_detection(dev, clip);
730 b43_nphy_reset_cca(dev);
732 if (--nphy->deaf_count == 0) {
733 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
734 b43_nphy_write_clip_detection(dev, nphy->clip_state);
739 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
740 static void b43_nphy_stop_playback(struct b43_wldev *dev)
742 struct b43_phy_n *nphy = dev->phy.n;
745 if (nphy->hang_avoid)
746 b43_nphy_stay_in_carrier_search(dev, 1);
748 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
750 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
752 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
754 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
756 if (nphy->bb_mult_save & 0x80000000) {
757 tmp = nphy->bb_mult_save & 0xFFFF;
758 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
759 nphy->bb_mult_save = 0;
762 if (nphy->hang_avoid)
763 b43_nphy_stay_in_carrier_search(dev, 0);
766 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
767 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
769 struct b43_phy_n *nphy = dev->phy.n;
771 unsigned int channel;
772 int tone[2] = { 57, 58 };
773 u32 noise[2] = { 0x3FF, 0x3FF };
775 B43_WARN_ON(dev->phy.rev < 3);
777 if (nphy->hang_avoid)
778 b43_nphy_stay_in_carrier_search(dev, 1);
780 /* FIXME: channel = radio_chanspec */
782 if (nphy->gband_spurwar_en) {
783 /* TODO: N PHY Adjust Analog Pfbw (7) */
784 if (channel == 11 && dev->phy.is_40mhz)
785 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
787 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
788 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
791 if (nphy->aband_spurwar_en) {
795 } else if (channel == 38 || channel == 102 || channel == 118) {
803 } else if (channel == 134) {
806 } else if (channel == 151) {
809 } else if (channel == 153 || channel == 161) {
817 if (!tone[0] && !noise[0])
818 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
820 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
823 if (nphy->hang_avoid)
824 b43_nphy_stay_in_carrier_search(dev, 0);
827 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
828 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
830 struct b43_phy_n *nphy = dev->phy.n;
834 /* TODO: for PHY >= 3
835 s8 *lna1_gain, *lna2_gain;
836 u8 *gain_db, *gain_bits;
838 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
839 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
842 u8 rfseq_events[3] = { 6, 8, 7 };
843 u8 rfseq_delays[3] = { 10, 30, 1 };
845 if (dev->phy.rev >= 3) {
848 /* Set Clip 2 detect */
849 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
850 B43_NPHY_C1_CGAINI_CL2DETECT);
851 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
852 B43_NPHY_C2_CGAINI_CL2DETECT);
854 /* Set narrowband clip threshold */
855 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
856 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
858 if (!dev->phy.is_40mhz) {
859 /* Set dwell lengths */
860 b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
861 b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
862 b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
863 b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
866 /* Set wideband clip 2 threshold */
867 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
868 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
870 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
871 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
874 if (!dev->phy.is_40mhz) {
875 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
876 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
877 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
878 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
879 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
880 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
881 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
882 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
885 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
887 if (nphy->gain_boost) {
888 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
894 code = dev->phy.is_40mhz ? 6 : 7;
897 /* Set HPVGA2 index */
898 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
899 ~B43_NPHY_C1_INITGAIN_HPVGA2,
900 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
901 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
902 ~B43_NPHY_C2_INITGAIN_HPVGA2,
903 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
905 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
906 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
908 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
911 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
913 if (nphy->elna_gain_config) {
914 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
915 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
916 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
917 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
918 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
920 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
921 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
922 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
923 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
924 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
926 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
927 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
929 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
933 if (dev->phy.rev == 2) {
934 for (i = 0; i < 4; i++) {
935 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
936 (0x0400 * i) + 0x0020);
937 for (j = 0; j < 21; j++)
939 B43_NPHY_TABLE_DATALO, 3 * j);
942 b43_nphy_set_rf_sequence(dev, 5,
943 rfseq_events, rfseq_delays, 3);
944 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
945 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
946 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
948 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
949 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
955 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
956 static void b43_nphy_workarounds(struct b43_wldev *dev)
958 struct ssb_bus *bus = dev->dev->bus;
959 struct b43_phy *phy = &dev->phy;
960 struct b43_phy_n *nphy = phy->n;
962 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
963 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
965 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
966 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
968 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
969 b43_nphy_classifier(dev, 1, 0);
971 b43_nphy_classifier(dev, 1, 1);
973 if (nphy->hang_avoid)
974 b43_nphy_stay_in_carrier_search(dev, 1);
976 b43_phy_set(dev, B43_NPHY_IQFLIP,
977 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
979 if (dev->phy.rev >= 3) {
982 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
983 nphy->band5g_pwrgain) {
984 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
985 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
987 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
988 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
991 /* TODO: convert to b43_ntab_write? */
992 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
993 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
994 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
995 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
996 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
997 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
998 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
999 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1001 if (dev->phy.rev < 2) {
1002 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1003 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1004 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1005 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1006 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1007 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1008 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1009 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1010 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1011 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1012 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1013 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1016 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1017 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1018 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1019 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1021 if (bus->sprom.boardflags2_lo & 0x100 &&
1022 bus->boardinfo.type == 0x8B) {
1026 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1027 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1029 b43_nphy_gain_crtl_workarounds(dev);
1031 if (dev->phy.rev < 2) {
1032 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1033 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
1034 } else if (dev->phy.rev == 2) {
1035 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1036 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1039 if (dev->phy.rev < 2)
1040 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1041 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1043 /* Set phase track alpha and beta */
1044 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1045 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1046 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1047 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1048 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1049 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1051 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1052 (u16)~B43_NPHY_PIL_DW_64QAM);
1053 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1054 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1055 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1057 if (dev->phy.rev == 2)
1058 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1059 B43_NPHY_FINERX2_CGC_DECGC);
1062 if (nphy->hang_avoid)
1063 b43_nphy_stay_in_carrier_search(dev, 0);
1066 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1067 static int b43_nphy_load_samples(struct b43_wldev *dev,
1068 struct b43_c32 *samples, u16 len) {
1069 struct b43_phy_n *nphy = dev->phy.n;
1073 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1075 b43err(dev->wl, "allocation for samples loading failed\n");
1078 if (nphy->hang_avoid)
1079 b43_nphy_stay_in_carrier_search(dev, 1);
1081 for (i = 0; i < len; i++) {
1082 data[i] = (samples[i].i & 0x3FF << 10);
1083 data[i] |= samples[i].q & 0x3FF;
1085 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1088 if (nphy->hang_avoid)
1089 b43_nphy_stay_in_carrier_search(dev, 0);
1093 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1094 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1098 u16 bw, len, rot, angle;
1099 struct b43_c32 *samples;
1102 bw = (dev->phy.is_40mhz) ? 40 : 20;
1106 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1111 if (dev->phy.is_40mhz)
1117 samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1119 b43err(dev->wl, "allocation for samples generation failed\n");
1122 rot = (((freq * 36) / bw) << 16) / 100;
1125 for (i = 0; i < len; i++) {
1126 samples[i] = b43_cordic(angle);
1128 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1129 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1132 i = b43_nphy_load_samples(dev, samples, len);
1134 return (i < 0) ? 0 : len;
1137 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1138 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1139 u16 wait, bool iqmode, bool dac_test)
1141 struct b43_phy_n *nphy = dev->phy.n;
1146 if (nphy->hang_avoid)
1147 b43_nphy_stay_in_carrier_search(dev, true);
1149 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1150 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1151 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1154 if (!dev->phy.is_40mhz)
1158 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1160 if (nphy->hang_avoid)
1161 b43_nphy_stay_in_carrier_search(dev, false);
1163 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1165 if (loops != 0xFFFF)
1166 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1168 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1170 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1172 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1174 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1176 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1177 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1180 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1182 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1184 for (i = 0; i < 100; i++) {
1185 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1192 b43err(dev->wl, "run samples timeout\n");
1194 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1198 * Transmits a known value for LO calibration
1199 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1201 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1202 bool iqmode, bool dac_test)
1204 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1207 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1211 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1212 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1214 struct b43_phy_n *nphy = dev->phy.n;
1217 u32 cur_real, cur_imag, real_part, imag_part;
1221 if (nphy->hang_avoid)
1222 b43_nphy_stay_in_carrier_search(dev, true);
1224 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1226 for (i = 0; i < 2; i++) {
1227 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1228 (buffer[i * 2 + 1] & 0x3FF);
1229 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1230 (((i + 26) << 10) | 320));
1231 for (j = 0; j < 128; j++) {
1232 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1233 ((tmp >> 16) & 0xFFFF));
1234 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1239 for (i = 0; i < 2; i++) {
1240 tmp = buffer[5 + i];
1241 real_part = (tmp >> 8) & 0xFF;
1242 imag_part = (tmp & 0xFF);
1243 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1244 (((i + 26) << 10) | 448));
1246 if (dev->phy.rev >= 3) {
1247 cur_real = real_part;
1248 cur_imag = imag_part;
1249 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1252 for (j = 0; j < 128; j++) {
1253 if (dev->phy.rev < 3) {
1254 cur_real = (real_part * loscale[j] + 128) >> 8;
1255 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1256 tmp = ((cur_real & 0xFF) << 8) |
1259 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1260 ((tmp >> 16) & 0xFFFF));
1261 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1266 if (dev->phy.rev >= 3) {
1267 b43_shm_write16(dev, B43_SHM_SHARED,
1268 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1269 b43_shm_write16(dev, B43_SHM_SHARED,
1270 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1273 if (nphy->hang_avoid)
1274 b43_nphy_stay_in_carrier_search(dev, false);
1277 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1278 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1279 u8 *events, u8 *delays, u8 length)
1281 struct b43_phy_n *nphy = dev->phy.n;
1283 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1284 u16 offset1 = cmd << 4;
1285 u16 offset2 = offset1 + 0x80;
1287 if (nphy->hang_avoid)
1288 b43_nphy_stay_in_carrier_search(dev, true);
1290 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1291 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1293 for (i = length; i < 16; i++) {
1294 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1295 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1298 if (nphy->hang_avoid)
1299 b43_nphy_stay_in_carrier_search(dev, false);
1302 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1303 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1304 enum b43_nphy_rf_sequence seq)
1306 static const u16 trigger[] = {
1307 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1308 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1309 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1310 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1311 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1312 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1315 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1317 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1319 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1320 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1321 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1322 for (i = 0; i < 200; i++) {
1323 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1327 b43err(dev->wl, "RF sequence status timeout\n");
1329 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1332 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1333 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1334 u16 value, u8 core, bool off)
1337 u8 index = fls(field);
1338 u8 addr, en_addr, val_addr;
1339 /* we expect only one bit set */
1340 B43_WARN_ON(field & (~(1 << (index - 1))));
1342 if (dev->phy.rev >= 3) {
1343 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1344 for (i = 0; i < 2; i++) {
1345 if (index == 0 || index == 16) {
1347 "Unsupported RF Ctrl Override call\n");
1351 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1352 en_addr = B43_PHY_N((i == 0) ?
1353 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1354 val_addr = B43_PHY_N((i == 0) ?
1355 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1358 b43_phy_mask(dev, en_addr, ~(field));
1359 b43_phy_mask(dev, val_addr,
1360 ~(rf_ctrl->val_mask));
1362 if (core == 0 || ((1 << core) & i) != 0) {
1363 b43_phy_set(dev, en_addr, field);
1364 b43_phy_maskset(dev, val_addr,
1365 ~(rf_ctrl->val_mask),
1366 (value << rf_ctrl->val_shift));
1371 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1373 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1376 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1379 for (i = 0; i < 2; i++) {
1380 if (index <= 1 || index == 16) {
1382 "Unsupported RF Ctrl Override call\n");
1386 if (index == 2 || index == 10 ||
1387 (index >= 13 && index <= 15)) {
1391 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1392 addr = B43_PHY_N((i == 0) ?
1393 rf_ctrl->addr0 : rf_ctrl->addr1);
1395 if ((core & (1 << i)) != 0)
1396 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1397 (value << rf_ctrl->shift));
1399 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1400 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1401 B43_NPHY_RFCTL_CMD_START);
1403 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1408 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1409 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1415 B43_WARN_ON(dev->phy.rev < 3);
1416 B43_WARN_ON(field > 4);
1418 for (i = 0; i < 2; i++) {
1419 if ((core == 1 && i == 1) || (core == 2 && !i))
1423 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1424 b43_phy_mask(dev, reg, 0xFBFF);
1428 b43_phy_write(dev, reg, 0);
1429 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1433 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1434 0xFC3F, (value << 6));
1435 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1437 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1438 B43_NPHY_RFCTL_CMD_START);
1439 for (j = 0; j < 100; j++) {
1440 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1448 "intc override timeout\n");
1449 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1452 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1453 0xFC3F, (value << 6));
1454 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1456 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1457 B43_NPHY_RFCTL_CMD_RXTX);
1458 for (j = 0; j < 100; j++) {
1459 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1467 "intc override timeout\n");
1468 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1473 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1480 b43_phy_maskset(dev, reg, ~tmp, val);
1483 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1490 b43_phy_maskset(dev, reg, ~tmp, val);
1493 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1500 b43_phy_maskset(dev, reg, ~tmp, val);
1506 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1512 for (i = 0; i < 14; i++) {
1513 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1517 for (i = 0; i < 16; i++) {
1518 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1521 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1524 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1525 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1526 s8 offset, u8 core, u8 rail, u8 type)
1529 bool core1or5 = (core == 1) || (core == 5);
1530 bool core2or5 = (core == 2) || (core == 5);
1532 offset = clamp_val(offset, -32, 31);
1533 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1535 if (core1or5 && (rail == 0) && (type == 2))
1536 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1537 if (core1or5 && (rail == 1) && (type == 2))
1538 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1539 if (core2or5 && (rail == 0) && (type == 2))
1540 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1541 if (core2or5 && (rail == 1) && (type == 2))
1542 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1543 if (core1or5 && (rail == 0) && (type == 0))
1544 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1545 if (core1or5 && (rail == 1) && (type == 0))
1546 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1547 if (core2or5 && (rail == 0) && (type == 0))
1548 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1549 if (core2or5 && (rail == 1) && (type == 0))
1550 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1551 if (core1or5 && (rail == 0) && (type == 1))
1552 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1553 if (core1or5 && (rail == 1) && (type == 1))
1554 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1555 if (core2or5 && (rail == 0) && (type == 1))
1556 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1557 if (core2or5 && (rail == 1) && (type == 1))
1558 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1559 if (core1or5 && (rail == 0) && (type == 6))
1560 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1561 if (core1or5 && (rail == 1) && (type == 6))
1562 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1563 if (core2or5 && (rail == 0) && (type == 6))
1564 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1565 if (core2or5 && (rail == 1) && (type == 6))
1566 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1567 if (core1or5 && (rail == 0) && (type == 3))
1568 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1569 if (core1or5 && (rail == 1) && (type == 3))
1570 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1571 if (core2or5 && (rail == 0) && (type == 3))
1572 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1573 if (core2or5 && (rail == 1) && (type == 3))
1574 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1575 if (core1or5 && (type == 4))
1576 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1577 if (core2or5 && (type == 4))
1578 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1579 if (core1or5 && (type == 5))
1580 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1581 if (core2or5 && (type == 5))
1582 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1585 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1598 val = (val << 12) | (val << 14);
1599 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1600 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1603 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1605 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1609 /* TODO use some definitions */
1611 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1613 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1614 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1615 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1617 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1620 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1623 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1625 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1626 0xEFDC, (code << 1 | 0x1021));
1627 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1629 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1634 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1636 struct b43_phy_n *nphy = dev->phy.n;
1641 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1642 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1643 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1644 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1645 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1646 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1647 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1648 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1650 for (i = 0; i < 2; i++) {
1651 if ((code == 1 && i == 1) || (code == 2 && !i))
1655 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1656 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1660 B43_NPHY_AFECTL_C1 :
1662 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1665 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1666 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1667 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1670 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1675 b43_phy_set(dev, reg, val);
1678 B43_NPHY_TXF_40CO_B1S0 :
1679 B43_NPHY_TXF_40CO_B32S1;
1680 b43_phy_set(dev, reg, 0x0020);
1690 B43_NPHY_AFECTL_C1 :
1693 b43_phy_maskset(dev, reg, 0xFCFF, val);
1694 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1696 if (type != 3 && type != 6) {
1697 enum ieee80211_band band =
1698 b43_current_band(dev->wl);
1700 if ((nphy->ipa2g_on &&
1701 band == IEEE80211_BAND_2GHZ) ||
1703 band == IEEE80211_BAND_5GHZ))
1704 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1707 reg = (i == 0) ? 0x2000 : 0x3000;
1708 reg |= B2055_PADDRV;
1709 b43_radio_write16(dev, reg, val);
1712 B43_NPHY_AFECTL_OVER1 :
1713 B43_NPHY_AFECTL_OVER;
1714 b43_phy_set(dev, reg, 0x0200);
1721 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1722 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1724 if (dev->phy.rev >= 3)
1725 b43_nphy_rev3_rssi_select(dev, code, type);
1727 b43_nphy_rev2_rssi_select(dev, code, type);
1730 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1731 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1734 for (i = 0; i < 2; i++) {
1737 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1739 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1742 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1744 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1745 0xFC, buf[2 * i + 1]);
1749 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1752 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1753 0xF3, buf[2 * i + 1] << 2);
1758 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1759 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1764 u16 save_regs_phy[9];
1767 if (dev->phy.rev >= 3) {
1768 save_regs_phy[0] = b43_phy_read(dev,
1769 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1770 save_regs_phy[1] = b43_phy_read(dev,
1771 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1772 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1773 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1774 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1775 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1776 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1777 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1780 b43_nphy_rssi_select(dev, 5, type);
1782 if (dev->phy.rev < 2) {
1783 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1784 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1787 for (i = 0; i < 4; i++)
1790 for (i = 0; i < nsamp; i++) {
1791 if (dev->phy.rev < 2) {
1792 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1793 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1795 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1796 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1799 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1800 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1801 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1802 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1804 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1805 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1807 if (dev->phy.rev < 2)
1808 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1810 if (dev->phy.rev >= 3) {
1811 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1813 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1815 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1816 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1817 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1818 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1819 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1820 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1826 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1827 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1832 u16 class, override;
1833 u8 regs_save_radio[2];
1834 u16 regs_save_phy[2];
1838 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1839 s32 results_min[4] = { };
1840 u8 vcm_final[4] = { };
1841 s32 results[4][4] = { };
1842 s32 miniq[4][2] = { };
1847 } else if (type < 2) {
1855 class = b43_nphy_classifier(dev, 0, 0);
1856 b43_nphy_classifier(dev, 7, 4);
1857 b43_nphy_read_clip_detection(dev, clip_state);
1858 b43_nphy_write_clip_detection(dev, clip_off);
1860 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1865 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1866 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1867 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1868 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1870 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1871 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1872 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1873 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1875 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1876 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1877 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1878 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1879 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1880 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1882 b43_nphy_rssi_select(dev, 5, type);
1883 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1884 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1886 for (i = 0; i < 4; i++) {
1888 for (j = 0; j < 4; j++)
1891 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1892 b43_nphy_poll_rssi(dev, type, results[i], 8);
1894 for (j = 0; j < 2; j++)
1895 miniq[i][j] = min(results[i][2 * j],
1896 results[i][2 * j + 1]);
1899 for (i = 0; i < 4; i++) {
1904 for (j = 0; j < 4; j++) {
1906 curr = abs(results[j][i]);
1908 curr = abs(miniq[j][i / 2] - code * 8);
1915 if (results[j][i] < minpoll)
1916 minpoll = results[j][i];
1918 results_min[i] = minpoll;
1919 vcm_final[i] = minvcm;
1923 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1925 for (i = 0; i < 4; i++) {
1926 offset[i] = (code * 8) - results[vcm_final[i]][i];
1929 offset[i] = -((abs(offset[i]) + 4) / 8);
1931 offset[i] = (offset[i] + 4) / 8;
1933 if (results_min[i] == 248)
1934 offset[i] = code - 32;
1937 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1940 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1944 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1945 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1949 b43_nphy_rssi_select(dev, 1, 2);
1952 b43_nphy_rssi_select(dev, 1, 0);
1955 b43_nphy_rssi_select(dev, 1, 1);
1958 b43_nphy_rssi_select(dev, 1, 1);
1964 b43_nphy_rssi_select(dev, 2, 2);
1967 b43_nphy_rssi_select(dev, 2, 0);
1970 b43_nphy_rssi_select(dev, 2, 1);
1974 b43_nphy_rssi_select(dev, 0, type);
1976 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1977 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1978 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1979 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1981 b43_nphy_classifier(dev, 7, class);
1982 b43_nphy_write_clip_detection(dev, clip_state);
1985 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1986 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1993 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1995 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1997 if (dev->phy.rev >= 3) {
1998 b43_nphy_rev3_rssi_cal(dev);
2000 b43_nphy_rev2_rssi_cal(dev, 2);
2001 b43_nphy_rev2_rssi_cal(dev, 0);
2002 b43_nphy_rev2_rssi_cal(dev, 1);
2007 * Restore RSSI Calibration
2008 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2010 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2012 struct b43_phy_n *nphy = dev->phy.n;
2014 u16 *rssical_radio_regs = NULL;
2015 u16 *rssical_phy_regs = NULL;
2017 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2018 if (!nphy->rssical_chanspec_2G)
2020 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2021 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2023 if (!nphy->rssical_chanspec_5G)
2025 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2026 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2029 /* TODO use some definitions */
2030 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2031 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2033 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2034 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2035 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2036 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2038 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2039 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2040 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2041 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2043 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2044 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2045 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2046 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2049 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2050 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2052 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2053 if (dev->phy.rev >= 6) {
2054 /* TODO If the chip is 47162
2055 return txpwrctrl_tx_gain_ipa_rev5 */
2056 return txpwrctrl_tx_gain_ipa_rev6;
2057 } else if (dev->phy.rev >= 5) {
2058 return txpwrctrl_tx_gain_ipa_rev5;
2060 return txpwrctrl_tx_gain_ipa;
2063 return txpwrctrl_tx_gain_ipa_5g;
2067 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2068 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2070 struct b43_phy_n *nphy = dev->phy.n;
2071 u16 *save = nphy->tx_rx_cal_radio_saveregs;
2075 if (dev->phy.rev >= 3) {
2076 for (i = 0; i < 2; i++) {
2077 tmp = (i == 0) ? 0x2000 : 0x3000;
2080 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2081 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2082 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2083 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2084 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2085 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2086 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2087 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2088 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2089 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2090 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2092 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2093 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2094 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2095 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2096 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2097 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2098 if (nphy->ipa5g_on) {
2099 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2100 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2102 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2103 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2105 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2107 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2108 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2109 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2110 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2111 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2112 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2113 if (nphy->ipa2g_on) {
2114 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2115 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2116 (dev->phy.rev < 5) ? 0x11 : 0x01);
2118 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2119 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2122 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2123 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2124 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2127 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2128 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2130 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2131 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2133 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2134 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2136 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2137 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2139 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2140 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2142 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2143 B43_NPHY_BANDCTL_5GHZ)) {
2144 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2145 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2147 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2148 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2151 if (dev->phy.rev < 2) {
2152 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2153 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2155 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2156 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2161 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2162 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2163 struct nphy_txgains target,
2164 struct nphy_iqcal_params *params)
2169 if (dev->phy.rev >= 3) {
2170 params->txgm = target.txgm[core];
2171 params->pga = target.pga[core];
2172 params->pad = target.pad[core];
2173 params->ipa = target.ipa[core];
2174 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2175 (params->pad << 4) | (params->ipa);
2176 for (j = 0; j < 5; j++)
2177 params->ncorr[j] = 0x79;
2179 gain = (target.pad[core]) | (target.pga[core] << 4) |
2180 (target.txgm[core] << 8);
2182 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2184 for (i = 0; i < 9; i++)
2185 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2189 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2190 params->pga = tbl_iqcal_gainparams[indx][i][2];
2191 params->pad = tbl_iqcal_gainparams[indx][i][3];
2192 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2194 for (j = 0; j < 4; j++)
2195 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2199 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2200 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2202 struct b43_phy_n *nphy = dev->phy.n;
2206 u16 tmp = nphy->txcal_bbmult;
2211 for (i = 0; i < 18; i++) {
2212 scale = (ladder_lo[i].percent * tmp) / 100;
2213 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2214 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2216 scale = (ladder_iq[i].percent * tmp) / 100;
2217 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2218 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2222 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2223 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2226 for (i = 0; i < 15; i++)
2227 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2228 tbl_tx_filter_coef_rev4[2][i]);
2231 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2232 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2235 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2236 u16 offset[] = { 0x186, 0x195, 0x2C5 };
2238 for (i = 0; i < 3; i++)
2239 for (j = 0; j < 15; j++)
2240 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2241 tbl_tx_filter_coef_rev4[i][j]);
2243 if (dev->phy.is_40mhz) {
2244 for (j = 0; j < 15; j++)
2245 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2246 tbl_tx_filter_coef_rev4[3][j]);
2247 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2248 for (j = 0; j < 15; j++)
2249 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2250 tbl_tx_filter_coef_rev4[5][j]);
2253 if (dev->phy.channel == 14)
2254 for (j = 0; j < 15; j++)
2255 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2256 tbl_tx_filter_coef_rev4[6][j]);
2259 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2260 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2262 struct b43_phy_n *nphy = dev->phy.n;
2265 struct nphy_txgains target;
2266 const u32 *table = NULL;
2268 if (nphy->txpwrctrl == 0) {
2271 if (nphy->hang_avoid)
2272 b43_nphy_stay_in_carrier_search(dev, true);
2273 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2274 if (nphy->hang_avoid)
2275 b43_nphy_stay_in_carrier_search(dev, false);
2277 for (i = 0; i < 2; ++i) {
2278 if (dev->phy.rev >= 3) {
2279 target.ipa[i] = curr_gain[i] & 0x000F;
2280 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2281 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2282 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2284 target.ipa[i] = curr_gain[i] & 0x0003;
2285 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2286 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2287 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2293 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2294 B43_NPHY_TXPCTL_STAT_BIDX) >>
2295 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2296 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2297 B43_NPHY_TXPCTL_STAT_BIDX) >>
2298 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2300 for (i = 0; i < 2; ++i) {
2301 if (dev->phy.rev >= 3) {
2302 enum ieee80211_band band =
2303 b43_current_band(dev->wl);
2305 if ((nphy->ipa2g_on &&
2306 band == IEEE80211_BAND_2GHZ) ||
2308 band == IEEE80211_BAND_5GHZ)) {
2309 table = b43_nphy_get_ipa_gain_table(dev);
2311 if (band == IEEE80211_BAND_5GHZ) {
2312 if (dev->phy.rev == 3)
2313 table = b43_ntab_tx_gain_rev3_5ghz;
2314 else if (dev->phy.rev == 4)
2315 table = b43_ntab_tx_gain_rev4_5ghz;
2317 table = b43_ntab_tx_gain_rev5plus_5ghz;
2319 table = b43_ntab_tx_gain_rev3plus_2ghz;
2323 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2324 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2325 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2326 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2328 table = b43_ntab_tx_gain_rev0_1_2;
2330 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2331 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2332 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2333 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2342 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2344 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2346 if (dev->phy.rev >= 3) {
2347 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2348 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2349 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2350 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2351 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2352 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2353 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2354 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2355 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2356 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2357 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2358 b43_nphy_reset_cca(dev);
2360 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2361 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2362 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2363 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2364 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2365 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2366 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2370 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2371 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2373 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2376 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2377 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2378 if (dev->phy.rev >= 3) {
2379 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2380 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2382 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2384 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2386 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2388 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2390 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2391 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2393 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2395 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2397 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2399 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2400 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2401 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2403 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2404 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2405 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2407 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2408 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2409 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2410 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2412 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2413 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2414 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2416 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2417 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2420 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2421 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2424 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2425 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2426 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2427 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2431 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2432 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2436 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2437 static void b43_nphy_save_cal(struct b43_wldev *dev)
2439 struct b43_phy_n *nphy = dev->phy.n;
2441 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2442 u16 *txcal_radio_regs = NULL;
2446 if (nphy->hang_avoid)
2447 b43_nphy_stay_in_carrier_search(dev, 1);
2449 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2450 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2451 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2452 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2453 table = nphy->cal_cache.txcal_coeffs_2G;
2455 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2456 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2457 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2458 table = nphy->cal_cache.txcal_coeffs_5G;
2461 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2462 /* TODO use some definitions */
2463 if (dev->phy.rev >= 3) {
2464 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2465 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2466 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2467 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2468 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2469 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2470 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2471 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2473 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2474 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2475 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2476 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2478 *iqcal_chanspec = nphy->radio_chanspec;
2479 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2481 if (nphy->hang_avoid)
2482 b43_nphy_stay_in_carrier_search(dev, 0);
2485 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2486 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2488 struct b43_phy_n *nphy = dev->phy.n;
2495 u16 *txcal_radio_regs = NULL;
2496 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2498 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2499 if (nphy->iqcal_chanspec_2G == 0)
2501 table = nphy->cal_cache.txcal_coeffs_2G;
2502 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2504 if (nphy->iqcal_chanspec_5G == 0)
2506 table = nphy->cal_cache.txcal_coeffs_5G;
2507 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2510 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2512 for (i = 0; i < 4; i++) {
2513 if (dev->phy.rev >= 3)
2519 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2520 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2521 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2523 if (dev->phy.rev < 2)
2524 b43_nphy_tx_iq_workaround(dev);
2526 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2527 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2528 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2530 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2531 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2534 /* TODO use some definitions */
2535 if (dev->phy.rev >= 3) {
2536 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2537 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2538 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2539 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2540 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2541 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2542 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2543 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2545 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2546 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2547 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2548 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2550 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2553 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2554 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2555 struct nphy_txgains target,
2556 bool full, bool mphase)
2558 struct b43_phy_n *nphy = dev->phy.n;
2564 u16 tmp, core, type, count, max, numb, last, cmd;
2572 struct nphy_iqcal_params params[2];
2573 bool updated[2] = { };
2575 b43_nphy_stay_in_carrier_search(dev, true);
2577 if (dev->phy.rev >= 4) {
2578 avoid = nphy->hang_avoid;
2579 nphy->hang_avoid = 0;
2582 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2584 for (i = 0; i < 2; i++) {
2585 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
2586 gain[i] = params[i].cal_gain;
2589 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2591 b43_nphy_tx_cal_radio_setup(dev);
2592 b43_nphy_tx_cal_phy_setup(dev);
2594 phy6or5x = dev->phy.rev >= 6 ||
2595 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2596 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2598 if (dev->phy.is_40mhz) {
2599 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2600 tbl_tx_iqlo_cal_loft_ladder_40);
2601 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2602 tbl_tx_iqlo_cal_iqimb_ladder_40);
2604 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2605 tbl_tx_iqlo_cal_loft_ladder_20);
2606 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2607 tbl_tx_iqlo_cal_iqimb_ladder_20);
2611 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2613 if (!dev->phy.is_40mhz)
2618 if (nphy->mphase_cal_phase_id > 2)
2619 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2620 0xFFFF, 0, true, false);
2622 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2625 if (nphy->mphase_cal_phase_id > 2) {
2626 table = nphy->mphase_txcal_bestcoeffs;
2628 if (dev->phy.rev < 3)
2631 if (!full && nphy->txiqlocal_coeffsvalid) {
2632 table = nphy->txiqlocal_bestc;
2634 if (dev->phy.rev < 3)
2638 if (dev->phy.rev >= 3) {
2639 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2640 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2642 table = tbl_tx_iqlo_cal_startcoefs;
2643 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2648 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2651 if (dev->phy.rev >= 3)
2652 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2654 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2656 if (dev->phy.rev >= 3)
2657 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2659 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2663 count = nphy->mphase_txcal_cmdidx;
2665 (u16)(count + nphy->mphase_txcal_numcmds));
2671 for (; count < numb; count++) {
2673 if (dev->phy.rev >= 3)
2674 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2676 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2678 if (dev->phy.rev >= 3)
2679 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2681 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2684 core = (cmd & 0x3000) >> 12;
2685 type = (cmd & 0x0F00) >> 8;
2687 if (phy6or5x && updated[core] == 0) {
2688 b43_nphy_update_tx_cal_ladder(dev, core);
2692 tmp = (params[core].ncorr[type] << 8) | 0x66;
2693 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2695 if (type == 1 || type == 3 || type == 4) {
2696 buffer[0] = b43_ntab_read(dev,
2697 B43_NTAB16(15, 69 + core));
2698 diq_start = buffer[0];
2700 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2704 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2705 for (i = 0; i < 2000; i++) {
2706 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2712 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2714 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2717 if (type == 1 || type == 3 || type == 4)
2718 buffer[0] = diq_start;
2722 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2724 last = (dev->phy.rev < 3) ? 6 : 7;
2726 if (!mphase || nphy->mphase_cal_phase_id == last) {
2727 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2728 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2729 if (dev->phy.rev < 3) {
2735 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2737 b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2739 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2741 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2744 if (dev->phy.rev < 3)
2746 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2747 nphy->txiqlocal_bestc);
2748 nphy->txiqlocal_coeffsvalid = true;
2749 /* TODO: Set nphy->txiqlocal_chanspec to
2750 the current channel */
2753 if (dev->phy.rev < 3)
2755 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2756 nphy->mphase_txcal_bestcoeffs);
2759 b43_nphy_stop_playback(dev);
2760 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2763 b43_nphy_tx_cal_phy_cleanup(dev);
2764 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2766 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2767 b43_nphy_tx_iq_workaround(dev);
2769 if (dev->phy.rev >= 4)
2770 nphy->hang_avoid = avoid;
2772 b43_nphy_stay_in_carrier_search(dev, false);
2777 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2778 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2780 struct b43_phy_n *nphy = dev->phy.n;
2785 if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */)
2788 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2789 for (i = 0; i < 4; i++) {
2790 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2797 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2798 nphy->txiqlocal_bestc);
2799 for (i = 0; i < 4; i++)
2801 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2803 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2804 &nphy->txiqlocal_bestc[5]);
2805 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2806 &nphy->txiqlocal_bestc[5]);
2810 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2811 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2812 struct nphy_txgains target, u8 type, bool debug)
2814 struct b43_phy_n *nphy = dev->phy.n;
2819 u16 cur_hpf1, cur_hpf2, cur_lna;
2821 enum ieee80211_band band;
2825 u16 lna[3] = { 3, 3, 1 };
2826 u16 hpf1[3] = { 7, 2, 0 };
2827 u16 hpf2[3] = { 2, 0, 0 };
2831 struct nphy_iqcal_params cal_params[2];
2832 struct nphy_iq_est est;
2834 bool playtone = true;
2837 b43_nphy_stay_in_carrier_search(dev, 1);
2839 if (dev->phy.rev < 2)
2840 b43_nphy_reapply_tx_cal_coeffs(dev);
2841 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2842 for (i = 0; i < 2; i++) {
2843 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2844 cal_gain[i] = cal_params[i].cal_gain;
2846 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2848 for (i = 0; i < 2; i++) {
2850 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2851 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2852 afectl_core = B43_NPHY_AFECTL_C1;
2854 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2855 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2856 afectl_core = B43_NPHY_AFECTL_C2;
2859 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2860 tmp[2] = b43_phy_read(dev, afectl_core);
2861 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2862 tmp[4] = b43_phy_read(dev, rfctl[0]);
2863 tmp[5] = b43_phy_read(dev, rfctl[1]);
2865 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2866 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2867 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2868 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2870 b43_phy_set(dev, afectl_core, 0x0006);
2871 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2873 band = b43_current_band(dev->wl);
2875 if (nphy->rxcalparams & 0xFF000000) {
2876 if (band == IEEE80211_BAND_5GHZ)
2877 b43_phy_write(dev, rfctl[0], 0x140);
2879 b43_phy_write(dev, rfctl[0], 0x110);
2881 if (band == IEEE80211_BAND_5GHZ)
2882 b43_phy_write(dev, rfctl[0], 0x180);
2884 b43_phy_write(dev, rfctl[0], 0x120);
2887 if (band == IEEE80211_BAND_5GHZ)
2888 b43_phy_write(dev, rfctl[1], 0x148);
2890 b43_phy_write(dev, rfctl[1], 0x114);
2892 if (nphy->rxcalparams & 0x10000) {
2893 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2895 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2899 for (j = 0; i < 4; j++) {
2905 if (power[1] > 10000) {
2910 if (power[0] > 10000) {
2920 cur_lna = lna[index];
2921 cur_hpf1 = hpf1[index];
2922 cur_hpf2 = hpf2[index];
2923 cur_hpf += desired - hweight32(power[index]);
2924 cur_hpf = clamp_val(cur_hpf, 0, 10);
2931 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2933 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2935 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2936 b43_nphy_stop_playback(dev);
2939 ret = b43_nphy_tx_tone(dev, 4000,
2940 (nphy->rxcalparams & 0xFFFF),
2944 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2950 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2959 power[i] = ((real + imag) / 1024) + 1;
2961 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2963 b43_nphy_stop_playback(dev);
2970 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2971 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2972 b43_phy_write(dev, rfctl[1], tmp[5]);
2973 b43_phy_write(dev, rfctl[0], tmp[4]);
2974 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2975 b43_phy_write(dev, afectl_core, tmp[2]);
2976 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2982 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2983 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2984 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2986 b43_nphy_stay_in_carrier_search(dev, 0);
2991 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2992 struct nphy_txgains target, u8 type, bool debug)
2997 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2998 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2999 struct nphy_txgains target, u8 type, bool debug)
3001 if (dev->phy.rev >= 3)
3002 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3004 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3009 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3011 int b43_phy_initn(struct b43_wldev *dev)
3013 struct ssb_bus *bus = dev->dev->bus;
3014 struct b43_phy *phy = &dev->phy;
3015 struct b43_phy_n *nphy = phy->n;
3017 struct nphy_txgains target;
3019 enum ieee80211_band tmp2;
3023 bool do_cal = false;
3025 if ((dev->phy.rev >= 3) &&
3026 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3027 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3028 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3030 nphy->deaf_count = 0;
3031 b43_nphy_tables_init(dev);
3032 nphy->crsminpwr_adjusted = false;
3033 nphy->noisevars_adjusted = false;
3035 /* Clear all overrides */
3036 if (dev->phy.rev >= 3) {
3037 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3038 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3039 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3040 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3042 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3044 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3045 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3046 if (dev->phy.rev < 6) {
3047 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3048 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3050 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3051 ~(B43_NPHY_RFSEQMODE_CAOVER |
3052 B43_NPHY_RFSEQMODE_TROVER));
3053 if (dev->phy.rev >= 3)
3054 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3055 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3057 if (dev->phy.rev <= 2) {
3058 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3059 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3060 ~B43_NPHY_BPHY_CTL3_SCALE,
3061 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3063 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3064 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3066 if (bus->sprom.boardflags2_lo & 0x100 ||
3067 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3068 bus->boardinfo.type == 0x8B))
3069 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3071 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3072 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3073 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3074 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3076 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3077 b43_nphy_update_txrx_chain(dev);
3080 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3081 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3084 tmp2 = b43_current_band(dev->wl);
3085 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3086 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3087 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3088 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3089 nphy->papd_epsilon_offset[0] << 7);
3090 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3091 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3092 nphy->papd_epsilon_offset[1] << 7);
3093 b43_nphy_int_pa_set_tx_dig_filters(dev);
3094 } else if (phy->rev >= 5) {
3095 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3098 b43_nphy_workarounds(dev);
3100 /* Reset CCA, in init code it differs a little from standard way */
3101 b43_nphy_bmac_clock_fgc(dev, 1);
3102 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3103 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3104 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3105 b43_nphy_bmac_clock_fgc(dev, 0);
3107 /* TODO N PHY MAC PHY Clock Set with argument 1 */
3109 b43_nphy_pa_override(dev, false);
3110 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3111 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3112 b43_nphy_pa_override(dev, true);
3114 b43_nphy_classifier(dev, 0, 0);
3115 b43_nphy_read_clip_detection(dev, clip);
3116 tx_pwr_state = nphy->txpwrctrl;
3117 /* TODO N PHY TX power control with argument 0
3118 (turning off power control) */
3119 /* TODO Fix the TX Power Settings */
3120 /* TODO N PHY TX Power Control Idle TSSI */
3121 /* TODO N PHY TX Power Control Setup */
3123 if (phy->rev >= 3) {
3126 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3127 b43_ntab_tx_gain_rev0_1_2);
3128 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3129 b43_ntab_tx_gain_rev0_1_2);
3132 if (nphy->phyrxchain != 3)
3133 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3134 if (nphy->mphase_cal_phase_id > 0)
3135 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3137 do_rssi_cal = false;
3138 if (phy->rev >= 3) {
3139 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3140 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
3142 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
3145 b43_nphy_rssi_cal(dev);
3147 b43_nphy_restore_rssi_cal(dev);
3149 b43_nphy_rssi_cal(dev);
3152 if (!((nphy->measure_hold & 0x6) != 0)) {
3153 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3154 do_cal = (nphy->iqcal_chanspec_2G == 0);
3156 do_cal = (nphy->iqcal_chanspec_5G == 0);
3162 target = b43_nphy_get_tx_gains(dev);
3164 if (nphy->antsel_type == 2)
3165 b43_nphy_superswitch_init(dev, true);
3166 if (nphy->perical != 2) {
3167 b43_nphy_rssi_cal(dev);
3168 if (phy->rev >= 3) {
3169 nphy->cal_orig_pwr_idx[0] =
3170 nphy->txpwrindex[0].index_internal;
3171 nphy->cal_orig_pwr_idx[1] =
3172 nphy->txpwrindex[1].index_internal;
3173 /* TODO N PHY Pre Calibrate TX Gain */
3174 target = b43_nphy_get_tx_gains(dev);
3180 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3181 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3182 b43_nphy_save_cal(dev);
3183 else if (nphy->mphase_cal_phase_id == 0)
3184 ;/* N PHY Periodic Calibration with argument 3 */
3186 b43_nphy_restore_cal(dev);
3189 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3190 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3191 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3192 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3193 if (phy->rev >= 3 && phy->rev <= 6)
3194 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3195 b43_nphy_tx_lp_fbw(dev);
3197 b43_nphy_spur_workaround(dev);
3199 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3203 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3205 struct b43_phy_n *nphy;
3207 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3215 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3217 struct b43_phy *phy = &dev->phy;
3218 struct b43_phy_n *nphy = phy->n;
3220 memset(nphy, 0, sizeof(*nphy));
3222 //TODO init struct b43_phy_n
3225 static void b43_nphy_op_free(struct b43_wldev *dev)
3227 struct b43_phy *phy = &dev->phy;
3228 struct b43_phy_n *nphy = phy->n;
3234 static int b43_nphy_op_init(struct b43_wldev *dev)
3236 return b43_phy_initn(dev);
3239 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3242 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3243 /* OFDM registers are onnly available on A/G-PHYs */
3244 b43err(dev->wl, "Invalid OFDM PHY access at "
3245 "0x%04X on N-PHY\n", offset);
3248 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3249 /* Ext-G registers are only available on G-PHYs */
3250 b43err(dev->wl, "Invalid EXT-G PHY access at "
3251 "0x%04X on N-PHY\n", offset);
3254 #endif /* B43_DEBUG */
3257 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3259 check_phyreg(dev, reg);
3260 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3261 return b43_read16(dev, B43_MMIO_PHY_DATA);
3264 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3266 check_phyreg(dev, reg);
3267 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3268 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3271 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3273 /* Register 1 is a 32-bit register. */
3274 B43_WARN_ON(reg == 1);
3275 /* N-PHY needs 0x100 for read access */
3278 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3279 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3282 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3284 /* Register 1 is a 32-bit register. */
3285 B43_WARN_ON(reg == 1);
3287 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3288 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3291 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3292 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3295 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3296 b43err(dev->wl, "MAC not suspended\n");
3299 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3300 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3301 if (dev->phy.rev >= 3) {
3302 b43_radio_mask(dev, 0x09, ~0x2);
3304 b43_radio_write(dev, 0x204D, 0);
3305 b43_radio_write(dev, 0x2053, 0);
3306 b43_radio_write(dev, 0x2058, 0);
3307 b43_radio_write(dev, 0x205E, 0);
3308 b43_radio_mask(dev, 0x2062, ~0xF0);
3309 b43_radio_write(dev, 0x2064, 0);
3311 b43_radio_write(dev, 0x304D, 0);
3312 b43_radio_write(dev, 0x3053, 0);
3313 b43_radio_write(dev, 0x3058, 0);
3314 b43_radio_write(dev, 0x305E, 0);
3315 b43_radio_mask(dev, 0x3062, ~0xF0);
3316 b43_radio_write(dev, 0x3064, 0);
3319 if (dev->phy.rev >= 3) {
3320 /* TODO: b43_radio_init2056(dev); */
3321 /* TODO: PHY Set Channel Spec (dev, radio_chanspec) */
3323 b43_radio_init2055(dev);
3328 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3330 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3334 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3335 unsigned int new_channel)
3337 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3338 if ((new_channel < 1) || (new_channel > 14))
3341 if (new_channel > 200)
3345 return nphy_channel_switch(dev, new_channel);
3348 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3350 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3355 const struct b43_phy_operations b43_phyops_n = {
3356 .allocate = b43_nphy_op_allocate,
3357 .free = b43_nphy_op_free,
3358 .prepare_structs = b43_nphy_op_prepare_structs,
3359 .init = b43_nphy_op_init,
3360 .phy_read = b43_nphy_op_read,
3361 .phy_write = b43_nphy_op_write,
3362 .radio_read = b43_nphy_op_radio_read,
3363 .radio_write = b43_nphy_op_radio_write,
3364 .software_rfkill = b43_nphy_op_software_rfkill,
3365 .switch_analog = b43_nphy_op_switch_analog,
3366 .switch_channel = b43_nphy_op_switch_channel,
3367 .get_default_chan = b43_nphy_op_get_default_chan,
3368 .recalc_txpower = b43_nphy_op_recalc_txpower,
3369 .adjust_txpower = b43_nphy_op_adjust_txpower,