drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "radio_2057.h"
  36 #include "main.h"
  37
  38 struct nphy_txgains {
  39         u16 tx_lpf[2];
  40         u16 txgm[2];
  41         u16 pga[2];
  42         u16 pad[2];
  43         u16 ipa[2];
  44 };
  45
  46 struct nphy_iqcal_params {
  47         u16 tx_lpf;
  48         u16 txgm;
  49         u16 pga;
  50         u16 pad;
  51         u16 ipa;
  52         u16 cal_gain;
  53         u16 ncorr[5];
  54 };
  55
  56 struct nphy_iq_est {
  57         s32 iq0_prod;
  58         u32 i0_pwr;
  59         u32 q0_pwr;
  60         s32 iq1_prod;
  61         u32 i1_pwr;
  62         u32 q1_pwr;
  63 };
  64
  65 enum b43_nphy_rf_sequence {
  66         B43_RFSEQ_RX2TX,
  67         B43_RFSEQ_TX2RX,
  68         B43_RFSEQ_RESET2RX,
  69         B43_RFSEQ_UPDATE_GAINH,
  70         B43_RFSEQ_UPDATE_GAINL,
  71         B43_RFSEQ_UPDATE_GAINU,
  72 };
  73
  74 enum n_rf_ctl_over_cmd {
  75         N_RF_CTL_OVER_CMD_RXRF_PU = 0,
  76         N_RF_CTL_OVER_CMD_RX_PU = 1,
  77         N_RF_CTL_OVER_CMD_TX_PU = 2,
  78         N_RF_CTL_OVER_CMD_RX_GAIN = 3,
  79         N_RF_CTL_OVER_CMD_TX_GAIN = 4,
  80 };
  81
  82 enum n_intc_override {
  83         N_INTC_OVERRIDE_OFF = 0,
  84         N_INTC_OVERRIDE_TRSW = 1,
  85         N_INTC_OVERRIDE_PA = 2,
  86         N_INTC_OVERRIDE_EXT_LNA_PU = 3,
  87         N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
  88 };
  89
  90 enum n_rssi_type {
  91         N_RSSI_W1 = 0,
  92         N_RSSI_W2,
  93         N_RSSI_NB,
  94         N_RSSI_IQ,
  95         N_RSSI_TSSI_2G,
  96         N_RSSI_TSSI_5G,
  97         N_RSSI_TBD,
  98 };
  99
 100 enum n_rail_type {
 101         N_RAIL_I = 0,
 102         N_RAIL_Q = 1,
 103 };
 104
 105 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
 106 {
 107         enum ieee80211_band band = b43_current_band(dev->wl);
 108         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 109                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
 110 }
 111
 112 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
 113 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
 114 {
 115         return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
 116                 B43_NPHY_RFSEQCA_RXEN_SHIFT;
 117 }
 118
 119 /**************************************************
 120  * RF (just without b43_nphy_rf_ctl_intc_override)
 121  **************************************************/
 122
 123 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
 124 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 125                                        enum b43_nphy_rf_sequence seq)
 126 {
 127         static const u16 trigger[] = {
 128                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 129                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 130                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 131                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 132                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 133                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 134         };
 135         int i;
 136         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
 137
 138         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 139
 140         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 141                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 142         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 143         for (i = 0; i < 200; i++) {
 144                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 145                         goto ok;
 146                 msleep(1);
 147         }
 148         b43err(dev->wl, "RF sequence status timeout\n");
 149 ok:
 150         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
 151 }
 152
 153 static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field,
 154                                            u16 value, u8 core, bool off,
 155                                            u8 override_id)
 156 {
 157         /* TODO */
 158 }
 159
 160 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
 161 static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
 162                                           u16 value, u8 core, bool off,
 163                                           u8 override)
 164 {
 165         struct b43_phy *phy = &dev->phy;
 166         const struct nphy_rf_control_override_rev7 *e;
 167         u16 en_addrs[3][2] = {
 168                 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
 169         };
 170         u16 en_addr;
 171         u16 en_mask = field;
 172         u16 val_addr;
 173         u8 i;
 174
 175         if (phy->rev >= 19 || phy->rev < 3) {
 176                 B43_WARN_ON(1);
 177                 return;
 178         }
 179
 180         /* Remember: we can get NULL! */
 181         e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
 182
 183         for (i = 0; i < 2; i++) {
 184                 if (override >= ARRAY_SIZE(en_addrs)) {
 185                         b43err(dev->wl, "Invalid override value %d\n", override);
 186                         return;
 187                 }
 188                 en_addr = en_addrs[override][i];
 189
 190                 if (e)
 191                         val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
 192
 193                 if (off) {
 194                         b43_phy_mask(dev, en_addr, ~en_mask);
 195                         if (e) /* Do it safer, better than wl */
 196                                 b43_phy_mask(dev, val_addr, ~e->val_mask);
 197                 } else {
 198                         if (!core || (core & (1 << i))) {
 199                                 b43_phy_set(dev, en_addr, en_mask);
 200                                 if (e)
 201                                         b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
 202                         }
 203                 }
 204         }
 205 }
 206
 207 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */
 208 static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev,
 209                                                  enum n_rf_ctl_over_cmd cmd,
 210                                                  u16 value, u8 core, bool off)
 211 {
 212         struct b43_phy *phy = &dev->phy;
 213         u16 tmp;
 214
 215         B43_WARN_ON(phy->rev < 7);
 216
 217         switch (cmd) {
 218         case N_RF_CTL_OVER_CMD_RXRF_PU:
 219                 b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1);
 220                 b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1);
 221                 b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1);
 222                 break;
 223         case N_RF_CTL_OVER_CMD_RX_PU:
 224                 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1);
 225                 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
 226                 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1);
 227                 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2);
 228                 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1);
 229                 break;
 230         case N_RF_CTL_OVER_CMD_TX_PU:
 231                 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0);
 232                 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
 233                 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2);
 234                 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1);
 235                 break;
 236         case N_RF_CTL_OVER_CMD_RX_GAIN:
 237                 tmp = value & 0xFF;
 238                 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0);
 239                 tmp = value >> 8;
 240                 b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0);
 241                 break;
 242         case N_RF_CTL_OVER_CMD_TX_GAIN:
 243                 tmp = value & 0x7FFF;
 244                 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0);
 245                 tmp = value >> 14;
 246                 b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0);
 247                 break;
 248         }
 249 }
 250
 251 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
 252 static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
 253                                      u16 value, u8 core, bool off)
 254 {
 255         int i;
 256         u8 index = fls(field);
 257         u8 addr, en_addr, val_addr;
 258         /* we expect only one bit set */
 259         B43_WARN_ON(field & (~(1 << (index - 1))));
 260
 261         if (dev->phy.rev >= 3) {
 262                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
 263                 for (i = 0; i < 2; i++) {
 264                         if (index == 0 || index == 16) {
 265                                 b43err(dev->wl,
 266                                         "Unsupported RF Ctrl Override call\n");
 267                                 return;
 268                         }
 269
 270                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
 271                         en_addr = B43_PHY_N((i == 0) ?
 272                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
 273                         val_addr = B43_PHY_N((i == 0) ?
 274                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
 275
 276                         if (off) {
 277                                 b43_phy_mask(dev, en_addr, ~(field));
 278                                 b43_phy_mask(dev, val_addr,
 279                                                 ~(rf_ctrl->val_mask));
 280                         } else {
 281                                 if (core == 0 || ((1 << i) & core)) {
 282                                         b43_phy_set(dev, en_addr, field);
 283                                         b43_phy_maskset(dev, val_addr,
 284                                                 ~(rf_ctrl->val_mask),
 285                                                 (value << rf_ctrl->val_shift));
 286                                 }
 287                         }
 288                 }
 289         } else {
 290                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
 291                 if (off) {
 292                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
 293                         value = 0;
 294                 } else {
 295                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
 296                 }
 297
 298                 for (i = 0; i < 2; i++) {
 299                         if (index <= 1 || index == 16) {
 300                                 b43err(dev->wl,
 301                                         "Unsupported RF Ctrl Override call\n");
 302                                 return;
 303                         }
 304
 305                         if (index == 2 || index == 10 ||
 306                             (index >= 13 && index <= 15)) {
 307                                 core = 1;
 308                         }
 309
 310                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
 311                         addr = B43_PHY_N((i == 0) ?
 312                                 rf_ctrl->addr0 : rf_ctrl->addr1);
 313
 314                         if ((1 << i) & core)
 315                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
 316                                                 (value << rf_ctrl->shift));
 317
 318                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
 319                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 320                                         B43_NPHY_RFCTL_CMD_START);
 321                         udelay(1);
 322                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
 323                 }
 324         }
 325 }
 326
 327 static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
 328                                                enum n_intc_override intc_override,
 329                                                u16 value, u8 core_sel)
 330 {
 331         u16 reg, tmp, tmp2, val;
 332         int core;
 333
 334         /* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */
 335
 336         for (core = 0; core < 2; core++) {
 337                 if ((core_sel == 1 && core != 0) ||
 338                     (core_sel == 2 && core != 1))
 339                         continue;
 340
 341                 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
 342
 343                 switch (intc_override) {
 344                 case N_INTC_OVERRIDE_OFF:
 345                         b43_phy_write(dev, reg, 0);
 346                         b43_phy_mask(dev, 0x2ff, ~0x2000);
 347                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 348                         break;
 349                 case N_INTC_OVERRIDE_TRSW:
 350                         b43_phy_maskset(dev, reg, ~0xC0, value << 6);
 351                         b43_phy_set(dev, reg, 0x400);
 352
 353                         b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
 354                         b43_phy_set(dev, 0x2ff, 0x2000);
 355                         b43_phy_set(dev, 0x2ff, 0x0001);
 356                         break;
 357                 case N_INTC_OVERRIDE_PA:
 358                         tmp = 0x0030;
 359                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 360                                 val = value << 5;
 361                         else
 362                                 val = value << 4;
 363                         b43_phy_maskset(dev, reg, ~tmp, val);
 364                         b43_phy_set(dev, reg, 0x1000);
 365                         break;
 366                 case N_INTC_OVERRIDE_EXT_LNA_PU:
 367                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 368                                 tmp = 0x0001;
 369                                 tmp2 = 0x0004;
 370                                 val = value;
 371                         } else {
 372                                 tmp = 0x0004;
 373                                 tmp2 = 0x0001;
 374                                 val = value << 2;
 375                         }
 376                         b43_phy_maskset(dev, reg, ~tmp, val);
 377                         b43_phy_mask(dev, reg, ~tmp2);
 378                         break;
 379                 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
 380                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 381                                 tmp = 0x0002;
 382                                 tmp2 = 0x0008;
 383                                 val = value << 1;
 384                         } else {
 385                                 tmp = 0x0008;
 386                                 tmp2 = 0x0002;
 387                                 val = value << 3;
 388                         }
 389                         b43_phy_maskset(dev, reg, ~tmp, val);
 390                         b43_phy_mask(dev, reg, ~tmp2);
 391                         break;
 392                 }
 393         }
 394 }
 395
 396 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
 397 static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
 398                                           enum n_intc_override intc_override,
 399                                           u16 value, u8 core)
 400 {
 401         u8 i, j;
 402         u16 reg, tmp, val;
 403
 404         if (dev->phy.rev >= 7) {
 405                 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
 406                                                    core);
 407                 return;
 408         }
 409
 410         B43_WARN_ON(dev->phy.rev < 3);
 411
 412         for (i = 0; i < 2; i++) {
 413                 if ((core == 1 && i == 1) || (core == 2 && !i))
 414                         continue;
 415
 416                 reg = (i == 0) ?
 417                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
 418                 b43_phy_set(dev, reg, 0x400);
 419
 420                 switch (intc_override) {
 421                 case N_INTC_OVERRIDE_OFF:
 422                         b43_phy_write(dev, reg, 0);
 423                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 424                         break;
 425                 case N_INTC_OVERRIDE_TRSW:
 426                         if (!i) {
 427                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
 428                                                 0xFC3F, (value << 6));
 429                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
 430                                                 0xFFFE, 1);
 431                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 432                                                 B43_NPHY_RFCTL_CMD_START);
 433                                 for (j = 0; j < 100; j++) {
 434                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
 435                                                 j = 0;
 436                                                 break;
 437                                         }
 438                                         udelay(10);
 439                                 }
 440                                 if (j)
 441                                         b43err(dev->wl,
 442                                                 "intc override timeout\n");
 443                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
 444                                                 0xFFFE);
 445                         } else {
 446                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
 447                                                 0xFC3F, (value << 6));
 448                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 449                                                 0xFFFE, 1);
 450                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 451                                                 B43_NPHY_RFCTL_CMD_RXTX);
 452                                 for (j = 0; j < 100; j++) {
 453                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
 454                                                 j = 0;
 455                                                 break;
 456                                         }
 457                                         udelay(10);
 458                                 }
 459                                 if (j)
 460                                         b43err(dev->wl,
 461                                                 "intc override timeout\n");
 462                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
 463                                                 0xFFFE);
 464                         }
 465                         break;
 466                 case N_INTC_OVERRIDE_PA:
 467                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 468                                 tmp = 0x0020;
 469                                 val = value << 5;
 470                         } else {
 471                                 tmp = 0x0010;
 472                                 val = value << 4;
 473                         }
 474                         b43_phy_maskset(dev, reg, ~tmp, val);
 475                         break;
 476                 case N_INTC_OVERRIDE_EXT_LNA_PU:
 477                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 478                                 tmp = 0x0001;
 479                                 val = value;
 480                         } else {
 481                                 tmp = 0x0004;
 482                                 val = value << 2;
 483                         }
 484                         b43_phy_maskset(dev, reg, ~tmp, val);
 485                         break;
 486                 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
 487                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 488                                 tmp = 0x0002;
 489                                 val = value << 1;
 490                         } else {
 491                                 tmp = 0x0008;
 492                                 val = value << 3;
 493                         }
 494                         b43_phy_maskset(dev, reg, ~tmp, val);
 495                         break;
 496                 }
 497         }
 498 }
 499
 500 /**************************************************
 501  * Various PHY ops
 502  **************************************************/
 503
 504 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 505 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 506                                           const u16 *clip_st)
 507 {
 508         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 509         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 510 }
 511
 512 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 513 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 514 {
 515         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 516         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 517 }
 518
 519 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 520 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 521 {
 522         u16 tmp;
 523
 524         if (dev->dev->core_rev == 16)
 525                 b43_mac_suspend(dev);
 526
 527         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 528         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 529                 B43_NPHY_CLASSCTL_WAITEDEN);
 530         tmp &= ~mask;
 531         tmp |= (val & mask);
 532         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 533
 534         if (dev->dev->core_rev == 16)
 535                 b43_mac_enable(dev);
 536
 537         return tmp;
 538 }
 539
 540 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 541 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 542 {
 543         u16 bbcfg;
 544
 545         b43_phy_force_clock(dev, 1);
 546         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 547         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 548         udelay(1);
 549         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 550         b43_phy_force_clock(dev, 0);
 551         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 552 }
 553
 554 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 555 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 556 {
 557         struct b43_phy *phy = &dev->phy;
 558         struct b43_phy_n *nphy = phy->n;
 559
 560         if (enable) {
 561                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
 562                 if (nphy->deaf_count++ == 0) {
 563                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 564                         b43_nphy_classifier(dev, 0x7,
 565                                             B43_NPHY_CLASSCTL_WAITEDEN);
 566                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 567                         b43_nphy_write_clip_detection(dev, clip);
 568                 }
 569                 b43_nphy_reset_cca(dev);
 570         } else {
 571                 if (--nphy->deaf_count == 0) {
 572                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 573                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 574                 }
 575         }
 576 }
 577
 578 /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
 579 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
 580 {
 581         if (!offset)
 582                 offset = b43_is_40mhz(dev) ? 0x159 : 0x154;
 583         return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
 584 }
 585
 586 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 587 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 588 {
 589         struct b43_phy_n *nphy = dev->phy.n;
 590
 591         u8 i;
 592         s16 tmp;
 593         u16 data[4];
 594         s16 gain[2];
 595         u16 minmax[2];
 596         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
 597
 598         if (nphy->hang_avoid)
 599                 b43_nphy_stay_in_carrier_search(dev, 1);
 600
 601         if (nphy->gain_boost) {
 602                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 603                         gain[0] = 6;
 604                         gain[1] = 6;
 605                 } else {
 606                         tmp = 40370 - 315 * dev->phy.channel;
 607                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 608                         tmp = 23242 - 224 * dev->phy.channel;
 609                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 610                 }
 611         } else {
 612                 gain[0] = 0;
 613                 gain[1] = 0;
 614         }
 615
 616         for (i = 0; i < 2; i++) {
 617                 if (nphy->elna_gain_config) {
 618                         data[0] = 19 + gain[i];
 619                         data[1] = 25 + gain[i];
 620                         data[2] = 25 + gain[i];
 621                         data[3] = 25 + gain[i];
 622                 } else {
 623                         data[0] = lna_gain[0] + gain[i];
 624                         data[1] = lna_gain[1] + gain[i];
 625                         data[2] = lna_gain[2] + gain[i];
 626                         data[3] = lna_gain[3] + gain[i];
 627                 }
 628                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
 629
 630                 minmax[i] = 23 + gain[i];
 631         }
 632
 633         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 634                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 635         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 636                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 637
 638         if (nphy->hang_avoid)
 639                 b43_nphy_stay_in_carrier_search(dev, 0);
 640 }
 641
 642 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
 643 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
 644                                         u8 *events, u8 *delays, u8 length)
 645 {
 646         struct b43_phy_n *nphy = dev->phy.n;
 647         u8 i;
 648         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
 649         u16 offset1 = cmd << 4;
 650         u16 offset2 = offset1 + 0x80;
 651
 652         if (nphy->hang_avoid)
 653                 b43_nphy_stay_in_carrier_search(dev, true);
 654
 655         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
 656         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
 657
 658         for (i = length; i < 16; i++) {
 659                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
 660                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
 661         }
 662
 663         if (nphy->hang_avoid)
 664                 b43_nphy_stay_in_carrier_search(dev, false);
 665 }
 666
 667 /**************************************************
 668  * Radio 0x2057
 669  **************************************************/
 670
 671 static void b43_radio_2057_chantab_upload(struct b43_wldev *dev,
 672                                           const struct b43_nphy_chantabent_rev7 *e_r7,
 673                                           const struct b43_nphy_chantabent_rev7_2g *e_r7_2g)
 674 {
 675         if (e_r7_2g) {
 676                 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0);
 677                 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1);
 678                 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize);
 679                 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1);
 680                 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2);
 681                 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1);
 682                 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac);
 683                 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0);
 684                 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1);
 685                 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune);
 686                 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune);
 687                 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune);
 688                 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0);
 689                 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0);
 690                 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0);
 691                 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1);
 692                 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1);
 693                 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1);
 694
 695         } else {
 696                 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0);
 697                 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1);
 698                 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize);
 699                 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1);
 700                 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2);
 701                 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1);
 702                 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac);
 703                 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0);
 704                 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1);
 705                 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune);
 706                 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune);
 707                 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune);
 708                 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune);
 709                 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune);
 710                 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0);
 711                 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0);
 712                 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0);
 713                 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0);
 714                 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0);
 715                 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0);
 716                 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0);
 717                 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1);
 718                 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1);
 719                 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1);
 720                 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1);
 721                 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1);
 722                 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1);
 723                 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1);
 724         }
 725 }
 726
 727 static void b43_radio_2057_setup(struct b43_wldev *dev,
 728                                  const struct b43_nphy_chantabent_rev7 *tabent_r7,
 729                                  const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g)
 730 {
 731         struct b43_phy *phy = &dev->phy;
 732
 733         b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g);
 734
 735         switch (phy->radio_rev) {
 736         case 0 ... 4:
 737         case 6:
 738                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 739                         b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f);
 740                         b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
 741                         b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
 742                         b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
 743                 } else {
 744                         b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f);
 745                         b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
 746                         b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
 747                         b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
 748                 }
 749                 break;
 750         case 9: /* e.g. PHY rev 16 */
 751                 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20);
 752                 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18);
 753                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 754                         b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38);
 755                         b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f);
 756
 757                         if (b43_is_40mhz(dev)) {
 758                                 /* TODO */
 759                         } else {
 760                                 b43_radio_write(dev,
 761                                                 R2057_PAD_BIAS_FILTER_BWS_CORE0,
 762                                                 0x3c);
 763                                 b43_radio_write(dev,
 764                                                 R2057_PAD_BIAS_FILTER_BWS_CORE1,
 765                                                 0x3c);
 766                         }
 767                 }
 768                 break;
 769         case 14: /* 2 GHz only */
 770                 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b);
 771                 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
 772                 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f);
 773                 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f);
 774                 break;
 775         }
 776
 777         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 778                 u16 txmix2g_tune_boost_pu = 0;
 779                 u16 pad2g_tune_pus = 0;
 780
 781                 if (b43_nphy_ipa(dev)) {
 782                         switch (phy->radio_rev) {
 783                         case 9:
 784                                 txmix2g_tune_boost_pu = 0x0041;
 785                                 /* TODO */
 786                                 break;
 787                         case 14:
 788                                 txmix2g_tune_boost_pu = 0x21;
 789                                 pad2g_tune_pus = 0x23;
 790                                 break;
 791                         }
 792                 }
 793
 794                 if (txmix2g_tune_boost_pu)
 795                         b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
 796                                         txmix2g_tune_boost_pu);
 797                 if (pad2g_tune_pus)
 798                         b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0,
 799                                         pad2g_tune_pus);
 800                 if (txmix2g_tune_boost_pu)
 801                         b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
 802                                         txmix2g_tune_boost_pu);
 803                 if (pad2g_tune_pus)
 804                         b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1,
 805                                         pad2g_tune_pus);
 806         }
 807
 808         usleep_range(50, 100);
 809
 810         /* VCO calibration */
 811         b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01);
 812         b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04);
 813         b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4);
 814         b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01);
 815         usleep_range(300, 600);
 816 }
 817
 818 /* Calibrate resistors in LPF of PLL?
 819  * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal
 820  */
 821 static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
 822 {
 823         struct b43_phy *phy = &dev->phy;
 824         u16 saved_regs_phy[12];
 825         u16 saved_regs_phy_rf[6];
 826         u16 saved_regs_radio[2] = { };
 827         static const u16 phy_to_store[] = {
 828                 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2,
 829                 B43_NPHY_RFCTL_LUT_TRSW_LO1, B43_NPHY_RFCTL_LUT_TRSW_LO2,
 830                 B43_NPHY_RFCTL_RXG1, B43_NPHY_RFCTL_RXG2,
 831                 B43_NPHY_RFCTL_TXG1, B43_NPHY_RFCTL_TXG2,
 832                 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4,
 833                 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6,
 834         };
 835         static const u16 phy_to_store_rf[] = {
 836                 B43_NPHY_REV3_RFCTL_OVER0, B43_NPHY_REV3_RFCTL_OVER1,
 837                 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4,
 838                 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6,
 839         };
 840         u16 tmp;
 841         int i;
 842
 843         /* Save */
 844         for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
 845                 saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]);
 846         for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++)
 847                 saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]);
 848
 849         /* Set */
 850         for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
 851                 b43_phy_write(dev, phy_to_store[i], 0);
 852         b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff);
 853         b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff);
 854         b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff);
 855         b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff);
 856         b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f);
 857         b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f);
 858
 859         switch (phy->radio_rev) {
 860         case 5:
 861                 b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2);
 862                 udelay(10);
 863                 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
 864                 b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1);
 865                 break;
 866         case 9:
 867                 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2);
 868                 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
 869                 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU);
 870                 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11);
 871                 break;
 872         case 14:
 873                 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU);
 874                 saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2);
 875                 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
 876                 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2);
 877                 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2);
 878                 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1);
 879                 break;
 880         }
 881
 882         /* Enable */
 883         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
 884         udelay(10);
 885
 886         /* Start */
 887         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2);
 888         usleep_range(100, 200);
 889
 890         /* Stop */
 891         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
 892
 893         /* Wait and check for result */
 894         if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) {
 895                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
 896                 return 0;
 897         }
 898         tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
 899
 900         /* Disable */
 901         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
 902
 903         /* Restore */
 904         for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++)
 905                 b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]);
 906         for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
 907                 b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]);
 908
 909         switch (phy->radio_rev) {
 910         case 0 ... 4:
 911         case 6:
 912                 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
 913                 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
 914                                   tmp << 2);
 915                 break;
 916         case 5:
 917                 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
 918                 b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2);
 919                 break;
 920         case 9:
 921                 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
 922                 break;
 923         case 14:
 924                 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
 925                 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]);
 926                 break;
 927         }
 928
 929         return tmp & 0x3e;
 930 }
 931
 932 /* Calibrate the internal RC oscillator?
 933  * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal
 934  */
 935 static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
 936 {
 937         struct b43_phy *phy = &dev->phy;
 938         bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
 939                         phy->radio_rev == 6);
 940         u16 tmp;
 941
 942         /* Setup cal */
 943         if (special) {
 944                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
 945                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
 946         } else {
 947                 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61);
 948                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9);
 949         }
 950         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 951
 952         /* Start, wait, stop */
 953         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 954         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
 955                                   5000000))
 956                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 957         usleep_range(35, 70);
 958         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 959         usleep_range(70, 140);
 960
 961         /* Setup cal */
 962         if (special) {
 963                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
 964                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 965         } else {
 966                 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69);
 967                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
 968         }
 969         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 970
 971         /* Start, wait, stop */
 972         usleep_range(35, 70);
 973         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 974         usleep_range(70, 140);
 975         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
 976                                   5000000))
 977                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 978         usleep_range(35, 70);
 979         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 980         usleep_range(70, 140);
 981
 982         /* Setup cal */
 983         if (special) {
 984                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
 985                 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
 986                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 987         } else {
 988                 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73);
 989                 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 990                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
 991         }
 992
 993         /* Start, wait, stop */
 994         usleep_range(35, 70);
 995         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 996         usleep_range(70, 140);
 997         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
 998                                   5000000)) {
 999                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
1000                 return 0;
1001         }
1002         tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
1003         usleep_range(35, 70);
1004         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
1005         usleep_range(70, 140);
1006
1007         if (special)
1008                 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1);
1009         else
1010                 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1);
1011
1012         return tmp;
1013 }
1014
1015 static void b43_radio_2057_init_pre(struct b43_wldev *dev)
1016 {
1017         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1018         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1019         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
1020         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1021         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
1022 }
1023
1024 static void b43_radio_2057_init_post(struct b43_wldev *dev)
1025 {
1026         b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
1027
1028         if (0) /* FIXME: Is this BCM43217 specific? */
1029                 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2);
1030
1031         b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
1032         b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
1033         mdelay(2);
1034         b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
1035         b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
1036
1037         if (dev->phy.do_full_init) {
1038                 b43_radio_2057_rcal(dev);
1039                 b43_radio_2057_rccal(dev);
1040         }
1041         b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
1042 }
1043
1044 /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
1045 static void b43_radio_2057_init(struct b43_wldev *dev)
1046 {
1047         b43_radio_2057_init_pre(dev);
1048         r2057_upload_inittabs(dev);
1049         b43_radio_2057_init_post(dev);
1050 }
1051
1052 /**************************************************
1053  * Radio 0x2056
1054  **************************************************/
1055
1056 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
1057                                 const struct b43_nphy_channeltab_entry_rev3 *e)
1058 {
1059         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
1060         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
1061         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
1062         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
1063         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
1064         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
1065                                         e->radio_syn_pll_loopfilter1);
1066         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
1067                                         e->radio_syn_pll_loopfilter2);
1068         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
1069                                         e->radio_syn_pll_loopfilter3);
1070         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
1071                                         e->radio_syn_pll_loopfilter4);
1072         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
1073                                         e->radio_syn_pll_loopfilter5);
1074         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
1075                                         e->radio_syn_reserved_addr27);
1076         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
1077                                         e->radio_syn_reserved_addr28);
1078         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
1079                                         e->radio_syn_reserved_addr29);
1080         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
1081                                         e->radio_syn_logen_vcobuf1);
1082         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
1083         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
1084         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
1085
1086         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
1087                                         e->radio_rx0_lnaa_tune);
1088         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
1089                                         e->radio_rx0_lnag_tune);
1090
1091         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
1092                                         e->radio_tx0_intpaa_boost_tune);
1093         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
1094                                         e->radio_tx0_intpag_boost_tune);
1095         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
1096                                         e->radio_tx0_pada_boost_tune);
1097         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
1098                                         e->radio_tx0_padg_boost_tune);
1099         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
1100                                         e->radio_tx0_pgaa_boost_tune);
1101         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
1102                                         e->radio_tx0_pgag_boost_tune);
1103         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
1104                                         e->radio_tx0_mixa_boost_tune);
1105         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
1106                                         e->radio_tx0_mixg_boost_tune);
1107
1108         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
1109                                         e->radio_rx1_lnaa_tune);
1110         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
1111                                         e->radio_rx1_lnag_tune);
1112
1113         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
1114                                         e->radio_tx1_intpaa_boost_tune);
1115         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
1116                                         e->radio_tx1_intpag_boost_tune);
1117         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
1118                                         e->radio_tx1_pada_boost_tune);
1119         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
1120                                         e->radio_tx1_padg_boost_tune);
1121         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
1122                                         e->radio_tx1_pgaa_boost_tune);
1123         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
1124                                         e->radio_tx1_pgag_boost_tune);
1125         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
1126                                         e->radio_tx1_mixa_boost_tune);
1127         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
1128                                         e->radio_tx1_mixg_boost_tune);
1129 }
1130
1131 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
1132 static void b43_radio_2056_setup(struct b43_wldev *dev,
1133                                 const struct b43_nphy_channeltab_entry_rev3 *e)
1134 {
1135         struct b43_phy *phy = &dev->phy;
1136         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1137         enum ieee80211_band band = b43_current_band(dev->wl);
1138         u16 offset;
1139         u8 i;
1140         u16 bias, cbias;
1141         u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
1142         u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
1143         bool is_pkg_fab_smic;
1144
1145         B43_WARN_ON(dev->phy.rev < 3);
1146
1147         is_pkg_fab_smic =
1148                 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
1149                   dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
1150                   dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
1151                  dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
1152
1153         b43_chantab_radio_2056_upload(dev, e);
1154         b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
1155
1156         if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1157             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1158                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1159                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
1160                 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
1161                     dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
1162                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
1163                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
1164                 } else {
1165                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
1166                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
1167                 }
1168         }
1169         if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
1170             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1171                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
1172                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
1173                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
1174                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
1175         }
1176         if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1177             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1178                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1179                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
1180                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
1181                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
1182         }
1183
1184         if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
1185                 for (i = 0; i < 2; i++) {
1186                         offset = i ? B2056_TX1 : B2056_TX0;
1187                         if (dev->phy.rev >= 5) {
1188                                 b43_radio_write(dev,
1189                                         offset | B2056_TX_PADG_IDAC, 0xcc);
1190
1191                                 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
1192                                     dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
1193                                         bias = 0x40;
1194                                         cbias = 0x45;
1195                                         pag_boost = 0x5;
1196                                         pgag_boost = 0x33;
1197                                         mixg_boost = 0x55;
1198                                 } else {
1199                                         bias = 0x25;
1200                                         cbias = 0x20;
1201                                         if (is_pkg_fab_smic) {
1202                                                 bias = 0x2a;
1203                                                 cbias = 0x38;
1204                                         }
1205                                         pag_boost = 0x4;
1206                                         pgag_boost = 0x03;
1207                                         mixg_boost = 0x65;
1208                                 }
1209                                 padg_boost = 0x77;
1210
1211                                 b43_radio_write(dev,
1212                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
1213                                         bias);
1214                                 b43_radio_write(dev,
1215                                         offset | B2056_TX_INTPAG_IAUX_STAT,
1216                                         bias);
1217                                 b43_radio_write(dev,
1218                                         offset | B2056_TX_INTPAG_CASCBIAS,
1219                                         cbias);
1220                                 b43_radio_write(dev,
1221                                         offset | B2056_TX_INTPAG_BOOST_TUNE,
1222                                         pag_boost);
1223                                 b43_radio_write(dev,
1224                                         offset | B2056_TX_PGAG_BOOST_TUNE,
1225                                         pgag_boost);
1226                                 b43_radio_write(dev,
1227                                         offset | B2056_TX_PADG_BOOST_TUNE,
1228                                         padg_boost);
1229                                 b43_radio_write(dev,
1230                                         offset | B2056_TX_MIXG_BOOST_TUNE,
1231                                         mixg_boost);
1232                         } else {
1233                                 bias = b43_is_40mhz(dev) ? 0x40 : 0x20;
1234                                 b43_radio_write(dev,
1235                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
1236                                         bias);
1237                                 b43_radio_write(dev,
1238                                         offset | B2056_TX_INTPAG_IAUX_STAT,
1239                                         bias);
1240                                 b43_radio_write(dev,
1241                                         offset | B2056_TX_INTPAG_CASCBIAS,
1242                                         0x30);
1243                         }
1244                         b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
1245                 }
1246         } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
1247                 u16 freq = phy->chandef->chan->center_freq;
1248                 if (freq < 5100) {
1249                         paa_boost = 0xA;
1250                         pada_boost = 0x77;
1251                         pgaa_boost = 0xF;
1252                         mixa_boost = 0xF;
1253                 } else if (freq < 5340) {
1254                         paa_boost = 0x8;
1255                         pada_boost = 0x77;
1256                         pgaa_boost = 0xFB;
1257                         mixa_boost = 0xF;
1258                 } else if (freq < 5650) {
1259                         paa_boost = 0x0;
1260                         pada_boost = 0x77;
1261                         pgaa_boost = 0xB;
1262                         mixa_boost = 0xF;
1263                 } else {
1264                         paa_boost = 0x0;
1265                         pada_boost = 0x77;
1266                         if (freq != 5825)
1267                                 pgaa_boost = -(freq - 18) / 36 + 168;
1268                         else
1269                                 pgaa_boost = 6;
1270                         mixa_boost = 0xF;
1271                 }
1272
1273                 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
1274
1275                 for (i = 0; i < 2; i++) {
1276                         offset = i ? B2056_TX1 : B2056_TX0;
1277
1278                         b43_radio_write(dev,
1279                                 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
1280                         b43_radio_write(dev,
1281                                 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
1282                         b43_radio_write(dev,
1283                                 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
1284                         b43_radio_write(dev,
1285                                 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
1286                         b43_radio_write(dev,
1287                                 offset | B2056_TX_TXSPARE1, 0x30);
1288                         b43_radio_write(dev,
1289                                 offset | B2056_TX_PA_SPARE2, 0xee);
1290                         b43_radio_write(dev,
1291                                 offset | B2056_TX_PADA_CASCBIAS, 0x03);
1292                         b43_radio_write(dev,
1293                                 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
1294                         b43_radio_write(dev,
1295                                 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
1296                         b43_radio_write(dev,
1297                                 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
1298                 }
1299         }
1300
1301         udelay(50);
1302         /* VCO calibration */
1303         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
1304         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1305         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
1306         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1307         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
1308         udelay(300);
1309 }
1310
1311 static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
1312 {
1313         struct b43_phy *phy = &dev->phy;
1314         u16 mast2, tmp;
1315
1316         if (phy->rev != 3)
1317                 return 0;
1318
1319         mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
1320         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
1321
1322         udelay(10);
1323         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1324         udelay(10);
1325         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
1326
1327         if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
1328                                   1000000)) {
1329                 b43err(dev->wl, "Radio recalibration timeout\n");
1330                 return 0;
1331         }
1332
1333         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1334         tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1335         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1336
1337         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1338
1339         return tmp & 0x1f;
1340 }
1341
1342 static void b43_radio_init2056_pre(struct b43_wldev *dev)
1343 {
1344         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1345                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1346         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1347         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1348                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
1349         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1350                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1351         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1352                     B43_NPHY_RFCTL_CMD_CHIP0PU);
1353 }
1354
1355 static void b43_radio_init2056_post(struct b43_wldev *dev)
1356 {
1357         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1358         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1359         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1360         msleep(1);
1361         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1362         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1363         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
1364         if (dev->phy.do_full_init)
1365                 b43_radio_2056_rcal(dev);
1366 }
1367
1368 /*
1369  * Initialize a Broadcom 2056 N-radio
1370  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1371  */
1372 static void b43_radio_init2056(struct b43_wldev *dev)
1373 {
1374         b43_radio_init2056_pre(dev);
1375         b2056_upload_inittabs(dev, 0, 0);
1376         b43_radio_init2056_post(dev);
1377 }
1378
1379 /**************************************************
1380  * Radio 0x2055
1381  **************************************************/
1382
1383 static void b43_chantab_radio_upload(struct b43_wldev *dev,
1384                                 const struct b43_nphy_channeltab_entry_rev2 *e)
1385 {
1386         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1387         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1388         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1389         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1390         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1391
1392         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1393         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1394         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1395         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1396         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1397
1398         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1399         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1400         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1401         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1402         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1403
1404         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1405         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1406         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1407         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1408         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1409
1410         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1411         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1412         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1413         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1414         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1415
1416         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1417         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
1418 }
1419
1420 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1421 static void b43_radio_2055_setup(struct b43_wldev *dev,
1422                                 const struct b43_nphy_channeltab_entry_rev2 *e)
1423 {
1424         B43_WARN_ON(dev->phy.rev >= 3);
1425
1426         b43_chantab_radio_upload(dev, e);
1427         udelay(50);
1428         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1429         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1430         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1431         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1432         udelay(300);
1433 }
1434
1435 static void b43_radio_init2055_pre(struct b43_wldev *dev)
1436 {
1437         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1438                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
1439         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1440                     B43_NPHY_RFCTL_CMD_CHIP0PU |
1441                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
1442         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1443                     B43_NPHY_RFCTL_CMD_PORFORCE);
1444 }
1445
1446 static void b43_radio_init2055_post(struct b43_wldev *dev)
1447 {
1448         struct b43_phy_n *nphy = dev->phy.n;
1449         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1450         bool workaround = false;
1451
1452         if (sprom->revision < 4)
1453                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1454                               && dev->dev->board_type == SSB_BOARD_CB2_4321
1455                               && dev->dev->board_rev >= 0x41);
1456         else
1457                 workaround =
1458                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1459
1460         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1461         if (workaround) {
1462                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1463                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1464         }
1465         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1466         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1467         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1468         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1469         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1470         msleep(1);
1471         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1472         if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1473                 b43err(dev->wl, "radio post init timeout\n");
1474         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1475         b43_switch_channel(dev, dev->phy.channel);
1476         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1477         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1478         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1479         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1480         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1481         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1482         if (!nphy->gain_boost) {
1483                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1484                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1485         } else {
1486                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1487                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1488         }
1489         udelay(2);
1490 }
1491
1492 /*
1493  * Initialize a Broadcom 2055 N-radio
1494  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1495  */
1496 static void b43_radio_init2055(struct b43_wldev *dev)
1497 {
1498         b43_radio_init2055_pre(dev);
1499         if (b43_status(dev) < B43_STAT_INITIALIZED) {
1500                 /* Follow wl, not specs. Do not force uploading all regs */
1501                 b2055_upload_inittab(dev, 0, 0);
1502         } else {
1503                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1504                 b2055_upload_inittab(dev, ghz5, 0);
1505         }
1506         b43_radio_init2055_post(dev);
1507 }
1508
1509 /**************************************************
1510  * Samples
1511  **************************************************/
1512
1513 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1514 static int b43_nphy_load_samples(struct b43_wldev *dev,
1515                                         struct b43_c32 *samples, u16 len) {
1516         struct b43_phy_n *nphy = dev->phy.n;
1517         u16 i;
1518         u32 *data;
1519
1520         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1521         if (!data) {
1522                 b43err(dev->wl, "allocation for samples loading failed\n");
1523                 return -ENOMEM;
1524         }
1525         if (nphy->hang_avoid)
1526                 b43_nphy_stay_in_carrier_search(dev, 1);
1527
1528         for (i = 0; i < len; i++) {
1529                 data[i] = (samples[i].i & 0x3FF << 10);
1530                 data[i] |= samples[i].q & 0x3FF;
1531         }
1532         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1533
1534         kfree(data);
1535         if (nphy->hang_avoid)
1536                 b43_nphy_stay_in_carrier_search(dev, 0);
1537         return 0;
1538 }
1539
1540 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1541 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1542                                         bool test)
1543 {
1544         int i;
1545         u16 bw, len, rot, angle;
1546         struct b43_c32 *samples;
1547
1548         bw = b43_is_40mhz(dev) ? 40 : 20;
1549         len = bw << 3;
1550
1551         if (test) {
1552                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1553                         bw = 82;
1554                 else
1555                         bw = 80;
1556
1557                 if (b43_is_40mhz(dev))
1558                         bw <<= 1;
1559
1560                 len = bw << 1;
1561         }
1562
1563         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1564         if (!samples) {
1565                 b43err(dev->wl, "allocation for samples generation failed\n");
1566                 return 0;
1567         }
1568         rot = (((freq * 36) / bw) << 16) / 100;
1569         angle = 0;
1570
1571         for (i = 0; i < len; i++) {
1572                 samples[i] = b43_cordic(angle);
1573                 angle += rot;
1574                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1575                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1576         }
1577
1578         i = b43_nphy_load_samples(dev, samples, len);
1579         kfree(samples);
1580         return (i < 0) ? 0 : len;
1581 }
1582
1583 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1584 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1585                                  u16 wait, bool iqmode, bool dac_test,
1586                                  bool modify_bbmult)
1587 {
1588         struct b43_phy *phy = &dev->phy;
1589         struct b43_phy_n *nphy = dev->phy.n;
1590         int i;
1591         u16 seq_mode;
1592         u32 tmp;
1593
1594         b43_nphy_stay_in_carrier_search(dev, true);
1595
1596         if (phy->rev >= 7) {
1597                 bool lpf_bw3, lpf_bw4;
1598
1599                 lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80;
1600                 lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80;
1601
1602                 if (lpf_bw3 || lpf_bw4) {
1603                         /* TODO */
1604                 } else {
1605                         u16 value = b43_nphy_read_lpf_ctl(dev, 0);
1606                         if (phy->rev >= 19)
1607                                 b43_nphy_rf_ctl_override_rev19(dev, 0x80, value,
1608                                                                0, false, 1);
1609                         else
1610                                 b43_nphy_rf_ctl_override_rev7(dev, 0x80, value,
1611                                                               0, false, 1);
1612                         nphy->lpf_bw_overrode_for_sample_play = true;
1613                 }
1614         }
1615
1616         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1617                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1618                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1619         }
1620
1621         if (modify_bbmult) {
1622                 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747;
1623                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1624         }
1625
1626         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1627
1628         if (loops != 0xFFFF)
1629                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1630         else
1631                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1632
1633         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1634
1635         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1636
1637         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1638         if (iqmode) {
1639                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1640                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1641         } else {
1642                 tmp = dac_test ? 5 : 1;
1643                 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp);
1644         }
1645         for (i = 0; i < 100; i++) {
1646                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1647                         i = 0;
1648                         break;
1649                 }
1650                 udelay(10);
1651         }
1652         if (i)
1653                 b43err(dev->wl, "run samples timeout\n");
1654
1655         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1656
1657         b43_nphy_stay_in_carrier_search(dev, false);
1658 }
1659
1660 /**************************************************
1661  * RSSI
1662  **************************************************/
1663
1664 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1665 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1666                                         s8 offset, u8 core,
1667                                         enum n_rail_type rail,
1668                                         enum n_rssi_type rssi_type)
1669 {
1670         u16 tmp;
1671         bool core1or5 = (core == 1) || (core == 5);
1672         bool core2or5 = (core == 2) || (core == 5);
1673
1674         offset = clamp_val(offset, -32, 31);
1675         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1676
1677         switch (rssi_type) {
1678         case N_RSSI_NB:
1679                 if (core1or5 && rail == N_RAIL_I)
1680                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1681                 if (core1or5 && rail == N_RAIL_Q)
1682                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1683                 if (core2or5 && rail == N_RAIL_I)
1684                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1685                 if (core2or5 && rail == N_RAIL_Q)
1686                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1687                 break;
1688         case N_RSSI_W1:
1689                 if (core1or5 && rail == N_RAIL_I)
1690                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1691                 if (core1or5 && rail == N_RAIL_Q)
1692                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1693                 if (core2or5 && rail == N_RAIL_I)
1694                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1695                 if (core2or5 && rail == N_RAIL_Q)
1696                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1697                 break;
1698         case N_RSSI_W2:
1699                 if (core1or5 && rail == N_RAIL_I)
1700                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1701                 if (core1or5 && rail == N_RAIL_Q)
1702                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1703                 if (core2or5 && rail == N_RAIL_I)
1704                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1705                 if (core2or5 && rail == N_RAIL_Q)
1706                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1707                 break;
1708         case N_RSSI_TBD:
1709                 if (core1or5 && rail == N_RAIL_I)
1710                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1711                 if (core1or5 && rail == N_RAIL_Q)
1712                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1713                 if (core2or5 && rail == N_RAIL_I)
1714                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1715                 if (core2or5 && rail == N_RAIL_Q)
1716                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1717                 break;
1718         case N_RSSI_IQ:
1719                 if (core1or5 && rail == N_RAIL_I)
1720                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1721                 if (core1or5 && rail == N_RAIL_Q)
1722                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1723                 if (core2or5 && rail == N_RAIL_I)
1724                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1725                 if (core2or5 && rail == N_RAIL_Q)
1726                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1727                 break;
1728         case N_RSSI_TSSI_2G:
1729                 if (core1or5)
1730                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1731                 if (core2or5)
1732                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1733                 break;
1734         case N_RSSI_TSSI_5G:
1735                 if (core1or5)
1736                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1737                 if (core2or5)
1738                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1739                 break;
1740         }
1741 }
1742
1743 static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code,
1744                                        enum n_rssi_type rssi_type)
1745 {
1746         /* TODO */
1747 }
1748
1749 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1750                                       enum n_rssi_type rssi_type)
1751 {
1752         u8 i;
1753         u16 reg, val;
1754
1755         if (code == 0) {
1756                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1757                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1758                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1759                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1760                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1761                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1762                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1763                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1764         } else {
1765                 for (i = 0; i < 2; i++) {
1766                         if ((code == 1 && i == 1) || (code == 2 && !i))
1767                                 continue;
1768
1769                         reg = (i == 0) ?
1770                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1771                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1772
1773                         if (rssi_type == N_RSSI_W1 ||
1774                             rssi_type == N_RSSI_W2 ||
1775                             rssi_type == N_RSSI_NB) {
1776                                 reg = (i == 0) ?
1777                                         B43_NPHY_AFECTL_C1 :
1778                                         B43_NPHY_AFECTL_C2;
1779                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1780
1781                                 reg = (i == 0) ?
1782                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1783                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1784                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1785
1786                                 if (rssi_type == N_RSSI_W1)
1787                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1788                                 else if (rssi_type == N_RSSI_W2)
1789                                         val = 16;
1790                                 else
1791                                         val = 32;
1792                                 b43_phy_set(dev, reg, val);
1793
1794                                 reg = (i == 0) ?
1795                                         B43_NPHY_TXF_40CO_B1S0 :
1796                                         B43_NPHY_TXF_40CO_B32S1;
1797                                 b43_phy_set(dev, reg, 0x0020);
1798                         } else {
1799                                 if (rssi_type == N_RSSI_TBD)
1800                                         val = 0x0100;
1801                                 else if (rssi_type == N_RSSI_IQ)
1802                                         val = 0x0200;
1803                                 else
1804                                         val = 0x0300;
1805
1806                                 reg = (i == 0) ?
1807                                         B43_NPHY_AFECTL_C1 :
1808                                         B43_NPHY_AFECTL_C2;
1809
1810                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1811                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1812
1813                                 if (rssi_type != N_RSSI_IQ &&
1814                                     rssi_type != N_RSSI_TBD) {
1815                                         enum ieee80211_band band =
1816                                                 b43_current_band(dev->wl);
1817
1818                                         if (dev->phy.rev < 7) {
1819                                                 if (b43_nphy_ipa(dev))
1820                                                         val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1821                                                 else
1822                                                         val = 0x11;
1823                                                 reg = (i == 0) ? B2056_TX0 : B2056_TX1;
1824                                                 reg |= B2056_TX_TX_SSI_MUX;
1825                                                 b43_radio_write(dev, reg, val);
1826                                         }
1827
1828                                         reg = (i == 0) ?
1829                                                 B43_NPHY_AFECTL_OVER1 :
1830                                                 B43_NPHY_AFECTL_OVER;
1831                                         b43_phy_set(dev, reg, 0x0200);
1832                                 }
1833                         }
1834                 }
1835         }
1836 }
1837
1838 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1839                                       enum n_rssi_type rssi_type)
1840 {
1841         u16 val;
1842         bool rssi_w1_w2_nb = false;
1843
1844         switch (rssi_type) {
1845         case N_RSSI_W1:
1846         case N_RSSI_W2:
1847         case N_RSSI_NB:
1848                 val = 0;
1849                 rssi_w1_w2_nb = true;
1850                 break;
1851         case N_RSSI_TBD:
1852                 val = 1;
1853                 break;
1854         case N_RSSI_IQ:
1855                 val = 2;
1856                 break;
1857         default:
1858                 val = 3;
1859         }
1860
1861         val = (val << 12) | (val << 14);
1862         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1863         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1864
1865         if (rssi_w1_w2_nb) {
1866                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1867                                 (rssi_type + 1) << 4);
1868                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1869                                 (rssi_type + 1) << 4);
1870         }
1871
1872         if (code == 0) {
1873                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1874                 if (rssi_w1_w2_nb) {
1875                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1876                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1877                                   B43_NPHY_RFCTL_CMD_CORESEL));
1878                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1879                                 ~(0x1 << 12 |
1880                                   0x1 << 5 |
1881                                   0x1 << 1 |
1882                                   0x1));
1883                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1884                                 ~B43_NPHY_RFCTL_CMD_START);
1885                         udelay(20);
1886                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1887                 }
1888         } else {
1889                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1890                 if (rssi_w1_w2_nb) {
1891                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1892                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1893                                   B43_NPHY_RFCTL_CMD_CORESEL),
1894                                 (B43_NPHY_RFCTL_CMD_RXEN |
1895                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1896                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1897                                 (0x1 << 12 |
1898                                   0x1 << 5 |
1899                                   0x1 << 1 |
1900                                   0x1));
1901                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1902                                 B43_NPHY_RFCTL_CMD_START);
1903                         udelay(20);
1904                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1905                 }
1906         }
1907 }
1908
1909 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1910 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1911                                  enum n_rssi_type type)
1912 {
1913         if (dev->phy.rev >= 19)
1914                 b43_nphy_rssi_select_rev19(dev, code, type);
1915         else if (dev->phy.rev >= 3)
1916                 b43_nphy_rev3_rssi_select(dev, code, type);
1917         else
1918                 b43_nphy_rev2_rssi_select(dev, code, type);
1919 }
1920
1921 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1922 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1923                                        enum n_rssi_type rssi_type, u8 *buf)
1924 {
1925         int i;
1926         for (i = 0; i < 2; i++) {
1927                 if (rssi_type == N_RSSI_NB) {
1928                         if (i == 0) {
1929                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1930                                                   0xFC, buf[0]);
1931                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1932                                                   0xFC, buf[1]);
1933                         } else {
1934                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1935                                                   0xFC, buf[2 * i]);
1936                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1937                                                   0xFC, buf[2 * i + 1]);
1938                         }
1939                 } else {
1940                         if (i == 0)
1941                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1942                                                   0xF3, buf[0] << 2);
1943                         else
1944                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1945                                                   0xF3, buf[2 * i + 1] << 2);
1946                 }
1947         }
1948 }
1949
1950 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1951 static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1952                               s32 *buf, u8 nsamp)
1953 {
1954         int i;
1955         int out;
1956         u16 save_regs_phy[9];
1957         u16 s[2];
1958
1959         /* TODO: rev7+ is treated like rev3+, what about rev19+? */
1960
1961         if (dev->phy.rev >= 3) {
1962                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1963                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1964                 save_regs_phy[2] = b43_phy_read(dev,
1965                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1966                 save_regs_phy[3] = b43_phy_read(dev,
1967                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1968                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1969                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1970                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1971                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1972                 save_regs_phy[8] = 0;
1973         } else {
1974                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1975                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1976                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1977                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1978                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1979                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1980                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1981                 save_regs_phy[7] = 0;
1982                 save_regs_phy[8] = 0;
1983         }
1984
1985         b43_nphy_rssi_select(dev, 5, rssi_type);
1986
1987         if (dev->phy.rev < 2) {
1988                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1989                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1990         }
1991
1992         for (i = 0; i < 4; i++)
1993                 buf[i] = 0;
1994
1995         for (i = 0; i < nsamp; i++) {
1996                 if (dev->phy.rev < 2) {
1997                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1998                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1999                 } else {
2000                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2001                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2002                 }
2003
2004                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2005                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2006                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2007                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2008         }
2009         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2010                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2011
2012         if (dev->phy.rev < 2)
2013                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2014
2015         if (dev->phy.rev >= 3) {
2016                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2017                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2018                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2019                                 save_regs_phy[2]);
2020                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2021                                 save_regs_phy[3]);
2022                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2023                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2024                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2025                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2026         } else {
2027                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2028                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2029                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2030                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2031                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2032                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2033                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2034         }
2035
2036         return out;
2037 }
2038
2039 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2040 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2041 {
2042         struct b43_phy *phy = &dev->phy;
2043         struct b43_phy_n *nphy = dev->phy.n;
2044
2045         u16 saved_regs_phy_rfctl[2];
2046         u16 saved_regs_phy[22];
2047         u16 regs_to_store_rev3[] = {
2048                 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
2049                 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
2050                 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
2051                 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
2052                 B43_NPHY_RFCTL_CMD,
2053                 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2054                 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
2055         };
2056         u16 regs_to_store_rev7[] = {
2057                 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
2058                 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
2059                 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
2060                 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4,
2061                 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6,
2062                 0x2ff,
2063                 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
2064                 B43_NPHY_RFCTL_CMD,
2065                 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2066                 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4,
2067                 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6,
2068                 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
2069         };
2070         u16 *regs_to_store;
2071         int regs_amount;
2072
2073         u16 class;
2074
2075         u16 clip_state[2];
2076         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2077
2078         u8 vcm_final = 0;
2079         s32 offset[4];
2080         s32 results[8][4] = { };
2081         s32 results_min[4] = { };
2082         s32 poll_results[4] = { };
2083
2084         u16 *rssical_radio_regs = NULL;
2085         u16 *rssical_phy_regs = NULL;
2086
2087         u16 r; /* routing */
2088         u8 rx_core_state;
2089         int core, i, j, vcm;
2090
2091         if (dev->phy.rev >= 7) {
2092                 regs_to_store = regs_to_store_rev7;
2093                 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
2094         } else {
2095                 regs_to_store = regs_to_store_rev3;
2096                 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
2097         }
2098         BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
2099
2100         class = b43_nphy_classifier(dev, 0, 0);
2101         b43_nphy_classifier(dev, 7, 4);
2102         b43_nphy_read_clip_detection(dev, clip_state);
2103         b43_nphy_write_clip_detection(dev, clip_off);
2104
2105         saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2106         saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2107         for (i = 0; i < regs_amount; i++)
2108                 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
2109
2110         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
2111         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
2112
2113         if (dev->phy.rev >= 7) {
2114                 b43_nphy_rf_ctl_override_one_to_many(dev,
2115                                                      N_RF_CTL_OVER_CMD_RXRF_PU,
2116                                                      0, 0, false);
2117                 b43_nphy_rf_ctl_override_one_to_many(dev,
2118                                                      N_RF_CTL_OVER_CMD_RX_PU,
2119                                                      1, 0, false);
2120                 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0);
2121                 b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0);
2122                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2123                         b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false,
2124                                                       0);
2125                         b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false,
2126                                                       0);
2127                 } else {
2128                         b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false,
2129                                                       0);
2130                         b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false,
2131                                                       0);
2132                 }
2133         } else {
2134                 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
2135                 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
2136                 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
2137                 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
2138                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2139                         b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
2140                         b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
2141                 } else {
2142                         b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
2143                         b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
2144                 }
2145         }
2146
2147         rx_core_state = b43_nphy_get_rx_core_state(dev);
2148         for (core = 0; core < 2; core++) {
2149                 if (!(rx_core_state & (1 << core)))
2150                         continue;
2151                 r = core ? B2056_RX1 : B2056_RX0;
2152                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
2153                                            N_RSSI_NB);
2154                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
2155                                            N_RSSI_NB);
2156
2157                 /* Grab RSSI results for every possible VCM */
2158                 for (vcm = 0; vcm < 8; vcm++) {
2159                         if (dev->phy.rev >= 7)
2160                                 b43_radio_maskset(dev,
2161                                                   core ? R2057_NB_MASTER_CORE1 :
2162                                                          R2057_NB_MASTER_CORE0,
2163                                                   ~R2057_VCM_MASK, vcm);
2164                         else
2165                                 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
2166                                                   0xE3, vcm << 2);
2167                         b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
2168                 }
2169
2170                 /* Find out which VCM got the best results */
2171                 for (i = 0; i < 4; i += 2) {
2172                         s32 currd;
2173                         s32 mind = 0x100000;
2174                         s32 minpoll = 249;
2175                         u8 minvcm = 0;
2176                         if (2 * core != i)
2177                                 continue;
2178                         for (vcm = 0; vcm < 8; vcm++) {
2179                                 currd = results[vcm][i] * results[vcm][i] +
2180                                         results[vcm][i + 1] * results[vcm][i];
2181                                 if (currd < mind) {
2182                                         mind = currd;
2183                                         minvcm = vcm;
2184                                 }
2185                                 if (results[vcm][i] < minpoll)
2186                                         minpoll = results[vcm][i];
2187                         }
2188                         vcm_final = minvcm;
2189                         results_min[i] = minpoll;
2190                 }
2191
2192                 /* Select the best VCM */
2193                 if (dev->phy.rev >= 7)
2194                         b43_radio_maskset(dev,
2195                                           core ? R2057_NB_MASTER_CORE1 :
2196                                                  R2057_NB_MASTER_CORE0,
2197                                           ~R2057_VCM_MASK, vcm);
2198                 else
2199                         b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
2200                                           0xE3, vcm_final << 2);
2201
2202                 for (i = 0; i < 4; i++) {
2203                         if (core != i / 2)
2204                                 continue;
2205                         offset[i] = -results[vcm_final][i];
2206                         if (offset[i] < 0)
2207                                 offset[i] = -((abs(offset[i]) + 4) / 8);
2208                         else
2209                                 offset[i] = (offset[i] + 4) / 8;
2210                         if (results_min[i] == 248)
2211                                 offset[i] = -32;
2212                         b43_nphy_scale_offset_rssi(dev, 0, offset[i],
2213                                                    (i / 2 == 0) ? 1 : 2,
2214                                                    (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
2215                                                    N_RSSI_NB);
2216                 }
2217         }
2218
2219         for (core = 0; core < 2; core++) {
2220                 if (!(rx_core_state & (1 << core)))
2221                         continue;
2222                 for (i = 0; i < 2; i++) {
2223                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
2224                                                    N_RAIL_I, i);
2225                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
2226                                                    N_RAIL_Q, i);
2227                         b43_nphy_poll_rssi(dev, i, poll_results, 8);
2228                         for (j = 0; j < 4; j++) {
2229                                 if (j / 2 == core) {
2230                                         offset[j] = 232 - poll_results[j];
2231                                         if (offset[j] < 0)
2232                                                 offset[j] = -(abs(offset[j] + 4) / 8);
2233                                         else
2234                                                 offset[j] = (offset[j] + 4) / 8;
2235                                         b43_nphy_scale_offset_rssi(dev, 0,
2236                                                 offset[2 * core], core + 1, j % 2, i);
2237                                 }
2238                         }
2239                 }
2240         }
2241
2242         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
2243         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
2244
2245         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2246
2247         b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
2248         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
2249         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
2250
2251         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
2252         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
2253         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2254
2255         for (i = 0; i < regs_amount; i++)
2256                 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
2257
2258         /* Store for future configuration */
2259         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2260                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2261                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2262         } else {
2263                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2264                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2265         }
2266         if (dev->phy.rev >= 7) {
2267                 rssical_radio_regs[0] = b43_radio_read(dev,
2268                                                        R2057_NB_MASTER_CORE0);
2269                 rssical_radio_regs[1] = b43_radio_read(dev,
2270                                                        R2057_NB_MASTER_CORE1);
2271         } else {
2272                 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
2273                                                        B2056_RX_RSSI_MISC);
2274                 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
2275                                                        B2056_RX_RSSI_MISC);
2276         }
2277         rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
2278         rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
2279         rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
2280         rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
2281         rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
2282         rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
2283         rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
2284         rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
2285         rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
2286         rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
2287         rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
2288         rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
2289
2290         /* Remember for which channel we store configuration */
2291         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2292                 nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq;
2293         else
2294                 nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq;
2295
2296         /* End of calibration, restore configuration */
2297         b43_nphy_classifier(dev, 7, class);
2298         b43_nphy_write_clip_detection(dev, clip_state);
2299 }
2300
2301 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2302 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
2303 {
2304         int i, j, vcm;
2305         u8 state[4];
2306         u8 code, val;
2307         u16 class, override;
2308         u8 regs_save_radio[2];
2309         u16 regs_save_phy[2];
2310
2311         s32 offset[4];
2312         u8 core;
2313         u8 rail;
2314
2315         u16 clip_state[2];
2316         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2317         s32 results_min[4] = { };
2318         u8 vcm_final[4] = { };
2319         s32 results[4][4] = { };
2320         s32 miniq[4][2] = { };
2321
2322         if (type == N_RSSI_NB) {
2323                 code = 0;
2324                 val = 6;
2325         } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
2326                 code = 25;
2327                 val = 4;
2328         } else {
2329                 B43_WARN_ON(1);
2330                 return;
2331         }
2332
2333         class = b43_nphy_classifier(dev, 0, 0);
2334         b43_nphy_classifier(dev, 7, 4);
2335         b43_nphy_read_clip_detection(dev, clip_state);
2336         b43_nphy_write_clip_detection(dev, clip_off);
2337
2338         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2339                 override = 0x140;
2340         else
2341                 override = 0x110;
2342
2343         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2344         regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
2345         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2346         b43_radio_write(dev, B2055_C1_PD_RXTX, val);
2347
2348         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2349         regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
2350         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2351         b43_radio_write(dev, B2055_C2_PD_RXTX, val);
2352
2353         state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2354         state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2355         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2356         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2357         state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
2358         state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
2359
2360         b43_nphy_rssi_select(dev, 5, type);
2361         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
2362         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
2363
2364         for (vcm = 0; vcm < 4; vcm++) {
2365                 u8 tmp[4];
2366                 for (j = 0; j < 4; j++)
2367                         tmp[j] = vcm;
2368                 if (type != N_RSSI_W2)
2369                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2370                 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
2371                 if (type == N_RSSI_W1 || type == N_RSSI_W2)
2372                         for (j = 0; j < 2; j++)
2373                                 miniq[vcm][j] = min(results[vcm][2 * j],
2374                                                     results[vcm][2 * j + 1]);
2375         }
2376
2377         for (i = 0; i < 4; i++) {
2378                 s32 mind = 0x100000;
2379                 u8 minvcm = 0;
2380                 s32 minpoll = 249;
2381                 s32 currd;
2382                 for (vcm = 0; vcm < 4; vcm++) {
2383                         if (type == N_RSSI_NB)
2384                                 currd = abs(results[vcm][i] - code * 8);
2385                         else
2386                                 currd = abs(miniq[vcm][i / 2] - code * 8);
2387
2388                         if (currd < mind) {
2389                                 mind = currd;
2390                                 minvcm = vcm;
2391                         }
2392
2393                         if (results[vcm][i] < minpoll)
2394                                 minpoll = results[vcm][i];
2395                 }
2396                 results_min[i] = minpoll;
2397                 vcm_final[i] = minvcm;
2398         }
2399
2400         if (type != N_RSSI_W2)
2401                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2402
2403         for (i = 0; i < 4; i++) {
2404                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2405
2406                 if (offset[i] < 0)
2407                         offset[i] = -((abs(offset[i]) + 4) / 8);
2408                 else
2409                         offset[i] = (offset[i] + 4) / 8;
2410
2411                 if (results_min[i] == 248)
2412                         offset[i] = code - 32;
2413
2414                 core = (i / 2) ? 2 : 1;
2415                 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
2416
2417                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2418                                                 type);
2419         }
2420
2421         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2422         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2423
2424         switch (state[2]) {
2425         case 1:
2426                 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
2427                 break;
2428         case 4:
2429                 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
2430                 break;
2431         case 2:
2432                 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2433                 break;
2434         default:
2435                 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2436                 break;
2437         }
2438
2439         switch (state[3]) {
2440         case 1:
2441                 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
2442                 break;
2443         case 4:
2444                 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
2445                 break;
2446         default:
2447                 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
2448                 break;
2449         }
2450
2451         b43_nphy_rssi_select(dev, 0, type);
2452
2453         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2454         b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2455         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2456         b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2457
2458         b43_nphy_classifier(dev, 7, class);
2459         b43_nphy_write_clip_detection(dev, clip_state);
2460         /* Specs don't say about reset here, but it makes wl and b43 dumps
2461            identical, it really seems wl performs this */
2462         b43_nphy_reset_cca(dev);
2463 }
2464
2465 /*
2466  * RSSI Calibration
2467  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2468  */
2469 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2470 {
2471         if (dev->phy.rev >= 19) {
2472                 /* TODO */
2473         } else if (dev->phy.rev >= 3) {
2474                 b43_nphy_rev3_rssi_cal(dev);
2475         } else {
2476                 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2477                 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2478                 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
2479         }
2480 }
2481
2482 /**************************************************
2483  * Workarounds
2484  **************************************************/
2485
2486 static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev)
2487 {
2488         /* TODO */
2489 }
2490
2491 static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev)
2492 {
2493         struct b43_phy *phy = &dev->phy;
2494
2495         switch (phy->rev) {
2496         /* TODO */
2497         }
2498 }
2499
2500 static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev)
2501 {
2502         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2503
2504         bool ghz5;
2505         bool ext_lna;
2506         u16 rssi_gain;
2507         struct nphy_gain_ctl_workaround_entry *e;
2508         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2509         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2510
2511         /* Prepare values */
2512         ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2513                 & B43_NPHY_BANDCTL_5GHZ;
2514         ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2515                 sprom->boardflags_lo & B43_BFL_EXTLNA;
2516         e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2517         if (ghz5 && dev->phy.rev >= 5)
2518                 rssi_gain = 0x90;
2519         else
2520                 rssi_gain = 0x50;
2521
2522         b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2523
2524         /* Set Clip 2 detect */
2525         b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2526         b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2527
2528         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2529                         0x17);
2530         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2531                         0x17);
2532         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2533         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2534         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2535         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2536         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2537                         rssi_gain);
2538         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2539                         rssi_gain);
2540         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2541                         0x17);
2542         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2543                         0x17);
2544         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2545         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2546
2547         b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2548         b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2549         b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2550         b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2551         b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2552         b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2553         b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2554         b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2555         b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2556         b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2557         b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2558         b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2559
2560         b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2561         b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2562
2563         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2564                                 e->rfseq_init);
2565
2566         b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2567         b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2568         b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2569         b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2570         b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2571         b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2572
2573         b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2574         b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2575         b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
2576         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2577         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2578         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2579                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2580         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2581                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2582         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2583 }
2584
2585 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2586 {
2587         struct b43_phy_n *nphy = dev->phy.n;
2588
2589         u8 i, j;
2590         u8 code;
2591         u16 tmp;
2592         u8 rfseq_events[3] = { 6, 8, 7 };
2593         u8 rfseq_delays[3] = { 10, 30, 1 };
2594
2595         /* Set Clip 2 detect */
2596         b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2597         b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2598
2599         /* Set narrowband clip threshold */
2600         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2601         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2602
2603         if (!b43_is_40mhz(dev)) {
2604                 /* Set dwell lengths */
2605                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2606                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2607                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2608                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2609         }
2610
2611         /* Set wideband clip 2 threshold */
2612         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2613                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2614         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2615                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2616
2617         if (!b43_is_40mhz(dev)) {
2618                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2619                         ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2620                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2621                         ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2622                 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2623                         ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2624                 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2625                         ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2626         }
2627
2628         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2629
2630         if (nphy->gain_boost) {
2631                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2632                     b43_is_40mhz(dev))
2633                         code = 4;
2634                 else
2635                         code = 5;
2636         } else {
2637                 code = b43_is_40mhz(dev) ? 6 : 7;
2638         }
2639
2640         /* Set HPVGA2 index */
2641         b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2642                         code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2643         b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2644                         code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2645
2646         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2647         /* specs say about 2 loops, but wl does 4 */
2648         for (i = 0; i < 4; i++)
2649                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2650
2651         b43_nphy_adjust_lna_gain_table(dev);
2652
2653         if (nphy->elna_gain_config) {
2654                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2655                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2656                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2657                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2658                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2659
2660                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2661                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2662                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2663                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2664                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2665
2666                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2667                 /* specs say about 2 loops, but wl does 4 */
2668                 for (i = 0; i < 4; i++)
2669                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2670                                                 (code << 8 | 0x74));
2671         }
2672
2673         if (dev->phy.rev == 2) {
2674                 for (i = 0; i < 4; i++) {
2675                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2676                                         (0x0400 * i) + 0x0020);
2677                         for (j = 0; j < 21; j++) {
2678                                 tmp = j * (i < 2 ? 3 : 1);
2679                                 b43_phy_write(dev,
2680                                         B43_NPHY_TABLE_DATALO, tmp);
2681                         }
2682                 }
2683         }
2684
2685         b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2686         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2687                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2688                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2689
2690         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2691                 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2692 }
2693
2694 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2695 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2696 {
2697         if (dev->phy.rev >= 19)
2698                 b43_nphy_gain_ctl_workarounds_rev19(dev);
2699         else if (dev->phy.rev >= 7)
2700                 b43_nphy_gain_ctl_workarounds_rev7(dev);
2701         else if (dev->phy.rev >= 3)
2702                 b43_nphy_gain_ctl_workarounds_rev3(dev);
2703         else
2704                 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2705 }
2706
2707 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2708 {
2709         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2710         struct b43_phy *phy = &dev->phy;
2711
2712         /* TX to RX */
2713         u8 tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, };
2714         u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, };
2715         /* RX to TX */
2716         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2717                                         0x1F };
2718         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2719
2720         static const u16 ntab7_15e_16e[] = { 0, 0x10f, 0x10f };
2721         u8 ntab7_138_146[] = { 0x11, 0x11 };
2722         u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2723
2724         u16 lpf_ofdm_20mhz[2], lpf_ofdm_40mhz[2], lpf_11b[2];
2725         u16 bcap_val;
2726         s16 bcap_val_11b[2], bcap_val_11n_20[2], bcap_val_11n_40[2];
2727         u16 scap_val;
2728         s16 scap_val_11b[2], scap_val_11n_20[2], scap_val_11n_40[2];
2729         bool rccal_ovrd = false;
2730
2731         u16 bias, conv, filt;
2732
2733         u32 noise_tbl[2];
2734
2735         u32 tmp32;
2736         u8 core;
2737
2738         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2739         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3);
2740         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2741         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e);
2742         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd);
2743         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2744
2745         if (phy->rev == 7) {
2746                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2747                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2748                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2749                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2750                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2751                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2752                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2753                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2754                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2755                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2756                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2757                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2758                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2759                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2760                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2761                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2762                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2763         }
2764
2765         if (phy->rev >= 16) {
2766                 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff);
2767                 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff);
2768         } else if (phy->rev <= 8) {
2769                 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2770                 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2771         }
2772
2773         if (phy->rev >= 16)
2774                 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0);
2775         else if (phy->rev >= 8)
2776                 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2777
2778         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2779         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2780         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2781         tmp32 &= 0xffffff;
2782         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2783         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e);
2784         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e);
2785
2786         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2787                                  ARRAY_SIZE(tx2rx_events));
2788         if (b43_nphy_ipa(dev))
2789                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2790                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2791
2792         b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2793         b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2794
2795         for (core = 0; core < 2; core++) {
2796                 lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10);
2797                 lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10);
2798                 lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10);
2799         }
2800
2801         bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL);
2802         scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL);
2803
2804         if (b43_nphy_ipa(dev)) {
2805                 bool ghz2 = b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ;
2806
2807                 switch (phy->radio_rev) {
2808                 case 5:
2809                         /* Check radio version (to be 0) by PHY rev for now */
2810                         if (phy->rev == 8 && b43_is_40mhz(dev)) {
2811                                 for (core = 0; core < 2; core++) {
2812                                         scap_val_11b[core] = scap_val;
2813                                         bcap_val_11b[core] = bcap_val;
2814                                         scap_val_11n_20[core] = scap_val;
2815                                         bcap_val_11n_20[core] = bcap_val;
2816                                         scap_val_11n_40[core] = 0xc;
2817                                         bcap_val_11n_40[core] = 0xc;
2818                                 }
2819
2820                                 rccal_ovrd = true;
2821                         }
2822                         if (phy->rev == 9) {
2823                                 /* TODO: Radio version 1 (e.g. BCM5357B0) */
2824                         }
2825                         break;
2826                 case 7:
2827                 case 8:
2828                         for (core = 0; core < 2; core++) {
2829                                 scap_val_11b[core] = scap_val;
2830                                 bcap_val_11b[core] = bcap_val;
2831                                 lpf_ofdm_20mhz[core] = 4;
2832                                 lpf_11b[core] = 1;
2833                                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2834                                         scap_val_11n_20[core] = 0xc;
2835                                         bcap_val_11n_20[core] = 0xc;
2836                                         scap_val_11n_40[core] = 0xa;
2837                                         bcap_val_11n_40[core] = 0xa;
2838                                 } else {
2839                                         scap_val_11n_20[core] = 0x14;
2840                                         bcap_val_11n_20[core] = 0x14;
2841                                         scap_val_11n_40[core] = 0xf;
2842                                         bcap_val_11n_40[core] = 0xf;
2843                                 }
2844                         }
2845
2846                         rccal_ovrd = true;
2847                         break;
2848                 case 9:
2849                         for (core = 0; core < 2; core++) {
2850                                 bcap_val_11b[core] = bcap_val;
2851                                 scap_val_11b[core] = scap_val;
2852                                 lpf_11b[core] = 1;
2853
2854                                 if (ghz2) {
2855                                         bcap_val_11n_20[core] = bcap_val + 13;
2856                                         scap_val_11n_20[core] = scap_val + 15;
2857                                 } else {
2858                                         bcap_val_11n_20[core] = bcap_val + 14;
2859                                         scap_val_11n_20[core] = scap_val + 15;
2860                                 }
2861                                 lpf_ofdm_20mhz[core] = 4;
2862
2863                                 if (ghz2) {
2864                                         bcap_val_11n_40[core] = bcap_val - 7;
2865                                         scap_val_11n_40[core] = scap_val - 5;
2866                                 } else {
2867                                         bcap_val_11n_40[core] = bcap_val + 2;
2868                                         scap_val_11n_40[core] = scap_val + 4;
2869                                 }
2870                                 lpf_ofdm_40mhz[core] = 4;
2871                         }
2872
2873                         rccal_ovrd = true;
2874                         break;
2875                 case 14:
2876                         for (core = 0; core < 2; core++) {
2877                                 bcap_val_11b[core] = bcap_val;
2878                                 scap_val_11b[core] = scap_val;
2879                                 lpf_11b[core] = 1;
2880                         }
2881
2882                         bcap_val_11n_20[0] = bcap_val + 20;
2883                         scap_val_11n_20[0] = scap_val + 20;
2884                         lpf_ofdm_20mhz[0] = 3;
2885
2886                         bcap_val_11n_20[1] = bcap_val + 16;
2887                         scap_val_11n_20[1] = scap_val + 16;
2888                         lpf_ofdm_20mhz[1] = 3;
2889
2890                         bcap_val_11n_40[0] = bcap_val + 20;
2891                         scap_val_11n_40[0] = scap_val + 20;
2892                         lpf_ofdm_40mhz[0] = 4;
2893
2894                         bcap_val_11n_40[1] = bcap_val + 10;
2895                         scap_val_11n_40[1] = scap_val + 10;
2896                         lpf_ofdm_40mhz[1] = 4;
2897
2898                         rccal_ovrd = true;
2899                         break;
2900                 }
2901         } else {
2902                 if (phy->radio_rev == 5) {
2903                         for (core = 0; core < 2; core++) {
2904                                 lpf_ofdm_20mhz[core] = 1;
2905                                 lpf_ofdm_40mhz[core] = 3;
2906                                 scap_val_11b[core] = scap_val;
2907                                 bcap_val_11b[core] = bcap_val;
2908                                 scap_val_11n_20[core] = 0x11;
2909                                 scap_val_11n_40[core] = 0x11;
2910                                 bcap_val_11n_20[core] = 0x13;
2911                                 bcap_val_11n_40[core] = 0x13;
2912                         }
2913
2914                         rccal_ovrd = true;
2915                 }
2916         }
2917         if (rccal_ovrd) {
2918                 u16 rx2tx_lut_20_11b[2], rx2tx_lut_20_11n[2], rx2tx_lut_40_11n[2];
2919                 u8 rx2tx_lut_extra = 1;
2920
2921                 for (core = 0; core < 2; core++) {
2922                         bcap_val_11b[core] = clamp_val(bcap_val_11b[core], 0, 0x1f);
2923                         scap_val_11b[core] = clamp_val(scap_val_11b[core], 0, 0x1f);
2924                         bcap_val_11n_20[core] = clamp_val(bcap_val_11n_20[core], 0, 0x1f);
2925                         scap_val_11n_20[core] = clamp_val(scap_val_11n_20[core], 0, 0x1f);
2926                         bcap_val_11n_40[core] = clamp_val(bcap_val_11n_40[core], 0, 0x1f);
2927                         scap_val_11n_40[core] = clamp_val(scap_val_11n_40[core], 0, 0x1f);
2928
2929                         rx2tx_lut_20_11b[core] = (rx2tx_lut_extra << 13) |
2930                                                  (bcap_val_11b[core] << 8) |
2931                                                  (scap_val_11b[core] << 3) |
2932                                                  lpf_11b[core];
2933                         rx2tx_lut_20_11n[core] = (rx2tx_lut_extra << 13) |
2934                                                  (bcap_val_11n_20[core] << 8) |
2935                                                  (scap_val_11n_20[core] << 3) |
2936                                                  lpf_ofdm_20mhz[core];
2937                         rx2tx_lut_40_11n[core] = (rx2tx_lut_extra << 13) |
2938                                                  (bcap_val_11n_40[core] << 8) |
2939                                                  (scap_val_11n_40[core] << 3) |
2940                                                  lpf_ofdm_40mhz[core];
2941                 }
2942
2943                 for (core = 0; core < 2; core++) {
2944                         b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2945                                        rx2tx_lut_20_11b[core]);
2946                         b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2947                                        rx2tx_lut_20_11n[core]);
2948                         b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2949                                        rx2tx_lut_20_11n[core]);
2950                         b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2951                                        rx2tx_lut_40_11n[core]);
2952                         b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2953                                        rx2tx_lut_40_11n[core]);
2954                         b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2955                                        rx2tx_lut_40_11n[core]);
2956                         b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2957                                        rx2tx_lut_40_11n[core]);
2958                         b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2959                                        rx2tx_lut_40_11n[core]);
2960                 }
2961         }
2962
2963         b43_phy_write(dev, 0x32F, 0x3);
2964
2965         if (phy->radio_rev == 4 || phy->radio_rev == 6)
2966                 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
2967
2968         if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2969                 if (sprom->revision &&
2970                     sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2971                         b43_radio_write(dev, 0x5, 0x05);
2972                         b43_radio_write(dev, 0x6, 0x30);
2973                         b43_radio_write(dev, 0x7, 0x00);
2974                         b43_radio_set(dev, 0x4f, 0x1);
2975                         b43_radio_set(dev, 0xd4, 0x1);
2976                         bias = 0x1f;
2977                         conv = 0x6f;
2978                         filt = 0xaa;
2979                 } else {
2980                         bias = 0x2b;
2981                         conv = 0x7f;
2982                         filt = 0xee;
2983                 }
2984                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2985                         for (core = 0; core < 2; core++) {
2986                                 if (core == 0) {
2987                                         b43_radio_write(dev, 0x5F, bias);
2988                                         b43_radio_write(dev, 0x64, conv);
2989                                         b43_radio_write(dev, 0x66, filt);
2990                                 } else {
2991                                         b43_radio_write(dev, 0xE8, bias);
2992                                         b43_radio_write(dev, 0xE9, conv);
2993                                         b43_radio_write(dev, 0xEB, filt);
2994                                 }
2995                         }
2996                 }
2997         }
2998
2999         if (b43_nphy_ipa(dev)) {
3000                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3001                         if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
3002                             phy->radio_rev == 6) {
3003                                 for (core = 0; core < 2; core++) {
3004                                         if (core == 0)
3005                                                 b43_radio_write(dev, 0x51,
3006                                                                 0x7f);
3007                                         else
3008                                                 b43_radio_write(dev, 0xd6,
3009                                                                 0x7f);
3010                                 }
3011                         }
3012                         switch (phy->radio_rev) {
3013                         case 3:
3014                                 for (core = 0; core < 2; core++) {
3015                                         if (core == 0) {
3016                                                 b43_radio_write(dev, 0x64,
3017                                                                 0x13);
3018                                                 b43_radio_write(dev, 0x5F,
3019                                                                 0x1F);
3020                                                 b43_radio_write(dev, 0x66,
3021                                                                 0xEE);
3022                                                 b43_radio_write(dev, 0x59,
3023                                                                 0x8A);
3024                                                 b43_radio_write(dev, 0x80,
3025                                                                 0x3E);
3026                                         } else {
3027                                                 b43_radio_write(dev, 0x69,
3028                                                                 0x13);
3029                                                 b43_radio_write(dev, 0xE8,
3030                                                                 0x1F);
3031                                                 b43_radio_write(dev, 0xEB,
3032                                                                 0xEE);
3033                                                 b43_radio_write(dev, 0xDE,
3034                                                                 0x8A);
3035                                                 b43_radio_write(dev, 0x105,
3036                                                                 0x3E);
3037                                         }
3038                                 }
3039                                 break;
3040                         case 7:
3041                         case 8:
3042                                 if (!b43_is_40mhz(dev)) {
3043                                         b43_radio_write(dev, 0x5F, 0x14);
3044                                         b43_radio_write(dev, 0xE8, 0x12);
3045                                 } else {
3046                                         b43_radio_write(dev, 0x5F, 0x16);
3047                                         b43_radio_write(dev, 0xE8, 0x16);
3048                                 }
3049                                 break;
3050                         case 14:
3051                                 for (core = 0; core < 2; core++) {
3052                                         int o = core ? 0x85 : 0;
3053
3054                                         b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13);
3055                                         b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21);
3056                                         b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff);
3057                                         b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88);
3058                                         b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23);
3059                                         b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16);
3060                                         b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e);
3061                                         b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10);
3062                                 }
3063                                 break;
3064                         }
3065                 } else {
3066                         u16 freq = phy->chandef->chan->center_freq;
3067                         if ((freq >= 5180 && freq <= 5230) ||
3068                             (freq >= 5745 && freq <= 5805)) {
3069                                 b43_radio_write(dev, 0x7D, 0xFF);
3070                                 b43_radio_write(dev, 0xFE, 0xFF);
3071                         }
3072                 }
3073         } else {
3074                 if (phy->radio_rev != 5) {
3075                         for (core = 0; core < 2; core++) {
3076                                 if (core == 0) {
3077                                         b43_radio_write(dev, 0x5c, 0x61);
3078                                         b43_radio_write(dev, 0x51, 0x70);
3079                                 } else {
3080                                         b43_radio_write(dev, 0xe1, 0x61);
3081                                         b43_radio_write(dev, 0xd6, 0x70);
3082                                 }
3083                         }
3084                 }
3085         }
3086
3087         if (phy->radio_rev == 4) {
3088                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
3089                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
3090                 for (core = 0; core < 2; core++) {
3091                         if (core == 0) {
3092                                 b43_radio_write(dev, 0x1a1, 0x00);
3093                                 b43_radio_write(dev, 0x1a2, 0x3f);
3094                                 b43_radio_write(dev, 0x1a6, 0x3f);
3095                         } else {
3096                                 b43_radio_write(dev, 0x1a7, 0x00);
3097                                 b43_radio_write(dev, 0x1ab, 0x3f);
3098                                 b43_radio_write(dev, 0x1ac, 0x3f);
3099                         }
3100                 }
3101         } else {
3102                 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
3103                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
3104                 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
3105                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
3106
3107                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
3108                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
3109                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
3110                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
3111                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0);
3112                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0);
3113
3114                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
3115                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
3116                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
3117                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
3118         }
3119
3120         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
3121
3122         b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
3123         b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146);
3124         b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
3125         b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133);
3126         b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146);
3127         b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
3128         b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
3129
3130         b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl);
3131         noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D;
3132         b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl);
3133
3134         b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl);
3135         noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D;
3136         b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl);
3137
3138         b43_nphy_gain_ctl_workarounds(dev);
3139
3140         /* TODO
3141         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
3142                             aux_adc_vmid_rev7_core0);
3143         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
3144                             aux_adc_vmid_rev7_core1);
3145         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
3146                             aux_adc_gain_rev7);
3147         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
3148                             aux_adc_gain_rev7);
3149         */
3150 }
3151
3152 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
3153 {
3154         struct b43_phy_n *nphy = dev->phy.n;
3155         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3156
3157         /* TX to RX */
3158         u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
3159         u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
3160         /* RX to TX */
3161         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
3162                                         0x1F };
3163         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
3164         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
3165         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
3166
3167         u16 vmids[5][4] = {
3168                 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
3169                 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
3170                 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
3171                 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
3172                 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
3173         };
3174         u16 gains[5][4] = {
3175                 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
3176                 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
3177                 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
3178                 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
3179                 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
3180         };
3181         u16 *vmid, *gain;
3182
3183         u8 pdet_range;
3184         u16 tmp16;
3185         u32 tmp32;
3186
3187         b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
3188         b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
3189
3190         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
3191         tmp32 &= 0xffffff;
3192         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
3193
3194         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
3195         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
3196         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
3197         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
3198         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
3199         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
3200
3201         b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
3202         b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
3203
3204         /* TX to RX */
3205         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
3206                                  ARRAY_SIZE(tx2rx_events));
3207
3208         /* RX to TX */
3209         if (b43_nphy_ipa(dev))
3210                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
3211                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
3212         if (nphy->hw_phyrxchain != 3 &&
3213             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
3214                 if (b43_nphy_ipa(dev)) {
3215                         rx2tx_delays[5] = 59;
3216                         rx2tx_delays[6] = 1;
3217                         rx2tx_events[7] = 0x1F;
3218                 }
3219                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
3220                                          ARRAY_SIZE(rx2tx_events));
3221         }
3222
3223         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
3224                 0x2 : 0x9C40;
3225         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
3226
3227         b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
3228
3229         if (!b43_is_40mhz(dev)) {
3230                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
3231                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
3232         } else {
3233                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
3234                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
3235         }
3236
3237         b43_nphy_gain_ctl_workarounds(dev);
3238
3239         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
3240         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
3241
3242         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3243                 pdet_range = sprom->fem.ghz2.pdet_range;
3244         else
3245                 pdet_range = sprom->fem.ghz5.pdet_range;
3246         vmid = vmids[min_t(u16, pdet_range, 4)];
3247         gain = gains[min_t(u16, pdet_range, 4)];
3248         switch (pdet_range) {
3249         case 3:
3250                 if (!(dev->phy.rev >= 4 &&
3251                       b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
3252                         break;
3253                 /* FALL THROUGH */
3254         case 0:
3255         case 1:
3256                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
3257                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
3258                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
3259                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
3260                 break;
3261         case 2:
3262                 if (dev->phy.rev >= 6) {
3263                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3264                                 vmid[3] = 0x94;
3265                         else
3266                                 vmid[3] = 0x8e;
3267                         gain[3] = 3;
3268                 } else if (dev->phy.rev == 5) {
3269                         vmid[3] = 0x84;
3270                         gain[3] = 2;
3271                 }
3272                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
3273                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
3274                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
3275                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
3276                 break;
3277         case 4:
3278         case 5:
3279                 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
3280                         if (pdet_range == 4) {
3281                                 vmid[3] = 0x8e;
3282                                 tmp16 = 0x96;
3283                                 gain[3] = 0x2;
3284                         } else {
3285                                 vmid[3] = 0x89;
3286                                 tmp16 = 0x89;
3287                                 gain[3] = 0;
3288                         }
3289                 } else {
3290                         if (pdet_range == 4) {
3291                                 vmid[3] = 0x89;
3292                                 tmp16 = 0x8b;
3293                                 gain[3] = 0x2;
3294                         } else {
3295                                 vmid[3] = 0x74;
3296                                 tmp16 = 0x70;
3297                                 gain[3] = 0;
3298                         }
3299                 }
3300                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
3301                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
3302                 vmid[3] = tmp16;
3303                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
3304                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
3305                 break;
3306         }
3307
3308         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3309         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3310         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3311         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3312         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3313         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3314         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3315         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3316         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3317         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3318         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3319         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3320
3321         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
3322
3323         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
3324              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
3325             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
3326              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
3327                 tmp32 = 0x00088888;
3328         else
3329                 tmp32 = 0x88888888;
3330         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
3331         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
3332         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
3333
3334         if (dev->phy.rev == 4 &&
3335             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3336                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
3337                                 0x70);
3338                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
3339                                 0x70);
3340         }
3341
3342         /* Dropped probably-always-true condition */
3343         b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
3344         b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
3345         b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
3346         b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
3347         b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
3348         b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
3349         b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
3350         b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
3351         b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
3352         b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
3353         b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
3354         b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
3355
3356         if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
3357                 ; /* TODO: 0x0080000000000000 HF */
3358 }
3359
3360 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
3361 {
3362         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3363         struct b43_phy *phy = &dev->phy;
3364         struct b43_phy_n *nphy = phy->n;
3365
3366         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
3367         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
3368
3369         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
3370         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
3371
3372         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
3373             dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
3374                 delays1[0] = 0x1;
3375                 delays1[5] = 0x14;
3376         }
3377
3378         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
3379             nphy->band5g_pwrgain) {
3380                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
3381                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
3382         } else {
3383                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
3384                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
3385         }
3386
3387         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
3388         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
3389         if (dev->phy.rev < 3) {
3390                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
3391                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
3392         }
3393
3394         if (dev->phy.rev < 2) {
3395                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
3396                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
3397                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
3398                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
3399                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
3400                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
3401         }
3402
3403         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
3404         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
3405         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
3406         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
3407
3408         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
3409         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
3410
3411         b43_nphy_gain_ctl_workarounds(dev);
3412
3413         if (dev->phy.rev < 2) {
3414                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
3415                         b43_hf_write(dev, b43_hf_read(dev) |
3416                                         B43_HF_MLADVW);
3417         } else if (dev->phy.rev == 2) {
3418                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
3419                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
3420         }
3421
3422         if (dev->phy.rev < 2)
3423                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
3424                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
3425
3426         /* Set phase track alpha and beta */
3427         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
3428         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
3429         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
3430         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
3431         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
3432         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
3433
3434         if (dev->phy.rev < 3) {
3435                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
3436                              ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
3437                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
3438                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
3439                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
3440         }
3441
3442         if (dev->phy.rev == 2)
3443                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
3444                                 B43_NPHY_FINERX2_CGC_DECGC);
3445 }
3446
3447 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
3448 static void b43_nphy_workarounds(struct b43_wldev *dev)
3449 {
3450         struct b43_phy *phy = &dev->phy;
3451         struct b43_phy_n *nphy = phy->n;
3452
3453         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3454                 b43_nphy_classifier(dev, 1, 0);
3455         else
3456                 b43_nphy_classifier(dev, 1, 1);
3457
3458         if (nphy->hang_avoid)
3459                 b43_nphy_stay_in_carrier_search(dev, 1);
3460
3461         b43_phy_set(dev, B43_NPHY_IQFLIP,
3462                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
3463
3464         /* TODO: rev19+ */
3465         if (dev->phy.rev >= 7)
3466                 b43_nphy_workarounds_rev7plus(dev);
3467         else if (dev->phy.rev >= 3)
3468                 b43_nphy_workarounds_rev3plus(dev);
3469         else
3470                 b43_nphy_workarounds_rev1_2(dev);
3471
3472         if (nphy->hang_avoid)
3473                 b43_nphy_stay_in_carrier_search(dev, 0);
3474 }
3475
3476 /**************************************************
3477  * Tx/Rx common
3478  **************************************************/
3479
3480 /*
3481  * Transmits a known value for LO calibration
3482  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
3483  */
3484 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
3485                             bool iqmode, bool dac_test, bool modify_bbmult)
3486 {
3487         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
3488         if (samp == 0)
3489                 return -1;
3490         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test,
3491                              modify_bbmult);
3492         return 0;
3493 }
3494
3495 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
3496 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
3497 {
3498         struct b43_phy_n *nphy = dev->phy.n;
3499
3500         bool override = false;
3501         u16 chain = 0x33;
3502
3503         if (nphy->txrx_chain == 0) {
3504                 chain = 0x11;
3505                 override = true;
3506         } else if (nphy->txrx_chain == 1) {
3507                 chain = 0x22;
3508                 override = true;
3509         }
3510
3511         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3512                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
3513                         chain);
3514
3515         if (override)
3516                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
3517                                 B43_NPHY_RFSEQMODE_CAOVER);
3518         else
3519                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3520                                 ~B43_NPHY_RFSEQMODE_CAOVER);
3521 }
3522
3523 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
3524 static void b43_nphy_stop_playback(struct b43_wldev *dev)
3525 {
3526         struct b43_phy *phy = &dev->phy;
3527         struct b43_phy_n *nphy = dev->phy.n;
3528         u16 tmp;
3529
3530         if (nphy->hang_avoid)
3531                 b43_nphy_stay_in_carrier_search(dev, 1);
3532
3533         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
3534         if (tmp & 0x1)
3535                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
3536         else if (tmp & 0x2)
3537                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3538
3539         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3540
3541         if (nphy->bb_mult_save & 0x80000000) {
3542                 tmp = nphy->bb_mult_save & 0xFFFF;
3543                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3544                 nphy->bb_mult_save = 0;
3545         }
3546
3547         if (phy->rev >= 7 && nphy->lpf_bw_overrode_for_sample_play) {
3548                 if (phy->rev >= 19)
3549                         b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true,
3550                                                        1);
3551                 else
3552                         b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1);
3553                 nphy->lpf_bw_overrode_for_sample_play = false;
3554         }
3555
3556         if (nphy->hang_avoid)
3557                 b43_nphy_stay_in_carrier_search(dev, 0);
3558 }
3559
3560 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3561 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3562                                         struct nphy_txgains target,
3563                                         struct nphy_iqcal_params *params)
3564 {
3565         struct b43_phy *phy = &dev->phy;
3566         int i, j, indx;
3567         u16 gain;
3568
3569         if (dev->phy.rev >= 3) {
3570                 params->tx_lpf = target.tx_lpf[core]; /* Rev 7+ */
3571                 params->txgm = target.txgm[core];
3572                 params->pga = target.pga[core];
3573                 params->pad = target.pad[core];
3574                 params->ipa = target.ipa[core];
3575                 if (phy->rev >= 19) {
3576                         /* TODO */
3577                 } else if (phy->rev >= 7) {
3578                         params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15);
3579                 } else {
3580                         params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa);
3581                 }
3582                 for (j = 0; j < 5; j++)
3583                         params->ncorr[j] = 0x79;
3584         } else {
3585                 gain = (target.pad[core]) | (target.pga[core] << 4) |
3586                         (target.txgm[core] << 8);
3587
3588                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3589                         1 : 0;
3590                 for (i = 0; i < 9; i++)
3591                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
3592                                 break;
3593                 i = min(i, 8);
3594
3595                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3596                 params->pga = tbl_iqcal_gainparams[indx][i][2];
3597                 params->pad = tbl_iqcal_gainparams[indx][i][3];
3598                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3599                                         (params->pad << 2);
3600                 for (j = 0; j < 4; j++)
3601                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3602         }
3603 }
3604
3605 /**************************************************
3606  * Tx and Rx
3607  **************************************************/
3608
3609 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3610 {//TODO
3611 }
3612
3613 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3614                                                         bool ignore_tssi)
3615 {//TODO
3616         return B43_TXPWR_RES_DONE;
3617 }
3618
3619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3620 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3621 {
3622         struct b43_phy *phy = &dev->phy;
3623         struct b43_phy_n *nphy = dev->phy.n;
3624         u8 i;
3625         u16 bmask, val, tmp;
3626         enum ieee80211_band band = b43_current_band(dev->wl);
3627
3628         if (nphy->hang_avoid)
3629                 b43_nphy_stay_in_carrier_search(dev, 1);
3630
3631         nphy->txpwrctrl = enable;
3632         if (!enable) {
3633                 if (dev->phy.rev >= 3 &&
3634                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3635                      (B43_NPHY_TXPCTL_CMD_COEFF |
3636                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3637                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3638                         /* We disable enabled TX pwr ctl, save it's state */
3639                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3640                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3641                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3642                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3643                 }
3644
3645                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3646                 for (i = 0; i < 84; i++)
3647                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
3648
3649                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3650                 for (i = 0; i < 84; i++)
3651                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
3652
3653                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3654                 if (dev->phy.rev >= 3)
3655                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3656                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
3657
3658                 if (dev->phy.rev >= 3) {
3659                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3660                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3661                 } else {
3662                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3663                 }
3664
3665                 if (dev->phy.rev == 2)
3666                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3667                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3668                 else if (dev->phy.rev < 2)
3669                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3670                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
3671
3672                 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
3673                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
3674         } else {
3675                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3676                                     nphy->adj_pwr_tbl);
3677                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3678                                     nphy->adj_pwr_tbl);
3679
3680                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3681                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3682                 /* wl does useless check for "enable" param here */
3683                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3684                 if (dev->phy.rev >= 3) {
3685                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3686                         if (val)
3687                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3688                 }
3689                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
3690
3691                 if (band == IEEE80211_BAND_5GHZ) {
3692                         if (phy->rev >= 19) {
3693                                 /* TODO */
3694                         } else if (phy->rev >= 7) {
3695                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3696                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
3697                                                 0x32);
3698                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3699                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3700                                                 0x32);
3701                         } else {
3702                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3703                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
3704                                                 0x64);
3705                                 if (phy->rev > 1)
3706                                         b43_phy_maskset(dev,
3707                                                         B43_NPHY_TXPCTL_INIT,
3708                                                         ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3709                                                         0x64);
3710                         }
3711                 }
3712
3713                 if (dev->phy.rev >= 3) {
3714                         if (nphy->tx_pwr_idx[0] != 128 &&
3715                             nphy->tx_pwr_idx[1] != 128) {
3716                                 /* Recover TX pwr ctl state */
3717                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3718                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
3719                                                 nphy->tx_pwr_idx[0]);
3720                                 if (dev->phy.rev > 1)
3721                                         b43_phy_maskset(dev,
3722                                                 B43_NPHY_TXPCTL_INIT,
3723                                                 ~0xff, nphy->tx_pwr_idx[1]);
3724                         }
3725                 }
3726
3727                 if (phy->rev >= 7) {
3728                         /* TODO */
3729                 }
3730
3731                 if (dev->phy.rev >= 3) {
3732                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3733                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3734                 } else {
3735                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3736                 }
3737
3738                 if (dev->phy.rev == 2)
3739                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3740                 else if (dev->phy.rev < 2)
3741                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
3742
3743                 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
3744                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
3745
3746                 if (b43_nphy_ipa(dev)) {
3747                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3748                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
3749                 }
3750         }
3751
3752         if (nphy->hang_avoid)
3753                 b43_nphy_stay_in_carrier_search(dev, 0);
3754 }
3755
3756 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
3757 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
3758 {
3759         struct b43_phy *phy = &dev->phy;
3760         struct b43_phy_n *nphy = dev->phy.n;
3761         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3762
3763         u8 txpi[2], bbmult, i;
3764         u16 tmp, radio_gain, dac_gain;
3765         u16 freq = phy->chandef->chan->center_freq;
3766         u32 txgain;
3767         /* u32 gaintbl; rev3+ */
3768
3769         if (nphy->hang_avoid)
3770                 b43_nphy_stay_in_carrier_search(dev, 1);
3771
3772         /* TODO: rev19+ */
3773         if (dev->phy.rev >= 7) {
3774                 txpi[0] = txpi[1] = 30;
3775         } else if (dev->phy.rev >= 3) {
3776                 txpi[0] = 40;
3777                 txpi[1] = 40;
3778         } else if (sprom->revision < 4) {
3779                 txpi[0] = 72;
3780                 txpi[1] = 72;
3781         } else {
3782                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3783                         txpi[0] = sprom->txpid2g[0];
3784                         txpi[1] = sprom->txpid2g[1];
3785                 } else if (freq >= 4900 && freq < 5100) {
3786                         txpi[0] = sprom->txpid5gl[0];
3787                         txpi[1] = sprom->txpid5gl[1];
3788                 } else if (freq >= 5100 && freq < 5500) {
3789                         txpi[0] = sprom->txpid5g[0];
3790                         txpi[1] = sprom->txpid5g[1];
3791                 } else if (freq >= 5500) {
3792                         txpi[0] = sprom->txpid5gh[0];
3793                         txpi[1] = sprom->txpid5gh[1];
3794                 } else {
3795                         txpi[0] = 91;
3796                         txpi[1] = 91;
3797                 }
3798         }
3799         if (dev->phy.rev < 7 &&
3800             (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
3801                 txpi[0] = txpi[1] = 91;
3802
3803         /*
3804         for (i = 0; i < 2; i++) {
3805                 nphy->txpwrindex[i].index_internal = txpi[i];
3806                 nphy->txpwrindex[i].index_internal_save = txpi[i];
3807         }
3808         */
3809
3810         for (i = 0; i < 2; i++) {
3811                 const u32 *table = b43_nphy_get_tx_gain_table(dev);
3812
3813                 if (!table)
3814                         break;
3815                 txgain = *(table + txpi[i]);
3816
3817                 if (dev->phy.rev >= 3)
3818                         radio_gain = (txgain >> 16) & 0x1FFFF;
3819                 else
3820                         radio_gain = (txgain >> 16) & 0x1FFF;
3821
3822                 if (dev->phy.rev >= 7)
3823                         dac_gain = (txgain >> 8) & 0x7;
3824                 else
3825                         dac_gain = (txgain >> 8) & 0x3F;
3826                 bbmult = txgain & 0xFF;
3827
3828                 if (dev->phy.rev >= 3) {
3829                         if (i == 0)
3830                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3831                         else
3832                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3833                 } else {
3834                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3835                 }
3836
3837                 if (i == 0)
3838                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3839                 else
3840                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3841
3842                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3843
3844                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3845                 if (i == 0)
3846                         tmp = (tmp & 0x00FF) | (bbmult << 8);
3847                 else
3848                         tmp = (tmp & 0xFF00) | bbmult;
3849                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3850
3851                 if (b43_nphy_ipa(dev)) {
3852                         u32 tmp32;
3853                         u16 reg = (i == 0) ?
3854                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3855                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3856                                                               576 + txpi[i]));
3857                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3858                         b43_phy_set(dev, reg, 0x4);
3859                 }
3860         }
3861
3862         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3863
3864         if (nphy->hang_avoid)
3865                 b43_nphy_stay_in_carrier_search(dev, 0);
3866 }
3867
3868 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3869 {
3870         struct b43_phy *phy = &dev->phy;
3871
3872         u8 core;
3873         u16 r; /* routing */
3874
3875         if (phy->rev >= 19) {
3876                 /* TODO */
3877         } else if (phy->rev >= 7) {
3878                 for (core = 0; core < 2; core++) {
3879                         r = core ? 0x190 : 0x170;
3880                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3881                                 b43_radio_write(dev, r + 0x5, 0x5);
3882                                 b43_radio_write(dev, r + 0x9, 0xE);
3883                                 if (phy->rev != 5)
3884                                         b43_radio_write(dev, r + 0xA, 0);
3885                                 if (phy->rev != 7)
3886                                         b43_radio_write(dev, r + 0xB, 1);
3887                                 else
3888                                         b43_radio_write(dev, r + 0xB, 0x31);
3889                         } else {
3890                                 b43_radio_write(dev, r + 0x5, 0x9);
3891                                 b43_radio_write(dev, r + 0x9, 0xC);
3892                                 b43_radio_write(dev, r + 0xB, 0x0);
3893                                 if (phy->rev != 5)
3894                                         b43_radio_write(dev, r + 0xA, 1);
3895                                 else
3896                                         b43_radio_write(dev, r + 0xA, 0x31);
3897                         }
3898                         b43_radio_write(dev, r + 0x6, 0);
3899                         b43_radio_write(dev, r + 0x7, 0);
3900                         b43_radio_write(dev, r + 0x8, 3);
3901                         b43_radio_write(dev, r + 0xC, 0);
3902                 }
3903         } else {
3904                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3905                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3906                 else
3907                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3908                 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3909                 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3910
3911                 for (core = 0; core < 2; core++) {
3912                         r = core ? B2056_TX1 : B2056_TX0;
3913
3914                         b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3915                         b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3916                         b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3917                         b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3918                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3919                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3920                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3921                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3922                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3923                                                 0x5);
3924                                 if (phy->rev != 5)
3925                                         b43_radio_write(dev, r | B2056_TX_TSSIA,
3926                                                         0x00);
3927                                 if (phy->rev >= 5)
3928                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3929                                                         0x31);
3930                                 else
3931                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3932                                                         0x11);
3933                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3934                                                 0xE);
3935                         } else {
3936                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3937                                                 0x9);
3938                                 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3939                                 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3940                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3941                                                 0xC);
3942                         }
3943                 }
3944         }
3945 }
3946
3947 /*
3948  * Stop radio and transmit known signal. Then check received signal strength to
3949  * get TSSI (Transmit Signal Strength Indicator).
3950  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3951  */
3952 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3953 {
3954         struct b43_phy *phy = &dev->phy;
3955         struct b43_phy_n *nphy = dev->phy.n;
3956
3957         u32 tmp;
3958         s32 rssi[4] = { };
3959
3960         if (phy->chandef->chan->flags & IEEE80211_CHAN_NO_IR)
3961                 return;
3962
3963         if (b43_nphy_ipa(dev))
3964                 b43_nphy_ipa_internal_tssi_setup(dev);
3965
3966         if (phy->rev >= 19)
3967                 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0);
3968         else if (phy->rev >= 7)
3969                 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0);
3970         else if (phy->rev >= 3)
3971                 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3972
3973         b43_nphy_stop_playback(dev);
3974         b43_nphy_tx_tone(dev, 4000, 0, false, false, false);
3975         udelay(20);
3976         tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3977         b43_nphy_stop_playback(dev);
3978
3979         b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3980
3981         if (phy->rev >= 19)
3982                 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0);
3983         else if (phy->rev >= 7)
3984                 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0);
3985         else if (phy->rev >= 3)
3986                 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3987
3988         if (phy->rev >= 19) {
3989                 /* TODO */
3990                 return;
3991         } else if (phy->rev >= 3) {
3992                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3993                 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3994         } else {
3995                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3996                 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3997         }
3998         nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3999         nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
4000 }
4001
4002 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
4003 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
4004 {
4005         struct b43_phy_n *nphy = dev->phy.n;
4006
4007         u8 idx, delta;
4008         u8 i, stf_mode;
4009
4010         /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
4011          * 21 groups, each containing 4 entries.
4012          *
4013          * First group has entries for CCK modulation.
4014          * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
4015          *
4016          * Group 0 is for CCK
4017          * Groups 1..4 use BPSK (group per coding rate)
4018          * Groups 5..8 use QPSK (group per coding rate)
4019          * Groups 9..12 use 16-QAM (group per coding rate)
4020          * Groups 13..16 use 64-QAM (group per coding rate)
4021          * Groups 17..20 are unknown
4022          */
4023
4024         for (i = 0; i < 4; i++)
4025                 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
4026
4027         for (stf_mode = 0; stf_mode < 4; stf_mode++) {
4028                 delta = 0;
4029                 switch (stf_mode) {
4030                 case 0:
4031                         if (b43_is_40mhz(dev) && dev->phy.rev >= 5) {
4032                                 idx = 68;
4033                         } else {
4034                                 delta = 1;
4035                                 idx = b43_is_40mhz(dev) ? 52 : 4;
4036                         }
4037                         break;
4038                 case 1:
4039                         idx = b43_is_40mhz(dev) ? 76 : 28;
4040                         break;
4041                 case 2:
4042                         idx = b43_is_40mhz(dev) ? 84 : 36;
4043                         break;
4044                 case 3:
4045                         idx = b43_is_40mhz(dev) ? 92 : 44;
4046                         break;
4047                 }
4048
4049                 for (i = 0; i < 20; i++) {
4050                         nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
4051                                 nphy->tx_power_offset[idx];
4052                         if (i == 0)
4053                                 idx += delta;
4054                         if (i == 14)
4055                                 idx += 1 - delta;
4056                         if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
4057                             i == 13)
4058                                 idx += 1;
4059                 }
4060         }
4061 }
4062
4063 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
4064 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
4065 {
4066         struct b43_phy *phy = &dev->phy;
4067         struct b43_phy_n *nphy = dev->phy.n;
4068         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4069
4070         s16 a1[2], b0[2], b1[2];
4071         u8 idle[2];
4072         s8 target[2];
4073         s32 num, den, pwr;
4074         u32 regval[64];
4075
4076         u16 freq = phy->chandef->chan->center_freq;
4077         u16 tmp;
4078         u16 r; /* routing */
4079         u8 i, c;
4080
4081         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
4082                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
4083                 b43_read32(dev, B43_MMIO_MACCTL);
4084                 udelay(1);
4085         }
4086
4087         if (nphy->hang_avoid)
4088                 b43_nphy_stay_in_carrier_search(dev, true);
4089
4090         b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
4091         if (dev->phy.rev >= 3)
4092                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
4093                              ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
4094         else
4095                 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
4096                             B43_NPHY_TXPCTL_CMD_PCTLEN);
4097
4098         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
4099                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
4100
4101         if (sprom->revision < 4) {
4102                 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
4103                 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
4104                 target[0] = target[1] = 52;
4105                 a1[0] = a1[1] = -424;
4106                 b0[0] = b0[1] = 5612;
4107                 b1[0] = b1[1] = -1393;
4108         } else {
4109                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4110                         for (c = 0; c < 2; c++) {
4111                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
4112                                 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
4113                                 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
4114                                 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
4115                                 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
4116                         }
4117                 } else if (freq >= 4900 && freq < 5100) {
4118                         for (c = 0; c < 2; c++) {
4119                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
4120                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
4121                                 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
4122                                 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
4123                                 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
4124                         }
4125                 } else if (freq >= 5100 && freq < 5500) {
4126                         for (c = 0; c < 2; c++) {
4127                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
4128                                 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
4129                                 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
4130                                 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
4131                                 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
4132                         }
4133                 } else if (freq >= 5500) {
4134                         for (c = 0; c < 2; c++) {
4135                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
4136                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
4137                                 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
4138                                 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
4139                                 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
4140                         }
4141                 } else {
4142                         idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
4143                         idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
4144                         target[0] = target[1] = 52;
4145                         a1[0] = a1[1] = -424;
4146                         b0[0] = b0[1] = 5612;
4147                         b1[0] = b1[1] = -1393;
4148                 }
4149         }
4150         /* target[0] = target[1] = nphy->tx_power_max; */
4151
4152         if (dev->phy.rev >= 3) {
4153                 if (sprom->fem.ghz2.tssipos)
4154                         b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
4155                 if (dev->phy.rev >= 7) {
4156                         for (c = 0; c < 2; c++) {
4157                                 r = c ? 0x190 : 0x170;
4158                                 if (b43_nphy_ipa(dev))
4159                                         b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
4160                         }
4161                 } else {
4162                         if (b43_nphy_ipa(dev)) {
4163                                 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
4164                                 b43_radio_write(dev,
4165                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
4166                                 b43_radio_write(dev,
4167                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
4168                         } else {
4169                                 b43_radio_write(dev,
4170                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
4171                                 b43_radio_write(dev,
4172                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
4173                         }
4174                 }
4175         }
4176
4177         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
4178                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
4179                 b43_read32(dev, B43_MMIO_MACCTL);
4180                 udelay(1);
4181         }
4182
4183         if (phy->rev >= 19) {
4184                 /* TODO */
4185         } else if (phy->rev >= 7) {
4186                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
4187                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
4188                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
4189                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
4190         } else {
4191                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
4192                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
4193                 if (dev->phy.rev > 1)
4194                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
4195                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
4196         }
4197
4198         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
4199                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
4200
4201         b43_phy_write(dev, B43_NPHY_TXPCTL_N,
4202                       0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
4203                       3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
4204         b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
4205                       idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
4206                       idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
4207                       B43_NPHY_TXPCTL_ITSSI_BINF);
4208         b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
4209                       target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
4210                       target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
4211
4212         for (c = 0; c < 2; c++) {
4213                 for (i = 0; i < 64; i++) {
4214                         num = 8 * (16 * b0[c] + b1[c] * i);
4215                         den = 32768 + a1[c] * i;
4216                         pwr = max((4 * num + den / 2) / den, -8);
4217                         if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
4218                                 pwr = max(pwr, target[c] + 1);
4219                         regval[i] = pwr;
4220                 }
4221                 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
4222         }
4223
4224         b43_nphy_tx_prepare_adjusted_power_table(dev);
4225         b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
4226         b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
4227
4228         if (nphy->hang_avoid)
4229                 b43_nphy_stay_in_carrier_search(dev, false);
4230 }
4231
4232 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
4233 {
4234         struct b43_phy *phy = &dev->phy;
4235
4236         const u32 *table = NULL;
4237         u32 rfpwr_offset;
4238         u8 pga_gain;
4239         int i;
4240
4241         table = b43_nphy_get_tx_gain_table(dev);
4242         if (!table)
4243                 return;
4244
4245         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
4246         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
4247
4248         if (phy->rev < 3)
4249                 return;
4250
4251 #if 0
4252         nphy->gmval = (table[0] >> 16) & 0x7000;
4253 #endif
4254
4255         for (i = 0; i < 128; i++) {
4256                 if (phy->rev >= 19) {
4257                         /* TODO */
4258                         return;
4259                 } else if (phy->rev >= 7) {
4260                         /* TODO */
4261                         return;
4262                 } else {
4263                         pga_gain = (table[i] >> 24) & 0xF;
4264                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4265                                 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
4266                         else
4267                                 rfpwr_offset = 0; /* FIXME */
4268                 }
4269
4270                 b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset);
4271                 b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset);
4272         }
4273 }
4274
4275 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
4276 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
4277 {
4278         struct b43_phy_n *nphy = dev->phy.n;
4279         enum ieee80211_band band;
4280         u16 tmp;
4281
4282         if (!enable) {
4283                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
4284                                                        B43_NPHY_RFCTL_INTC1);
4285                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
4286                                                        B43_NPHY_RFCTL_INTC2);
4287                 band = b43_current_band(dev->wl);
4288                 if (dev->phy.rev >= 7) {
4289                         tmp = 0x1480;
4290                 } else if (dev->phy.rev >= 3) {
4291                         if (band == IEEE80211_BAND_5GHZ)
4292                                 tmp = 0x600;
4293                         else
4294                                 tmp = 0x480;
4295                 } else {
4296                         if (band == IEEE80211_BAND_5GHZ)
4297                                 tmp = 0x180;
4298                         else
4299                                 tmp = 0x120;
4300                 }
4301                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4302                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4303         } else {
4304                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
4305                                 nphy->rfctrl_intc1_save);
4306                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
4307                                 nphy->rfctrl_intc2_save);
4308         }
4309 }
4310
4311 /*
4312  * TX low-pass filter bandwidth setup
4313  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw
4314  */
4315 static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev)
4316 {
4317         u16 tmp;
4318
4319         if (dev->phy.rev < 3 || dev->phy.rev >= 7)
4320                 return;
4321
4322         if (b43_nphy_ipa(dev))
4323                 tmp = b43_is_40mhz(dev) ? 5 : 4;
4324         else
4325                 tmp = b43_is_40mhz(dev) ? 3 : 1;
4326         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
4327                       (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
4328
4329         if (b43_nphy_ipa(dev)) {
4330                 tmp = b43_is_40mhz(dev) ? 4 : 1;
4331                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
4332                               (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
4333         }
4334 }
4335
4336 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
4337 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
4338                                 u16 samps, u8 time, bool wait)
4339 {
4340         int i;
4341         u16 tmp;
4342
4343         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
4344         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
4345         if (wait)
4346                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
4347         else
4348                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
4349
4350         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
4351
4352         for (i = 1000; i; i--) {
4353                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
4354                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
4355                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
4356                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
4357                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
4358                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
4359                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
4360                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
4361
4362                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
4363                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
4364                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
4365                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
4366                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
4367                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
4368                         return;
4369                 }
4370                 udelay(10);
4371         }
4372         memset(est, 0, sizeof(*est));
4373 }
4374
4375 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
4376 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
4377                                         struct b43_phy_n_iq_comp *pcomp)
4378 {
4379         if (write) {
4380                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
4381                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
4382                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
4383                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
4384         } else {
4385                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
4386                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
4387                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
4388                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
4389         }
4390 }
4391
4392 #if 0
4393 /* Ready but not used anywhere */
4394 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
4395 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
4396 {
4397         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4398
4399         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
4400         if (core == 0) {
4401                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
4402                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4403         } else {
4404                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4405                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4406         }
4407         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
4408         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
4409         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
4410         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
4411         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
4412         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
4413         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4414         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4415 }
4416
4417 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
4418 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
4419 {
4420         u8 rxval, txval;
4421         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4422
4423         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4424         if (core == 0) {
4425                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4426                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4427         } else {
4428                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4429                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4430         }
4431         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4432         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4433         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
4434         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
4435         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
4436         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
4437         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4438         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4439
4440         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4441         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4442
4443         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4444                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4445                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4446         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4447                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
4448         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4449                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
4450         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
4451                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
4452
4453         if (core == 0) {
4454                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
4455                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
4456         } else {
4457                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
4458                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
4459         }
4460
4461         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
4462         b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
4463         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
4464
4465         if (core == 0) {
4466                 rxval = 1;
4467                 txval = 8;
4468         } else {
4469                 rxval = 4;
4470                 txval = 2;
4471         }
4472         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
4473                                       core + 1);
4474         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
4475                                       2 - core);
4476 }
4477 #endif
4478
4479 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
4480 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
4481 {
4482         int i;
4483         s32 iq;
4484         u32 ii;
4485         u32 qq;
4486         int iq_nbits, qq_nbits;
4487         int arsh, brsh;
4488         u16 tmp, a, b;
4489
4490         struct nphy_iq_est est;
4491         struct b43_phy_n_iq_comp old;
4492         struct b43_phy_n_iq_comp new = { };
4493         bool error = false;
4494
4495         if (mask == 0)
4496                 return;
4497
4498         b43_nphy_rx_iq_coeffs(dev, false, &old);
4499         b43_nphy_rx_iq_coeffs(dev, true, &new);
4500         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
4501         new = old;
4502
4503         for (i = 0; i < 2; i++) {
4504                 if (i == 0 && (mask & 1)) {
4505                         iq = est.iq0_prod;
4506                         ii = est.i0_pwr;
4507                         qq = est.q0_pwr;
4508                 } else if (i == 1 && (mask & 2)) {
4509                         iq = est.iq1_prod;
4510                         ii = est.i1_pwr;
4511                         qq = est.q1_pwr;
4512                 } else {
4513                         continue;
4514                 }
4515
4516                 if (ii + qq < 2) {
4517                         error = true;
4518                         break;
4519                 }
4520
4521                 iq_nbits = fls(abs(iq));
4522                 qq_nbits = fls(qq);
4523
4524                 arsh = iq_nbits - 20;
4525                 if (arsh >= 0) {
4526                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
4527                         tmp = ii >> arsh;
4528                 } else {
4529                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
4530                         tmp = ii << -arsh;
4531                 }
4532                 if (tmp == 0) {
4533                         error = true;
4534                         break;
4535                 }
4536                 a /= tmp;
4537
4538                 brsh = qq_nbits - 11;
4539                 if (brsh >= 0) {
4540                         b = (qq << (31 - qq_nbits));
4541                         tmp = ii >> brsh;
4542                 } else {
4543                         b = (qq << (31 - qq_nbits));
4544                         tmp = ii << -brsh;
4545                 }
4546                 if (tmp == 0) {
4547                         error = true;
4548                         break;
4549                 }
4550                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
4551
4552                 if (i == 0 && (mask & 0x1)) {
4553                         if (dev->phy.rev >= 3) {
4554                                 new.a0 = a & 0x3FF;
4555                                 new.b0 = b & 0x3FF;
4556                         } else {
4557                                 new.a0 = b & 0x3FF;
4558                                 new.b0 = a & 0x3FF;
4559                         }
4560                 } else if (i == 1 && (mask & 0x2)) {
4561                         if (dev->phy.rev >= 3) {
4562                                 new.a1 = a & 0x3FF;
4563                                 new.b1 = b & 0x3FF;
4564                         } else {
4565                                 new.a1 = b & 0x3FF;
4566                                 new.b1 = a & 0x3FF;
4567                         }
4568                 }
4569         }
4570
4571         if (error)
4572                 new = old;
4573
4574         b43_nphy_rx_iq_coeffs(dev, true, &new);
4575 }
4576
4577 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
4578 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
4579 {
4580         u16 array[4];
4581         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
4582
4583         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
4584         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
4585         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
4586         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
4587 }
4588
4589 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
4590 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
4591 {
4592         struct b43_phy_n *nphy = dev->phy.n;
4593
4594         u8 channel = dev->phy.channel;
4595         int tone[2] = { 57, 58 };
4596         u32 noise[2] = { 0x3FF, 0x3FF };
4597
4598         B43_WARN_ON(dev->phy.rev < 3);
4599
4600         if (nphy->hang_avoid)
4601                 b43_nphy_stay_in_carrier_search(dev, 1);
4602
4603         if (nphy->gband_spurwar_en) {
4604                 /* TODO: N PHY Adjust Analog Pfbw (7) */
4605                 if (channel == 11 && b43_is_40mhz(dev))
4606                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
4607                 else
4608                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4609                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
4610         }
4611
4612         if (nphy->aband_spurwar_en) {
4613                 if (channel == 54) {
4614                         tone[0] = 0x20;
4615                         noise[0] = 0x25F;
4616                 } else if (channel == 38 || channel == 102 || channel == 118) {
4617                         if (0 /* FIXME */) {
4618                                 tone[0] = 0x20;
4619                                 noise[0] = 0x21F;
4620                         } else {
4621                                 tone[0] = 0;
4622                                 noise[0] = 0;
4623                         }
4624                 } else if (channel == 134) {
4625                         tone[0] = 0x20;
4626                         noise[0] = 0x21F;
4627                 } else if (channel == 151) {
4628                         tone[0] = 0x10;
4629                         noise[0] = 0x23F;
4630                 } else if (channel == 153 || channel == 161) {
4631                         tone[0] = 0x30;
4632                         noise[0] = 0x23F;
4633                 } else {
4634                         tone[0] = 0;
4635                         noise[0] = 0;
4636                 }
4637
4638                 if (!tone[0] && !noise[0])
4639                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
4640                 else
4641                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4642         }
4643
4644         if (nphy->hang_avoid)
4645                 b43_nphy_stay_in_carrier_search(dev, 0);
4646 }
4647
4648 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4649 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4650 {
4651         struct b43_phy_n *nphy = dev->phy.n;
4652         int i, j;
4653         u32 tmp;
4654         u32 cur_real, cur_imag, real_part, imag_part;
4655
4656         u16 buffer[7];
4657
4658         if (nphy->hang_avoid)
4659                 b43_nphy_stay_in_carrier_search(dev, true);
4660
4661         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4662
4663         for (i = 0; i < 2; i++) {
4664                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4665                         (buffer[i * 2 + 1] & 0x3FF);
4666                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4667                                 (((i + 26) << 10) | 320));
4668                 for (j = 0; j < 128; j++) {
4669                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4670                                         ((tmp >> 16) & 0xFFFF));
4671                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4672                                         (tmp & 0xFFFF));
4673                 }
4674         }
4675
4676         for (i = 0; i < 2; i++) {
4677                 tmp = buffer[5 + i];
4678                 real_part = (tmp >> 8) & 0xFF;
4679                 imag_part = (tmp & 0xFF);
4680                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4681                                 (((i + 26) << 10) | 448));
4682
4683                 if (dev->phy.rev >= 3) {
4684                         cur_real = real_part;
4685                         cur_imag = imag_part;
4686                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4687                 }
4688
4689                 for (j = 0; j < 128; j++) {
4690                         if (dev->phy.rev < 3) {
4691                                 cur_real = (real_part * loscale[j] + 128) >> 8;
4692                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4693                                 tmp = ((cur_real & 0xFF) << 8) |
4694                                         (cur_imag & 0xFF);
4695                         }
4696                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4697                                         ((tmp >> 16) & 0xFFFF));
4698                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4699                                         (tmp & 0xFFFF));
4700                 }
4701         }
4702
4703         if (dev->phy.rev >= 3) {
4704                 b43_shm_write16(dev, B43_SHM_SHARED,
4705                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4706                 b43_shm_write16(dev, B43_SHM_SHARED,
4707                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4708         }
4709
4710         if (nphy->hang_avoid)
4711                 b43_nphy_stay_in_carrier_search(dev, false);
4712 }
4713
4714 /*
4715  * Restore RSSI Calibration
4716  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4717  */
4718 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4719 {
4720         struct b43_phy_n *nphy = dev->phy.n;
4721
4722         u16 *rssical_radio_regs = NULL;
4723         u16 *rssical_phy_regs = NULL;
4724
4725         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4726                 if (!nphy->rssical_chanspec_2G.center_freq)
4727                         return;
4728                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4729                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4730         } else {
4731                 if (!nphy->rssical_chanspec_5G.center_freq)
4732                         return;
4733                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4734                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4735         }
4736
4737         if (dev->phy.rev >= 19) {
4738                 /* TODO */
4739         } else if (dev->phy.rev >= 7) {
4740                 b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK,
4741                                   rssical_radio_regs[0]);
4742                 b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK,
4743                                   rssical_radio_regs[1]);
4744         } else {
4745                 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4746                                   rssical_radio_regs[0]);
4747                 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4748                                   rssical_radio_regs[1]);
4749         }
4750
4751         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4752         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4753         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4754         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4755
4756         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4757         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4758         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4759         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4760
4761         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4762         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4763         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4764         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4765 }
4766
4767 static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev)
4768 {
4769         /* TODO */
4770 }
4771
4772 static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev)
4773 {
4774         struct b43_phy *phy = &dev->phy;
4775         struct b43_phy_n *nphy = dev->phy.n;
4776         u16 *save = nphy->tx_rx_cal_radio_saveregs;
4777         int core, off;
4778         u16 r, tmp;
4779
4780         for (core = 0; core < 2; core++) {
4781                 r = core ? 0x20 : 0;
4782                 off = core * 11;
4783
4784                 save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER);
4785                 save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG);
4786                 save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC);
4787                 save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM);
4788                 save[off + 4] = 0;
4789                 save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX);
4790                 if (phy->radio_rev != 5)
4791                         save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA);
4792                 save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG);
4793                 save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1);
4794
4795                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4796                         b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA);
4797                         b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4798                         b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55);
4799                         b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0);
4800                         b43_radio_write(dev, r + R2057_TX0_TSSIG, 0);
4801                         if (nphy->use_int_tx_iq_lo_cal) {
4802                                 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4);
4803                                 tmp = true ? 0x31 : 0x21; /* TODO */
4804                                 b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp);
4805                         }
4806                         b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00);
4807                 } else {
4808                         b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6);
4809                         b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4810                         b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55);
4811                         b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0);
4812
4813                         if (phy->radio_rev != 5)
4814                                 b43_radio_write(dev, r + R2057_TX0_TSSIA, 0);
4815                         if (nphy->use_int_tx_iq_lo_cal) {
4816                                 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6);
4817                                 tmp = true ? 0x31 : 0x21; /* TODO */
4818                                 b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp);
4819                         }
4820                         b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0);
4821                 }
4822         }
4823 }
4824
4825 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4826 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4827 {
4828         struct b43_phy *phy = &dev->phy;
4829         struct b43_phy_n *nphy = dev->phy.n;
4830         u16 *save = nphy->tx_rx_cal_radio_saveregs;
4831         u16 tmp;
4832         u8 offset, i;
4833
4834         if (phy->rev >= 19) {
4835                 b43_nphy_tx_cal_radio_setup_rev19(dev);
4836         } else if (phy->rev >= 7) {
4837                 b43_nphy_tx_cal_radio_setup_rev7(dev);
4838         } else if (phy->rev >= 3) {
4839             for (i = 0; i < 2; i++) {
4840                 tmp = (i == 0) ? 0x2000 : 0x3000;
4841                 offset = i * 11;
4842
4843                 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4844                 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4845                 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4846                 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4847                 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4848                 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4849                 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4850                 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4851                 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4852                 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4853                 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
4854
4855                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4856                         b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4857                         b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4858                         b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4859                         b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4860                         b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4861                         if (nphy->ipa5g_on) {
4862                                 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4863                                 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
4864                         } else {
4865                                 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4866                                 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
4867                         }
4868                         b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4869                 } else {
4870                         b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4871                         b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4872                         b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4873                         b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4874                         b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4875                         b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
4876                         if (nphy->ipa2g_on) {
4877                                 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4878                                 b43_radio_write(dev, tmp | B2055_XOCTL2,
4879                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
4880                         } else {
4881                                 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4882                                 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4883                         }
4884                 }
4885                 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4886                 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4887                 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
4888             }
4889         } else {
4890                 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4891                 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
4892
4893                 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4894                 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
4895
4896                 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4897                 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
4898
4899                 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4900                 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
4901
4902                 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4903                 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
4904
4905                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4906                     B43_NPHY_BANDCTL_5GHZ)) {
4907                         b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4908                         b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
4909                 } else {
4910                         b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4911                         b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
4912                 }
4913
4914                 if (dev->phy.rev < 2) {
4915                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4916                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4917                 } else {
4918                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4919                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4920                 }
4921         }
4922 }
4923
4924 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4925 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4926 {
4927         struct b43_phy_n *nphy = dev->phy.n;
4928         int i;
4929         u16 scale, entry;
4930
4931         u16 tmp = nphy->txcal_bbmult;
4932         if (core == 0)
4933                 tmp >>= 8;
4934         tmp &= 0xff;
4935
4936         for (i = 0; i < 18; i++) {
4937                 scale = (ladder_lo[i].percent * tmp) / 100;
4938                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
4939                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
4940
4941                 scale = (ladder_iq[i].percent * tmp) / 100;
4942                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
4943                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
4944         }
4945 }
4946
4947 static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset,
4948                                           const s16 *filter)
4949 {
4950         int i;
4951
4952         offset = B43_PHY_N(offset);
4953
4954         for (i = 0; i < 15; i++, offset++)
4955                 b43_phy_write(dev, offset, filter[i]);
4956 }
4957
4958 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4959 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4960 {
4961         b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5,
4962                                       tbl_tx_filter_coef_rev4[2]);
4963 }
4964
4965 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4966 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4967 {
4968         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
4969         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4970         static const s16 dig_filter_phy_rev16[] = {
4971                 -375, 136, -407, 208, -1527,
4972                 956, 93, 186, 93, 230,
4973                 -44, 230, 201, -191, 201,
4974         };
4975         int i;
4976
4977         for (i = 0; i < 3; i++)
4978                 b43_nphy_pa_set_tx_dig_filter(dev, offset[i],
4979                                               tbl_tx_filter_coef_rev4[i]);
4980
4981         /* Verified with BCM43227 and BCM43228 */
4982         if (dev->phy.rev == 16)
4983                 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16);
4984
4985         /* Verified with BCM43131 and BCM43217 */
4986         if (dev->phy.rev == 17) {
4987                 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16);
4988                 b43_nphy_pa_set_tx_dig_filter(dev, 0x195,
4989                                               tbl_tx_filter_coef_rev4[1]);
4990         }
4991
4992         if (b43_is_40mhz(dev)) {
4993                 b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
4994                                               tbl_tx_filter_coef_rev4[3]);
4995         } else {
4996                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4997                         b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
4998                                                       tbl_tx_filter_coef_rev4[5]);
4999                 if (dev->phy.channel == 14)
5000                         b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
5001                                                       tbl_tx_filter_coef_rev4[6]);
5002         }
5003 }
5004
5005 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
5006 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
5007 {
5008         struct b43_phy_n *nphy = dev->phy.n;
5009
5010         u16 curr_gain[2];
5011         struct nphy_txgains target;
5012         const u32 *table = NULL;
5013
5014         if (!nphy->txpwrctrl) {
5015                 int i;
5016
5017                 if (nphy->hang_avoid)
5018                         b43_nphy_stay_in_carrier_search(dev, true);
5019                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
5020                 if (nphy->hang_avoid)
5021                         b43_nphy_stay_in_carrier_search(dev, false);
5022
5023                 for (i = 0; i < 2; ++i) {
5024                         if (dev->phy.rev >= 7) {
5025                                 target.ipa[i] = curr_gain[i] & 0x0007;
5026                                 target.pad[i] = (curr_gain[i] & 0x00F8) >> 3;
5027                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
5028                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
5029                                 target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15;
5030                         } else if (dev->phy.rev >= 3) {
5031                                 target.ipa[i] = curr_gain[i] & 0x000F;
5032                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
5033                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
5034                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
5035                         } else {
5036                                 target.ipa[i] = curr_gain[i] & 0x0003;
5037                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
5038                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
5039                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
5040                         }
5041                 }
5042         } else {
5043                 int i;
5044                 u16 index[2];
5045                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
5046                         B43_NPHY_TXPCTL_STAT_BIDX) >>
5047                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
5048                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
5049                         B43_NPHY_TXPCTL_STAT_BIDX) >>
5050                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
5051
5052                 for (i = 0; i < 2; ++i) {
5053                         table = b43_nphy_get_tx_gain_table(dev);
5054                         if (!table)
5055                                 break;
5056
5057                         if (dev->phy.rev >= 7) {
5058                                 target.ipa[i] = (table[index[i]] >> 16) & 0x7;
5059                                 target.pad[i] = (table[index[i]] >> 19) & 0x1F;
5060                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
5061                                 target.txgm[i] = (table[index[i]] >> 28) & 0x7;
5062                                 target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1;
5063                         } else if (dev->phy.rev >= 3) {
5064                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
5065                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
5066                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
5067                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
5068                         } else {
5069                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
5070                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
5071                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
5072                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
5073                         }
5074                 }
5075         }
5076
5077         return target;
5078 }
5079
5080 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
5081 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
5082 {
5083         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
5084
5085         if (dev->phy.rev >= 3) {
5086                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
5087                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
5088                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
5089                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
5090                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
5091                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
5092                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
5093                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
5094                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
5095                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
5096                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
5097                 b43_nphy_reset_cca(dev);
5098         } else {
5099                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
5100                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
5101                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
5102                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
5103                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
5104                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
5105                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
5106         }
5107 }
5108
5109 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
5110 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
5111 {
5112         struct b43_phy *phy = &dev->phy;
5113         struct b43_phy_n *nphy = dev->phy.n;
5114         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
5115         u16 tmp;
5116
5117         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
5118         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
5119         if (dev->phy.rev >= 3) {
5120                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
5121                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
5122
5123                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
5124                 regs[2] = tmp;
5125                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
5126
5127                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5128                 regs[3] = tmp;
5129                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
5130
5131                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
5132                 b43_phy_mask(dev, B43_NPHY_BBCFG,
5133                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5134
5135                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
5136                 regs[5] = tmp;
5137                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
5138
5139                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
5140                 regs[6] = tmp;
5141                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
5142                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
5143                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
5144
5145                 if (!nphy->use_int_tx_iq_lo_cal)
5146                         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA,
5147                                                       1, 3);
5148                 else
5149                         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA,
5150                                                       0, 3);
5151                 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
5152                 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
5153
5154                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
5155                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
5156                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
5157                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
5158
5159                 tmp = b43_nphy_read_lpf_ctl(dev, 0);
5160                 if (phy->rev >= 19)
5161                         b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false,
5162                                                        1);
5163                 else if (phy->rev >= 7)
5164                         b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false,
5165                                                       1);
5166
5167                 if (nphy->use_int_tx_iq_lo_cal && true /* FIXME */) {
5168                         if (phy->rev >= 19) {
5169                                 b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3,
5170                                                                false, 0);
5171                         } else if (phy->rev >= 8) {
5172                                 b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3,
5173                                                               false, 0);
5174                         } else if (phy->rev == 7) {
5175                                 b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4);
5176                                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5177                                         b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0);
5178                                         b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0);
5179                                 } else {
5180                                         b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0);
5181                                         b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0);
5182                                 }
5183                         }
5184                 }
5185         } else {
5186                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
5187                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
5188                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5189                 regs[2] = tmp;
5190                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
5191                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
5192                 regs[3] = tmp;
5193                 tmp |= 0x2000;
5194                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
5195                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
5196                 regs[4] = tmp;
5197                 tmp |= 0x2000;
5198                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
5199                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
5200                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
5201                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
5202                         tmp = 0x0180;
5203                 else
5204                         tmp = 0x0120;
5205                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
5206                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
5207         }
5208 }
5209
5210 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
5211 static void b43_nphy_save_cal(struct b43_wldev *dev)
5212 {
5213         struct b43_phy *phy = &dev->phy;
5214         struct b43_phy_n *nphy = dev->phy.n;
5215
5216         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
5217         u16 *txcal_radio_regs = NULL;
5218         struct b43_chanspec *iqcal_chanspec;
5219         u16 *table = NULL;
5220
5221         if (nphy->hang_avoid)
5222                 b43_nphy_stay_in_carrier_search(dev, 1);
5223
5224         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5225                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
5226                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
5227                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
5228                 table = nphy->cal_cache.txcal_coeffs_2G;
5229         } else {
5230                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
5231                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
5232                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
5233                 table = nphy->cal_cache.txcal_coeffs_5G;
5234         }
5235
5236         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
5237         /* TODO use some definitions */
5238         if (phy->rev >= 19) {
5239                 /* TODO */
5240         } else if (phy->rev >= 7) {
5241                 txcal_radio_regs[0] = b43_radio_read(dev,
5242                                                      R2057_TX0_LOFT_FINE_I);
5243                 txcal_radio_regs[1] = b43_radio_read(dev,
5244                                                      R2057_TX0_LOFT_FINE_Q);
5245                 txcal_radio_regs[4] = b43_radio_read(dev,
5246                                                      R2057_TX0_LOFT_COARSE_I);
5247                 txcal_radio_regs[5] = b43_radio_read(dev,
5248                                                      R2057_TX0_LOFT_COARSE_Q);
5249                 txcal_radio_regs[2] = b43_radio_read(dev,
5250                                                      R2057_TX1_LOFT_FINE_I);
5251                 txcal_radio_regs[3] = b43_radio_read(dev,
5252                                                      R2057_TX1_LOFT_FINE_Q);
5253                 txcal_radio_regs[6] = b43_radio_read(dev,
5254                                                      R2057_TX1_LOFT_COARSE_I);
5255                 txcal_radio_regs[7] = b43_radio_read(dev,
5256                                                      R2057_TX1_LOFT_COARSE_Q);
5257         } else if (phy->rev >= 3) {
5258                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
5259                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
5260                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
5261                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
5262                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
5263                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
5264                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
5265                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
5266         } else {
5267                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
5268                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
5269                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
5270                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
5271         }
5272         iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq;
5273         iqcal_chanspec->channel_type =
5274                                 cfg80211_get_chandef_type(dev->phy.chandef);
5275         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
5276
5277         if (nphy->hang_avoid)
5278                 b43_nphy_stay_in_carrier_search(dev, 0);
5279 }
5280
5281 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
5282 static void b43_nphy_restore_cal(struct b43_wldev *dev)
5283 {
5284         struct b43_phy *phy = &dev->phy;
5285         struct b43_phy_n *nphy = dev->phy.n;
5286
5287         u16 coef[4];
5288         u16 *loft = NULL;
5289         u16 *table = NULL;
5290
5291         int i;
5292         u16 *txcal_radio_regs = NULL;
5293         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
5294
5295         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5296                 if (!nphy->iqcal_chanspec_2G.center_freq)
5297                         return;
5298                 table = nphy->cal_cache.txcal_coeffs_2G;
5299                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
5300         } else {
5301                 if (!nphy->iqcal_chanspec_5G.center_freq)
5302                         return;
5303                 table = nphy->cal_cache.txcal_coeffs_5G;
5304                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
5305         }
5306
5307         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
5308
5309         for (i = 0; i < 4; i++) {
5310                 if (dev->phy.rev >= 3)
5311                         table[i] = coef[i];
5312                 else
5313                         coef[i] = 0;
5314         }
5315
5316         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
5317         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
5318         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
5319
5320         if (dev->phy.rev < 2)
5321                 b43_nphy_tx_iq_workaround(dev);
5322
5323         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5324                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
5325                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
5326         } else {
5327                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
5328                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
5329         }
5330
5331         /* TODO use some definitions */
5332         if (phy->rev >= 19) {
5333                 /* TODO */
5334         } else if (phy->rev >= 7) {
5335                 b43_radio_write(dev, R2057_TX0_LOFT_FINE_I,
5336                                 txcal_radio_regs[0]);
5337                 b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q,
5338                                 txcal_radio_regs[1]);
5339                 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I,
5340                                 txcal_radio_regs[4]);
5341                 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q,
5342                                 txcal_radio_regs[5]);
5343                 b43_radio_write(dev, R2057_TX1_LOFT_FINE_I,
5344                                 txcal_radio_regs[2]);
5345                 b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q,
5346                                 txcal_radio_regs[3]);
5347                 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I,
5348                                 txcal_radio_regs[6]);
5349                 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q,
5350                                 txcal_radio_regs[7]);
5351         } else if (phy->rev >= 3) {
5352                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
5353                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
5354                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
5355                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
5356                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
5357                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
5358                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
5359                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
5360         } else {
5361                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
5362                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
5363                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
5364                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
5365         }
5366         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
5367 }
5368
5369 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
5370 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
5371                                 struct nphy_txgains target,
5372                                 bool full, bool mphase)
5373 {
5374         struct b43_phy *phy = &dev->phy;
5375         struct b43_phy_n *nphy = dev->phy.n;
5376         int i;
5377         int error = 0;
5378         int freq;
5379         bool avoid = false;
5380         u8 length;
5381         u16 tmp, core, type, count, max, numb, last = 0, cmd;
5382         const u16 *table;
5383         bool phy6or5x;
5384
5385         u16 buffer[11];
5386         u16 diq_start = 0;
5387         u16 save[2];
5388         u16 gain[2];
5389         struct nphy_iqcal_params params[2];
5390         bool updated[2] = { };
5391
5392         b43_nphy_stay_in_carrier_search(dev, true);
5393
5394         if (dev->phy.rev >= 4) {
5395                 avoid = nphy->hang_avoid;
5396                 nphy->hang_avoid = false;
5397         }
5398
5399         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
5400
5401         for (i = 0; i < 2; i++) {
5402                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
5403                 gain[i] = params[i].cal_gain;
5404         }
5405
5406         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
5407
5408         b43_nphy_tx_cal_radio_setup(dev);
5409         b43_nphy_tx_cal_phy_setup(dev);
5410
5411         phy6or5x = dev->phy.rev >= 6 ||
5412                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
5413                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
5414         if (phy6or5x) {
5415                 if (b43_is_40mhz(dev)) {
5416                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
5417                                         tbl_tx_iqlo_cal_loft_ladder_40);
5418                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
5419                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
5420                 } else {
5421                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
5422                                         tbl_tx_iqlo_cal_loft_ladder_20);
5423                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
5424                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
5425                 }
5426         }
5427
5428         if (phy->rev >= 19) {
5429                 /* TODO */
5430         } else if (phy->rev >= 7) {
5431                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9);
5432         } else {
5433                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
5434         }
5435
5436         if (!b43_is_40mhz(dev))
5437                 freq = 2500;
5438         else
5439                 freq = 5000;
5440
5441         if (nphy->mphase_cal_phase_id > 2)
5442                 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8,
5443                                      0xFFFF, 0, true, false, false);
5444         else
5445                 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false);
5446
5447         if (error == 0) {
5448                 if (nphy->mphase_cal_phase_id > 2) {
5449                         table = nphy->mphase_txcal_bestcoeffs;
5450                         length = 11;
5451                         if (dev->phy.rev < 3)
5452                                 length -= 2;
5453                 } else {
5454                         if (!full && nphy->txiqlocal_coeffsvalid) {
5455                                 table = nphy->txiqlocal_bestc;
5456                                 length = 11;
5457                                 if (dev->phy.rev < 3)
5458                                         length -= 2;
5459                         } else {
5460                                 full = true;
5461                                 if (dev->phy.rev >= 3) {
5462                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
5463                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
5464                                 } else {
5465                                         table = tbl_tx_iqlo_cal_startcoefs;
5466                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
5467                                 }
5468                         }
5469                 }
5470
5471                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
5472
5473                 if (full) {
5474                         if (dev->phy.rev >= 3)
5475                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
5476                         else
5477                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
5478                 } else {
5479                         if (dev->phy.rev >= 3)
5480                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
5481                         else
5482                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
5483                 }
5484
5485                 if (mphase) {
5486                         count = nphy->mphase_txcal_cmdidx;
5487                         numb = min(max,
5488                                 (u16)(count + nphy->mphase_txcal_numcmds));
5489                 } else {
5490                         count = 0;
5491                         numb = max;
5492                 }
5493
5494                 for (; count < numb; count++) {
5495                         if (full) {
5496                                 if (dev->phy.rev >= 3)
5497                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
5498                                 else
5499                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
5500                         } else {
5501                                 if (dev->phy.rev >= 3)
5502                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
5503                                 else
5504                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
5505                         }
5506
5507                         core = (cmd & 0x3000) >> 12;
5508                         type = (cmd & 0x0F00) >> 8;
5509
5510                         if (phy6or5x && updated[core] == 0) {
5511                                 b43_nphy_update_tx_cal_ladder(dev, core);
5512                                 updated[core] = true;
5513                         }
5514
5515                         tmp = (params[core].ncorr[type] << 8) | 0x66;
5516                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
5517
5518                         if (type == 1 || type == 3 || type == 4) {
5519                                 buffer[0] = b43_ntab_read(dev,
5520                                                 B43_NTAB16(15, 69 + core));
5521                                 diq_start = buffer[0];
5522                                 buffer[0] = 0;
5523                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
5524                                                 0);
5525                         }
5526
5527                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
5528                         for (i = 0; i < 2000; i++) {
5529                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
5530                                 if (tmp & 0xC000)
5531                                         break;
5532                                 udelay(10);
5533                         }
5534
5535                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5536                                                 buffer);
5537                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
5538                                                 buffer);
5539
5540                         if (type == 1 || type == 3 || type == 4)
5541                                 buffer[0] = diq_start;
5542                 }
5543
5544                 if (mphase)
5545                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
5546
5547                 last = (dev->phy.rev < 3) ? 6 : 7;
5548
5549                 if (!mphase || nphy->mphase_cal_phase_id == last) {
5550                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
5551                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
5552                         if (dev->phy.rev < 3) {
5553                                 buffer[0] = 0;
5554                                 buffer[1] = 0;
5555                                 buffer[2] = 0;
5556                                 buffer[3] = 0;
5557                         }
5558                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
5559                                                 buffer);
5560                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
5561                                                 buffer);
5562                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
5563                                                 buffer);
5564                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
5565                                                 buffer);
5566                         length = 11;
5567                         if (dev->phy.rev < 3)
5568                                 length -= 2;
5569                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5570                                                 nphy->txiqlocal_bestc);
5571                         nphy->txiqlocal_coeffsvalid = true;
5572                         nphy->txiqlocal_chanspec.center_freq =
5573                                                 phy->chandef->chan->center_freq;
5574                         nphy->txiqlocal_chanspec.channel_type =
5575                                         cfg80211_get_chandef_type(phy->chandef);
5576                 } else {
5577                         length = 11;
5578                         if (dev->phy.rev < 3)
5579                                 length -= 2;
5580                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5581                                                 nphy->mphase_txcal_bestcoeffs);
5582                 }
5583
5584                 b43_nphy_stop_playback(dev);
5585                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
5586         }
5587
5588         b43_nphy_tx_cal_phy_cleanup(dev);
5589         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
5590
5591         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
5592                 b43_nphy_tx_iq_workaround(dev);
5593
5594         if (dev->phy.rev >= 4)
5595                 nphy->hang_avoid = avoid;
5596
5597         b43_nphy_stay_in_carrier_search(dev, false);
5598
5599         return error;
5600 }
5601
5602 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
5603 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
5604 {
5605         struct b43_phy_n *nphy = dev->phy.n;
5606         u8 i;
5607         u16 buffer[7];
5608         bool equal = true;
5609
5610         if (!nphy->txiqlocal_coeffsvalid ||
5611             nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq ||
5612             nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef))
5613                 return;
5614
5615         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
5616         for (i = 0; i < 4; i++) {
5617                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
5618                         equal = false;
5619                         break;
5620                 }
5621         }
5622
5623         if (!equal) {
5624                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
5625                                         nphy->txiqlocal_bestc);
5626                 for (i = 0; i < 4; i++)
5627                         buffer[i] = 0;
5628                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
5629                                         buffer);
5630                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
5631                                         &nphy->txiqlocal_bestc[5]);
5632                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
5633                                         &nphy->txiqlocal_bestc[5]);
5634         }
5635 }
5636
5637 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
5638 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
5639                         struct nphy_txgains target, u8 type, bool debug)
5640 {
5641         struct b43_phy_n *nphy = dev->phy.n;
5642         int i, j, index;
5643         u8 rfctl[2];
5644         u8 afectl_core;
5645         u16 tmp[6];
5646         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
5647         u32 real, imag;
5648         enum ieee80211_band band;
5649
5650         u8 use;
5651         u16 cur_hpf;
5652         u16 lna[3] = { 3, 3, 1 };
5653         u16 hpf1[3] = { 7, 2, 0 };
5654         u16 hpf2[3] = { 2, 0, 0 };
5655         u32 power[3] = { };
5656         u16 gain_save[2];
5657         u16 cal_gain[2];
5658         struct nphy_iqcal_params cal_params[2];
5659         struct nphy_iq_est est;
5660         int ret = 0;
5661         bool playtone = true;
5662         int desired = 13;
5663
5664         b43_nphy_stay_in_carrier_search(dev, 1);
5665
5666         if (dev->phy.rev < 2)
5667                 b43_nphy_reapply_tx_cal_coeffs(dev);
5668         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
5669         for (i = 0; i < 2; i++) {
5670                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
5671                 cal_gain[i] = cal_params[i].cal_gain;
5672         }
5673         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
5674
5675         for (i = 0; i < 2; i++) {
5676                 if (i == 0) {
5677                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
5678                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
5679                         afectl_core = B43_NPHY_AFECTL_C1;
5680                 } else {
5681                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
5682                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
5683                         afectl_core = B43_NPHY_AFECTL_C2;
5684                 }
5685
5686                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
5687                 tmp[2] = b43_phy_read(dev, afectl_core);
5688                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5689                 tmp[4] = b43_phy_read(dev, rfctl[0]);
5690                 tmp[5] = b43_phy_read(dev, rfctl[1]);
5691
5692                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
5693                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
5694                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
5695                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
5696                                 (1 - i));
5697                 b43_phy_set(dev, afectl_core, 0x0006);
5698                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
5699
5700                 band = b43_current_band(dev->wl);
5701
5702                 if (nphy->rxcalparams & 0xFF000000) {
5703                         if (band == IEEE80211_BAND_5GHZ)
5704                                 b43_phy_write(dev, rfctl[0], 0x140);
5705                         else
5706                                 b43_phy_write(dev, rfctl[0], 0x110);
5707                 } else {
5708                         if (band == IEEE80211_BAND_5GHZ)
5709                                 b43_phy_write(dev, rfctl[0], 0x180);
5710                         else
5711                                 b43_phy_write(dev, rfctl[0], 0x120);
5712                 }
5713
5714                 if (band == IEEE80211_BAND_5GHZ)
5715                         b43_phy_write(dev, rfctl[1], 0x148);
5716                 else
5717                         b43_phy_write(dev, rfctl[1], 0x114);
5718
5719                 if (nphy->rxcalparams & 0x10000) {
5720                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
5721                                         (i + 1));
5722                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
5723                                         (2 - i));
5724                 }
5725
5726                 for (j = 0; j < 4; j++) {
5727                         if (j < 3) {
5728                                 cur_lna = lna[j];
5729                                 cur_hpf1 = hpf1[j];
5730                                 cur_hpf2 = hpf2[j];
5731                         } else {
5732                                 if (power[1] > 10000) {
5733                                         use = 1;
5734                                         cur_hpf = cur_hpf1;
5735                                         index = 2;
5736                                 } else {
5737                                         if (power[0] > 10000) {
5738                                                 use = 1;
5739                                                 cur_hpf = cur_hpf1;
5740                                                 index = 1;
5741                                         } else {
5742                                                 index = 0;
5743                                                 use = 2;
5744                                                 cur_hpf = cur_hpf2;
5745                                         }
5746                                 }
5747                                 cur_lna = lna[index];
5748                                 cur_hpf1 = hpf1[index];
5749                                 cur_hpf2 = hpf2[index];
5750                                 cur_hpf += desired - hweight32(power[index]);
5751                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
5752                                 if (use == 1)
5753                                         cur_hpf1 = cur_hpf;
5754                                 else
5755                                         cur_hpf2 = cur_hpf;
5756                         }
5757
5758                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
5759                                         (cur_lna << 2));
5760                         b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
5761                                                                         false);
5762                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5763                         b43_nphy_stop_playback(dev);
5764
5765                         if (playtone) {
5766                                 ret = b43_nphy_tx_tone(dev, 4000,
5767                                                 (nphy->rxcalparams & 0xFFFF),
5768                                                 false, false, true);
5769                                 playtone = false;
5770                         } else {
5771                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false,
5772                                                      false, true);
5773                         }
5774
5775                         if (ret == 0) {
5776                                 if (j < 3) {
5777                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
5778                                                                         false);
5779                                         if (i == 0) {
5780                                                 real = est.i0_pwr;
5781                                                 imag = est.q0_pwr;
5782                                         } else {
5783                                                 real = est.i1_pwr;
5784                                                 imag = est.q1_pwr;
5785                                         }
5786                                         power[i] = ((real + imag) / 1024) + 1;
5787                                 } else {
5788                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
5789                                 }
5790                                 b43_nphy_stop_playback(dev);
5791                         }
5792
5793                         if (ret != 0)
5794                                 break;
5795                 }
5796
5797                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5798                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5799                 b43_phy_write(dev, rfctl[1], tmp[5]);
5800                 b43_phy_write(dev, rfctl[0], tmp[4]);
5801                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5802                 b43_phy_write(dev, afectl_core, tmp[2]);
5803                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5804
5805                 if (ret != 0)
5806                         break;
5807         }
5808
5809         b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
5810         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5811         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
5812
5813         b43_nphy_stay_in_carrier_search(dev, 0);
5814
5815         return ret;
5816 }
5817
5818 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5819                         struct nphy_txgains target, u8 type, bool debug)
5820 {
5821         return -1;
5822 }
5823
5824 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5825 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5826                         struct nphy_txgains target, u8 type, bool debug)
5827 {
5828         if (dev->phy.rev >= 7)
5829                 type = 0;
5830
5831         if (dev->phy.rev >= 3)
5832                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5833         else
5834                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5835 }
5836
5837 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5838 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5839 {
5840         struct b43_phy *phy = &dev->phy;
5841         struct b43_phy_n *nphy = phy->n;
5842         /* u16 buf[16]; it's rev3+ */
5843
5844         nphy->phyrxchain = mask;
5845
5846         if (0 /* FIXME clk */)
5847                 return;
5848
5849         b43_mac_suspend(dev);
5850
5851         if (nphy->hang_avoid)
5852                 b43_nphy_stay_in_carrier_search(dev, true);
5853
5854         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5855                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5856
5857         if ((mask & 0x3) != 0x3) {
5858                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5859                 if (dev->phy.rev >= 3) {
5860                         /* TODO */
5861                 }
5862         } else {
5863                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5864                 if (dev->phy.rev >= 3) {
5865                         /* TODO */
5866                 }
5867         }
5868
5869         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5870
5871         if (nphy->hang_avoid)
5872                 b43_nphy_stay_in_carrier_search(dev, false);
5873
5874         b43_mac_enable(dev);
5875 }
5876
5877 /**************************************************
5878  * N-PHY init
5879  **************************************************/
5880
5881 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5882 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5883 {
5884         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5885
5886         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5887         if (preamble == 1)
5888                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5889         else
5890                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5891
5892         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5893 }
5894
5895 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5896 static void b43_nphy_bphy_init(struct b43_wldev *dev)
5897 {
5898         unsigned int i;
5899         u16 val;
5900
5901         val = 0x1E1F;
5902         for (i = 0; i < 16; i++) {
5903                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5904                 val -= 0x202;
5905         }
5906         val = 0x3E3F;
5907         for (i = 0; i < 16; i++) {
5908                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5909                 val -= 0x202;
5910         }
5911         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5912 }
5913
5914 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5915 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5916 {
5917         if (dev->phy.rev >= 7)
5918                 return;
5919
5920         if (dev->phy.rev >= 3) {
5921                 if (!init)
5922                         return;
5923                 if (0 /* FIXME */) {
5924                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5925                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5926                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5927                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5928                 }
5929         } else {
5930                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5931                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5932
5933                 switch (dev->dev->bus_type) {
5934 #ifdef CONFIG_B43_BCMA
5935                 case B43_BUS_BCMA:
5936                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5937                                                  0xFC00, 0xFC00);
5938                         break;
5939 #endif
5940 #ifdef CONFIG_B43_SSB
5941                 case B43_BUS_SSB:
5942                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5943                                                 0xFC00, 0xFC00);
5944                         break;
5945 #endif
5946                 }
5947
5948                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5949                 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5950                 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5951                               0);
5952
5953                 if (init) {
5954                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5955                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5956                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5957                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5958                 }
5959         }
5960 }
5961
5962 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
5963 static int b43_phy_initn(struct b43_wldev *dev)
5964 {
5965         struct ssb_sprom *sprom = dev->dev->bus_sprom;
5966         struct b43_phy *phy = &dev->phy;
5967         struct b43_phy_n *nphy = phy->n;
5968         u8 tx_pwr_state;
5969         struct nphy_txgains target;
5970         u16 tmp;
5971         enum ieee80211_band tmp2;
5972         bool do_rssi_cal;
5973
5974         u16 clip[2];
5975         bool do_cal = false;
5976
5977         if ((dev->phy.rev >= 3) &&
5978            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
5979            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
5980                 switch (dev->dev->bus_type) {
5981 #ifdef CONFIG_B43_BCMA
5982                 case B43_BUS_BCMA:
5983                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5984                                       BCMA_CC_CHIPCTL, 0x40);
5985                         break;
5986 #endif
5987 #ifdef CONFIG_B43_SSB
5988                 case B43_BUS_SSB:
5989                         chipco_set32(&dev->dev->sdev->bus->chipco,
5990                                      SSB_CHIPCO_CHIPCTL, 0x40);
5991                         break;
5992 #endif
5993                 }
5994         }
5995         nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) ||
5996                 phy->rev >= 7 ||
5997                 (phy->rev >= 5 &&
5998                  sprom->boardflags2_hi & B43_BFH2_INTERNDET_TXIQCAL);
5999         nphy->deaf_count = 0;
6000         b43_nphy_tables_init(dev);
6001         nphy->crsminpwr_adjusted = false;
6002         nphy->noisevars_adjusted = false;
6003
6004         /* Clear all overrides */
6005         if (dev->phy.rev >= 3) {
6006                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
6007                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
6008                 if (phy->rev >= 7) {
6009                         b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0);
6010                         b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0);
6011                         b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0);
6012                         b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0);
6013                 }
6014                 if (phy->rev >= 19) {
6015                         /* TODO */
6016                 }
6017
6018                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
6019                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
6020         } else {
6021                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
6022         }
6023         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
6024         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
6025         if (dev->phy.rev < 6) {
6026                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
6027                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
6028         }
6029         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
6030                      ~(B43_NPHY_RFSEQMODE_CAOVER |
6031                        B43_NPHY_RFSEQMODE_TROVER));
6032         if (dev->phy.rev >= 3)
6033                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
6034         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
6035
6036         if (dev->phy.rev <= 2) {
6037                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
6038                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
6039                                 ~B43_NPHY_BPHY_CTL3_SCALE,
6040                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
6041         }
6042         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
6043         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
6044
6045         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
6046             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
6047              dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
6048                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
6049         else
6050                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
6051         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
6052         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
6053         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
6054
6055         if (phy->rev < 8)
6056                 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
6057
6058         b43_nphy_update_txrx_chain(dev);
6059
6060         if (phy->rev < 2) {
6061                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
6062                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
6063         }
6064
6065         tmp2 = b43_current_band(dev->wl);
6066         if (b43_nphy_ipa(dev)) {
6067                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
6068                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
6069                                 nphy->papd_epsilon_offset[0] << 7);
6070                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
6071                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
6072                                 nphy->papd_epsilon_offset[1] << 7);
6073                 b43_nphy_int_pa_set_tx_dig_filters(dev);
6074         } else if (phy->rev >= 5) {
6075                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
6076         }
6077
6078         b43_nphy_workarounds(dev);
6079
6080         /* Reset CCA, in init code it differs a little from standard way */
6081         b43_phy_force_clock(dev, 1);
6082         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
6083         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
6084         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
6085         b43_phy_force_clock(dev, 0);
6086
6087         b43_mac_phy_clock_set(dev, true);
6088
6089         if (phy->rev < 7) {
6090                 b43_nphy_pa_override(dev, false);
6091                 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6092                 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
6093                 b43_nphy_pa_override(dev, true);
6094         }
6095
6096         b43_nphy_classifier(dev, 0, 0);
6097         b43_nphy_read_clip_detection(dev, clip);
6098         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
6099                 b43_nphy_bphy_init(dev);
6100
6101         tx_pwr_state = nphy->txpwrctrl;
6102         b43_nphy_tx_power_ctrl(dev, false);
6103         b43_nphy_tx_power_fix(dev);
6104         b43_nphy_tx_power_ctl_idle_tssi(dev);
6105         b43_nphy_tx_power_ctl_setup(dev);
6106         b43_nphy_tx_gain_table_upload(dev);
6107
6108         if (nphy->phyrxchain != 3)
6109                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
6110         if (nphy->mphase_cal_phase_id > 0)
6111                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
6112
6113         do_rssi_cal = false;
6114         if (phy->rev >= 3) {
6115                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
6116                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
6117                 else
6118                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
6119
6120                 if (do_rssi_cal)
6121                         b43_nphy_rssi_cal(dev);
6122                 else
6123                         b43_nphy_restore_rssi_cal(dev);
6124         } else {
6125                 b43_nphy_rssi_cal(dev);
6126         }
6127
6128         if (!((nphy->measure_hold & 0x6) != 0)) {
6129                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
6130                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
6131                 else
6132                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
6133
6134                 if (nphy->mute)
6135                         do_cal = false;
6136
6137                 if (do_cal) {
6138                         target = b43_nphy_get_tx_gains(dev);
6139
6140                         if (nphy->antsel_type == 2)
6141                                 b43_nphy_superswitch_init(dev, true);
6142                         if (nphy->perical != 2) {
6143                                 b43_nphy_rssi_cal(dev);
6144                                 if (phy->rev >= 3) {
6145                                         nphy->cal_orig_pwr_idx[0] =
6146                                             nphy->txpwrindex[0].index_internal;
6147                                         nphy->cal_orig_pwr_idx[1] =
6148                                             nphy->txpwrindex[1].index_internal;
6149                                         /* TODO N PHY Pre Calibrate TX Gain */
6150                                         target = b43_nphy_get_tx_gains(dev);
6151                                 }
6152                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
6153                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
6154                                                 b43_nphy_save_cal(dev);
6155                         } else if (nphy->mphase_cal_phase_id == 0)
6156                                 ;/* N PHY Periodic Calibration with arg 3 */
6157                 } else {
6158                         b43_nphy_restore_cal(dev);
6159                 }
6160         }
6161
6162         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
6163         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
6164         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
6165         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
6166         if (phy->rev >= 3 && phy->rev <= 6)
6167                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
6168         b43_nphy_tx_lpf_bw(dev);
6169         if (phy->rev >= 3)
6170                 b43_nphy_spur_workaround(dev);
6171
6172         return 0;
6173 }
6174
6175 /**************************************************
6176  * Channel switching ops.
6177  **************************************************/
6178
6179 static void b43_chantab_phy_upload(struct b43_wldev *dev,
6180                                    const struct b43_phy_n_sfo_cfg *e)
6181 {
6182         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
6183         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
6184         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
6185         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
6186         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
6187         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
6188 }
6189
6190 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
6191 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
6192 {
6193         switch (dev->dev->bus_type) {
6194 #ifdef CONFIG_B43_BCMA
6195         case B43_BUS_BCMA:
6196                 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
6197                                              avoid);
6198                 break;
6199 #endif
6200 #ifdef CONFIG_B43_SSB
6201         case B43_BUS_SSB:
6202                 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
6203                                             avoid);
6204                 break;
6205 #endif
6206         }
6207 }
6208
6209 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
6210 static void b43_nphy_channel_setup(struct b43_wldev *dev,
6211                                 const struct b43_phy_n_sfo_cfg *e,
6212                                 struct ieee80211_channel *new_channel)
6213 {
6214         struct b43_phy *phy = &dev->phy;
6215         struct b43_phy_n *nphy = dev->phy.n;
6216         int ch = new_channel->hw_value;
6217         u16 tmp16;
6218
6219         if (new_channel->band == IEEE80211_BAND_5GHZ) {
6220                 /* Switch to 2 GHz for a moment to access B43_PHY_B_BBCFG */
6221                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
6222
6223                 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
6224                 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
6225                 /* Put BPHY in the reset */
6226                 b43_phy_set(dev, B43_PHY_B_BBCFG,
6227                             B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX);
6228                 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
6229                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
6230         } else if (new_channel->band == IEEE80211_BAND_2GHZ) {
6231                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
6232                 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
6233                 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
6234                 /* Take BPHY out of the reset */
6235                 b43_phy_mask(dev, B43_PHY_B_BBCFG,
6236                              (u16)~(B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX));
6237                 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
6238         }
6239
6240         b43_chantab_phy_upload(dev, e);
6241
6242         if (new_channel->hw_value == 14) {
6243                 b43_nphy_classifier(dev, 2, 0);
6244                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
6245         } else {
6246                 b43_nphy_classifier(dev, 2, 2);
6247                 if (new_channel->band == IEEE80211_BAND_2GHZ)
6248                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
6249         }
6250
6251         if (!nphy->txpwrctrl)
6252                 b43_nphy_tx_power_fix(dev);
6253
6254         if (dev->phy.rev < 3)
6255                 b43_nphy_adjust_lna_gain_table(dev);
6256
6257         b43_nphy_tx_lpf_bw(dev);
6258
6259         if (dev->phy.rev >= 3 &&
6260             dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
6261                 u8 spuravoid = 0;
6262
6263                 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
6264                         spuravoid = 1;
6265                 } else if (phy->rev >= 19) {
6266                         /* TODO */
6267                 } else if (phy->rev >= 18) {
6268                         /* TODO */
6269                 } else if (phy->rev >= 17) {
6270                         /* TODO: Off for channels 1-11, but check 12-14! */
6271                 } else if (phy->rev >= 16) {
6272                         /* TODO: Off for 2 GHz, but check 5 GHz! */
6273                 } else if (phy->rev >= 7) {
6274                         if (!b43_is_40mhz(dev)) { /* 20MHz */
6275                                 if (ch == 13 || ch == 14 || ch == 153)
6276                                         spuravoid = 1;
6277                         } else { /* 40 MHz */
6278                                 if (ch == 54)
6279                                         spuravoid = 1;
6280                         }
6281                 } else {
6282                         if (!b43_is_40mhz(dev)) { /* 20MHz */
6283                                 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
6284                                         spuravoid = 1;
6285                         } else { /* 40MHz */
6286                                 if (nphy->aband_spurwar_en &&
6287                                     (ch == 38 || ch == 102 || ch == 118))
6288                                         spuravoid = dev->dev->chip_id == 0x4716;
6289                         }
6290                 }
6291
6292                 b43_nphy_pmu_spur_avoid(dev, spuravoid);
6293
6294                 b43_mac_switch_freq(dev, spuravoid);
6295
6296                 if (dev->phy.rev == 3 || dev->phy.rev == 4)
6297                         ; /* TODO: reset PLL */
6298
6299                 if (spuravoid)
6300                         b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
6301                 else
6302                         b43_phy_mask(dev, B43_NPHY_BBCFG,
6303                                      ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
6304
6305                 b43_nphy_reset_cca(dev);
6306
6307                 /* wl sets useless phy_isspuravoid here */
6308         }
6309
6310         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
6311
6312         if (phy->rev >= 3)
6313                 b43_nphy_spur_workaround(dev);
6314 }
6315
6316 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
6317 static int b43_nphy_set_channel(struct b43_wldev *dev,
6318                                 struct ieee80211_channel *channel,
6319                                 enum nl80211_channel_type channel_type)
6320 {
6321         struct b43_phy *phy = &dev->phy;
6322
6323         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
6324         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
6325         const struct b43_nphy_chantabent_rev7 *tabent_r7 = NULL;
6326         const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL;
6327
6328         u8 tmp;
6329
6330         if (phy->rev >= 19) {
6331                 return -ESRCH;
6332                 /* TODO */
6333         } else if (phy->rev >= 7) {
6334                 r2057_get_chantabent_rev7(dev, channel->center_freq,
6335                                           &tabent_r7, &tabent_r7_2g);
6336                 if (!tabent_r7 && !tabent_r7_2g)
6337                         return -ESRCH;
6338         } else if (phy->rev >= 3) {
6339                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
6340                                                         channel->center_freq);
6341                 if (!tabent_r3)
6342                         return -ESRCH;
6343         } else {
6344                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
6345                                                         channel->hw_value);
6346                 if (!tabent_r2)
6347                         return -ESRCH;
6348         }
6349
6350         /* Channel is set later in common code, but we need to set it on our
6351            own to let this function's subcalls work properly. */
6352         phy->channel = channel->hw_value;
6353
6354 #if 0
6355         if (b43_channel_type_is_40mhz(phy->channel_type) !=
6356                 b43_channel_type_is_40mhz(channel_type))
6357                 ; /* TODO: BMAC BW Set (channel_type) */
6358 #endif
6359
6360         if (channel_type == NL80211_CHAN_HT40PLUS) {
6361                 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20);
6362                 if (phy->rev >= 7)
6363                         b43_phy_set(dev, 0x310, 0x8000);
6364         } else if (channel_type == NL80211_CHAN_HT40MINUS) {
6365                 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20);
6366                 if (phy->rev >= 7)
6367                         b43_phy_mask(dev, 0x310, (u16)~0x8000);
6368         }
6369
6370         if (phy->rev >= 19) {
6371                 /* TODO */
6372         } else if (phy->rev >= 7) {
6373                 const struct b43_phy_n_sfo_cfg *phy_regs = tabent_r7 ?
6374                         &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs);
6375
6376                 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
6377                         tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 2 : 0;
6378                         b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp);
6379                         b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp);
6380                 }
6381
6382                 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g);
6383                 b43_nphy_channel_setup(dev, phy_regs, channel);
6384         } else if (phy->rev >= 3) {
6385                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
6386                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
6387                 b43_radio_2056_setup(dev, tabent_r3);
6388                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
6389         } else {
6390                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
6391                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
6392                 b43_radio_2055_setup(dev, tabent_r2);
6393                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
6394         }
6395
6396         return 0;
6397 }
6398
6399 /**************************************************
6400  * Basic PHY ops.
6401  **************************************************/
6402
6403 static int b43_nphy_op_allocate(struct b43_wldev *dev)
6404 {
6405         struct b43_phy_n *nphy;
6406
6407         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
6408         if (!nphy)
6409                 return -ENOMEM;
6410         dev->phy.n = nphy;
6411
6412         return 0;
6413 }
6414
6415 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
6416 {
6417         struct b43_phy *phy = &dev->phy;
6418         struct b43_phy_n *nphy = phy->n;
6419         struct ssb_sprom *sprom = dev->dev->bus_sprom;
6420
6421         memset(nphy, 0, sizeof(*nphy));
6422
6423         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
6424         nphy->spur_avoid = (phy->rev >= 3) ?
6425                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
6426         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
6427         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
6428         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
6429         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
6430         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
6431          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
6432         nphy->tx_pwr_idx[0] = 128;
6433         nphy->tx_pwr_idx[1] = 128;
6434
6435         /* Hardware TX power control and 5GHz power gain */
6436         nphy->txpwrctrl = false;
6437         nphy->pwg_gain_5ghz = false;
6438         if (dev->phy.rev >= 3 ||
6439             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
6440              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
6441                 nphy->txpwrctrl = true;
6442                 nphy->pwg_gain_5ghz = true;
6443         } else if (sprom->revision >= 4) {
6444                 if (dev->phy.rev >= 2 &&
6445                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
6446                         nphy->txpwrctrl = true;
6447 #ifdef CONFIG_B43_SSB
6448                         if (dev->dev->bus_type == B43_BUS_SSB &&
6449                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
6450                                 struct pci_dev *pdev =
6451                                         dev->dev->sdev->bus->host_pci;
6452                                 if (pdev->device == 0x4328 ||
6453                                     pdev->device == 0x432a)
6454                                         nphy->pwg_gain_5ghz = true;
6455                         }
6456 #endif
6457                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
6458                         nphy->pwg_gain_5ghz = true;
6459                 }
6460         }
6461
6462         if (dev->phy.rev >= 3) {
6463                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
6464                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
6465         }
6466 }
6467
6468 static void b43_nphy_op_free(struct b43_wldev *dev)
6469 {
6470         struct b43_phy *phy = &dev->phy;
6471         struct b43_phy_n *nphy = phy->n;
6472
6473         kfree(nphy);
6474         phy->n = NULL;
6475 }
6476
6477 static int b43_nphy_op_init(struct b43_wldev *dev)
6478 {
6479         return b43_phy_initn(dev);
6480 }
6481
6482 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
6483 {
6484 #if B43_DEBUG
6485         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
6486                 /* OFDM registers are onnly available on A/G-PHYs */
6487                 b43err(dev->wl, "Invalid OFDM PHY access at "
6488                        "0x%04X on N-PHY\n", offset);
6489                 dump_stack();
6490         }
6491         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
6492                 /* Ext-G registers are only available on G-PHYs */
6493                 b43err(dev->wl, "Invalid EXT-G PHY access at "
6494                        "0x%04X on N-PHY\n", offset);
6495                 dump_stack();
6496         }
6497 #endif /* B43_DEBUG */
6498 }
6499
6500 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
6501 {
6502         check_phyreg(dev, reg);
6503         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
6504         return b43_read16(dev, B43_MMIO_PHY_DATA);
6505 }
6506
6507 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
6508 {
6509         check_phyreg(dev, reg);
6510         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
6511         b43_write16(dev, B43_MMIO_PHY_DATA, value);
6512 }
6513
6514 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
6515                                  u16 set)
6516 {
6517         check_phyreg(dev, reg);
6518         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
6519         b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
6520 }
6521
6522 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
6523 {
6524         /* Register 1 is a 32-bit register. */
6525         B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
6526
6527         if (dev->phy.rev >= 7)
6528                 reg |= 0x200; /* Radio 0x2057 */
6529         else
6530                 reg |= 0x100;
6531
6532         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
6533         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
6534 }
6535
6536 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
6537 {
6538         /* Register 1 is a 32-bit register. */
6539         B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
6540
6541         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
6542         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
6543 }
6544
6545 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
6546 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
6547                                         bool blocked)
6548 {
6549         struct b43_phy *phy = &dev->phy;
6550
6551         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
6552                 b43err(dev->wl, "MAC not suspended\n");
6553
6554         if (blocked) {
6555                 if (phy->rev >= 19) {
6556                         /* TODO */
6557                 } else if (phy->rev >= 8) {
6558                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
6559                                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
6560                 } else if (phy->rev >= 7) {
6561                         /* Nothing needed */
6562                 } else if (phy->rev >= 3) {
6563                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
6564                                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
6565
6566                         b43_radio_mask(dev, 0x09, ~0x2);
6567
6568                         b43_radio_write(dev, 0x204D, 0);
6569                         b43_radio_write(dev, 0x2053, 0);
6570                         b43_radio_write(dev, 0x2058, 0);
6571                         b43_radio_write(dev, 0x205E, 0);
6572                         b43_radio_mask(dev, 0x2062, ~0xF0);
6573                         b43_radio_write(dev, 0x2064, 0);
6574
6575                         b43_radio_write(dev, 0x304D, 0);
6576                         b43_radio_write(dev, 0x3053, 0);
6577                         b43_radio_write(dev, 0x3058, 0);
6578                         b43_radio_write(dev, 0x305E, 0);
6579                         b43_radio_mask(dev, 0x3062, ~0xF0);
6580                         b43_radio_write(dev, 0x3064, 0);
6581                 }
6582         } else {
6583                 if (phy->rev >= 19) {
6584                         /* TODO */
6585                 } else if (phy->rev >= 7) {
6586                         if (!dev->phy.radio_on)
6587                                 b43_radio_2057_init(dev);
6588                         b43_switch_channel(dev, dev->phy.channel);
6589                 } else if (phy->rev >= 3) {
6590                         if (!dev->phy.radio_on)
6591                                 b43_radio_init2056(dev);
6592                         b43_switch_channel(dev, dev->phy.channel);
6593                 } else {
6594                         b43_radio_init2055(dev);
6595                 }
6596         }
6597 }
6598
6599 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
6600 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
6601 {
6602         struct b43_phy *phy = &dev->phy;
6603         u16 override = on ? 0x0 : 0x7FFF;
6604         u16 core = on ? 0xD : 0x00FD;
6605
6606         if (phy->rev >= 19) {
6607                 /* TODO */
6608         } else if (phy->rev >= 3) {
6609                 if (on) {
6610                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
6611                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
6612                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
6613                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6614                 } else {
6615                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
6616                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
6617                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6618                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
6619                 }
6620         } else {
6621                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6622         }
6623 }
6624
6625 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
6626                                       unsigned int new_channel)
6627 {
6628         struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
6629         enum nl80211_channel_type channel_type =
6630                 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
6631
6632         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
6633                 if ((new_channel < 1) || (new_channel > 14))
6634                         return -EINVAL;
6635         } else {
6636                 if (new_channel > 200)
6637                         return -EINVAL;
6638         }
6639
6640         return b43_nphy_set_channel(dev, channel, channel_type);
6641 }
6642
6643 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
6644 {
6645         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
6646                 return 1;
6647         return 36;
6648 }
6649
6650 const struct b43_phy_operations b43_phyops_n = {
6651         .allocate               = b43_nphy_op_allocate,
6652         .free                   = b43_nphy_op_free,
6653         .prepare_structs        = b43_nphy_op_prepare_structs,
6654         .init                   = b43_nphy_op_init,
6655         .phy_read               = b43_nphy_op_read,
6656         .phy_write              = b43_nphy_op_write,
6657         .phy_maskset            = b43_nphy_op_maskset,
6658         .radio_read             = b43_nphy_op_radio_read,
6659         .radio_write            = b43_nphy_op_radio_write,
6660         .software_rfkill        = b43_nphy_op_software_rfkill,
6661         .switch_analog          = b43_nphy_op_switch_analog,
6662         .switch_channel         = b43_nphy_op_switch_channel,
6663         .get_default_chan       = b43_nphy_op_get_default_chan,
6664         .recalc_txpower         = b43_nphy_op_recalc_txpower,
6665         .adjust_txpower         = b43_nphy_op_adjust_txpower,
6666 };