3 Broadcom B43legacy wireless driver
5 DMA ringbuffer and descriptor allocation/management
7 Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
30 #include "b43legacy.h"
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/slab.h>
45 struct b43legacy_dmadesc32 *op32_idx2desc(struct b43legacy_dmaring *ring,
47 struct b43legacy_dmadesc_meta **meta)
49 struct b43legacy_dmadesc32 *desc;
51 *meta = &(ring->meta[slot]);
52 desc = ring->descbase;
55 return (struct b43legacy_dmadesc32 *)desc;
58 static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
59 struct b43legacy_dmadesc32 *desc,
60 dma_addr_t dmaaddr, u16 bufsize,
61 int start, int end, int irq)
63 struct b43legacy_dmadesc32 *descbase = ring->descbase;
69 slot = (int)(desc - descbase);
70 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
72 addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
73 addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
74 >> SSB_DMA_TRANSLATION_SHIFT;
75 addr |= ring->dev->dma.translation;
76 ctl = (bufsize - ring->frameoffset)
77 & B43legacy_DMA32_DCTL_BYTECNT;
78 if (slot == ring->nr_slots - 1)
79 ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
81 ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
83 ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
85 ctl |= B43legacy_DMA32_DCTL_IRQ;
86 ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
87 & B43legacy_DMA32_DCTL_ADDREXT_MASK;
89 desc->control = cpu_to_le32(ctl);
90 desc->address = cpu_to_le32(addr);
93 static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
95 b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
96 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
99 static void op32_tx_suspend(struct b43legacy_dmaring *ring)
101 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
102 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
103 | B43legacy_DMA32_TXSUSPEND);
106 static void op32_tx_resume(struct b43legacy_dmaring *ring)
108 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
109 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
110 & ~B43legacy_DMA32_TXSUSPEND);
113 static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
117 val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
118 val &= B43legacy_DMA32_RXDPTR;
120 return (val / sizeof(struct b43legacy_dmadesc32));
123 static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
126 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
127 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
130 static inline int free_slots(struct b43legacy_dmaring *ring)
132 return (ring->nr_slots - ring->used_slots);
135 static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
137 B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
138 if (slot == ring->nr_slots - 1)
143 static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
145 B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
147 return ring->nr_slots - 1;
151 #ifdef CONFIG_B43LEGACY_DEBUG
152 static void update_max_used_slots(struct b43legacy_dmaring *ring,
153 int current_used_slots)
155 if (current_used_slots <= ring->max_used_slots)
157 ring->max_used_slots = current_used_slots;
158 if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
159 b43legacydbg(ring->dev->wl,
160 "max_used_slots increased to %d on %s ring %d\n",
161 ring->max_used_slots,
162 ring->tx ? "TX" : "RX",
167 void update_max_used_slots(struct b43legacy_dmaring *ring,
168 int current_used_slots)
172 /* Request a slot for usage. */
174 int request_slot(struct b43legacy_dmaring *ring)
178 B43legacy_WARN_ON(!ring->tx);
179 B43legacy_WARN_ON(ring->stopped);
180 B43legacy_WARN_ON(free_slots(ring) == 0);
182 slot = next_slot(ring, ring->current_slot);
183 ring->current_slot = slot;
186 update_max_used_slots(ring, ring->used_slots);
191 /* Mac80211-queue to b43legacy-ring mapping */
192 static struct b43legacy_dmaring *priority_to_txring(
193 struct b43legacy_wldev *dev,
196 struct b43legacy_dmaring *ring;
198 /*FIXME: For now we always run on TX-ring-1 */
199 return dev->dma.tx_ring1;
201 /* 0 = highest priority */
202 switch (queue_priority) {
204 B43legacy_WARN_ON(1);
207 ring = dev->dma.tx_ring3;
210 ring = dev->dma.tx_ring2;
213 ring = dev->dma.tx_ring1;
216 ring = dev->dma.tx_ring0;
219 ring = dev->dma.tx_ring4;
222 ring = dev->dma.tx_ring5;
229 /* Bcm4301-ring to mac80211-queue mapping */
230 static inline int txring_to_priority(struct b43legacy_dmaring *ring)
232 static const u8 idx_to_prio[] =
233 { 3, 2, 1, 0, 4, 5, };
235 /*FIXME: have only one queue, for now */
238 return idx_to_prio[ring->index];
242 static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
245 static const u16 map32[] = {
246 B43legacy_MMIO_DMA32_BASE0,
247 B43legacy_MMIO_DMA32_BASE1,
248 B43legacy_MMIO_DMA32_BASE2,
249 B43legacy_MMIO_DMA32_BASE3,
250 B43legacy_MMIO_DMA32_BASE4,
251 B43legacy_MMIO_DMA32_BASE5,
254 B43legacy_WARN_ON(!(controller_idx >= 0 &&
255 controller_idx < ARRAY_SIZE(map32)));
256 return map32[controller_idx];
260 dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
268 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
272 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
280 void unmap_descbuffer(struct b43legacy_dmaring *ring,
286 dma_unmap_single(ring->dev->dev->dma_dev,
290 dma_unmap_single(ring->dev->dev->dma_dev,
296 void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
300 B43legacy_WARN_ON(ring->tx);
302 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
303 addr, len, DMA_FROM_DEVICE);
307 void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
311 B43legacy_WARN_ON(ring->tx);
313 dma_sync_single_for_device(ring->dev->dev->dma_dev,
314 addr, len, DMA_FROM_DEVICE);
318 void free_descriptor_buffer(struct b43legacy_dmaring *ring,
319 struct b43legacy_dmadesc_meta *meta,
324 dev_kfree_skb_irq(meta->skb);
326 dev_kfree_skb(meta->skb);
331 static int alloc_ringmemory(struct b43legacy_dmaring *ring)
333 /* GFP flags must match the flags in free_ringmemory()! */
334 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
335 B43legacy_DMA_RINGMEMSIZE,
338 if (!ring->descbase) {
339 b43legacyerr(ring->dev->wl, "DMA ringmemory allocation"
343 memset(ring->descbase, 0, B43legacy_DMA_RINGMEMSIZE);
348 static void free_ringmemory(struct b43legacy_dmaring *ring)
350 dma_free_coherent(ring->dev->dev->dma_dev, B43legacy_DMA_RINGMEMSIZE,
351 ring->descbase, ring->dmabase);
354 /* Reset the RX DMA channel */
355 static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
357 enum b43legacy_dmatype type)
365 offset = B43legacy_DMA32_RXCTL;
366 b43legacy_write32(dev, mmio_base + offset, 0);
367 for (i = 0; i < 10; i++) {
368 offset = B43legacy_DMA32_RXSTATUS;
369 value = b43legacy_read32(dev, mmio_base + offset);
370 value &= B43legacy_DMA32_RXSTATE;
371 if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
378 b43legacyerr(dev->wl, "DMA RX reset timed out\n");
385 /* Reset the RX DMA channel */
386 static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
388 enum b43legacy_dmatype type)
396 for (i = 0; i < 10; i++) {
397 offset = B43legacy_DMA32_TXSTATUS;
398 value = b43legacy_read32(dev, mmio_base + offset);
399 value &= B43legacy_DMA32_TXSTATE;
400 if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
401 value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
402 value == B43legacy_DMA32_TXSTAT_STOPPED)
406 offset = B43legacy_DMA32_TXCTL;
407 b43legacy_write32(dev, mmio_base + offset, 0);
408 for (i = 0; i < 10; i++) {
409 offset = B43legacy_DMA32_TXSTATUS;
410 value = b43legacy_read32(dev, mmio_base + offset);
411 value &= B43legacy_DMA32_TXSTATE;
412 if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
419 b43legacyerr(dev->wl, "DMA TX reset timed out\n");
422 /* ensure the reset is completed. */
428 /* Check if a DMA mapping address is invalid. */
429 static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
434 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
437 switch (ring->type) {
438 case B43legacy_DMA_30BIT:
439 if ((u64)addr + buffersize > (1ULL << 30))
442 case B43legacy_DMA_32BIT:
443 if ((u64)addr + buffersize > (1ULL << 32))
448 /* The address is OK. */
452 /* We can't support this address. Unmap it again. */
453 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
458 static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
459 struct b43legacy_dmadesc32 *desc,
460 struct b43legacy_dmadesc_meta *meta,
463 struct b43legacy_rxhdr_fw3 *rxhdr;
464 struct b43legacy_hwtxstatus *txstat;
468 B43legacy_WARN_ON(ring->tx);
470 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
473 dmaaddr = map_descbuffer(ring, skb->data,
474 ring->rx_buffersize, 0);
475 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
476 /* ugh. try to realloc in zone_dma */
477 gfp_flags |= GFP_DMA;
479 dev_kfree_skb_any(skb);
481 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
484 dmaaddr = map_descbuffer(ring, skb->data,
485 ring->rx_buffersize, 0);
488 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
489 dev_kfree_skb_any(skb);
494 meta->dmaaddr = dmaaddr;
495 op32_fill_descriptor(ring, desc, dmaaddr, ring->rx_buffersize, 0, 0, 0);
497 rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
498 rxhdr->frame_len = 0;
499 txstat = (struct b43legacy_hwtxstatus *)(skb->data);
505 /* Allocate the initial descbuffers.
506 * This is used for an RX ring only.
508 static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
512 struct b43legacy_dmadesc32 *desc;
513 struct b43legacy_dmadesc_meta *meta;
515 for (i = 0; i < ring->nr_slots; i++) {
516 desc = op32_idx2desc(ring, i, &meta);
518 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
520 b43legacyerr(ring->dev->wl,
521 "Failed to allocate initial descbuffers\n");
525 mb(); /* all descbuffer setup before next line */
526 ring->used_slots = ring->nr_slots;
532 for (i--; i >= 0; i--) {
533 desc = op32_idx2desc(ring, i, &meta);
535 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
536 dev_kfree_skb(meta->skb);
541 /* Do initial setup of the DMA controller.
542 * Reset the controller, write the ring busaddress
543 * and switch the "enable" bit on.
545 static int dmacontroller_setup(struct b43legacy_dmaring *ring)
550 u32 trans = ring->dev->dma.translation;
551 u32 ringbase = (u32)(ring->dmabase);
554 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
555 >> SSB_DMA_TRANSLATION_SHIFT;
556 value = B43legacy_DMA32_TXENABLE;
557 value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
558 & B43legacy_DMA32_TXADDREXT_MASK;
559 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL, value);
560 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
561 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
564 err = alloc_initial_descbuffers(ring);
568 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
569 >> SSB_DMA_TRANSLATION_SHIFT;
570 value = (ring->frameoffset <<
571 B43legacy_DMA32_RXFROFF_SHIFT);
572 value |= B43legacy_DMA32_RXENABLE;
573 value |= (addrext << B43legacy_DMA32_RXADDREXT_SHIFT)
574 & B43legacy_DMA32_RXADDREXT_MASK;
575 b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL, value);
576 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
577 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
579 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX, 200);
586 /* Shutdown the DMA controller. */
587 static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
590 b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
592 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
594 b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
596 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
600 static void free_all_descbuffers(struct b43legacy_dmaring *ring)
602 struct b43legacy_dmadesc_meta *meta;
605 if (!ring->used_slots)
607 for (i = 0; i < ring->nr_slots; i++) {
608 op32_idx2desc(ring, i, &meta);
611 B43legacy_WARN_ON(!ring->tx);
615 unmap_descbuffer(ring, meta->dmaaddr,
618 unmap_descbuffer(ring, meta->dmaaddr,
619 ring->rx_buffersize, 0);
620 free_descriptor_buffer(ring, meta, 0);
624 static u64 supported_dma_mask(struct b43legacy_wldev *dev)
629 mmio_base = b43legacy_dmacontroller_base(0, 0);
630 b43legacy_write32(dev,
631 mmio_base + B43legacy_DMA32_TXCTL,
632 B43legacy_DMA32_TXADDREXT_MASK);
633 tmp = b43legacy_read32(dev, mmio_base +
634 B43legacy_DMA32_TXCTL);
635 if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
636 return DMA_BIT_MASK(32);
638 return DMA_BIT_MASK(30);
641 static enum b43legacy_dmatype dma_mask_to_engine_type(u64 dmamask)
643 if (dmamask == DMA_BIT_MASK(30))
644 return B43legacy_DMA_30BIT;
645 if (dmamask == DMA_BIT_MASK(32))
646 return B43legacy_DMA_32BIT;
647 B43legacy_WARN_ON(1);
648 return B43legacy_DMA_30BIT;
651 /* Main initialization function. */
653 struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
654 int controller_index,
656 enum b43legacy_dmatype type)
658 struct b43legacy_dmaring *ring;
663 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
669 nr_slots = B43legacy_RXRING_SLOTS;
671 nr_slots = B43legacy_TXRING_SLOTS;
673 ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
678 ring->txhdr_cache = kcalloc(nr_slots,
679 sizeof(struct b43legacy_txhdr_fw3),
681 if (!ring->txhdr_cache)
684 /* test for ability to dma to txhdr_cache */
685 dma_test = dma_map_single(dev->dev->dma_dev, ring->txhdr_cache,
686 sizeof(struct b43legacy_txhdr_fw3),
689 if (b43legacy_dma_mapping_error(ring, dma_test,
690 sizeof(struct b43legacy_txhdr_fw3), 1)) {
692 kfree(ring->txhdr_cache);
693 ring->txhdr_cache = kcalloc(nr_slots,
694 sizeof(struct b43legacy_txhdr_fw3),
695 GFP_KERNEL | GFP_DMA);
696 if (!ring->txhdr_cache)
699 dma_test = dma_map_single(dev->dev->dma_dev,
701 sizeof(struct b43legacy_txhdr_fw3),
704 if (b43legacy_dma_mapping_error(ring, dma_test,
705 sizeof(struct b43legacy_txhdr_fw3), 1))
706 goto err_kfree_txhdr_cache;
709 dma_unmap_single(dev->dev->dma_dev, dma_test,
710 sizeof(struct b43legacy_txhdr_fw3),
714 ring->nr_slots = nr_slots;
715 ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);
716 ring->index = controller_index;
719 ring->current_slot = -1;
721 if (ring->index == 0) {
722 ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
723 ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
724 } else if (ring->index == 3) {
725 ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
726 ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
728 B43legacy_WARN_ON(1);
730 spin_lock_init(&ring->lock);
731 #ifdef CONFIG_B43LEGACY_DEBUG
732 ring->last_injected_overflow = jiffies;
735 err = alloc_ringmemory(ring);
737 goto err_kfree_txhdr_cache;
738 err = dmacontroller_setup(ring);
740 goto err_free_ringmemory;
746 free_ringmemory(ring);
747 err_kfree_txhdr_cache:
748 kfree(ring->txhdr_cache);
757 /* Main cleanup function. */
758 static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
763 b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:"
764 " %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,
765 (ring->tx) ? "TX" : "RX", ring->max_used_slots,
767 /* Device IRQs are disabled prior entering this function,
768 * so no need to take care of concurrency with rx handler stuff.
770 dmacontroller_cleanup(ring);
771 free_all_descbuffers(ring);
772 free_ringmemory(ring);
774 kfree(ring->txhdr_cache);
779 void b43legacy_dma_free(struct b43legacy_wldev *dev)
781 struct b43legacy_dma *dma;
783 if (b43legacy_using_pio(dev))
787 b43legacy_destroy_dmaring(dma->rx_ring3);
788 dma->rx_ring3 = NULL;
789 b43legacy_destroy_dmaring(dma->rx_ring0);
790 dma->rx_ring0 = NULL;
792 b43legacy_destroy_dmaring(dma->tx_ring5);
793 dma->tx_ring5 = NULL;
794 b43legacy_destroy_dmaring(dma->tx_ring4);
795 dma->tx_ring4 = NULL;
796 b43legacy_destroy_dmaring(dma->tx_ring3);
797 dma->tx_ring3 = NULL;
798 b43legacy_destroy_dmaring(dma->tx_ring2);
799 dma->tx_ring2 = NULL;
800 b43legacy_destroy_dmaring(dma->tx_ring1);
801 dma->tx_ring1 = NULL;
802 b43legacy_destroy_dmaring(dma->tx_ring0);
803 dma->tx_ring0 = NULL;
806 static int b43legacy_dma_set_mask(struct b43legacy_wldev *dev, u64 mask)
808 u64 orig_mask = mask;
809 bool fallback = false;
812 /* Try to set the DMA mask. If it fails, try falling back to a
813 * lower mask, as we can always also support a lower one. */
815 err = dma_set_mask(dev->dev->dma_dev, mask);
817 err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
821 if (mask == DMA_BIT_MASK(64)) {
822 mask = DMA_BIT_MASK(32);
826 if (mask == DMA_BIT_MASK(32)) {
827 mask = DMA_BIT_MASK(30);
831 b43legacyerr(dev->wl, "The machine/kernel does not support "
832 "the required %u-bit DMA mask\n",
833 (unsigned int)dma_mask_to_engine_type(orig_mask));
837 b43legacyinfo(dev->wl, "DMA mask fallback from %u-bit to %u-"
839 (unsigned int)dma_mask_to_engine_type(orig_mask),
840 (unsigned int)dma_mask_to_engine_type(mask));
846 int b43legacy_dma_init(struct b43legacy_wldev *dev)
848 struct b43legacy_dma *dma = &dev->dma;
849 struct b43legacy_dmaring *ring;
852 enum b43legacy_dmatype type;
854 dmamask = supported_dma_mask(dev);
855 type = dma_mask_to_engine_type(dmamask);
856 err = b43legacy_dma_set_mask(dev, dmamask);
858 #ifdef CONFIG_B43LEGACY_PIO
859 b43legacywarn(dev->wl, "DMA for this device not supported. "
860 "Falling back to PIO\n");
861 dev->__using_pio = true;
864 b43legacyerr(dev->wl, "DMA for this device not supported and "
865 "no PIO support compiled in\n");
869 dma->translation = ssb_dma_translation(dev->dev);
872 /* setup TX DMA channels. */
873 ring = b43legacy_setup_dmaring(dev, 0, 1, type);
876 dma->tx_ring0 = ring;
878 ring = b43legacy_setup_dmaring(dev, 1, 1, type);
880 goto err_destroy_tx0;
881 dma->tx_ring1 = ring;
883 ring = b43legacy_setup_dmaring(dev, 2, 1, type);
885 goto err_destroy_tx1;
886 dma->tx_ring2 = ring;
888 ring = b43legacy_setup_dmaring(dev, 3, 1, type);
890 goto err_destroy_tx2;
891 dma->tx_ring3 = ring;
893 ring = b43legacy_setup_dmaring(dev, 4, 1, type);
895 goto err_destroy_tx3;
896 dma->tx_ring4 = ring;
898 ring = b43legacy_setup_dmaring(dev, 5, 1, type);
900 goto err_destroy_tx4;
901 dma->tx_ring5 = ring;
903 /* setup RX DMA channels. */
904 ring = b43legacy_setup_dmaring(dev, 0, 0, type);
906 goto err_destroy_tx5;
907 dma->rx_ring0 = ring;
909 if (dev->dev->id.revision < 5) {
910 ring = b43legacy_setup_dmaring(dev, 3, 0, type);
912 goto err_destroy_rx0;
913 dma->rx_ring3 = ring;
916 b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type);
922 b43legacy_destroy_dmaring(dma->rx_ring0);
923 dma->rx_ring0 = NULL;
925 b43legacy_destroy_dmaring(dma->tx_ring5);
926 dma->tx_ring5 = NULL;
928 b43legacy_destroy_dmaring(dma->tx_ring4);
929 dma->tx_ring4 = NULL;
931 b43legacy_destroy_dmaring(dma->tx_ring3);
932 dma->tx_ring3 = NULL;
934 b43legacy_destroy_dmaring(dma->tx_ring2);
935 dma->tx_ring2 = NULL;
937 b43legacy_destroy_dmaring(dma->tx_ring1);
938 dma->tx_ring1 = NULL;
940 b43legacy_destroy_dmaring(dma->tx_ring0);
941 dma->tx_ring0 = NULL;
945 /* Generate a cookie for the TX header. */
946 static u16 generate_cookie(struct b43legacy_dmaring *ring,
951 /* Use the upper 4 bits of the cookie as
952 * DMA controller ID and store the slot number
953 * in the lower 12 bits.
954 * Note that the cookie must never be 0, as this
955 * is a special value used in RX path.
957 switch (ring->index) {
977 B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000));
983 /* Inspect a cookie and find out to which controller/slot it belongs. */
985 struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
986 u16 cookie, int *slot)
988 struct b43legacy_dma *dma = &dev->dma;
989 struct b43legacy_dmaring *ring = NULL;
991 switch (cookie & 0xF000) {
993 ring = dma->tx_ring0;
996 ring = dma->tx_ring1;
999 ring = dma->tx_ring2;
1002 ring = dma->tx_ring3;
1005 ring = dma->tx_ring4;
1008 ring = dma->tx_ring5;
1011 B43legacy_WARN_ON(1);
1013 *slot = (cookie & 0x0FFF);
1014 B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1019 static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1020 struct sk_buff **in_skb)
1022 struct sk_buff *skb = *in_skb;
1023 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1025 int slot, old_top_slot, old_used_slots;
1027 struct b43legacy_dmadesc32 *desc;
1028 struct b43legacy_dmadesc_meta *meta;
1029 struct b43legacy_dmadesc_meta *meta_hdr;
1030 struct sk_buff *bounce_skb;
1032 #define SLOTS_PER_PACKET 2
1033 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
1035 old_top_slot = ring->current_slot;
1036 old_used_slots = ring->used_slots;
1038 /* Get a slot for the header. */
1039 slot = request_slot(ring);
1040 desc = op32_idx2desc(ring, slot, &meta_hdr);
1041 memset(meta_hdr, 0, sizeof(*meta_hdr));
1043 header = &(ring->txhdr_cache[slot * sizeof(
1044 struct b43legacy_txhdr_fw3)]);
1045 err = b43legacy_generate_txhdr(ring->dev, header,
1046 skb->data, skb->len, info,
1047 generate_cookie(ring, slot));
1048 if (unlikely(err)) {
1049 ring->current_slot = old_top_slot;
1050 ring->used_slots = old_used_slots;
1054 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1055 sizeof(struct b43legacy_txhdr_fw3), 1);
1056 if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr,
1057 sizeof(struct b43legacy_txhdr_fw3), 1)) {
1058 ring->current_slot = old_top_slot;
1059 ring->used_slots = old_used_slots;
1062 op32_fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1063 sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0);
1065 /* Get a slot for the payload. */
1066 slot = request_slot(ring);
1067 desc = op32_idx2desc(ring, slot, &meta);
1068 memset(meta, 0, sizeof(*meta));
1071 meta->is_last_fragment = true;
1073 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1074 /* create a bounce buffer in zone_dma on mapping failure. */
1075 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1076 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1078 ring->current_slot = old_top_slot;
1079 ring->used_slots = old_used_slots;
1084 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1085 memcpy(bounce_skb->cb, skb->cb, sizeof(skb->cb));
1086 bounce_skb->dev = skb->dev;
1087 skb_set_queue_mapping(bounce_skb, skb_get_queue_mapping(skb));
1088 info = IEEE80211_SKB_CB(bounce_skb);
1090 dev_kfree_skb_any(skb);
1092 *in_skb = bounce_skb;
1094 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1095 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1096 ring->current_slot = old_top_slot;
1097 ring->used_slots = old_used_slots;
1099 goto out_free_bounce;
1103 op32_fill_descriptor(ring, desc, meta->dmaaddr,
1106 wmb(); /* previous stuff MUST be done */
1107 /* Now transfer the whole frame. */
1108 op32_poke_tx(ring, next_slot(ring, slot));
1112 dev_kfree_skb_any(skb);
1114 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1115 sizeof(struct b43legacy_txhdr_fw3), 1);
1120 int should_inject_overflow(struct b43legacy_dmaring *ring)
1122 #ifdef CONFIG_B43LEGACY_DEBUG
1123 if (unlikely(b43legacy_debug(ring->dev,
1124 B43legacy_DBG_DMAOVERFLOW))) {
1125 /* Check if we should inject another ringbuffer overflow
1126 * to test handling of this situation in the stack. */
1127 unsigned long next_overflow;
1129 next_overflow = ring->last_injected_overflow + HZ;
1130 if (time_after(jiffies, next_overflow)) {
1131 ring->last_injected_overflow = jiffies;
1132 b43legacydbg(ring->dev->wl,
1133 "Injecting TX ring overflow on "
1134 "DMA controller %d\n", ring->index);
1138 #endif /* CONFIG_B43LEGACY_DEBUG */
1142 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1143 struct sk_buff *skb)
1145 struct b43legacy_dmaring *ring;
1147 unsigned long flags;
1149 ring = priority_to_txring(dev, skb_get_queue_mapping(skb));
1150 spin_lock_irqsave(&ring->lock, flags);
1151 B43legacy_WARN_ON(!ring->tx);
1153 if (unlikely(ring->stopped)) {
1154 /* We get here only because of a bug in mac80211.
1155 * Because of a race, one packet may be queued after
1156 * the queue is stopped, thus we got called when we shouldn't.
1157 * For now, just refuse the transmit. */
1158 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1159 b43legacyerr(dev->wl, "Packet after queue stopped\n");
1164 if (unlikely(WARN_ON(free_slots(ring) < SLOTS_PER_PACKET))) {
1165 /* If we get here, we have a real error with the queue
1166 * full, but queues not stopped. */
1167 b43legacyerr(dev->wl, "DMA queue overflow\n");
1172 /* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing
1173 * into the skb data or cb now. */
1174 err = dma_tx_fragment(ring, &skb);
1175 if (unlikely(err == -ENOKEY)) {
1176 /* Drop this packet, as we don't have the encryption key
1177 * anymore and must not transmit it unencrypted. */
1178 dev_kfree_skb_any(skb);
1182 if (unlikely(err)) {
1183 b43legacyerr(dev->wl, "DMA tx mapping failure\n");
1186 if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1187 should_inject_overflow(ring)) {
1188 /* This TX ring is full. */
1189 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1190 ring->stopped = true;
1191 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1192 b43legacydbg(dev->wl, "Stopped TX ring %d\n",
1196 spin_unlock_irqrestore(&ring->lock, flags);
1201 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1202 const struct b43legacy_txstatus *status)
1204 struct b43legacy_dmaring *ring;
1205 struct b43legacy_dmadesc_meta *meta;
1209 ring = parse_cookie(dev, status->cookie, &slot);
1210 if (unlikely(!ring))
1212 B43legacy_WARN_ON(!irqs_disabled());
1213 spin_lock(&ring->lock);
1215 B43legacy_WARN_ON(!ring->tx);
1217 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1218 op32_idx2desc(ring, slot, &meta);
1221 unmap_descbuffer(ring, meta->dmaaddr,
1224 unmap_descbuffer(ring, meta->dmaaddr,
1225 sizeof(struct b43legacy_txhdr_fw3),
1228 if (meta->is_last_fragment) {
1229 struct ieee80211_tx_info *info;
1231 info = IEEE80211_SKB_CB(meta->skb);
1233 /* preserve the confiured retry limit before clearing the status
1234 * The xmit function has overwritten the rc's value with the actual
1235 * retry limit done by the hardware */
1236 retry_limit = info->status.rates[0].count;
1237 ieee80211_tx_info_clear_status(info);
1240 info->flags |= IEEE80211_TX_STAT_ACK;
1242 if (status->rts_count > dev->wl->hw->conf.short_frame_max_tx_count) {
1244 * If the short retries (RTS, not data frame) have exceeded
1245 * the limit, the hw will not have tried the selected rate,
1246 * but will have used the fallback rate instead.
1247 * Don't let the rate control count attempts for the selected
1248 * rate in this case, otherwise the statistics will be off.
1250 info->status.rates[0].count = 0;
1251 info->status.rates[1].count = status->frame_count;
1253 if (status->frame_count > retry_limit) {
1254 info->status.rates[0].count = retry_limit;
1255 info->status.rates[1].count = status->frame_count -
1259 info->status.rates[0].count = status->frame_count;
1260 info->status.rates[1].idx = -1;
1264 /* Call back to inform the ieee80211 subsystem about the
1265 * status of the transmission.
1266 * Some fields of txstat are already filled in dma_tx().
1268 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1269 /* skb is freed by ieee80211_tx_status_irqsafe() */
1272 /* No need to call free_descriptor_buffer here, as
1273 * this is only the txhdr, which is not allocated.
1275 B43legacy_WARN_ON(meta->skb != NULL);
1278 /* Everything unmapped and free'd. So it's not used anymore. */
1281 if (meta->is_last_fragment)
1283 slot = next_slot(ring, slot);
1285 dev->stats.last_tx = jiffies;
1286 if (ring->stopped) {
1287 B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1288 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1289 ring->stopped = false;
1290 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1291 b43legacydbg(dev->wl, "Woke up TX ring %d\n",
1295 spin_unlock(&ring->lock);
1298 static void dma_rx(struct b43legacy_dmaring *ring,
1301 struct b43legacy_dmadesc32 *desc;
1302 struct b43legacy_dmadesc_meta *meta;
1303 struct b43legacy_rxhdr_fw3 *rxhdr;
1304 struct sk_buff *skb;
1309 desc = op32_idx2desc(ring, *slot, &meta);
1311 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1314 if (ring->index == 3) {
1315 /* We received an xmit status. */
1316 struct b43legacy_hwtxstatus *hw =
1317 (struct b43legacy_hwtxstatus *)skb->data;
1320 while (hw->cookie == 0) {
1327 b43legacy_handle_hwtxstatus(ring->dev, hw);
1328 /* recycle the descriptor buffer. */
1329 sync_descbuffer_for_device(ring, meta->dmaaddr,
1330 ring->rx_buffersize);
1334 rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data;
1335 len = le16_to_cpu(rxhdr->frame_len);
1342 len = le16_to_cpu(rxhdr->frame_len);
1343 } while (len == 0 && i++ < 5);
1344 if (unlikely(len == 0)) {
1345 /* recycle the descriptor buffer. */
1346 sync_descbuffer_for_device(ring, meta->dmaaddr,
1347 ring->rx_buffersize);
1351 if (unlikely(len > ring->rx_buffersize)) {
1352 /* The data did not fit into one descriptor buffer
1353 * and is split over multiple buffers.
1354 * This should never happen, as we try to allocate buffers
1355 * big enough. So simply ignore this packet.
1361 desc = op32_idx2desc(ring, *slot, &meta);
1362 /* recycle the descriptor buffer. */
1363 sync_descbuffer_for_device(ring, meta->dmaaddr,
1364 ring->rx_buffersize);
1365 *slot = next_slot(ring, *slot);
1367 tmp -= ring->rx_buffersize;
1371 b43legacyerr(ring->dev->wl, "DMA RX buffer too small "
1372 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1373 len, ring->rx_buffersize, cnt);
1377 dmaaddr = meta->dmaaddr;
1378 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1379 if (unlikely(err)) {
1380 b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()"
1382 sync_descbuffer_for_device(ring, dmaaddr,
1383 ring->rx_buffersize);
1387 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1388 skb_put(skb, len + ring->frameoffset);
1389 skb_pull(skb, ring->frameoffset);
1391 b43legacy_rx(ring->dev, skb, rxhdr);
1396 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
1402 B43legacy_WARN_ON(ring->tx);
1403 current_slot = op32_get_current_rxslot(ring);
1404 B43legacy_WARN_ON(!(current_slot >= 0 && current_slot <
1407 slot = ring->current_slot;
1408 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1409 dma_rx(ring, &slot);
1410 update_max_used_slots(ring, ++used_slots);
1412 op32_set_current_rxslot(ring, slot);
1413 ring->current_slot = slot;
1416 static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring)
1418 unsigned long flags;
1420 spin_lock_irqsave(&ring->lock, flags);
1421 B43legacy_WARN_ON(!ring->tx);
1422 op32_tx_suspend(ring);
1423 spin_unlock_irqrestore(&ring->lock, flags);
1426 static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring)
1428 unsigned long flags;
1430 spin_lock_irqsave(&ring->lock, flags);
1431 B43legacy_WARN_ON(!ring->tx);
1432 op32_tx_resume(ring);
1433 spin_unlock_irqrestore(&ring->lock, flags);
1436 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
1438 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1439 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0);
1440 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1);
1441 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2);
1442 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3);
1443 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4);
1444 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5);
1447 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
1449 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5);
1450 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4);
1451 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3);
1452 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2);
1453 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1);
1454 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0);
1455 b43legacy_power_saving_ctl_bits(dev, -1, -1);