drivers/net/wireless/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <asm/unaligned.h>
  26
  27 #include <soc.h>
  28 #include <chipcommon.h>
  29 #include <brcmu_utils.h>
  30 #include <brcmu_wifi.h>
  31 #include <brcm_hw_ids.h>
  32
  33 #include "debug.h"
  34 #include "bus.h"
  35 #include "commonring.h"
  36 #include "msgbuf.h"
  37 #include "pcie.h"
  38 #include "firmware.h"
  39 #include "chip.h"
  40
  41
  42 enum brcmf_pcie_state {
  43         BRCMFMAC_PCIE_STATE_DOWN,
  44         BRCMFMAC_PCIE_STATE_UP
  45 };
  46
  47
  48 #define BRCMF_PCIE_43602_FW_NAME                "brcm/brcmfmac43602-pcie.bin"
  49 #define BRCMF_PCIE_43602_NVRAM_NAME             "brcm/brcmfmac43602-pcie.txt"
  50 #define BRCMF_PCIE_4354_FW_NAME                 "brcm/brcmfmac4354-pcie.bin"
  51 #define BRCMF_PCIE_4354_NVRAM_NAME              "brcm/brcmfmac4354-pcie.txt"
  52 #define BRCMF_PCIE_4356_FW_NAME                 "brcm/brcmfmac4356-pcie.bin"
  53 #define BRCMF_PCIE_4356_NVRAM_NAME              "brcm/brcmfmac4356-pcie.txt"
  54 #define BRCMF_PCIE_43570_FW_NAME                "brcm/brcmfmac43570-pcie.bin"
  55 #define BRCMF_PCIE_43570_NVRAM_NAME             "brcm/brcmfmac43570-pcie.txt"
  56
  57 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  58
  59 #define BRCMF_PCIE_TCM_MAP_SIZE                 (4096 * 1024)
  60 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  61
  62 /* backplane addres space accessed by BAR0 */
  63 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  64 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  65 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  66
  67 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  68 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  69
  70 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  71 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  72
  73 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  74 #define BRCMF_PCIE_REG_INTMASK                  0x94
  75 #define BRCMF_PCIE_REG_SBMBX                    0x98
  76
  77 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
  78 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
  79 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
  80 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
  81 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
  82 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
  83
  84 #define BRCMF_PCIE_GENREV1                      1
  85 #define BRCMF_PCIE_GENREV2                      2
  86
  87 #define BRCMF_PCIE2_INTA                        0x01
  88 #define BRCMF_PCIE2_INTB                        0x02
  89
  90 #define BRCMF_PCIE_INT_0                        0x01
  91 #define BRCMF_PCIE_INT_1                        0x02
  92 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
  93                                                  BRCMF_PCIE_INT_1)
  94
  95 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
  96 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
  97 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
  98 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
  99 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 100 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 101 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 102 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 103 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 104 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 105
 106 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 107                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 108                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 109                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 110                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 111                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 112                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 113                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 114
 115 #define BRCMF_PCIE_MIN_SHARED_VERSION           4
 116 #define BRCMF_PCIE_MAX_SHARED_VERSION           5
 117 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 118 #define BRCMF_PCIE_SHARED_TXPUSH_SUPPORT        0x4000
 119
 120 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 121 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 122
 123 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 124 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 125 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 126 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 127 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 128 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 129 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 130 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 131 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 132 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 133 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 134
 135 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 136 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 137 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 138 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 139
 140 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 141 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 142 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 143 #define BRCMF_RING_MEM_SZ                       16
 144 #define BRCMF_RING_STATE_SZ                     8
 145
 146 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET  4
 147 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET  8
 148 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET  12
 149 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET  16
 150 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET     0
 151 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES        52
 152
 153 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 154
 155 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 156 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 157 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 158
 159 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 160 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 161
 162 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 163 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 164 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 165
 166 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 167 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 168 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 169 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 170
 171 #define BRCMF_PCIE_MBDATA_TIMEOUT               2000
 172
 173 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 174 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 175 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 176 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 177 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 178 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 179 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 180 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 181 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 182 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 183 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 184 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 185 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 186
 187
 188 MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
 189 MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
 190 MODULE_FIRMWARE(BRCMF_PCIE_4354_FW_NAME);
 191 MODULE_FIRMWARE(BRCMF_PCIE_4354_NVRAM_NAME);
 192 MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
 193 MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
 194
 195
 196 struct brcmf_pcie_console {
 197         u32 base_addr;
 198         u32 buf_addr;
 199         u32 bufsize;
 200         u32 read_idx;
 201         u8 log_str[256];
 202         u8 log_idx;
 203 };
 204
 205 struct brcmf_pcie_shared_info {
 206         u32 tcm_base_address;
 207         u32 flags;
 208         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 209         struct brcmf_pcie_ringbuf *flowrings;
 210         u16 max_rxbufpost;
 211         u32 nrof_flowrings;
 212         u32 rx_dataoffset;
 213         u32 htod_mb_data_addr;
 214         u32 dtoh_mb_data_addr;
 215         u32 ring_info_addr;
 216         struct brcmf_pcie_console console;
 217         void *scratch;
 218         dma_addr_t scratch_dmahandle;
 219         void *ringupd;
 220         dma_addr_t ringupd_dmahandle;
 221 };
 222
 223 struct brcmf_pcie_core_info {
 224         u32 base;
 225         u32 wrapbase;
 226 };
 227
 228 struct brcmf_pciedev_info {
 229         enum brcmf_pcie_state state;
 230         bool in_irq;
 231         bool irq_requested;
 232         struct pci_dev *pdev;
 233         char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 234         char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 235         void __iomem *regs;
 236         void __iomem *tcm;
 237         u32 tcm_size;
 238         u32 ram_base;
 239         u32 ram_size;
 240         struct brcmf_chip *ci;
 241         u32 coreid;
 242         u32 generic_corerev;
 243         struct brcmf_pcie_shared_info shared;
 244         void (*ringbell)(struct brcmf_pciedev_info *devinfo);
 245         wait_queue_head_t mbdata_resp_wait;
 246         bool mbdata_completed;
 247         bool irq_allocated;
 248         bool wowl_enabled;
 249 };
 250
 251 struct brcmf_pcie_ringbuf {
 252         struct brcmf_commonring commonring;
 253         dma_addr_t dma_handle;
 254         u32 w_idx_addr;
 255         u32 r_idx_addr;
 256         struct brcmf_pciedev_info *devinfo;
 257         u8 id;
 258 };
 259
 260
 261 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 262         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 263         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 264         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 265         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 266         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 267 };
 268
 269 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 270         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 271         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 272         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 273         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 274         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 275 };
 276
 277
 278 /* dma flushing needs implementation for mips and arm platforms. Should
 279  * be put in util. Note, this is not real flushing. It is virtual non
 280  * cached memory. Only write buffers should have to be drained. Though
 281  * this may be different depending on platform......
 282  */
 283 #define brcmf_dma_flush(addr, len)
 284 #define brcmf_dma_invalidate_cache(addr, len)
 285
 286
 287 static u32
 288 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 289 {
 290         void __iomem *address = devinfo->regs + reg_offset;
 291
 292         return (ioread32(address));
 293 }
 294
 295
 296 static void
 297 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 298                        u32 value)
 299 {
 300         void __iomem *address = devinfo->regs + reg_offset;
 301
 302         iowrite32(value, address);
 303 }
 304
 305
 306 static u8
 307 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 308 {
 309         void __iomem *address = devinfo->tcm + mem_offset;
 310
 311         return (ioread8(address));
 312 }
 313
 314
 315 static u16
 316 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 317 {
 318         void __iomem *address = devinfo->tcm + mem_offset;
 319
 320         return (ioread16(address));
 321 }
 322
 323
 324 static void
 325 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 326                        u16 value)
 327 {
 328         void __iomem *address = devinfo->tcm + mem_offset;
 329
 330         iowrite16(value, address);
 331 }
 332
 333
 334 static u32
 335 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 336 {
 337         void __iomem *address = devinfo->tcm + mem_offset;
 338
 339         return (ioread32(address));
 340 }
 341
 342
 343 static void
 344 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 345                        u32 value)
 346 {
 347         void __iomem *address = devinfo->tcm + mem_offset;
 348
 349         iowrite32(value, address);
 350 }
 351
 352
 353 static u32
 354 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 355 {
 356         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 357
 358         return (ioread32(addr));
 359 }
 360
 361
 362 static void
 363 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 364                        u32 value)
 365 {
 366         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 367
 368         iowrite32(value, addr);
 369 }
 370
 371
 372 static void
 373 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 374                           void *srcaddr, u32 len)
 375 {
 376         void __iomem *address = devinfo->tcm + mem_offset;
 377         __le32 *src32;
 378         __le16 *src16;
 379         u8 *src8;
 380
 381         if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
 382                 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
 383                         src8 = (u8 *)srcaddr;
 384                         while (len) {
 385                                 iowrite8(*src8, address);
 386                                 address++;
 387                                 src8++;
 388                                 len--;
 389                         }
 390                 } else {
 391                         len = len / 2;
 392                         src16 = (__le16 *)srcaddr;
 393                         while (len) {
 394                                 iowrite16(le16_to_cpu(*src16), address);
 395                                 address += 2;
 396                                 src16++;
 397                                 len--;
 398                         }
 399                 }
 400         } else {
 401                 len = len / 4;
 402                 src32 = (__le32 *)srcaddr;
 403                 while (len) {
 404                         iowrite32(le32_to_cpu(*src32), address);
 405                         address += 4;
 406                         src32++;
 407                         len--;
 408                 }
 409         }
 410 }
 411
 412
 413 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 414                 CHIPCREGOFFS(reg), value)
 415
 416
 417 static void
 418 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 419 {
 420         const struct pci_dev *pdev = devinfo->pdev;
 421         struct brcmf_core *core;
 422         u32 bar0_win;
 423
 424         core = brcmf_chip_get_core(devinfo->ci, coreid);
 425         if (core) {
 426                 bar0_win = core->base;
 427                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 428                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 429                                           &bar0_win) == 0) {
 430                         if (bar0_win != core->base) {
 431                                 bar0_win = core->base;
 432                                 pci_write_config_dword(pdev,
 433                                                        BRCMF_PCIE_BAR0_WINDOW,
 434                                                        bar0_win);
 435                         }
 436                 }
 437         } else {
 438                 brcmf_err("Unsupported core selected %x\n", coreid);
 439         }
 440 }
 441
 442
 443 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 444 {
 445         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 446                              BRCMF_PCIE_CFGREG_PM_CSR,
 447                              BRCMF_PCIE_CFGREG_MSI_CAP,
 448                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 449                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 450                              BRCMF_PCIE_CFGREG_MSI_DATA,
 451                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 452                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 453                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 454                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 455                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 456         u32 i;
 457         u32 val;
 458         u32 lsc;
 459
 460         if (!devinfo->ci)
 461                 return;
 462
 463         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 464         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 465                                BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
 466         lsc = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 467         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 468         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, val);
 469
 470         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 471         WRITECC32(devinfo, watchdog, 4);
 472         msleep(100);
 473
 474         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 475         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 476                                BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
 477         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, lsc);
 478
 479         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 480         for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 481                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 482                                        cfg_offset[i]);
 483                 val = brcmf_pcie_read_reg32(devinfo,
 484                                             BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 485                 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 486                           cfg_offset[i], val);
 487                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 488                                        val);
 489         }
 490 }
 491
 492
 493 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 494 {
 495         u32 config;
 496
 497         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 498         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0)
 499                 brcmf_pcie_reset_device(devinfo);
 500         /* BAR1 window may not be sized properly */
 501         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 502         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 503         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 504         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 505
 506         device_wakeup_enable(&devinfo->pdev->dev);
 507 }
 508
 509
 510 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 511 {
 512         brcmf_chip_enter_download(devinfo->ci);
 513
 514         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 515                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 516                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 517                                        5);
 518                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 519                                        0);
 520                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 521                                        7);
 522                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 523                                        0);
 524         }
 525         return 0;
 526 }
 527
 528
 529 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 530                                           u32 resetintr)
 531 {
 532         struct brcmf_core *core;
 533
 534         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 535                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 536                 brcmf_chip_resetcore(core, 0, 0, 0);
 537         }
 538
 539         return !brcmf_chip_exit_download(devinfo->ci, resetintr);
 540 }
 541
 542
 543 static int
 544 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 545 {
 546         struct brcmf_pcie_shared_info *shared;
 547         u32 addr;
 548         u32 cur_htod_mb_data;
 549         u32 i;
 550
 551         shared = &devinfo->shared;
 552         addr = shared->htod_mb_data_addr;
 553         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 554
 555         if (cur_htod_mb_data != 0)
 556                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 557                           cur_htod_mb_data);
 558
 559         i = 0;
 560         while (cur_htod_mb_data != 0) {
 561                 msleep(10);
 562                 i++;
 563                 if (i > 100)
 564                         return -EIO;
 565                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 566         }
 567
 568         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 569         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 570         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 571
 572         return 0;
 573 }
 574
 575
 576 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 577 {
 578         struct brcmf_pcie_shared_info *shared;
 579         u32 addr;
 580         u32 dtoh_mb_data;
 581
 582         shared = &devinfo->shared;
 583         addr = shared->dtoh_mb_data_addr;
 584         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 585
 586         if (!dtoh_mb_data)
 587                 return;
 588
 589         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 590
 591         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 592         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 593                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 594                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 595                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 596         }
 597         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 598                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 599         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 600                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 601                 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
 602                         devinfo->mbdata_completed = true;
 603                         wake_up(&devinfo->mbdata_resp_wait);
 604                 }
 605         }
 606 }
 607
 608
 609 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 610 {
 611         struct brcmf_pcie_shared_info *shared;
 612         struct brcmf_pcie_console *console;
 613         u32 addr;
 614
 615         shared = &devinfo->shared;
 616         console = &shared->console;
 617         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 618         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 619
 620         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 621         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 622         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 623         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 624
 625         brcmf_dbg(PCIE, "Console: base %x, buf %x, size %d\n",
 626                   console->base_addr, console->buf_addr, console->bufsize);
 627 }
 628
 629
 630 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 631 {
 632         struct brcmf_pcie_console *console;
 633         u32 addr;
 634         u8 ch;
 635         u32 newidx;
 636
 637         console = &devinfo->shared.console;
 638         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 639         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 640         while (newidx != console->read_idx) {
 641                 addr = console->buf_addr + console->read_idx;
 642                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 643                 console->read_idx++;
 644                 if (console->read_idx == console->bufsize)
 645                         console->read_idx = 0;
 646                 if (ch == '\r')
 647                         continue;
 648                 console->log_str[console->log_idx] = ch;
 649                 console->log_idx++;
 650                 if ((ch != '\n') &&
 651                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 652                         ch = '\n';
 653                         console->log_str[console->log_idx] = ch;
 654                         console->log_idx++;
 655                 }
 656
 657                 if (ch == '\n') {
 658                         console->log_str[console->log_idx] = 0;
 659                         brcmf_dbg(PCIE, "CONSOLE: %s\n", console->log_str);
 660                         console->log_idx = 0;
 661                 }
 662         }
 663 }
 664
 665
 666 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
 667 {
 668         u32 reg_value;
 669
 670         brcmf_dbg(PCIE, "RING !\n");
 671         reg_value = brcmf_pcie_read_reg32(devinfo,
 672                                           BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 673         reg_value |= BRCMF_PCIE2_INTB;
 674         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 675                                reg_value);
 676 }
 677
 678
 679 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
 680 {
 681         brcmf_dbg(PCIE, "RING !\n");
 682         /* Any arbitrary value will do, lets use 1 */
 683         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 684 }
 685
 686
 687 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 688 {
 689         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 690                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 691                                        0);
 692         else
 693                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 694                                        0);
 695 }
 696
 697
 698 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 699 {
 700         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 701                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 702                                        BRCMF_PCIE_INT_DEF);
 703         else
 704                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 705                                        BRCMF_PCIE_MB_INT_D2H_DB |
 706                                        BRCMF_PCIE_MB_INT_FN0_0 |
 707                                        BRCMF_PCIE_MB_INT_FN0_1);
 708 }
 709
 710
 711 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
 712 {
 713         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 714         u32 status;
 715
 716         status = 0;
 717         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 718         if (status) {
 719                 brcmf_pcie_intr_disable(devinfo);
 720                 brcmf_dbg(PCIE, "Enter\n");
 721                 return IRQ_WAKE_THREAD;
 722         }
 723         return IRQ_NONE;
 724 }
 725
 726
 727 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
 728 {
 729         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 730
 731         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 732                 brcmf_pcie_intr_disable(devinfo);
 733                 brcmf_dbg(PCIE, "Enter\n");
 734                 return IRQ_WAKE_THREAD;
 735         }
 736         return IRQ_NONE;
 737 }
 738
 739
 740 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
 741 {
 742         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 743         const struct pci_dev *pdev = devinfo->pdev;
 744         u32 status;
 745
 746         devinfo->in_irq = true;
 747         status = 0;
 748         pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 749         brcmf_dbg(PCIE, "Enter %x\n", status);
 750         if (status) {
 751                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 752                 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 753                         brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
 754         }
 755         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 756                 brcmf_pcie_intr_enable(devinfo);
 757         devinfo->in_irq = false;
 758         return IRQ_HANDLED;
 759 }
 760
 761
 762 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
 763 {
 764         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 765         u32 status;
 766
 767         devinfo->in_irq = true;
 768         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 769         brcmf_dbg(PCIE, "Enter %x\n", status);
 770         if (status) {
 771                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 772                                        status);
 773                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 774                               BRCMF_PCIE_MB_INT_FN0_1))
 775                         brcmf_pcie_handle_mb_data(devinfo);
 776                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 777                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 778                                 brcmf_proto_msgbuf_rx_trigger(
 779                                                         &devinfo->pdev->dev);
 780                 }
 781         }
 782         brcmf_pcie_bus_console_read(devinfo);
 783         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 784                 brcmf_pcie_intr_enable(devinfo);
 785         devinfo->in_irq = false;
 786         return IRQ_HANDLED;
 787 }
 788
 789
 790 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 791 {
 792         struct pci_dev *pdev;
 793
 794         pdev = devinfo->pdev;
 795
 796         brcmf_pcie_intr_disable(devinfo);
 797
 798         brcmf_dbg(PCIE, "Enter\n");
 799         /* is it a v1 or v2 implementation */
 800         devinfo->irq_requested = false;
 801         pci_enable_msi(pdev);
 802         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 803                 if (request_threaded_irq(pdev->irq,
 804                                          brcmf_pcie_quick_check_isr_v1,
 805                                          brcmf_pcie_isr_thread_v1,
 806                                          IRQF_SHARED, "brcmf_pcie_intr",
 807                                          devinfo)) {
 808                         pci_disable_msi(pdev);
 809                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 810                         return -EIO;
 811                 }
 812         } else {
 813                 if (request_threaded_irq(pdev->irq,
 814                                          brcmf_pcie_quick_check_isr_v2,
 815                                          brcmf_pcie_isr_thread_v2,
 816                                          IRQF_SHARED, "brcmf_pcie_intr",
 817                                          devinfo)) {
 818                         pci_disable_msi(pdev);
 819                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 820                         return -EIO;
 821                 }
 822         }
 823         devinfo->irq_requested = true;
 824         devinfo->irq_allocated = true;
 825         return 0;
 826 }
 827
 828
 829 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 830 {
 831         struct pci_dev *pdev;
 832         u32 status;
 833         u32 count;
 834
 835         if (!devinfo->irq_allocated)
 836                 return;
 837
 838         pdev = devinfo->pdev;
 839
 840         brcmf_pcie_intr_disable(devinfo);
 841         if (!devinfo->irq_requested)
 842                 return;
 843         devinfo->irq_requested = false;
 844         free_irq(pdev->irq, devinfo);
 845         pci_disable_msi(pdev);
 846
 847         msleep(50);
 848         count = 0;
 849         while ((devinfo->in_irq) && (count < 20)) {
 850                 msleep(50);
 851                 count++;
 852         }
 853         if (devinfo->in_irq)
 854                 brcmf_err("Still in IRQ (processing) !!!\n");
 855
 856         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 857                 status = 0;
 858                 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 859                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 860         } else {
 861                 status = brcmf_pcie_read_reg32(devinfo,
 862                                                BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 863                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 864                                        status);
 865         }
 866         devinfo->irq_allocated = false;
 867 }
 868
 869
 870 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 871 {
 872         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 873         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 874         struct brcmf_commonring *commonring = &ring->commonring;
 875
 876         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 877                 return -EIO;
 878
 879         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 880                   commonring->w_ptr, ring->id);
 881
 882         brcmf_pcie_write_tcm16(devinfo, ring->r_idx_addr, commonring->r_ptr);
 883
 884         return 0;
 885 }
 886
 887
 888 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 889 {
 890         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 891         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 892         struct brcmf_commonring *commonring = &ring->commonring;
 893
 894         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 895                 return -EIO;
 896
 897         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 898                   commonring->r_ptr, ring->id);
 899
 900         brcmf_pcie_write_tcm16(devinfo, ring->w_idx_addr, commonring->w_ptr);
 901
 902         return 0;
 903 }
 904
 905
 906 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 907 {
 908         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 909         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 910
 911         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 912                 return -EIO;
 913
 914         devinfo->ringbell(devinfo);
 915
 916         return 0;
 917 }
 918
 919
 920 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 921 {
 922         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 923         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 924         struct brcmf_commonring *commonring = &ring->commonring;
 925
 926         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 927                 return -EIO;
 928
 929         commonring->r_ptr = brcmf_pcie_read_tcm16(devinfo, ring->r_idx_addr);
 930
 931         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 932                   commonring->w_ptr, ring->id);
 933
 934         return 0;
 935 }
 936
 937
 938 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
 939 {
 940         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 941         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 942         struct brcmf_commonring *commonring = &ring->commonring;
 943
 944         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 945                 return -EIO;
 946
 947         commonring->w_ptr = brcmf_pcie_read_tcm16(devinfo, ring->w_idx_addr);
 948
 949         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 950                   commonring->r_ptr, ring->id);
 951
 952         return 0;
 953 }
 954
 955
 956 static void *
 957 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
 958                                      u32 size, u32 tcm_dma_phys_addr,
 959                                      dma_addr_t *dma_handle)
 960 {
 961         void *ring;
 962         long long address;
 963
 964         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
 965                                   GFP_KERNEL);
 966         if (!ring)
 967                 return NULL;
 968
 969         address = (long long)(long)*dma_handle;
 970         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
 971                                address & 0xffffffff);
 972         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
 973
 974         memset(ring, 0, size);
 975
 976         return (ring);
 977 }
 978
 979
 980 static struct brcmf_pcie_ringbuf *
 981 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
 982                               u32 tcm_ring_phys_addr)
 983 {
 984         void *dma_buf;
 985         dma_addr_t dma_handle;
 986         struct brcmf_pcie_ringbuf *ring;
 987         u32 size;
 988         u32 addr;
 989
 990         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
 991         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
 992                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
 993                         &dma_handle);
 994         if (!dma_buf)
 995                 return NULL;
 996
 997         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
 998         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
 999         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1000         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
1001
1002         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1003         if (!ring) {
1004                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1005                                   dma_handle);
1006                 return NULL;
1007         }
1008         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1009                                 brcmf_ring_itemsize[ring_id], dma_buf);
1010         ring->dma_handle = dma_handle;
1011         ring->devinfo = devinfo;
1012         brcmf_commonring_register_cb(&ring->commonring,
1013                                      brcmf_pcie_ring_mb_ring_bell,
1014                                      brcmf_pcie_ring_mb_update_rptr,
1015                                      brcmf_pcie_ring_mb_update_wptr,
1016                                      brcmf_pcie_ring_mb_write_rptr,
1017                                      brcmf_pcie_ring_mb_write_wptr, ring);
1018
1019         return (ring);
1020 }
1021
1022
1023 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1024                                           struct brcmf_pcie_ringbuf *ring)
1025 {
1026         void *dma_buf;
1027         u32 size;
1028
1029         if (!ring)
1030                 return;
1031
1032         dma_buf = ring->commonring.buf_addr;
1033         if (dma_buf) {
1034                 size = ring->commonring.depth * ring->commonring.item_len;
1035                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1036         }
1037         kfree(ring);
1038 }
1039
1040
1041 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1042 {
1043         u32 i;
1044
1045         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1046                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1047                                               devinfo->shared.commonrings[i]);
1048                 devinfo->shared.commonrings[i] = NULL;
1049         }
1050         kfree(devinfo->shared.flowrings);
1051         devinfo->shared.flowrings = NULL;
1052 }
1053
1054
1055 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1056 {
1057         struct brcmf_pcie_ringbuf *ring;
1058         struct brcmf_pcie_ringbuf *rings;
1059         u32 ring_addr;
1060         u32 d2h_w_idx_ptr;
1061         u32 d2h_r_idx_ptr;
1062         u32 h2d_w_idx_ptr;
1063         u32 h2d_r_idx_ptr;
1064         u32 addr;
1065         u32 ring_mem_ptr;
1066         u32 i;
1067         u16 max_sub_queues;
1068
1069         ring_addr = devinfo->shared.ring_info_addr;
1070         brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1071
1072         addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1073         d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1074         addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1075         d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1076         addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1077         h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1078         addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1079         h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1080
1081         addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1082         ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1083
1084         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1085                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1086                 if (!ring)
1087                         goto fail;
1088                 ring->w_idx_addr = h2d_w_idx_ptr;
1089                 ring->r_idx_addr = h2d_r_idx_ptr;
1090                 ring->id = i;
1091                 devinfo->shared.commonrings[i] = ring;
1092
1093                 h2d_w_idx_ptr += sizeof(u32);
1094                 h2d_r_idx_ptr += sizeof(u32);
1095                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1096         }
1097
1098         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1099              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1100                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1101                 if (!ring)
1102                         goto fail;
1103                 ring->w_idx_addr = d2h_w_idx_ptr;
1104                 ring->r_idx_addr = d2h_r_idx_ptr;
1105                 ring->id = i;
1106                 devinfo->shared.commonrings[i] = ring;
1107
1108                 d2h_w_idx_ptr += sizeof(u32);
1109                 d2h_r_idx_ptr += sizeof(u32);
1110                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1111         }
1112
1113         addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1114         max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1115         devinfo->shared.nrof_flowrings =
1116                         max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1117         rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1118                         GFP_KERNEL);
1119         if (!rings)
1120                 goto fail;
1121
1122         brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1123                   devinfo->shared.nrof_flowrings);
1124
1125         for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1126                 ring = &rings[i];
1127                 ring->devinfo = devinfo;
1128                 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1129                 brcmf_commonring_register_cb(&ring->commonring,
1130                                              brcmf_pcie_ring_mb_ring_bell,
1131                                              brcmf_pcie_ring_mb_update_rptr,
1132                                              brcmf_pcie_ring_mb_update_wptr,
1133                                              brcmf_pcie_ring_mb_write_rptr,
1134                                              brcmf_pcie_ring_mb_write_wptr,
1135                                              ring);
1136                 ring->w_idx_addr = h2d_w_idx_ptr;
1137                 ring->r_idx_addr = h2d_r_idx_ptr;
1138                 h2d_w_idx_ptr += sizeof(u32);
1139                 h2d_r_idx_ptr += sizeof(u32);
1140         }
1141         devinfo->shared.flowrings = rings;
1142
1143         return 0;
1144
1145 fail:
1146         brcmf_err("Allocating commonring buffers failed\n");
1147         brcmf_pcie_release_ringbuffers(devinfo);
1148         return -ENOMEM;
1149 }
1150
1151
1152 static void
1153 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1154 {
1155         if (devinfo->shared.scratch)
1156                 dma_free_coherent(&devinfo->pdev->dev,
1157                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1158                                   devinfo->shared.scratch,
1159                                   devinfo->shared.scratch_dmahandle);
1160         if (devinfo->shared.ringupd)
1161                 dma_free_coherent(&devinfo->pdev->dev,
1162                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1163                                   devinfo->shared.ringupd,
1164                                   devinfo->shared.ringupd_dmahandle);
1165 }
1166
1167 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1168 {
1169         long long address;
1170         u32 addr;
1171
1172         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1173                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1174                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1175         if (!devinfo->shared.scratch)
1176                 goto fail;
1177
1178         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1179         brcmf_dma_flush(devinfo->shared.scratch, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1180
1181         addr = devinfo->shared.tcm_base_address +
1182                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1183         address = (long long)(long)devinfo->shared.scratch_dmahandle;
1184         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1185         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1186         addr = devinfo->shared.tcm_base_address +
1187                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1188         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1189
1190         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1191                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1192                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1193         if (!devinfo->shared.ringupd)
1194                 goto fail;
1195
1196         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1197         brcmf_dma_flush(devinfo->shared.ringupd, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1198
1199         addr = devinfo->shared.tcm_base_address +
1200                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1201         address = (long long)(long)devinfo->shared.ringupd_dmahandle;
1202         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1203         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1204         addr = devinfo->shared.tcm_base_address +
1205                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1206         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1207         return 0;
1208
1209 fail:
1210         brcmf_err("Allocating scratch buffers failed\n");
1211         brcmf_pcie_release_scratchbuffers(devinfo);
1212         return -ENOMEM;
1213 }
1214
1215
1216 static void brcmf_pcie_down(struct device *dev)
1217 {
1218 }
1219
1220
1221 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1222 {
1223         return 0;
1224 }
1225
1226
1227 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1228                                 uint len)
1229 {
1230         return 0;
1231 }
1232
1233
1234 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1235                                 uint len)
1236 {
1237         return 0;
1238 }
1239
1240
1241 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1242 {
1243         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1244         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1245         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1246
1247         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1248         devinfo->wowl_enabled = enabled;
1249         if (enabled)
1250                 device_set_wakeup_enable(&devinfo->pdev->dev, true);
1251         else
1252                 device_set_wakeup_enable(&devinfo->pdev->dev, false);
1253 }
1254
1255
1256 static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1257         .txdata = brcmf_pcie_tx,
1258         .stop = brcmf_pcie_down,
1259         .txctl = brcmf_pcie_tx_ctlpkt,
1260         .rxctl = brcmf_pcie_rx_ctlpkt,
1261         .wowl_config = brcmf_pcie_wowl_config,
1262 };
1263
1264
1265 static int
1266 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1267                                u32 sharedram_addr)
1268 {
1269         struct brcmf_pcie_shared_info *shared;
1270         u32 addr;
1271         u32 version;
1272
1273         shared = &devinfo->shared;
1274         shared->tcm_base_address = sharedram_addr;
1275
1276         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1277         version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1278         brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1279         if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1280             (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1281                 brcmf_err("Unsupported PCIE version %d\n", version);
1282                 return -EINVAL;
1283         }
1284         if (shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT) {
1285                 brcmf_err("Unsupported legacy TX mode 0x%x\n",
1286                           shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT);
1287                 return -EINVAL;
1288         }
1289
1290         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1291         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1292         if (shared->max_rxbufpost == 0)
1293                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1294
1295         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1296         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1297
1298         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1299         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1300
1301         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1302         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1303
1304         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1305         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1306
1307         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1308                   shared->max_rxbufpost, shared->rx_dataoffset);
1309
1310         brcmf_pcie_bus_console_init(devinfo);
1311
1312         return 0;
1313 }
1314
1315
1316 static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1317 {
1318         char *fw_name;
1319         char *nvram_name;
1320         uint fw_len, nv_len;
1321         char end;
1322
1323         brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1324                   devinfo->ci->chiprev);
1325
1326         switch (devinfo->ci->chip) {
1327         case BRCM_CC_43602_CHIP_ID:
1328                 fw_name = BRCMF_PCIE_43602_FW_NAME;
1329                 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1330                 break;
1331         case BRCM_CC_4354_CHIP_ID:
1332                 fw_name = BRCMF_PCIE_4354_FW_NAME;
1333                 nvram_name = BRCMF_PCIE_4354_NVRAM_NAME;
1334                 break;
1335         case BRCM_CC_4356_CHIP_ID:
1336                 fw_name = BRCMF_PCIE_4356_FW_NAME;
1337                 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1338                 break;
1339         case BRCM_CC_43567_CHIP_ID:
1340         case BRCM_CC_43569_CHIP_ID:
1341         case BRCM_CC_43570_CHIP_ID:
1342                 fw_name = BRCMF_PCIE_43570_FW_NAME;
1343                 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1344                 break;
1345         default:
1346                 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1347                 return -ENODEV;
1348         }
1349
1350         fw_len = sizeof(devinfo->fw_name) - 1;
1351         nv_len = sizeof(devinfo->nvram_name) - 1;
1352         /* check if firmware path is provided by module parameter */
1353         if (brcmf_firmware_path[0] != '\0') {
1354                 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1355                 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1356                 fw_len -= strlen(devinfo->fw_name);
1357                 nv_len -= strlen(devinfo->nvram_name);
1358
1359                 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1360                 if (end != '/') {
1361                         strncat(devinfo->fw_name, "/", fw_len);
1362                         strncat(devinfo->nvram_name, "/", nv_len);
1363                         fw_len--;
1364                         nv_len--;
1365                 }
1366         }
1367         strncat(devinfo->fw_name, fw_name, fw_len);
1368         strncat(devinfo->nvram_name, nvram_name, nv_len);
1369
1370         return 0;
1371 }
1372
1373
1374 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1375                                         const struct firmware *fw, void *nvram,
1376                                         u32 nvram_len)
1377 {
1378         u32 sharedram_addr;
1379         u32 sharedram_addr_written;
1380         u32 loop_counter;
1381         int err;
1382         u32 address;
1383         u32 resetintr;
1384
1385         devinfo->ringbell = brcmf_pcie_ringbell_v2;
1386         devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1387
1388         brcmf_dbg(PCIE, "Halt ARM.\n");
1389         err = brcmf_pcie_enter_download_state(devinfo);
1390         if (err)
1391                 return err;
1392
1393         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1394         brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1395                                   (void *)fw->data, fw->size);
1396
1397         resetintr = get_unaligned_le32(fw->data);
1398         release_firmware(fw);
1399
1400         /* reset last 4 bytes of RAM address. to be used for shared
1401          * area. This identifies when FW is running
1402          */
1403         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1404
1405         if (nvram) {
1406                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1407                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1408                           nvram_len;
1409                 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1410                 brcmf_fw_nvram_free(nvram);
1411         } else {
1412                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1413                           devinfo->nvram_name);
1414         }
1415
1416         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1417                                                        devinfo->ci->ramsize -
1418                                                        4);
1419         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1420         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1421         if (err)
1422                 return err;
1423
1424         brcmf_dbg(PCIE, "Wait for FW init\n");
1425         sharedram_addr = sharedram_addr_written;
1426         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1427         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1428                 msleep(50);
1429                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1430                                                        devinfo->ci->ramsize -
1431                                                        4);
1432                 loop_counter--;
1433         }
1434         if (sharedram_addr == sharedram_addr_written) {
1435                 brcmf_err("FW failed to initialize\n");
1436                 return -ENODEV;
1437         }
1438         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1439
1440         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1441 }
1442
1443
1444 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1445 {
1446         struct pci_dev *pdev;
1447         int err;
1448         phys_addr_t  bar0_addr, bar1_addr;
1449         ulong bar1_size;
1450
1451         pdev = devinfo->pdev;
1452
1453         err = pci_enable_device(pdev);
1454         if (err) {
1455                 brcmf_err("pci_enable_device failed err=%d\n", err);
1456                 return err;
1457         }
1458
1459         pci_set_master(pdev);
1460
1461         /* Bar-0 mapped address */
1462         bar0_addr = pci_resource_start(pdev, 0);
1463         /* Bar-1 mapped address */
1464         bar1_addr = pci_resource_start(pdev, 2);
1465         /* read Bar-1 mapped memory range */
1466         bar1_size = pci_resource_len(pdev, 2);
1467         if ((bar1_size == 0) || (bar1_addr == 0)) {
1468                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1469                           bar1_size, (unsigned long long)bar1_addr);
1470                 return -EINVAL;
1471         }
1472
1473         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1474         devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1475         devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1476
1477         if (!devinfo->regs || !devinfo->tcm) {
1478                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1479                           devinfo->tcm);
1480                 return -EINVAL;
1481         }
1482         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1483                   devinfo->regs, (unsigned long long)bar0_addr);
1484         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1485                   devinfo->tcm, (unsigned long long)bar1_addr);
1486
1487         return 0;
1488 }
1489
1490
1491 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1492 {
1493         if (devinfo->tcm)
1494                 iounmap(devinfo->tcm);
1495         if (devinfo->regs)
1496                 iounmap(devinfo->regs);
1497
1498         pci_disable_device(devinfo->pdev);
1499 }
1500
1501
1502 static int brcmf_pcie_attach_bus(struct device *dev)
1503 {
1504         int ret;
1505
1506         /* Attach to the common driver interface */
1507         ret = brcmf_attach(dev);
1508         if (ret) {
1509                 brcmf_err("brcmf_attach failed\n");
1510         } else {
1511                 ret = brcmf_bus_start(dev);
1512                 if (ret)
1513                         brcmf_err("dongle is not responding\n");
1514         }
1515
1516         return ret;
1517 }
1518
1519
1520 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1521 {
1522         u32 ret_addr;
1523
1524         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1525         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1526         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1527
1528         return ret_addr;
1529 }
1530
1531
1532 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1533 {
1534         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1535
1536         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1537         return brcmf_pcie_read_reg32(devinfo, addr);
1538 }
1539
1540
1541 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1542 {
1543         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1544
1545         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1546         brcmf_pcie_write_reg32(devinfo, addr, value);
1547 }
1548
1549
1550 static int brcmf_pcie_buscoreprep(void *ctx)
1551 {
1552         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1553         int err;
1554
1555         err = brcmf_pcie_get_resource(devinfo);
1556         if (err == 0) {
1557                 /* Set CC watchdog to reset all the cores on the chip to bring
1558                  * back dongle to a sane state.
1559                  */
1560                 brcmf_pcie_buscore_write32(ctx, CORE_CC_REG(SI_ENUM_BASE,
1561                                                             watchdog), 4);
1562                 msleep(100);
1563         }
1564
1565         return err;
1566 }
1567
1568
1569 static void brcmf_pcie_buscore_exitdl(void *ctx, struct brcmf_chip *chip,
1570                                       u32 rstvec)
1571 {
1572         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1573
1574         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1575 }
1576
1577
1578 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1579         .prepare = brcmf_pcie_buscoreprep,
1580         .exit_dl = brcmf_pcie_buscore_exitdl,
1581         .read32 = brcmf_pcie_buscore_read32,
1582         .write32 = brcmf_pcie_buscore_write32,
1583 };
1584
1585 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1586                              void *nvram, u32 nvram_len)
1587 {
1588         struct brcmf_bus *bus = dev_get_drvdata(dev);
1589         struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1590         struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1591         struct brcmf_commonring **flowrings;
1592         int ret;
1593         u32 i;
1594
1595         brcmf_pcie_attach(devinfo);
1596
1597         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1598         if (ret)
1599                 goto fail;
1600
1601         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1602
1603         ret = brcmf_pcie_init_ringbuffers(devinfo);
1604         if (ret)
1605                 goto fail;
1606
1607         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1608         if (ret)
1609                 goto fail;
1610
1611         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1612         ret = brcmf_pcie_request_irq(devinfo);
1613         if (ret)
1614                 goto fail;
1615
1616         /* hook the commonrings in the bus structure. */
1617         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1618                 bus->msgbuf->commonrings[i] =
1619                                 &devinfo->shared.commonrings[i]->commonring;
1620
1621         flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(flowrings),
1622                             GFP_KERNEL);
1623         if (!flowrings)
1624                 goto fail;
1625
1626         for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1627                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1628         bus->msgbuf->flowrings = flowrings;
1629
1630         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1631         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1632         bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1633
1634         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1635
1636         brcmf_pcie_intr_enable(devinfo);
1637         if (brcmf_pcie_attach_bus(bus->dev) == 0)
1638                 return;
1639
1640         brcmf_pcie_bus_console_read(devinfo);
1641
1642 fail:
1643         device_release_driver(dev);
1644 }
1645
1646 static int
1647 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1648 {
1649         int ret;
1650         struct brcmf_pciedev_info *devinfo;
1651         struct brcmf_pciedev *pcie_bus_dev;
1652         struct brcmf_bus *bus;
1653
1654         brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
1655
1656         ret = -ENOMEM;
1657         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1658         if (devinfo == NULL)
1659                 return ret;
1660
1661         devinfo->pdev = pdev;
1662         pcie_bus_dev = NULL;
1663         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1664         if (IS_ERR(devinfo->ci)) {
1665                 ret = PTR_ERR(devinfo->ci);
1666                 devinfo->ci = NULL;
1667                 goto fail;
1668         }
1669
1670         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1671         if (pcie_bus_dev == NULL) {
1672                 ret = -ENOMEM;
1673                 goto fail;
1674         }
1675
1676         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1677         if (!bus) {
1678                 ret = -ENOMEM;
1679                 goto fail;
1680         }
1681         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1682         if (!bus->msgbuf) {
1683                 ret = -ENOMEM;
1684                 kfree(bus);
1685                 goto fail;
1686         }
1687
1688         /* hook it all together. */
1689         pcie_bus_dev->devinfo = devinfo;
1690         pcie_bus_dev->bus = bus;
1691         bus->dev = &pdev->dev;
1692         bus->bus_priv.pcie = pcie_bus_dev;
1693         bus->ops = &brcmf_pcie_bus_ops;
1694         bus->proto_type = BRCMF_PROTO_MSGBUF;
1695         bus->chip = devinfo->coreid;
1696         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1697         dev_set_drvdata(&pdev->dev, bus);
1698
1699         ret = brcmf_pcie_get_fwnames(devinfo);
1700         if (ret)
1701                 goto fail_bus;
1702
1703         ret = brcmf_fw_get_firmwares(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1704                                                BRCMF_FW_REQ_NV_OPTIONAL,
1705                                      devinfo->fw_name, devinfo->nvram_name,
1706                                      brcmf_pcie_setup);
1707         if (ret == 0)
1708                 return 0;
1709 fail_bus:
1710         kfree(bus->msgbuf);
1711         kfree(bus);
1712 fail:
1713         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1714         brcmf_pcie_release_resource(devinfo);
1715         if (devinfo->ci)
1716                 brcmf_chip_detach(devinfo->ci);
1717         kfree(pcie_bus_dev);
1718         kfree(devinfo);
1719         return ret;
1720 }
1721
1722
1723 static void
1724 brcmf_pcie_remove(struct pci_dev *pdev)
1725 {
1726         struct brcmf_pciedev_info *devinfo;
1727         struct brcmf_bus *bus;
1728
1729         brcmf_dbg(PCIE, "Enter\n");
1730
1731         bus = dev_get_drvdata(&pdev->dev);
1732         if (bus == NULL)
1733                 return;
1734
1735         devinfo = bus->bus_priv.pcie->devinfo;
1736
1737         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1738         if (devinfo->ci)
1739                 brcmf_pcie_intr_disable(devinfo);
1740
1741         brcmf_detach(&pdev->dev);
1742
1743         kfree(bus->bus_priv.pcie);
1744         kfree(bus->msgbuf->flowrings);
1745         kfree(bus->msgbuf);
1746         kfree(bus);
1747
1748         brcmf_pcie_release_irq(devinfo);
1749         brcmf_pcie_release_scratchbuffers(devinfo);
1750         brcmf_pcie_release_ringbuffers(devinfo);
1751         brcmf_pcie_reset_device(devinfo);
1752         brcmf_pcie_release_resource(devinfo);
1753
1754         if (devinfo->ci)
1755                 brcmf_chip_detach(devinfo->ci);
1756
1757         kfree(devinfo);
1758         dev_set_drvdata(&pdev->dev, NULL);
1759 }
1760
1761
1762 #ifdef CONFIG_PM
1763
1764
1765 static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1766 {
1767         struct brcmf_pciedev_info *devinfo;
1768         struct brcmf_bus *bus;
1769         int err;
1770
1771         brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1772
1773         bus = dev_get_drvdata(&pdev->dev);
1774         devinfo = bus->bus_priv.pcie->devinfo;
1775
1776         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1777
1778         devinfo->mbdata_completed = false;
1779         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1780
1781         wait_event_timeout(devinfo->mbdata_resp_wait,
1782                            devinfo->mbdata_completed,
1783                            msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1784         if (!devinfo->mbdata_completed) {
1785                 brcmf_err("Timeout on response for entering D3 substate\n");
1786                 return -EIO;
1787         }
1788         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
1789
1790         err = pci_save_state(pdev);
1791         if (err)
1792                 brcmf_err("pci_save_state failed, err=%d\n", err);
1793         if ((err) || (!devinfo->wowl_enabled)) {
1794                 brcmf_chip_detach(devinfo->ci);
1795                 devinfo->ci = NULL;
1796                 brcmf_pcie_remove(pdev);
1797                 return 0;
1798         }
1799
1800         return pci_prepare_to_sleep(pdev);
1801 }
1802
1803 static int brcmf_pcie_resume(struct pci_dev *pdev)
1804 {
1805         struct brcmf_pciedev_info *devinfo;
1806         struct brcmf_bus *bus;
1807         int err;
1808
1809         bus = dev_get_drvdata(&pdev->dev);
1810         brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
1811
1812         err = pci_set_power_state(pdev, PCI_D0);
1813         if (err) {
1814                 brcmf_err("pci_set_power_state failed, err=%d\n", err);
1815                 goto cleanup;
1816         }
1817         pci_restore_state(pdev);
1818         pci_enable_wake(pdev, PCI_D3hot, false);
1819         pci_enable_wake(pdev, PCI_D3cold, false);
1820
1821         /* Check if device is still up and running, if so we are ready */
1822         if (bus) {
1823                 devinfo = bus->bus_priv.pcie->devinfo;
1824                 if (brcmf_pcie_read_reg32(devinfo,
1825                                           BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1826                         if (brcmf_pcie_send_mb_data(devinfo,
1827                                                     BRCMF_H2D_HOST_D0_INFORM))
1828                                 goto cleanup;
1829                         brcmf_dbg(PCIE, "Hot resume, continue....\n");
1830                         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1831                         brcmf_bus_change_state(bus, BRCMF_BUS_DATA);
1832                         brcmf_pcie_intr_enable(devinfo);
1833                         return 0;
1834                 }
1835         }
1836
1837 cleanup:
1838         if (bus) {
1839                 devinfo = bus->bus_priv.pcie->devinfo;
1840                 brcmf_chip_detach(devinfo->ci);
1841                 devinfo->ci = NULL;
1842                 brcmf_pcie_remove(pdev);
1843         }
1844         err = brcmf_pcie_probe(pdev, NULL);
1845         if (err)
1846                 brcmf_err("probe after resume failed, err=%d\n", err);
1847
1848         return err;
1849 }
1850
1851
1852 #endif /* CONFIG_PM */
1853
1854
1855 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1856         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1857
1858 static struct pci_device_id brcmf_pcie_devid_table[] = {
1859         BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_DEVICE_ID),
1860         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1861         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1862         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1863         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1864         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
1865         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
1866         { /* end: all zeroes */ }
1867 };
1868
1869
1870 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1871
1872
1873 static struct pci_driver brcmf_pciedrvr = {
1874         .node = {},
1875         .name = KBUILD_MODNAME,
1876         .id_table = brcmf_pcie_devid_table,
1877         .probe = brcmf_pcie_probe,
1878         .remove = brcmf_pcie_remove,
1879 #ifdef CONFIG_PM
1880         .suspend = brcmf_pcie_suspend,
1881         .resume = brcmf_pcie_resume
1882 #endif /* CONFIG_PM */
1883 };
1884
1885
1886 void brcmf_pcie_register(void)
1887 {
1888         int err;
1889
1890         brcmf_dbg(PCIE, "Enter\n");
1891         err = pci_register_driver(&brcmf_pciedrvr);
1892         if (err)
1893                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
1894 }
1895
1896
1897 void brcmf_pcie_exit(void)
1898 {
1899         brcmf_dbg(PCIE, "Enter\n");
1900         pci_unregister_driver(&brcmf_pciedrvr);
1901 }