2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_ids.h>
27 #include <linux/mmc/sdio_func.h>
28 #include <linux/mmc/card.h>
29 #include <linux/semaphore.h>
30 #include <linux/firmware.h>
31 #include <linux/module.h>
32 #include <linux/bcma/bcma.h>
33 #include <linux/debugfs.h>
34 #include <linux/vmalloc.h>
35 #include <linux/platform_data/brcmfmac-sdio.h>
36 #include <linux/moduleparam.h>
37 #include <asm/unaligned.h>
39 #include <brcmu_wifi.h>
40 #include <brcmu_utils.h>
41 #include <brcm_hw_ids.h>
47 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
48 #define CTL_DONE_TIMEOUT 2000 /* In milli second */
52 #define BRCMF_TRAP_INFO_SIZE 80
54 #define CBUF_LEN (128)
56 /* Device console log buffer state */
57 #define CONSOLE_BUFFER_MAX 2024
60 __le32 buf; /* Can't be pointer on (64-bit) hosts */
63 char *_buf_compat; /* Redundant pointer for backward compat. */
68 * When there is no UART (e.g. Quickturn),
69 * the host should write a complete
70 * input line directly into cbuf and then write
71 * the length into vcons_in.
72 * This may also be used when there is a real UART
73 * (at risk of conflicting with
74 * the real UART). vcons_out is currently unused.
79 /* Output (logging) buffer
80 * Console output is written to a ring buffer log_buf at index log_idx.
81 * The host may read the output when it sees log_idx advance.
82 * Output will be lost if the output wraps around faster than the host
85 struct rte_log_le log_le;
87 /* Console input line buffer
88 * Characters are read one at a time into cbuf
89 * until <CR> is received, then
90 * the buffer is processed as a command line.
91 * Also used for virtual UART.
98 #include <chipcommon.h>
102 #include "tracepoint.h"
104 #define TXQLEN 2048 /* bulk tx queue length */
105 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
106 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
109 #define TXRETRIES 2 /* # of retries for tx frames */
111 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
114 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
117 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
119 #define MEMBLOCK 2048 /* Block size used for downloading
121 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
122 biggest possible glom */
124 #define BRCMF_FIRSTREAD (1 << 6)
127 /* SBSDIO_DEVICE_CTL */
129 /* 1: device will assert busy signal when receiving CMD53 */
130 #define SBSDIO_DEVCTL_SETBUSY 0x01
131 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
132 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
133 /* 1: mask all interrupts to host except the chipActive (rev 8) */
134 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
135 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
136 * sdio bus power cycle to clear (rev 9) */
137 #define SBSDIO_DEVCTL_PADS_ISO 0x08
138 /* Force SD->SB reset mapping (rev 11) */
139 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
140 /* Determined by CoreControl bit */
141 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
142 /* Force backplane reset */
143 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
144 /* Force no backplane reset */
145 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
147 /* direct(mapped) cis space */
149 /* MAPPED common CIS address */
150 #define SBSDIO_CIS_BASE_COMMON 0x1000
151 /* maximum bytes in one CIS */
152 #define SBSDIO_CIS_SIZE_LIMIT 0x200
153 /* cis offset addr is < 17 bits */
154 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
156 /* manfid tuple length, include tuple, link bytes */
157 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
159 #define CORE_BUS_REG(base, field) \
160 (base + offsetof(struct sdpcmd_regs, field))
162 /* SDIO function 1 register CHIPCLKCSR */
163 /* Force ALP request to backplane */
164 #define SBSDIO_FORCE_ALP 0x01
165 /* Force HT request to backplane */
166 #define SBSDIO_FORCE_HT 0x02
167 /* Force ILP request to backplane */
168 #define SBSDIO_FORCE_ILP 0x04
169 /* Make ALP ready (power up xtal) */
170 #define SBSDIO_ALP_AVAIL_REQ 0x08
171 /* Make HT ready (power up PLL) */
172 #define SBSDIO_HT_AVAIL_REQ 0x10
173 /* Squelch clock requests from HW */
174 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
175 /* Status: ALP is ready */
176 #define SBSDIO_ALP_AVAIL 0x40
177 /* Status: HT is ready */
178 #define SBSDIO_HT_AVAIL 0x80
179 #define SBSDIO_CSR_MASK 0x1F
180 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
181 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
182 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
183 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
184 #define SBSDIO_CLKAV(regval, alponly) \
185 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
188 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
189 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
190 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
191 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
192 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
193 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
194 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
195 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
196 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
197 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
198 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
199 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
200 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
201 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
202 #define I_PC (1 << 10) /* descriptor error */
203 #define I_PD (1 << 11) /* data error */
204 #define I_DE (1 << 12) /* Descriptor protocol Error */
205 #define I_RU (1 << 13) /* Receive descriptor Underflow */
206 #define I_RO (1 << 14) /* Receive fifo Overflow */
207 #define I_XU (1 << 15) /* Transmit fifo Underflow */
208 #define I_RI (1 << 16) /* Receive Interrupt */
209 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
210 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
211 #define I_XI (1 << 24) /* Transmit Interrupt */
212 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
213 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
214 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
215 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
216 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
217 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
218 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
219 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
220 #define I_DMA (I_RI | I_XI | I_ERRORS)
223 #define CC_CISRDY (1 << 0) /* CIS Ready */
224 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
225 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
226 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
227 #define CC_XMTDATAAVAIL_MODE (1 << 4)
228 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
231 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
232 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
233 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
234 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
237 * Software allocation of To SB Mailbox resources
240 /* tosbmailbox bits corresponding to intstatus bits */
241 #define SMB_NAK (1 << 0) /* Frame NAK */
242 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
243 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
244 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
246 /* tosbmailboxdata */
247 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
250 * Software allocation of To Host Mailbox resources
254 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
255 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
256 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
257 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
259 /* tohostmailboxdata */
260 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
261 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
262 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
263 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
265 #define HMB_DATA_FCDATA_MASK 0xff000000
266 #define HMB_DATA_FCDATA_SHIFT 24
268 #define HMB_DATA_VERSION_MASK 0x00ff0000
269 #define HMB_DATA_VERSION_SHIFT 16
272 * Software-defined protocol header
275 /* Current protocol version */
276 #define SDPCM_PROT_VERSION 4
279 * Shared structure between dongle and the host.
280 * The structure contains pointers to trap or assert information.
282 #define SDPCM_SHARED_VERSION 0x0003
283 #define SDPCM_SHARED_VERSION_MASK 0x00FF
284 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
285 #define SDPCM_SHARED_ASSERT 0x0200
286 #define SDPCM_SHARED_TRAP 0x0400
288 /* Space for header read, limit for data packets */
289 #define MAX_HDR_READ (1 << 6)
290 #define MAX_RX_DATASZ 2048
292 /* Bump up limit on waiting for HT to account for first startup;
293 * if the image is doing a CRC calculation before programming the PMU
294 * for HT availability, it could take a couple hundred ms more, so
295 * max out at a 1 second (1000000us).
297 #undef PMU_MAX_TRANSITION_DLY
298 #define PMU_MAX_TRANSITION_DLY 1000000
300 /* Value for ChipClockCSR during initial setup */
301 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
302 SBSDIO_ALP_AVAIL_REQ)
304 /* Flags for SDH calls */
305 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
307 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
310 #define BRCMF_IDLE_INTERVAL 1
312 #define KSO_WAIT_US 50
313 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
316 * Conversion of 802.1D priority to precedence level
318 static uint prio2prec(u32 prio)
320 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
325 /* Device console log buffer state */
326 struct brcmf_console {
327 uint count; /* Poll interval msec counter */
328 uint log_addr; /* Log struct address (fixed) */
329 struct rte_log_le log_le; /* Log struct (host copy) */
330 uint bufsize; /* Size of log buffer */
331 u8 *buf; /* Log buffer (host copy) */
332 uint last; /* Last buffer read index */
335 struct brcmf_trap_info {
349 __le32 r9; /* sb/v6 */
350 __le32 r10; /* sl/v7 */
351 __le32 r11; /* fp/v8 */
359 struct sdpcm_shared {
363 u32 assert_file_addr;
365 u32 console_addr; /* Address of struct rte_console */
371 struct sdpcm_shared_le {
374 __le32 assert_exp_addr;
375 __le32 assert_file_addr;
377 __le32 console_addr; /* Address of struct rte_console */
378 __le32 msgtrace_addr;
383 /* dongle SDIO bus specific header info */
384 struct brcmf_sdio_hdrinfo {
396 * hold counter variables
398 struct brcmf_sdio_count {
399 uint intrcount; /* Count of device interrupt callbacks */
400 uint lastintrs; /* Count as of last watchdog timer */
401 uint pollcnt; /* Count of active polls */
402 uint regfails; /* Count of R_REG failures */
403 uint tx_sderrs; /* Count of tx attempts with sd errors */
404 uint fcqueued; /* Tx packets that got queued */
405 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
406 uint rx_toolong; /* Receive frames too long to receive */
407 uint rxc_errors; /* SDIO errors when reading control frames */
408 uint rx_hdrfail; /* SDIO errors on header reads */
409 uint rx_badhdr; /* Bad received headers (roosync?) */
410 uint rx_badseq; /* Mismatched rx sequence number */
411 uint fc_rcvd; /* Number of flow-control events received */
412 uint fc_xoff; /* Number which turned on flow-control */
413 uint fc_xon; /* Number which turned off flow-control */
414 uint rxglomfail; /* Failed deglom attempts */
415 uint rxglomframes; /* Number of glom frames (superframes) */
416 uint rxglompkts; /* Number of packets from glom frames */
417 uint f2rxhdrs; /* Number of header reads */
418 uint f2rxdata; /* Number of frame data reads */
419 uint f2txdata; /* Number of f2 frame writes */
420 uint f1regdata; /* Number of f1 register accesses */
421 uint tickcnt; /* Number of watchdog been schedule */
422 ulong tx_ctlerrs; /* Err of sending ctrl frames */
423 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
424 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
425 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
426 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
429 /* misc chip info needed by some of the routines */
430 /* Private data for SDIO bus interaction */
432 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
433 struct brcmf_chip *ci; /* Chip info struct */
435 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
437 u32 hostintmask; /* Copy of Host Interrupt Mask */
438 atomic_t intstatus; /* Intstatus bits (events) pending */
439 atomic_t fcstate; /* State of dongle flow-control */
441 uint blocksize; /* Block size of SDIO transfers */
442 uint roundup; /* Max roundup limit */
444 struct pktq txq; /* Queue length used for flow-control */
445 u8 flowcontrol; /* per prio flow control bitmask */
446 u8 tx_seq; /* Transmit sequence number (next) */
447 u8 tx_max; /* Maximum transmit sequence allowed */
449 u8 *hdrbuf; /* buffer for handling rx frame */
450 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
451 u8 rx_seq; /* Receive sequence number (expected) */
452 struct brcmf_sdio_hdrinfo cur_read;
453 /* info of current read frame */
454 bool rxskip; /* Skip receive (awaiting NAK ACK) */
455 bool rxpending; /* Data frame pending in dongle */
457 uint rxbound; /* Rx frames to read before resched */
458 uint txbound; /* Tx frames to send before resched */
461 struct sk_buff *glomd; /* Packet containing glomming descriptor */
462 struct sk_buff_head glom; /* Packet list for glommed superframe */
463 uint glomerr; /* Glom packet read errors */
465 u8 *rxbuf; /* Buffer for receiving control packets */
466 uint rxblen; /* Allocated length of rxbuf */
467 u8 *rxctl; /* Aligned pointer into rxbuf */
468 u8 *rxctl_orig; /* pointer for freeing rxctl */
469 uint rxlen; /* Length of valid data in buffer */
470 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
472 u8 sdpcm_ver; /* Bus protocol reported by dongle */
474 bool intr; /* Use interrupts */
475 bool poll; /* Use polling */
476 atomic_t ipend; /* Device interrupt is pending */
477 uint spurious; /* Count of spurious interrupts */
478 uint pollrate; /* Ticks between device polls */
479 uint polltick; /* Tick counter */
482 uint console_interval;
483 struct brcmf_console console; /* Console output polling support */
484 uint console_addr; /* Console address from shared struct */
487 uint clkstate; /* State of sd and backplane clock(s) */
488 bool activity; /* Activity flag for clock down */
489 s32 idletime; /* Control for activity timeout */
490 s32 idlecount; /* Activity timeout counter */
491 s32 idleclock; /* How to set bus driver when idle */
492 bool rxflow_mode; /* Rx flow control mode */
493 bool rxflow; /* Is rx flow control on */
494 bool alp_only; /* Don't use HT clock (ALP only) */
498 bool ctrl_frame_stat;
501 spinlock_t txq_lock; /* protect bus->txq */
502 wait_queue_head_t ctrl_wait;
503 wait_queue_head_t dcmd_resp_wait;
505 struct timer_list timer;
506 struct completion watchdog_wait;
507 struct task_struct *watchdog_tsk;
511 struct workqueue_struct *brcmf_wq;
512 struct work_struct datawork;
515 bool txoff; /* Transmit flow-controlled */
516 struct brcmf_sdio_count sdcnt;
517 bool sr_enabled; /* SaveRestore enabled */
520 u8 tx_hdrlen; /* sdio bus header length for tx packet */
521 bool txglom; /* host tx glomming enable flag */
522 u16 head_align; /* buffer pointer alignment */
523 u16 sgentry_align; /* scatter-gather buffer alignment */
529 #define CLK_PENDING 2
533 static int qcount[NUMPRIO];
536 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
538 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
540 /* Retry count for register access failures */
541 static const uint retry_limit = 2;
543 /* Limit on rounding up frames */
544 static const uint max_roundup = 512;
548 enum brcmf_sdio_frmtype {
549 BRCMF_SDIO_FT_NORMAL,
554 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
556 /* SDIO Pad drive strength to select value mappings */
557 struct sdiod_drive_str {
558 u8 strength; /* Pad Drive Strength in mA */
559 u8 sel; /* Chip-specific select value */
562 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
563 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
574 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
575 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
585 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
586 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
592 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
593 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
600 #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin"
601 #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt"
602 #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin"
603 #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt"
604 #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin"
605 #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt"
606 #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin"
607 #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt"
608 #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin"
609 #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
610 #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
611 #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
612 #define BCM43340_FIRMWARE_NAME "brcm/brcmfmac43340-sdio.bin"
613 #define BCM43340_NVRAM_NAME "brcm/brcmfmac43340-sdio.txt"
614 #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
615 #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
616 #define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin"
617 #define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt"
618 #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
619 #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
620 #define BCM4354_FIRMWARE_NAME "brcm/brcmfmac4354-sdio.bin"
621 #define BCM4354_NVRAM_NAME "brcm/brcmfmac4354-sdio.txt"
623 MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME);
624 MODULE_FIRMWARE(BCM43143_NVRAM_NAME);
625 MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME);
626 MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME);
627 MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME);
628 MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME);
629 MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME);
630 MODULE_FIRMWARE(BCM4329_NVRAM_NAME);
631 MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
632 MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
633 MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
634 MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
635 MODULE_FIRMWARE(BCM43340_FIRMWARE_NAME);
636 MODULE_FIRMWARE(BCM43340_NVRAM_NAME);
637 MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
638 MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
639 MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME);
640 MODULE_FIRMWARE(BCM43362_NVRAM_NAME);
641 MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
642 MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
643 MODULE_FIRMWARE(BCM4354_FIRMWARE_NAME);
644 MODULE_FIRMWARE(BCM4354_NVRAM_NAME);
646 struct brcmf_firmware_names {
653 enum brcmf_firmware_type {
658 #define BRCMF_FIRMWARE_NVRAM(name) \
659 name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
661 static const struct brcmf_firmware_names brcmf_fwname_data[] = {
662 { BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
663 { BRCM_CC_43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
664 { BRCM_CC_43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
665 { BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
666 { BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
667 { BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
668 { BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43340) },
669 { BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
670 { BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
671 { BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) },
672 { BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) }
675 static int brcmf_sdio_get_fwnames(struct brcmf_chip *ci,
676 struct brcmf_sdio_dev *sdiodev)
681 for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
682 if (brcmf_fwname_data[i].chipid == ci->chip &&
683 brcmf_fwname_data[i].revmsk & BIT(ci->chiprev))
687 if (i == ARRAY_SIZE(brcmf_fwname_data)) {
688 brcmf_err("Unknown chipid %d [%d]\n", ci->chip, ci->chiprev);
692 /* check if firmware path is provided by module parameter */
693 if (brcmf_firmware_path[0] != '\0') {
694 strlcpy(sdiodev->fw_name, brcmf_firmware_path,
695 sizeof(sdiodev->fw_name));
696 strlcpy(sdiodev->nvram_name, brcmf_firmware_path,
697 sizeof(sdiodev->nvram_name));
699 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
701 strlcat(sdiodev->fw_name, "/",
702 sizeof(sdiodev->fw_name));
703 strlcat(sdiodev->nvram_name, "/",
704 sizeof(sdiodev->nvram_name));
707 strlcat(sdiodev->fw_name, brcmf_fwname_data[i].bin,
708 sizeof(sdiodev->fw_name));
709 strlcat(sdiodev->nvram_name, brcmf_fwname_data[i].nv,
710 sizeof(sdiodev->nvram_name));
715 static void pkt_align(struct sk_buff *p, int len, int align)
718 datalign = (unsigned long)(p->data);
719 datalign = roundup(datalign, (align)) - datalign;
721 skb_pull(p, datalign);
725 /* To check if there's window offered */
726 static bool data_ok(struct brcmf_sdio *bus)
728 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
729 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
733 * Reads a register in the SDIO hardware block. This block occupies a series of
734 * adresses on the 32 bit backplane bus.
736 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
738 struct brcmf_core *core;
741 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
742 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
747 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
749 struct brcmf_core *core;
752 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
753 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
759 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
761 u8 wr_val = 0, rd_val, cmp_val, bmask;
765 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
767 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
768 /* 1st KSO write goes to AOS wake up core if device is asleep */
769 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
773 /* device WAKEUP through KSO:
774 * write bit 0 & read back until
775 * both bits 0 (kso bit) & 1 (dev on status) are set
777 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
778 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
780 usleep_range(2000, 3000);
782 /* Put device to sleep, turn off KSO */
784 /* only check for bit0, bit1(dev on status) may not
785 * get cleared right away
787 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
791 /* reliable KSO bit set/clr:
792 * the sdiod sleep write access is synced to PMU 32khz clk
793 * just one write attempt may fail,
794 * read it back until it matches written value
796 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
798 if (((rd_val & bmask) == cmp_val) && !err)
802 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
804 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
807 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
810 if (try_cnt > MAX_KSO_ATTEMPTS)
811 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
816 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
818 /* Turn backplane clock on or off */
819 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
822 u8 clkctl, clkreq, devctl;
823 unsigned long timeout;
825 brcmf_dbg(SDIO, "Enter\n");
829 if (bus->sr_enabled) {
830 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
835 /* Request HT Avail */
837 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
839 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
842 brcmf_err("HT Avail request error: %d\n", err);
846 /* Check current status */
847 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
848 SBSDIO_FUNC1_CHIPCLKCSR, &err);
850 brcmf_err("HT Avail read error: %d\n", err);
854 /* Go to pending and await interrupt if appropriate */
855 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
856 /* Allow only clock-available interrupt */
857 devctl = brcmf_sdiod_regrb(bus->sdiodev,
858 SBSDIO_DEVICE_CTL, &err);
860 brcmf_err("Devctl error setting CA: %d\n",
865 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
866 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
868 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
869 bus->clkstate = CLK_PENDING;
872 } else if (bus->clkstate == CLK_PENDING) {
873 /* Cancel CA-only interrupt filter */
874 devctl = brcmf_sdiod_regrb(bus->sdiodev,
875 SBSDIO_DEVICE_CTL, &err);
876 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
877 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
881 /* Otherwise, wait here (polling) for HT Avail */
883 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
884 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
885 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
886 SBSDIO_FUNC1_CHIPCLKCSR,
888 if (time_after(jiffies, timeout))
891 usleep_range(5000, 10000);
894 brcmf_err("HT Avail request error: %d\n", err);
897 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
898 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
899 PMU_MAX_TRANSITION_DLY, clkctl);
903 /* Mark clock available */
904 bus->clkstate = CLK_AVAIL;
905 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
908 if (!bus->alp_only) {
909 if (SBSDIO_ALPONLY(clkctl))
910 brcmf_err("HT Clock should be on\n");
912 #endif /* defined (DEBUG) */
917 if (bus->clkstate == CLK_PENDING) {
918 /* Cancel CA-only interrupt filter */
919 devctl = brcmf_sdiod_regrb(bus->sdiodev,
920 SBSDIO_DEVICE_CTL, &err);
921 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
922 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
926 bus->clkstate = CLK_SDONLY;
927 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
929 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
931 brcmf_err("Failed access turning clock off: %d\n",
939 /* Change idle/active SD state */
940 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
942 brcmf_dbg(SDIO, "Enter\n");
945 bus->clkstate = CLK_SDONLY;
947 bus->clkstate = CLK_NONE;
952 /* Transition SD and backplane clock readiness */
953 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
956 uint oldstate = bus->clkstate;
959 brcmf_dbg(SDIO, "Enter\n");
961 /* Early exit if we're already there */
962 if (bus->clkstate == target) {
963 if (target == CLK_AVAIL) {
964 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
965 bus->activity = true;
972 /* Make sure SD clock is available */
973 if (bus->clkstate == CLK_NONE)
974 brcmf_sdio_sdclk(bus, true);
975 /* Now request HT Avail on the backplane */
976 brcmf_sdio_htclk(bus, true, pendok);
977 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
978 bus->activity = true;
982 /* Remove HT request, or bring up SD clock */
983 if (bus->clkstate == CLK_NONE)
984 brcmf_sdio_sdclk(bus, true);
985 else if (bus->clkstate == CLK_AVAIL)
986 brcmf_sdio_htclk(bus, false, false);
988 brcmf_err("request for %d -> %d\n",
989 bus->clkstate, target);
990 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
994 /* Make sure to remove HT request */
995 if (bus->clkstate == CLK_AVAIL)
996 brcmf_sdio_htclk(bus, false, false);
997 /* Now remove the SD clock */
998 brcmf_sdio_sdclk(bus, false);
999 brcmf_sdio_wd_timer(bus, 0);
1003 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
1010 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
1015 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
1016 (sleep ? "SLEEP" : "WAKE"),
1017 (bus->sleeping ? "SLEEP" : "WAKE"));
1019 /* If SR is enabled control bus state with KSO */
1020 if (bus->sr_enabled) {
1021 /* Done if we're already in the requested state */
1022 if (sleep == bus->sleeping)
1025 /* Going to sleep */
1027 /* Don't sleep if something is pending */
1028 if (atomic_read(&bus->intstatus) ||
1029 atomic_read(&bus->ipend) > 0 ||
1030 bus->ctrl_frame_stat ||
1031 (!atomic_read(&bus->fcstate) &&
1032 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
1038 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
1039 SBSDIO_FUNC1_CHIPCLKCSR,
1041 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
1042 brcmf_dbg(SDIO, "no clock, set ALP\n");
1043 brcmf_sdiod_regwb(bus->sdiodev,
1044 SBSDIO_FUNC1_CHIPCLKCSR,
1045 SBSDIO_ALP_AVAIL_REQ, &err);
1047 err = brcmf_sdio_kso_control(bus, false);
1048 /* disable watchdog */
1050 brcmf_sdio_wd_timer(bus, 0);
1053 err = brcmf_sdio_kso_control(bus, true);
1056 brcmf_err("error while changing bus sleep state %d\n",
1063 /* control clocks */
1065 if (!bus->sr_enabled)
1066 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
1068 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
1070 bus->sleeping = sleep;
1071 brcmf_dbg(SDIO, "new state %s\n",
1072 (sleep ? "SLEEP" : "WAKE"));
1074 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
1080 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
1082 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
1085 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
1086 struct sdpcm_shared *sh)
1091 struct sdpcm_shared_le sh_le;
1094 shaddr = bus->ci->rambase + bus->ramsize - 4;
1097 * Read last word in socram to determine
1098 * address of sdpcm_shared structure
1100 sdio_claim_host(bus->sdiodev->func[1]);
1101 brcmf_sdio_bus_sleep(bus, false, false);
1102 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4);
1103 sdio_release_host(bus->sdiodev->func[1]);
1107 addr = le32_to_cpu(addr_le);
1109 brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr);
1112 * Check if addr is valid.
1113 * NVRAM length at the end of memory should have been overwritten.
1115 if (!brcmf_sdio_valid_shared_address(addr)) {
1116 brcmf_err("invalid sdpcm_shared address 0x%08X\n",
1121 /* Read hndrte_shared structure */
1122 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1123 sizeof(struct sdpcm_shared_le));
1128 sh->flags = le32_to_cpu(sh_le.flags);
1129 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1130 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1131 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1132 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1133 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1134 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1136 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1137 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1138 SDPCM_SHARED_VERSION,
1139 sh->flags & SDPCM_SHARED_VERSION_MASK);
1146 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1148 struct sdpcm_shared sh;
1150 if (brcmf_sdio_readshared(bus, &sh) == 0)
1151 bus->console_addr = sh.console_addr;
1154 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1159 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1166 brcmf_dbg(SDIO, "Enter\n");
1168 /* Read mailbox data and ack that we did so */
1169 ret = r_sdreg32(bus, &hmb_data,
1170 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1173 w_sdreg32(bus, SMB_INT_ACK,
1174 offsetof(struct sdpcmd_regs, tosbmailbox));
1175 bus->sdcnt.f1regdata += 2;
1177 /* Dongle recomposed rx frames, accept them again */
1178 if (hmb_data & HMB_DATA_NAKHANDLED) {
1179 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1182 brcmf_err("unexpected NAKHANDLED!\n");
1184 bus->rxskip = false;
1185 intstatus |= I_HMB_FRAME_IND;
1189 * DEVREADY does not occur with gSPI.
1191 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1193 (hmb_data & HMB_DATA_VERSION_MASK) >>
1194 HMB_DATA_VERSION_SHIFT;
1195 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1196 brcmf_err("Version mismatch, dongle reports %d, "
1198 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1200 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1204 * Retrieve console state address now that firmware should have
1207 brcmf_sdio_get_console_addr(bus);
1211 * Flow Control has been moved into the RX headers and this out of band
1212 * method isn't used any more.
1213 * remaining backward compatible with older dongles.
1215 if (hmb_data & HMB_DATA_FC) {
1216 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1217 HMB_DATA_FCDATA_SHIFT;
1219 if (fcbits & ~bus->flowcontrol)
1220 bus->sdcnt.fc_xoff++;
1222 if (bus->flowcontrol & ~fcbits)
1223 bus->sdcnt.fc_xon++;
1225 bus->sdcnt.fc_rcvd++;
1226 bus->flowcontrol = fcbits;
1229 /* Shouldn't be any others */
1230 if (hmb_data & ~(HMB_DATA_DEVREADY |
1231 HMB_DATA_NAKHANDLED |
1234 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1235 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1241 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1248 brcmf_err("%sterminate frame%s\n",
1249 abort ? "abort command, " : "",
1250 rtx ? ", send NAK" : "");
1253 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1255 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1257 bus->sdcnt.f1regdata++;
1259 /* Wait until the packet has been flushed (device/FIFO stable) */
1260 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1261 hi = brcmf_sdiod_regrb(bus->sdiodev,
1262 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1263 lo = brcmf_sdiod_regrb(bus->sdiodev,
1264 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1265 bus->sdcnt.f1regdata += 2;
1267 if ((hi == 0) && (lo == 0))
1270 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1271 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1272 lastrbc, (hi << 8) + lo);
1274 lastrbc = (hi << 8) + lo;
1278 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1280 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1284 err = w_sdreg32(bus, SMB_NAK,
1285 offsetof(struct sdpcmd_regs, tosbmailbox));
1287 bus->sdcnt.f1regdata++;
1292 /* Clear partial in any case */
1293 bus->cur_read.len = 0;
1296 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1298 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1301 /* On failure, abort the command and terminate the frame */
1302 brcmf_err("sdio error, abort command and terminate frame\n");
1303 bus->sdcnt.tx_sderrs++;
1305 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1306 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1307 bus->sdcnt.f1regdata++;
1309 for (i = 0; i < 3; i++) {
1310 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1311 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1312 bus->sdcnt.f1regdata += 2;
1313 if ((hi == 0) && (lo == 0))
1318 /* return total length of buffer chain */
1319 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1325 skb_queue_walk(&bus->glom, p)
1330 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1332 struct sk_buff *cur, *next;
1334 skb_queue_walk_safe(&bus->glom, cur, next) {
1335 skb_unlink(cur, &bus->glom);
1336 brcmu_pkt_buf_free_skb(cur);
1341 * brcmfmac sdio bus specific header
1342 * This is the lowest layer header wrapped on the packets transmitted between
1343 * host and WiFi dongle which contains information needed for SDIO core and
1346 * It consists of 3 parts: hardware header, hardware extension header and
1348 * hardware header (frame tag) - 4 bytes
1349 * Byte 0~1: Frame length
1350 * Byte 2~3: Checksum, bit-wise inverse of frame length
1351 * hardware extension header - 8 bytes
1352 * Tx glom mode only, N/A for Rx or normal Tx
1353 * Byte 0~1: Packet length excluding hw frame tag
1355 * Byte 3: Frame flags, bit 0: last frame indication
1356 * Byte 4~5: Reserved
1357 * Byte 6~7: Tail padding length
1358 * software header - 8 bytes
1359 * Byte 0: Rx/Tx sequence number
1360 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1361 * Byte 2: Length of next data frame, reserved for Tx
1362 * Byte 3: Data offset
1363 * Byte 4: Flow control bits, reserved for Tx
1364 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1365 * Byte 6~7: Reserved
1367 #define SDPCM_HWHDR_LEN 4
1368 #define SDPCM_HWEXT_LEN 8
1369 #define SDPCM_SWHDR_LEN 8
1370 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1371 /* software header */
1372 #define SDPCM_SEQ_MASK 0x000000ff
1373 #define SDPCM_SEQ_WRAP 256
1374 #define SDPCM_CHANNEL_MASK 0x00000f00
1375 #define SDPCM_CHANNEL_SHIFT 8
1376 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1377 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1378 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1379 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1380 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1381 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1382 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1383 #define SDPCM_NEXTLEN_SHIFT 16
1384 #define SDPCM_DOFFSET_MASK 0xff000000
1385 #define SDPCM_DOFFSET_SHIFT 24
1386 #define SDPCM_FCMASK_MASK 0x000000ff
1387 #define SDPCM_WINDOW_MASK 0x0000ff00
1388 #define SDPCM_WINDOW_SHIFT 8
1390 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1393 hdrvalue = *(u32 *)swheader;
1394 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1397 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1398 struct brcmf_sdio_hdrinfo *rd,
1399 enum brcmf_sdio_frmtype type)
1402 u8 rx_seq, fc, tx_seq_max;
1405 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1408 len = get_unaligned_le16(header);
1409 checksum = get_unaligned_le16(header + sizeof(u16));
1410 /* All zero means no more to read */
1411 if (!(len | checksum)) {
1412 bus->rxpending = false;
1415 if ((u16)(~(len ^ checksum))) {
1416 brcmf_err("HW header checksum error\n");
1417 bus->sdcnt.rx_badhdr++;
1418 brcmf_sdio_rxfail(bus, false, false);
1421 if (len < SDPCM_HDRLEN) {
1422 brcmf_err("HW header length error\n");
1425 if (type == BRCMF_SDIO_FT_SUPER &&
1426 (roundup(len, bus->blocksize) != rd->len)) {
1427 brcmf_err("HW superframe header length error\n");
1430 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1431 brcmf_err("HW subframe header length error\n");
1436 /* software header */
1437 header += SDPCM_HWHDR_LEN;
1438 swheader = le32_to_cpu(*(__le32 *)header);
1439 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1440 brcmf_err("Glom descriptor found in superframe head\n");
1444 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1445 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1446 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1447 type != BRCMF_SDIO_FT_SUPER) {
1448 brcmf_err("HW header length too long\n");
1449 bus->sdcnt.rx_toolong++;
1450 brcmf_sdio_rxfail(bus, false, false);
1454 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1455 brcmf_err("Wrong channel for superframe\n");
1459 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1460 rd->channel != SDPCM_EVENT_CHANNEL) {
1461 brcmf_err("Wrong channel for subframe\n");
1465 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1466 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1467 brcmf_err("seq %d: bad data offset\n", rx_seq);
1468 bus->sdcnt.rx_badhdr++;
1469 brcmf_sdio_rxfail(bus, false, false);
1473 if (rd->seq_num != rx_seq) {
1474 brcmf_err("seq %d: sequence number error, expect %d\n",
1475 rx_seq, rd->seq_num);
1476 bus->sdcnt.rx_badseq++;
1477 rd->seq_num = rx_seq;
1479 /* no need to check the reset for subframe */
1480 if (type == BRCMF_SDIO_FT_SUB)
1482 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1483 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1484 /* only warm for NON glom packet */
1485 if (rd->channel != SDPCM_GLOM_CHANNEL)
1486 brcmf_err("seq %d: next length error\n", rx_seq);
1489 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1490 fc = swheader & SDPCM_FCMASK_MASK;
1491 if (bus->flowcontrol != fc) {
1492 if (~bus->flowcontrol & fc)
1493 bus->sdcnt.fc_xoff++;
1494 if (bus->flowcontrol & ~fc)
1495 bus->sdcnt.fc_xon++;
1496 bus->sdcnt.fc_rcvd++;
1497 bus->flowcontrol = fc;
1499 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1500 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1501 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1502 tx_seq_max = bus->tx_seq + 2;
1504 bus->tx_max = tx_seq_max;
1509 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1511 *(__le16 *)header = cpu_to_le16(frm_length);
1512 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1515 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1516 struct brcmf_sdio_hdrinfo *hd_info)
1521 brcmf_sdio_update_hwhdr(header, hd_info->len);
1522 hdr_offset = SDPCM_HWHDR_LEN;
1525 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1526 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1527 hdrval = (u16)hd_info->tail_pad << 16;
1528 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1529 hdr_offset += SDPCM_HWEXT_LEN;
1532 hdrval = hd_info->seq_num;
1533 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1535 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1537 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1538 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1539 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1542 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1547 struct sk_buff *pfirst, *pnext;
1552 struct brcmf_sdio_hdrinfo rd_new;
1554 /* If packets, issue read(s) and send up packet chain */
1555 /* Return sequence numbers consumed? */
1557 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1558 bus->glomd, skb_peek(&bus->glom));
1560 /* If there's a descriptor, generate the packet chain */
1562 pfirst = pnext = NULL;
1563 dlen = (u16) (bus->glomd->len);
1564 dptr = bus->glomd->data;
1565 if (!dlen || (dlen & 1)) {
1566 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1571 for (totlen = num = 0; dlen; num++) {
1572 /* Get (and move past) next length */
1573 sublen = get_unaligned_le16(dptr);
1574 dlen -= sizeof(u16);
1575 dptr += sizeof(u16);
1576 if ((sublen < SDPCM_HDRLEN) ||
1577 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1578 brcmf_err("descriptor len %d bad: %d\n",
1583 if (sublen % bus->sgentry_align) {
1584 brcmf_err("sublen %d not multiple of %d\n",
1585 sublen, bus->sgentry_align);
1589 /* For last frame, adjust read len so total
1590 is a block multiple */
1593 (roundup(totlen, bus->blocksize) - totlen);
1594 totlen = roundup(totlen, bus->blocksize);
1597 /* Allocate/chain packet for next subframe */
1598 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1599 if (pnext == NULL) {
1600 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1604 skb_queue_tail(&bus->glom, pnext);
1606 /* Adhere to start alignment requirements */
1607 pkt_align(pnext, sublen, bus->sgentry_align);
1610 /* If all allocations succeeded, save packet chain
1613 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1615 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1616 totlen != bus->cur_read.len) {
1617 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1618 bus->cur_read.len, totlen, rxseq);
1620 pfirst = pnext = NULL;
1622 brcmf_sdio_free_glom(bus);
1626 /* Done with descriptor packet */
1627 brcmu_pkt_buf_free_skb(bus->glomd);
1629 bus->cur_read.len = 0;
1632 /* Ok -- either we just generated a packet chain,
1633 or had one from before */
1634 if (!skb_queue_empty(&bus->glom)) {
1635 if (BRCMF_GLOM_ON()) {
1636 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1637 skb_queue_walk(&bus->glom, pnext) {
1638 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1639 pnext, (u8 *) (pnext->data),
1640 pnext->len, pnext->len);
1644 pfirst = skb_peek(&bus->glom);
1645 dlen = (u16) brcmf_sdio_glom_len(bus);
1647 /* Do an SDIO read for the superframe. Configurable iovar to
1648 * read directly into the chained packet, or allocate a large
1649 * packet and and copy into the chain.
1651 sdio_claim_host(bus->sdiodev->func[1]);
1652 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1654 sdio_release_host(bus->sdiodev->func[1]);
1655 bus->sdcnt.f2rxdata++;
1657 /* On failure, kill the superframe, allow a couple retries */
1659 brcmf_err("glom read of %d bytes failed: %d\n",
1662 sdio_claim_host(bus->sdiodev->func[1]);
1663 if (bus->glomerr++ < 3) {
1664 brcmf_sdio_rxfail(bus, true, true);
1667 brcmf_sdio_rxfail(bus, true, false);
1668 bus->sdcnt.rxglomfail++;
1669 brcmf_sdio_free_glom(bus);
1671 sdio_release_host(bus->sdiodev->func[1]);
1675 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1676 pfirst->data, min_t(int, pfirst->len, 48),
1679 rd_new.seq_num = rxseq;
1681 sdio_claim_host(bus->sdiodev->func[1]);
1682 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1683 BRCMF_SDIO_FT_SUPER);
1684 sdio_release_host(bus->sdiodev->func[1]);
1685 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1687 /* Remove superframe header, remember offset */
1688 skb_pull(pfirst, rd_new.dat_offset);
1689 sfdoff = rd_new.dat_offset;
1692 /* Validate all the subframe headers */
1693 skb_queue_walk(&bus->glom, pnext) {
1694 /* leave when invalid subframe is found */
1698 rd_new.len = pnext->len;
1699 rd_new.seq_num = rxseq++;
1700 sdio_claim_host(bus->sdiodev->func[1]);
1701 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1703 sdio_release_host(bus->sdiodev->func[1]);
1704 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1705 pnext->data, 32, "subframe:\n");
1711 /* Terminate frame on error, request
1713 sdio_claim_host(bus->sdiodev->func[1]);
1714 if (bus->glomerr++ < 3) {
1715 /* Restore superframe header space */
1716 skb_push(pfirst, sfdoff);
1717 brcmf_sdio_rxfail(bus, true, true);
1720 brcmf_sdio_rxfail(bus, true, false);
1721 bus->sdcnt.rxglomfail++;
1722 brcmf_sdio_free_glom(bus);
1724 sdio_release_host(bus->sdiodev->func[1]);
1725 bus->cur_read.len = 0;
1729 /* Basic SD framing looks ok - process each packet (header) */
1731 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1732 dptr = (u8 *) (pfirst->data);
1733 sublen = get_unaligned_le16(dptr);
1734 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1736 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1738 "Rx Subframe Data:\n");
1740 __skb_trim(pfirst, sublen);
1741 skb_pull(pfirst, doff);
1743 if (pfirst->len == 0) {
1744 skb_unlink(pfirst, &bus->glom);
1745 brcmu_pkt_buf_free_skb(pfirst);
1749 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1751 min_t(int, pfirst->len, 32),
1752 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1753 bus->glom.qlen, pfirst, pfirst->data,
1754 pfirst->len, pfirst->next,
1756 skb_unlink(pfirst, &bus->glom);
1757 brcmf_rx_frame(bus->sdiodev->dev, pfirst);
1758 bus->sdcnt.rxglompkts++;
1761 bus->sdcnt.rxglomframes++;
1766 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1769 DECLARE_WAITQUEUE(wait, current);
1770 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1772 /* Wait until control frame is available */
1773 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1774 set_current_state(TASK_INTERRUPTIBLE);
1776 while (!(*condition) && (!signal_pending(current) && timeout))
1777 timeout = schedule_timeout(timeout);
1779 if (signal_pending(current))
1782 set_current_state(TASK_RUNNING);
1783 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1788 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1790 if (waitqueue_active(&bus->dcmd_resp_wait))
1791 wake_up_interruptible(&bus->dcmd_resp_wait);
1796 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1799 u8 *buf = NULL, *rbuf;
1802 brcmf_dbg(TRACE, "Enter\n");
1805 buf = vzalloc(bus->rxblen);
1810 pad = ((unsigned long)rbuf % bus->head_align);
1812 rbuf += (bus->head_align - pad);
1814 /* Copy the already-read portion over */
1815 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1816 if (len <= BRCMF_FIRSTREAD)
1819 /* Raise rdlen to next SDIO block to avoid tail command */
1820 rdlen = len - BRCMF_FIRSTREAD;
1821 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1822 pad = bus->blocksize - (rdlen % bus->blocksize);
1823 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1824 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1826 } else if (rdlen % bus->head_align) {
1827 rdlen += bus->head_align - (rdlen % bus->head_align);
1830 /* Drop if the read is too big or it exceeds our maximum */
1831 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1832 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1833 rdlen, bus->sdiodev->bus_if->maxctl);
1834 brcmf_sdio_rxfail(bus, false, false);
1838 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1839 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1840 len, len - doff, bus->sdiodev->bus_if->maxctl);
1841 bus->sdcnt.rx_toolong++;
1842 brcmf_sdio_rxfail(bus, false, false);
1846 /* Read remain of frame body */
1847 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1848 bus->sdcnt.f2rxdata++;
1850 /* Control frame failures need retransmission */
1852 brcmf_err("read %d control bytes failed: %d\n",
1854 bus->sdcnt.rxc_errors++;
1855 brcmf_sdio_rxfail(bus, true, true);
1858 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1862 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1863 buf, len, "RxCtrl:\n");
1865 /* Point to valid data and indicate its length */
1866 spin_lock_bh(&bus->rxctl_lock);
1868 brcmf_err("last control frame is being processed.\n");
1869 spin_unlock_bh(&bus->rxctl_lock);
1873 bus->rxctl = buf + doff;
1874 bus->rxctl_orig = buf;
1875 bus->rxlen = len - doff;
1876 spin_unlock_bh(&bus->rxctl_lock);
1879 /* Awake any waiters */
1880 brcmf_sdio_dcmd_resp_wake(bus);
1883 /* Pad read to blocksize for efficiency */
1884 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1886 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1887 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1888 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1889 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1891 } else if (*rdlen % bus->head_align) {
1892 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1896 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1898 struct sk_buff *pkt; /* Packet for event or data frames */
1899 u16 pad; /* Number of pad bytes to read */
1900 uint rxleft = 0; /* Remaining number of frames allowed */
1901 int ret; /* Return code from calls */
1902 uint rxcount = 0; /* Total frames read */
1903 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1906 brcmf_dbg(TRACE, "Enter\n");
1908 /* Not finished unless we encounter no more frames indication */
1909 bus->rxpending = true;
1911 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1912 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1913 rd->seq_num++, rxleft--) {
1915 /* Handle glomming separately */
1916 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1918 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1919 bus->glomd, skb_peek(&bus->glom));
1920 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1921 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1922 rd->seq_num += cnt - 1;
1923 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1927 rd->len_left = rd->len;
1928 /* read header first for unknow frame length */
1929 sdio_claim_host(bus->sdiodev->func[1]);
1931 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1932 bus->rxhdr, BRCMF_FIRSTREAD);
1933 bus->sdcnt.f2rxhdrs++;
1935 brcmf_err("RXHEADER FAILED: %d\n",
1937 bus->sdcnt.rx_hdrfail++;
1938 brcmf_sdio_rxfail(bus, true, true);
1939 sdio_release_host(bus->sdiodev->func[1]);
1943 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1944 bus->rxhdr, SDPCM_HDRLEN,
1947 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1948 BRCMF_SDIO_FT_NORMAL)) {
1949 sdio_release_host(bus->sdiodev->func[1]);
1950 if (!bus->rxpending)
1956 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1957 brcmf_sdio_read_control(bus, bus->rxhdr,
1960 /* prepare the descriptor for the next read */
1961 rd->len = rd->len_nxtfrm << 4;
1963 /* treat all packet as event if we don't know */
1964 rd->channel = SDPCM_EVENT_CHANNEL;
1965 sdio_release_host(bus->sdiodev->func[1]);
1968 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1969 rd->len - BRCMF_FIRSTREAD : 0;
1970 head_read = BRCMF_FIRSTREAD;
1973 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1975 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1978 /* Give up on data, request rtx of events */
1979 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1980 brcmf_sdio_rxfail(bus, false,
1981 RETRYCHAN(rd->channel));
1982 sdio_release_host(bus->sdiodev->func[1]);
1985 skb_pull(pkt, head_read);
1986 pkt_align(pkt, rd->len_left, bus->head_align);
1988 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1989 bus->sdcnt.f2rxdata++;
1990 sdio_release_host(bus->sdiodev->func[1]);
1993 brcmf_err("read %d bytes from channel %d failed: %d\n",
1994 rd->len, rd->channel, ret);
1995 brcmu_pkt_buf_free_skb(pkt);
1996 sdio_claim_host(bus->sdiodev->func[1]);
1997 brcmf_sdio_rxfail(bus, true,
1998 RETRYCHAN(rd->channel));
1999 sdio_release_host(bus->sdiodev->func[1]);
2004 skb_push(pkt, head_read);
2005 memcpy(pkt->data, bus->rxhdr, head_read);
2008 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
2009 rd_new.seq_num = rd->seq_num;
2010 sdio_claim_host(bus->sdiodev->func[1]);
2011 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
2012 BRCMF_SDIO_FT_NORMAL)) {
2014 brcmu_pkt_buf_free_skb(pkt);
2016 bus->sdcnt.rx_readahead_cnt++;
2017 if (rd->len != roundup(rd_new.len, 16)) {
2018 brcmf_err("frame length mismatch:read %d, should be %d\n",
2020 roundup(rd_new.len, 16) >> 4);
2022 brcmf_sdio_rxfail(bus, true, true);
2023 sdio_release_host(bus->sdiodev->func[1]);
2024 brcmu_pkt_buf_free_skb(pkt);
2027 sdio_release_host(bus->sdiodev->func[1]);
2028 rd->len_nxtfrm = rd_new.len_nxtfrm;
2029 rd->channel = rd_new.channel;
2030 rd->dat_offset = rd_new.dat_offset;
2032 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
2035 bus->rxhdr, SDPCM_HDRLEN,
2038 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
2039 brcmf_err("readahead on control packet %d?\n",
2041 /* Force retry w/normal header read */
2043 sdio_claim_host(bus->sdiodev->func[1]);
2044 brcmf_sdio_rxfail(bus, false, true);
2045 sdio_release_host(bus->sdiodev->func[1]);
2046 brcmu_pkt_buf_free_skb(pkt);
2051 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
2052 pkt->data, rd->len, "Rx Data:\n");
2054 /* Save superframe descriptor and allocate packet frame */
2055 if (rd->channel == SDPCM_GLOM_CHANNEL) {
2056 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
2057 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2059 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
2062 __skb_trim(pkt, rd->len);
2063 skb_pull(pkt, SDPCM_HDRLEN);
2066 brcmf_err("%s: glom superframe w/o "
2067 "descriptor!\n", __func__);
2068 sdio_claim_host(bus->sdiodev->func[1]);
2069 brcmf_sdio_rxfail(bus, false, false);
2070 sdio_release_host(bus->sdiodev->func[1]);
2072 /* prepare the descriptor for the next read */
2073 rd->len = rd->len_nxtfrm << 4;
2075 /* treat all packet as event if we don't know */
2076 rd->channel = SDPCM_EVENT_CHANNEL;
2080 /* Fill in packet len and prio, deliver upward */
2081 __skb_trim(pkt, rd->len);
2082 skb_pull(pkt, rd->dat_offset);
2084 /* prepare the descriptor for the next read */
2085 rd->len = rd->len_nxtfrm << 4;
2087 /* treat all packet as event if we don't know */
2088 rd->channel = SDPCM_EVENT_CHANNEL;
2090 if (pkt->len == 0) {
2091 brcmu_pkt_buf_free_skb(pkt);
2095 brcmf_rx_frame(bus->sdiodev->dev, pkt);
2098 rxcount = maxframes - rxleft;
2099 /* Message if we hit the limit */
2101 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2103 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2104 /* Back off rxseq if awaiting rtx, update rx_seq */
2107 bus->rx_seq = rd->seq_num;
2113 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2115 if (waitqueue_active(&bus->ctrl_wait))
2116 wake_up_interruptible(&bus->ctrl_wait);
2120 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2125 dat_buf = (u8 *)(pkt->data);
2127 /* Check head padding */
2128 head_pad = ((unsigned long)dat_buf % bus->head_align);
2130 if (skb_headroom(pkt) < head_pad) {
2131 bus->sdiodev->bus_if->tx_realloc++;
2133 if (skb_cow(pkt, head_pad))
2136 skb_push(pkt, head_pad);
2137 dat_buf = (u8 *)(pkt->data);
2138 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2144 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2147 /* flag marking a dummy skb added for DMA alignment requirement */
2148 #define ALIGN_SKB_FLAG 0x8000
2149 /* bit mask of data length chopped from the previous packet */
2150 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2152 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2153 struct sk_buff_head *pktq,
2154 struct sk_buff *pkt, u16 total_len)
2156 struct brcmf_sdio_dev *sdiodev;
2157 struct sk_buff *pkt_pad;
2158 u16 tail_pad, tail_chop, chain_pad;
2159 unsigned int blksize;
2163 sdiodev = bus->sdiodev;
2164 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2165 /* sg entry alignment should be a divisor of block size */
2166 WARN_ON(blksize % bus->sgentry_align);
2168 /* Check tail padding */
2169 lastfrm = skb_queue_is_last(pktq, pkt);
2171 tail_chop = pkt->len % bus->sgentry_align;
2173 tail_pad = bus->sgentry_align - tail_chop;
2174 chain_pad = (total_len + tail_pad) % blksize;
2175 if (lastfrm && chain_pad)
2176 tail_pad += blksize - chain_pad;
2177 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2178 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2180 if (pkt_pad == NULL)
2182 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2183 if (unlikely(ret < 0)) {
2187 memcpy(pkt_pad->data,
2188 pkt->data + pkt->len - tail_chop,
2190 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2191 skb_trim(pkt, pkt->len - tail_chop);
2192 skb_trim(pkt_pad, tail_pad + tail_chop);
2193 __skb_queue_after(pktq, pkt, pkt_pad);
2195 ntail = pkt->data_len + tail_pad -
2196 (pkt->end - pkt->tail);
2197 if (skb_cloned(pkt) || ntail > 0)
2198 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2200 if (skb_linearize(pkt))
2202 __skb_put(pkt, tail_pad);
2209 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2210 * @bus: brcmf_sdio structure pointer
2211 * @pktq: packet list pointer
2212 * @chan: virtual channel to transmit the packet
2214 * Processes to be applied to the packet
2215 * - Align data buffer pointer
2216 * - Align data buffer length
2218 * Return: negative value if there is error
2221 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2224 u16 head_pad, total_len;
2225 struct sk_buff *pkt_next;
2228 struct brcmf_sdio_hdrinfo hd_info = {0};
2230 txseq = bus->tx_seq;
2232 skb_queue_walk(pktq, pkt_next) {
2233 /* alignment packet inserted in previous
2234 * loop cycle can be skipped as it is
2235 * already properly aligned and does not
2236 * need an sdpcm header.
2238 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2241 /* align packet data pointer */
2242 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2245 head_pad = (u16)ret;
2247 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2249 total_len += pkt_next->len;
2251 hd_info.len = pkt_next->len;
2252 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2253 if (bus->txglom && pktq->qlen > 1) {
2254 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2255 pkt_next, total_len);
2258 hd_info.tail_pad = (u16)ret;
2259 total_len += (u16)ret;
2262 hd_info.channel = chan;
2263 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2264 hd_info.seq_num = txseq++;
2266 /* Now fill the header */
2267 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2269 if (BRCMF_BYTES_ON() &&
2270 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2271 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2272 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2274 else if (BRCMF_HDRS_ON())
2275 brcmf_dbg_hex_dump(true, pkt_next->data,
2276 head_pad + bus->tx_hdrlen,
2279 /* Hardware length tag of the first packet should be total
2280 * length of the chain (including padding)
2283 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2288 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2289 * @bus: brcmf_sdio structure pointer
2290 * @pktq: packet list pointer
2292 * Processes to be applied to the packet
2293 * - Remove head padding
2294 * - Remove tail padding
2297 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2302 u16 dummy_flags, chop_len;
2303 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2305 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2306 dummy_flags = *(u16 *)(pkt_next->cb);
2307 if (dummy_flags & ALIGN_SKB_FLAG) {
2308 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2310 pkt_prev = pkt_next->prev;
2311 skb_put(pkt_prev, chop_len);
2313 __skb_unlink(pkt_next, pktq);
2314 brcmu_pkt_buf_free_skb(pkt_next);
2316 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2317 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2318 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2319 SDPCM_DOFFSET_SHIFT;
2320 skb_pull(pkt_next, dat_offset);
2322 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2323 skb_trim(pkt_next, pkt_next->len - tail_pad);
2329 /* Writes a HW/SW header into the packet and sends it. */
2330 /* Assumes: (a) header space already there, (b) caller holds lock */
2331 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2335 struct sk_buff *pkt_next, *tmp;
2337 brcmf_dbg(TRACE, "Enter\n");
2339 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2343 sdio_claim_host(bus->sdiodev->func[1]);
2344 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2345 bus->sdcnt.f2txdata++;
2348 brcmf_sdio_txfail(bus);
2350 sdio_release_host(bus->sdiodev->func[1]);
2353 brcmf_sdio_txpkt_postp(bus, pktq);
2355 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2356 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2357 __skb_unlink(pkt_next, pktq);
2358 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2363 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2365 struct sk_buff *pkt;
2366 struct sk_buff_head pktq;
2368 int ret = 0, prec_out, i;
2370 u8 tx_prec_map, pkt_num;
2372 brcmf_dbg(TRACE, "Enter\n");
2374 tx_prec_map = ~bus->flowcontrol;
2376 /* Send frames until the limit or some other event */
2377 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2380 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2381 bus->sdiodev->txglomsz);
2382 pkt_num = min_t(u32, pkt_num,
2383 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2384 __skb_queue_head_init(&pktq);
2385 spin_lock_bh(&bus->txq_lock);
2386 for (i = 0; i < pkt_num; i++) {
2387 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2391 __skb_queue_tail(&pktq, pkt);
2393 spin_unlock_bh(&bus->txq_lock);
2397 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2401 /* In poll mode, need to check for other events */
2403 /* Check device status, signal pending interrupt */
2404 sdio_claim_host(bus->sdiodev->func[1]);
2405 ret = r_sdreg32(bus, &intstatus,
2406 offsetof(struct sdpcmd_regs,
2408 sdio_release_host(bus->sdiodev->func[1]);
2409 bus->sdcnt.f2txdata++;
2412 if (intstatus & bus->hostintmask)
2413 atomic_set(&bus->ipend, 1);
2417 /* Deflow-control stack if needed */
2418 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2419 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2421 brcmf_txflowblock(bus->sdiodev->dev, false);
2427 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2432 struct brcmf_sdio_hdrinfo hd_info = {0};
2435 brcmf_dbg(TRACE, "Enter\n");
2437 /* Back the pointer to make room for bus header */
2438 frame -= bus->tx_hdrlen;
2439 len += bus->tx_hdrlen;
2441 /* Add alignment padding (optional for ctl frames) */
2442 doff = ((unsigned long)frame % bus->head_align);
2446 memset(frame + bus->tx_hdrlen, 0, doff);
2449 /* Round send length to next SDIO block */
2451 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2452 pad = bus->blocksize - (len % bus->blocksize);
2453 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2455 } else if (len % bus->head_align) {
2456 pad = bus->head_align - (len % bus->head_align);
2460 hd_info.len = len - pad;
2461 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2462 hd_info.dat_offset = doff + bus->tx_hdrlen;
2463 hd_info.seq_num = bus->tx_seq;
2464 hd_info.lastfrm = true;
2465 hd_info.tail_pad = pad;
2466 brcmf_sdio_hdpack(bus, frame, &hd_info);
2469 brcmf_sdio_update_hwhdr(frame, len);
2471 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2472 frame, len, "Tx Frame:\n");
2473 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2475 frame, min_t(u16, len, 16), "TxHdr:\n");
2478 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2481 brcmf_sdio_txfail(bus);
2483 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2484 } while (ret < 0 && retries++ < TXRETRIES);
2489 static void brcmf_sdio_bus_stop(struct device *dev)
2491 u32 local_hostintmask;
2494 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2495 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2496 struct brcmf_sdio *bus = sdiodev->bus;
2498 brcmf_dbg(TRACE, "Enter\n");
2500 if (bus->watchdog_tsk) {
2501 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2502 kthread_stop(bus->watchdog_tsk);
2503 bus->watchdog_tsk = NULL;
2506 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2507 sdio_claim_host(sdiodev->func[1]);
2509 /* Enable clock for device interrupts */
2510 brcmf_sdio_bus_sleep(bus, false, false);
2512 /* Disable and clear interrupts at the chip level also */
2513 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2514 local_hostintmask = bus->hostintmask;
2515 bus->hostintmask = 0;
2517 /* Force backplane clocks to assure F2 interrupt propagates */
2518 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2521 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2522 (saveclk | SBSDIO_FORCE_HT), &err);
2524 brcmf_err("Failed to force clock for F2: err %d\n",
2527 /* Turn off the bus (F2), free any pending packets */
2528 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2529 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2531 /* Clear any pending interrupts now that F2 is disabled */
2532 w_sdreg32(bus, local_hostintmask,
2533 offsetof(struct sdpcmd_regs, intstatus));
2535 sdio_release_host(sdiodev->func[1]);
2537 /* Clear the data packet queues */
2538 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2540 /* Clear any held glomming stuff */
2541 brcmu_pkt_buf_free_skb(bus->glomd);
2542 brcmf_sdio_free_glom(bus);
2544 /* Clear rx control and wake any waiters */
2545 spin_lock_bh(&bus->rxctl_lock);
2547 spin_unlock_bh(&bus->rxctl_lock);
2548 brcmf_sdio_dcmd_resp_wake(bus);
2550 /* Reset some F2 state stuff */
2551 bus->rxskip = false;
2552 bus->tx_seq = bus->rx_seq = 0;
2555 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2557 unsigned long flags;
2559 if (bus->sdiodev->oob_irq_requested) {
2560 spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
2561 if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2562 enable_irq(bus->sdiodev->pdata->oob_irq_nr);
2563 bus->sdiodev->irq_en = true;
2565 spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
2569 static void atomic_orr(int val, atomic_t *v)
2573 old_val = atomic_read(v);
2574 while (atomic_cmpxchg(v, old_val, val | old_val) != old_val)
2575 old_val = atomic_read(v);
2578 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2580 struct brcmf_core *buscore;
2585 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2586 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2588 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2589 bus->sdcnt.f1regdata++;
2593 val &= bus->hostintmask;
2594 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2596 /* Clear interrupts */
2598 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2599 bus->sdcnt.f1regdata++;
2600 atomic_orr(val, &bus->intstatus);
2606 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2609 unsigned long intstatus;
2610 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2611 uint framecnt; /* Temporary counter of tx/rx frames */
2614 brcmf_dbg(TRACE, "Enter\n");
2616 sdio_claim_host(bus->sdiodev->func[1]);
2618 /* If waiting for HTAVAIL, check status */
2619 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2620 u8 clkctl, devctl = 0;
2623 /* Check for inconsistent device control */
2624 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2625 SBSDIO_DEVICE_CTL, &err);
2628 /* Read CSR, if clock on switch to AVAIL, else ignore */
2629 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2630 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2632 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2635 if (SBSDIO_HTAV(clkctl)) {
2636 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2637 SBSDIO_DEVICE_CTL, &err);
2638 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2639 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2641 bus->clkstate = CLK_AVAIL;
2645 /* Make sure backplane clock is on */
2646 brcmf_sdio_bus_sleep(bus, false, true);
2648 /* Pending interrupt indicates new device status */
2649 if (atomic_read(&bus->ipend) > 0) {
2650 atomic_set(&bus->ipend, 0);
2651 err = brcmf_sdio_intr_rstatus(bus);
2654 /* Start with leftover status bits */
2655 intstatus = atomic_xchg(&bus->intstatus, 0);
2657 /* Handle flow-control change: read new state in case our ack
2658 * crossed another change interrupt. If change still set, assume
2659 * FC ON for safety, let next loop through do the debounce.
2661 if (intstatus & I_HMB_FC_CHANGE) {
2662 intstatus &= ~I_HMB_FC_CHANGE;
2663 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2664 offsetof(struct sdpcmd_regs, intstatus));
2666 err = r_sdreg32(bus, &newstatus,
2667 offsetof(struct sdpcmd_regs, intstatus));
2668 bus->sdcnt.f1regdata += 2;
2669 atomic_set(&bus->fcstate,
2670 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2671 intstatus |= (newstatus & bus->hostintmask);
2674 /* Handle host mailbox indication */
2675 if (intstatus & I_HMB_HOST_INT) {
2676 intstatus &= ~I_HMB_HOST_INT;
2677 intstatus |= brcmf_sdio_hostmail(bus);
2680 sdio_release_host(bus->sdiodev->func[1]);
2682 /* Generally don't ask for these, can get CRC errors... */
2683 if (intstatus & I_WR_OOSYNC) {
2684 brcmf_err("Dongle reports WR_OOSYNC\n");
2685 intstatus &= ~I_WR_OOSYNC;
2688 if (intstatus & I_RD_OOSYNC) {
2689 brcmf_err("Dongle reports RD_OOSYNC\n");
2690 intstatus &= ~I_RD_OOSYNC;
2693 if (intstatus & I_SBINT) {
2694 brcmf_err("Dongle reports SBINT\n");
2695 intstatus &= ~I_SBINT;
2698 /* Would be active due to wake-wlan in gSPI */
2699 if (intstatus & I_CHIPACTIVE) {
2700 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2701 intstatus &= ~I_CHIPACTIVE;
2704 /* Ignore frame indications if rxskip is set */
2706 intstatus &= ~I_HMB_FRAME_IND;
2708 /* On frame indication, read available frames */
2709 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2710 brcmf_sdio_readframes(bus, bus->rxbound);
2711 if (!bus->rxpending)
2712 intstatus &= ~I_HMB_FRAME_IND;
2715 /* Keep still-pending events for next scheduling */
2717 atomic_orr(intstatus, &bus->intstatus);
2719 brcmf_sdio_clrintr(bus);
2721 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2723 sdio_claim_host(bus->sdiodev->func[1]);
2724 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2725 bus->ctrl_frame_len);
2726 sdio_release_host(bus->sdiodev->func[1]);
2727 bus->ctrl_frame_err = err;
2728 bus->ctrl_frame_stat = false;
2729 brcmf_sdio_wait_event_wakeup(bus);
2731 /* Send queued frames (limit 1 if rx may still be pending) */
2732 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2733 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2735 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2737 brcmf_sdio_sendfromq(bus, framecnt);
2740 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2741 brcmf_err("failed backplane access over SDIO, halting operation\n");
2742 atomic_set(&bus->intstatus, 0);
2743 } else if (atomic_read(&bus->intstatus) ||
2744 atomic_read(&bus->ipend) > 0 ||
2745 (!atomic_read(&bus->fcstate) &&
2746 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2748 atomic_inc(&bus->dpc_tskcnt);
2752 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2754 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2755 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2756 struct brcmf_sdio *bus = sdiodev->bus;
2761 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2764 int eprec = -1; /* precedence to evict from */
2766 /* Fast case, precedence queue is not full and we are also not
2767 * exceeding total queue length
2769 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2770 brcmu_pktq_penq(q, prec, pkt);
2774 /* Determine precedence from which to evict packet, if any */
2775 if (pktq_pfull(q, prec)) {
2777 } else if (pktq_full(q)) {
2778 p = brcmu_pktq_peek_tail(q, &eprec);
2783 /* Evict if needed */
2785 /* Detect queueing to unconfigured precedence */
2787 return false; /* refuse newer (incoming) packet */
2788 /* Evict packet according to discard policy */
2789 p = brcmu_pktq_pdeq_tail(q, eprec);
2791 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2792 brcmu_pkt_buf_free_skb(p);
2796 p = brcmu_pktq_penq(q, prec, pkt);
2798 brcmf_err("brcmu_pktq_penq() failed\n");
2803 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2807 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2808 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2809 struct brcmf_sdio *bus = sdiodev->bus;
2811 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2813 /* Add space for the header */
2814 skb_push(pkt, bus->tx_hdrlen);
2815 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2817 prec = prio2prec((pkt->priority & PRIOMASK));
2819 /* Check for existing queue, current flow-control,
2820 pending event, or pending clock */
2821 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2822 bus->sdcnt.fcqueued++;
2824 /* Priority based enq */
2825 spin_lock_bh(&bus->txq_lock);
2826 /* reset bus_flags in packet cb */
2827 *(u16 *)(pkt->cb) = 0;
2828 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2829 skb_pull(pkt, bus->tx_hdrlen);
2830 brcmf_err("out of bus->txq !!!\n");
2836 if (pktq_len(&bus->txq) >= TXHI) {
2838 brcmf_txflowblock(dev, true);
2840 spin_unlock_bh(&bus->txq_lock);
2843 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2844 qcount[prec] = pktq_plen(&bus->txq, prec);
2847 brcmf_sdio_trigger_dpc(bus);
2852 #define CONSOLE_LINE_MAX 192
2854 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2856 struct brcmf_console *c = &bus->console;
2857 u8 line[CONSOLE_LINE_MAX], ch;
2861 /* Don't do anything until FWREADY updates console address */
2862 if (bus->console_addr == 0)
2865 /* Read console log struct */
2866 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2867 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2872 /* Allocate console buffer (one time only) */
2873 if (c->buf == NULL) {
2874 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2875 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2880 idx = le32_to_cpu(c->log_le.idx);
2882 /* Protect against corrupt value */
2883 if (idx > c->bufsize)
2886 /* Skip reading the console buffer if the index pointer
2891 /* Read the console buffer */
2892 addr = le32_to_cpu(c->log_le.buf);
2893 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2897 while (c->last != idx) {
2898 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2899 if (c->last == idx) {
2900 /* This would output a partial line.
2902 * the buffer pointer and output this
2903 * line next time around.
2908 c->last = c->bufsize - n;
2911 ch = c->buf[c->last];
2912 c->last = (c->last + 1) % c->bufsize;
2919 if (line[n - 1] == '\r')
2922 pr_debug("CONSOLE: %s\n", line);
2932 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2934 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2935 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2936 struct brcmf_sdio *bus = sdiodev->bus;
2939 brcmf_dbg(TRACE, "Enter\n");
2942 bus->ctrl_frame_buf = msg;
2943 bus->ctrl_frame_len = msglen;
2944 bus->ctrl_frame_stat = true;
2946 brcmf_sdio_trigger_dpc(bus);
2947 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2948 msecs_to_jiffies(CTL_DONE_TIMEOUT));
2950 if (!bus->ctrl_frame_stat) {
2951 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2952 bus->ctrl_frame_err);
2953 ret = bus->ctrl_frame_err;
2955 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2956 bus->ctrl_frame_stat = false;
2961 bus->sdcnt.tx_ctlerrs++;
2963 bus->sdcnt.tx_ctlpkts++;
2969 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2970 struct sdpcm_shared *sh)
2972 u32 addr, console_ptr, console_size, console_index;
2973 char *conbuf = NULL;
2977 /* obtain console information from device memory */
2978 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2979 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2980 (u8 *)&sh_val, sizeof(u32));
2983 console_ptr = le32_to_cpu(sh_val);
2985 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2986 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2987 (u8 *)&sh_val, sizeof(u32));
2990 console_size = le32_to_cpu(sh_val);
2992 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2993 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2994 (u8 *)&sh_val, sizeof(u32));
2997 console_index = le32_to_cpu(sh_val);
2999 /* allocate buffer for console data */
3000 if (console_size <= CONSOLE_BUFFER_MAX)
3001 conbuf = vzalloc(console_size+1);
3006 /* obtain the console data from device */
3007 conbuf[console_size] = '\0';
3008 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
3013 rv = seq_write(seq, conbuf + console_index,
3014 console_size - console_index);
3018 if (console_index > 0)
3019 rv = seq_write(seq, conbuf, console_index - 1);
3026 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
3027 struct sdpcm_shared *sh)
3030 struct brcmf_trap_info tr;
3032 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
3033 brcmf_dbg(INFO, "no trap in firmware\n");
3037 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3038 sizeof(struct brcmf_trap_info));
3043 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3044 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3045 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3046 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3047 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3048 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3049 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3050 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3051 le32_to_cpu(tr.pc), sh->trap_addr,
3052 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3053 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3054 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3055 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3060 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3061 struct sdpcm_shared *sh)
3064 char file[80] = "?";
3065 char expr[80] = "<???>";
3067 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3068 brcmf_dbg(INFO, "firmware not built with -assert\n");
3070 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3071 brcmf_dbg(INFO, "no assert in dongle\n");
3075 sdio_claim_host(bus->sdiodev->func[1]);
3076 if (sh->assert_file_addr != 0) {
3077 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3078 sh->assert_file_addr, (u8 *)file, 80);
3082 if (sh->assert_exp_addr != 0) {
3083 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3084 sh->assert_exp_addr, (u8 *)expr, 80);
3088 sdio_release_host(bus->sdiodev->func[1]);
3090 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3091 file, sh->assert_line, expr);
3095 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3098 struct sdpcm_shared sh;
3100 error = brcmf_sdio_readshared(bus, &sh);
3105 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3106 brcmf_dbg(INFO, "firmware not built with -assert\n");
3107 else if (sh.flags & SDPCM_SHARED_ASSERT)
3108 brcmf_err("assertion in dongle\n");
3110 if (sh.flags & SDPCM_SHARED_TRAP)
3111 brcmf_err("firmware trap in dongle\n");
3116 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3119 struct sdpcm_shared sh;
3121 error = brcmf_sdio_readshared(bus, &sh);
3125 error = brcmf_sdio_assert_info(seq, bus, &sh);
3129 error = brcmf_sdio_trap_info(seq, bus, &sh);
3133 error = brcmf_sdio_dump_console(seq, bus, &sh);
3139 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3141 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3142 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3144 return brcmf_sdio_died_dump(seq, bus);
3147 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3149 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3150 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3151 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3154 "intrcount: %u\nlastintrs: %u\n"
3155 "pollcnt: %u\nregfails: %u\n"
3156 "tx_sderrs: %u\nfcqueued: %u\n"
3157 "rxrtx: %u\nrx_toolong: %u\n"
3158 "rxc_errors: %u\nrx_hdrfail: %u\n"
3159 "rx_badhdr: %u\nrx_badseq: %u\n"
3160 "fc_rcvd: %u\nfc_xoff: %u\n"
3161 "fc_xon: %u\nrxglomfail: %u\n"
3162 "rxglomframes: %u\nrxglompkts: %u\n"
3163 "f2rxhdrs: %u\nf2rxdata: %u\n"
3164 "f2txdata: %u\nf1regdata: %u\n"
3165 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3166 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3167 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3168 sdcnt->intrcount, sdcnt->lastintrs,
3169 sdcnt->pollcnt, sdcnt->regfails,
3170 sdcnt->tx_sderrs, sdcnt->fcqueued,
3171 sdcnt->rxrtx, sdcnt->rx_toolong,
3172 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3173 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3174 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3175 sdcnt->fc_xon, sdcnt->rxglomfail,
3176 sdcnt->rxglomframes, sdcnt->rxglompkts,
3177 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3178 sdcnt->f2txdata, sdcnt->f1regdata,
3179 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3180 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3181 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3186 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3188 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3189 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3191 if (IS_ERR_OR_NULL(dentry))
3194 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3195 brcmf_debugfs_add_entry(drvr, "counters",
3196 brcmf_debugfs_sdio_count_read);
3197 debugfs_create_u32("console_interval", 0644, dentry,
3198 &bus->console_interval);
3201 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3206 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3212 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3218 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3219 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3220 struct brcmf_sdio *bus = sdiodev->bus;
3222 brcmf_dbg(TRACE, "Enter\n");
3224 /* Wait until control frame is available */
3225 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3227 spin_lock_bh(&bus->rxctl_lock);
3229 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3231 buf = bus->rxctl_orig;
3232 bus->rxctl_orig = NULL;
3234 spin_unlock_bh(&bus->rxctl_lock);
3238 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3240 } else if (timeleft == 0) {
3241 brcmf_err("resumed on timeout\n");
3242 brcmf_sdio_checkdied(bus);
3243 } else if (pending) {
3244 brcmf_dbg(CTL, "cancelled\n");
3245 return -ERESTARTSYS;
3247 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3248 brcmf_sdio_checkdied(bus);
3252 bus->sdcnt.rx_ctlpkts++;
3254 bus->sdcnt.rx_ctlerrs++;
3256 return rxlen ? (int)rxlen : -ETIMEDOUT;
3261 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3262 u8 *ram_data, uint ram_sz)
3271 /* read back and verify */
3272 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3274 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3275 /* do not proceed while no memory but */
3281 while (offset < ram_sz) {
3282 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3284 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3286 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3290 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3291 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3306 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3307 u8 *ram_data, uint ram_sz)
3313 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3314 const struct firmware *fw)
3318 brcmf_dbg(TRACE, "Enter\n");
3320 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3321 (u8 *)fw->data, fw->size);
3323 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3324 err, (int)fw->size, bus->ci->rambase);
3325 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3326 (u8 *)fw->data, fw->size))
3332 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3333 void *vars, u32 varsz)
3338 brcmf_dbg(TRACE, "Enter\n");
3340 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3341 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3343 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3344 err, varsz, address);
3345 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3351 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3352 const struct firmware *fw,
3353 void *nvram, u32 nvlen)
3355 int bcmerror = -EFAULT;
3358 sdio_claim_host(bus->sdiodev->func[1]);
3359 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3361 /* Keep arm in reset */
3362 brcmf_chip_enter_download(bus->ci);
3364 rstvec = get_unaligned_le32(fw->data);
3365 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3367 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3368 release_firmware(fw);
3370 brcmf_err("dongle image file download failed\n");
3371 brcmf_fw_nvram_free(nvram);
3375 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3376 brcmf_fw_nvram_free(nvram);
3378 brcmf_err("dongle nvram file download failed\n");
3382 /* Take arm out of reset */
3383 if (!brcmf_chip_exit_download(bus->ci, rstvec)) {
3384 brcmf_err("error getting out of ARM core reset\n");
3388 /* Allow full data communication using DPC from now on. */
3389 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3393 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3394 sdio_release_host(bus->sdiodev->func[1]);
3398 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3403 brcmf_dbg(TRACE, "Enter\n");
3405 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3407 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3411 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3412 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3414 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3418 /* Add CMD14 Support */
3419 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3420 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3421 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3424 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3428 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3429 SBSDIO_FORCE_HT, &err);
3431 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3436 bus->sr_enabled = true;
3437 brcmf_dbg(INFO, "SR enabled\n");
3440 /* enable KSO bit */
3441 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3446 brcmf_dbg(TRACE, "Enter\n");
3448 /* KSO bit added in SDIO core rev 12 */
3449 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3452 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3454 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3458 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3459 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3460 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3461 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3464 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3473 static int brcmf_sdio_bus_preinit(struct device *dev)
3475 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3476 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3477 struct brcmf_sdio *bus = sdiodev->bus;
3482 /* the commands below use the terms tx and rx from
3483 * a device perspective, ie. bus:txglom affects the
3484 * bus transfers from device to host.
3486 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3487 /* for sdio core rev < 12, disable txgloming */
3489 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3492 /* otherwise, set txglomalign */
3495 value = sdiodev->pdata->sd_sgentry_align;
3496 /* SDIO ADMA requires at least 32 bit alignment */
3497 value = max_t(u32, value, 4);
3498 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3505 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3506 if (sdiodev->sg_support) {
3507 bus->txglom = false;
3509 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3510 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3511 &value, sizeof(u32));
3513 /* bus:rxglom is allowed to fail */
3517 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3520 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3526 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3528 if (atomic_read(&bus->dpc_tskcnt) == 0) {
3529 atomic_inc(&bus->dpc_tskcnt);
3530 queue_work(bus->brcmf_wq, &bus->datawork);
3534 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3536 brcmf_dbg(TRACE, "Enter\n");
3539 brcmf_err("bus is null pointer, exiting\n");
3543 if (bus->sdiodev->state != BRCMF_SDIOD_DATA) {
3544 brcmf_err("bus is down. we have nothing to do\n");
3547 /* Count the interrupt call */
3548 bus->sdcnt.intrcount++;
3550 atomic_set(&bus->ipend, 1);
3552 if (brcmf_sdio_intr_rstatus(bus)) {
3553 brcmf_err("failed backplane access\n");
3556 /* Disable additional interrupts (is this needed now)? */
3558 brcmf_err("isr w/o interrupt configured!\n");
3560 atomic_inc(&bus->dpc_tskcnt);
3561 queue_work(bus->brcmf_wq, &bus->datawork);
3564 static bool brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3566 brcmf_dbg(TIMER, "Enter\n");
3568 /* Poll period: check device if appropriate. */
3569 if (!bus->sr_enabled &&
3570 bus->poll && (++bus->polltick >= bus->pollrate)) {
3573 /* Reset poll tick */
3576 /* Check device if no interrupts */
3578 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3580 if (atomic_read(&bus->dpc_tskcnt) == 0) {
3583 sdio_claim_host(bus->sdiodev->func[1]);
3584 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3587 sdio_release_host(bus->sdiodev->func[1]);
3588 intstatus = devpend & (INTR_STATUS_FUNC1 |
3592 /* If there is something, make like the ISR and
3595 bus->sdcnt.pollcnt++;
3596 atomic_set(&bus->ipend, 1);
3598 atomic_inc(&bus->dpc_tskcnt);
3599 queue_work(bus->brcmf_wq, &bus->datawork);
3603 /* Update interrupt tracking */
3604 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3607 /* Poll for console output periodically */
3608 if (bus->sdiodev->state == BRCMF_SDIOD_DATA &&
3609 bus->console_interval != 0) {
3610 bus->console.count += BRCMF_WD_POLL_MS;
3611 if (bus->console.count >= bus->console_interval) {
3612 bus->console.count -= bus->console_interval;
3613 sdio_claim_host(bus->sdiodev->func[1]);
3614 /* Make sure backplane clock is on */
3615 brcmf_sdio_bus_sleep(bus, false, false);
3616 if (brcmf_sdio_readconsole(bus) < 0)
3618 bus->console_interval = 0;
3619 sdio_release_host(bus->sdiodev->func[1]);
3624 /* On idle timeout clear activity flag and/or turn off clock */
3625 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3626 if (++bus->idlecount >= bus->idletime) {
3628 if (bus->activity) {
3629 bus->activity = false;
3630 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
3632 brcmf_dbg(SDIO, "idle\n");
3633 sdio_claim_host(bus->sdiodev->func[1]);
3634 brcmf_sdio_bus_sleep(bus, true, false);
3635 sdio_release_host(bus->sdiodev->func[1]);
3640 return (atomic_read(&bus->ipend) > 0);
3643 static void brcmf_sdio_dataworker(struct work_struct *work)
3645 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3648 while (atomic_read(&bus->dpc_tskcnt)) {
3649 atomic_set(&bus->dpc_tskcnt, 0);
3650 brcmf_sdio_dpc(bus);
3652 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3653 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3654 brcmf_sdiod_try_freeze(bus->sdiodev);
3655 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3660 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3661 struct brcmf_chip *ci, u32 drivestrength)
3663 const struct sdiod_drive_str *str_tab = NULL;
3668 u32 drivestrength_sel = 0;
3672 if (!(ci->cc_caps & CC_CAP_PMU))
3675 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3676 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3677 str_tab = sdiod_drvstr_tab1_1v8;
3678 str_mask = 0x00003800;
3681 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3682 str_tab = sdiod_drvstr_tab6_1v8;
3683 str_mask = 0x00001800;
3686 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3687 /* note: 43143 does not support tristate */
3688 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3689 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3690 str_tab = sdiod_drvstr_tab2_3v3;
3691 str_mask = 0x00000007;
3694 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3695 ci->name, drivestrength);
3697 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3698 str_tab = sdiod_drive_strength_tab5_1v8;
3699 str_mask = 0x00003800;
3703 brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
3704 ci->name, ci->chiprev, ci->pmurev);
3708 if (str_tab != NULL) {
3709 for (i = 0; str_tab[i].strength != 0; i++) {
3710 if (drivestrength >= str_tab[i].strength) {
3711 drivestrength_sel = str_tab[i].sel;
3715 base = brcmf_chip_get_chipcommon(ci)->base;
3716 addr = CORE_CC_REG(base, chipcontrol_addr);
3717 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3718 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3719 cc_data_temp &= ~str_mask;
3720 drivestrength_sel <<= str_shift;
3721 cc_data_temp |= drivestrength_sel;
3722 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3724 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3725 str_tab[i].strength, drivestrength, cc_data_temp);
3729 static int brcmf_sdio_buscoreprep(void *ctx)
3731 struct brcmf_sdio_dev *sdiodev = ctx;
3735 /* Try forcing SDIO core to do ALPAvail request only */
3736 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3737 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3739 brcmf_err("error writing for HT off\n");
3743 /* If register supported, wait for ALPAvail and then force ALP */
3744 /* This may take up to 15 milliseconds */
3745 clkval = brcmf_sdiod_regrb(sdiodev,
3746 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3748 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3749 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3754 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3755 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3756 !SBSDIO_ALPAV(clkval)),
3757 PMU_MAX_TRANSITION_DLY);
3758 if (!SBSDIO_ALPAV(clkval)) {
3759 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3764 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3765 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3768 /* Also, disable the extra SDIO pull-ups */
3769 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3774 static void brcmf_sdio_buscore_exitdl(void *ctx, struct brcmf_chip *chip,
3777 struct brcmf_sdio_dev *sdiodev = ctx;
3778 struct brcmf_core *core;
3781 /* clear all interrupts */
3782 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3783 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3784 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3787 /* Write reset vector to address 0 */
3788 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3792 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3794 struct brcmf_sdio_dev *sdiodev = ctx;
3797 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3798 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
3799 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3800 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3802 val &= ~CID_ID_MASK;
3803 val |= BRCM_CC_4339_CHIP_ID;
3809 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3811 struct brcmf_sdio_dev *sdiodev = ctx;
3813 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3816 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3817 .prepare = brcmf_sdio_buscoreprep,
3818 .exit_dl = brcmf_sdio_buscore_exitdl,
3819 .read32 = brcmf_sdio_buscore_read32,
3820 .write32 = brcmf_sdio_buscore_write32,
3824 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3832 sdio_claim_host(bus->sdiodev->func[1]);
3834 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3835 brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
3838 * Force PLL off until brcmf_chip_attach()
3839 * programs PLL control regs
3842 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3843 BRCMF_INIT_CLKCTL1, &err);
3845 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
3846 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3848 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3849 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3850 err, BRCMF_INIT_CLKCTL1, clkctl);
3854 bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops);
3855 if (IS_ERR(bus->ci)) {
3856 brcmf_err("brcmf_chip_attach failed!\n");
3861 if (brcmf_sdio_kso_init(bus)) {
3862 brcmf_err("error enabling KSO\n");
3866 if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength))
3867 drivestrength = bus->sdiodev->pdata->drive_strength;
3869 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3870 brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength);
3872 /* Get info on the SOCRAM cores... */
3873 bus->ramsize = bus->ci->ramsize;
3874 if (!(bus->ramsize)) {
3875 brcmf_err("failed to find SOCRAM memory!\n");
3879 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3880 reg_val = brcmf_sdiod_regrb(bus->sdiodev,
3881 SDIO_CCCR_BRCM_CARDCTRL, &err);
3885 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3887 brcmf_sdiod_regwb(bus->sdiodev,
3888 SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3892 /* set PMUControl so a backplane reset does PMU state reload */
3893 reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base,
3895 reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err);
3899 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3901 brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err);
3905 sdio_release_host(bus->sdiodev->func[1]);
3907 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3909 /* allocate header buffer */
3910 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3913 /* Locate an appropriately-aligned portion of hdrbuf */
3914 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3917 /* Set the poll and/or interrupt flags */
3926 sdio_release_host(bus->sdiodev->func[1]);
3931 brcmf_sdio_watchdog_thread(void *data)
3933 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3936 allow_signal(SIGTERM);
3937 /* Run until signal received */
3938 brcmf_sdiod_freezer_count(bus->sdiodev);
3940 if (kthread_should_stop())
3942 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3943 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3944 brcmf_sdiod_freezer_count(bus->sdiodev);
3945 brcmf_sdiod_try_freeze(bus->sdiodev);
3947 brcmf_sdio_bus_watchdog(bus);
3948 /* Count the tick for reference */
3949 bus->sdcnt.tickcnt++;
3950 reinit_completion(&bus->watchdog_wait);
3958 brcmf_sdio_watchdog(unsigned long data)
3960 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3962 if (bus->watchdog_tsk) {
3963 complete(&bus->watchdog_wait);
3964 /* Reschedule the watchdog */
3965 if (bus->wd_timer_valid)
3966 mod_timer(&bus->timer,
3967 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
3971 static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3972 .stop = brcmf_sdio_bus_stop,
3973 .preinit = brcmf_sdio_bus_preinit,
3974 .txdata = brcmf_sdio_bus_txdata,
3975 .txctl = brcmf_sdio_bus_txctl,
3976 .rxctl = brcmf_sdio_bus_rxctl,
3977 .gettxq = brcmf_sdio_bus_gettxq,
3978 .wowl_config = brcmf_sdio_wowl_config
3981 static void brcmf_sdio_firmware_callback(struct device *dev,
3982 const struct firmware *code,
3983 void *nvram, u32 nvram_len)
3985 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3986 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3987 struct brcmf_sdio *bus = sdiodev->bus;
3991 brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
3996 /* try to download image and nvram to the dongle */
3997 bus->alp_only = true;
3998 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4001 bus->alp_only = false;
4003 /* Start the watchdog timer */
4004 bus->sdcnt.tickcnt = 0;
4005 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
4007 sdio_claim_host(sdiodev->func[1]);
4009 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4010 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4011 if (bus->clkstate != CLK_AVAIL)
4014 /* Force clocks on backplane to be sure F2 interrupt propagates */
4015 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4017 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4018 (saveclk | SBSDIO_FORCE_HT), &err);
4021 brcmf_err("Failed to force clock for F2: err %d\n", err);
4025 /* Enable function 2 (frame transfers) */
4026 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4027 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4028 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4031 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4033 /* If F2 successfully enabled, set core and enable interrupts */
4035 /* Set up the interrupt mask and enable interrupts */
4036 bus->hostintmask = HOSTINTMASK;
4037 w_sdreg32(bus, bus->hostintmask,
4038 offsetof(struct sdpcmd_regs, hostintmask));
4040 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4042 /* Disable F2 again */
4043 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4047 if (brcmf_chip_sr_capable(bus->ci)) {
4048 brcmf_sdio_sr_init(bus);
4050 /* Restore previous clock setting */
4051 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4056 err = brcmf_sdiod_intr_register(sdiodev);
4058 brcmf_err("intr register failed:%d\n", err);
4061 /* If we didn't come up, turn off backplane clock */
4063 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4065 sdio_release_host(sdiodev->func[1]);
4067 err = brcmf_bus_start(dev);
4069 brcmf_err("dongle is not responding\n");
4075 sdio_release_host(sdiodev->func[1]);
4077 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4078 device_release_driver(dev);
4081 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4084 struct brcmf_sdio *bus;
4085 struct workqueue_struct *wq;
4087 brcmf_dbg(TRACE, "Enter\n");
4089 /* Allocate private bus interface state */
4090 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4094 bus->sdiodev = sdiodev;
4096 skb_queue_head_init(&bus->glom);
4097 bus->txbound = BRCMF_TXBOUND;
4098 bus->rxbound = BRCMF_RXBOUND;
4099 bus->txminmax = BRCMF_TXMINMAX;
4100 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4102 /* platform specific configuration:
4103 * alignments must be at least 4 bytes for ADMA
4105 bus->head_align = ALIGNMENT;
4106 bus->sgentry_align = ALIGNMENT;
4107 if (sdiodev->pdata) {
4108 if (sdiodev->pdata->sd_head_align > ALIGNMENT)
4109 bus->head_align = sdiodev->pdata->sd_head_align;
4110 if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT)
4111 bus->sgentry_align = sdiodev->pdata->sd_sgentry_align;
4114 /* single-threaded workqueue */
4115 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4116 dev_name(&sdiodev->func[1]->dev));
4118 brcmf_err("insufficient memory to create txworkqueue\n");
4121 brcmf_sdiod_freezer_count(sdiodev);
4122 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4125 /* attempt to attach to the dongle */
4126 if (!(brcmf_sdio_probe_attach(bus))) {
4127 brcmf_err("brcmf_sdio_probe_attach failed\n");
4131 spin_lock_init(&bus->rxctl_lock);
4132 spin_lock_init(&bus->txq_lock);
4133 init_waitqueue_head(&bus->ctrl_wait);
4134 init_waitqueue_head(&bus->dcmd_resp_wait);
4136 /* Set up the watchdog timer */
4137 init_timer(&bus->timer);
4138 bus->timer.data = (unsigned long)bus;
4139 bus->timer.function = brcmf_sdio_watchdog;
4141 /* Initialize watchdog thread */
4142 init_completion(&bus->watchdog_wait);
4143 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4144 bus, "brcmf_wdog/%s",
4145 dev_name(&sdiodev->func[1]->dev));
4146 if (IS_ERR(bus->watchdog_tsk)) {
4147 pr_warn("brcmf_watchdog thread failed to start\n");
4148 bus->watchdog_tsk = NULL;
4150 /* Initialize DPC thread */
4151 atomic_set(&bus->dpc_tskcnt, 0);
4153 /* Assign bus interface call back */
4154 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4155 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4156 bus->sdiodev->bus_if->chip = bus->ci->chip;
4157 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4159 /* default sdio bus header length for tx packet */
4160 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4162 /* Attach to the common layer, reserve hdr space */
4163 ret = brcmf_attach(bus->sdiodev->dev);
4165 brcmf_err("brcmf_attach failed\n");
4169 /* Query the F2 block size, set roundup accordingly */
4170 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4171 bus->roundup = min(max_roundup, bus->blocksize);
4173 /* Allocate buffers */
4174 if (bus->sdiodev->bus_if->maxctl) {
4175 bus->sdiodev->bus_if->maxctl += bus->roundup;
4177 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4178 ALIGNMENT) + bus->head_align;
4179 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4180 if (!(bus->rxbuf)) {
4181 brcmf_err("rxbuf allocation failed\n");
4186 sdio_claim_host(bus->sdiodev->func[1]);
4188 /* Disable F2 to clear any intermediate frame state on the dongle */
4189 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4191 bus->rxflow = false;
4193 /* Done with backplane-dependent accesses, can drop clock... */
4194 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4196 sdio_release_host(bus->sdiodev->func[1]);
4198 /* ...and initialize clock/power states */
4199 bus->clkstate = CLK_SDONLY;
4200 bus->idletime = BRCMF_IDLE_INTERVAL;
4201 bus->idleclock = BRCMF_IDLE_ACTIVE;
4204 bus->sr_enabled = false;
4206 brcmf_sdio_debugfs_create(bus);
4207 brcmf_dbg(INFO, "completed!!\n");
4209 ret = brcmf_sdio_get_fwnames(bus->ci, sdiodev);
4213 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4214 sdiodev->fw_name, sdiodev->nvram_name,
4215 brcmf_sdio_firmware_callback);
4217 brcmf_err("async firmware request failed: %d\n", ret);
4224 brcmf_sdio_remove(bus);
4228 /* Detach and free everything */
4229 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4231 brcmf_dbg(TRACE, "Enter\n");
4234 /* De-register interrupt handler */
4235 brcmf_sdiod_intr_unregister(bus->sdiodev);
4237 brcmf_detach(bus->sdiodev->dev);
4239 cancel_work_sync(&bus->datawork);
4241 destroy_workqueue(bus->brcmf_wq);
4244 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4245 sdio_claim_host(bus->sdiodev->func[1]);
4246 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4247 /* Leave the device in state where it is
4248 * 'quiet'. This is done by putting it in
4249 * download_state which essentially resets
4250 * all necessary cores.
4253 brcmf_chip_enter_download(bus->ci);
4254 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4255 sdio_release_host(bus->sdiodev->func[1]);
4257 brcmf_chip_detach(bus->ci);
4265 brcmf_dbg(TRACE, "Disconnected\n");
4268 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
4270 /* Totally stop the timer */
4271 if (!wdtick && bus->wd_timer_valid) {
4272 del_timer_sync(&bus->timer);
4273 bus->wd_timer_valid = false;
4274 bus->save_ms = wdtick;
4278 /* don't start the wd until fw is loaded */
4279 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4283 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4284 if (bus->wd_timer_valid)
4285 /* Stop timer and restart at new value */
4286 del_timer_sync(&bus->timer);
4288 /* Create timer again when watchdog period is
4289 dynamically changed or in the first instance
4291 bus->timer.expires =
4292 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS);
4293 add_timer(&bus->timer);
4296 /* Re arm the timer, at last watchdog period */
4297 mod_timer(&bus->timer,
4298 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
4301 bus->wd_timer_valid = true;
4302 bus->save_ms = wdtick;
4306 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4310 sdio_claim_host(bus->sdiodev->func[1]);
4311 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4312 sdio_release_host(bus->sdiodev->func[1]);
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