2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
48 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
49 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
53 #define BRCMF_TRAP_INFO_SIZE 80
55 #define CBUF_LEN (128)
57 /* Device console log buffer state */
58 #define CONSOLE_BUFFER_MAX 2024
61 __le32 buf; /* Can't be pointer on (64-bit) hosts */
64 char *_buf_compat; /* Redundant pointer for backward compat. */
69 * When there is no UART (e.g. Quickturn),
70 * the host should write a complete
71 * input line directly into cbuf and then write
72 * the length into vcons_in.
73 * This may also be used when there is a real UART
74 * (at risk of conflicting with
75 * the real UART). vcons_out is currently unused.
80 /* Output (logging) buffer
81 * Console output is written to a ring buffer log_buf at index log_idx.
82 * The host may read the output when it sees log_idx advance.
83 * Output will be lost if the output wraps around faster than the host
86 struct rte_log_le log_le;
88 /* Console input line buffer
89 * Characters are read one at a time into cbuf
90 * until <CR> is received, then
91 * the buffer is processed as a command line.
92 * Also used for virtual UART.
99 #include <chipcommon.h>
103 #include "tracepoint.h"
105 #define TXQLEN 2048 /* bulk tx queue length */
106 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
107 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
110 #define TXRETRIES 2 /* # of retries for tx frames */
112 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
115 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
118 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
120 #define MEMBLOCK 2048 /* Block size used for downloading
122 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
123 biggest possible glom */
125 #define BRCMF_FIRSTREAD (1 << 6)
127 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
129 /* SBSDIO_DEVICE_CTL */
131 /* 1: device will assert busy signal when receiving CMD53 */
132 #define SBSDIO_DEVCTL_SETBUSY 0x01
133 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
134 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
135 /* 1: mask all interrupts to host except the chipActive (rev 8) */
136 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
137 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
138 * sdio bus power cycle to clear (rev 9) */
139 #define SBSDIO_DEVCTL_PADS_ISO 0x08
140 /* Force SD->SB reset mapping (rev 11) */
141 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
142 /* Determined by CoreControl bit */
143 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
144 /* Force backplane reset */
145 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
146 /* Force no backplane reset */
147 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
149 /* direct(mapped) cis space */
151 /* MAPPED common CIS address */
152 #define SBSDIO_CIS_BASE_COMMON 0x1000
153 /* maximum bytes in one CIS */
154 #define SBSDIO_CIS_SIZE_LIMIT 0x200
155 /* cis offset addr is < 17 bits */
156 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
158 /* manfid tuple length, include tuple, link bytes */
159 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
161 #define CORE_BUS_REG(base, field) \
162 (base + offsetof(struct sdpcmd_regs, field))
164 /* SDIO function 1 register CHIPCLKCSR */
165 /* Force ALP request to backplane */
166 #define SBSDIO_FORCE_ALP 0x01
167 /* Force HT request to backplane */
168 #define SBSDIO_FORCE_HT 0x02
169 /* Force ILP request to backplane */
170 #define SBSDIO_FORCE_ILP 0x04
171 /* Make ALP ready (power up xtal) */
172 #define SBSDIO_ALP_AVAIL_REQ 0x08
173 /* Make HT ready (power up PLL) */
174 #define SBSDIO_HT_AVAIL_REQ 0x10
175 /* Squelch clock requests from HW */
176 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
177 /* Status: ALP is ready */
178 #define SBSDIO_ALP_AVAIL 0x40
179 /* Status: HT is ready */
180 #define SBSDIO_HT_AVAIL 0x80
181 #define SBSDIO_CSR_MASK 0x1F
182 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
183 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
184 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
185 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
186 #define SBSDIO_CLKAV(regval, alponly) \
187 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
190 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
191 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
192 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
193 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
194 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
195 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
196 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
197 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
198 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
199 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
200 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
201 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
202 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
203 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
204 #define I_PC (1 << 10) /* descriptor error */
205 #define I_PD (1 << 11) /* data error */
206 #define I_DE (1 << 12) /* Descriptor protocol Error */
207 #define I_RU (1 << 13) /* Receive descriptor Underflow */
208 #define I_RO (1 << 14) /* Receive fifo Overflow */
209 #define I_XU (1 << 15) /* Transmit fifo Underflow */
210 #define I_RI (1 << 16) /* Receive Interrupt */
211 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
212 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
213 #define I_XI (1 << 24) /* Transmit Interrupt */
214 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
215 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
216 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
217 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
218 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
219 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
220 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
221 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
222 #define I_DMA (I_RI | I_XI | I_ERRORS)
225 #define CC_CISRDY (1 << 0) /* CIS Ready */
226 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
227 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
228 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
229 #define CC_XMTDATAAVAIL_MODE (1 << 4)
230 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
233 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
234 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
235 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
236 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
239 * Software allocation of To SB Mailbox resources
242 /* tosbmailbox bits corresponding to intstatus bits */
243 #define SMB_NAK (1 << 0) /* Frame NAK */
244 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
245 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
246 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
248 /* tosbmailboxdata */
249 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
252 * Software allocation of To Host Mailbox resources
256 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
257 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
258 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
259 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
261 /* tohostmailboxdata */
262 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
263 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
264 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
265 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
267 #define HMB_DATA_FCDATA_MASK 0xff000000
268 #define HMB_DATA_FCDATA_SHIFT 24
270 #define HMB_DATA_VERSION_MASK 0x00ff0000
271 #define HMB_DATA_VERSION_SHIFT 16
274 * Software-defined protocol header
277 /* Current protocol version */
278 #define SDPCM_PROT_VERSION 4
281 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information.
284 #define SDPCM_SHARED_VERSION 0x0003
285 #define SDPCM_SHARED_VERSION_MASK 0x00FF
286 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
287 #define SDPCM_SHARED_ASSERT 0x0200
288 #define SDPCM_SHARED_TRAP 0x0400
290 /* Space for header read, limit for data packets */
291 #define MAX_HDR_READ (1 << 6)
292 #define MAX_RX_DATASZ 2048
294 /* Bump up limit on waiting for HT to account for first startup;
295 * if the image is doing a CRC calculation before programming the PMU
296 * for HT availability, it could take a couple hundred ms more, so
297 * max out at a 1 second (1000000us).
299 #undef PMU_MAX_TRANSITION_DLY
300 #define PMU_MAX_TRANSITION_DLY 1000000
302 /* Value for ChipClockCSR during initial setup */
303 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
304 SBSDIO_ALP_AVAIL_REQ)
306 /* Flags for SDH calls */
307 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
309 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
312 #define BRCMF_IDLE_INTERVAL 1
314 #define KSO_WAIT_US 50
315 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
318 * Conversion of 802.1D priority to precedence level
320 static uint prio2prec(u32 prio)
322 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
327 /* Device console log buffer state */
328 struct brcmf_console {
329 uint count; /* Poll interval msec counter */
330 uint log_addr; /* Log struct address (fixed) */
331 struct rte_log_le log_le; /* Log struct (host copy) */
332 uint bufsize; /* Size of log buffer */
333 u8 *buf; /* Log buffer (host copy) */
334 uint last; /* Last buffer read index */
337 struct brcmf_trap_info {
351 __le32 r9; /* sb/v6 */
352 __le32 r10; /* sl/v7 */
353 __le32 r11; /* fp/v8 */
361 struct sdpcm_shared {
365 u32 assert_file_addr;
367 u32 console_addr; /* Address of struct rte_console */
373 struct sdpcm_shared_le {
376 __le32 assert_exp_addr;
377 __le32 assert_file_addr;
379 __le32 console_addr; /* Address of struct rte_console */
380 __le32 msgtrace_addr;
385 /* dongle SDIO bus specific header info */
386 struct brcmf_sdio_hdrinfo {
398 * hold counter variables
400 struct brcmf_sdio_count {
401 uint intrcount; /* Count of device interrupt callbacks */
402 uint lastintrs; /* Count as of last watchdog timer */
403 uint pollcnt; /* Count of active polls */
404 uint regfails; /* Count of R_REG failures */
405 uint tx_sderrs; /* Count of tx attempts with sd errors */
406 uint fcqueued; /* Tx packets that got queued */
407 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
408 uint rx_toolong; /* Receive frames too long to receive */
409 uint rxc_errors; /* SDIO errors when reading control frames */
410 uint rx_hdrfail; /* SDIO errors on header reads */
411 uint rx_badhdr; /* Bad received headers (roosync?) */
412 uint rx_badseq; /* Mismatched rx sequence number */
413 uint fc_rcvd; /* Number of flow-control events received */
414 uint fc_xoff; /* Number which turned on flow-control */
415 uint fc_xon; /* Number which turned off flow-control */
416 uint rxglomfail; /* Failed deglom attempts */
417 uint rxglomframes; /* Number of glom frames (superframes) */
418 uint rxglompkts; /* Number of packets from glom frames */
419 uint f2rxhdrs; /* Number of header reads */
420 uint f2rxdata; /* Number of frame data reads */
421 uint f2txdata; /* Number of f2 frame writes */
422 uint f1regdata; /* Number of f1 register accesses */
423 uint tickcnt; /* Number of watchdog been schedule */
424 ulong tx_ctlerrs; /* Err of sending ctrl frames */
425 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
426 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
427 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
428 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
431 /* misc chip info needed by some of the routines */
432 /* Private data for SDIO bus interaction */
434 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
435 struct brcmf_chip *ci; /* Chip info struct */
437 u32 hostintmask; /* Copy of Host Interrupt Mask */
438 atomic_t intstatus; /* Intstatus bits (events) pending */
439 atomic_t fcstate; /* State of dongle flow-control */
441 uint blocksize; /* Block size of SDIO transfers */
442 uint roundup; /* Max roundup limit */
444 struct pktq txq; /* Queue length used for flow-control */
445 u8 flowcontrol; /* per prio flow control bitmask */
446 u8 tx_seq; /* Transmit sequence number (next) */
447 u8 tx_max; /* Maximum transmit sequence allowed */
449 u8 *hdrbuf; /* buffer for handling rx frame */
450 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
451 u8 rx_seq; /* Receive sequence number (expected) */
452 struct brcmf_sdio_hdrinfo cur_read;
453 /* info of current read frame */
454 bool rxskip; /* Skip receive (awaiting NAK ACK) */
455 bool rxpending; /* Data frame pending in dongle */
457 uint rxbound; /* Rx frames to read before resched */
458 uint txbound; /* Tx frames to send before resched */
461 struct sk_buff *glomd; /* Packet containing glomming descriptor */
462 struct sk_buff_head glom; /* Packet list for glommed superframe */
464 u8 *rxbuf; /* Buffer for receiving control packets */
465 uint rxblen; /* Allocated length of rxbuf */
466 u8 *rxctl; /* Aligned pointer into rxbuf */
467 u8 *rxctl_orig; /* pointer for freeing rxctl */
468 uint rxlen; /* Length of valid data in buffer */
469 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
471 u8 sdpcm_ver; /* Bus protocol reported by dongle */
473 bool intr; /* Use interrupts */
474 bool poll; /* Use polling */
475 atomic_t ipend; /* Device interrupt is pending */
476 uint spurious; /* Count of spurious interrupts */
477 uint pollrate; /* Ticks between device polls */
478 uint polltick; /* Tick counter */
481 uint console_interval;
482 struct brcmf_console console; /* Console output polling support */
483 uint console_addr; /* Console address from shared struct */
486 uint clkstate; /* State of sd and backplane clock(s) */
487 s32 idletime; /* Control for activity timeout */
488 s32 idlecount; /* Activity timeout counter */
489 s32 idleclock; /* How to set bus driver when idle */
490 bool rxflow_mode; /* Rx flow control mode */
491 bool rxflow; /* Is rx flow control on */
492 bool alp_only; /* Don't use HT clock (ALP only) */
496 bool ctrl_frame_stat;
499 spinlock_t txq_lock; /* protect bus->txq */
500 wait_queue_head_t ctrl_wait;
501 wait_queue_head_t dcmd_resp_wait;
503 struct timer_list timer;
504 struct completion watchdog_wait;
505 struct task_struct *watchdog_tsk;
508 struct workqueue_struct *brcmf_wq;
509 struct work_struct datawork;
513 bool txoff; /* Transmit flow-controlled */
514 struct brcmf_sdio_count sdcnt;
515 bool sr_enabled; /* SaveRestore enabled */
518 u8 tx_hdrlen; /* sdio bus header length for tx packet */
519 bool txglom; /* host tx glomming enable flag */
520 u16 head_align; /* buffer pointer alignment */
521 u16 sgentry_align; /* scatter-gather buffer alignment */
527 #define CLK_PENDING 2
531 static int qcount[NUMPRIO];
534 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
536 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
538 /* Limit on rounding up frames */
539 static const uint max_roundup = 512;
543 enum brcmf_sdio_frmtype {
544 BRCMF_SDIO_FT_NORMAL,
549 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
551 /* SDIO Pad drive strength to select value mappings */
552 struct sdiod_drive_str {
553 u8 strength; /* Pad Drive Strength in mA */
554 u8 sel; /* Chip-specific select value */
557 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
558 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
569 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
570 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
580 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
581 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
587 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
588 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
595 BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt");
596 BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin",
597 "brcmfmac43241b0-sdio.txt");
598 BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin",
599 "brcmfmac43241b4-sdio.txt");
600 BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin",
601 "brcmfmac43241b5-sdio.txt");
602 BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt");
603 BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt");
604 BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt");
605 BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt");
606 BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt");
607 BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt");
608 BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt");
609 BRCMF_FW_NVRAM_DEF(43430, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt");
610 BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt");
611 BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt");
613 static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
614 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
615 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
616 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
617 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
618 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
619 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
620 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
621 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
622 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
623 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
624 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
625 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, 43430),
626 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
627 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354)
630 static void pkt_align(struct sk_buff *p, int len, int align)
633 datalign = (unsigned long)(p->data);
634 datalign = roundup(datalign, (align)) - datalign;
636 skb_pull(p, datalign);
640 /* To check if there's window offered */
641 static bool data_ok(struct brcmf_sdio *bus)
643 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
644 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
648 * Reads a register in the SDIO hardware block. This block occupies a series of
649 * adresses on the 32 bit backplane bus.
651 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
653 struct brcmf_core *core;
656 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
657 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
662 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
664 struct brcmf_core *core;
667 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
668 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
674 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
676 u8 wr_val = 0, rd_val, cmp_val, bmask;
680 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
682 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
683 /* 1st KSO write goes to AOS wake up core if device is asleep */
684 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
688 /* device WAKEUP through KSO:
689 * write bit 0 & read back until
690 * both bits 0 (kso bit) & 1 (dev on status) are set
692 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
693 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
695 usleep_range(2000, 3000);
697 /* Put device to sleep, turn off KSO */
699 /* only check for bit0, bit1(dev on status) may not
700 * get cleared right away
702 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
706 /* reliable KSO bit set/clr:
707 * the sdiod sleep write access is synced to PMU 32khz clk
708 * just one write attempt may fail,
709 * read it back until it matches written value
711 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
713 if (((rd_val & bmask) == cmp_val) && !err)
717 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
719 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
722 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
725 if (try_cnt > MAX_KSO_ATTEMPTS)
726 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
731 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
733 /* Turn backplane clock on or off */
734 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
737 u8 clkctl, clkreq, devctl;
738 unsigned long timeout;
740 brcmf_dbg(SDIO, "Enter\n");
744 if (bus->sr_enabled) {
745 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
750 /* Request HT Avail */
752 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
754 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
757 brcmf_err("HT Avail request error: %d\n", err);
761 /* Check current status */
762 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
763 SBSDIO_FUNC1_CHIPCLKCSR, &err);
765 brcmf_err("HT Avail read error: %d\n", err);
769 /* Go to pending and await interrupt if appropriate */
770 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
771 /* Allow only clock-available interrupt */
772 devctl = brcmf_sdiod_regrb(bus->sdiodev,
773 SBSDIO_DEVICE_CTL, &err);
775 brcmf_err("Devctl error setting CA: %d\n",
780 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
781 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
783 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
784 bus->clkstate = CLK_PENDING;
787 } else if (bus->clkstate == CLK_PENDING) {
788 /* Cancel CA-only interrupt filter */
789 devctl = brcmf_sdiod_regrb(bus->sdiodev,
790 SBSDIO_DEVICE_CTL, &err);
791 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
792 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
796 /* Otherwise, wait here (polling) for HT Avail */
798 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
799 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
800 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
801 SBSDIO_FUNC1_CHIPCLKCSR,
803 if (time_after(jiffies, timeout))
806 usleep_range(5000, 10000);
809 brcmf_err("HT Avail request error: %d\n", err);
812 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
813 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
814 PMU_MAX_TRANSITION_DLY, clkctl);
818 /* Mark clock available */
819 bus->clkstate = CLK_AVAIL;
820 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
823 if (!bus->alp_only) {
824 if (SBSDIO_ALPONLY(clkctl))
825 brcmf_err("HT Clock should be on\n");
827 #endif /* defined (DEBUG) */
832 if (bus->clkstate == CLK_PENDING) {
833 /* Cancel CA-only interrupt filter */
834 devctl = brcmf_sdiod_regrb(bus->sdiodev,
835 SBSDIO_DEVICE_CTL, &err);
836 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
837 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
841 bus->clkstate = CLK_SDONLY;
842 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
844 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
846 brcmf_err("Failed access turning clock off: %d\n",
854 /* Change idle/active SD state */
855 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
857 brcmf_dbg(SDIO, "Enter\n");
860 bus->clkstate = CLK_SDONLY;
862 bus->clkstate = CLK_NONE;
867 /* Transition SD and backplane clock readiness */
868 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
871 uint oldstate = bus->clkstate;
874 brcmf_dbg(SDIO, "Enter\n");
876 /* Early exit if we're already there */
877 if (bus->clkstate == target)
882 /* Make sure SD clock is available */
883 if (bus->clkstate == CLK_NONE)
884 brcmf_sdio_sdclk(bus, true);
885 /* Now request HT Avail on the backplane */
886 brcmf_sdio_htclk(bus, true, pendok);
890 /* Remove HT request, or bring up SD clock */
891 if (bus->clkstate == CLK_NONE)
892 brcmf_sdio_sdclk(bus, true);
893 else if (bus->clkstate == CLK_AVAIL)
894 brcmf_sdio_htclk(bus, false, false);
896 brcmf_err("request for %d -> %d\n",
897 bus->clkstate, target);
901 /* Make sure to remove HT request */
902 if (bus->clkstate == CLK_AVAIL)
903 brcmf_sdio_htclk(bus, false, false);
904 /* Now remove the SD clock */
905 brcmf_sdio_sdclk(bus, false);
909 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
916 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
921 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
922 (sleep ? "SLEEP" : "WAKE"),
923 (bus->sleeping ? "SLEEP" : "WAKE"));
925 /* If SR is enabled control bus state with KSO */
926 if (bus->sr_enabled) {
927 /* Done if we're already in the requested state */
928 if (sleep == bus->sleeping)
933 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
934 SBSDIO_FUNC1_CHIPCLKCSR,
936 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
937 brcmf_dbg(SDIO, "no clock, set ALP\n");
938 brcmf_sdiod_regwb(bus->sdiodev,
939 SBSDIO_FUNC1_CHIPCLKCSR,
940 SBSDIO_ALP_AVAIL_REQ, &err);
942 err = brcmf_sdio_kso_control(bus, false);
944 err = brcmf_sdio_kso_control(bus, true);
947 brcmf_err("error while changing bus sleep state %d\n",
956 if (!bus->sr_enabled)
957 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
959 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
960 brcmf_sdio_wd_timer(bus, true);
962 bus->sleeping = sleep;
963 brcmf_dbg(SDIO, "new state %s\n",
964 (sleep ? "SLEEP" : "WAKE"));
966 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
972 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
974 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
977 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
978 struct sdpcm_shared *sh)
983 struct sdpcm_shared_le sh_le;
986 sdio_claim_host(bus->sdiodev->func[1]);
987 brcmf_sdio_bus_sleep(bus, false, false);
990 * Read last word in socram to determine
991 * address of sdpcm_shared structure
993 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
994 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
995 shaddr -= bus->ci->srsize;
996 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1002 * Check if addr is valid.
1003 * NVRAM length at the end of memory should have been overwritten.
1005 addr = le32_to_cpu(addr_le);
1006 if (!brcmf_sdio_valid_shared_address(addr)) {
1007 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1012 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1014 /* Read hndrte_shared structure */
1015 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1016 sizeof(struct sdpcm_shared_le));
1020 sdio_release_host(bus->sdiodev->func[1]);
1023 sh->flags = le32_to_cpu(sh_le.flags);
1024 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1025 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1026 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1027 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1028 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1029 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1031 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1032 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1033 SDPCM_SHARED_VERSION,
1034 sh->flags & SDPCM_SHARED_VERSION_MASK);
1040 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1042 sdio_release_host(bus->sdiodev->func[1]);
1046 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1048 struct sdpcm_shared sh;
1050 if (brcmf_sdio_readshared(bus, &sh) == 0)
1051 bus->console_addr = sh.console_addr;
1054 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1059 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1066 brcmf_dbg(SDIO, "Enter\n");
1068 /* Read mailbox data and ack that we did so */
1069 ret = r_sdreg32(bus, &hmb_data,
1070 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1073 w_sdreg32(bus, SMB_INT_ACK,
1074 offsetof(struct sdpcmd_regs, tosbmailbox));
1075 bus->sdcnt.f1regdata += 2;
1077 /* Dongle recomposed rx frames, accept them again */
1078 if (hmb_data & HMB_DATA_NAKHANDLED) {
1079 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1082 brcmf_err("unexpected NAKHANDLED!\n");
1084 bus->rxskip = false;
1085 intstatus |= I_HMB_FRAME_IND;
1089 * DEVREADY does not occur with gSPI.
1091 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1093 (hmb_data & HMB_DATA_VERSION_MASK) >>
1094 HMB_DATA_VERSION_SHIFT;
1095 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1096 brcmf_err("Version mismatch, dongle reports %d, "
1098 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1100 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1104 * Retrieve console state address now that firmware should have
1107 brcmf_sdio_get_console_addr(bus);
1111 * Flow Control has been moved into the RX headers and this out of band
1112 * method isn't used any more.
1113 * remaining backward compatible with older dongles.
1115 if (hmb_data & HMB_DATA_FC) {
1116 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1117 HMB_DATA_FCDATA_SHIFT;
1119 if (fcbits & ~bus->flowcontrol)
1120 bus->sdcnt.fc_xoff++;
1122 if (bus->flowcontrol & ~fcbits)
1123 bus->sdcnt.fc_xon++;
1125 bus->sdcnt.fc_rcvd++;
1126 bus->flowcontrol = fcbits;
1129 /* Shouldn't be any others */
1130 if (hmb_data & ~(HMB_DATA_DEVREADY |
1131 HMB_DATA_NAKHANDLED |
1134 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1135 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1141 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1148 brcmf_err("%sterminate frame%s\n",
1149 abort ? "abort command, " : "",
1150 rtx ? ", send NAK" : "");
1153 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1155 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1157 bus->sdcnt.f1regdata++;
1159 /* Wait until the packet has been flushed (device/FIFO stable) */
1160 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1161 hi = brcmf_sdiod_regrb(bus->sdiodev,
1162 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1163 lo = brcmf_sdiod_regrb(bus->sdiodev,
1164 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1165 bus->sdcnt.f1regdata += 2;
1167 if ((hi == 0) && (lo == 0))
1170 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1171 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1172 lastrbc, (hi << 8) + lo);
1174 lastrbc = (hi << 8) + lo;
1178 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1180 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1184 err = w_sdreg32(bus, SMB_NAK,
1185 offsetof(struct sdpcmd_regs, tosbmailbox));
1187 bus->sdcnt.f1regdata++;
1192 /* Clear partial in any case */
1193 bus->cur_read.len = 0;
1196 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1198 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1201 /* On failure, abort the command and terminate the frame */
1202 brcmf_err("sdio error, abort command and terminate frame\n");
1203 bus->sdcnt.tx_sderrs++;
1205 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1206 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1207 bus->sdcnt.f1regdata++;
1209 for (i = 0; i < 3; i++) {
1210 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1211 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1212 bus->sdcnt.f1regdata += 2;
1213 if ((hi == 0) && (lo == 0))
1218 /* return total length of buffer chain */
1219 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1225 skb_queue_walk(&bus->glom, p)
1230 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1232 struct sk_buff *cur, *next;
1234 skb_queue_walk_safe(&bus->glom, cur, next) {
1235 skb_unlink(cur, &bus->glom);
1236 brcmu_pkt_buf_free_skb(cur);
1241 * brcmfmac sdio bus specific header
1242 * This is the lowest layer header wrapped on the packets transmitted between
1243 * host and WiFi dongle which contains information needed for SDIO core and
1246 * It consists of 3 parts: hardware header, hardware extension header and
1248 * hardware header (frame tag) - 4 bytes
1249 * Byte 0~1: Frame length
1250 * Byte 2~3: Checksum, bit-wise inverse of frame length
1251 * hardware extension header - 8 bytes
1252 * Tx glom mode only, N/A for Rx or normal Tx
1253 * Byte 0~1: Packet length excluding hw frame tag
1255 * Byte 3: Frame flags, bit 0: last frame indication
1256 * Byte 4~5: Reserved
1257 * Byte 6~7: Tail padding length
1258 * software header - 8 bytes
1259 * Byte 0: Rx/Tx sequence number
1260 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1261 * Byte 2: Length of next data frame, reserved for Tx
1262 * Byte 3: Data offset
1263 * Byte 4: Flow control bits, reserved for Tx
1264 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1265 * Byte 6~7: Reserved
1267 #define SDPCM_HWHDR_LEN 4
1268 #define SDPCM_HWEXT_LEN 8
1269 #define SDPCM_SWHDR_LEN 8
1270 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1271 /* software header */
1272 #define SDPCM_SEQ_MASK 0x000000ff
1273 #define SDPCM_SEQ_WRAP 256
1274 #define SDPCM_CHANNEL_MASK 0x00000f00
1275 #define SDPCM_CHANNEL_SHIFT 8
1276 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1277 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1278 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1279 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1280 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1281 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1282 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1283 #define SDPCM_NEXTLEN_SHIFT 16
1284 #define SDPCM_DOFFSET_MASK 0xff000000
1285 #define SDPCM_DOFFSET_SHIFT 24
1286 #define SDPCM_FCMASK_MASK 0x000000ff
1287 #define SDPCM_WINDOW_MASK 0x0000ff00
1288 #define SDPCM_WINDOW_SHIFT 8
1290 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1293 hdrvalue = *(u32 *)swheader;
1294 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1297 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1298 struct brcmf_sdio_hdrinfo *rd,
1299 enum brcmf_sdio_frmtype type)
1302 u8 rx_seq, fc, tx_seq_max;
1305 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1308 len = get_unaligned_le16(header);
1309 checksum = get_unaligned_le16(header + sizeof(u16));
1310 /* All zero means no more to read */
1311 if (!(len | checksum)) {
1312 bus->rxpending = false;
1315 if ((u16)(~(len ^ checksum))) {
1316 brcmf_err("HW header checksum error\n");
1317 bus->sdcnt.rx_badhdr++;
1318 brcmf_sdio_rxfail(bus, false, false);
1321 if (len < SDPCM_HDRLEN) {
1322 brcmf_err("HW header length error\n");
1325 if (type == BRCMF_SDIO_FT_SUPER &&
1326 (roundup(len, bus->blocksize) != rd->len)) {
1327 brcmf_err("HW superframe header length error\n");
1330 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1331 brcmf_err("HW subframe header length error\n");
1336 /* software header */
1337 header += SDPCM_HWHDR_LEN;
1338 swheader = le32_to_cpu(*(__le32 *)header);
1339 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1340 brcmf_err("Glom descriptor found in superframe head\n");
1344 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1345 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1346 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1347 type != BRCMF_SDIO_FT_SUPER) {
1348 brcmf_err("HW header length too long\n");
1349 bus->sdcnt.rx_toolong++;
1350 brcmf_sdio_rxfail(bus, false, false);
1354 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1355 brcmf_err("Wrong channel for superframe\n");
1359 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1360 rd->channel != SDPCM_EVENT_CHANNEL) {
1361 brcmf_err("Wrong channel for subframe\n");
1365 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1366 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1367 brcmf_err("seq %d: bad data offset\n", rx_seq);
1368 bus->sdcnt.rx_badhdr++;
1369 brcmf_sdio_rxfail(bus, false, false);
1373 if (rd->seq_num != rx_seq) {
1374 brcmf_err("seq %d: sequence number error, expect %d\n",
1375 rx_seq, rd->seq_num);
1376 bus->sdcnt.rx_badseq++;
1377 rd->seq_num = rx_seq;
1379 /* no need to check the reset for subframe */
1380 if (type == BRCMF_SDIO_FT_SUB)
1382 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1383 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1384 /* only warm for NON glom packet */
1385 if (rd->channel != SDPCM_GLOM_CHANNEL)
1386 brcmf_err("seq %d: next length error\n", rx_seq);
1389 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1390 fc = swheader & SDPCM_FCMASK_MASK;
1391 if (bus->flowcontrol != fc) {
1392 if (~bus->flowcontrol & fc)
1393 bus->sdcnt.fc_xoff++;
1394 if (bus->flowcontrol & ~fc)
1395 bus->sdcnt.fc_xon++;
1396 bus->sdcnt.fc_rcvd++;
1397 bus->flowcontrol = fc;
1399 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1400 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1401 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1402 tx_seq_max = bus->tx_seq + 2;
1404 bus->tx_max = tx_seq_max;
1409 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1411 *(__le16 *)header = cpu_to_le16(frm_length);
1412 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1415 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1416 struct brcmf_sdio_hdrinfo *hd_info)
1421 brcmf_sdio_update_hwhdr(header, hd_info->len);
1422 hdr_offset = SDPCM_HWHDR_LEN;
1425 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1426 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1427 hdrval = (u16)hd_info->tail_pad << 16;
1428 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1429 hdr_offset += SDPCM_HWEXT_LEN;
1432 hdrval = hd_info->seq_num;
1433 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1435 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1437 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1438 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1439 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1442 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1447 struct sk_buff *pfirst, *pnext;
1452 struct brcmf_sdio_hdrinfo rd_new;
1454 /* If packets, issue read(s) and send up packet chain */
1455 /* Return sequence numbers consumed? */
1457 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1458 bus->glomd, skb_peek(&bus->glom));
1460 /* If there's a descriptor, generate the packet chain */
1462 pfirst = pnext = NULL;
1463 dlen = (u16) (bus->glomd->len);
1464 dptr = bus->glomd->data;
1465 if (!dlen || (dlen & 1)) {
1466 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1471 for (totlen = num = 0; dlen; num++) {
1472 /* Get (and move past) next length */
1473 sublen = get_unaligned_le16(dptr);
1474 dlen -= sizeof(u16);
1475 dptr += sizeof(u16);
1476 if ((sublen < SDPCM_HDRLEN) ||
1477 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1478 brcmf_err("descriptor len %d bad: %d\n",
1483 if (sublen % bus->sgentry_align) {
1484 brcmf_err("sublen %d not multiple of %d\n",
1485 sublen, bus->sgentry_align);
1489 /* For last frame, adjust read len so total
1490 is a block multiple */
1493 (roundup(totlen, bus->blocksize) - totlen);
1494 totlen = roundup(totlen, bus->blocksize);
1497 /* Allocate/chain packet for next subframe */
1498 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1499 if (pnext == NULL) {
1500 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1504 skb_queue_tail(&bus->glom, pnext);
1506 /* Adhere to start alignment requirements */
1507 pkt_align(pnext, sublen, bus->sgentry_align);
1510 /* If all allocations succeeded, save packet chain
1513 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1515 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1516 totlen != bus->cur_read.len) {
1517 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1518 bus->cur_read.len, totlen, rxseq);
1520 pfirst = pnext = NULL;
1522 brcmf_sdio_free_glom(bus);
1526 /* Done with descriptor packet */
1527 brcmu_pkt_buf_free_skb(bus->glomd);
1529 bus->cur_read.len = 0;
1532 /* Ok -- either we just generated a packet chain,
1533 or had one from before */
1534 if (!skb_queue_empty(&bus->glom)) {
1535 if (BRCMF_GLOM_ON()) {
1536 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1537 skb_queue_walk(&bus->glom, pnext) {
1538 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1539 pnext, (u8 *) (pnext->data),
1540 pnext->len, pnext->len);
1544 pfirst = skb_peek(&bus->glom);
1545 dlen = (u16) brcmf_sdio_glom_len(bus);
1547 /* Do an SDIO read for the superframe. Configurable iovar to
1548 * read directly into the chained packet, or allocate a large
1549 * packet and and copy into the chain.
1551 sdio_claim_host(bus->sdiodev->func[1]);
1552 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1554 sdio_release_host(bus->sdiodev->func[1]);
1555 bus->sdcnt.f2rxdata++;
1557 /* On failure, kill the superframe */
1559 brcmf_err("glom read of %d bytes failed: %d\n",
1562 sdio_claim_host(bus->sdiodev->func[1]);
1563 brcmf_sdio_rxfail(bus, true, false);
1564 bus->sdcnt.rxglomfail++;
1565 brcmf_sdio_free_glom(bus);
1566 sdio_release_host(bus->sdiodev->func[1]);
1570 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1571 pfirst->data, min_t(int, pfirst->len, 48),
1574 rd_new.seq_num = rxseq;
1576 sdio_claim_host(bus->sdiodev->func[1]);
1577 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1578 BRCMF_SDIO_FT_SUPER);
1579 sdio_release_host(bus->sdiodev->func[1]);
1580 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1582 /* Remove superframe header, remember offset */
1583 skb_pull(pfirst, rd_new.dat_offset);
1584 sfdoff = rd_new.dat_offset;
1587 /* Validate all the subframe headers */
1588 skb_queue_walk(&bus->glom, pnext) {
1589 /* leave when invalid subframe is found */
1593 rd_new.len = pnext->len;
1594 rd_new.seq_num = rxseq++;
1595 sdio_claim_host(bus->sdiodev->func[1]);
1596 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1598 sdio_release_host(bus->sdiodev->func[1]);
1599 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1600 pnext->data, 32, "subframe:\n");
1606 /* Terminate frame on error */
1607 sdio_claim_host(bus->sdiodev->func[1]);
1608 brcmf_sdio_rxfail(bus, true, false);
1609 bus->sdcnt.rxglomfail++;
1610 brcmf_sdio_free_glom(bus);
1611 sdio_release_host(bus->sdiodev->func[1]);
1612 bus->cur_read.len = 0;
1616 /* Basic SD framing looks ok - process each packet (header) */
1618 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1619 dptr = (u8 *) (pfirst->data);
1620 sublen = get_unaligned_le16(dptr);
1621 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1623 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1625 "Rx Subframe Data:\n");
1627 __skb_trim(pfirst, sublen);
1628 skb_pull(pfirst, doff);
1630 if (pfirst->len == 0) {
1631 skb_unlink(pfirst, &bus->glom);
1632 brcmu_pkt_buf_free_skb(pfirst);
1636 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1638 min_t(int, pfirst->len, 32),
1639 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1640 bus->glom.qlen, pfirst, pfirst->data,
1641 pfirst->len, pfirst->next,
1643 skb_unlink(pfirst, &bus->glom);
1644 brcmf_rx_frame(bus->sdiodev->dev, pfirst);
1645 bus->sdcnt.rxglompkts++;
1648 bus->sdcnt.rxglomframes++;
1653 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1656 DECLARE_WAITQUEUE(wait, current);
1657 int timeout = DCMD_RESP_TIMEOUT;
1659 /* Wait until control frame is available */
1660 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1661 set_current_state(TASK_INTERRUPTIBLE);
1663 while (!(*condition) && (!signal_pending(current) && timeout))
1664 timeout = schedule_timeout(timeout);
1666 if (signal_pending(current))
1669 set_current_state(TASK_RUNNING);
1670 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1675 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1677 wake_up_interruptible(&bus->dcmd_resp_wait);
1682 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1685 u8 *buf = NULL, *rbuf;
1688 brcmf_dbg(TRACE, "Enter\n");
1691 buf = vzalloc(bus->rxblen);
1696 pad = ((unsigned long)rbuf % bus->head_align);
1698 rbuf += (bus->head_align - pad);
1700 /* Copy the already-read portion over */
1701 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1702 if (len <= BRCMF_FIRSTREAD)
1705 /* Raise rdlen to next SDIO block to avoid tail command */
1706 rdlen = len - BRCMF_FIRSTREAD;
1707 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1708 pad = bus->blocksize - (rdlen % bus->blocksize);
1709 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1710 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1712 } else if (rdlen % bus->head_align) {
1713 rdlen += bus->head_align - (rdlen % bus->head_align);
1716 /* Drop if the read is too big or it exceeds our maximum */
1717 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1718 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1719 rdlen, bus->sdiodev->bus_if->maxctl);
1720 brcmf_sdio_rxfail(bus, false, false);
1724 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1725 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1726 len, len - doff, bus->sdiodev->bus_if->maxctl);
1727 bus->sdcnt.rx_toolong++;
1728 brcmf_sdio_rxfail(bus, false, false);
1732 /* Read remain of frame body */
1733 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1734 bus->sdcnt.f2rxdata++;
1736 /* Control frame failures need retransmission */
1738 brcmf_err("read %d control bytes failed: %d\n",
1740 bus->sdcnt.rxc_errors++;
1741 brcmf_sdio_rxfail(bus, true, true);
1744 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1748 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1749 buf, len, "RxCtrl:\n");
1751 /* Point to valid data and indicate its length */
1752 spin_lock_bh(&bus->rxctl_lock);
1754 brcmf_err("last control frame is being processed.\n");
1755 spin_unlock_bh(&bus->rxctl_lock);
1759 bus->rxctl = buf + doff;
1760 bus->rxctl_orig = buf;
1761 bus->rxlen = len - doff;
1762 spin_unlock_bh(&bus->rxctl_lock);
1765 /* Awake any waiters */
1766 brcmf_sdio_dcmd_resp_wake(bus);
1769 /* Pad read to blocksize for efficiency */
1770 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1772 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1773 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1774 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1775 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1777 } else if (*rdlen % bus->head_align) {
1778 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1782 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1784 struct sk_buff *pkt; /* Packet for event or data frames */
1785 u16 pad; /* Number of pad bytes to read */
1786 uint rxleft = 0; /* Remaining number of frames allowed */
1787 int ret; /* Return code from calls */
1788 uint rxcount = 0; /* Total frames read */
1789 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1792 brcmf_dbg(TRACE, "Enter\n");
1794 /* Not finished unless we encounter no more frames indication */
1795 bus->rxpending = true;
1797 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1798 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1799 rd->seq_num++, rxleft--) {
1801 /* Handle glomming separately */
1802 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1804 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1805 bus->glomd, skb_peek(&bus->glom));
1806 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1807 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1808 rd->seq_num += cnt - 1;
1809 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1813 rd->len_left = rd->len;
1814 /* read header first for unknow frame length */
1815 sdio_claim_host(bus->sdiodev->func[1]);
1817 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1818 bus->rxhdr, BRCMF_FIRSTREAD);
1819 bus->sdcnt.f2rxhdrs++;
1821 brcmf_err("RXHEADER FAILED: %d\n",
1823 bus->sdcnt.rx_hdrfail++;
1824 brcmf_sdio_rxfail(bus, true, true);
1825 sdio_release_host(bus->sdiodev->func[1]);
1829 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1830 bus->rxhdr, SDPCM_HDRLEN,
1833 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1834 BRCMF_SDIO_FT_NORMAL)) {
1835 sdio_release_host(bus->sdiodev->func[1]);
1836 if (!bus->rxpending)
1842 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1843 brcmf_sdio_read_control(bus, bus->rxhdr,
1846 /* prepare the descriptor for the next read */
1847 rd->len = rd->len_nxtfrm << 4;
1849 /* treat all packet as event if we don't know */
1850 rd->channel = SDPCM_EVENT_CHANNEL;
1851 sdio_release_host(bus->sdiodev->func[1]);
1854 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1855 rd->len - BRCMF_FIRSTREAD : 0;
1856 head_read = BRCMF_FIRSTREAD;
1859 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1861 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1864 /* Give up on data, request rtx of events */
1865 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1866 brcmf_sdio_rxfail(bus, false,
1867 RETRYCHAN(rd->channel));
1868 sdio_release_host(bus->sdiodev->func[1]);
1871 skb_pull(pkt, head_read);
1872 pkt_align(pkt, rd->len_left, bus->head_align);
1874 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1875 bus->sdcnt.f2rxdata++;
1876 sdio_release_host(bus->sdiodev->func[1]);
1879 brcmf_err("read %d bytes from channel %d failed: %d\n",
1880 rd->len, rd->channel, ret);
1881 brcmu_pkt_buf_free_skb(pkt);
1882 sdio_claim_host(bus->sdiodev->func[1]);
1883 brcmf_sdio_rxfail(bus, true,
1884 RETRYCHAN(rd->channel));
1885 sdio_release_host(bus->sdiodev->func[1]);
1890 skb_push(pkt, head_read);
1891 memcpy(pkt->data, bus->rxhdr, head_read);
1894 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1895 rd_new.seq_num = rd->seq_num;
1896 sdio_claim_host(bus->sdiodev->func[1]);
1897 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1898 BRCMF_SDIO_FT_NORMAL)) {
1900 brcmu_pkt_buf_free_skb(pkt);
1902 bus->sdcnt.rx_readahead_cnt++;
1903 if (rd->len != roundup(rd_new.len, 16)) {
1904 brcmf_err("frame length mismatch:read %d, should be %d\n",
1906 roundup(rd_new.len, 16) >> 4);
1908 brcmf_sdio_rxfail(bus, true, true);
1909 sdio_release_host(bus->sdiodev->func[1]);
1910 brcmu_pkt_buf_free_skb(pkt);
1913 sdio_release_host(bus->sdiodev->func[1]);
1914 rd->len_nxtfrm = rd_new.len_nxtfrm;
1915 rd->channel = rd_new.channel;
1916 rd->dat_offset = rd_new.dat_offset;
1918 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1921 bus->rxhdr, SDPCM_HDRLEN,
1924 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1925 brcmf_err("readahead on control packet %d?\n",
1927 /* Force retry w/normal header read */
1929 sdio_claim_host(bus->sdiodev->func[1]);
1930 brcmf_sdio_rxfail(bus, false, true);
1931 sdio_release_host(bus->sdiodev->func[1]);
1932 brcmu_pkt_buf_free_skb(pkt);
1937 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1938 pkt->data, rd->len, "Rx Data:\n");
1940 /* Save superframe descriptor and allocate packet frame */
1941 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1942 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1943 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1945 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1948 __skb_trim(pkt, rd->len);
1949 skb_pull(pkt, SDPCM_HDRLEN);
1952 brcmf_err("%s: glom superframe w/o "
1953 "descriptor!\n", __func__);
1954 sdio_claim_host(bus->sdiodev->func[1]);
1955 brcmf_sdio_rxfail(bus, false, false);
1956 sdio_release_host(bus->sdiodev->func[1]);
1958 /* prepare the descriptor for the next read */
1959 rd->len = rd->len_nxtfrm << 4;
1961 /* treat all packet as event if we don't know */
1962 rd->channel = SDPCM_EVENT_CHANNEL;
1966 /* Fill in packet len and prio, deliver upward */
1967 __skb_trim(pkt, rd->len);
1968 skb_pull(pkt, rd->dat_offset);
1970 /* prepare the descriptor for the next read */
1971 rd->len = rd->len_nxtfrm << 4;
1973 /* treat all packet as event if we don't know */
1974 rd->channel = SDPCM_EVENT_CHANNEL;
1976 if (pkt->len == 0) {
1977 brcmu_pkt_buf_free_skb(pkt);
1981 brcmf_rx_frame(bus->sdiodev->dev, pkt);
1984 rxcount = maxframes - rxleft;
1985 /* Message if we hit the limit */
1987 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
1989 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
1990 /* Back off rxseq if awaiting rtx, update rx_seq */
1993 bus->rx_seq = rd->seq_num;
1999 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2001 wake_up_interruptible(&bus->ctrl_wait);
2005 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2010 dat_buf = (u8 *)(pkt->data);
2012 /* Check head padding */
2013 head_pad = ((unsigned long)dat_buf % bus->head_align);
2015 if (skb_headroom(pkt) < head_pad) {
2016 bus->sdiodev->bus_if->tx_realloc++;
2018 if (skb_cow(pkt, head_pad))
2021 skb_push(pkt, head_pad);
2022 dat_buf = (u8 *)(pkt->data);
2023 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2029 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2032 /* flag marking a dummy skb added for DMA alignment requirement */
2033 #define ALIGN_SKB_FLAG 0x8000
2034 /* bit mask of data length chopped from the previous packet */
2035 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2037 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2038 struct sk_buff_head *pktq,
2039 struct sk_buff *pkt, u16 total_len)
2041 struct brcmf_sdio_dev *sdiodev;
2042 struct sk_buff *pkt_pad;
2043 u16 tail_pad, tail_chop, chain_pad;
2044 unsigned int blksize;
2048 sdiodev = bus->sdiodev;
2049 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2050 /* sg entry alignment should be a divisor of block size */
2051 WARN_ON(blksize % bus->sgentry_align);
2053 /* Check tail padding */
2054 lastfrm = skb_queue_is_last(pktq, pkt);
2056 tail_chop = pkt->len % bus->sgentry_align;
2058 tail_pad = bus->sgentry_align - tail_chop;
2059 chain_pad = (total_len + tail_pad) % blksize;
2060 if (lastfrm && chain_pad)
2061 tail_pad += blksize - chain_pad;
2062 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2063 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2065 if (pkt_pad == NULL)
2067 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2068 if (unlikely(ret < 0)) {
2072 memcpy(pkt_pad->data,
2073 pkt->data + pkt->len - tail_chop,
2075 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2076 skb_trim(pkt, pkt->len - tail_chop);
2077 skb_trim(pkt_pad, tail_pad + tail_chop);
2078 __skb_queue_after(pktq, pkt, pkt_pad);
2080 ntail = pkt->data_len + tail_pad -
2081 (pkt->end - pkt->tail);
2082 if (skb_cloned(pkt) || ntail > 0)
2083 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2085 if (skb_linearize(pkt))
2087 __skb_put(pkt, tail_pad);
2094 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2095 * @bus: brcmf_sdio structure pointer
2096 * @pktq: packet list pointer
2097 * @chan: virtual channel to transmit the packet
2099 * Processes to be applied to the packet
2100 * - Align data buffer pointer
2101 * - Align data buffer length
2103 * Return: negative value if there is error
2106 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2109 u16 head_pad, total_len;
2110 struct sk_buff *pkt_next;
2113 struct brcmf_sdio_hdrinfo hd_info = {0};
2115 txseq = bus->tx_seq;
2117 skb_queue_walk(pktq, pkt_next) {
2118 /* alignment packet inserted in previous
2119 * loop cycle can be skipped as it is
2120 * already properly aligned and does not
2121 * need an sdpcm header.
2123 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2126 /* align packet data pointer */
2127 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2130 head_pad = (u16)ret;
2132 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2134 total_len += pkt_next->len;
2136 hd_info.len = pkt_next->len;
2137 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2138 if (bus->txglom && pktq->qlen > 1) {
2139 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2140 pkt_next, total_len);
2143 hd_info.tail_pad = (u16)ret;
2144 total_len += (u16)ret;
2147 hd_info.channel = chan;
2148 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2149 hd_info.seq_num = txseq++;
2151 /* Now fill the header */
2152 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2154 if (BRCMF_BYTES_ON() &&
2155 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2156 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2157 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2159 else if (BRCMF_HDRS_ON())
2160 brcmf_dbg_hex_dump(true, pkt_next->data,
2161 head_pad + bus->tx_hdrlen,
2164 /* Hardware length tag of the first packet should be total
2165 * length of the chain (including padding)
2168 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2173 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2174 * @bus: brcmf_sdio structure pointer
2175 * @pktq: packet list pointer
2177 * Processes to be applied to the packet
2178 * - Remove head padding
2179 * - Remove tail padding
2182 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2187 u16 dummy_flags, chop_len;
2188 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2190 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2191 dummy_flags = *(u16 *)(pkt_next->cb);
2192 if (dummy_flags & ALIGN_SKB_FLAG) {
2193 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2195 pkt_prev = pkt_next->prev;
2196 skb_put(pkt_prev, chop_len);
2198 __skb_unlink(pkt_next, pktq);
2199 brcmu_pkt_buf_free_skb(pkt_next);
2201 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2202 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2203 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2204 SDPCM_DOFFSET_SHIFT;
2205 skb_pull(pkt_next, dat_offset);
2207 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2208 skb_trim(pkt_next, pkt_next->len - tail_pad);
2214 /* Writes a HW/SW header into the packet and sends it. */
2215 /* Assumes: (a) header space already there, (b) caller holds lock */
2216 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2220 struct sk_buff *pkt_next, *tmp;
2222 brcmf_dbg(TRACE, "Enter\n");
2224 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2228 sdio_claim_host(bus->sdiodev->func[1]);
2229 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2230 bus->sdcnt.f2txdata++;
2233 brcmf_sdio_txfail(bus);
2235 sdio_release_host(bus->sdiodev->func[1]);
2238 brcmf_sdio_txpkt_postp(bus, pktq);
2240 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2241 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2242 __skb_unlink(pkt_next, pktq);
2243 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2248 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2250 struct sk_buff *pkt;
2251 struct sk_buff_head pktq;
2253 int ret = 0, prec_out, i;
2255 u8 tx_prec_map, pkt_num;
2257 brcmf_dbg(TRACE, "Enter\n");
2259 tx_prec_map = ~bus->flowcontrol;
2261 /* Send frames until the limit or some other event */
2262 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2265 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2266 bus->sdiodev->txglomsz);
2267 pkt_num = min_t(u32, pkt_num,
2268 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2269 __skb_queue_head_init(&pktq);
2270 spin_lock_bh(&bus->txq_lock);
2271 for (i = 0; i < pkt_num; i++) {
2272 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2276 __skb_queue_tail(&pktq, pkt);
2278 spin_unlock_bh(&bus->txq_lock);
2282 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2286 /* In poll mode, need to check for other events */
2288 /* Check device status, signal pending interrupt */
2289 sdio_claim_host(bus->sdiodev->func[1]);
2290 ret = r_sdreg32(bus, &intstatus,
2291 offsetof(struct sdpcmd_regs,
2293 sdio_release_host(bus->sdiodev->func[1]);
2294 bus->sdcnt.f2txdata++;
2297 if (intstatus & bus->hostintmask)
2298 atomic_set(&bus->ipend, 1);
2302 /* Deflow-control stack if needed */
2303 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2304 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2306 brcmf_txflowblock(bus->sdiodev->dev, false);
2312 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2317 struct brcmf_sdio_hdrinfo hd_info = {0};
2320 brcmf_dbg(TRACE, "Enter\n");
2322 /* Back the pointer to make room for bus header */
2323 frame -= bus->tx_hdrlen;
2324 len += bus->tx_hdrlen;
2326 /* Add alignment padding (optional for ctl frames) */
2327 doff = ((unsigned long)frame % bus->head_align);
2331 memset(frame + bus->tx_hdrlen, 0, doff);
2334 /* Round send length to next SDIO block */
2336 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2337 pad = bus->blocksize - (len % bus->blocksize);
2338 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2340 } else if (len % bus->head_align) {
2341 pad = bus->head_align - (len % bus->head_align);
2345 hd_info.len = len - pad;
2346 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2347 hd_info.dat_offset = doff + bus->tx_hdrlen;
2348 hd_info.seq_num = bus->tx_seq;
2349 hd_info.lastfrm = true;
2350 hd_info.tail_pad = pad;
2351 brcmf_sdio_hdpack(bus, frame, &hd_info);
2354 brcmf_sdio_update_hwhdr(frame, len);
2356 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2357 frame, len, "Tx Frame:\n");
2358 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2360 frame, min_t(u16, len, 16), "TxHdr:\n");
2363 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2366 brcmf_sdio_txfail(bus);
2368 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2369 } while (ret < 0 && retries++ < TXRETRIES);
2374 static void brcmf_sdio_bus_stop(struct device *dev)
2376 u32 local_hostintmask;
2379 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2380 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2381 struct brcmf_sdio *bus = sdiodev->bus;
2383 brcmf_dbg(TRACE, "Enter\n");
2385 if (bus->watchdog_tsk) {
2386 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2387 kthread_stop(bus->watchdog_tsk);
2388 bus->watchdog_tsk = NULL;
2391 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2392 sdio_claim_host(sdiodev->func[1]);
2394 /* Enable clock for device interrupts */
2395 brcmf_sdio_bus_sleep(bus, false, false);
2397 /* Disable and clear interrupts at the chip level also */
2398 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2399 local_hostintmask = bus->hostintmask;
2400 bus->hostintmask = 0;
2402 /* Force backplane clocks to assure F2 interrupt propagates */
2403 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2406 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2407 (saveclk | SBSDIO_FORCE_HT), &err);
2409 brcmf_err("Failed to force clock for F2: err %d\n",
2412 /* Turn off the bus (F2), free any pending packets */
2413 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2414 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2416 /* Clear any pending interrupts now that F2 is disabled */
2417 w_sdreg32(bus, local_hostintmask,
2418 offsetof(struct sdpcmd_regs, intstatus));
2420 sdio_release_host(sdiodev->func[1]);
2422 /* Clear the data packet queues */
2423 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2425 /* Clear any held glomming stuff */
2426 brcmu_pkt_buf_free_skb(bus->glomd);
2427 brcmf_sdio_free_glom(bus);
2429 /* Clear rx control and wake any waiters */
2430 spin_lock_bh(&bus->rxctl_lock);
2432 spin_unlock_bh(&bus->rxctl_lock);
2433 brcmf_sdio_dcmd_resp_wake(bus);
2435 /* Reset some F2 state stuff */
2436 bus->rxskip = false;
2437 bus->tx_seq = bus->rx_seq = 0;
2440 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2442 struct brcmf_sdio_dev *sdiodev;
2443 unsigned long flags;
2445 sdiodev = bus->sdiodev;
2446 if (sdiodev->oob_irq_requested) {
2447 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2448 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2449 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2450 sdiodev->irq_en = true;
2452 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2456 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2458 struct brcmf_core *buscore;
2463 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2464 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2466 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2467 bus->sdcnt.f1regdata++;
2471 val &= bus->hostintmask;
2472 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2474 /* Clear interrupts */
2476 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2477 bus->sdcnt.f1regdata++;
2478 atomic_or(val, &bus->intstatus);
2484 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2487 unsigned long intstatus;
2488 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2489 uint framecnt; /* Temporary counter of tx/rx frames */
2492 brcmf_dbg(TRACE, "Enter\n");
2494 sdio_claim_host(bus->sdiodev->func[1]);
2496 /* If waiting for HTAVAIL, check status */
2497 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2498 u8 clkctl, devctl = 0;
2501 /* Check for inconsistent device control */
2502 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2503 SBSDIO_DEVICE_CTL, &err);
2506 /* Read CSR, if clock on switch to AVAIL, else ignore */
2507 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2508 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2510 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2513 if (SBSDIO_HTAV(clkctl)) {
2514 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2515 SBSDIO_DEVICE_CTL, &err);
2516 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2517 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2519 bus->clkstate = CLK_AVAIL;
2523 /* Make sure backplane clock is on */
2524 brcmf_sdio_bus_sleep(bus, false, true);
2526 /* Pending interrupt indicates new device status */
2527 if (atomic_read(&bus->ipend) > 0) {
2528 atomic_set(&bus->ipend, 0);
2529 err = brcmf_sdio_intr_rstatus(bus);
2532 /* Start with leftover status bits */
2533 intstatus = atomic_xchg(&bus->intstatus, 0);
2535 /* Handle flow-control change: read new state in case our ack
2536 * crossed another change interrupt. If change still set, assume
2537 * FC ON for safety, let next loop through do the debounce.
2539 if (intstatus & I_HMB_FC_CHANGE) {
2540 intstatus &= ~I_HMB_FC_CHANGE;
2541 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2542 offsetof(struct sdpcmd_regs, intstatus));
2544 err = r_sdreg32(bus, &newstatus,
2545 offsetof(struct sdpcmd_regs, intstatus));
2546 bus->sdcnt.f1regdata += 2;
2547 atomic_set(&bus->fcstate,
2548 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2549 intstatus |= (newstatus & bus->hostintmask);
2552 /* Handle host mailbox indication */
2553 if (intstatus & I_HMB_HOST_INT) {
2554 intstatus &= ~I_HMB_HOST_INT;
2555 intstatus |= brcmf_sdio_hostmail(bus);
2558 sdio_release_host(bus->sdiodev->func[1]);
2560 /* Generally don't ask for these, can get CRC errors... */
2561 if (intstatus & I_WR_OOSYNC) {
2562 brcmf_err("Dongle reports WR_OOSYNC\n");
2563 intstatus &= ~I_WR_OOSYNC;
2566 if (intstatus & I_RD_OOSYNC) {
2567 brcmf_err("Dongle reports RD_OOSYNC\n");
2568 intstatus &= ~I_RD_OOSYNC;
2571 if (intstatus & I_SBINT) {
2572 brcmf_err("Dongle reports SBINT\n");
2573 intstatus &= ~I_SBINT;
2576 /* Would be active due to wake-wlan in gSPI */
2577 if (intstatus & I_CHIPACTIVE) {
2578 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2579 intstatus &= ~I_CHIPACTIVE;
2582 /* Ignore frame indications if rxskip is set */
2584 intstatus &= ~I_HMB_FRAME_IND;
2586 /* On frame indication, read available frames */
2587 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2588 brcmf_sdio_readframes(bus, bus->rxbound);
2589 if (!bus->rxpending)
2590 intstatus &= ~I_HMB_FRAME_IND;
2593 /* Keep still-pending events for next scheduling */
2595 atomic_or(intstatus, &bus->intstatus);
2597 brcmf_sdio_clrintr(bus);
2599 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2601 sdio_claim_host(bus->sdiodev->func[1]);
2602 if (bus->ctrl_frame_stat) {
2603 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2604 bus->ctrl_frame_len);
2605 bus->ctrl_frame_err = err;
2607 bus->ctrl_frame_stat = false;
2609 sdio_release_host(bus->sdiodev->func[1]);
2610 brcmf_sdio_wait_event_wakeup(bus);
2612 /* Send queued frames (limit 1 if rx may still be pending) */
2613 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2614 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2616 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2618 brcmf_sdio_sendfromq(bus, framecnt);
2621 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2622 brcmf_err("failed backplane access over SDIO, halting operation\n");
2623 atomic_set(&bus->intstatus, 0);
2624 if (bus->ctrl_frame_stat) {
2625 sdio_claim_host(bus->sdiodev->func[1]);
2626 if (bus->ctrl_frame_stat) {
2627 bus->ctrl_frame_err = -ENODEV;
2629 bus->ctrl_frame_stat = false;
2630 brcmf_sdio_wait_event_wakeup(bus);
2632 sdio_release_host(bus->sdiodev->func[1]);
2634 } else if (atomic_read(&bus->intstatus) ||
2635 atomic_read(&bus->ipend) > 0 ||
2636 (!atomic_read(&bus->fcstate) &&
2637 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2639 bus->dpc_triggered = true;
2643 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2645 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2646 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2647 struct brcmf_sdio *bus = sdiodev->bus;
2652 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2655 int eprec = -1; /* precedence to evict from */
2657 /* Fast case, precedence queue is not full and we are also not
2658 * exceeding total queue length
2660 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2661 brcmu_pktq_penq(q, prec, pkt);
2665 /* Determine precedence from which to evict packet, if any */
2666 if (pktq_pfull(q, prec)) {
2668 } else if (pktq_full(q)) {
2669 p = brcmu_pktq_peek_tail(q, &eprec);
2674 /* Evict if needed */
2676 /* Detect queueing to unconfigured precedence */
2678 return false; /* refuse newer (incoming) packet */
2679 /* Evict packet according to discard policy */
2680 p = brcmu_pktq_pdeq_tail(q, eprec);
2682 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2683 brcmu_pkt_buf_free_skb(p);
2687 p = brcmu_pktq_penq(q, prec, pkt);
2689 brcmf_err("brcmu_pktq_penq() failed\n");
2694 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2698 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2699 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2700 struct brcmf_sdio *bus = sdiodev->bus;
2702 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2703 if (sdiodev->state != BRCMF_SDIOD_DATA)
2706 /* Add space for the header */
2707 skb_push(pkt, bus->tx_hdrlen);
2708 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2710 prec = prio2prec((pkt->priority & PRIOMASK));
2712 /* Check for existing queue, current flow-control,
2713 pending event, or pending clock */
2714 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2715 bus->sdcnt.fcqueued++;
2717 /* Priority based enq */
2718 spin_lock_bh(&bus->txq_lock);
2719 /* reset bus_flags in packet cb */
2720 *(u16 *)(pkt->cb) = 0;
2721 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2722 skb_pull(pkt, bus->tx_hdrlen);
2723 brcmf_err("out of bus->txq !!!\n");
2729 if (pktq_len(&bus->txq) >= TXHI) {
2731 brcmf_txflowblock(dev, true);
2733 spin_unlock_bh(&bus->txq_lock);
2736 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2737 qcount[prec] = pktq_plen(&bus->txq, prec);
2740 brcmf_sdio_trigger_dpc(bus);
2745 #define CONSOLE_LINE_MAX 192
2747 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2749 struct brcmf_console *c = &bus->console;
2750 u8 line[CONSOLE_LINE_MAX], ch;
2754 /* Don't do anything until FWREADY updates console address */
2755 if (bus->console_addr == 0)
2758 /* Read console log struct */
2759 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2760 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2765 /* Allocate console buffer (one time only) */
2766 if (c->buf == NULL) {
2767 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2768 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2773 idx = le32_to_cpu(c->log_le.idx);
2775 /* Protect against corrupt value */
2776 if (idx > c->bufsize)
2779 /* Skip reading the console buffer if the index pointer
2784 /* Read the console buffer */
2785 addr = le32_to_cpu(c->log_le.buf);
2786 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2790 while (c->last != idx) {
2791 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2792 if (c->last == idx) {
2793 /* This would output a partial line.
2795 * the buffer pointer and output this
2796 * line next time around.
2801 c->last = c->bufsize - n;
2804 ch = c->buf[c->last];
2805 c->last = (c->last + 1) % c->bufsize;
2812 if (line[n - 1] == '\r')
2815 pr_debug("CONSOLE: %s\n", line);
2825 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2827 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2828 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2829 struct brcmf_sdio *bus = sdiodev->bus;
2832 brcmf_dbg(TRACE, "Enter\n");
2833 if (sdiodev->state != BRCMF_SDIOD_DATA)
2837 bus->ctrl_frame_buf = msg;
2838 bus->ctrl_frame_len = msglen;
2840 bus->ctrl_frame_stat = true;
2842 brcmf_sdio_trigger_dpc(bus);
2843 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2846 if (bus->ctrl_frame_stat) {
2847 sdio_claim_host(bus->sdiodev->func[1]);
2848 if (bus->ctrl_frame_stat) {
2849 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2850 bus->ctrl_frame_stat = false;
2853 sdio_release_host(bus->sdiodev->func[1]);
2856 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2857 bus->ctrl_frame_err);
2859 ret = bus->ctrl_frame_err;
2863 bus->sdcnt.tx_ctlerrs++;
2865 bus->sdcnt.tx_ctlpkts++;
2871 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2872 struct sdpcm_shared *sh)
2874 u32 addr, console_ptr, console_size, console_index;
2875 char *conbuf = NULL;
2879 /* obtain console information from device memory */
2880 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2881 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2882 (u8 *)&sh_val, sizeof(u32));
2885 console_ptr = le32_to_cpu(sh_val);
2887 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2888 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2889 (u8 *)&sh_val, sizeof(u32));
2892 console_size = le32_to_cpu(sh_val);
2894 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2895 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2896 (u8 *)&sh_val, sizeof(u32));
2899 console_index = le32_to_cpu(sh_val);
2901 /* allocate buffer for console data */
2902 if (console_size <= CONSOLE_BUFFER_MAX)
2903 conbuf = vzalloc(console_size+1);
2908 /* obtain the console data from device */
2909 conbuf[console_size] = '\0';
2910 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
2915 rv = seq_write(seq, conbuf + console_index,
2916 console_size - console_index);
2920 if (console_index > 0)
2921 rv = seq_write(seq, conbuf, console_index - 1);
2928 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
2929 struct sdpcm_shared *sh)
2932 struct brcmf_trap_info tr;
2934 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
2935 brcmf_dbg(INFO, "no trap in firmware\n");
2939 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
2940 sizeof(struct brcmf_trap_info));
2945 "dongle trap info: type 0x%x @ epc 0x%08x\n"
2946 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
2947 " lr 0x%08x pc 0x%08x offset 0x%x\n"
2948 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
2949 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
2950 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
2951 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
2952 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
2953 le32_to_cpu(tr.pc), sh->trap_addr,
2954 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
2955 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
2956 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
2957 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
2962 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
2963 struct sdpcm_shared *sh)
2966 char file[80] = "?";
2967 char expr[80] = "<???>";
2969 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2970 brcmf_dbg(INFO, "firmware not built with -assert\n");
2972 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
2973 brcmf_dbg(INFO, "no assert in dongle\n");
2977 sdio_claim_host(bus->sdiodev->func[1]);
2978 if (sh->assert_file_addr != 0) {
2979 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
2980 sh->assert_file_addr, (u8 *)file, 80);
2984 if (sh->assert_exp_addr != 0) {
2985 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
2986 sh->assert_exp_addr, (u8 *)expr, 80);
2990 sdio_release_host(bus->sdiodev->func[1]);
2992 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
2993 file, sh->assert_line, expr);
2997 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3000 struct sdpcm_shared sh;
3002 error = brcmf_sdio_readshared(bus, &sh);
3007 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3008 brcmf_dbg(INFO, "firmware not built with -assert\n");
3009 else if (sh.flags & SDPCM_SHARED_ASSERT)
3010 brcmf_err("assertion in dongle\n");
3012 if (sh.flags & SDPCM_SHARED_TRAP)
3013 brcmf_err("firmware trap in dongle\n");
3018 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3021 struct sdpcm_shared sh;
3023 error = brcmf_sdio_readshared(bus, &sh);
3027 error = brcmf_sdio_assert_info(seq, bus, &sh);
3031 error = brcmf_sdio_trap_info(seq, bus, &sh);
3035 error = brcmf_sdio_dump_console(seq, bus, &sh);
3041 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3043 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3044 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3046 return brcmf_sdio_died_dump(seq, bus);
3049 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3051 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3052 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3053 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3056 "intrcount: %u\nlastintrs: %u\n"
3057 "pollcnt: %u\nregfails: %u\n"
3058 "tx_sderrs: %u\nfcqueued: %u\n"
3059 "rxrtx: %u\nrx_toolong: %u\n"
3060 "rxc_errors: %u\nrx_hdrfail: %u\n"
3061 "rx_badhdr: %u\nrx_badseq: %u\n"
3062 "fc_rcvd: %u\nfc_xoff: %u\n"
3063 "fc_xon: %u\nrxglomfail: %u\n"
3064 "rxglomframes: %u\nrxglompkts: %u\n"
3065 "f2rxhdrs: %u\nf2rxdata: %u\n"
3066 "f2txdata: %u\nf1regdata: %u\n"
3067 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3068 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3069 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3070 sdcnt->intrcount, sdcnt->lastintrs,
3071 sdcnt->pollcnt, sdcnt->regfails,
3072 sdcnt->tx_sderrs, sdcnt->fcqueued,
3073 sdcnt->rxrtx, sdcnt->rx_toolong,
3074 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3075 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3076 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3077 sdcnt->fc_xon, sdcnt->rxglomfail,
3078 sdcnt->rxglomframes, sdcnt->rxglompkts,
3079 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3080 sdcnt->f2txdata, sdcnt->f1regdata,
3081 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3082 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3083 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3088 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3090 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3091 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3093 if (IS_ERR_OR_NULL(dentry))
3096 bus->console_interval = BRCMF_CONSOLE;
3098 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3099 brcmf_debugfs_add_entry(drvr, "counters",
3100 brcmf_debugfs_sdio_count_read);
3101 debugfs_create_u32("console_interval", 0644, dentry,
3102 &bus->console_interval);
3105 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3110 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3116 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3122 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3123 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3124 struct brcmf_sdio *bus = sdiodev->bus;
3126 brcmf_dbg(TRACE, "Enter\n");
3127 if (sdiodev->state != BRCMF_SDIOD_DATA)
3130 /* Wait until control frame is available */
3131 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3133 spin_lock_bh(&bus->rxctl_lock);
3135 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3137 buf = bus->rxctl_orig;
3138 bus->rxctl_orig = NULL;
3140 spin_unlock_bh(&bus->rxctl_lock);
3144 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3146 } else if (timeleft == 0) {
3147 brcmf_err("resumed on timeout\n");
3148 brcmf_sdio_checkdied(bus);
3149 } else if (pending) {
3150 brcmf_dbg(CTL, "cancelled\n");
3151 return -ERESTARTSYS;
3153 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3154 brcmf_sdio_checkdied(bus);
3158 bus->sdcnt.rx_ctlpkts++;
3160 bus->sdcnt.rx_ctlerrs++;
3162 return rxlen ? (int)rxlen : -ETIMEDOUT;
3167 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3168 u8 *ram_data, uint ram_sz)
3177 /* read back and verify */
3178 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3180 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3181 /* do not proceed while no memory but */
3187 while (offset < ram_sz) {
3188 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3190 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3192 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3196 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3197 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3212 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3213 u8 *ram_data, uint ram_sz)
3219 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3220 const struct firmware *fw)
3224 brcmf_dbg(TRACE, "Enter\n");
3226 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3227 (u8 *)fw->data, fw->size);
3229 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3230 err, (int)fw->size, bus->ci->rambase);
3231 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3232 (u8 *)fw->data, fw->size))
3238 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3239 void *vars, u32 varsz)
3244 brcmf_dbg(TRACE, "Enter\n");
3246 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3247 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3249 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3250 err, varsz, address);
3251 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3257 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3258 const struct firmware *fw,
3259 void *nvram, u32 nvlen)
3264 sdio_claim_host(bus->sdiodev->func[1]);
3265 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3267 rstvec = get_unaligned_le32(fw->data);
3268 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3270 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3271 release_firmware(fw);
3273 brcmf_err("dongle image file download failed\n");
3274 brcmf_fw_nvram_free(nvram);
3278 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3279 brcmf_fw_nvram_free(nvram);
3281 brcmf_err("dongle nvram file download failed\n");
3285 /* Take arm out of reset */
3286 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3287 brcmf_err("error getting out of ARM core reset\n");
3291 /* Allow full data communication using DPC from now on. */
3292 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3296 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3297 sdio_release_host(bus->sdiodev->func[1]);
3301 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3306 brcmf_dbg(TRACE, "Enter\n");
3308 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3310 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3314 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3315 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3317 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3321 /* Add CMD14 Support */
3322 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3323 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3324 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3327 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3331 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3332 SBSDIO_FORCE_HT, &err);
3334 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3339 bus->sr_enabled = true;
3340 brcmf_dbg(INFO, "SR enabled\n");
3343 /* enable KSO bit */
3344 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3349 brcmf_dbg(TRACE, "Enter\n");
3351 /* KSO bit added in SDIO core rev 12 */
3352 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3355 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3357 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3361 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3362 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3363 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3364 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3367 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3376 static int brcmf_sdio_bus_preinit(struct device *dev)
3378 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3379 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3380 struct brcmf_sdio *bus = sdiodev->bus;
3385 /* the commands below use the terms tx and rx from
3386 * a device perspective, ie. bus:txglom affects the
3387 * bus transfers from device to host.
3389 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3390 /* for sdio core rev < 12, disable txgloming */
3392 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3395 /* otherwise, set txglomalign */
3396 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3397 /* SDIO ADMA requires at least 32 bit alignment */
3398 value = max_t(u32, value, 4);
3399 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3406 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3407 if (sdiodev->sg_support) {
3408 bus->txglom = false;
3410 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3411 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3412 &value, sizeof(u32));
3414 /* bus:rxglom is allowed to fail */
3418 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3421 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3427 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3429 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3430 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3431 struct brcmf_sdio *bus = sdiodev->bus;
3433 return bus->ci->ramsize - bus->ci->srsize;
3436 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3439 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3440 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3441 struct brcmf_sdio *bus = sdiodev->bus;
3447 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3450 address = bus->ci->rambase;
3452 sdio_claim_host(sdiodev->func[1]);
3453 while (offset < mem_size) {
3454 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3456 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3458 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3468 sdio_release_host(sdiodev->func[1]);
3472 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3474 if (!bus->dpc_triggered) {
3475 bus->dpc_triggered = true;
3476 queue_work(bus->brcmf_wq, &bus->datawork);
3480 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3482 brcmf_dbg(TRACE, "Enter\n");
3485 brcmf_err("bus is null pointer, exiting\n");
3489 /* Count the interrupt call */
3490 bus->sdcnt.intrcount++;
3492 atomic_set(&bus->ipend, 1);
3494 if (brcmf_sdio_intr_rstatus(bus)) {
3495 brcmf_err("failed backplane access\n");
3498 /* Disable additional interrupts (is this needed now)? */
3500 brcmf_err("isr w/o interrupt configured!\n");
3502 bus->dpc_triggered = true;
3503 queue_work(bus->brcmf_wq, &bus->datawork);
3506 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3508 brcmf_dbg(TIMER, "Enter\n");
3510 /* Poll period: check device if appropriate. */
3511 if (!bus->sr_enabled &&
3512 bus->poll && (++bus->polltick >= bus->pollrate)) {
3515 /* Reset poll tick */
3518 /* Check device if no interrupts */
3520 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3522 if (!bus->dpc_triggered) {
3525 sdio_claim_host(bus->sdiodev->func[1]);
3526 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3529 sdio_release_host(bus->sdiodev->func[1]);
3530 intstatus = devpend & (INTR_STATUS_FUNC1 |
3534 /* If there is something, make like the ISR and
3537 bus->sdcnt.pollcnt++;
3538 atomic_set(&bus->ipend, 1);
3540 bus->dpc_triggered = true;
3541 queue_work(bus->brcmf_wq, &bus->datawork);
3545 /* Update interrupt tracking */
3546 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3549 /* Poll for console output periodically */
3550 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3551 bus->console_interval != 0) {
3552 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3553 if (bus->console.count >= bus->console_interval) {
3554 bus->console.count -= bus->console_interval;
3555 sdio_claim_host(bus->sdiodev->func[1]);
3556 /* Make sure backplane clock is on */
3557 brcmf_sdio_bus_sleep(bus, false, false);
3558 if (brcmf_sdio_readconsole(bus) < 0)
3560 bus->console_interval = 0;
3561 sdio_release_host(bus->sdiodev->func[1]);
3566 /* On idle timeout clear activity flag and/or turn off clock */
3567 if (!bus->dpc_triggered) {
3569 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3570 (bus->clkstate == CLK_AVAIL)) {
3572 if (bus->idlecount > bus->idletime) {
3573 brcmf_dbg(SDIO, "idle\n");
3574 sdio_claim_host(bus->sdiodev->func[1]);
3575 brcmf_sdio_wd_timer(bus, false);
3577 brcmf_sdio_bus_sleep(bus, true, false);
3578 sdio_release_host(bus->sdiodev->func[1]);
3588 static void brcmf_sdio_dataworker(struct work_struct *work)
3590 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3593 bus->dpc_running = true;
3595 while (ACCESS_ONCE(bus->dpc_triggered)) {
3596 bus->dpc_triggered = false;
3597 brcmf_sdio_dpc(bus);
3600 bus->dpc_running = false;
3601 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3602 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3603 brcmf_sdiod_try_freeze(bus->sdiodev);
3604 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3609 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3610 struct brcmf_chip *ci, u32 drivestrength)
3612 const struct sdiod_drive_str *str_tab = NULL;
3616 u32 drivestrength_sel = 0;
3620 if (!(ci->cc_caps & CC_CAP_PMU))
3623 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3624 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3625 str_tab = sdiod_drvstr_tab1_1v8;
3626 str_mask = 0x00003800;
3629 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3630 str_tab = sdiod_drvstr_tab6_1v8;
3631 str_mask = 0x00001800;
3634 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3635 /* note: 43143 does not support tristate */
3636 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3637 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3638 str_tab = sdiod_drvstr_tab2_3v3;
3639 str_mask = 0x00000007;
3642 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3643 ci->name, drivestrength);
3645 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3646 str_tab = sdiod_drive_strength_tab5_1v8;
3647 str_mask = 0x00003800;
3651 brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
3652 ci->name, ci->chiprev, ci->pmurev);
3656 if (str_tab != NULL) {
3657 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3659 for (i = 0; str_tab[i].strength != 0; i++) {
3660 if (drivestrength >= str_tab[i].strength) {
3661 drivestrength_sel = str_tab[i].sel;
3665 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3666 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3667 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3668 cc_data_temp &= ~str_mask;
3669 drivestrength_sel <<= str_shift;
3670 cc_data_temp |= drivestrength_sel;
3671 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3673 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3674 str_tab[i].strength, drivestrength, cc_data_temp);
3678 static int brcmf_sdio_buscoreprep(void *ctx)
3680 struct brcmf_sdio_dev *sdiodev = ctx;
3684 /* Try forcing SDIO core to do ALPAvail request only */
3685 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3686 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3688 brcmf_err("error writing for HT off\n");
3692 /* If register supported, wait for ALPAvail and then force ALP */
3693 /* This may take up to 15 milliseconds */
3694 clkval = brcmf_sdiod_regrb(sdiodev,
3695 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3697 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3698 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3703 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3704 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3705 !SBSDIO_ALPAV(clkval)),
3706 PMU_MAX_TRANSITION_DLY);
3707 if (!SBSDIO_ALPAV(clkval)) {
3708 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3713 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3714 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3717 /* Also, disable the extra SDIO pull-ups */
3718 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3723 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3726 struct brcmf_sdio_dev *sdiodev = ctx;
3727 struct brcmf_core *core;
3730 /* clear all interrupts */
3731 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3732 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3733 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3736 /* Write reset vector to address 0 */
3737 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3741 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3743 struct brcmf_sdio_dev *sdiodev = ctx;
3746 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3747 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
3748 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3749 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3751 val &= ~CID_ID_MASK;
3752 val |= BRCM_CC_4339_CHIP_ID;
3758 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3760 struct brcmf_sdio_dev *sdiodev = ctx;
3762 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3765 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3766 .prepare = brcmf_sdio_buscoreprep,
3767 .activate = brcmf_sdio_buscore_activate,
3768 .read32 = brcmf_sdio_buscore_read32,
3769 .write32 = brcmf_sdio_buscore_write32,
3773 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3775 struct brcmf_sdio_dev *sdiodev;
3782 sdiodev = bus->sdiodev;
3783 sdio_claim_host(sdiodev->func[1]);
3785 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3786 brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL));
3789 * Force PLL off until brcmf_chip_attach()
3790 * programs PLL control regs
3793 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3794 BRCMF_INIT_CLKCTL1, &err);
3796 clkctl = brcmf_sdiod_regrb(sdiodev,
3797 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3799 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3800 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3801 err, BRCMF_INIT_CLKCTL1, clkctl);
3805 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
3806 if (IS_ERR(bus->ci)) {
3807 brcmf_err("brcmf_chip_attach failed!\n");
3811 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
3815 if (!sdiodev->settings) {
3816 brcmf_err("Failed to get device parameters\n");
3819 /* platform specific configuration:
3820 * alignments must be at least 4 bytes for ADMA
3822 bus->head_align = ALIGNMENT;
3823 bus->sgentry_align = ALIGNMENT;
3824 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
3825 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
3826 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
3827 bus->sgentry_align =
3828 sdiodev->settings->bus.sdio.sd_sgentry_align;
3830 /* allocate scatter-gather table. sg support
3831 * will be disabled upon allocation failure.
3833 brcmf_sdiod_sgtable_alloc(sdiodev);
3835 #ifdef CONFIG_PM_SLEEP
3836 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
3837 * is true or when platform data OOB irq is true).
3839 if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) &&
3840 ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) ||
3841 (sdiodev->settings->bus.sdio.oob_irq_supported)))
3842 sdiodev->bus_if->wowl_supported = true;
3845 if (brcmf_sdio_kso_init(bus)) {
3846 brcmf_err("error enabling KSO\n");
3850 if (sdiodev->settings->bus.sdio.drive_strength)
3851 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
3853 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3854 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
3856 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3857 reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
3861 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3863 brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3867 /* set PMUControl so a backplane reset does PMU state reload */
3868 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
3869 reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err);
3873 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3875 brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err);
3879 sdio_release_host(sdiodev->func[1]);
3881 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3883 /* allocate header buffer */
3884 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3887 /* Locate an appropriately-aligned portion of hdrbuf */
3888 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3891 /* Set the poll and/or interrupt flags */
3900 sdio_release_host(sdiodev->func[1]);
3905 brcmf_sdio_watchdog_thread(void *data)
3907 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3910 allow_signal(SIGTERM);
3911 /* Run until signal received */
3912 brcmf_sdiod_freezer_count(bus->sdiodev);
3914 if (kthread_should_stop())
3916 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3917 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3918 brcmf_sdiod_freezer_count(bus->sdiodev);
3919 brcmf_sdiod_try_freeze(bus->sdiodev);
3921 brcmf_sdio_bus_watchdog(bus);
3922 /* Count the tick for reference */
3923 bus->sdcnt.tickcnt++;
3924 reinit_completion(&bus->watchdog_wait);
3932 brcmf_sdio_watchdog(unsigned long data)
3934 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3936 if (bus->watchdog_tsk) {
3937 complete(&bus->watchdog_wait);
3938 /* Reschedule the watchdog */
3940 mod_timer(&bus->timer,
3941 jiffies + BRCMF_WD_POLL);
3945 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3946 .stop = brcmf_sdio_bus_stop,
3947 .preinit = brcmf_sdio_bus_preinit,
3948 .txdata = brcmf_sdio_bus_txdata,
3949 .txctl = brcmf_sdio_bus_txctl,
3950 .rxctl = brcmf_sdio_bus_rxctl,
3951 .gettxq = brcmf_sdio_bus_gettxq,
3952 .wowl_config = brcmf_sdio_wowl_config,
3953 .get_ramsize = brcmf_sdio_bus_get_ramsize,
3954 .get_memdump = brcmf_sdio_bus_get_memdump,
3957 static void brcmf_sdio_firmware_callback(struct device *dev,
3958 const struct firmware *code,
3959 void *nvram, u32 nvram_len)
3961 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3962 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3963 struct brcmf_sdio *bus = sdiodev->bus;
3967 brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
3972 /* try to download image and nvram to the dongle */
3973 bus->alp_only = true;
3974 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
3977 bus->alp_only = false;
3979 /* Start the watchdog timer */
3980 bus->sdcnt.tickcnt = 0;
3981 brcmf_sdio_wd_timer(bus, true);
3983 sdio_claim_host(sdiodev->func[1]);
3985 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3986 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3987 if (bus->clkstate != CLK_AVAIL)
3990 /* Force clocks on backplane to be sure F2 interrupt propagates */
3991 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
3993 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3994 (saveclk | SBSDIO_FORCE_HT), &err);
3997 brcmf_err("Failed to force clock for F2: err %d\n", err);
4001 /* Enable function 2 (frame transfers) */
4002 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4003 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4004 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4007 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4009 /* If F2 successfully enabled, set core and enable interrupts */
4011 /* Set up the interrupt mask and enable interrupts */
4012 bus->hostintmask = HOSTINTMASK;
4013 w_sdreg32(bus, bus->hostintmask,
4014 offsetof(struct sdpcmd_regs, hostintmask));
4016 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4018 /* Disable F2 again */
4019 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4023 if (brcmf_chip_sr_capable(bus->ci)) {
4024 brcmf_sdio_sr_init(bus);
4026 /* Restore previous clock setting */
4027 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4032 err = brcmf_sdiod_intr_register(sdiodev);
4034 brcmf_err("intr register failed:%d\n", err);
4037 /* If we didn't come up, turn off backplane clock */
4039 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4041 sdio_release_host(sdiodev->func[1]);
4043 err = brcmf_bus_start(dev);
4045 brcmf_err("dongle is not responding\n");
4051 sdio_release_host(sdiodev->func[1]);
4053 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4054 device_release_driver(dev);
4057 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4060 struct brcmf_sdio *bus;
4061 struct workqueue_struct *wq;
4063 brcmf_dbg(TRACE, "Enter\n");
4065 /* Allocate private bus interface state */
4066 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4070 bus->sdiodev = sdiodev;
4072 skb_queue_head_init(&bus->glom);
4073 bus->txbound = BRCMF_TXBOUND;
4074 bus->rxbound = BRCMF_RXBOUND;
4075 bus->txminmax = BRCMF_TXMINMAX;
4076 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4078 /* single-threaded workqueue */
4079 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4080 dev_name(&sdiodev->func[1]->dev));
4082 brcmf_err("insufficient memory to create txworkqueue\n");
4085 brcmf_sdiod_freezer_count(sdiodev);
4086 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4089 /* attempt to attach to the dongle */
4090 if (!(brcmf_sdio_probe_attach(bus))) {
4091 brcmf_err("brcmf_sdio_probe_attach failed\n");
4095 spin_lock_init(&bus->rxctl_lock);
4096 spin_lock_init(&bus->txq_lock);
4097 init_waitqueue_head(&bus->ctrl_wait);
4098 init_waitqueue_head(&bus->dcmd_resp_wait);
4100 /* Set up the watchdog timer */
4101 init_timer(&bus->timer);
4102 bus->timer.data = (unsigned long)bus;
4103 bus->timer.function = brcmf_sdio_watchdog;
4105 /* Initialize watchdog thread */
4106 init_completion(&bus->watchdog_wait);
4107 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4108 bus, "brcmf_wdog/%s",
4109 dev_name(&sdiodev->func[1]->dev));
4110 if (IS_ERR(bus->watchdog_tsk)) {
4111 pr_warn("brcmf_watchdog thread failed to start\n");
4112 bus->watchdog_tsk = NULL;
4114 /* Initialize DPC thread */
4115 bus->dpc_triggered = false;
4116 bus->dpc_running = false;
4118 /* Assign bus interface call back */
4119 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4120 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4121 bus->sdiodev->bus_if->chip = bus->ci->chip;
4122 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4124 /* default sdio bus header length for tx packet */
4125 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4127 /* Attach to the common layer, reserve hdr space */
4128 ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings);
4130 brcmf_err("brcmf_attach failed\n");
4134 /* allocate scatter-gather table. sg support
4135 * will be disabled upon allocation failure.
4137 brcmf_sdiod_sgtable_alloc(bus->sdiodev);
4139 /* Query the F2 block size, set roundup accordingly */
4140 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4141 bus->roundup = min(max_roundup, bus->blocksize);
4143 /* Allocate buffers */
4144 if (bus->sdiodev->bus_if->maxctl) {
4145 bus->sdiodev->bus_if->maxctl += bus->roundup;
4147 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4148 ALIGNMENT) + bus->head_align;
4149 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4150 if (!(bus->rxbuf)) {
4151 brcmf_err("rxbuf allocation failed\n");
4156 sdio_claim_host(bus->sdiodev->func[1]);
4158 /* Disable F2 to clear any intermediate frame state on the dongle */
4159 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4161 bus->rxflow = false;
4163 /* Done with backplane-dependent accesses, can drop clock... */
4164 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4166 sdio_release_host(bus->sdiodev->func[1]);
4168 /* ...and initialize clock/power states */
4169 bus->clkstate = CLK_SDONLY;
4170 bus->idletime = BRCMF_IDLE_INTERVAL;
4171 bus->idleclock = BRCMF_IDLE_ACTIVE;
4174 bus->sr_enabled = false;
4176 brcmf_sdio_debugfs_create(bus);
4177 brcmf_dbg(INFO, "completed!!\n");
4179 ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev,
4181 ARRAY_SIZE(brcmf_sdio_fwnames),
4182 sdiodev->fw_name, sdiodev->nvram_name);
4186 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4187 sdiodev->fw_name, sdiodev->nvram_name,
4188 brcmf_sdio_firmware_callback);
4190 brcmf_err("async firmware request failed: %d\n", ret);
4197 brcmf_sdio_remove(bus);
4201 /* Detach and free everything */
4202 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4204 brcmf_dbg(TRACE, "Enter\n");
4207 /* De-register interrupt handler */
4208 brcmf_sdiod_intr_unregister(bus->sdiodev);
4210 brcmf_detach(bus->sdiodev->dev);
4212 cancel_work_sync(&bus->datawork);
4214 destroy_workqueue(bus->brcmf_wq);
4217 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4218 sdio_claim_host(bus->sdiodev->func[1]);
4219 brcmf_sdio_wd_timer(bus, false);
4220 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4221 /* Leave the device in state where it is
4222 * 'passive'. This is done by resetting all
4226 brcmf_chip_set_passive(bus->ci);
4227 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4228 sdio_release_host(bus->sdiodev->func[1]);
4230 brcmf_chip_detach(bus->ci);
4232 if (bus->sdiodev->settings)
4233 brcmf_release_module_param(bus->sdiodev->settings);
4240 brcmf_dbg(TRACE, "Disconnected\n");
4243 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4245 /* Totally stop the timer */
4246 if (!active && bus->wd_active) {
4247 del_timer_sync(&bus->timer);
4248 bus->wd_active = false;
4252 /* don't start the wd until fw is loaded */
4253 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4257 if (!bus->wd_active) {
4258 /* Create timer again when watchdog period is
4259 dynamically changed or in the first instance
4261 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4262 add_timer(&bus->timer);
4263 bus->wd_active = true;
4265 /* Re arm the timer, at last watchdog period */
4266 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4271 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4275 sdio_claim_host(bus->sdiodev->func[1]);
4276 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4277 sdio_release_host(bus->sdiodev->func[1]);
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