1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
48 #include <net/mac80211.h>
50 #include <asm/div64.h>
52 #define DRV_NAME "iwlagn"
54 #include "iwl-eeprom.h"
58 #include "iwl-helpers.h"
60 #include "iwl-agn-calib.h"
62 #include "iwl-agn-led.h"
65 /******************************************************************************
69 ******************************************************************************/
72 * module name, copyright, version, etc.
74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
76 #ifdef CONFIG_IWLWIFI_DEBUG
82 #define DRV_VERSION IWLWIFI_VERSION VD
85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
86 MODULE_VERSION(DRV_VERSION);
87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
88 MODULE_LICENSE("GPL");
89 MODULE_ALIAS("iwl4965");
91 static int iwlagn_ant_coupling;
92 static bool iwlagn_bt_ch_announce = 1;
94 void iwl_update_chain_flags(struct iwl_priv *priv)
96 struct iwl_rxon_context *ctx;
98 if (priv->cfg->ops->hcmd->set_rxon_chain) {
99 for_each_context(priv, ctx) {
100 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
101 if (ctx->active.rx_chain != ctx->staging.rx_chain)
102 iwlcore_commit_rxon(priv, ctx);
107 static void iwl_clear_free_frames(struct iwl_priv *priv)
109 struct list_head *element;
111 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
114 while (!list_empty(&priv->free_frames)) {
115 element = priv->free_frames.next;
117 kfree(list_entry(element, struct iwl_frame, list));
118 priv->frames_count--;
121 if (priv->frames_count) {
122 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
124 priv->frames_count = 0;
128 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
130 struct iwl_frame *frame;
131 struct list_head *element;
132 if (list_empty(&priv->free_frames)) {
133 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
135 IWL_ERR(priv, "Could not allocate frame!\n");
139 priv->frames_count++;
143 element = priv->free_frames.next;
145 return list_entry(element, struct iwl_frame, list);
148 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
150 memset(frame, 0, sizeof(*frame));
151 list_add(&frame->list, &priv->free_frames);
154 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
155 struct ieee80211_hdr *hdr,
158 lockdep_assert_held(&priv->mutex);
160 if (!priv->beacon_skb)
163 if (priv->beacon_skb->len > left)
166 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
168 return priv->beacon_skb->len;
171 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
172 static void iwl_set_beacon_tim(struct iwl_priv *priv,
173 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
174 u8 *beacon, u32 frame_size)
177 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
180 * The index is relative to frame start but we start looking at the
181 * variable-length part of the beacon.
183 tim_idx = mgmt->u.beacon.variable - beacon;
185 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
186 while ((tim_idx < (frame_size - 2)) &&
187 (beacon[tim_idx] != WLAN_EID_TIM))
188 tim_idx += beacon[tim_idx+1] + 2;
190 /* If TIM field was found, set variables */
191 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
192 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
193 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
195 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
198 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
199 struct iwl_frame *frame)
201 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
206 * We have to set up the TX command, the TX Beacon command, and the
210 lockdep_assert_held(&priv->mutex);
212 if (!priv->beacon_ctx) {
213 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
217 /* Initialize memory */
218 tx_beacon_cmd = &frame->u.beacon;
219 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
221 /* Set up TX beacon contents */
222 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
223 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
224 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
229 /* Set up TX command fields */
230 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
231 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
232 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
233 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
234 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
236 /* Set up TX beacon command fields */
237 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
240 /* Set up packet rate and flags */
241 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
242 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
243 priv->hw_params.valid_tx_ant);
244 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
245 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
246 rate_flags |= RATE_MCS_CCK_MSK;
247 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
250 return sizeof(*tx_beacon_cmd) + frame_size;
253 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
255 struct iwl_frame *frame;
256 unsigned int frame_size;
259 frame = iwl_get_free_frame(priv);
261 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
266 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
268 IWL_ERR(priv, "Error configuring the beacon command\n");
269 iwl_free_frame(priv, frame);
273 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
276 iwl_free_frame(priv, frame);
281 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
283 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
285 dma_addr_t addr = get_unaligned_le32(&tb->lo);
286 if (sizeof(dma_addr_t) > sizeof(u32))
288 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
293 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
295 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
297 return le16_to_cpu(tb->hi_n_len) >> 4;
300 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
301 dma_addr_t addr, u16 len)
303 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
304 u16 hi_n_len = len << 4;
306 put_unaligned_le32(addr, &tb->lo);
307 if (sizeof(dma_addr_t) > sizeof(u32))
308 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
310 tb->hi_n_len = cpu_to_le16(hi_n_len);
312 tfd->num_tbs = idx + 1;
315 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
317 return tfd->num_tbs & 0x1f;
321 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
322 * @priv - driver private data
325 * Does NOT advance any TFD circular buffer read/write indexes
326 * Does NOT free the TFD itself (which is within circular buffer)
328 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
330 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
332 struct pci_dev *dev = priv->pci_dev;
333 int index = txq->q.read_ptr;
337 tfd = &tfd_tmp[index];
339 /* Sanity check on number of chunks */
340 num_tbs = iwl_tfd_get_num_tbs(tfd);
342 if (num_tbs >= IWL_NUM_OF_TBS) {
343 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
344 /* @todo issue fatal error, it is quite serious situation */
350 pci_unmap_single(dev,
351 dma_unmap_addr(&txq->meta[index], mapping),
352 dma_unmap_len(&txq->meta[index], len),
353 PCI_DMA_BIDIRECTIONAL);
355 /* Unmap chunks, if any. */
356 for (i = 1; i < num_tbs; i++)
357 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
358 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
364 skb = txq->txb[txq->q.read_ptr].skb;
366 /* can be called from irqs-disabled context */
368 dev_kfree_skb_any(skb);
369 txq->txb[txq->q.read_ptr].skb = NULL;
374 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
375 struct iwl_tx_queue *txq,
376 dma_addr_t addr, u16 len,
380 struct iwl_tfd *tfd, *tfd_tmp;
384 tfd_tmp = (struct iwl_tfd *)txq->tfds;
385 tfd = &tfd_tmp[q->write_ptr];
388 memset(tfd, 0, sizeof(*tfd));
390 num_tbs = iwl_tfd_get_num_tbs(tfd);
392 /* Each TFD can point to a maximum 20 Tx buffers */
393 if (num_tbs >= IWL_NUM_OF_TBS) {
394 IWL_ERR(priv, "Error can not send more than %d chunks\n",
399 BUG_ON(addr & ~DMA_BIT_MASK(36));
400 if (unlikely(addr & ~IWL_TX_DMA_MASK))
401 IWL_ERR(priv, "Unaligned address = %llx\n",
402 (unsigned long long)addr);
404 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
410 * Tell nic where to find circular buffer of Tx Frame Descriptors for
411 * given Tx queue, and enable the DMA channel used for that queue.
413 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
414 * channels supported in hardware.
416 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
417 struct iwl_tx_queue *txq)
419 int txq_id = txq->q.id;
421 /* Circular buffer (TFD queue in DRAM) physical base address */
422 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
423 txq->q.dma_addr >> 8);
428 /******************************************************************************
430 * Generic RX handler implementations
432 ******************************************************************************/
433 static void iwl_rx_reply_alive(struct iwl_priv *priv,
434 struct iwl_rx_mem_buffer *rxb)
436 struct iwl_rx_packet *pkt = rxb_addr(rxb);
437 struct iwl_alive_resp *palive;
438 struct delayed_work *pwork;
440 palive = &pkt->u.alive_frame;
442 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
444 palive->is_valid, palive->ver_type,
445 palive->ver_subtype);
447 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
448 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
449 memcpy(&priv->card_alive_init,
451 sizeof(struct iwl_init_alive_resp));
452 pwork = &priv->init_alive_start;
454 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
455 memcpy(&priv->card_alive, &pkt->u.alive_frame,
456 sizeof(struct iwl_alive_resp));
457 pwork = &priv->alive_start;
460 /* We delay the ALIVE response by 5ms to
461 * give the HW RF Kill time to activate... */
462 if (palive->is_valid == UCODE_VALID_OK)
463 queue_delayed_work(priv->workqueue, pwork,
464 msecs_to_jiffies(5));
466 IWL_WARN(priv, "%s uCode did not respond OK.\n",
467 (palive->ver_subtype == INITIALIZE_SUBTYPE) ?
469 queue_work(priv->workqueue, &priv->restart);
473 static void iwl_bg_beacon_update(struct work_struct *work)
475 struct iwl_priv *priv =
476 container_of(work, struct iwl_priv, beacon_update);
477 struct sk_buff *beacon;
479 mutex_lock(&priv->mutex);
480 if (!priv->beacon_ctx) {
481 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
485 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
487 * The ucode will send beacon notifications even in
488 * IBSS mode, but we don't want to process them. But
489 * we need to defer the type check to here due to
490 * requiring locking around the beacon_ctx access.
495 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
496 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
498 IWL_ERR(priv, "update beacon failed -- keeping old\n");
502 /* new beacon skb is allocated every time; dispose previous.*/
503 dev_kfree_skb(priv->beacon_skb);
505 priv->beacon_skb = beacon;
507 iwlagn_send_beacon_cmd(priv);
509 mutex_unlock(&priv->mutex);
512 static void iwl_bg_bt_runtime_config(struct work_struct *work)
514 struct iwl_priv *priv =
515 container_of(work, struct iwl_priv, bt_runtime_config);
517 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
520 /* dont send host command if rf-kill is on */
521 if (!iwl_is_ready_rf(priv))
523 priv->cfg->ops->hcmd->send_bt_config(priv);
526 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
528 struct iwl_priv *priv =
529 container_of(work, struct iwl_priv, bt_full_concurrency);
530 struct iwl_rxon_context *ctx;
532 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
535 /* dont send host command if rf-kill is on */
536 if (!iwl_is_ready_rf(priv))
539 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
540 priv->bt_full_concurrent ?
541 "full concurrency" : "3-wire");
544 * LQ & RXON updated cmds must be sent before BT Config cmd
545 * to avoid 3-wire collisions
547 mutex_lock(&priv->mutex);
548 for_each_context(priv, ctx) {
549 if (priv->cfg->ops->hcmd->set_rxon_chain)
550 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
551 iwlcore_commit_rxon(priv, ctx);
553 mutex_unlock(&priv->mutex);
555 priv->cfg->ops->hcmd->send_bt_config(priv);
559 * iwl_bg_statistics_periodic - Timer callback to queue statistics
561 * This callback is provided in order to send a statistics request.
563 * This timer function is continually reset to execute within
564 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
565 * was received. We need to ensure we receive the statistics in order
566 * to update the temperature used for calibrating the TXPOWER.
568 static void iwl_bg_statistics_periodic(unsigned long data)
570 struct iwl_priv *priv = (struct iwl_priv *)data;
572 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
575 /* dont send host command if rf-kill is on */
576 if (!iwl_is_ready_rf(priv))
579 iwl_send_statistics_request(priv, CMD_ASYNC, false);
583 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
584 u32 start_idx, u32 num_events,
588 u32 ptr; /* SRAM byte address of log data */
589 u32 ev, time, data; /* event log data */
590 unsigned long reg_flags;
593 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
595 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
597 /* Make sure device is powered up for SRAM reads */
598 spin_lock_irqsave(&priv->reg_lock, reg_flags);
599 if (iwl_grab_nic_access(priv)) {
600 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
604 /* Set starting address; reads will auto-increment */
605 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
609 * "time" is actually "data" for mode 0 (no timestamp).
610 * place event id # at far right for easier visual parsing.
612 for (i = 0; i < num_events; i++) {
613 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
614 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
616 trace_iwlwifi_dev_ucode_cont_event(priv,
619 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
620 trace_iwlwifi_dev_ucode_cont_event(priv,
624 /* Allow device to power down */
625 iwl_release_nic_access(priv);
626 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
629 static void iwl_continuous_event_trace(struct iwl_priv *priv)
631 u32 capacity; /* event log capacity in # entries */
632 u32 base; /* SRAM byte address of event log header */
633 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
634 u32 num_wraps; /* # times uCode wrapped to top of log */
635 u32 next_entry; /* index of next entry to be written by uCode */
637 if (priv->ucode_type == UCODE_INIT)
638 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
640 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
641 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
642 capacity = iwl_read_targ_mem(priv, base);
643 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
644 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
645 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
649 if (num_wraps == priv->event_log.num_wraps) {
650 iwl_print_cont_event_trace(priv,
651 base, priv->event_log.next_entry,
652 next_entry - priv->event_log.next_entry,
654 priv->event_log.non_wraps_count++;
656 if ((num_wraps - priv->event_log.num_wraps) > 1)
657 priv->event_log.wraps_more_count++;
659 priv->event_log.wraps_once_count++;
660 trace_iwlwifi_dev_ucode_wrap_event(priv,
661 num_wraps - priv->event_log.num_wraps,
662 next_entry, priv->event_log.next_entry);
663 if (next_entry < priv->event_log.next_entry) {
664 iwl_print_cont_event_trace(priv, base,
665 priv->event_log.next_entry,
666 capacity - priv->event_log.next_entry,
669 iwl_print_cont_event_trace(priv, base, 0,
672 iwl_print_cont_event_trace(priv, base,
673 next_entry, capacity - next_entry,
676 iwl_print_cont_event_trace(priv, base, 0,
680 priv->event_log.num_wraps = num_wraps;
681 priv->event_log.next_entry = next_entry;
685 * iwl_bg_ucode_trace - Timer callback to log ucode event
687 * The timer is continually set to execute every
688 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
689 * this function is to perform continuous uCode event logging operation
692 static void iwl_bg_ucode_trace(unsigned long data)
694 struct iwl_priv *priv = (struct iwl_priv *)data;
696 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
699 if (priv->event_log.ucode_trace) {
700 iwl_continuous_event_trace(priv);
701 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
702 mod_timer(&priv->ucode_trace,
703 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
707 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
708 struct iwl_rx_mem_buffer *rxb)
710 struct iwl_rx_packet *pkt = rxb_addr(rxb);
711 struct iwl4965_beacon_notif *beacon =
712 (struct iwl4965_beacon_notif *)pkt->u.raw;
713 #ifdef CONFIG_IWLWIFI_DEBUG
714 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
716 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
717 "tsf %d %d rate %d\n",
718 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
719 beacon->beacon_notify_hdr.failure_frame,
720 le32_to_cpu(beacon->ibss_mgr_status),
721 le32_to_cpu(beacon->high_tsf),
722 le32_to_cpu(beacon->low_tsf), rate);
725 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
727 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
728 queue_work(priv->workqueue, &priv->beacon_update);
731 /* Handle notification from uCode that card's power state is changing
732 * due to software, hardware, or critical temperature RFKILL */
733 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
734 struct iwl_rx_mem_buffer *rxb)
736 struct iwl_rx_packet *pkt = rxb_addr(rxb);
737 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
738 unsigned long status = priv->status;
740 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
741 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
742 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
743 (flags & CT_CARD_DISABLED) ?
744 "Reached" : "Not reached");
746 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
749 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
750 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
752 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
753 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
755 if (!(flags & RXON_CARD_DISABLED)) {
756 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
757 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
758 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
759 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
761 if (flags & CT_CARD_DISABLED)
762 iwl_tt_enter_ct_kill(priv);
764 if (!(flags & CT_CARD_DISABLED))
765 iwl_tt_exit_ct_kill(priv);
767 if (flags & HW_CARD_DISABLED)
768 set_bit(STATUS_RF_KILL_HW, &priv->status);
770 clear_bit(STATUS_RF_KILL_HW, &priv->status);
773 if (!(flags & RXON_CARD_DISABLED))
774 iwl_scan_cancel(priv);
776 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
777 test_bit(STATUS_RF_KILL_HW, &priv->status)))
778 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
779 test_bit(STATUS_RF_KILL_HW, &priv->status));
781 wake_up_interruptible(&priv->wait_command_queue);
784 static void iwl_bg_tx_flush(struct work_struct *work)
786 struct iwl_priv *priv =
787 container_of(work, struct iwl_priv, tx_flush);
789 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
792 /* do nothing if rf-kill is on */
793 if (!iwl_is_ready_rf(priv))
796 if (priv->cfg->ops->lib->txfifo_flush) {
797 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
798 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
803 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
805 * Setup the RX handlers for each of the reply types sent from the uCode
808 * This function chains into the hardware specific files for them to setup
809 * any hardware specific handlers as well.
811 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
813 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
814 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
815 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
816 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
817 iwl_rx_spectrum_measure_notif;
818 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
819 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
820 iwl_rx_pm_debug_statistics_notif;
821 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
824 * The same handler is used for both the REPLY to a discrete
825 * statistics request from the host as well as for the periodic
826 * statistics notifications (after received beacons) from the uCode.
828 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
829 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
831 iwl_setup_rx_scan_handlers(priv);
833 /* status change handler */
834 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
836 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
837 iwl_rx_missed_beacon_notif;
839 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
840 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
842 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
843 /* Set up hardware specific Rx handlers */
844 priv->cfg->ops->lib->rx_handler_setup(priv);
848 * iwl_rx_handle - Main entry function for receiving responses from uCode
850 * Uses the priv->rx_handlers callback function array to invoke
851 * the appropriate handlers, including command responses,
852 * frame-received notifications, and other notifications.
854 static void iwl_rx_handle(struct iwl_priv *priv)
856 struct iwl_rx_mem_buffer *rxb;
857 struct iwl_rx_packet *pkt;
858 struct iwl_rx_queue *rxq = &priv->rxq;
866 /* uCode's read index (stored in shared DRAM) indicates the last Rx
867 * buffer that the driver may process (last buffer filled by ucode). */
868 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
871 /* Rx interrupt, but nothing sent from uCode */
873 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
875 /* calculate total frames need to be restock after handling RX */
876 total_empty = r - rxq->write_actual;
878 total_empty += RX_QUEUE_SIZE;
880 if (total_empty > (RX_QUEUE_SIZE / 2))
888 /* If an RXB doesn't have a Rx queue slot associated with it,
889 * then a bug has been introduced in the queue refilling
890 * routines -- catch it here */
893 rxq->queue[i] = NULL;
895 pci_unmap_page(priv->pci_dev, rxb->page_dma,
896 PAGE_SIZE << priv->hw_params.rx_page_order,
900 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
901 len += sizeof(u32); /* account for status word */
902 trace_iwlwifi_dev_rx(priv, pkt, len);
904 /* Reclaim a command buffer only if this packet is a response
905 * to a (driver-originated) command.
906 * If the packet (e.g. Rx frame) originated from uCode,
907 * there is no command buffer to reclaim.
908 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
909 * but apparently a few don't get set; catch them here. */
910 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
911 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
912 (pkt->hdr.cmd != REPLY_RX) &&
913 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
914 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
915 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
916 (pkt->hdr.cmd != REPLY_TX);
919 * Do the notification wait before RX handlers so
920 * even if the RX handler consumes the RXB we have
921 * access to it in the notification wait entry.
923 if (!list_empty(&priv->_agn.notif_waits)) {
924 struct iwl_notification_wait *w;
926 spin_lock(&priv->_agn.notif_wait_lock);
927 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
928 if (w->cmd == pkt->hdr.cmd) {
934 spin_unlock(&priv->_agn.notif_wait_lock);
936 wake_up_all(&priv->_agn.notif_waitq);
939 /* Based on type of command response or notification,
940 * handle those that need handling via function in
941 * rx_handlers table. See iwl_setup_rx_handlers() */
942 if (priv->rx_handlers[pkt->hdr.cmd]) {
943 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
944 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
945 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
946 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
948 /* No handling needed */
950 "r %d i %d No handler needed for %s, 0x%02x\n",
951 r, i, get_cmd_string(pkt->hdr.cmd),
956 * XXX: After here, we should always check rxb->page
957 * against NULL before touching it or its virtual
958 * memory (pkt). Because some rx_handler might have
959 * already taken or freed the pages.
963 /* Invoke any callbacks, transfer the buffer to caller,
964 * and fire off the (possibly) blocking iwl_send_cmd()
965 * as we reclaim the driver command queue */
967 iwl_tx_cmd_complete(priv, rxb);
969 IWL_WARN(priv, "Claim null rxb?\n");
972 /* Reuse the page if possible. For notification packets and
973 * SKBs that fail to Rx correctly, add them back into the
974 * rx_free list for reuse later. */
975 spin_lock_irqsave(&rxq->lock, flags);
976 if (rxb->page != NULL) {
977 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
978 0, PAGE_SIZE << priv->hw_params.rx_page_order,
980 list_add_tail(&rxb->list, &rxq->rx_free);
983 list_add_tail(&rxb->list, &rxq->rx_used);
985 spin_unlock_irqrestore(&rxq->lock, flags);
987 i = (i + 1) & RX_QUEUE_MASK;
988 /* If there are a lot of unused frames,
989 * restock the Rx queue so ucode wont assert. */
994 iwlagn_rx_replenish_now(priv);
1000 /* Backtrack one entry */
1003 iwlagn_rx_replenish_now(priv);
1005 iwlagn_rx_queue_restock(priv);
1008 /* call this function to flush any scheduled tasklet */
1009 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1011 /* wait to make sure we flush pending tasklet*/
1012 synchronize_irq(priv->pci_dev->irq);
1013 tasklet_kill(&priv->irq_tasklet);
1016 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1018 u32 inta, handled = 0;
1020 unsigned long flags;
1022 #ifdef CONFIG_IWLWIFI_DEBUG
1026 spin_lock_irqsave(&priv->lock, flags);
1028 /* Ack/clear/reset pending uCode interrupts.
1029 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1030 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
1031 inta = iwl_read32(priv, CSR_INT);
1032 iwl_write32(priv, CSR_INT, inta);
1034 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1035 * Any new interrupts that happen after this, either while we're
1036 * in this tasklet, or later, will show up in next ISR/tasklet. */
1037 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1038 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1040 #ifdef CONFIG_IWLWIFI_DEBUG
1041 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1042 /* just for debug */
1043 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1044 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1045 inta, inta_mask, inta_fh);
1049 spin_unlock_irqrestore(&priv->lock, flags);
1051 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1052 * atomic, make sure that inta covers all the interrupts that
1053 * we've discovered, even if FH interrupt came in just after
1054 * reading CSR_INT. */
1055 if (inta_fh & CSR49_FH_INT_RX_MASK)
1056 inta |= CSR_INT_BIT_FH_RX;
1057 if (inta_fh & CSR49_FH_INT_TX_MASK)
1058 inta |= CSR_INT_BIT_FH_TX;
1060 /* Now service all interrupt bits discovered above. */
1061 if (inta & CSR_INT_BIT_HW_ERR) {
1062 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1064 /* Tell the device to stop sending interrupts */
1065 iwl_disable_interrupts(priv);
1067 priv->isr_stats.hw++;
1068 iwl_irq_handle_error(priv);
1070 handled |= CSR_INT_BIT_HW_ERR;
1075 #ifdef CONFIG_IWLWIFI_DEBUG
1076 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1077 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1078 if (inta & CSR_INT_BIT_SCD) {
1079 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1080 "the frame/frames.\n");
1081 priv->isr_stats.sch++;
1084 /* Alive notification via Rx interrupt will do the real work */
1085 if (inta & CSR_INT_BIT_ALIVE) {
1086 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1087 priv->isr_stats.alive++;
1091 /* Safely ignore these bits for debug checks below */
1092 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1094 /* HW RF KILL switch toggled */
1095 if (inta & CSR_INT_BIT_RF_KILL) {
1097 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1098 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1101 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1102 hw_rf_kill ? "disable radio" : "enable radio");
1104 priv->isr_stats.rfkill++;
1106 /* driver only loads ucode once setting the interface up.
1107 * the driver allows loading the ucode even if the radio
1108 * is killed. Hence update the killswitch state here. The
1109 * rfkill handler will care about restarting if needed.
1111 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1113 set_bit(STATUS_RF_KILL_HW, &priv->status);
1115 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1116 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1119 handled |= CSR_INT_BIT_RF_KILL;
1122 /* Chip got too hot and stopped itself */
1123 if (inta & CSR_INT_BIT_CT_KILL) {
1124 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1125 priv->isr_stats.ctkill++;
1126 handled |= CSR_INT_BIT_CT_KILL;
1129 /* Error detected by uCode */
1130 if (inta & CSR_INT_BIT_SW_ERR) {
1131 IWL_ERR(priv, "Microcode SW error detected. "
1132 " Restarting 0x%X.\n", inta);
1133 priv->isr_stats.sw++;
1134 iwl_irq_handle_error(priv);
1135 handled |= CSR_INT_BIT_SW_ERR;
1139 * uCode wakes up after power-down sleep.
1140 * Tell device about any new tx or host commands enqueued,
1141 * and about any Rx buffers made available while asleep.
1143 if (inta & CSR_INT_BIT_WAKEUP) {
1144 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1145 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1146 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1147 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1148 priv->isr_stats.wakeup++;
1149 handled |= CSR_INT_BIT_WAKEUP;
1152 /* All uCode command responses, including Tx command responses,
1153 * Rx "responses" (frame-received notification), and other
1154 * notifications from uCode come through here*/
1155 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1156 iwl_rx_handle(priv);
1157 priv->isr_stats.rx++;
1158 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1161 /* This "Tx" DMA channel is used only for loading uCode */
1162 if (inta & CSR_INT_BIT_FH_TX) {
1163 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1164 priv->isr_stats.tx++;
1165 handled |= CSR_INT_BIT_FH_TX;
1166 /* Wake up uCode load routine, now that load is complete */
1167 priv->ucode_write_complete = 1;
1168 wake_up_interruptible(&priv->wait_command_queue);
1171 if (inta & ~handled) {
1172 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1173 priv->isr_stats.unhandled++;
1176 if (inta & ~(priv->inta_mask)) {
1177 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1178 inta & ~priv->inta_mask);
1179 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1182 /* Re-enable all interrupts */
1183 /* only Re-enable if disabled by irq */
1184 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1185 iwl_enable_interrupts(priv);
1187 #ifdef CONFIG_IWLWIFI_DEBUG
1188 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1189 inta = iwl_read32(priv, CSR_INT);
1190 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1191 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1192 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1193 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1198 /* tasklet for iwlagn interrupt */
1199 static void iwl_irq_tasklet(struct iwl_priv *priv)
1203 unsigned long flags;
1205 #ifdef CONFIG_IWLWIFI_DEBUG
1209 spin_lock_irqsave(&priv->lock, flags);
1211 /* Ack/clear/reset pending uCode interrupts.
1212 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1214 /* There is a hardware bug in the interrupt mask function that some
1215 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1216 * they are disabled in the CSR_INT_MASK register. Furthermore the
1217 * ICT interrupt handling mechanism has another bug that might cause
1218 * these unmasked interrupts fail to be detected. We workaround the
1219 * hardware bugs here by ACKing all the possible interrupts so that
1220 * interrupt coalescing can still be achieved.
1222 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1224 inta = priv->_agn.inta;
1226 #ifdef CONFIG_IWLWIFI_DEBUG
1227 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1228 /* just for debug */
1229 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1230 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1235 spin_unlock_irqrestore(&priv->lock, flags);
1237 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1238 priv->_agn.inta = 0;
1240 /* Now service all interrupt bits discovered above. */
1241 if (inta & CSR_INT_BIT_HW_ERR) {
1242 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1244 /* Tell the device to stop sending interrupts */
1245 iwl_disable_interrupts(priv);
1247 priv->isr_stats.hw++;
1248 iwl_irq_handle_error(priv);
1250 handled |= CSR_INT_BIT_HW_ERR;
1255 #ifdef CONFIG_IWLWIFI_DEBUG
1256 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1257 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1258 if (inta & CSR_INT_BIT_SCD) {
1259 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1260 "the frame/frames.\n");
1261 priv->isr_stats.sch++;
1264 /* Alive notification via Rx interrupt will do the real work */
1265 if (inta & CSR_INT_BIT_ALIVE) {
1266 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1267 priv->isr_stats.alive++;
1271 /* Safely ignore these bits for debug checks below */
1272 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1274 /* HW RF KILL switch toggled */
1275 if (inta & CSR_INT_BIT_RF_KILL) {
1277 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1278 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1281 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1282 hw_rf_kill ? "disable radio" : "enable radio");
1284 priv->isr_stats.rfkill++;
1286 /* driver only loads ucode once setting the interface up.
1287 * the driver allows loading the ucode even if the radio
1288 * is killed. Hence update the killswitch state here. The
1289 * rfkill handler will care about restarting if needed.
1291 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1293 set_bit(STATUS_RF_KILL_HW, &priv->status);
1295 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1296 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1299 handled |= CSR_INT_BIT_RF_KILL;
1302 /* Chip got too hot and stopped itself */
1303 if (inta & CSR_INT_BIT_CT_KILL) {
1304 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1305 priv->isr_stats.ctkill++;
1306 handled |= CSR_INT_BIT_CT_KILL;
1309 /* Error detected by uCode */
1310 if (inta & CSR_INT_BIT_SW_ERR) {
1311 IWL_ERR(priv, "Microcode SW error detected. "
1312 " Restarting 0x%X.\n", inta);
1313 priv->isr_stats.sw++;
1314 iwl_irq_handle_error(priv);
1315 handled |= CSR_INT_BIT_SW_ERR;
1318 /* uCode wakes up after power-down sleep */
1319 if (inta & CSR_INT_BIT_WAKEUP) {
1320 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1321 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1322 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1323 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1325 priv->isr_stats.wakeup++;
1327 handled |= CSR_INT_BIT_WAKEUP;
1330 /* All uCode command responses, including Tx command responses,
1331 * Rx "responses" (frame-received notification), and other
1332 * notifications from uCode come through here*/
1333 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1334 CSR_INT_BIT_RX_PERIODIC)) {
1335 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1336 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1337 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1338 iwl_write32(priv, CSR_FH_INT_STATUS,
1339 CSR49_FH_INT_RX_MASK);
1341 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1342 handled |= CSR_INT_BIT_RX_PERIODIC;
1343 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1345 /* Sending RX interrupt require many steps to be done in the
1347 * 1- write interrupt to current index in ICT table.
1349 * 3- update RX shared data to indicate last write index.
1350 * 4- send interrupt.
1351 * This could lead to RX race, driver could receive RX interrupt
1352 * but the shared data changes does not reflect this;
1353 * periodic interrupt will detect any dangling Rx activity.
1356 /* Disable periodic interrupt; we use it as just a one-shot. */
1357 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1358 CSR_INT_PERIODIC_DIS);
1359 iwl_rx_handle(priv);
1362 * Enable periodic interrupt in 8 msec only if we received
1363 * real RX interrupt (instead of just periodic int), to catch
1364 * any dangling Rx interrupt. If it was just the periodic
1365 * interrupt, there was no dangling Rx activity, and no need
1366 * to extend the periodic interrupt; one-shot is enough.
1368 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1369 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1370 CSR_INT_PERIODIC_ENA);
1372 priv->isr_stats.rx++;
1375 /* This "Tx" DMA channel is used only for loading uCode */
1376 if (inta & CSR_INT_BIT_FH_TX) {
1377 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1378 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1379 priv->isr_stats.tx++;
1380 handled |= CSR_INT_BIT_FH_TX;
1381 /* Wake up uCode load routine, now that load is complete */
1382 priv->ucode_write_complete = 1;
1383 wake_up_interruptible(&priv->wait_command_queue);
1386 if (inta & ~handled) {
1387 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1388 priv->isr_stats.unhandled++;
1391 if (inta & ~(priv->inta_mask)) {
1392 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1393 inta & ~priv->inta_mask);
1396 /* Re-enable all interrupts */
1397 /* only Re-enable if disabled by irq */
1398 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1399 iwl_enable_interrupts(priv);
1402 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1403 #define ACK_CNT_RATIO (50)
1404 #define BA_TIMEOUT_CNT (5)
1405 #define BA_TIMEOUT_MAX (16)
1408 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1410 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1411 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1414 bool iwl_good_ack_health(struct iwl_priv *priv,
1415 struct iwl_rx_packet *pkt)
1418 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1419 int ba_timeout_delta;
1421 actual_ack_cnt_delta =
1422 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1423 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1424 expected_ack_cnt_delta =
1425 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1426 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1428 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1429 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1430 if ((priv->_agn.agg_tids_count > 0) &&
1431 (expected_ack_cnt_delta > 0) &&
1432 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1434 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1435 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1436 " expected_ack_cnt = %d\n",
1437 actual_ack_cnt_delta, expected_ack_cnt_delta);
1439 #ifdef CONFIG_IWLWIFI_DEBUGFS
1441 * This is ifdef'ed on DEBUGFS because otherwise the
1442 * statistics aren't available. If DEBUGFS is set but
1443 * DEBUG is not, these will just compile out.
1445 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1446 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1447 IWL_DEBUG_RADIO(priv,
1448 "ack_or_ba_timeout_collision delta = %d\n",
1449 priv->_agn.delta_statistics.tx.
1450 ack_or_ba_timeout_collision);
1452 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1454 if (!actual_ack_cnt_delta &&
1455 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1462 /*****************************************************************************
1466 *****************************************************************************/
1468 #ifdef CONFIG_IWLWIFI_DEBUG
1471 * The following adds a new attribute to the sysfs representation
1472 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1473 * used for controlling the debug level.
1475 * See the level definitions in iwl for details.
1477 * The debug_level being managed using sysfs below is a per device debug
1478 * level that is used instead of the global debug level if it (the per
1479 * device debug level) is set.
1481 static ssize_t show_debug_level(struct device *d,
1482 struct device_attribute *attr, char *buf)
1484 struct iwl_priv *priv = dev_get_drvdata(d);
1485 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1487 static ssize_t store_debug_level(struct device *d,
1488 struct device_attribute *attr,
1489 const char *buf, size_t count)
1491 struct iwl_priv *priv = dev_get_drvdata(d);
1495 ret = strict_strtoul(buf, 0, &val);
1497 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1499 priv->debug_level = val;
1500 if (iwl_alloc_traffic_mem(priv))
1502 "Not enough memory to generate traffic log\n");
1504 return strnlen(buf, count);
1507 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1508 show_debug_level, store_debug_level);
1511 #endif /* CONFIG_IWLWIFI_DEBUG */
1514 static ssize_t show_temperature(struct device *d,
1515 struct device_attribute *attr, char *buf)
1517 struct iwl_priv *priv = dev_get_drvdata(d);
1519 if (!iwl_is_alive(priv))
1522 return sprintf(buf, "%d\n", priv->temperature);
1525 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1527 static ssize_t show_tx_power(struct device *d,
1528 struct device_attribute *attr, char *buf)
1530 struct iwl_priv *priv = dev_get_drvdata(d);
1532 if (!iwl_is_ready_rf(priv))
1533 return sprintf(buf, "off\n");
1535 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1538 static ssize_t store_tx_power(struct device *d,
1539 struct device_attribute *attr,
1540 const char *buf, size_t count)
1542 struct iwl_priv *priv = dev_get_drvdata(d);
1546 ret = strict_strtoul(buf, 10, &val);
1548 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1550 ret = iwl_set_tx_power(priv, val, false);
1552 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1560 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1562 static struct attribute *iwl_sysfs_entries[] = {
1563 &dev_attr_temperature.attr,
1564 &dev_attr_tx_power.attr,
1565 #ifdef CONFIG_IWLWIFI_DEBUG
1566 &dev_attr_debug_level.attr,
1571 static struct attribute_group iwl_attribute_group = {
1572 .name = NULL, /* put in device directory */
1573 .attrs = iwl_sysfs_entries,
1576 /******************************************************************************
1578 * uCode download functions
1580 ******************************************************************************/
1582 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1584 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1585 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1586 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1587 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1588 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1589 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1592 static void iwl_nic_start(struct iwl_priv *priv)
1594 /* Remove all resets to allow NIC to operate */
1595 iwl_write32(priv, CSR_RESET, 0);
1598 struct iwlagn_ucode_capabilities {
1599 u32 max_probe_length;
1600 u32 standard_phy_calibration_size;
1604 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1605 static int iwl_mac_setup_register(struct iwl_priv *priv,
1606 struct iwlagn_ucode_capabilities *capa);
1608 #define UCODE_EXPERIMENTAL_INDEX 100
1609 #define UCODE_EXPERIMENTAL_TAG "exp"
1611 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1613 const char *name_pre = priv->cfg->fw_name_pre;
1617 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1618 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1619 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1620 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1622 priv->fw_index = priv->cfg->ucode_api_max;
1623 sprintf(tag, "%d", priv->fw_index);
1626 sprintf(tag, "%d", priv->fw_index);
1629 if (priv->fw_index < priv->cfg->ucode_api_min) {
1630 IWL_ERR(priv, "no suitable firmware found!\n");
1634 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1636 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1637 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1638 ? "EXPERIMENTAL " : "",
1639 priv->firmware_name);
1641 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1642 &priv->pci_dev->dev, GFP_KERNEL, priv,
1643 iwl_ucode_callback);
1646 struct iwlagn_firmware_pieces {
1647 const void *inst, *data, *init, *init_data, *boot;
1648 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1652 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1653 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1656 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1657 const struct firmware *ucode_raw,
1658 struct iwlagn_firmware_pieces *pieces)
1660 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1661 u32 api_ver, hdr_size;
1664 priv->ucode_ver = le32_to_cpu(ucode->ver);
1665 api_ver = IWL_UCODE_API(priv->ucode_ver);
1670 * 4965 doesn't revision the firmware file format
1671 * along with the API version, it always uses v1
1674 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1675 CSR_HW_REV_TYPE_4965) {
1677 if (ucode_raw->size < hdr_size) {
1678 IWL_ERR(priv, "File size too small!\n");
1681 pieces->build = le32_to_cpu(ucode->u.v2.build);
1682 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1683 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1684 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1685 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1686 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1687 src = ucode->u.v2.data;
1690 /* fall through for 4965 */
1695 if (ucode_raw->size < hdr_size) {
1696 IWL_ERR(priv, "File size too small!\n");
1700 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1701 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1702 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1703 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1704 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1705 src = ucode->u.v1.data;
1709 /* Verify size of file vs. image size info in file's header */
1710 if (ucode_raw->size != hdr_size + pieces->inst_size +
1711 pieces->data_size + pieces->init_size +
1712 pieces->init_data_size + pieces->boot_size) {
1715 "uCode file size %d does not match expected size\n",
1716 (int)ucode_raw->size);
1721 src += pieces->inst_size;
1723 src += pieces->data_size;
1725 src += pieces->init_size;
1726 pieces->init_data = src;
1727 src += pieces->init_data_size;
1729 src += pieces->boot_size;
1734 static int iwlagn_wanted_ucode_alternative = 1;
1736 static int iwlagn_load_firmware(struct iwl_priv *priv,
1737 const struct firmware *ucode_raw,
1738 struct iwlagn_firmware_pieces *pieces,
1739 struct iwlagn_ucode_capabilities *capa)
1741 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1742 struct iwl_ucode_tlv *tlv;
1743 size_t len = ucode_raw->size;
1745 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1748 enum iwl_ucode_tlv_type tlv_type;
1751 if (len < sizeof(*ucode)) {
1752 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1756 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1757 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1758 le32_to_cpu(ucode->magic));
1763 * Check which alternatives are present, and "downgrade"
1764 * when the chosen alternative is not present, warning
1765 * the user when that happens. Some files may not have
1766 * any alternatives, so don't warn in that case.
1768 alternatives = le64_to_cpu(ucode->alternatives);
1769 tmp = wanted_alternative;
1770 if (wanted_alternative > 63)
1771 wanted_alternative = 63;
1772 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1773 wanted_alternative--;
1774 if (wanted_alternative && wanted_alternative != tmp)
1776 "uCode alternative %d not available, choosing %d\n",
1777 tmp, wanted_alternative);
1779 priv->ucode_ver = le32_to_cpu(ucode->ver);
1780 pieces->build = le32_to_cpu(ucode->build);
1783 len -= sizeof(*ucode);
1785 while (len >= sizeof(*tlv)) {
1788 len -= sizeof(*tlv);
1791 tlv_len = le32_to_cpu(tlv->length);
1792 tlv_type = le16_to_cpu(tlv->type);
1793 tlv_alt = le16_to_cpu(tlv->alternative);
1794 tlv_data = tlv->data;
1796 if (len < tlv_len) {
1797 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1801 len -= ALIGN(tlv_len, 4);
1802 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1805 * Alternative 0 is always valid.
1807 * Skip alternative TLVs that are not selected.
1809 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1813 case IWL_UCODE_TLV_INST:
1814 pieces->inst = tlv_data;
1815 pieces->inst_size = tlv_len;
1817 case IWL_UCODE_TLV_DATA:
1818 pieces->data = tlv_data;
1819 pieces->data_size = tlv_len;
1821 case IWL_UCODE_TLV_INIT:
1822 pieces->init = tlv_data;
1823 pieces->init_size = tlv_len;
1825 case IWL_UCODE_TLV_INIT_DATA:
1826 pieces->init_data = tlv_data;
1827 pieces->init_data_size = tlv_len;
1829 case IWL_UCODE_TLV_BOOT:
1830 pieces->boot = tlv_data;
1831 pieces->boot_size = tlv_len;
1833 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1834 if (tlv_len != sizeof(u32))
1835 goto invalid_tlv_len;
1836 capa->max_probe_length =
1837 le32_to_cpup((__le32 *)tlv_data);
1839 case IWL_UCODE_TLV_PAN:
1841 goto invalid_tlv_len;
1844 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1845 if (tlv_len != sizeof(u32))
1846 goto invalid_tlv_len;
1847 pieces->init_evtlog_ptr =
1848 le32_to_cpup((__le32 *)tlv_data);
1850 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1851 if (tlv_len != sizeof(u32))
1852 goto invalid_tlv_len;
1853 pieces->init_evtlog_size =
1854 le32_to_cpup((__le32 *)tlv_data);
1856 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1857 if (tlv_len != sizeof(u32))
1858 goto invalid_tlv_len;
1859 pieces->init_errlog_ptr =
1860 le32_to_cpup((__le32 *)tlv_data);
1862 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1863 if (tlv_len != sizeof(u32))
1864 goto invalid_tlv_len;
1865 pieces->inst_evtlog_ptr =
1866 le32_to_cpup((__le32 *)tlv_data);
1868 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1869 if (tlv_len != sizeof(u32))
1870 goto invalid_tlv_len;
1871 pieces->inst_evtlog_size =
1872 le32_to_cpup((__le32 *)tlv_data);
1874 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1875 if (tlv_len != sizeof(u32))
1876 goto invalid_tlv_len;
1877 pieces->inst_errlog_ptr =
1878 le32_to_cpup((__le32 *)tlv_data);
1880 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1882 goto invalid_tlv_len;
1883 priv->enhance_sensitivity_table = true;
1885 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1886 if (tlv_len != sizeof(u32))
1887 goto invalid_tlv_len;
1888 capa->standard_phy_calibration_size =
1889 le32_to_cpup((__le32 *)tlv_data);
1892 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1898 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1899 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1906 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1907 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1913 * iwl_ucode_callback - callback when firmware was loaded
1915 * If loaded successfully, copies the firmware into buffers
1916 * for the card to fetch (via DMA).
1918 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1920 struct iwl_priv *priv = context;
1921 struct iwl_ucode_header *ucode;
1923 struct iwlagn_firmware_pieces pieces;
1924 const unsigned int api_max = priv->cfg->ucode_api_max;
1925 const unsigned int api_min = priv->cfg->ucode_api_min;
1929 struct iwlagn_ucode_capabilities ucode_capa = {
1930 .max_probe_length = 200,
1931 .standard_phy_calibration_size =
1932 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1935 memset(&pieces, 0, sizeof(pieces));
1938 if (priv->fw_index <= priv->cfg->ucode_api_max)
1940 "request for firmware file '%s' failed.\n",
1941 priv->firmware_name);
1945 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1946 priv->firmware_name, ucode_raw->size);
1948 /* Make sure that we got at least the API version number */
1949 if (ucode_raw->size < 4) {
1950 IWL_ERR(priv, "File size way too small!\n");
1954 /* Data from ucode file: header followed by uCode images */
1955 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1958 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1960 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1966 api_ver = IWL_UCODE_API(priv->ucode_ver);
1967 build = pieces.build;
1970 * api_ver should match the api version forming part of the
1971 * firmware filename ... but we don't check for that and only rely
1972 * on the API version read from firmware header from here on forward
1974 /* no api version check required for experimental uCode */
1975 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1976 if (api_ver < api_min || api_ver > api_max) {
1978 "Driver unable to support your firmware API. "
1979 "Driver supports v%u, firmware is v%u.\n",
1984 if (api_ver != api_max)
1986 "Firmware has old API version. Expected v%u, "
1987 "got v%u. New firmware can be obtained "
1988 "from http://www.intellinuxwireless.org.\n",
1993 sprintf(buildstr, " build %u%s", build,
1994 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1999 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2000 IWL_UCODE_MAJOR(priv->ucode_ver),
2001 IWL_UCODE_MINOR(priv->ucode_ver),
2002 IWL_UCODE_API(priv->ucode_ver),
2003 IWL_UCODE_SERIAL(priv->ucode_ver),
2006 snprintf(priv->hw->wiphy->fw_version,
2007 sizeof(priv->hw->wiphy->fw_version),
2009 IWL_UCODE_MAJOR(priv->ucode_ver),
2010 IWL_UCODE_MINOR(priv->ucode_ver),
2011 IWL_UCODE_API(priv->ucode_ver),
2012 IWL_UCODE_SERIAL(priv->ucode_ver),
2016 * For any of the failures below (before allocating pci memory)
2017 * we will try to load a version with a smaller API -- maybe the
2018 * user just got a corrupted version of the latest API.
2021 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2023 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2025 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2027 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2029 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2030 pieces.init_data_size);
2031 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2034 /* Verify that uCode images will fit in card's SRAM */
2035 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2036 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2041 if (pieces.data_size > priv->hw_params.max_data_size) {
2042 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2047 if (pieces.init_size > priv->hw_params.max_inst_size) {
2048 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2053 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2054 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2055 pieces.init_data_size);
2059 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2060 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2065 /* Allocate ucode buffers for card's bus-master loading ... */
2067 /* Runtime instructions and 2 copies of data:
2068 * 1) unmodified from disk
2069 * 2) backup cache for save/restore during power-downs */
2070 priv->ucode_code.len = pieces.inst_size;
2071 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2073 priv->ucode_data.len = pieces.data_size;
2074 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2076 priv->ucode_data_backup.len = pieces.data_size;
2077 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2079 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2080 !priv->ucode_data_backup.v_addr)
2083 /* Initialization instructions and data */
2084 if (pieces.init_size && pieces.init_data_size) {
2085 priv->ucode_init.len = pieces.init_size;
2086 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2088 priv->ucode_init_data.len = pieces.init_data_size;
2089 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2091 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2095 /* Bootstrap (instructions only, no data) */
2096 if (pieces.boot_size) {
2097 priv->ucode_boot.len = pieces.boot_size;
2098 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2100 if (!priv->ucode_boot.v_addr)
2104 /* Now that we can no longer fail, copy information */
2107 * The (size - 16) / 12 formula is based on the information recorded
2108 * for each event, which is of mode 1 (including timestamp) for all
2109 * new microcodes that include this information.
2111 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2112 if (pieces.init_evtlog_size)
2113 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2115 priv->_agn.init_evtlog_size =
2116 priv->cfg->base_params->max_event_log_size;
2117 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2118 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2119 if (pieces.inst_evtlog_size)
2120 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2122 priv->_agn.inst_evtlog_size =
2123 priv->cfg->base_params->max_event_log_size;
2124 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2126 if (ucode_capa.pan) {
2127 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2128 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2130 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2132 /* Copy images into buffers for card's bus-master reads ... */
2134 /* Runtime instructions (first block of data in file) */
2135 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2137 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2139 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2140 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2144 * NOTE: Copy into backup buffer will be done in iwl_up()
2146 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2148 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2149 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2151 /* Initialization instructions */
2152 if (pieces.init_size) {
2153 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2155 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2158 /* Initialization data */
2159 if (pieces.init_data_size) {
2160 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2161 pieces.init_data_size);
2162 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2163 pieces.init_data_size);
2166 /* Bootstrap instructions */
2167 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2169 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2172 * figure out the offset of chain noise reset and gain commands
2173 * base on the size of standard phy calibration commands table size
2175 if (ucode_capa.standard_phy_calibration_size >
2176 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2177 ucode_capa.standard_phy_calibration_size =
2178 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2180 priv->_agn.phy_calib_chain_noise_reset_cmd =
2181 ucode_capa.standard_phy_calibration_size;
2182 priv->_agn.phy_calib_chain_noise_gain_cmd =
2183 ucode_capa.standard_phy_calibration_size + 1;
2185 /**************************************************
2186 * This is still part of probe() in a sense...
2188 * 9. Setup and register with mac80211 and debugfs
2189 **************************************************/
2190 err = iwl_mac_setup_register(priv, &ucode_capa);
2194 err = iwl_dbgfs_register(priv, DRV_NAME);
2196 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2198 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2199 &iwl_attribute_group);
2201 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2205 /* We have our copies now, allow OS release its copies */
2206 release_firmware(ucode_raw);
2207 complete(&priv->_agn.firmware_loading_complete);
2211 /* try next, if any */
2212 if (iwl_request_firmware(priv, false))
2214 release_firmware(ucode_raw);
2218 IWL_ERR(priv, "failed to allocate pci memory\n");
2219 iwl_dealloc_ucode_pci(priv);
2221 complete(&priv->_agn.firmware_loading_complete);
2222 device_release_driver(&priv->pci_dev->dev);
2223 release_firmware(ucode_raw);
2226 static const char *desc_lookup_text[] = {
2231 "NMI_INTERRUPT_WDG",
2235 "HW_ERROR_TUNE_LOCK",
2236 "HW_ERROR_TEMPERATURE",
2237 "ILLEGAL_CHAN_FREQ",
2240 "NMI_INTERRUPT_HOST",
2241 "NMI_INTERRUPT_ACTION_PT",
2242 "NMI_INTERRUPT_UNKNOWN",
2243 "UCODE_VERSION_MISMATCH",
2244 "HW_ERROR_ABS_LOCK",
2245 "HW_ERROR_CAL_LOCK_FAIL",
2246 "NMI_INTERRUPT_INST_ACTION_PT",
2247 "NMI_INTERRUPT_DATA_ACTION_PT",
2249 "NMI_INTERRUPT_TRM",
2250 "NMI_INTERRUPT_BREAK_POINT"
2257 static struct { char *name; u8 num; } advanced_lookup[] = {
2258 { "NMI_INTERRUPT_WDG", 0x34 },
2259 { "SYSASSERT", 0x35 },
2260 { "UCODE_VERSION_MISMATCH", 0x37 },
2261 { "BAD_COMMAND", 0x38 },
2262 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2263 { "FATAL_ERROR", 0x3D },
2264 { "NMI_TRM_HW_ERR", 0x46 },
2265 { "NMI_INTERRUPT_TRM", 0x4C },
2266 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2267 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2268 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2269 { "NMI_INTERRUPT_HOST", 0x66 },
2270 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2271 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2272 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2273 { "ADVANCED_SYSASSERT", 0 },
2276 static const char *desc_lookup(u32 num)
2279 int max = ARRAY_SIZE(desc_lookup_text);
2282 return desc_lookup_text[num];
2284 max = ARRAY_SIZE(advanced_lookup) - 1;
2285 for (i = 0; i < max; i++) {
2286 if (advanced_lookup[i].num == num)
2289 return advanced_lookup[i].name;
2292 #define ERROR_START_OFFSET (1 * sizeof(u32))
2293 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
2295 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2298 u32 desc, time, count, base, data1;
2299 u32 blink1, blink2, ilink1, ilink2;
2302 if (priv->ucode_type == UCODE_INIT) {
2303 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2305 base = priv->_agn.init_errlog_ptr;
2307 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2309 base = priv->_agn.inst_errlog_ptr;
2312 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2314 "Not valid error log pointer 0x%08X for %s uCode\n",
2315 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2319 count = iwl_read_targ_mem(priv, base);
2321 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2322 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2323 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2324 priv->status, count);
2327 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2328 priv->isr_stats.err_code = desc;
2329 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2330 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2331 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2332 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2333 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2334 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2335 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2336 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2337 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2338 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2340 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2341 blink1, blink2, ilink1, ilink2);
2343 IWL_ERR(priv, "Desc Time "
2344 "data1 data2 line\n");
2345 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2346 desc_lookup(desc), desc, time, data1, data2, line);
2347 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2348 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2349 pc, blink1, blink2, ilink1, ilink2, hcmd);
2352 #define EVENT_START_OFFSET (4 * sizeof(u32))
2355 * iwl_print_event_log - Dump error event log to syslog
2358 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2359 u32 num_events, u32 mode,
2360 int pos, char **buf, size_t bufsz)
2363 u32 base; /* SRAM byte address of event log header */
2364 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2365 u32 ptr; /* SRAM byte address of log data */
2366 u32 ev, time, data; /* event log data */
2367 unsigned long reg_flags;
2369 if (num_events == 0)
2372 if (priv->ucode_type == UCODE_INIT) {
2373 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2375 base = priv->_agn.init_evtlog_ptr;
2377 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2379 base = priv->_agn.inst_evtlog_ptr;
2383 event_size = 2 * sizeof(u32);
2385 event_size = 3 * sizeof(u32);
2387 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2389 /* Make sure device is powered up for SRAM reads */
2390 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2391 iwl_grab_nic_access(priv);
2393 /* Set starting address; reads will auto-increment */
2394 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2397 /* "time" is actually "data" for mode 0 (no timestamp).
2398 * place event id # at far right for easier visual parsing. */
2399 for (i = 0; i < num_events; i++) {
2400 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2401 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2405 pos += scnprintf(*buf + pos, bufsz - pos,
2406 "EVT_LOG:0x%08x:%04u\n",
2409 trace_iwlwifi_dev_ucode_event(priv, 0,
2411 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2415 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2417 pos += scnprintf(*buf + pos, bufsz - pos,
2418 "EVT_LOGT:%010u:0x%08x:%04u\n",
2421 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2423 trace_iwlwifi_dev_ucode_event(priv, time,
2429 /* Allow device to power down */
2430 iwl_release_nic_access(priv);
2431 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2436 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2438 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2439 u32 num_wraps, u32 next_entry,
2441 int pos, char **buf, size_t bufsz)
2444 * display the newest DEFAULT_LOG_ENTRIES entries
2445 * i.e the entries just before the next ont that uCode would fill.
2448 if (next_entry < size) {
2449 pos = iwl_print_event_log(priv,
2450 capacity - (size - next_entry),
2451 size - next_entry, mode,
2453 pos = iwl_print_event_log(priv, 0,
2457 pos = iwl_print_event_log(priv, next_entry - size,
2458 size, mode, pos, buf, bufsz);
2460 if (next_entry < size) {
2461 pos = iwl_print_event_log(priv, 0, next_entry,
2462 mode, pos, buf, bufsz);
2464 pos = iwl_print_event_log(priv, next_entry - size,
2465 size, mode, pos, buf, bufsz);
2471 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2473 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2474 char **buf, bool display)
2476 u32 base; /* SRAM byte address of event log header */
2477 u32 capacity; /* event log capacity in # entries */
2478 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2479 u32 num_wraps; /* # times uCode wrapped to top of log */
2480 u32 next_entry; /* index of next entry to be written by uCode */
2481 u32 size; /* # entries that we'll print */
2486 if (priv->ucode_type == UCODE_INIT) {
2487 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2488 logsize = priv->_agn.init_evtlog_size;
2490 base = priv->_agn.init_evtlog_ptr;
2492 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2493 logsize = priv->_agn.inst_evtlog_size;
2495 base = priv->_agn.inst_evtlog_ptr;
2498 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2500 "Invalid event log pointer 0x%08X for %s uCode\n",
2501 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2505 /* event log header */
2506 capacity = iwl_read_targ_mem(priv, base);
2507 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2508 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2509 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2511 if (capacity > logsize) {
2512 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2517 if (next_entry > logsize) {
2518 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2519 next_entry, logsize);
2520 next_entry = logsize;
2523 size = num_wraps ? capacity : next_entry;
2525 /* bail out if nothing in log */
2527 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2531 /* enable/disable bt channel inhibition */
2532 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2534 #ifdef CONFIG_IWLWIFI_DEBUG
2535 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2536 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2537 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2539 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2540 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2542 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2545 #ifdef CONFIG_IWLWIFI_DEBUG
2548 bufsz = capacity * 48;
2551 *buf = kmalloc(bufsz, GFP_KERNEL);
2555 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2557 * if uCode has wrapped back to top of log,
2558 * start at the oldest entry,
2559 * i.e the next one that uCode would fill.
2562 pos = iwl_print_event_log(priv, next_entry,
2563 capacity - next_entry, mode,
2565 /* (then/else) start at top of log */
2566 pos = iwl_print_event_log(priv, 0,
2567 next_entry, mode, pos, buf, bufsz);
2569 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2570 next_entry, size, mode,
2573 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2574 next_entry, size, mode,
2580 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2582 struct iwl_ct_kill_config cmd;
2583 struct iwl_ct_kill_throttling_config adv_cmd;
2584 unsigned long flags;
2587 spin_lock_irqsave(&priv->lock, flags);
2588 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2589 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2590 spin_unlock_irqrestore(&priv->lock, flags);
2591 priv->thermal_throttle.ct_kill_toggle = false;
2593 if (priv->cfg->base_params->support_ct_kill_exit) {
2594 adv_cmd.critical_temperature_enter =
2595 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2596 adv_cmd.critical_temperature_exit =
2597 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2599 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2600 sizeof(adv_cmd), &adv_cmd);
2602 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2604 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2606 "critical temperature enter is %d,"
2608 priv->hw_params.ct_kill_threshold,
2609 priv->hw_params.ct_kill_exit_threshold);
2611 cmd.critical_temperature_R =
2612 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2614 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2617 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2619 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2621 "critical temperature is %d\n",
2622 priv->hw_params.ct_kill_threshold);
2626 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2628 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2629 struct iwl_host_cmd cmd = {
2630 .id = CALIBRATION_CFG_CMD,
2631 .len = sizeof(struct iwl_calib_cfg_cmd),
2632 .data = &calib_cfg_cmd,
2635 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2636 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2637 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2639 return iwl_send_cmd(priv, &cmd);
2644 * iwl_alive_start - called after REPLY_ALIVE notification received
2645 * from protocol/runtime uCode (initialization uCode's
2646 * Alive gets handled by iwl_init_alive_start()).
2648 static void iwl_alive_start(struct iwl_priv *priv)
2651 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2653 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2655 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2656 * This is a paranoid check, because we would not have gotten the
2657 * "runtime" alive if code weren't properly loaded. */
2658 if (iwl_verify_ucode(priv)) {
2659 /* Runtime instruction load was bad;
2660 * take it all the way back down so we can try again */
2661 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2665 ret = priv->cfg->ops->lib->alive_notify(priv);
2668 "Could not complete ALIVE transition [ntf]: %d\n", ret);
2673 /* After the ALIVE response, we can send host commands to the uCode */
2674 set_bit(STATUS_ALIVE, &priv->status);
2676 /* Enable watchdog to monitor the driver tx queues */
2677 iwl_setup_watchdog(priv);
2679 if (iwl_is_rfkill(priv))
2682 /* download priority table before any calibration request */
2683 if (priv->cfg->bt_params &&
2684 priv->cfg->bt_params->advanced_bt_coexist) {
2685 /* Configure Bluetooth device coexistence support */
2686 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2687 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2688 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2689 priv->cfg->ops->hcmd->send_bt_config(priv);
2690 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2691 iwlagn_send_prio_tbl(priv);
2693 /* FIXME: w/a to force change uCode BT state machine */
2694 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2695 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2696 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2697 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2699 if (priv->hw_params.calib_rt_cfg)
2700 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2702 ieee80211_wake_queues(priv->hw);
2704 priv->active_rate = IWL_RATES_MASK;
2706 /* Configure Tx antenna selection based on H/W config */
2707 if (priv->cfg->ops->hcmd->set_tx_ant)
2708 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2710 if (iwl_is_associated_ctx(ctx)) {
2711 struct iwl_rxon_cmd *active_rxon =
2712 (struct iwl_rxon_cmd *)&ctx->active;
2713 /* apply any changes in staging */
2714 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2715 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2717 struct iwl_rxon_context *tmp;
2718 /* Initialize our rx_config data */
2719 for_each_context(priv, tmp)
2720 iwl_connection_init_rx_config(priv, tmp);
2722 if (priv->cfg->ops->hcmd->set_rxon_chain)
2723 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2726 if (priv->cfg->bt_params &&
2727 !priv->cfg->bt_params->advanced_bt_coexist) {
2728 /* Configure Bluetooth device coexistence support */
2729 priv->cfg->ops->hcmd->send_bt_config(priv);
2732 iwl_reset_run_time_calib(priv);
2734 set_bit(STATUS_READY, &priv->status);
2736 /* Configure the adapter for unassociated operation */
2737 iwlcore_commit_rxon(priv, ctx);
2739 /* At this point, the NIC is initialized and operational */
2740 iwl_rf_kill_ct_config(priv);
2742 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2743 wake_up_interruptible(&priv->wait_command_queue);
2745 iwl_power_update_mode(priv, true);
2746 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2752 queue_work(priv->workqueue, &priv->restart);
2755 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2757 static void __iwl_down(struct iwl_priv *priv)
2759 unsigned long flags;
2760 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2762 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2764 iwl_scan_cancel_timeout(priv, 200);
2766 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2768 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2769 * to prevent rearm timer */
2770 del_timer_sync(&priv->watchdog);
2772 iwl_clear_ucode_stations(priv, NULL);
2773 iwl_dealloc_bcast_stations(priv);
2774 iwl_clear_driver_stations(priv);
2776 /* reset BT coex data */
2777 priv->bt_status = 0;
2778 if (priv->cfg->bt_params)
2779 priv->bt_traffic_load =
2780 priv->cfg->bt_params->bt_init_traffic_load;
2782 priv->bt_traffic_load = 0;
2783 priv->bt_sco_active = false;
2784 priv->bt_full_concurrent = false;
2785 priv->bt_ci_compliance = 0;
2787 /* Unblock any waiting calls */
2788 wake_up_interruptible_all(&priv->wait_command_queue);
2790 /* Wipe out the EXIT_PENDING status bit if we are not actually
2791 * exiting the module */
2793 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2795 /* stop and reset the on-board processor */
2796 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2798 /* tell the device to stop sending interrupts */
2799 spin_lock_irqsave(&priv->lock, flags);
2800 iwl_disable_interrupts(priv);
2801 spin_unlock_irqrestore(&priv->lock, flags);
2802 iwl_synchronize_irq(priv);
2804 if (priv->mac80211_registered)
2805 ieee80211_stop_queues(priv->hw);
2807 /* If we have not previously called iwl_init() then
2808 * clear all bits but the RF Kill bit and return */
2809 if (!iwl_is_init(priv)) {
2810 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2812 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2813 STATUS_GEO_CONFIGURED |
2814 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2815 STATUS_EXIT_PENDING;
2819 /* ...otherwise clear out all the status bits but the RF Kill
2820 * bit and continue taking the NIC down. */
2821 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2823 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2824 STATUS_GEO_CONFIGURED |
2825 test_bit(STATUS_FW_ERROR, &priv->status) <<
2827 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2828 STATUS_EXIT_PENDING;
2830 /* device going down, Stop using ICT table */
2831 if (priv->cfg->ops->lib->isr_ops.disable)
2832 priv->cfg->ops->lib->isr_ops.disable(priv);
2834 iwlagn_txq_ctx_stop(priv);
2835 iwlagn_rxq_stop(priv);
2837 /* Power-down device's busmaster DMA clocks */
2838 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2841 /* Make sure (redundant) we've released our request to stay awake */
2842 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2844 /* Stop the device, and put it in low power state */
2848 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2850 dev_kfree_skb(priv->beacon_skb);
2851 priv->beacon_skb = NULL;
2853 /* clear out any free frames */
2854 iwl_clear_free_frames(priv);
2857 static void iwl_down(struct iwl_priv *priv)
2859 mutex_lock(&priv->mutex);
2861 mutex_unlock(&priv->mutex);
2863 iwl_cancel_deferred_work(priv);
2866 #define HW_READY_TIMEOUT (50)
2868 static int iwl_set_hw_ready(struct iwl_priv *priv)
2872 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2873 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2875 /* See if we got it */
2876 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2877 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2878 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2880 if (ret != -ETIMEDOUT)
2881 priv->hw_ready = true;
2883 priv->hw_ready = false;
2885 IWL_DEBUG_INFO(priv, "hardware %s\n",
2886 (priv->hw_ready == 1) ? "ready" : "not ready");
2890 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2894 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2896 ret = iwl_set_hw_ready(priv);
2900 /* If HW is not ready, prepare the conditions to check again */
2901 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2902 CSR_HW_IF_CONFIG_REG_PREPARE);
2904 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2905 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2906 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2908 /* HW should be ready by now, check again. */
2909 if (ret != -ETIMEDOUT)
2910 iwl_set_hw_ready(priv);
2915 #define MAX_HW_RESTARTS 5
2917 static int __iwl_up(struct iwl_priv *priv)
2919 struct iwl_rxon_context *ctx;
2923 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2924 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2928 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2929 IWL_ERR(priv, "ucode not available for device bringup\n");
2933 for_each_context(priv, ctx) {
2934 ret = iwlagn_alloc_bcast_station(priv, ctx);
2936 iwl_dealloc_bcast_stations(priv);
2941 iwl_prepare_card_hw(priv);
2943 if (!priv->hw_ready) {
2944 IWL_WARN(priv, "Exit HW not ready\n");
2948 /* If platform's RF_KILL switch is NOT set to KILL */
2949 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2950 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2952 set_bit(STATUS_RF_KILL_HW, &priv->status);
2954 if (iwl_is_rfkill(priv)) {
2955 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2957 iwl_enable_interrupts(priv);
2958 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2962 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2964 /* must be initialised before iwl_hw_nic_init */
2965 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2966 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2968 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2970 ret = iwlagn_hw_nic_init(priv);
2972 IWL_ERR(priv, "Unable to init nic\n");
2976 /* make sure rfkill handshake bits are cleared */
2977 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2978 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2979 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2981 /* clear (again), then enable host interrupts */
2982 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2983 iwl_enable_interrupts(priv);
2985 /* really make sure rfkill handshake bits are cleared */
2986 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2987 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2989 /* Copy original ucode data image from disk into backup cache.
2990 * This will be used to initialize the on-board processor's
2991 * data SRAM for a clean start when the runtime program first loads. */
2992 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2993 priv->ucode_data.len);
2995 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2997 /* load bootstrap state machine,
2998 * load bootstrap program into processor's memory,
2999 * prepare to load the "initialize" uCode */
3000 ret = priv->cfg->ops->lib->load_ucode(priv);
3003 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3008 /* start card; "initialize" will load runtime ucode */
3009 iwl_nic_start(priv);
3011 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3016 set_bit(STATUS_EXIT_PENDING, &priv->status);
3018 clear_bit(STATUS_EXIT_PENDING, &priv->status);
3020 /* tried to restart and config the device for as long as our
3021 * patience could withstand */
3022 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3027 /*****************************************************************************
3029 * Workqueue callbacks
3031 *****************************************************************************/
3033 static void iwl_bg_init_alive_start(struct work_struct *data)
3035 struct iwl_priv *priv =
3036 container_of(data, struct iwl_priv, init_alive_start.work);
3038 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3041 mutex_lock(&priv->mutex);
3042 priv->cfg->ops->lib->init_alive_start(priv);
3043 mutex_unlock(&priv->mutex);
3046 static void iwl_bg_alive_start(struct work_struct *data)
3048 struct iwl_priv *priv =
3049 container_of(data, struct iwl_priv, alive_start.work);
3051 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3054 /* enable dram interrupt */
3055 if (priv->cfg->ops->lib->isr_ops.reset)
3056 priv->cfg->ops->lib->isr_ops.reset(priv);
3058 mutex_lock(&priv->mutex);
3059 iwl_alive_start(priv);
3060 mutex_unlock(&priv->mutex);
3063 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3065 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3066 run_time_calib_work);
3068 mutex_lock(&priv->mutex);
3070 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3071 test_bit(STATUS_SCANNING, &priv->status)) {
3072 mutex_unlock(&priv->mutex);
3076 if (priv->start_calib) {
3077 if (iwl_bt_statistics(priv)) {
3078 iwl_chain_noise_calibration(priv,
3079 (void *)&priv->_agn.statistics_bt);
3080 iwl_sensitivity_calibration(priv,
3081 (void *)&priv->_agn.statistics_bt);
3083 iwl_chain_noise_calibration(priv,
3084 (void *)&priv->_agn.statistics);
3085 iwl_sensitivity_calibration(priv,
3086 (void *)&priv->_agn.statistics);
3090 mutex_unlock(&priv->mutex);
3093 static void iwl_bg_restart(struct work_struct *data)
3095 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3097 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3100 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3101 struct iwl_rxon_context *ctx;
3102 bool bt_sco, bt_full_concurrent;
3103 u8 bt_ci_compliance;
3107 mutex_lock(&priv->mutex);
3108 for_each_context(priv, ctx)
3113 * __iwl_down() will clear the BT status variables,
3114 * which is correct, but when we restart we really
3115 * want to keep them so restore them afterwards.
3117 * The restart process will later pick them up and
3118 * re-configure the hw when we reconfigure the BT
3121 bt_sco = priv->bt_sco_active;
3122 bt_full_concurrent = priv->bt_full_concurrent;
3123 bt_ci_compliance = priv->bt_ci_compliance;
3124 bt_load = priv->bt_traffic_load;
3125 bt_status = priv->bt_status;
3129 priv->bt_sco_active = bt_sco;
3130 priv->bt_full_concurrent = bt_full_concurrent;
3131 priv->bt_ci_compliance = bt_ci_compliance;
3132 priv->bt_traffic_load = bt_load;
3133 priv->bt_status = bt_status;
3135 mutex_unlock(&priv->mutex);
3136 iwl_cancel_deferred_work(priv);
3137 ieee80211_restart_hw(priv->hw);
3141 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3144 mutex_lock(&priv->mutex);
3146 mutex_unlock(&priv->mutex);
3150 static void iwl_bg_rx_replenish(struct work_struct *data)
3152 struct iwl_priv *priv =
3153 container_of(data, struct iwl_priv, rx_replenish);
3155 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3158 mutex_lock(&priv->mutex);
3159 iwlagn_rx_replenish(priv);
3160 mutex_unlock(&priv->mutex);
3163 /*****************************************************************************
3165 * mac80211 entry point functions
3167 *****************************************************************************/
3169 #define UCODE_READY_TIMEOUT (4 * HZ)
3172 * Not a mac80211 entry point function, but it fits in with all the
3173 * other mac80211 functions grouped here.
3175 static int iwl_mac_setup_register(struct iwl_priv *priv,
3176 struct iwlagn_ucode_capabilities *capa)
3179 struct ieee80211_hw *hw = priv->hw;
3180 struct iwl_rxon_context *ctx;
3182 hw->rate_control_algorithm = "iwl-agn-rs";
3184 /* Tell mac80211 our characteristics */
3185 hw->flags = IEEE80211_HW_SIGNAL_DBM |
3186 IEEE80211_HW_AMPDU_AGGREGATION |
3187 IEEE80211_HW_NEED_DTIM_PERIOD |
3188 IEEE80211_HW_SPECTRUM_MGMT |
3189 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3191 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3193 if (!priv->cfg->base_params->broken_powersave)
3194 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3195 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3197 if (priv->cfg->sku & IWL_SKU_N)
3198 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3199 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3201 hw->sta_data_size = sizeof(struct iwl_station_priv);
3202 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3204 for_each_context(priv, ctx) {
3205 hw->wiphy->interface_modes |= ctx->interface_modes;
3206 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3209 hw->wiphy->max_remain_on_channel_duration = 1000;
3211 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3212 WIPHY_FLAG_DISABLE_BEACON_HINTS |
3213 WIPHY_FLAG_IBSS_RSN;
3216 * For now, disable PS by default because it affects
3217 * RX performance significantly.
3219 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3221 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3222 /* we create the 802.11 header and a zero-length SSID element */
3223 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3225 /* Default value; 4 EDCA QOS priorities */
3228 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3230 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3231 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3232 &priv->bands[IEEE80211_BAND_2GHZ];
3233 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3234 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3235 &priv->bands[IEEE80211_BAND_5GHZ];
3237 iwl_leds_init(priv);
3239 ret = ieee80211_register_hw(priv->hw);
3241 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3244 priv->mac80211_registered = 1;
3250 int iwlagn_mac_start(struct ieee80211_hw *hw)
3252 struct iwl_priv *priv = hw->priv;
3255 IWL_DEBUG_MAC80211(priv, "enter\n");
3257 /* we should be verifying the device is ready to be opened */
3258 mutex_lock(&priv->mutex);
3259 ret = __iwl_up(priv);
3260 mutex_unlock(&priv->mutex);
3265 if (iwl_is_rfkill(priv))
3268 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3270 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3271 * mac80211 will not be run successfully. */
3272 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3273 test_bit(STATUS_READY, &priv->status),
3274 UCODE_READY_TIMEOUT);
3276 if (!test_bit(STATUS_READY, &priv->status)) {
3277 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3278 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3283 iwlagn_led_enable(priv);
3287 IWL_DEBUG_MAC80211(priv, "leave\n");
3291 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3293 struct iwl_priv *priv = hw->priv;
3295 IWL_DEBUG_MAC80211(priv, "enter\n");
3304 flush_workqueue(priv->workqueue);
3306 /* User space software may expect getting rfkill changes
3307 * even if interface is down */
3308 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3309 iwl_enable_rfkill_int(priv);
3311 IWL_DEBUG_MAC80211(priv, "leave\n");
3314 int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3316 struct iwl_priv *priv = hw->priv;
3318 IWL_DEBUG_MACDUMP(priv, "enter\n");
3320 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3321 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3323 if (iwlagn_tx_skb(priv, skb))
3324 dev_kfree_skb_any(skb);
3326 IWL_DEBUG_MACDUMP(priv, "leave\n");
3327 return NETDEV_TX_OK;
3330 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3331 struct ieee80211_vif *vif,
3332 struct ieee80211_key_conf *keyconf,
3333 struct ieee80211_sta *sta,
3334 u32 iv32, u16 *phase1key)
3336 struct iwl_priv *priv = hw->priv;
3337 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3339 IWL_DEBUG_MAC80211(priv, "enter\n");
3341 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3344 IWL_DEBUG_MAC80211(priv, "leave\n");
3347 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3348 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3349 struct ieee80211_key_conf *key)
3351 struct iwl_priv *priv = hw->priv;
3352 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3353 struct iwl_rxon_context *ctx = vif_priv->ctx;
3356 bool is_default_wep_key = false;
3358 IWL_DEBUG_MAC80211(priv, "enter\n");
3360 if (priv->cfg->mod_params->sw_crypto) {
3361 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3366 * To support IBSS RSN, don't program group keys in IBSS, the
3367 * hardware will then not attempt to decrypt the frames.
3369 if (vif->type == NL80211_IFTYPE_ADHOC &&
3370 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3373 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3374 if (sta_id == IWL_INVALID_STATION)
3377 mutex_lock(&priv->mutex);
3378 iwl_scan_cancel_timeout(priv, 100);
3381 * If we are getting WEP group key and we didn't receive any key mapping
3382 * so far, we are in legacy wep mode (group key only), otherwise we are
3384 * In legacy wep mode, we use another host command to the uCode.
3386 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3387 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3390 is_default_wep_key = !ctx->key_mapping_keys;
3392 is_default_wep_key =
3393 (key->hw_key_idx == HW_KEY_DEFAULT);
3398 if (is_default_wep_key)
3399 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3401 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3404 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3407 if (is_default_wep_key)
3408 ret = iwl_remove_default_wep_key(priv, ctx, key);
3410 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3412 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3418 mutex_unlock(&priv->mutex);
3419 IWL_DEBUG_MAC80211(priv, "leave\n");
3424 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3425 struct ieee80211_vif *vif,
3426 enum ieee80211_ampdu_mlme_action action,
3427 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3430 struct iwl_priv *priv = hw->priv;
3433 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3436 if (!(priv->cfg->sku & IWL_SKU_N))
3439 mutex_lock(&priv->mutex);
3442 case IEEE80211_AMPDU_RX_START:
3443 IWL_DEBUG_HT(priv, "start Rx\n");
3444 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3446 case IEEE80211_AMPDU_RX_STOP:
3447 IWL_DEBUG_HT(priv, "stop Rx\n");
3448 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3449 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3452 case IEEE80211_AMPDU_TX_START:
3453 IWL_DEBUG_HT(priv, "start Tx\n");
3454 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3456 priv->_agn.agg_tids_count++;
3457 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3458 priv->_agn.agg_tids_count);
3461 case IEEE80211_AMPDU_TX_STOP:
3462 IWL_DEBUG_HT(priv, "stop Tx\n");
3463 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3464 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3465 priv->_agn.agg_tids_count--;
3466 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3467 priv->_agn.agg_tids_count);
3469 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3471 if (priv->cfg->ht_params &&
3472 priv->cfg->ht_params->use_rts_for_aggregation) {
3473 struct iwl_station_priv *sta_priv =
3474 (void *) sta->drv_priv;
3476 * switch off RTS/CTS if it was previously enabled
3479 sta_priv->lq_sta.lq.general_params.flags &=
3480 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3481 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3482 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3485 case IEEE80211_AMPDU_TX_OPERATIONAL:
3486 if (priv->cfg->ht_params &&
3487 priv->cfg->ht_params->use_rts_for_aggregation) {
3488 struct iwl_station_priv *sta_priv =
3489 (void *) sta->drv_priv;
3492 * switch to RTS/CTS if it is the prefer protection
3493 * method for HT traffic
3496 sta_priv->lq_sta.lq.general_params.flags |=
3497 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3498 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3499 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3504 mutex_unlock(&priv->mutex);
3509 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3510 struct ieee80211_vif *vif,
3511 struct ieee80211_sta *sta)
3513 struct iwl_priv *priv = hw->priv;
3514 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3515 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3516 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3520 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3522 mutex_lock(&priv->mutex);
3523 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3525 sta_priv->common.sta_id = IWL_INVALID_STATION;
3527 atomic_set(&sta_priv->pending_frames, 0);
3528 if (vif->type == NL80211_IFTYPE_AP)
3529 sta_priv->client = true;
3531 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3532 is_ap, sta, &sta_id);
3534 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3536 /* Should we return success if return code is EEXIST ? */
3537 mutex_unlock(&priv->mutex);
3541 sta_priv->common.sta_id = sta_id;
3543 /* Initialize rate scaling */
3544 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3546 iwl_rs_rate_init(priv, sta, sta_id);
3547 mutex_unlock(&priv->mutex);
3552 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3553 struct ieee80211_channel_switch *ch_switch)
3555 struct iwl_priv *priv = hw->priv;
3556 const struct iwl_channel_info *ch_info;
3557 struct ieee80211_conf *conf = &hw->conf;
3558 struct ieee80211_channel *channel = ch_switch->channel;
3559 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3562 * When we add support for multiple interfaces, we need to
3563 * revisit this. The channel switch command in the device
3564 * only affects the BSS context, but what does that really
3565 * mean? And what if we get a CSA on the second interface?
3566 * This needs a lot of work.
3568 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3570 unsigned long flags = 0;
3572 IWL_DEBUG_MAC80211(priv, "enter\n");
3574 if (iwl_is_rfkill(priv))
3577 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3578 test_bit(STATUS_SCANNING, &priv->status))
3581 if (!iwl_is_associated_ctx(ctx))
3584 /* channel switch in progress */
3585 if (priv->switch_rxon.switch_in_progress == true)
3588 mutex_lock(&priv->mutex);
3589 if (priv->cfg->ops->lib->set_channel_switch) {
3591 ch = channel->hw_value;
3592 if (le16_to_cpu(ctx->active.channel) != ch) {
3593 ch_info = iwl_get_channel_info(priv,
3596 if (!is_channel_valid(ch_info)) {
3597 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3600 spin_lock_irqsave(&priv->lock, flags);
3602 priv->current_ht_config.smps = conf->smps_mode;
3604 /* Configure HT40 channels */
3605 ctx->ht.enabled = conf_is_ht(conf);
3606 if (ctx->ht.enabled) {
3607 if (conf_is_ht40_minus(conf)) {
3608 ctx->ht.extension_chan_offset =
3609 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3610 ctx->ht.is_40mhz = true;
3611 } else if (conf_is_ht40_plus(conf)) {
3612 ctx->ht.extension_chan_offset =
3613 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3614 ctx->ht.is_40mhz = true;
3616 ctx->ht.extension_chan_offset =
3617 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3618 ctx->ht.is_40mhz = false;
3621 ctx->ht.is_40mhz = false;
3623 if ((le16_to_cpu(ctx->staging.channel) != ch))
3624 ctx->staging.flags = 0;
3626 iwl_set_rxon_channel(priv, channel, ctx);
3627 iwl_set_rxon_ht(priv, ht_conf);
3628 iwl_set_flags_for_band(priv, ctx, channel->band,
3630 spin_unlock_irqrestore(&priv->lock, flags);
3634 * at this point, staging_rxon has the
3635 * configuration for channel switch
3637 if (priv->cfg->ops->lib->set_channel_switch(priv,
3639 priv->switch_rxon.switch_in_progress = false;
3643 mutex_unlock(&priv->mutex);
3645 if (!priv->switch_rxon.switch_in_progress)
3646 ieee80211_chswitch_done(ctx->vif, false);
3647 IWL_DEBUG_MAC80211(priv, "leave\n");
3650 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3651 unsigned int changed_flags,
3652 unsigned int *total_flags,
3655 struct iwl_priv *priv = hw->priv;
3656 __le32 filter_or = 0, filter_nand = 0;
3657 struct iwl_rxon_context *ctx;
3659 #define CHK(test, flag) do { \
3660 if (*total_flags & (test)) \
3661 filter_or |= (flag); \
3663 filter_nand |= (flag); \
3666 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3667 changed_flags, *total_flags);
3669 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3670 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3671 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3672 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3676 mutex_lock(&priv->mutex);
3678 for_each_context(priv, ctx) {
3679 ctx->staging.filter_flags &= ~filter_nand;
3680 ctx->staging.filter_flags |= filter_or;
3683 * Not committing directly because hardware can perform a scan,
3684 * but we'll eventually commit the filter flags change anyway.
3688 mutex_unlock(&priv->mutex);
3691 * Receiving all multicast frames is always enabled by the
3692 * default flags setup in iwl_connection_init_rx_config()
3693 * since we currently do not support programming multicast
3694 * filters into the device.
3696 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3697 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3700 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3702 struct iwl_priv *priv = hw->priv;
3704 mutex_lock(&priv->mutex);
3705 IWL_DEBUG_MAC80211(priv, "enter\n");
3707 /* do not support "flush" */
3708 if (!priv->cfg->ops->lib->txfifo_flush)
3711 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3712 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3715 if (iwl_is_rfkill(priv)) {
3716 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3721 * mac80211 will not push any more frames for transmit
3722 * until the flush is completed
3725 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3726 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3727 IWL_ERR(priv, "flush request fail\n");
3731 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3732 iwlagn_wait_tx_queue_empty(priv);
3734 mutex_unlock(&priv->mutex);
3735 IWL_DEBUG_MAC80211(priv, "leave\n");
3738 static void iwlagn_disable_roc(struct iwl_priv *priv)
3740 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3741 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3743 lockdep_assert_held(&priv->mutex);
3745 if (!ctx->is_active)
3748 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3749 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3750 iwl_set_rxon_channel(priv, chan, ctx);
3751 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3753 priv->_agn.hw_roc_channel = NULL;
3755 iwlagn_commit_rxon(priv, ctx);
3757 ctx->is_active = false;
3760 static void iwlagn_bg_roc_done(struct work_struct *work)
3762 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3763 _agn.hw_roc_work.work);
3765 mutex_lock(&priv->mutex);
3766 ieee80211_remain_on_channel_expired(priv->hw);
3767 iwlagn_disable_roc(priv);
3768 mutex_unlock(&priv->mutex);
3771 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3772 struct ieee80211_channel *channel,
3773 enum nl80211_channel_type channel_type,
3776 struct iwl_priv *priv = hw->priv;
3779 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3782 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3783 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3786 mutex_lock(&priv->mutex);
3788 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3789 test_bit(STATUS_SCAN_HW, &priv->status)) {
3794 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3795 priv->_agn.hw_roc_channel = channel;
3796 priv->_agn.hw_roc_chantype = channel_type;
3797 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3798 iwlagn_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3799 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3800 msecs_to_jiffies(duration + 20));
3802 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3803 ieee80211_ready_on_channel(priv->hw);
3806 mutex_unlock(&priv->mutex);
3811 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3813 struct iwl_priv *priv = hw->priv;
3815 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3818 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3820 mutex_lock(&priv->mutex);
3821 iwlagn_disable_roc(priv);
3822 mutex_unlock(&priv->mutex);
3827 /*****************************************************************************
3829 * driver setup and teardown
3831 *****************************************************************************/
3833 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3835 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3837 init_waitqueue_head(&priv->wait_command_queue);
3839 INIT_WORK(&priv->restart, iwl_bg_restart);
3840 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3841 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3842 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3843 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3844 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3845 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3846 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3847 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3848 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3850 iwl_setup_scan_deferred_work(priv);
3852 if (priv->cfg->ops->lib->setup_deferred_work)
3853 priv->cfg->ops->lib->setup_deferred_work(priv);
3855 init_timer(&priv->statistics_periodic);
3856 priv->statistics_periodic.data = (unsigned long)priv;
3857 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3859 init_timer(&priv->ucode_trace);
3860 priv->ucode_trace.data = (unsigned long)priv;
3861 priv->ucode_trace.function = iwl_bg_ucode_trace;
3863 init_timer(&priv->watchdog);
3864 priv->watchdog.data = (unsigned long)priv;
3865 priv->watchdog.function = iwl_bg_watchdog;
3867 if (!priv->cfg->base_params->use_isr_legacy)
3868 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3869 iwl_irq_tasklet, (unsigned long)priv);
3871 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3872 iwl_irq_tasklet_legacy, (unsigned long)priv);
3875 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3877 if (priv->cfg->ops->lib->cancel_deferred_work)
3878 priv->cfg->ops->lib->cancel_deferred_work(priv);
3880 cancel_delayed_work_sync(&priv->init_alive_start);
3881 cancel_delayed_work(&priv->alive_start);
3882 cancel_work_sync(&priv->run_time_calib_work);
3883 cancel_work_sync(&priv->beacon_update);
3885 iwl_cancel_scan_deferred_work(priv);
3887 cancel_work_sync(&priv->bt_full_concurrency);
3888 cancel_work_sync(&priv->bt_runtime_config);
3890 del_timer_sync(&priv->statistics_periodic);
3891 del_timer_sync(&priv->ucode_trace);
3894 static void iwl_init_hw_rates(struct iwl_priv *priv,
3895 struct ieee80211_rate *rates)
3899 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3900 rates[i].bitrate = iwl_rates[i].ieee * 5;
3901 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3902 rates[i].hw_value_short = i;
3904 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3906 * If CCK != 1M then set short preamble rate flag.
3909 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3910 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3915 static int iwl_init_drv(struct iwl_priv *priv)
3919 spin_lock_init(&priv->sta_lock);
3920 spin_lock_init(&priv->hcmd_lock);
3922 INIT_LIST_HEAD(&priv->free_frames);
3924 mutex_init(&priv->mutex);
3925 mutex_init(&priv->sync_cmd_mutex);
3927 priv->ieee_channels = NULL;
3928 priv->ieee_rates = NULL;
3929 priv->band = IEEE80211_BAND_2GHZ;
3931 priv->iw_mode = NL80211_IFTYPE_STATION;
3932 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3933 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3934 priv->_agn.agg_tids_count = 0;
3936 /* initialize force reset */
3937 priv->force_reset[IWL_RF_RESET].reset_duration =
3938 IWL_DELAY_NEXT_FORCE_RF_RESET;
3939 priv->force_reset[IWL_FW_RESET].reset_duration =
3940 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3942 /* Choose which receivers/antennas to use */
3943 if (priv->cfg->ops->hcmd->set_rxon_chain)
3944 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3945 &priv->contexts[IWL_RXON_CTX_BSS]);
3947 iwl_init_scan_params(priv);
3950 if (priv->cfg->bt_params &&
3951 priv->cfg->bt_params->advanced_bt_coexist) {
3952 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3953 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3954 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3955 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3956 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3957 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3960 /* Set the tx_power_user_lmt to the lowest power level
3961 * this value will get overwritten by channel max power avg
3963 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3964 priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3966 ret = iwl_init_channel_map(priv);
3968 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3972 ret = iwlcore_init_geos(priv);
3974 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3975 goto err_free_channel_map;
3977 iwl_init_hw_rates(priv, priv->ieee_rates);
3981 err_free_channel_map:
3982 iwl_free_channel_map(priv);
3987 static void iwl_uninit_drv(struct iwl_priv *priv)
3989 iwl_calib_free_results(priv);
3990 iwlcore_free_geos(priv);
3991 iwl_free_channel_map(priv);
3992 kfree(priv->scan_cmd);
3995 #ifdef CONFIG_IWL5000
3996 struct ieee80211_ops iwlagn_hw_ops = {
3997 .tx = iwlagn_mac_tx,
3998 .start = iwlagn_mac_start,
3999 .stop = iwlagn_mac_stop,
4000 .add_interface = iwl_mac_add_interface,
4001 .remove_interface = iwl_mac_remove_interface,
4002 .change_interface = iwl_mac_change_interface,
4003 .config = iwlagn_mac_config,
4004 .configure_filter = iwlagn_configure_filter,
4005 .set_key = iwlagn_mac_set_key,
4006 .update_tkip_key = iwlagn_mac_update_tkip_key,
4007 .conf_tx = iwl_mac_conf_tx,
4008 .bss_info_changed = iwlagn_bss_info_changed,
4009 .ampdu_action = iwlagn_mac_ampdu_action,
4010 .hw_scan = iwl_mac_hw_scan,
4011 .sta_notify = iwlagn_mac_sta_notify,
4012 .sta_add = iwlagn_mac_sta_add,
4013 .sta_remove = iwl_mac_sta_remove,
4014 .channel_switch = iwlagn_mac_channel_switch,
4015 .flush = iwlagn_mac_flush,
4016 .tx_last_beacon = iwl_mac_tx_last_beacon,
4017 .remain_on_channel = iwl_mac_remain_on_channel,
4018 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
4022 static void iwl_hw_detect(struct iwl_priv *priv)
4024 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4025 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4026 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4027 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4030 static int iwl_set_hw_params(struct iwl_priv *priv)
4032 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4033 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4034 if (priv->cfg->mod_params->amsdu_size_8K)
4035 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4037 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4039 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4041 if (priv->cfg->mod_params->disable_11n)
4042 priv->cfg->sku &= ~IWL_SKU_N;
4044 /* Device-specific setup */
4045 return priv->cfg->ops->lib->set_hw_params(priv);
4048 static const u8 iwlagn_bss_ac_to_fifo[] = {
4055 static const u8 iwlagn_bss_ac_to_queue[] = {
4059 static const u8 iwlagn_pan_ac_to_fifo[] = {
4060 IWL_TX_FIFO_VO_IPAN,
4061 IWL_TX_FIFO_VI_IPAN,
4062 IWL_TX_FIFO_BE_IPAN,
4063 IWL_TX_FIFO_BK_IPAN,
4066 static const u8 iwlagn_pan_ac_to_queue[] = {
4070 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4073 struct iwl_priv *priv;
4074 struct ieee80211_hw *hw;
4075 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4076 unsigned long flags;
4077 u16 pci_cmd, num_mac;
4079 /************************
4080 * 1. Allocating HW data
4081 ************************/
4083 /* Disabling hardware scan means that mac80211 will perform scans
4084 * "the hard way", rather than using device's scan. */
4085 if (cfg->mod_params->disable_hw_scan) {
4086 dev_printk(KERN_DEBUG, &(pdev->dev),
4087 "sw scan support is deprecated\n");
4088 #ifdef CONFIG_IWL5000
4089 iwlagn_hw_ops.hw_scan = NULL;
4091 #ifdef CONFIG_IWL4965
4092 iwl4965_hw_ops.hw_scan = NULL;
4096 hw = iwl_alloc_all(cfg);
4102 /* At this point both hw and priv are allocated. */
4105 * The default context is always valid,
4106 * more may be discovered when firmware
4109 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4111 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4112 priv->contexts[i].ctxid = i;
4114 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4115 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4116 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4117 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4118 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4119 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4120 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4121 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4122 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4123 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4124 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4125 BIT(NL80211_IFTYPE_ADHOC);
4126 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4127 BIT(NL80211_IFTYPE_STATION);
4128 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4129 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4130 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4131 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4133 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4134 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4135 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4136 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4137 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4138 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4139 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4140 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4141 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4142 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4143 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4144 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4145 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4146 #ifdef CONFIG_IWL_P2P
4147 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
4148 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
4150 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4151 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4152 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4154 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4156 SET_IEEE80211_DEV(hw, &pdev->dev);
4158 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4160 priv->pci_dev = pdev;
4161 priv->inta_mask = CSR_INI_SET_MASK;
4163 /* is antenna coupling more than 35dB ? */
4164 priv->bt_ant_couple_ok =
4165 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4168 /* enable/disable bt channel inhibition */
4169 priv->bt_ch_announce = iwlagn_bt_ch_announce;
4170 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4171 (priv->bt_ch_announce) ? "On" : "Off");
4173 if (iwl_alloc_traffic_mem(priv))
4174 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4176 /**************************
4177 * 2. Initializing PCI bus
4178 **************************/
4179 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4180 PCIE_LINK_STATE_CLKPM);
4182 if (pci_enable_device(pdev)) {
4184 goto out_ieee80211_free_hw;
4187 pci_set_master(pdev);
4189 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4191 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4193 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4195 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4196 /* both attempts failed: */
4198 IWL_WARN(priv, "No suitable DMA available.\n");
4199 goto out_pci_disable_device;
4203 err = pci_request_regions(pdev, DRV_NAME);
4205 goto out_pci_disable_device;
4207 pci_set_drvdata(pdev, priv);
4210 /***********************
4211 * 3. Read REV register
4212 ***********************/
4213 priv->hw_base = pci_iomap(pdev, 0, 0);
4214 if (!priv->hw_base) {
4216 goto out_pci_release_regions;
4219 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4220 (unsigned long long) pci_resource_len(pdev, 0));
4221 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4223 /* these spin locks will be used in apm_ops.init and EEPROM access
4224 * we should init now
4226 spin_lock_init(&priv->reg_lock);
4227 spin_lock_init(&priv->lock);
4230 * stop and reset the on-board processor just in case it is in a
4231 * strange state ... like being left stranded by a primary kernel
4232 * and this is now the kdump kernel trying to start up
4234 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4236 iwl_hw_detect(priv);
4237 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4238 priv->cfg->name, priv->hw_rev);
4240 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4241 * PCI Tx retries from interfering with C3 CPU state */
4242 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4244 iwl_prepare_card_hw(priv);
4245 if (!priv->hw_ready) {
4246 IWL_WARN(priv, "Failed, HW not ready\n");
4253 /* Read the EEPROM */
4254 err = iwl_eeprom_init(priv);
4256 IWL_ERR(priv, "Unable to init EEPROM\n");
4259 err = iwl_eeprom_check_version(priv);
4261 goto out_free_eeprom;
4263 err = iwl_eeprom_check_sku(priv);
4265 goto out_free_eeprom;
4267 /* extract MAC Address */
4268 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4269 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4270 priv->hw->wiphy->addresses = priv->addresses;
4271 priv->hw->wiphy->n_addresses = 1;
4272 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4274 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4276 priv->addresses[1].addr[5]++;
4277 priv->hw->wiphy->n_addresses++;
4280 /************************
4281 * 5. Setup HW constants
4282 ************************/
4283 if (iwl_set_hw_params(priv)) {
4284 IWL_ERR(priv, "failed to set hw parameters\n");
4285 goto out_free_eeprom;
4288 /*******************
4290 *******************/
4292 err = iwl_init_drv(priv);
4294 goto out_free_eeprom;
4295 /* At this point both hw and priv are initialized. */
4297 /********************
4299 ********************/
4300 spin_lock_irqsave(&priv->lock, flags);
4301 iwl_disable_interrupts(priv);
4302 spin_unlock_irqrestore(&priv->lock, flags);
4304 pci_enable_msi(priv->pci_dev);
4306 if (priv->cfg->ops->lib->isr_ops.alloc)
4307 priv->cfg->ops->lib->isr_ops.alloc(priv);
4309 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4310 IRQF_SHARED, DRV_NAME, priv);
4312 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4313 goto out_disable_msi;
4316 iwl_setup_deferred_work(priv);
4317 iwl_setup_rx_handlers(priv);
4319 /*********************************************
4320 * 8. Enable interrupts and read RFKILL state
4321 *********************************************/
4323 /* enable rfkill interrupt: hw bug w/a */
4324 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4325 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4326 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4327 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4330 iwl_enable_rfkill_int(priv);
4332 /* If platform's RF_KILL switch is NOT set to KILL */
4333 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4334 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4336 set_bit(STATUS_RF_KILL_HW, &priv->status);
4338 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4339 test_bit(STATUS_RF_KILL_HW, &priv->status));
4341 iwl_power_initialize(priv);
4342 iwl_tt_initialize(priv);
4344 init_completion(&priv->_agn.firmware_loading_complete);
4346 err = iwl_request_firmware(priv, true);
4348 goto out_destroy_workqueue;
4352 out_destroy_workqueue:
4353 destroy_workqueue(priv->workqueue);
4354 priv->workqueue = NULL;
4355 free_irq(priv->pci_dev->irq, priv);
4356 if (priv->cfg->ops->lib->isr_ops.free)
4357 priv->cfg->ops->lib->isr_ops.free(priv);
4359 pci_disable_msi(priv->pci_dev);
4360 iwl_uninit_drv(priv);
4362 iwl_eeprom_free(priv);
4364 pci_iounmap(pdev, priv->hw_base);
4365 out_pci_release_regions:
4366 pci_set_drvdata(pdev, NULL);
4367 pci_release_regions(pdev);
4368 out_pci_disable_device:
4369 pci_disable_device(pdev);
4370 out_ieee80211_free_hw:
4371 iwl_free_traffic_mem(priv);
4372 ieee80211_free_hw(priv->hw);
4377 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4379 struct iwl_priv *priv = pci_get_drvdata(pdev);
4380 unsigned long flags;
4385 wait_for_completion(&priv->_agn.firmware_loading_complete);
4387 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4389 iwl_dbgfs_unregister(priv);
4390 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4392 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4393 * to be called and iwl_down since we are removing the device
4394 * we need to set STATUS_EXIT_PENDING bit.
4396 set_bit(STATUS_EXIT_PENDING, &priv->status);
4398 iwl_leds_exit(priv);
4400 if (priv->mac80211_registered) {
4401 ieee80211_unregister_hw(priv->hw);
4402 priv->mac80211_registered = 0;
4408 * Make sure device is reset to low power before unloading driver.
4409 * This may be redundant with iwl_down(), but there are paths to
4410 * run iwl_down() without calling apm_ops.stop(), and there are
4411 * paths to avoid running iwl_down() at all before leaving driver.
4412 * This (inexpensive) call *makes sure* device is reset.
4418 /* make sure we flush any pending irq or
4419 * tasklet for the driver
4421 spin_lock_irqsave(&priv->lock, flags);
4422 iwl_disable_interrupts(priv);
4423 spin_unlock_irqrestore(&priv->lock, flags);
4425 iwl_synchronize_irq(priv);
4427 iwl_dealloc_ucode_pci(priv);
4430 iwlagn_rx_queue_free(priv, &priv->rxq);
4431 iwlagn_hw_txq_ctx_free(priv);
4433 iwl_eeprom_free(priv);
4436 /*netif_stop_queue(dev); */
4437 flush_workqueue(priv->workqueue);
4439 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4440 * priv->workqueue... so we can't take down the workqueue
4442 destroy_workqueue(priv->workqueue);
4443 priv->workqueue = NULL;
4444 iwl_free_traffic_mem(priv);
4446 free_irq(priv->pci_dev->irq, priv);
4447 pci_disable_msi(priv->pci_dev);
4448 pci_iounmap(pdev, priv->hw_base);
4449 pci_release_regions(pdev);
4450 pci_disable_device(pdev);
4451 pci_set_drvdata(pdev, NULL);
4453 iwl_uninit_drv(priv);
4455 if (priv->cfg->ops->lib->isr_ops.free)
4456 priv->cfg->ops->lib->isr_ops.free(priv);
4458 dev_kfree_skb(priv->beacon_skb);
4460 ieee80211_free_hw(priv->hw);
4464 /*****************************************************************************
4466 * driver and module entry point
4468 *****************************************************************************/
4470 /* Hardware specific file defines the PCI IDs table for that hardware module */
4471 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4472 #ifdef CONFIG_IWL4965
4473 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4474 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4475 #endif /* CONFIG_IWL4965 */
4476 #ifdef CONFIG_IWL5000
4477 /* 5100 Series WiFi */
4478 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4479 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4480 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4481 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4482 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4483 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4484 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4485 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4486 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4487 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4488 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4489 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4490 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4491 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4492 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4493 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4494 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4495 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4496 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4497 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4498 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4499 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4500 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4501 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4503 /* 5300 Series WiFi */
4504 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4505 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4506 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4507 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4508 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4509 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4510 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4511 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4512 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4513 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4514 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4515 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4517 /* 5350 Series WiFi/WiMax */
4518 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4519 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4520 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4522 /* 5150 Series Wifi/WiMax */
4523 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4524 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4525 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4526 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4527 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4528 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4530 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4531 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4532 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4533 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4536 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4537 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4538 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4539 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4540 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4541 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4542 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4543 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4544 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4545 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4548 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4549 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4550 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4551 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4552 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4553 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4554 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4557 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4558 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4559 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4560 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4561 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4562 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4563 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4564 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4565 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4566 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4567 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4568 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4569 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4570 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4571 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4572 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4574 /* 6x50 WiFi/WiMax Series */
4575 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4576 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4577 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4578 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4579 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4580 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4582 /* 6150 WiFi/WiMax Series */
4583 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4584 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4585 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4586 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4587 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4588 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4590 /* 1000 Series WiFi */
4591 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4592 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4593 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4594 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4595 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4596 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4597 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4598 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4599 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4600 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4601 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4602 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4604 /* 100 Series WiFi */
4605 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4606 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4607 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4608 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4609 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4610 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4612 /* 130 Series WiFi */
4613 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4614 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4615 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4616 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4617 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4618 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4621 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4622 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4623 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4624 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4625 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4626 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4629 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4630 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4631 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4632 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4633 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4634 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4637 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4638 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4639 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4640 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4641 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4642 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4643 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4644 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4645 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4648 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4649 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4650 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4651 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4652 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4653 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4656 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4657 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4658 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4659 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4660 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4661 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4663 #endif /* CONFIG_IWL5000 */
4667 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4669 static struct pci_driver iwl_driver = {
4671 .id_table = iwl_hw_card_ids,
4672 .probe = iwl_pci_probe,
4673 .remove = __devexit_p(iwl_pci_remove),
4674 .driver.pm = IWL_PM_OPS,
4677 static int __init iwl_init(void)
4681 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4682 pr_info(DRV_COPYRIGHT "\n");
4684 ret = iwlagn_rate_control_register();
4686 pr_err("Unable to register rate control algorithm: %d\n", ret);
4690 ret = pci_register_driver(&iwl_driver);
4692 pr_err("Unable to initialize PCI module\n");
4693 goto error_register;
4699 iwlagn_rate_control_unregister();
4703 static void __exit iwl_exit(void)
4705 pci_unregister_driver(&iwl_driver);
4706 iwlagn_rate_control_unregister();
4709 module_exit(iwl_exit);
4710 module_init(iwl_init);
4712 #ifdef CONFIG_IWLWIFI_DEBUG
4713 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4714 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4715 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4716 MODULE_PARM_DESC(debug, "debug output mask");
4719 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4720 MODULE_PARM_DESC(swcrypto50,
4721 "using crypto in software (default 0 [hardware]) (deprecated)");
4722 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4723 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4724 module_param_named(queues_num50,
4725 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4726 MODULE_PARM_DESC(queues_num50,
4727 "number of hw queues in 50xx series (deprecated)");
4728 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4729 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4730 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4731 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4732 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4733 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4734 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4736 MODULE_PARM_DESC(amsdu_size_8K50,
4737 "enable 8K amsdu size in 50XX series (deprecated)");
4738 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4740 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4741 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4742 MODULE_PARM_DESC(fw_restart50,
4743 "restart firmware in case of error (deprecated)");
4744 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4745 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4747 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4748 MODULE_PARM_DESC(disable_hw_scan,
4749 "disable hardware scanning (default 0) (deprecated)");
4751 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4753 MODULE_PARM_DESC(ucode_alternative,
4754 "specify ucode alternative to use from ucode file");
4756 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4757 MODULE_PARM_DESC(antenna_coupling,
4758 "specify antenna coupling in dB (defualt: 0 dB)");
4760 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4761 MODULE_PARM_DESC(bt_ch_inhibition,
4762 "Disable BT channel inhibition (default: enable)");