1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
33 /*TODO: Remove include to iwl-core.h*/
36 #include "iwl-helpers.h"
37 #include "iwl-trans-pcie-int.h"
39 /******************************************************************************
43 ******************************************************************************/
46 * Rx theory of operation
48 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
49 * each of which point to Receive Buffers to be filled by the NIC. These get
50 * used not only for Rx frames, but for any command response or notification
51 * from the NIC. The driver and NIC manage the Rx buffers by means
52 * of indexes into the circular buffer.
55 * The host/firmware share two index registers for managing the Rx buffers.
57 * The READ index maps to the first position that the firmware may be writing
58 * to -- the driver can read up to (but not including) this position and get
60 * The READ index is managed by the firmware once the card is enabled.
62 * The WRITE index maps to the last position the driver has read from -- the
63 * position preceding WRITE is the last slot the firmware can place a packet.
65 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
68 * During initialization, the host sets up the READ queue position to the first
69 * INDEX position, and WRITE to the last (READ - 1 wrapped)
71 * When the firmware places a packet in a buffer, it will advance the READ index
72 * and fire the RX interrupt. The driver can then query the READ index and
73 * process as many packets as possible, moving the WRITE index forward as it
74 * resets the Rx queue buffers with new memory.
76 * The management in the driver is as follows:
77 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
78 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
79 * to replenish the iwl->rxq->rx_free.
80 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
81 * iwl->rxq is replenished and the READ INDEX is updated (updating the
82 * 'processed' and 'read' driver indexes as well)
83 * + A received packet is processed and handed to the kernel network stack,
84 * detached from the iwl->rxq. The driver 'processed' index is updated.
85 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
86 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
87 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
88 * were enough free buffers and RX_STALLED is set it is cleared.
93 * iwl_rx_queue_alloc() Allocates rx_free
94 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
95 * iwl_rx_queue_restock
96 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
97 * queue, updates firmware pointers, and updates
98 * the WRITE index. If insufficient rx_free buffers
99 * are available, schedules iwl_rx_replenish
101 * -- enable interrupts --
102 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
103 * READ INDEX, detaching the SKB from the pool.
104 * Moves the packet buffer from queue to rx_used.
105 * Calls iwl_rx_queue_restock to refill any empty
112 * iwl_rx_queue_space - Return number of free slots available in queue.
114 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
116 int s = q->read - q->write;
119 /* keep some buffer to not confuse full and empty queue */
127 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
129 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
130 struct iwl_rx_queue *q)
135 spin_lock_irqsave(&q->lock, flags);
137 if (q->need_update == 0)
140 if (hw_params(trans).shadow_reg_enable) {
141 /* shadow register enabled */
142 /* Device expects a multiple of 8 */
143 q->write_actual = (q->write & ~0x7);
144 iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual);
146 /* If power-saving is in use, make sure device is awake */
147 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
148 reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
150 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
151 IWL_DEBUG_INFO(trans,
152 "Rx queue requesting wakeup,"
153 " GP1 = 0x%x\n", reg);
154 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
155 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
159 q->write_actual = (q->write & ~0x7);
160 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
163 /* Else device is assumed to be awake */
165 /* Device expects a multiple of 8 */
166 q->write_actual = (q->write & ~0x7);
167 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
174 spin_unlock_irqrestore(&q->lock, flags);
178 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
180 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
182 return cpu_to_le32((u32)(dma_addr >> 8));
186 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
188 * If there are slots in the RX queue that need to be restocked,
189 * and we have free pre-allocated buffers, fill the ranks as much
190 * as we can, pulling from rx_free.
192 * This moves the 'write' index forward to catch up with 'processed', and
193 * also updates the memory address in the firmware to reference the new
196 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
198 struct iwl_trans_pcie *trans_pcie =
199 IWL_TRANS_GET_PCIE_TRANS(trans);
201 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
202 struct list_head *element;
203 struct iwl_rx_mem_buffer *rxb;
206 spin_lock_irqsave(&rxq->lock, flags);
207 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
208 /* The overwritten rxb must be a used one */
209 rxb = rxq->queue[rxq->write];
210 BUG_ON(rxb && rxb->page);
212 /* Get next free Rx buffer, remove from free list */
213 element = rxq->rx_free.next;
214 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
217 /* Point to Rx buffer via next RBD in circular buffer */
218 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
219 rxq->queue[rxq->write] = rxb;
220 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
223 spin_unlock_irqrestore(&rxq->lock, flags);
224 /* If the pre-allocated buffer pool is dropping low, schedule to
226 if (rxq->free_count <= RX_LOW_WATERMARK)
227 queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish);
230 /* If we've added more space for the firmware to place data, tell it.
231 * Increment device's write pointer in multiples of 8. */
232 if (rxq->write_actual != (rxq->write & ~0x7)) {
233 spin_lock_irqsave(&rxq->lock, flags);
234 rxq->need_update = 1;
235 spin_unlock_irqrestore(&rxq->lock, flags);
236 iwl_rx_queue_update_write_ptr(trans, rxq);
241 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
243 * When moving to rx_free an SKB is allocated for the slot.
245 * Also restock the Rx queue via iwl_rx_queue_restock.
246 * This is called as a scheduled work item (except for during initialization)
248 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
250 struct iwl_trans_pcie *trans_pcie =
251 IWL_TRANS_GET_PCIE_TRANS(trans);
253 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
254 struct list_head *element;
255 struct iwl_rx_mem_buffer *rxb;
258 gfp_t gfp_mask = priority;
261 spin_lock_irqsave(&rxq->lock, flags);
262 if (list_empty(&rxq->rx_used)) {
263 spin_unlock_irqrestore(&rxq->lock, flags);
266 spin_unlock_irqrestore(&rxq->lock, flags);
268 if (rxq->free_count > RX_LOW_WATERMARK)
269 gfp_mask |= __GFP_NOWARN;
271 if (hw_params(trans).rx_page_order > 0)
272 gfp_mask |= __GFP_COMP;
274 /* Alloc a new receive buffer */
275 page = alloc_pages(gfp_mask,
276 hw_params(trans).rx_page_order);
279 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
281 hw_params(trans).rx_page_order);
283 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
285 IWL_CRIT(trans, "Failed to alloc_pages with %s."
286 "Only %u free buffers remaining.\n",
287 priority == GFP_ATOMIC ?
288 "GFP_ATOMIC" : "GFP_KERNEL",
290 /* We don't reschedule replenish work here -- we will
291 * call the restock method and if it still needs
292 * more buffers it will schedule replenish */
296 spin_lock_irqsave(&rxq->lock, flags);
298 if (list_empty(&rxq->rx_used)) {
299 spin_unlock_irqrestore(&rxq->lock, flags);
300 __free_pages(page, hw_params(trans).rx_page_order);
303 element = rxq->rx_used.next;
304 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
307 spin_unlock_irqrestore(&rxq->lock, flags);
311 /* Get physical address of the RB */
312 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0,
313 PAGE_SIZE << hw_params(trans).rx_page_order,
315 /* dma address must be no more than 36 bits */
316 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
317 /* and also 256 byte aligned! */
318 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
320 spin_lock_irqsave(&rxq->lock, flags);
322 list_add_tail(&rxb->list, &rxq->rx_free);
325 spin_unlock_irqrestore(&rxq->lock, flags);
329 void iwlagn_rx_replenish(struct iwl_trans *trans)
333 iwlagn_rx_allocate(trans, GFP_KERNEL);
335 spin_lock_irqsave(&trans->shrd->lock, flags);
336 iwlagn_rx_queue_restock(trans);
337 spin_unlock_irqrestore(&trans->shrd->lock, flags);
340 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
342 iwlagn_rx_allocate(trans, GFP_ATOMIC);
344 iwlagn_rx_queue_restock(trans);
347 void iwl_bg_rx_replenish(struct work_struct *data)
349 struct iwl_trans_pcie *trans_pcie =
350 container_of(data, struct iwl_trans_pcie, rx_replenish);
351 struct iwl_trans *trans = trans_pcie->trans;
353 if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
356 mutex_lock(&trans->shrd->mutex);
357 iwlagn_rx_replenish(trans);
358 mutex_unlock(&trans->shrd->mutex);
362 * iwl_rx_handle - Main entry function for receiving responses from uCode
364 * Uses the priv->rx_handlers callback function array to invoke
365 * the appropriate handlers, including command responses,
366 * frame-received notifications, and other notifications.
368 static void iwl_rx_handle(struct iwl_trans *trans)
370 struct iwl_rx_mem_buffer *rxb;
371 struct iwl_rx_packet *pkt;
372 struct iwl_trans_pcie *trans_pcie =
373 IWL_TRANS_GET_PCIE_TRANS(trans);
374 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
375 struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
376 struct iwl_device_cmd *cmd;
383 int index, cmd_index;
385 /* uCode's read index (stored in shared DRAM) indicates the last Rx
386 * buffer that the driver may process (last buffer filled by ucode). */
387 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
390 /* Rx interrupt, but nothing sent from uCode */
392 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
394 /* calculate total frames need to be restock after handling RX */
395 total_empty = r - rxq->write_actual;
397 total_empty += RX_QUEUE_SIZE;
399 if (total_empty > (RX_QUEUE_SIZE / 2))
404 u16 txq_id, sequence;
408 /* If an RXB doesn't have a Rx queue slot associated with it,
409 * then a bug has been introduced in the queue refilling
410 * routines -- catch it here */
411 if (WARN_ON(rxb == NULL)) {
412 i = (i + 1) & RX_QUEUE_MASK;
416 rxq->queue[i] = NULL;
418 dma_unmap_page(bus(trans)->dev, rxb->page_dma,
419 PAGE_SIZE << hw_params(trans).rx_page_order,
423 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
424 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
426 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
427 len += sizeof(u32); /* account for status word */
428 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
430 /* Reclaim a command buffer only if this packet is a response
431 * to a (driver-originated) command.
432 * If the packet (e.g. Rx frame) originated from uCode,
433 * there is no command buffer to reclaim.
434 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
435 * but apparently a few don't get set; catch them here. */
436 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
437 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
438 (pkt->hdr.cmd != REPLY_RX) &&
439 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
440 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
441 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
442 (pkt->hdr.cmd != REPLY_TX);
444 sequence = le16_to_cpu(pkt->hdr.sequence);
445 index = SEQ_TO_INDEX(sequence);
446 cmd_index = get_cmd_index(&txq->q, index);
449 cmd = txq->cmd[cmd_index];
453 /* warn if this is cmd response / notification and the uCode
454 * didn't set the SEQ_RX_FRAME for a frame that is
456 WARN(txq_id == trans->shrd->cmd_queue && reclaim == false &&
457 (!(pkt->hdr.sequence & SEQ_RX_FRAME)),
458 "reclaim is false, SEQ_RX_FRAME unset: %s\n",
459 get_cmd_string(pkt->hdr.cmd));
461 err = iwl_rx_dispatch(priv(trans), rxb, cmd);
464 * XXX: After here, we should always check rxb->page
465 * against NULL before touching it or its virtual
466 * memory (pkt). Because some rx_handler might have
467 * already taken or freed the pages.
471 /* Invoke any callbacks, transfer the buffer to caller,
472 * and fire off the (possibly) blocking
473 * iwl_trans_send_cmd()
474 * as we reclaim the driver command queue */
476 iwl_tx_cmd_complete(trans, rxb, err);
478 IWL_WARN(trans, "Claim null rxb?\n");
481 /* Reuse the page if possible. For notification packets and
482 * SKBs that fail to Rx correctly, add them back into the
483 * rx_free list for reuse later. */
484 spin_lock_irqsave(&rxq->lock, flags);
485 if (rxb->page != NULL) {
486 rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page,
488 hw_params(trans).rx_page_order,
490 list_add_tail(&rxb->list, &rxq->rx_free);
493 list_add_tail(&rxb->list, &rxq->rx_used);
495 spin_unlock_irqrestore(&rxq->lock, flags);
497 i = (i + 1) & RX_QUEUE_MASK;
498 /* If there are a lot of unused frames,
499 * restock the Rx queue so ucode wont assert. */
504 iwlagn_rx_replenish_now(trans);
510 /* Backtrack one entry */
513 iwlagn_rx_replenish_now(trans);
515 iwlagn_rx_queue_restock(trans);
518 static const char * const desc_lookup_text[] = {
527 "HW_ERROR_TUNE_LOCK",
528 "HW_ERROR_TEMPERATURE",
532 "NMI_INTERRUPT_HOST",
533 "NMI_INTERRUPT_ACTION_PT",
534 "NMI_INTERRUPT_UNKNOWN",
535 "UCODE_VERSION_MISMATCH",
537 "HW_ERROR_CAL_LOCK_FAIL",
538 "NMI_INTERRUPT_INST_ACTION_PT",
539 "NMI_INTERRUPT_DATA_ACTION_PT",
542 "NMI_INTERRUPT_BREAK_POINT",
549 static struct { char *name; u8 num; } advanced_lookup[] = {
550 { "NMI_INTERRUPT_WDG", 0x34 },
551 { "SYSASSERT", 0x35 },
552 { "UCODE_VERSION_MISMATCH", 0x37 },
553 { "BAD_COMMAND", 0x38 },
554 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
555 { "FATAL_ERROR", 0x3D },
556 { "NMI_TRM_HW_ERR", 0x46 },
557 { "NMI_INTERRUPT_TRM", 0x4C },
558 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
559 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
560 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
561 { "NMI_INTERRUPT_HOST", 0x66 },
562 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
563 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
564 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
565 { "ADVANCED_SYSASSERT", 0 },
568 static const char *desc_lookup(u32 num)
571 int max = ARRAY_SIZE(desc_lookup_text);
574 return desc_lookup_text[num];
576 max = ARRAY_SIZE(advanced_lookup) - 1;
577 for (i = 0; i < max; i++) {
578 if (advanced_lookup[i].num == num)
581 return advanced_lookup[i].name;
584 #define ERROR_START_OFFSET (1 * sizeof(u32))
585 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
587 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
590 struct iwl_error_event_table table;
591 struct iwl_priv *priv = priv(trans);
592 struct iwl_trans_pcie *trans_pcie =
593 IWL_TRANS_GET_PCIE_TRANS(trans);
595 base = priv->device_pointers.error_event_table;
596 if (priv->ucode_type == IWL_UCODE_INIT) {
598 base = priv->init_errlog_ptr;
601 base = priv->inst_errlog_ptr;
604 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
606 "Not valid error log pointer 0x%08X for %s uCode\n",
608 (priv->ucode_type == IWL_UCODE_INIT)
613 iwl_read_targ_mem_words(bus(priv), base, &table, sizeof(table));
615 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
616 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
617 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
618 trans->shrd->status, table.valid);
621 trans_pcie->isr_stats.err_code = table.error_id;
623 trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
624 table.data1, table.data2, table.line,
625 table.blink1, table.blink2, table.ilink1,
626 table.ilink2, table.bcon_time, table.gp1,
627 table.gp2, table.gp3, table.ucode_ver,
628 table.hw_ver, table.brd_ver);
629 IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
630 desc_lookup(table.error_id));
631 IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
632 IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
633 IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
634 IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
635 IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
636 IWL_ERR(trans, "0x%08X | data1\n", table.data1);
637 IWL_ERR(trans, "0x%08X | data2\n", table.data2);
638 IWL_ERR(trans, "0x%08X | line\n", table.line);
639 IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
640 IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
641 IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
642 IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
643 IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
644 IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
645 IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
646 IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
647 IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
648 IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
652 * iwl_irq_handle_error - called for HW or SW error interrupt from card
654 static void iwl_irq_handle_error(struct iwl_trans *trans)
656 struct iwl_priv *priv = priv(trans);
657 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
658 if (priv->cfg->internal_wimax_coex &&
659 (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) &
660 APMS_CLK_VAL_MRB_FUNC_MODE) ||
661 (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) &
662 APMG_PS_CTRL_VAL_RESET_REQ))) {
664 * Keep the restart process from trying to send host
665 * commands by clearing the ready bit.
667 clear_bit(STATUS_READY, &trans->shrd->status);
668 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
669 wake_up(&priv->shrd->wait_command_queue);
670 IWL_ERR(trans, "RF is used by WiMAX\n");
674 IWL_ERR(trans, "Loaded firmware version: %s\n",
675 priv->hw->wiphy->fw_version);
677 iwl_dump_nic_error_log(trans);
679 iwl_dump_fh(trans, NULL, false);
680 iwl_dump_nic_event_log(trans, false, NULL, false);
681 #ifdef CONFIG_IWLWIFI_DEBUG
682 if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
683 iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS);
686 iwlagn_fw_error(priv, false);
689 #define EVENT_START_OFFSET (4 * sizeof(u32))
692 * iwl_print_event_log - Dump error event log to syslog
695 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
696 u32 num_events, u32 mode,
697 int pos, char **buf, size_t bufsz)
700 u32 base; /* SRAM byte address of event log header */
701 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
702 u32 ptr; /* SRAM byte address of log data */
703 u32 ev, time, data; /* event log data */
704 unsigned long reg_flags;
705 struct iwl_priv *priv = priv(trans);
710 base = priv->device_pointers.log_event_table;
711 if (priv->ucode_type == IWL_UCODE_INIT) {
713 base = priv->init_evtlog_ptr;
716 base = priv->inst_evtlog_ptr;
720 event_size = 2 * sizeof(u32);
722 event_size = 3 * sizeof(u32);
724 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
726 /* Make sure device is powered up for SRAM reads */
727 spin_lock_irqsave(&bus(trans)->reg_lock, reg_flags);
728 iwl_grab_nic_access(bus(trans));
730 /* Set starting address; reads will auto-increment */
731 iwl_write32(bus(trans), HBUS_TARG_MEM_RADDR, ptr);
734 /* "time" is actually "data" for mode 0 (no timestamp).
735 * place event id # at far right for easier visual parsing. */
736 for (i = 0; i < num_events; i++) {
737 ev = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
738 time = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
742 pos += scnprintf(*buf + pos, bufsz - pos,
743 "EVT_LOG:0x%08x:%04u\n",
746 trace_iwlwifi_dev_ucode_event(priv, 0,
748 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
752 data = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
754 pos += scnprintf(*buf + pos, bufsz - pos,
755 "EVT_LOGT:%010u:0x%08x:%04u\n",
758 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
760 trace_iwlwifi_dev_ucode_event(priv, time,
766 /* Allow device to power down */
767 iwl_release_nic_access(bus(trans));
768 spin_unlock_irqrestore(&bus(trans)->reg_lock, reg_flags);
773 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
775 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
776 u32 num_wraps, u32 next_entry,
778 int pos, char **buf, size_t bufsz)
781 * display the newest DEFAULT_LOG_ENTRIES entries
782 * i.e the entries just before the next ont that uCode would fill.
785 if (next_entry < size) {
786 pos = iwl_print_event_log(trans,
787 capacity - (size - next_entry),
788 size - next_entry, mode,
790 pos = iwl_print_event_log(trans, 0,
794 pos = iwl_print_event_log(trans, next_entry - size,
795 size, mode, pos, buf, bufsz);
797 if (next_entry < size) {
798 pos = iwl_print_event_log(trans, 0, next_entry,
799 mode, pos, buf, bufsz);
801 pos = iwl_print_event_log(trans, next_entry - size,
802 size, mode, pos, buf, bufsz);
808 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
810 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
811 char **buf, bool display)
813 u32 base; /* SRAM byte address of event log header */
814 u32 capacity; /* event log capacity in # entries */
815 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
816 u32 num_wraps; /* # times uCode wrapped to top of log */
817 u32 next_entry; /* index of next entry to be written by uCode */
818 u32 size; /* # entries that we'll print */
822 struct iwl_priv *priv = priv(trans);
824 base = priv->device_pointers.log_event_table;
825 if (priv->ucode_type == IWL_UCODE_INIT) {
826 logsize = priv->init_evtlog_size;
828 base = priv->init_evtlog_ptr;
830 logsize = priv->inst_evtlog_size;
832 base = priv->inst_evtlog_ptr;
835 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
837 "Invalid event log pointer 0x%08X for %s uCode\n",
839 (priv->ucode_type == IWL_UCODE_INIT)
844 /* event log header */
845 capacity = iwl_read_targ_mem(bus(trans), base);
846 mode = iwl_read_targ_mem(bus(trans), base + (1 * sizeof(u32)));
847 num_wraps = iwl_read_targ_mem(bus(trans), base + (2 * sizeof(u32)));
848 next_entry = iwl_read_targ_mem(bus(trans), base + (3 * sizeof(u32)));
850 if (capacity > logsize) {
851 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
852 "entries\n", capacity, logsize);
856 if (next_entry > logsize) {
857 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
858 next_entry, logsize);
859 next_entry = logsize;
862 size = num_wraps ? capacity : next_entry;
864 /* bail out if nothing in log */
866 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
870 #ifdef CONFIG_IWLWIFI_DEBUG
871 if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log)
872 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
873 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
875 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
876 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
878 IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
881 #ifdef CONFIG_IWLWIFI_DEBUG
884 bufsz = capacity * 48;
887 *buf = kmalloc(bufsz, GFP_KERNEL);
891 if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) {
893 * if uCode has wrapped back to top of log,
894 * start at the oldest entry,
895 * i.e the next one that uCode would fill.
898 pos = iwl_print_event_log(trans, next_entry,
899 capacity - next_entry, mode,
901 /* (then/else) start at top of log */
902 pos = iwl_print_event_log(trans, 0,
903 next_entry, mode, pos, buf, bufsz);
905 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
906 next_entry, size, mode,
909 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
910 next_entry, size, mode,
916 /* tasklet for iwlagn interrupt */
917 void iwl_irq_tasklet(struct iwl_trans *trans)
923 #ifdef CONFIG_IWLWIFI_DEBUG
927 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
928 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
931 spin_lock_irqsave(&trans->shrd->lock, flags);
933 /* Ack/clear/reset pending uCode interrupts.
934 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
936 /* There is a hardware bug in the interrupt mask function that some
937 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
938 * they are disabled in the CSR_INT_MASK register. Furthermore the
939 * ICT interrupt handling mechanism has another bug that might cause
940 * these unmasked interrupts fail to be detected. We workaround the
941 * hardware bugs here by ACKing all the possible interrupts so that
942 * interrupt coalescing can still be achieved.
944 iwl_write32(bus(trans), CSR_INT,
945 trans_pcie->inta | ~trans_pcie->inta_mask);
947 inta = trans_pcie->inta;
949 #ifdef CONFIG_IWLWIFI_DEBUG
950 if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
952 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
953 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
958 spin_unlock_irqrestore(&trans->shrd->lock, flags);
960 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
961 trans_pcie->inta = 0;
963 /* Now service all interrupt bits discovered above. */
964 if (inta & CSR_INT_BIT_HW_ERR) {
965 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
967 /* Tell the device to stop sending interrupts */
968 iwl_disable_interrupts(trans);
971 iwl_irq_handle_error(trans);
973 handled |= CSR_INT_BIT_HW_ERR;
978 #ifdef CONFIG_IWLWIFI_DEBUG
979 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
980 /* NIC fires this, but we don't use it, redundant with WAKEUP */
981 if (inta & CSR_INT_BIT_SCD) {
982 IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
983 "the frame/frames.\n");
987 /* Alive notification via Rx interrupt will do the real work */
988 if (inta & CSR_INT_BIT_ALIVE) {
989 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
994 /* Safely ignore these bits for debug checks below */
995 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
997 /* HW RF KILL switch toggled */
998 if (inta & CSR_INT_BIT_RF_KILL) {
1000 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1001 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1004 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1005 hw_rf_kill ? "disable radio" : "enable radio");
1007 isr_stats->rfkill++;
1009 /* driver only loads ucode once setting the interface up.
1010 * the driver allows loading the ucode even if the radio
1011 * is killed. Hence update the killswitch state here. The
1012 * rfkill handler will care about restarting if needed.
1014 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1016 set_bit(STATUS_RF_KILL_HW,
1017 &trans->shrd->status);
1019 clear_bit(STATUS_RF_KILL_HW,
1020 &trans->shrd->status);
1021 iwl_set_hw_rfkill_state(priv(trans), hw_rf_kill);
1024 handled |= CSR_INT_BIT_RF_KILL;
1027 /* Chip got too hot and stopped itself */
1028 if (inta & CSR_INT_BIT_CT_KILL) {
1029 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1030 isr_stats->ctkill++;
1031 handled |= CSR_INT_BIT_CT_KILL;
1034 /* Error detected by uCode */
1035 if (inta & CSR_INT_BIT_SW_ERR) {
1036 IWL_ERR(trans, "Microcode SW error detected. "
1037 " Restarting 0x%X.\n", inta);
1039 iwl_irq_handle_error(trans);
1040 handled |= CSR_INT_BIT_SW_ERR;
1043 /* uCode wakes up after power-down sleep */
1044 if (inta & CSR_INT_BIT_WAKEUP) {
1045 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1046 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1047 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1048 iwl_txq_update_write_ptr(trans,
1049 &trans_pcie->txq[i]);
1051 isr_stats->wakeup++;
1053 handled |= CSR_INT_BIT_WAKEUP;
1056 /* All uCode command responses, including Tx command responses,
1057 * Rx "responses" (frame-received notification), and other
1058 * notifications from uCode come through here*/
1059 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1060 CSR_INT_BIT_RX_PERIODIC)) {
1061 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1062 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1063 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1064 iwl_write32(bus(trans), CSR_FH_INT_STATUS,
1065 CSR_FH_INT_RX_MASK);
1067 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1068 handled |= CSR_INT_BIT_RX_PERIODIC;
1069 iwl_write32(bus(trans),
1070 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1072 /* Sending RX interrupt require many steps to be done in the
1074 * 1- write interrupt to current index in ICT table.
1076 * 3- update RX shared data to indicate last write index.
1077 * 4- send interrupt.
1078 * This could lead to RX race, driver could receive RX interrupt
1079 * but the shared data changes does not reflect this;
1080 * periodic interrupt will detect any dangling Rx activity.
1083 /* Disable periodic interrupt; we use it as just a one-shot. */
1084 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1085 CSR_INT_PERIODIC_DIS);
1086 iwl_rx_handle(trans);
1089 * Enable periodic interrupt in 8 msec only if we received
1090 * real RX interrupt (instead of just periodic int), to catch
1091 * any dangling Rx interrupt. If it was just the periodic
1092 * interrupt, there was no dangling Rx activity, and no need
1093 * to extend the periodic interrupt; one-shot is enough.
1095 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1096 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1097 CSR_INT_PERIODIC_ENA);
1102 /* This "Tx" DMA channel is used only for loading uCode */
1103 if (inta & CSR_INT_BIT_FH_TX) {
1104 iwl_write32(bus(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1105 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1107 handled |= CSR_INT_BIT_FH_TX;
1108 /* Wake up uCode load routine, now that load is complete */
1109 priv(trans)->ucode_write_complete = 1;
1110 wake_up(&trans->shrd->wait_command_queue);
1113 if (inta & ~handled) {
1114 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1115 isr_stats->unhandled++;
1118 if (inta & ~(trans_pcie->inta_mask)) {
1119 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1120 inta & ~trans_pcie->inta_mask);
1123 /* Re-enable all interrupts */
1124 /* only Re-enable if disabled by irq */
1125 if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1126 iwl_enable_interrupts(trans);
1127 /* Re-enable RF_KILL if it occurred */
1128 else if (handled & CSR_INT_BIT_RF_KILL)
1129 iwl_enable_rfkill_int(priv(trans));
1132 /******************************************************************************
1136 ******************************************************************************/
1137 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1139 /* Free dram table */
1140 void iwl_free_isr_ict(struct iwl_trans *trans)
1142 struct iwl_trans_pcie *trans_pcie =
1143 IWL_TRANS_GET_PCIE_TRANS(trans);
1145 if (trans_pcie->ict_tbl_vir) {
1146 dma_free_coherent(bus(trans)->dev,
1147 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1148 trans_pcie->ict_tbl_vir,
1149 trans_pcie->ict_tbl_dma);
1150 trans_pcie->ict_tbl_vir = NULL;
1151 memset(&trans_pcie->ict_tbl_dma, 0,
1152 sizeof(trans_pcie->ict_tbl_dma));
1153 memset(&trans_pcie->aligned_ict_tbl_dma, 0,
1154 sizeof(trans_pcie->aligned_ict_tbl_dma));
1159 /* allocate dram shared table it is a PAGE_SIZE aligned
1160 * also reset all data related to ICT table interrupt.
1162 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1164 struct iwl_trans_pcie *trans_pcie =
1165 IWL_TRANS_GET_PCIE_TRANS(trans);
1167 /* allocate shrared data table */
1168 trans_pcie->ict_tbl_vir =
1169 dma_alloc_coherent(bus(trans)->dev,
1170 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1171 &trans_pcie->ict_tbl_dma, GFP_KERNEL);
1172 if (!trans_pcie->ict_tbl_vir)
1175 /* align table to PAGE_SIZE boundary */
1176 trans_pcie->aligned_ict_tbl_dma =
1177 ALIGN(trans_pcie->ict_tbl_dma, PAGE_SIZE);
1179 IWL_DEBUG_ISR(trans, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1180 (unsigned long long)trans_pcie->ict_tbl_dma,
1181 (unsigned long long)trans_pcie->aligned_ict_tbl_dma,
1182 (int)(trans_pcie->aligned_ict_tbl_dma -
1183 trans_pcie->ict_tbl_dma));
1185 trans_pcie->ict_tbl = trans_pcie->ict_tbl_vir +
1186 (trans_pcie->aligned_ict_tbl_dma -
1187 trans_pcie->ict_tbl_dma);
1189 IWL_DEBUG_ISR(trans, "ict vir addr %p vir aligned %p diff %d\n",
1190 trans_pcie->ict_tbl, trans_pcie->ict_tbl_vir,
1191 (int)(trans_pcie->aligned_ict_tbl_dma -
1192 trans_pcie->ict_tbl_dma));
1194 /* reset table and index to all 0 */
1195 memset(trans_pcie->ict_tbl_vir, 0,
1196 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1197 trans_pcie->ict_index = 0;
1199 /* add periodic RX interrupt */
1200 trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1204 /* Device is going up inform it about using ICT interrupt table,
1205 * also we need to tell the driver to start using ICT interrupt.
1207 int iwl_reset_ict(struct iwl_trans *trans)
1210 unsigned long flags;
1211 struct iwl_trans_pcie *trans_pcie =
1212 IWL_TRANS_GET_PCIE_TRANS(trans);
1214 if (!trans_pcie->ict_tbl_vir)
1217 spin_lock_irqsave(&trans->shrd->lock, flags);
1218 iwl_disable_interrupts(trans);
1220 memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
1222 val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;
1224 val |= CSR_DRAM_INT_TBL_ENABLE;
1225 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1227 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
1228 "aligned dma address %Lx\n",
1230 (unsigned long long)trans_pcie->aligned_ict_tbl_dma);
1232 iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
1233 trans_pcie->use_ict = true;
1234 trans_pcie->ict_index = 0;
1235 iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
1236 iwl_enable_interrupts(trans);
1237 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1242 /* Device is going down disable ict interrupt usage */
1243 void iwl_disable_ict(struct iwl_trans *trans)
1245 struct iwl_trans_pcie *trans_pcie =
1246 IWL_TRANS_GET_PCIE_TRANS(trans);
1248 unsigned long flags;
1250 spin_lock_irqsave(&trans->shrd->lock, flags);
1251 trans_pcie->use_ict = false;
1252 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1255 static irqreturn_t iwl_isr(int irq, void *data)
1257 struct iwl_trans *trans = data;
1258 struct iwl_trans_pcie *trans_pcie;
1259 u32 inta, inta_mask;
1260 unsigned long flags;
1261 #ifdef CONFIG_IWLWIFI_DEBUG
1267 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1269 spin_lock_irqsave(&trans->shrd->lock, flags);
1271 /* Disable (but don't clear!) interrupts here to avoid
1272 * back-to-back ISRs and sporadic interrupts from our NIC.
1273 * If we have something to service, the tasklet will re-enable ints.
1274 * If we *don't* have something, we'll re-enable before leaving here. */
1275 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK); /* just for debug */
1276 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1278 /* Discover which interrupts are active/pending */
1279 inta = iwl_read32(bus(trans), CSR_INT);
1281 /* Ignore interrupt if there's nothing in NIC to service.
1282 * This may be due to IRQ shared with another device,
1283 * or due to sporadic interrupts thrown from our NIC. */
1285 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1289 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1290 /* Hardware disappeared. It might have already raised
1292 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1296 #ifdef CONFIG_IWLWIFI_DEBUG
1297 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1298 inta_fh = iwl_read32(bus(trans), CSR_FH_INT_STATUS);
1299 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1300 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1304 trans_pcie->inta |= inta;
1305 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1307 tasklet_schedule(&trans_pcie->irq_tasklet);
1308 else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1310 iwl_enable_interrupts(trans);
1313 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1317 /* re-enable interrupts here since we don't have anything to service. */
1318 /* only Re-enable if disabled by irq and no schedules tasklet. */
1319 if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1321 iwl_enable_interrupts(trans);
1323 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1327 /* interrupt handler using ict table, with this interrupt driver will
1328 * stop using INTA register to get device's interrupt, reading this register
1329 * is expensive, device will write interrupts in ICT dram table, increment
1330 * index then will fire interrupt to driver, driver will OR all ICT table
1331 * entries from current index up to table entry with 0 value. the result is
1332 * the interrupt we need to service, driver will set the entries back to 0 and
1335 irqreturn_t iwl_isr_ict(int irq, void *data)
1337 struct iwl_trans *trans = data;
1338 struct iwl_trans_pcie *trans_pcie;
1339 u32 inta, inta_mask;
1341 unsigned long flags;
1346 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1348 /* dram interrupt table not set yet,
1349 * use legacy interrupt.
1351 if (!trans_pcie->use_ict)
1352 return iwl_isr(irq, data);
1354 spin_lock_irqsave(&trans->shrd->lock, flags);
1356 /* Disable (but don't clear!) interrupts here to avoid
1357 * back-to-back ISRs and sporadic interrupts from our NIC.
1358 * If we have something to service, the tasklet will re-enable ints.
1359 * If we *don't* have something, we'll re-enable before leaving here.
1361 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK); /* just for debug */
1362 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1365 /* Ignore interrupt if there's nothing in NIC to service.
1366 * This may be due to IRQ shared with another device,
1367 * or due to sporadic interrupts thrown from our NIC. */
1368 if (!trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1369 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1373 /* read all entries that not 0 start with ict_index */
1374 while (trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1376 val |= le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1377 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1378 trans_pcie->ict_index,
1380 trans_pcie->ict_tbl[trans_pcie->ict_index]));
1381 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1382 trans_pcie->ict_index =
1383 iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1387 /* We should not get this value, just ignore it. */
1388 if (val == 0xffffffff)
1392 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1393 * (bit 15 before shifting it to 31) to clear when using interrupt
1394 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1395 * so we use them to decide on the real state of the Rx bit.
1396 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1401 inta = (0xff & val) | ((0xff00 & val) << 16);
1402 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1403 inta, inta_mask, val);
1405 inta &= trans_pcie->inta_mask;
1406 trans_pcie->inta |= inta;
1408 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1410 tasklet_schedule(&trans_pcie->irq_tasklet);
1411 else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1412 !trans_pcie->inta) {
1413 /* Allow interrupt if was disabled by this handler and
1414 * no tasklet was schedules, We should not enable interrupt,
1415 * tasklet will enable it.
1417 iwl_enable_interrupts(trans);
1420 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1424 /* re-enable interrupts here since we don't have anything to service.
1425 * only Re-enable if disabled by irq.
1427 if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1429 iwl_enable_interrupts(trans);
1431 spin_unlock_irqrestore(&trans->shrd->lock, flags);