drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
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  20  * along with this program; if not, write to the Free Software
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  22  * USA
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  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
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  32  *
  33  * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
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  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/interrupt.h>
  64 #include <linux/debugfs.h>
  65 #include <linux/bitops.h>
  66 #include <linux/gfp.h>
  67
  68 #include "iwl-trans.h"
  69 #include "iwl-trans-pcie-int.h"
  70 #include "iwl-csr.h"
  71 #include "iwl-prph.h"
  72 #include "iwl-shared.h"
  73 #include "iwl-eeprom.h"
  74 #include "iwl-agn-hw.h"
  75
  76 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  77 {
  78         struct iwl_trans_pcie *trans_pcie =
  79                 IWL_TRANS_GET_PCIE_TRANS(trans);
  80         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  81         struct device *dev = bus(trans)->dev;
  82
  83         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  84
  85         spin_lock_init(&rxq->lock);
  86
  87         if (WARN_ON(rxq->bd || rxq->rb_stts))
  88                 return -EINVAL;
  89
  90         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  91         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  92                                       &rxq->bd_dma, GFP_KERNEL);
  93         if (!rxq->bd)
  94                 goto err_bd;
  95
  96         /*Allocate the driver's pointer to receive buffer status */
  97         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
  98                                            &rxq->rb_stts_dma, GFP_KERNEL);
  99         if (!rxq->rb_stts)
 100                 goto err_rb_stts;
 101
 102         return 0;
 103
 104 err_rb_stts:
 105         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 106                         rxq->bd, rxq->bd_dma);
 107         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 108         rxq->bd = NULL;
 109 err_bd:
 110         return -ENOMEM;
 111 }
 112
 113 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 114 {
 115         struct iwl_trans_pcie *trans_pcie =
 116                 IWL_TRANS_GET_PCIE_TRANS(trans);
 117         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 118         int i;
 119
 120         /* Fill the rx_used queue with _all_ of the Rx buffers */
 121         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 122                 /* In the reset function, these buffers may have been allocated
 123                  * to an SKB, so we need to unmap and free potential storage */
 124                 if (rxq->pool[i].page != NULL) {
 125                         dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
 126                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 127                                 DMA_FROM_DEVICE);
 128                         __free_pages(rxq->pool[i].page,
 129                                      hw_params(trans).rx_page_order);
 130                         rxq->pool[i].page = NULL;
 131                 }
 132                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 133         }
 134 }
 135
 136 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 137                                  struct iwl_rx_queue *rxq)
 138 {
 139         u32 rb_size;
 140         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 141         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 142
 143         if (iwlagn_mod_params.amsdu_size_8K)
 144                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 145         else
 146                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 147
 148         /* Stop Rx DMA */
 149         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 150
 151         /* Reset driver's Rx queue write index */
 152         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 153
 154         /* Tell device where to find RBD circular buffer in DRAM */
 155         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 156                            (u32)(rxq->bd_dma >> 8));
 157
 158         /* Tell device where in DRAM to update its Rx status */
 159         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
 160                            rxq->rb_stts_dma >> 4);
 161
 162         /* Enable Rx DMA
 163          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 164          *      the credit mechanism in 5000 HW RX FIFO
 165          * Direct rx interrupts to hosts
 166          * Rx buffer size 4 or 8k
 167          * RB timeout 0x10
 168          * 256 RBDs
 169          */
 170         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
 171                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 172                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 173                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 174                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 175                            rb_size|
 176                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 177                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 178
 179         /* Set interrupt coalescing timer to default (2048 usecs) */
 180         iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 181 }
 182
 183 static int iwl_rx_init(struct iwl_trans *trans)
 184 {
 185         struct iwl_trans_pcie *trans_pcie =
 186                 IWL_TRANS_GET_PCIE_TRANS(trans);
 187         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 188
 189         int i, err;
 190         unsigned long flags;
 191
 192         if (!rxq->bd) {
 193                 err = iwl_trans_rx_alloc(trans);
 194                 if (err)
 195                         return err;
 196         }
 197
 198         spin_lock_irqsave(&rxq->lock, flags);
 199         INIT_LIST_HEAD(&rxq->rx_free);
 200         INIT_LIST_HEAD(&rxq->rx_used);
 201
 202         iwl_trans_rxq_free_rx_bufs(trans);
 203
 204         for (i = 0; i < RX_QUEUE_SIZE; i++)
 205                 rxq->queue[i] = NULL;
 206
 207         /* Set us so that we have processed and used all buffers, but have
 208          * not restocked the Rx queue with fresh buffers */
 209         rxq->read = rxq->write = 0;
 210         rxq->write_actual = 0;
 211         rxq->free_count = 0;
 212         spin_unlock_irqrestore(&rxq->lock, flags);
 213
 214         iwlagn_rx_replenish(trans);
 215
 216         iwl_trans_rx_hw_init(trans, rxq);
 217
 218         spin_lock_irqsave(&trans->shrd->lock, flags);
 219         rxq->need_update = 1;
 220         iwl_rx_queue_update_write_ptr(trans, rxq);
 221         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 222
 223         return 0;
 224 }
 225
 226 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 227 {
 228         struct iwl_trans_pcie *trans_pcie =
 229                 IWL_TRANS_GET_PCIE_TRANS(trans);
 230         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 231
 232         unsigned long flags;
 233
 234         /*if rxq->bd is NULL, it means that nothing has been allocated,
 235          * exit now */
 236         if (!rxq->bd) {
 237                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 238                 return;
 239         }
 240
 241         spin_lock_irqsave(&rxq->lock, flags);
 242         iwl_trans_rxq_free_rx_bufs(trans);
 243         spin_unlock_irqrestore(&rxq->lock, flags);
 244
 245         dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 246                           rxq->bd, rxq->bd_dma);
 247         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 248         rxq->bd = NULL;
 249
 250         if (rxq->rb_stts)
 251                 dma_free_coherent(bus(trans)->dev,
 252                                   sizeof(struct iwl_rb_status),
 253                                   rxq->rb_stts, rxq->rb_stts_dma);
 254         else
 255                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 256         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 257         rxq->rb_stts = NULL;
 258 }
 259
 260 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 261 {
 262
 263         /* stop Rx DMA */
 264         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 265         return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
 266                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 267 }
 268
 269 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 270                                     struct iwl_dma_ptr *ptr, size_t size)
 271 {
 272         if (WARN_ON(ptr->addr))
 273                 return -EINVAL;
 274
 275         ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
 276                                        &ptr->dma, GFP_KERNEL);
 277         if (!ptr->addr)
 278                 return -ENOMEM;
 279         ptr->size = size;
 280         return 0;
 281 }
 282
 283 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 284                                     struct iwl_dma_ptr *ptr)
 285 {
 286         if (unlikely(!ptr->addr))
 287                 return;
 288
 289         dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
 290         memset(ptr, 0, sizeof(*ptr));
 291 }
 292
 293 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 294                                 struct iwl_tx_queue *txq, int slots_num,
 295                                 u32 txq_id)
 296 {
 297         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 298         int i;
 299
 300         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 301                 return -EINVAL;
 302
 303         txq->q.n_window = slots_num;
 304
 305         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 306         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 307
 308         if (!txq->meta || !txq->cmd)
 309                 goto error;
 310
 311         if (txq_id == trans->shrd->cmd_queue)
 312                 for (i = 0; i < slots_num; i++) {
 313                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 314                                                 GFP_KERNEL);
 315                         if (!txq->cmd[i])
 316                                 goto error;
 317                 }
 318
 319         /* Alloc driver data array and TFD circular buffer */
 320         /* Driver private data, only for Tx (not command) queues,
 321          * not shared with device. */
 322         if (txq_id != trans->shrd->cmd_queue) {
 323                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 324                                     GFP_KERNEL);
 325                 if (!txq->skbs) {
 326                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 327                                   "structures failed\n");
 328                         goto error;
 329                 }
 330         } else {
 331                 txq->skbs = NULL;
 332         }
 333
 334         /* Circular buffer of transmit frame descriptors (TFDs),
 335          * shared with device */
 336         txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
 337                                        &txq->q.dma_addr, GFP_KERNEL);
 338         if (!txq->tfds) {
 339                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 340                 goto error;
 341         }
 342         txq->q.id = txq_id;
 343
 344         return 0;
 345 error:
 346         kfree(txq->skbs);
 347         txq->skbs = NULL;
 348         /* since txq->cmd has been zeroed,
 349          * all non allocated cmd[i] will be NULL */
 350         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 351                 for (i = 0; i < slots_num; i++)
 352                         kfree(txq->cmd[i]);
 353         kfree(txq->meta);
 354         kfree(txq->cmd);
 355         txq->meta = NULL;
 356         txq->cmd = NULL;
 357
 358         return -ENOMEM;
 359
 360 }
 361
 362 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 363                       int slots_num, u32 txq_id)
 364 {
 365         int ret;
 366
 367         txq->need_update = 0;
 368         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 369
 370         /*
 371          * For the default queues 0-3, set up the swq_id
 372          * already -- all others need to get one later
 373          * (if they need one at all).
 374          */
 375         if (txq_id < 4)
 376                 iwl_set_swq_id(txq, txq_id, txq_id);
 377
 378         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 379          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 380         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 381
 382         /* Initialize queue's high/low-water marks, and head/tail indexes */
 383         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 384                         txq_id);
 385         if (ret)
 386                 return ret;
 387
 388         /*
 389          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 390          * given Tx queue, and enable the DMA channel used for that queue.
 391          * Circular buffer (TFD queue in DRAM) physical base address */
 392         iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
 393                              txq->q.dma_addr >> 8);
 394
 395         return 0;
 396 }
 397
 398 /**
 399  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 400  */
 401 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 402 {
 403         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 404         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 405         struct iwl_queue *q = &txq->q;
 406         enum dma_data_direction dma_dir;
 407         unsigned long flags;
 408         spinlock_t *lock;
 409
 410         if (!q->n_bd)
 411                 return;
 412
 413         /* In the command queue, all the TBs are mapped as BIDI
 414          * so unmap them as such.
 415          */
 416         if (txq_id == trans->shrd->cmd_queue) {
 417                 dma_dir = DMA_BIDIRECTIONAL;
 418                 lock = &trans->hcmd_lock;
 419         } else {
 420                 dma_dir = DMA_TO_DEVICE;
 421                 lock = &trans->shrd->sta_lock;
 422         }
 423
 424         spin_lock_irqsave(lock, flags);
 425         while (q->write_ptr != q->read_ptr) {
 426                 /* The read_ptr needs to bound by q->n_window */
 427                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 428                                     dma_dir);
 429                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 430         }
 431         spin_unlock_irqrestore(lock, flags);
 432 }
 433
 434 /**
 435  * iwl_tx_queue_free - Deallocate DMA queue.
 436  * @txq: Transmit queue to deallocate.
 437  *
 438  * Empty queue by removing and destroying all BD's.
 439  * Free all buffers.
 440  * 0-fill, but do not free "txq" descriptor structure.
 441  */
 442 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 443 {
 444         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 445         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 446         struct device *dev = bus(trans)->dev;
 447         int i;
 448         if (WARN_ON(!txq))
 449                 return;
 450
 451         iwl_tx_queue_unmap(trans, txq_id);
 452
 453         /* De-alloc array of command/tx buffers */
 454
 455         if (txq_id == trans->shrd->cmd_queue)
 456                 for (i = 0; i < txq->q.n_window; i++)
 457                         kfree(txq->cmd[i]);
 458
 459         /* De-alloc circular buffer of TFDs */
 460         if (txq->q.n_bd) {
 461                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 462                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 463                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 464         }
 465
 466         /* De-alloc array of per-TFD driver data */
 467         kfree(txq->skbs);
 468         txq->skbs = NULL;
 469
 470         /* deallocate arrays */
 471         kfree(txq->cmd);
 472         kfree(txq->meta);
 473         txq->cmd = NULL;
 474         txq->meta = NULL;
 475
 476         /* 0-fill queue descriptor structure */
 477         memset(txq, 0, sizeof(*txq));
 478 }
 479
 480 /**
 481  * iwl_trans_tx_free - Free TXQ Context
 482  *
 483  * Destroy all TX DMA queues and structures
 484  */
 485 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 486 {
 487         int txq_id;
 488         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 489
 490         /* Tx queues */
 491         if (trans_pcie->txq) {
 492                 for (txq_id = 0;
 493                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 494                         iwl_tx_queue_free(trans, txq_id);
 495         }
 496
 497         kfree(trans_pcie->txq);
 498         trans_pcie->txq = NULL;
 499
 500         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 501
 502         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 503 }
 504
 505 /**
 506  * iwl_trans_tx_alloc - allocate TX context
 507  * Allocate all Tx DMA structures and initialize them
 508  *
 509  * @param priv
 510  * @return error code
 511  */
 512 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 513 {
 514         int ret;
 515         int txq_id, slots_num;
 516         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 517
 518         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 519                         sizeof(struct iwlagn_scd_bc_tbl);
 520
 521         /*It is not allowed to alloc twice, so warn when this happens.
 522          * We cannot rely on the previous allocation, so free and fail */
 523         if (WARN_ON(trans_pcie->txq)) {
 524                 ret = -EINVAL;
 525                 goto error;
 526         }
 527
 528         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 529                                    scd_bc_tbls_size);
 530         if (ret) {
 531                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 532                 goto error;
 533         }
 534
 535         /* Alloc keep-warm buffer */
 536         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 537         if (ret) {
 538                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 539                 goto error;
 540         }
 541
 542         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 543                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 544         if (!trans_pcie->txq) {
 545                 IWL_ERR(trans, "Not enough memory for txq\n");
 546                 ret = ENOMEM;
 547                 goto error;
 548         }
 549
 550         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 551         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 552                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 553                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 554                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 555                                           slots_num, txq_id);
 556                 if (ret) {
 557                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 558                         goto error;
 559                 }
 560         }
 561
 562         return 0;
 563
 564 error:
 565         iwl_trans_pcie_tx_free(trans);
 566
 567         return ret;
 568 }
 569 static int iwl_tx_init(struct iwl_trans *trans)
 570 {
 571         int ret;
 572         int txq_id, slots_num;
 573         unsigned long flags;
 574         bool alloc = false;
 575         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 576
 577         if (!trans_pcie->txq) {
 578                 ret = iwl_trans_tx_alloc(trans);
 579                 if (ret)
 580                         goto error;
 581                 alloc = true;
 582         }
 583
 584         spin_lock_irqsave(&trans->shrd->lock, flags);
 585
 586         /* Turn off all Tx DMA fifos */
 587         iwl_write_prph(bus(trans), SCD_TXFACT, 0);
 588
 589         /* Tell NIC where to find the "keep warm" buffer */
 590         iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
 591                            trans_pcie->kw.dma >> 4);
 592
 593         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 594
 595         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 596         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 597                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 598                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 599                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 600                                          slots_num, txq_id);
 601                 if (ret) {
 602                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 603                         goto error;
 604                 }
 605         }
 606
 607         return 0;
 608 error:
 609         /*Upon error, free only if we allocated something */
 610         if (alloc)
 611                 iwl_trans_pcie_tx_free(trans);
 612         return ret;
 613 }
 614
 615 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 616 {
 617 /*
 618  * (for documentation purposes)
 619  * to set power to V_AUX, do:
 620
 621                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 622                         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 623                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 624                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 625  */
 626
 627         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 628                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 629                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 630 }
 631
 632 static int iwl_nic_init(struct iwl_trans *trans)
 633 {
 634         unsigned long flags;
 635
 636         /* nic_init */
 637         spin_lock_irqsave(&trans->shrd->lock, flags);
 638         iwl_apm_init(priv(trans));
 639
 640         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 641         iwl_write8(bus(trans), CSR_INT_COALESCING,
 642                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 643
 644         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 645
 646         iwl_set_pwr_vmain(trans);
 647
 648         iwl_nic_config(priv(trans));
 649
 650         /* Allocate the RX queue, or reset if it is already allocated */
 651         iwl_rx_init(trans);
 652
 653         /* Allocate or reset and init all Tx and Command queues */
 654         if (iwl_tx_init(trans))
 655                 return -ENOMEM;
 656
 657         if (hw_params(trans).shadow_reg_enable) {
 658                 /* enable shadow regs in HW */
 659                 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
 660                         0x800FFFFF);
 661         }
 662
 663         set_bit(STATUS_INIT, &trans->shrd->status);
 664
 665         return 0;
 666 }
 667
 668 #define HW_READY_TIMEOUT (50)
 669
 670 /* Note: returns poll_bit return value, which is >= 0 if success */
 671 static int iwl_set_hw_ready(struct iwl_trans *trans)
 672 {
 673         int ret;
 674
 675         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 676                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 677
 678         /* See if we got it */
 679         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 680                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 681                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 682                                 HW_READY_TIMEOUT);
 683
 684         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 685         return ret;
 686 }
 687
 688 /* Note: returns standard 0/-ERROR code */
 689 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
 690 {
 691         int ret;
 692
 693         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 694
 695         ret = iwl_set_hw_ready(trans);
 696         if (ret >= 0)
 697                 return 0;
 698
 699         /* If HW is not ready, prepare the conditions to check again */
 700         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 701                         CSR_HW_IF_CONFIG_REG_PREPARE);
 702
 703         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 704                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 705                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 706
 707         if (ret < 0)
 708                 return ret;
 709
 710         /* HW should be ready by now, check again. */
 711         ret = iwl_set_hw_ready(trans);
 712         if (ret >= 0)
 713                 return 0;
 714         return ret;
 715 }
 716
 717 #define IWL_AC_UNSET -1
 718
 719 struct queue_to_fifo_ac {
 720         s8 fifo, ac;
 721 };
 722
 723 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 724         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 725         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 726         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 727         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 728         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 729         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 730         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 731         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 732         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 733         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 734         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 735 };
 736
 737 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 738         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 739         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 740         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 741         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 742         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 743         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 744         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 745         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 746         { IWL_TX_FIFO_BE_IPAN, 2, },
 747         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 748         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 749 };
 750
 751 static const u8 iwlagn_bss_ac_to_fifo[] = {
 752         IWL_TX_FIFO_VO,
 753         IWL_TX_FIFO_VI,
 754         IWL_TX_FIFO_BE,
 755         IWL_TX_FIFO_BK,
 756 };
 757 static const u8 iwlagn_bss_ac_to_queue[] = {
 758         0, 1, 2, 3,
 759 };
 760 static const u8 iwlagn_pan_ac_to_fifo[] = {
 761         IWL_TX_FIFO_VO_IPAN,
 762         IWL_TX_FIFO_VI_IPAN,
 763         IWL_TX_FIFO_BE_IPAN,
 764         IWL_TX_FIFO_BK_IPAN,
 765 };
 766 static const u8 iwlagn_pan_ac_to_queue[] = {
 767         7, 6, 5, 4,
 768 };
 769
 770 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
 771 {
 772         int ret;
 773         struct iwl_trans_pcie *trans_pcie =
 774                 IWL_TRANS_GET_PCIE_TRANS(trans);
 775
 776         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
 777         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
 778         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
 779
 780         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
 781         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
 782
 783         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
 784         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
 785
 786         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
 787              iwl_trans_pcie_prepare_card_hw(trans)) {
 788                 IWL_WARN(trans, "Exit HW not ready\n");
 789                 return -EIO;
 790         }
 791
 792         /* If platform's RF_KILL switch is NOT set to KILL */
 793         if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
 794                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
 795                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 796         else
 797                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 798
 799         if (iwl_is_rfkill(trans->shrd)) {
 800                 iwl_set_hw_rfkill_state(priv(trans), true);
 801                 iwl_enable_interrupts(trans);
 802                 return -ERFKILL;
 803         }
 804
 805         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 806
 807         ret = iwl_nic_init(trans);
 808         if (ret) {
 809                 IWL_ERR(trans, "Unable to init nic\n");
 810                 return ret;
 811         }
 812
 813         /* make sure rfkill handshake bits are cleared */
 814         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 815         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
 816                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 817
 818         /* clear (again), then enable host interrupts */
 819         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 820         iwl_enable_interrupts(trans);
 821
 822         /* really make sure rfkill handshake bits are cleared */
 823         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 824         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 825
 826         return 0;
 827 }
 828
 829 /*
 830  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 831  * must be called under priv->shrd->lock and mac access
 832  */
 833 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
 834 {
 835         iwl_write_prph(bus(trans), SCD_TXFACT, mask);
 836 }
 837
 838 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
 839 {
 840         const struct queue_to_fifo_ac *queue_to_fifo;
 841         struct iwl_trans_pcie *trans_pcie =
 842                 IWL_TRANS_GET_PCIE_TRANS(trans);
 843         u32 a;
 844         unsigned long flags;
 845         int i, chan;
 846         u32 reg_val;
 847
 848         spin_lock_irqsave(&trans->shrd->lock, flags);
 849
 850         trans_pcie->scd_base_addr =
 851                 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
 852         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
 853         /* reset conext data memory */
 854         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
 855                 a += 4)
 856                 iwl_write_targ_mem(bus(trans), a, 0);
 857         /* reset tx status memory */
 858         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
 859                 a += 4)
 860                 iwl_write_targ_mem(bus(trans), a, 0);
 861         for (; a < trans_pcie->scd_base_addr +
 862                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
 863                a += 4)
 864                 iwl_write_targ_mem(bus(trans), a, 0);
 865
 866         iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
 867                        trans_pcie->scd_bc_tbls.dma >> 10);
 868
 869         /* Enable DMA channel */
 870         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
 871                 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 872                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 873                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 874
 875         /* Update FH chicken bits */
 876         reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
 877         iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
 878                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 879
 880         iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
 881                 SCD_QUEUECHAIN_SEL_ALL(trans));
 882         iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
 883
 884         /* initiate the queues */
 885         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
 886                 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
 887                 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
 888                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 889                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 890                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 891                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
 892                                 sizeof(u32),
 893                                 ((SCD_WIN_SIZE <<
 894                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 895                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 896                                 ((SCD_FRAME_LIMIT <<
 897                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 898                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 899         }
 900
 901         iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
 902                         IWL_MASK(0, hw_params(trans).max_txq_num));
 903
 904         /* Activate all Tx DMA/FIFO channels */
 905         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
 906
 907         /* map queues to FIFOs */
 908         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
 909                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
 910         else
 911                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
 912
 913         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
 914
 915         /* make sure all queue are not stopped */
 916         memset(&trans_pcie->queue_stopped[0], 0,
 917                 sizeof(trans_pcie->queue_stopped));
 918         for (i = 0; i < 4; i++)
 919                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
 920
 921         /* reset to 0 to enable all the queue first */
 922         trans_pcie->txq_ctx_active_msk = 0;
 923
 924         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
 925                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 926         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
 927                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 928
 929         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
 930                 int fifo = queue_to_fifo[i].fifo;
 931                 int ac = queue_to_fifo[i].ac;
 932
 933                 iwl_txq_ctx_activate(trans_pcie, i);
 934
 935                 if (fifo == IWL_TX_FIFO_UNUSED)
 936                         continue;
 937
 938                 if (ac != IWL_AC_UNSET)
 939                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
 940                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
 941                                               fifo, 0);
 942         }
 943
 944         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 945
 946         /* Enable L1-Active */
 947         iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
 948                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 949 }
 950
 951 /**
 952  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
 953  */
 954 static int iwl_trans_tx_stop(struct iwl_trans *trans)
 955 {
 956         int ch, txq_id;
 957         unsigned long flags;
 958         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 959
 960         /* Turn off all Tx DMA fifos */
 961         spin_lock_irqsave(&trans->shrd->lock, flags);
 962
 963         iwl_trans_txq_set_sched(trans, 0);
 964
 965         /* Stop each Tx DMA channel, and wait for it to be idle */
 966         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 967                 iwl_write_direct32(bus(trans),
 968                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 969                 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
 970                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
 971                                     1000))
 972                         IWL_ERR(trans, "Failing on timeout while stopping"
 973                             " DMA channel %d [0x%08x]", ch,
 974                             iwl_read_direct32(bus(trans),
 975                                               FH_TSSR_TX_STATUS_REG));
 976         }
 977         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 978
 979         if (!trans_pcie->txq) {
 980                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
 981                 return 0;
 982         }
 983
 984         /* Unmap DMA from host system and free skb's */
 985         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
 986                 iwl_tx_queue_unmap(trans, txq_id);
 987
 988         return 0;
 989 }
 990
 991 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 992 {
 993         unsigned long flags;
 994         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 995
 996         /* tell the device to stop sending interrupts */
 997         spin_lock_irqsave(&trans->shrd->lock, flags);
 998         iwl_disable_interrupts(trans);
 999         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1000
1001         /* device going down, Stop using ICT table */
1002         iwl_disable_ict(trans);
1003
1004         /*
1005          * If a HW restart happens during firmware loading,
1006          * then the firmware loading might call this function
1007          * and later it might be called again due to the
1008          * restart. So don't process again if the device is
1009          * already dead.
1010          */
1011         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1012                 iwl_trans_tx_stop(trans);
1013                 iwl_trans_rx_stop(trans);
1014
1015                 /* Power-down device's busmaster DMA clocks */
1016                 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1017                                APMG_CLK_VAL_DMA_CLK_RQT);
1018                 udelay(5);
1019         }
1020
1021         /* Make sure (redundant) we've released our request to stay awake */
1022         iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1023                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1024
1025         /* Stop the device, and put it in low power state */
1026         iwl_apm_stop(priv(trans));
1027
1028         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1029          * Clean again the interrupt here
1030          */
1031         spin_lock_irqsave(&trans->shrd->lock, flags);
1032         iwl_disable_interrupts(trans);
1033         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1034
1035         /* wait to make sure we flush pending tasklet*/
1036         synchronize_irq(bus(trans)->irq);
1037         tasklet_kill(&trans_pcie->irq_tasklet);
1038
1039         /* stop and reset the on-board processor */
1040         iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1041 }
1042
1043 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1044                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1045                 u8 sta_id, u8 tid)
1046 {
1047         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1048         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1049         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1050         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1051         struct iwl_cmd_meta *out_meta;
1052         struct iwl_tx_queue *txq;
1053         struct iwl_queue *q;
1054
1055         dma_addr_t phys_addr = 0;
1056         dma_addr_t txcmd_phys;
1057         dma_addr_t scratch_phys;
1058         u16 len, firstlen, secondlen;
1059         u8 wait_write_ptr = 0;
1060         u8 txq_id;
1061         bool is_agg = false;
1062         __le16 fc = hdr->frame_control;
1063         u8 hdr_len = ieee80211_hdrlen(fc);
1064         u16 __maybe_unused wifi_seq;
1065
1066         /*
1067          * Send this frame after DTIM -- there's a special queue
1068          * reserved for this for contexts that support AP mode.
1069          */
1070         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1071                 txq_id = trans_pcie->mcast_queue[ctx];
1072
1073                 /*
1074                  * The microcode will clear the more data
1075                  * bit in the last frame it transmits.
1076                  */
1077                 hdr->frame_control |=
1078                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1079         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1080                 txq_id = IWL_AUX_QUEUE;
1081         else
1082                 txq_id =
1083                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1084
1085         /* aggregation is on for this <sta,tid> */
1086         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1087                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1088                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1089                 is_agg = true;
1090         }
1091
1092         txq = &trans_pcie->txq[txq_id];
1093         q = &txq->q;
1094
1095         /* In AGG mode, the index in the ring must correspond to the WiFi
1096          * sequence number. This is a HW requirements to help the SCD to parse
1097          * the BA.
1098          * Check here that the packets are in the right place on the ring.
1099          */
1100 #ifdef CONFIG_IWLWIFI_DEBUG
1101         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1102         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1103                   "Q: %d WiFi Seq %d tfdNum %d",
1104                   txq_id, wifi_seq, q->write_ptr);
1105 #endif
1106
1107         /* Set up driver data for this TFD */
1108         txq->skbs[q->write_ptr] = skb;
1109         txq->cmd[q->write_ptr] = dev_cmd;
1110
1111         dev_cmd->hdr.cmd = REPLY_TX;
1112         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1113                                 INDEX_TO_SEQ(q->write_ptr)));
1114
1115         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1116         out_meta = &txq->meta[q->write_ptr];
1117
1118         /*
1119          * Use the first empty entry in this queue's command buffer array
1120          * to contain the Tx command and MAC header concatenated together
1121          * (payload data will be in another buffer).
1122          * Size of this varies, due to varying MAC header length.
1123          * If end is not dword aligned, we'll have 2 extra bytes at the end
1124          * of the MAC header (device reads on dword boundaries).
1125          * We'll tell device about this padding later.
1126          */
1127         len = sizeof(struct iwl_tx_cmd) +
1128                 sizeof(struct iwl_cmd_header) + hdr_len;
1129         firstlen = (len + 3) & ~3;
1130
1131         /* Tell NIC about any 2-byte padding after MAC header */
1132         if (firstlen != len)
1133                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1134
1135         /* Physical address of this Tx command's header (not MAC header!),
1136          * within command buffer array. */
1137         txcmd_phys = dma_map_single(bus(trans)->dev,
1138                                     &dev_cmd->hdr, firstlen,
1139                                     DMA_BIDIRECTIONAL);
1140         if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1141                 return -1;
1142         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1143         dma_unmap_len_set(out_meta, len, firstlen);
1144
1145         if (!ieee80211_has_morefrags(fc)) {
1146                 txq->need_update = 1;
1147         } else {
1148                 wait_write_ptr = 1;
1149                 txq->need_update = 0;
1150         }
1151
1152         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1153          * if any (802.11 null frames have no payload). */
1154         secondlen = skb->len - hdr_len;
1155         if (secondlen > 0) {
1156                 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1157                                            secondlen, DMA_TO_DEVICE);
1158                 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1159                         dma_unmap_single(bus(trans)->dev,
1160                                          dma_unmap_addr(out_meta, mapping),
1161                                          dma_unmap_len(out_meta, len),
1162                                          DMA_BIDIRECTIONAL);
1163                         return -1;
1164                 }
1165         }
1166
1167         /* Attach buffers to TFD */
1168         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1169         if (secondlen > 0)
1170                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1171                                              secondlen, 0);
1172
1173         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1174                                 offsetof(struct iwl_tx_cmd, scratch);
1175
1176         /* take back ownership of DMA buffer to enable update */
1177         dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1178                         DMA_BIDIRECTIONAL);
1179         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1180         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1181
1182         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1183                      le16_to_cpu(dev_cmd->hdr.sequence));
1184         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1185         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1186         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1187
1188         /* Set up entry for this TFD in Tx byte-count array */
1189         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1190
1191         dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1192                         DMA_BIDIRECTIONAL);
1193
1194         trace_iwlwifi_dev_tx(priv(trans),
1195                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1196                              sizeof(struct iwl_tfd),
1197                              &dev_cmd->hdr, firstlen,
1198                              skb->data + hdr_len, secondlen);
1199
1200         /* Tell device the write index *just past* this latest filled TFD */
1201         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1202         iwl_txq_update_write_ptr(trans, txq);
1203
1204         /*
1205          * At this point the frame is "transmitted" successfully
1206          * and we will get a TX status notification eventually,
1207          * regardless of the value of ret. "ret" only indicates
1208          * whether or not we should update the write pointer.
1209          */
1210         if (iwl_queue_space(q) < q->high_mark) {
1211                 if (wait_write_ptr) {
1212                         txq->need_update = 1;
1213                         iwl_txq_update_write_ptr(trans, txq);
1214                 } else {
1215                         iwl_stop_queue(trans, txq, "Queue is full");
1216                 }
1217         }
1218         return 0;
1219 }
1220
1221 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1222 {
1223         /* Remove all resets to allow NIC to operate */
1224         iwl_write32(bus(trans), CSR_RESET, 0);
1225 }
1226
1227 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1228 {
1229         struct iwl_trans_pcie *trans_pcie =
1230                 IWL_TRANS_GET_PCIE_TRANS(trans);
1231         int err;
1232
1233         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1234
1235         tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1236                 iwl_irq_tasklet, (unsigned long)trans);
1237
1238         iwl_alloc_isr_ict(trans);
1239
1240         err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1241                 DRV_NAME, trans);
1242         if (err) {
1243                 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1244                 iwl_free_isr_ict(trans);
1245                 return err;
1246         }
1247
1248         INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1249         return 0;
1250 }
1251
1252 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1253                       int txq_id, int ssn, u32 status,
1254                       struct sk_buff_head *skbs)
1255 {
1256         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1257         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1258         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1259         int tfd_num = ssn & (txq->q.n_bd - 1);
1260         int freed = 0;
1261
1262         txq->time_stamp = jiffies;
1263
1264         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1265                      tid != IWL_TID_NON_QOS &&
1266                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1267                 /*
1268                  * FIXME: this is a uCode bug which need to be addressed,
1269                  * log the information and return for now.
1270                  * Since it is can possibly happen very often and in order
1271                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1272                  */
1273                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1274                         "agg_txq[sta_id[tid] %d", txq_id,
1275                         trans_pcie->agg_txq[sta_id][tid]);
1276                 return 1;
1277         }
1278
1279         if (txq->q.read_ptr != tfd_num) {
1280                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1281                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1282                                 tfd_num, ssn);
1283                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1284                 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1285                    (!txq->sched_retry ||
1286                    status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1287                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1288         }
1289         return 0;
1290 }
1291
1292 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1293 {
1294         iwl_calib_free_results(trans);
1295         iwl_trans_pcie_tx_free(trans);
1296         iwl_trans_pcie_rx_free(trans);
1297         free_irq(bus(trans)->irq, trans);
1298         iwl_free_isr_ict(trans);
1299         trans->shrd->trans = NULL;
1300         kfree(trans);
1301 }
1302
1303 #ifdef CONFIG_PM_SLEEP
1304 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1305 {
1306         /*
1307          * This function is called when system goes into suspend state
1308          * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1309          * function first but since iwlagn_mac_stop() has no knowledge of
1310          * who the caller is,
1311          * it will not call apm_ops.stop() to stop the DMA operation.
1312          * Calling apm_ops.stop here to make sure we stop the DMA.
1313          *
1314          * But of course ... if we have configured WoWLAN then we did other
1315          * things already :-)
1316          */
1317         if (!trans->shrd->wowlan) {
1318                 iwl_apm_stop(priv(trans));
1319         } else {
1320                 iwl_disable_interrupts(trans);
1321                 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1322                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1329 {
1330         bool hw_rfkill = false;
1331
1332         iwl_enable_interrupts(trans);
1333
1334         if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1335                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1336                 hw_rfkill = true;
1337
1338         if (hw_rfkill)
1339                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1340         else
1341                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1342
1343         iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1344
1345         return 0;
1346 }
1347 #endif /* CONFIG_PM_SLEEP */
1348
1349 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1350                                           enum iwl_rxon_context_id ctx,
1351                                           const char *msg)
1352 {
1353         u8 ac, txq_id;
1354         struct iwl_trans_pcie *trans_pcie =
1355                 IWL_TRANS_GET_PCIE_TRANS(trans);
1356
1357         for (ac = 0; ac < AC_NUM; ac++) {
1358                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1359                 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1360                         ac,
1361                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1362                               ? "stopped" : "awake");
1363                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1364         }
1365 }
1366
1367 const struct iwl_trans_ops trans_ops_pcie;
1368
1369 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1370 {
1371         struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1372                                               sizeof(struct iwl_trans_pcie),
1373                                               GFP_KERNEL);
1374         if (iwl_trans) {
1375                 struct iwl_trans_pcie *trans_pcie =
1376                         IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1377                 iwl_trans->ops = &trans_ops_pcie;
1378                 iwl_trans->shrd = shrd;
1379                 trans_pcie->trans = iwl_trans;
1380                 spin_lock_init(&iwl_trans->hcmd_lock);
1381         }
1382
1383         return iwl_trans;
1384 }
1385
1386 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1387                                       const char *msg)
1388 {
1389         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1390
1391         iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1392 }
1393
1394 #define IWL_FLUSH_WAIT_MS       2000
1395
1396 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1397 {
1398         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1399         struct iwl_tx_queue *txq;
1400         struct iwl_queue *q;
1401         int cnt;
1402         unsigned long now = jiffies;
1403         int ret = 0;
1404
1405         /* waiting for all the tx frames complete might take a while */
1406         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1407                 if (cnt == trans->shrd->cmd_queue)
1408                         continue;
1409                 txq = &trans_pcie->txq[cnt];
1410                 q = &txq->q;
1411                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1412                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1413                         msleep(1);
1414
1415                 if (q->read_ptr != q->write_ptr) {
1416                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1417                         ret = -ETIMEDOUT;
1418                         break;
1419                 }
1420         }
1421         return ret;
1422 }
1423
1424 /*
1425  * On every watchdog tick we check (latest) time stamp. If it does not
1426  * change during timeout period and queue is not empty we reset firmware.
1427  */
1428 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1429 {
1430         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1431         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1432         struct iwl_queue *q = &txq->q;
1433         unsigned long timeout;
1434
1435         if (q->read_ptr == q->write_ptr) {
1436                 txq->time_stamp = jiffies;
1437                 return 0;
1438         }
1439
1440         timeout = txq->time_stamp +
1441                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1442
1443         if (time_after(jiffies, timeout)) {
1444                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1445                         hw_params(trans).wd_timeout);
1446                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1447                         q->read_ptr, q->write_ptr);
1448                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1449                         iwl_read_prph(bus(trans), SCD_QUEUE_RDPTR(cnt))
1450                                 & (TFD_QUEUE_SIZE_MAX - 1),
1451                         iwl_read_prph(bus(trans), SCD_QUEUE_WRPTR(cnt)));
1452                 return 1;
1453         }
1454
1455         return 0;
1456 }
1457
1458 static const char *get_fh_string(int cmd)
1459 {
1460         switch (cmd) {
1461         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1462         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1463         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1464         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1465         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1466         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1467         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1468         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1469         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1470         default:
1471                 return "UNKNOWN";
1472         }
1473 }
1474
1475 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1476 {
1477         int i;
1478 #ifdef CONFIG_IWLWIFI_DEBUG
1479         int pos = 0;
1480         size_t bufsz = 0;
1481 #endif
1482         static const u32 fh_tbl[] = {
1483                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1484                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1485                 FH_RSCSR_CHNL0_WPTR,
1486                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1487                 FH_MEM_RSSR_SHARED_CTRL_REG,
1488                 FH_MEM_RSSR_RX_STATUS_REG,
1489                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1490                 FH_TSSR_TX_STATUS_REG,
1491                 FH_TSSR_TX_ERROR_REG
1492         };
1493 #ifdef CONFIG_IWLWIFI_DEBUG
1494         if (display) {
1495                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1496                 *buf = kmalloc(bufsz, GFP_KERNEL);
1497                 if (!*buf)
1498                         return -ENOMEM;
1499                 pos += scnprintf(*buf + pos, bufsz - pos,
1500                                 "FH register values:\n");
1501                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1502                         pos += scnprintf(*buf + pos, bufsz - pos,
1503                                 "  %34s: 0X%08x\n",
1504                                 get_fh_string(fh_tbl[i]),
1505                                 iwl_read_direct32(bus(trans), fh_tbl[i]));
1506                 }
1507                 return pos;
1508         }
1509 #endif
1510         IWL_ERR(trans, "FH register values:\n");
1511         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1512                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1513                         get_fh_string(fh_tbl[i]),
1514                         iwl_read_direct32(bus(trans), fh_tbl[i]));
1515         }
1516         return 0;
1517 }
1518
1519 static const char *get_csr_string(int cmd)
1520 {
1521         switch (cmd) {
1522         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1523         IWL_CMD(CSR_INT_COALESCING);
1524         IWL_CMD(CSR_INT);
1525         IWL_CMD(CSR_INT_MASK);
1526         IWL_CMD(CSR_FH_INT_STATUS);
1527         IWL_CMD(CSR_GPIO_IN);
1528         IWL_CMD(CSR_RESET);
1529         IWL_CMD(CSR_GP_CNTRL);
1530         IWL_CMD(CSR_HW_REV);
1531         IWL_CMD(CSR_EEPROM_REG);
1532         IWL_CMD(CSR_EEPROM_GP);
1533         IWL_CMD(CSR_OTP_GP_REG);
1534         IWL_CMD(CSR_GIO_REG);
1535         IWL_CMD(CSR_GP_UCODE_REG);
1536         IWL_CMD(CSR_GP_DRIVER_REG);
1537         IWL_CMD(CSR_UCODE_DRV_GP1);
1538         IWL_CMD(CSR_UCODE_DRV_GP2);
1539         IWL_CMD(CSR_LED_REG);
1540         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1541         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1542         IWL_CMD(CSR_ANA_PLL_CFG);
1543         IWL_CMD(CSR_HW_REV_WA_REG);
1544         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1545         default:
1546                 return "UNKNOWN";
1547         }
1548 }
1549
1550 void iwl_dump_csr(struct iwl_trans *trans)
1551 {
1552         int i;
1553         static const u32 csr_tbl[] = {
1554                 CSR_HW_IF_CONFIG_REG,
1555                 CSR_INT_COALESCING,
1556                 CSR_INT,
1557                 CSR_INT_MASK,
1558                 CSR_FH_INT_STATUS,
1559                 CSR_GPIO_IN,
1560                 CSR_RESET,
1561                 CSR_GP_CNTRL,
1562                 CSR_HW_REV,
1563                 CSR_EEPROM_REG,
1564                 CSR_EEPROM_GP,
1565                 CSR_OTP_GP_REG,
1566                 CSR_GIO_REG,
1567                 CSR_GP_UCODE_REG,
1568                 CSR_GP_DRIVER_REG,
1569                 CSR_UCODE_DRV_GP1,
1570                 CSR_UCODE_DRV_GP2,
1571                 CSR_LED_REG,
1572                 CSR_DRAM_INT_TBL_REG,
1573                 CSR_GIO_CHICKEN_BITS,
1574                 CSR_ANA_PLL_CFG,
1575                 CSR_HW_REV_WA_REG,
1576                 CSR_DBG_HPET_MEM_REG
1577         };
1578         IWL_ERR(trans, "CSR values:\n");
1579         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1580                 "CSR_INT_PERIODIC_REG)\n");
1581         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1582                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1583                         get_csr_string(csr_tbl[i]),
1584                         iwl_read32(bus(trans), csr_tbl[i]));
1585         }
1586 }
1587
1588 #ifdef CONFIG_IWLWIFI_DEBUGFS
1589 /* create and remove of files */
1590 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1591         if (!debugfs_create_file(#name, mode, parent, trans,            \
1592                                  &iwl_dbgfs_##name##_ops))              \
1593                 return -ENOMEM;                                         \
1594 } while (0)
1595
1596 /* file operation */
1597 #define DEBUGFS_READ_FUNC(name)                                         \
1598 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1599                                         char __user *user_buf,          \
1600                                         size_t count, loff_t *ppos);
1601
1602 #define DEBUGFS_WRITE_FUNC(name)                                        \
1603 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1604                                         const char __user *user_buf,    \
1605                                         size_t count, loff_t *ppos);
1606
1607
1608 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1609 {
1610         file->private_data = inode->i_private;
1611         return 0;
1612 }
1613
1614 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1615         DEBUGFS_READ_FUNC(name);                                        \
1616 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1617         .read = iwl_dbgfs_##name##_read,                                \
1618         .open = iwl_dbgfs_open_file_generic,                            \
1619         .llseek = generic_file_llseek,                                  \
1620 };
1621
1622 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1623         DEBUGFS_WRITE_FUNC(name);                                       \
1624 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1625         .write = iwl_dbgfs_##name##_write,                              \
1626         .open = iwl_dbgfs_open_file_generic,                            \
1627         .llseek = generic_file_llseek,                                  \
1628 };
1629
1630 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1631         DEBUGFS_READ_FUNC(name);                                        \
1632         DEBUGFS_WRITE_FUNC(name);                                       \
1633 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1634         .write = iwl_dbgfs_##name##_write,                              \
1635         .read = iwl_dbgfs_##name##_read,                                \
1636         .open = iwl_dbgfs_open_file_generic,                            \
1637         .llseek = generic_file_llseek,                                  \
1638 };
1639
1640 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1641                                                 char __user *user_buf,
1642                                                 size_t count, loff_t *ppos)
1643 {
1644         struct iwl_trans *trans = file->private_data;
1645         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1646         struct iwl_tx_queue *txq;
1647         struct iwl_queue *q;
1648         char *buf;
1649         int pos = 0;
1650         int cnt;
1651         int ret;
1652         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1653
1654         if (!trans_pcie->txq) {
1655                 IWL_ERR(trans, "txq not ready\n");
1656                 return -EAGAIN;
1657         }
1658         buf = kzalloc(bufsz, GFP_KERNEL);
1659         if (!buf)
1660                 return -ENOMEM;
1661
1662         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1663                 txq = &trans_pcie->txq[cnt];
1664                 q = &txq->q;
1665                 pos += scnprintf(buf + pos, bufsz - pos,
1666                                 "hwq %.2d: read=%u write=%u stop=%d"
1667                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1668                                 cnt, q->read_ptr, q->write_ptr,
1669                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1670                                 txq->swq_id, txq->swq_id & 3,
1671                                 (txq->swq_id >> 2) & 0x1f);
1672                 if (cnt >= 4)
1673                         continue;
1674                 /* for the ACs, display the stop count too */
1675                 pos += scnprintf(buf + pos, bufsz - pos,
1676                         "        stop-count: %d\n",
1677                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1678         }
1679         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1680         kfree(buf);
1681         return ret;
1682 }
1683
1684 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1685                                                 char __user *user_buf,
1686                                                 size_t count, loff_t *ppos) {
1687         struct iwl_trans *trans = file->private_data;
1688         struct iwl_trans_pcie *trans_pcie =
1689                 IWL_TRANS_GET_PCIE_TRANS(trans);
1690         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1691         char buf[256];
1692         int pos = 0;
1693         const size_t bufsz = sizeof(buf);
1694
1695         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1696                                                 rxq->read);
1697         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1698                                                 rxq->write);
1699         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1700                                                 rxq->free_count);
1701         if (rxq->rb_stts) {
1702                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1703                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1704         } else {
1705                 pos += scnprintf(buf + pos, bufsz - pos,
1706                                         "closed_rb_num: Not Allocated\n");
1707         }
1708         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1709 }
1710
1711 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1712                                          char __user *user_buf,
1713                                          size_t count, loff_t *ppos)
1714 {
1715         struct iwl_trans *trans = file->private_data;
1716         char *buf;
1717         int pos = 0;
1718         ssize_t ret = -ENOMEM;
1719
1720         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1721         if (buf) {
1722                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1723                 kfree(buf);
1724         }
1725         return ret;
1726 }
1727
1728 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1729                                         const char __user *user_buf,
1730                                         size_t count, loff_t *ppos)
1731 {
1732         struct iwl_trans *trans = file->private_data;
1733         u32 event_log_flag;
1734         char buf[8];
1735         int buf_size;
1736
1737         memset(buf, 0, sizeof(buf));
1738         buf_size = min(count, sizeof(buf) -  1);
1739         if (copy_from_user(buf, user_buf, buf_size))
1740                 return -EFAULT;
1741         if (sscanf(buf, "%d", &event_log_flag) != 1)
1742                 return -EFAULT;
1743         if (event_log_flag == 1)
1744                 iwl_dump_nic_event_log(trans, true, NULL, false);
1745
1746         return count;
1747 }
1748
1749 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1750                                         char __user *user_buf,
1751                                         size_t count, loff_t *ppos) {
1752
1753         struct iwl_trans *trans = file->private_data;
1754         struct iwl_trans_pcie *trans_pcie =
1755                 IWL_TRANS_GET_PCIE_TRANS(trans);
1756         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1757
1758         int pos = 0;
1759         char *buf;
1760         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1761         ssize_t ret;
1762
1763         buf = kzalloc(bufsz, GFP_KERNEL);
1764         if (!buf) {
1765                 IWL_ERR(trans, "Can not allocate Buffer\n");
1766                 return -ENOMEM;
1767         }
1768
1769         pos += scnprintf(buf + pos, bufsz - pos,
1770                         "Interrupt Statistics Report:\n");
1771
1772         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1773                 isr_stats->hw);
1774         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1775                 isr_stats->sw);
1776         if (isr_stats->sw || isr_stats->hw) {
1777                 pos += scnprintf(buf + pos, bufsz - pos,
1778                         "\tLast Restarting Code:  0x%X\n",
1779                         isr_stats->err_code);
1780         }
1781 #ifdef CONFIG_IWLWIFI_DEBUG
1782         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1783                 isr_stats->sch);
1784         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1785                 isr_stats->alive);
1786 #endif
1787         pos += scnprintf(buf + pos, bufsz - pos,
1788                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1789
1790         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1791                 isr_stats->ctkill);
1792
1793         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1794                 isr_stats->wakeup);
1795
1796         pos += scnprintf(buf + pos, bufsz - pos,
1797                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1798
1799         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1800                 isr_stats->tx);
1801
1802         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1803                 isr_stats->unhandled);
1804
1805         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1806         kfree(buf);
1807         return ret;
1808 }
1809
1810 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1811                                          const char __user *user_buf,
1812                                          size_t count, loff_t *ppos)
1813 {
1814         struct iwl_trans *trans = file->private_data;
1815         struct iwl_trans_pcie *trans_pcie =
1816                 IWL_TRANS_GET_PCIE_TRANS(trans);
1817         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1818
1819         char buf[8];
1820         int buf_size;
1821         u32 reset_flag;
1822
1823         memset(buf, 0, sizeof(buf));
1824         buf_size = min(count, sizeof(buf) -  1);
1825         if (copy_from_user(buf, user_buf, buf_size))
1826                 return -EFAULT;
1827         if (sscanf(buf, "%x", &reset_flag) != 1)
1828                 return -EFAULT;
1829         if (reset_flag == 0)
1830                 memset(isr_stats, 0, sizeof(*isr_stats));
1831
1832         return count;
1833 }
1834
1835 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1836                                          const char __user *user_buf,
1837                                          size_t count, loff_t *ppos)
1838 {
1839         struct iwl_trans *trans = file->private_data;
1840         char buf[8];
1841         int buf_size;
1842         int csr;
1843
1844         memset(buf, 0, sizeof(buf));
1845         buf_size = min(count, sizeof(buf) -  1);
1846         if (copy_from_user(buf, user_buf, buf_size))
1847                 return -EFAULT;
1848         if (sscanf(buf, "%d", &csr) != 1)
1849                 return -EFAULT;
1850
1851         iwl_dump_csr(trans);
1852
1853         return count;
1854 }
1855
1856 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1857                                          char __user *user_buf,
1858                                          size_t count, loff_t *ppos)
1859 {
1860         struct iwl_trans *trans = file->private_data;
1861         char *buf;
1862         int pos = 0;
1863         ssize_t ret = -EFAULT;
1864
1865         ret = pos = iwl_dump_fh(trans, &buf, true);
1866         if (buf) {
1867                 ret = simple_read_from_buffer(user_buf,
1868                                               count, ppos, buf, pos);
1869                 kfree(buf);
1870         }
1871
1872         return ret;
1873 }
1874
1875 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1876 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1877 DEBUGFS_READ_FILE_OPS(fh_reg);
1878 DEBUGFS_READ_FILE_OPS(rx_queue);
1879 DEBUGFS_READ_FILE_OPS(tx_queue);
1880 DEBUGFS_WRITE_FILE_OPS(csr);
1881
1882 /*
1883  * Create the debugfs files and directories
1884  *
1885  */
1886 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1887                                         struct dentry *dir)
1888 {
1889         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1890         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1891         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1892         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1893         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1894         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1895         return 0;
1896 }
1897 #else
1898 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1899                                         struct dentry *dir)
1900 { return 0; }
1901
1902 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1903
1904 const struct iwl_trans_ops trans_ops_pcie = {
1905         .alloc = iwl_trans_pcie_alloc,
1906         .request_irq = iwl_trans_pcie_request_irq,
1907         .start_device = iwl_trans_pcie_start_device,
1908         .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1909         .stop_device = iwl_trans_pcie_stop_device,
1910
1911         .tx_start = iwl_trans_pcie_tx_start,
1912         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1913
1914         .send_cmd = iwl_trans_pcie_send_cmd,
1915
1916         .tx = iwl_trans_pcie_tx,
1917         .reclaim = iwl_trans_pcie_reclaim,
1918
1919         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1920         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1921         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1922
1923         .kick_nic = iwl_trans_pcie_kick_nic,
1924
1925         .free = iwl_trans_pcie_free,
1926         .stop_queue = iwl_trans_pcie_stop_queue,
1927
1928         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1929
1930         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1931         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1932
1933 #ifdef CONFIG_PM_SLEEP
1934         .suspend = iwl_trans_pcie_suspend,
1935         .resume = iwl_trans_pcie_resume,
1936 #endif
1937 };