drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  20  * along with this program; if not, write to the Free Software
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  22  * USA
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  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  32  *
  33  * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
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  37  * modification, are permitted provided that the following conditions
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  41  *    notice, this list of conditions and the following disclaimer.
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  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/interrupt.h>
  64 #include <linux/debugfs.h>
  65 #include <linux/bitops.h>
  66 #include <linux/gfp.h>
  67
  68 #include "iwl-trans.h"
  69 #include "iwl-trans-pcie-int.h"
  70 #include "iwl-csr.h"
  71 #include "iwl-prph.h"
  72 #include "iwl-shared.h"
  73 #include "iwl-eeprom.h"
  74 #include "iwl-agn-hw.h"
  75
  76 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  77 {
  78         struct iwl_trans_pcie *trans_pcie =
  79                 IWL_TRANS_GET_PCIE_TRANS(trans);
  80         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  81         struct device *dev = bus(trans)->dev;
  82
  83         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  84
  85         spin_lock_init(&rxq->lock);
  86
  87         if (WARN_ON(rxq->bd || rxq->rb_stts))
  88                 return -EINVAL;
  89
  90         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  91         rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  92                                      &rxq->bd_dma, GFP_KERNEL);
  93         if (!rxq->bd)
  94                 goto err_bd;
  95         memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
  96
  97         /*Allocate the driver's pointer to receive buffer status */
  98         rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
  99                                           &rxq->rb_stts_dma, GFP_KERNEL);
 100         if (!rxq->rb_stts)
 101                 goto err_rb_stts;
 102         memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 103
 104         return 0;
 105
 106 err_rb_stts:
 107         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 108                         rxq->bd, rxq->bd_dma);
 109         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 110         rxq->bd = NULL;
 111 err_bd:
 112         return -ENOMEM;
 113 }
 114
 115 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 116 {
 117         struct iwl_trans_pcie *trans_pcie =
 118                 IWL_TRANS_GET_PCIE_TRANS(trans);
 119         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 120         int i;
 121
 122         /* Fill the rx_used queue with _all_ of the Rx buffers */
 123         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 124                 /* In the reset function, these buffers may have been allocated
 125                  * to an SKB, so we need to unmap and free potential storage */
 126                 if (rxq->pool[i].page != NULL) {
 127                         dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
 128                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 129                                 DMA_FROM_DEVICE);
 130                         __free_pages(rxq->pool[i].page,
 131                                      hw_params(trans).rx_page_order);
 132                         rxq->pool[i].page = NULL;
 133                 }
 134                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 135         }
 136 }
 137
 138 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 139                                  struct iwl_rx_queue *rxq)
 140 {
 141         u32 rb_size;
 142         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 143         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 144
 145         if (iwlagn_mod_params.amsdu_size_8K)
 146                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 147         else
 148                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 149
 150         /* Stop Rx DMA */
 151         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 152
 153         /* Reset driver's Rx queue write index */
 154         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 155
 156         /* Tell device where to find RBD circular buffer in DRAM */
 157         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 158                            (u32)(rxq->bd_dma >> 8));
 159
 160         /* Tell device where in DRAM to update its Rx status */
 161         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
 162                            rxq->rb_stts_dma >> 4);
 163
 164         /* Enable Rx DMA
 165          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 166          *      the credit mechanism in 5000 HW RX FIFO
 167          * Direct rx interrupts to hosts
 168          * Rx buffer size 4 or 8k
 169          * RB timeout 0x10
 170          * 256 RBDs
 171          */
 172         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
 173                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 174                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 175                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 176                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 177                            rb_size|
 178                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 179                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 180
 181         /* Set interrupt coalescing timer to default (2048 usecs) */
 182         iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 183 }
 184
 185 static int iwl_rx_init(struct iwl_trans *trans)
 186 {
 187         struct iwl_trans_pcie *trans_pcie =
 188                 IWL_TRANS_GET_PCIE_TRANS(trans);
 189         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 190
 191         int i, err;
 192         unsigned long flags;
 193
 194         if (!rxq->bd) {
 195                 err = iwl_trans_rx_alloc(trans);
 196                 if (err)
 197                         return err;
 198         }
 199
 200         spin_lock_irqsave(&rxq->lock, flags);
 201         INIT_LIST_HEAD(&rxq->rx_free);
 202         INIT_LIST_HEAD(&rxq->rx_used);
 203
 204         iwl_trans_rxq_free_rx_bufs(trans);
 205
 206         for (i = 0; i < RX_QUEUE_SIZE; i++)
 207                 rxq->queue[i] = NULL;
 208
 209         /* Set us so that we have processed and used all buffers, but have
 210          * not restocked the Rx queue with fresh buffers */
 211         rxq->read = rxq->write = 0;
 212         rxq->write_actual = 0;
 213         rxq->free_count = 0;
 214         spin_unlock_irqrestore(&rxq->lock, flags);
 215
 216         iwlagn_rx_replenish(trans);
 217
 218         iwl_trans_rx_hw_init(trans, rxq);
 219
 220         spin_lock_irqsave(&trans->shrd->lock, flags);
 221         rxq->need_update = 1;
 222         iwl_rx_queue_update_write_ptr(trans, rxq);
 223         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 224
 225         return 0;
 226 }
 227
 228 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 229 {
 230         struct iwl_trans_pcie *trans_pcie =
 231                 IWL_TRANS_GET_PCIE_TRANS(trans);
 232         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 233
 234         unsigned long flags;
 235
 236         /*if rxq->bd is NULL, it means that nothing has been allocated,
 237          * exit now */
 238         if (!rxq->bd) {
 239                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 240                 return;
 241         }
 242
 243         spin_lock_irqsave(&rxq->lock, flags);
 244         iwl_trans_rxq_free_rx_bufs(trans);
 245         spin_unlock_irqrestore(&rxq->lock, flags);
 246
 247         dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 248                           rxq->bd, rxq->bd_dma);
 249         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 250         rxq->bd = NULL;
 251
 252         if (rxq->rb_stts)
 253                 dma_free_coherent(bus(trans)->dev,
 254                                   sizeof(struct iwl_rb_status),
 255                                   rxq->rb_stts, rxq->rb_stts_dma);
 256         else
 257                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 258         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 259         rxq->rb_stts = NULL;
 260 }
 261
 262 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 263 {
 264
 265         /* stop Rx DMA */
 266         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 267         return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
 268                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 269 }
 270
 271 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 272                                     struct iwl_dma_ptr *ptr, size_t size)
 273 {
 274         if (WARN_ON(ptr->addr))
 275                 return -EINVAL;
 276
 277         ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
 278                                        &ptr->dma, GFP_KERNEL);
 279         if (!ptr->addr)
 280                 return -ENOMEM;
 281         ptr->size = size;
 282         return 0;
 283 }
 284
 285 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 286                                     struct iwl_dma_ptr *ptr)
 287 {
 288         if (unlikely(!ptr->addr))
 289                 return;
 290
 291         dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
 292         memset(ptr, 0, sizeof(*ptr));
 293 }
 294
 295 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 296                                 struct iwl_tx_queue *txq, int slots_num,
 297                                 u32 txq_id)
 298 {
 299         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 300         int i;
 301
 302         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 303                 return -EINVAL;
 304
 305         txq->q.n_window = slots_num;
 306
 307         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 308         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 309
 310         if (!txq->meta || !txq->cmd)
 311                 goto error;
 312
 313         if (txq_id == trans->shrd->cmd_queue)
 314                 for (i = 0; i < slots_num; i++) {
 315                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 316                                                 GFP_KERNEL);
 317                         if (!txq->cmd[i])
 318                                 goto error;
 319                 }
 320
 321         /* Alloc driver data array and TFD circular buffer */
 322         /* Driver private data, only for Tx (not command) queues,
 323          * not shared with device. */
 324         if (txq_id != trans->shrd->cmd_queue) {
 325                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 326                                     GFP_KERNEL);
 327                 if (!txq->skbs) {
 328                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 329                                   "structures failed\n");
 330                         goto error;
 331                 }
 332         } else {
 333                 txq->skbs = NULL;
 334         }
 335
 336         /* Circular buffer of transmit frame descriptors (TFDs),
 337          * shared with device */
 338         txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
 339                                        &txq->q.dma_addr, GFP_KERNEL);
 340         if (!txq->tfds) {
 341                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 342                 goto error;
 343         }
 344         txq->q.id = txq_id;
 345
 346         return 0;
 347 error:
 348         kfree(txq->skbs);
 349         txq->skbs = NULL;
 350         /* since txq->cmd has been zeroed,
 351          * all non allocated cmd[i] will be NULL */
 352         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 353                 for (i = 0; i < slots_num; i++)
 354                         kfree(txq->cmd[i]);
 355         kfree(txq->meta);
 356         kfree(txq->cmd);
 357         txq->meta = NULL;
 358         txq->cmd = NULL;
 359
 360         return -ENOMEM;
 361
 362 }
 363
 364 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 365                       int slots_num, u32 txq_id)
 366 {
 367         int ret;
 368
 369         txq->need_update = 0;
 370         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 371
 372         /*
 373          * For the default queues 0-3, set up the swq_id
 374          * already -- all others need to get one later
 375          * (if they need one at all).
 376          */
 377         if (txq_id < 4)
 378                 iwl_set_swq_id(txq, txq_id, txq_id);
 379
 380         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 381          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 382         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 383
 384         /* Initialize queue's high/low-water marks, and head/tail indexes */
 385         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 386                         txq_id);
 387         if (ret)
 388                 return ret;
 389
 390         /*
 391          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 392          * given Tx queue, and enable the DMA channel used for that queue.
 393          * Circular buffer (TFD queue in DRAM) physical base address */
 394         iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
 395                              txq->q.dma_addr >> 8);
 396
 397         return 0;
 398 }
 399
 400 /**
 401  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 402  */
 403 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 404 {
 405         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 406         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 407         struct iwl_queue *q = &txq->q;
 408         enum dma_data_direction dma_dir;
 409         unsigned long flags;
 410         spinlock_t *lock;
 411
 412         if (!q->n_bd)
 413                 return;
 414
 415         /* In the command queue, all the TBs are mapped as BIDI
 416          * so unmap them as such.
 417          */
 418         if (txq_id == trans->shrd->cmd_queue) {
 419                 dma_dir = DMA_BIDIRECTIONAL;
 420                 lock = &trans->hcmd_lock;
 421         } else {
 422                 dma_dir = DMA_TO_DEVICE;
 423                 lock = &trans->shrd->sta_lock;
 424         }
 425
 426         spin_lock_irqsave(lock, flags);
 427         while (q->write_ptr != q->read_ptr) {
 428                 /* The read_ptr needs to bound by q->n_window */
 429                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 430                                     dma_dir);
 431                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 432         }
 433         spin_unlock_irqrestore(lock, flags);
 434 }
 435
 436 /**
 437  * iwl_tx_queue_free - Deallocate DMA queue.
 438  * @txq: Transmit queue to deallocate.
 439  *
 440  * Empty queue by removing and destroying all BD's.
 441  * Free all buffers.
 442  * 0-fill, but do not free "txq" descriptor structure.
 443  */
 444 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 445 {
 446         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 447         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 448         struct device *dev = bus(trans)->dev;
 449         int i;
 450         if (WARN_ON(!txq))
 451                 return;
 452
 453         iwl_tx_queue_unmap(trans, txq_id);
 454
 455         /* De-alloc array of command/tx buffers */
 456
 457         if (txq_id == trans->shrd->cmd_queue)
 458                 for (i = 0; i < txq->q.n_window; i++)
 459                         kfree(txq->cmd[i]);
 460
 461         /* De-alloc circular buffer of TFDs */
 462         if (txq->q.n_bd) {
 463                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 464                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 465                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 466         }
 467
 468         /* De-alloc array of per-TFD driver data */
 469         kfree(txq->skbs);
 470         txq->skbs = NULL;
 471
 472         /* deallocate arrays */
 473         kfree(txq->cmd);
 474         kfree(txq->meta);
 475         txq->cmd = NULL;
 476         txq->meta = NULL;
 477
 478         /* 0-fill queue descriptor structure */
 479         memset(txq, 0, sizeof(*txq));
 480 }
 481
 482 /**
 483  * iwl_trans_tx_free - Free TXQ Context
 484  *
 485  * Destroy all TX DMA queues and structures
 486  */
 487 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 488 {
 489         int txq_id;
 490         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 491
 492         /* Tx queues */
 493         if (trans_pcie->txq) {
 494                 for (txq_id = 0;
 495                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 496                         iwl_tx_queue_free(trans, txq_id);
 497         }
 498
 499         kfree(trans_pcie->txq);
 500         trans_pcie->txq = NULL;
 501
 502         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 503
 504         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 505 }
 506
 507 /**
 508  * iwl_trans_tx_alloc - allocate TX context
 509  * Allocate all Tx DMA structures and initialize them
 510  *
 511  * @param priv
 512  * @return error code
 513  */
 514 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 515 {
 516         int ret;
 517         int txq_id, slots_num;
 518         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 519
 520         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 521                         sizeof(struct iwlagn_scd_bc_tbl);
 522
 523         /*It is not allowed to alloc twice, so warn when this happens.
 524          * We cannot rely on the previous allocation, so free and fail */
 525         if (WARN_ON(trans_pcie->txq)) {
 526                 ret = -EINVAL;
 527                 goto error;
 528         }
 529
 530         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 531                                    scd_bc_tbls_size);
 532         if (ret) {
 533                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 534                 goto error;
 535         }
 536
 537         /* Alloc keep-warm buffer */
 538         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 539         if (ret) {
 540                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 541                 goto error;
 542         }
 543
 544         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 545                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 546         if (!trans_pcie->txq) {
 547                 IWL_ERR(trans, "Not enough memory for txq\n");
 548                 ret = ENOMEM;
 549                 goto error;
 550         }
 551
 552         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 553         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 554                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 555                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 556                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 557                                           slots_num, txq_id);
 558                 if (ret) {
 559                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 560                         goto error;
 561                 }
 562         }
 563
 564         return 0;
 565
 566 error:
 567         iwl_trans_pcie_tx_free(trans);
 568
 569         return ret;
 570 }
 571 static int iwl_tx_init(struct iwl_trans *trans)
 572 {
 573         int ret;
 574         int txq_id, slots_num;
 575         unsigned long flags;
 576         bool alloc = false;
 577         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 578
 579         if (!trans_pcie->txq) {
 580                 ret = iwl_trans_tx_alloc(trans);
 581                 if (ret)
 582                         goto error;
 583                 alloc = true;
 584         }
 585
 586         spin_lock_irqsave(&trans->shrd->lock, flags);
 587
 588         /* Turn off all Tx DMA fifos */
 589         iwl_write_prph(bus(trans), SCD_TXFACT, 0);
 590
 591         /* Tell NIC where to find the "keep warm" buffer */
 592         iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
 593                            trans_pcie->kw.dma >> 4);
 594
 595         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 596
 597         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 598         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 599                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 600                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 601                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 602                                          slots_num, txq_id);
 603                 if (ret) {
 604                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 605                         goto error;
 606                 }
 607         }
 608
 609         return 0;
 610 error:
 611         /*Upon error, free only if we allocated something */
 612         if (alloc)
 613                 iwl_trans_pcie_tx_free(trans);
 614         return ret;
 615 }
 616
 617 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 618 {
 619 /*
 620  * (for documentation purposes)
 621  * to set power to V_AUX, do:
 622
 623                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 624                         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 625                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 626                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 627  */
 628
 629         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 630                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 631                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 632 }
 633
 634 static int iwl_nic_init(struct iwl_trans *trans)
 635 {
 636         unsigned long flags;
 637
 638         /* nic_init */
 639         spin_lock_irqsave(&trans->shrd->lock, flags);
 640         iwl_apm_init(priv(trans));
 641
 642         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 643         iwl_write8(bus(trans), CSR_INT_COALESCING,
 644                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 645
 646         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 647
 648         iwl_set_pwr_vmain(trans);
 649
 650         iwl_nic_config(priv(trans));
 651
 652         /* Allocate the RX queue, or reset if it is already allocated */
 653         iwl_rx_init(trans);
 654
 655         /* Allocate or reset and init all Tx and Command queues */
 656         if (iwl_tx_init(trans))
 657                 return -ENOMEM;
 658
 659         if (hw_params(trans).shadow_reg_enable) {
 660                 /* enable shadow regs in HW */
 661                 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
 662                         0x800FFFFF);
 663         }
 664
 665         set_bit(STATUS_INIT, &trans->shrd->status);
 666
 667         return 0;
 668 }
 669
 670 #define HW_READY_TIMEOUT (50)
 671
 672 /* Note: returns poll_bit return value, which is >= 0 if success */
 673 static int iwl_set_hw_ready(struct iwl_trans *trans)
 674 {
 675         int ret;
 676
 677         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 678                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 679
 680         /* See if we got it */
 681         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 682                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 683                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 684                                 HW_READY_TIMEOUT);
 685
 686         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 687         return ret;
 688 }
 689
 690 /* Note: returns standard 0/-ERROR code */
 691 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
 692 {
 693         int ret;
 694
 695         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 696
 697         ret = iwl_set_hw_ready(trans);
 698         if (ret >= 0)
 699                 return 0;
 700
 701         /* If HW is not ready, prepare the conditions to check again */
 702         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 703                         CSR_HW_IF_CONFIG_REG_PREPARE);
 704
 705         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 706                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 707                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 708
 709         if (ret < 0)
 710                 return ret;
 711
 712         /* HW should be ready by now, check again. */
 713         ret = iwl_set_hw_ready(trans);
 714         if (ret >= 0)
 715                 return 0;
 716         return ret;
 717 }
 718
 719 #define IWL_AC_UNSET -1
 720
 721 struct queue_to_fifo_ac {
 722         s8 fifo, ac;
 723 };
 724
 725 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 726         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 727         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 728         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 729         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 730         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 731         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 732         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 733         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 734         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 735         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 736         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 737 };
 738
 739 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 740         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 741         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 742         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 743         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 744         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 745         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 746         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 747         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 748         { IWL_TX_FIFO_BE_IPAN, 2, },
 749         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 750         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 751 };
 752
 753 static const u8 iwlagn_bss_ac_to_fifo[] = {
 754         IWL_TX_FIFO_VO,
 755         IWL_TX_FIFO_VI,
 756         IWL_TX_FIFO_BE,
 757         IWL_TX_FIFO_BK,
 758 };
 759 static const u8 iwlagn_bss_ac_to_queue[] = {
 760         0, 1, 2, 3,
 761 };
 762 static const u8 iwlagn_pan_ac_to_fifo[] = {
 763         IWL_TX_FIFO_VO_IPAN,
 764         IWL_TX_FIFO_VI_IPAN,
 765         IWL_TX_FIFO_BE_IPAN,
 766         IWL_TX_FIFO_BK_IPAN,
 767 };
 768 static const u8 iwlagn_pan_ac_to_queue[] = {
 769         7, 6, 5, 4,
 770 };
 771
 772 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
 773 {
 774         int ret;
 775         struct iwl_trans_pcie *trans_pcie =
 776                 IWL_TRANS_GET_PCIE_TRANS(trans);
 777
 778         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
 779         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
 780         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
 781
 782         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
 783         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
 784
 785         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
 786         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
 787
 788         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
 789              iwl_trans_pcie_prepare_card_hw(trans)) {
 790                 IWL_WARN(trans, "Exit HW not ready\n");
 791                 return -EIO;
 792         }
 793
 794         /* If platform's RF_KILL switch is NOT set to KILL */
 795         if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
 796                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
 797                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 798         else
 799                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 800
 801         if (iwl_is_rfkill(trans->shrd)) {
 802                 iwl_set_hw_rfkill_state(priv(trans), true);
 803                 iwl_enable_interrupts(trans);
 804                 return -ERFKILL;
 805         }
 806
 807         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 808
 809         ret = iwl_nic_init(trans);
 810         if (ret) {
 811                 IWL_ERR(trans, "Unable to init nic\n");
 812                 return ret;
 813         }
 814
 815         /* make sure rfkill handshake bits are cleared */
 816         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 817         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
 818                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 819
 820         /* clear (again), then enable host interrupts */
 821         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 822         iwl_enable_interrupts(trans);
 823
 824         /* really make sure rfkill handshake bits are cleared */
 825         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 826         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 827
 828         return 0;
 829 }
 830
 831 /*
 832  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 833  * must be called under priv->shrd->lock and mac access
 834  */
 835 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
 836 {
 837         iwl_write_prph(bus(trans), SCD_TXFACT, mask);
 838 }
 839
 840 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
 841 {
 842         const struct queue_to_fifo_ac *queue_to_fifo;
 843         struct iwl_trans_pcie *trans_pcie =
 844                 IWL_TRANS_GET_PCIE_TRANS(trans);
 845         u32 a;
 846         unsigned long flags;
 847         int i, chan;
 848         u32 reg_val;
 849
 850         spin_lock_irqsave(&trans->shrd->lock, flags);
 851
 852         trans_pcie->scd_base_addr =
 853                 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
 854         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
 855         /* reset conext data memory */
 856         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
 857                 a += 4)
 858                 iwl_write_targ_mem(bus(trans), a, 0);
 859         /* reset tx status memory */
 860         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
 861                 a += 4)
 862                 iwl_write_targ_mem(bus(trans), a, 0);
 863         for (; a < trans_pcie->scd_base_addr +
 864                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
 865                a += 4)
 866                 iwl_write_targ_mem(bus(trans), a, 0);
 867
 868         iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
 869                        trans_pcie->scd_bc_tbls.dma >> 10);
 870
 871         /* Enable DMA channel */
 872         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
 873                 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 874                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 875                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 876
 877         /* Update FH chicken bits */
 878         reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
 879         iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
 880                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 881
 882         iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
 883                 SCD_QUEUECHAIN_SEL_ALL(trans));
 884         iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
 885
 886         /* initiate the queues */
 887         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
 888                 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
 889                 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
 890                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 891                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 892                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 893                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
 894                                 sizeof(u32),
 895                                 ((SCD_WIN_SIZE <<
 896                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 897                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 898                                 ((SCD_FRAME_LIMIT <<
 899                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 900                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 901         }
 902
 903         iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
 904                         IWL_MASK(0, hw_params(trans).max_txq_num));
 905
 906         /* Activate all Tx DMA/FIFO channels */
 907         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
 908
 909         /* map queues to FIFOs */
 910         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
 911                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
 912         else
 913                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
 914
 915         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
 916
 917         /* make sure all queue are not stopped */
 918         memset(&trans_pcie->queue_stopped[0], 0,
 919                 sizeof(trans_pcie->queue_stopped));
 920         for (i = 0; i < 4; i++)
 921                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
 922
 923         /* reset to 0 to enable all the queue first */
 924         trans_pcie->txq_ctx_active_msk = 0;
 925
 926         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
 927                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 928         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
 929                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 930
 931         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
 932                 int fifo = queue_to_fifo[i].fifo;
 933                 int ac = queue_to_fifo[i].ac;
 934
 935                 iwl_txq_ctx_activate(trans_pcie, i);
 936
 937                 if (fifo == IWL_TX_FIFO_UNUSED)
 938                         continue;
 939
 940                 if (ac != IWL_AC_UNSET)
 941                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
 942                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
 943                                               fifo, 0);
 944         }
 945
 946         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 947
 948         /* Enable L1-Active */
 949         iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
 950                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 951 }
 952
 953 /**
 954  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
 955  */
 956 static int iwl_trans_tx_stop(struct iwl_trans *trans)
 957 {
 958         int ch, txq_id;
 959         unsigned long flags;
 960         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 961
 962         /* Turn off all Tx DMA fifos */
 963         spin_lock_irqsave(&trans->shrd->lock, flags);
 964
 965         iwl_trans_txq_set_sched(trans, 0);
 966
 967         /* Stop each Tx DMA channel, and wait for it to be idle */
 968         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 969                 iwl_write_direct32(bus(trans),
 970                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 971                 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
 972                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
 973                                     1000))
 974                         IWL_ERR(trans, "Failing on timeout while stopping"
 975                             " DMA channel %d [0x%08x]", ch,
 976                             iwl_read_direct32(bus(trans),
 977                                               FH_TSSR_TX_STATUS_REG));
 978         }
 979         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 980
 981         if (!trans_pcie->txq) {
 982                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
 983                 return 0;
 984         }
 985
 986         /* Unmap DMA from host system and free skb's */
 987         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
 988                 iwl_tx_queue_unmap(trans, txq_id);
 989
 990         return 0;
 991 }
 992
 993 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 994 {
 995         unsigned long flags;
 996         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 997
 998         /* tell the device to stop sending interrupts */
 999         spin_lock_irqsave(&trans->shrd->lock, flags);
1000         iwl_disable_interrupts(trans);
1001         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1002
1003         /* device going down, Stop using ICT table */
1004         iwl_disable_ict(trans);
1005
1006         /*
1007          * If a HW restart happens during firmware loading,
1008          * then the firmware loading might call this function
1009          * and later it might be called again due to the
1010          * restart. So don't process again if the device is
1011          * already dead.
1012          */
1013         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1014                 iwl_trans_tx_stop(trans);
1015                 iwl_trans_rx_stop(trans);
1016
1017                 /* Power-down device's busmaster DMA clocks */
1018                 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1019                                APMG_CLK_VAL_DMA_CLK_RQT);
1020                 udelay(5);
1021         }
1022
1023         /* Make sure (redundant) we've released our request to stay awake */
1024         iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1025                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1026
1027         /* Stop the device, and put it in low power state */
1028         iwl_apm_stop(priv(trans));
1029
1030         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1031          * Clean again the interrupt here
1032          */
1033         spin_lock_irqsave(&trans->shrd->lock, flags);
1034         iwl_disable_interrupts(trans);
1035         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1036
1037         /* wait to make sure we flush pending tasklet*/
1038         synchronize_irq(bus(trans)->irq);
1039         tasklet_kill(&trans_pcie->irq_tasklet);
1040
1041         /* stop and reset the on-board processor */
1042         iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1043 }
1044
1045 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1046                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1047                 u8 sta_id, u8 tid)
1048 {
1049         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1050         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1051         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1052         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1053         struct iwl_cmd_meta *out_meta;
1054         struct iwl_tx_queue *txq;
1055         struct iwl_queue *q;
1056
1057         dma_addr_t phys_addr = 0;
1058         dma_addr_t txcmd_phys;
1059         dma_addr_t scratch_phys;
1060         u16 len, firstlen, secondlen;
1061         u8 wait_write_ptr = 0;
1062         u8 txq_id;
1063         bool is_agg = false;
1064         __le16 fc = hdr->frame_control;
1065         u8 hdr_len = ieee80211_hdrlen(fc);
1066         u16 __maybe_unused wifi_seq;
1067
1068         /*
1069          * Send this frame after DTIM -- there's a special queue
1070          * reserved for this for contexts that support AP mode.
1071          */
1072         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1073                 txq_id = trans_pcie->mcast_queue[ctx];
1074
1075                 /*
1076                  * The microcode will clear the more data
1077                  * bit in the last frame it transmits.
1078                  */
1079                 hdr->frame_control |=
1080                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1081         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1082                 txq_id = IWL_AUX_QUEUE;
1083         else
1084                 txq_id =
1085                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1086
1087         /* aggregation is on for this <sta,tid> */
1088         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1089                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1090                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1091                 is_agg = true;
1092         }
1093
1094         txq = &trans_pcie->txq[txq_id];
1095         q = &txq->q;
1096
1097         /* In AGG mode, the index in the ring must correspond to the WiFi
1098          * sequence number. This is a HW requirements to help the SCD to parse
1099          * the BA.
1100          * Check here that the packets are in the right place on the ring.
1101          */
1102 #ifdef CONFIG_IWLWIFI_DEBUG
1103         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1104         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1105                   "Q: %d WiFi Seq %d tfdNum %d",
1106                   txq_id, wifi_seq, q->write_ptr);
1107 #endif
1108
1109         /* Set up driver data for this TFD */
1110         txq->skbs[q->write_ptr] = skb;
1111         txq->cmd[q->write_ptr] = dev_cmd;
1112
1113         dev_cmd->hdr.cmd = REPLY_TX;
1114         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1115                                 INDEX_TO_SEQ(q->write_ptr)));
1116
1117         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1118         out_meta = &txq->meta[q->write_ptr];
1119
1120         /*
1121          * Use the first empty entry in this queue's command buffer array
1122          * to contain the Tx command and MAC header concatenated together
1123          * (payload data will be in another buffer).
1124          * Size of this varies, due to varying MAC header length.
1125          * If end is not dword aligned, we'll have 2 extra bytes at the end
1126          * of the MAC header (device reads on dword boundaries).
1127          * We'll tell device about this padding later.
1128          */
1129         len = sizeof(struct iwl_tx_cmd) +
1130                 sizeof(struct iwl_cmd_header) + hdr_len;
1131         firstlen = (len + 3) & ~3;
1132
1133         /* Tell NIC about any 2-byte padding after MAC header */
1134         if (firstlen != len)
1135                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1136
1137         /* Physical address of this Tx command's header (not MAC header!),
1138          * within command buffer array. */
1139         txcmd_phys = dma_map_single(bus(trans)->dev,
1140                                     &dev_cmd->hdr, firstlen,
1141                                     DMA_BIDIRECTIONAL);
1142         if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1143                 return -1;
1144         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1145         dma_unmap_len_set(out_meta, len, firstlen);
1146
1147         if (!ieee80211_has_morefrags(fc)) {
1148                 txq->need_update = 1;
1149         } else {
1150                 wait_write_ptr = 1;
1151                 txq->need_update = 0;
1152         }
1153
1154         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1155          * if any (802.11 null frames have no payload). */
1156         secondlen = skb->len - hdr_len;
1157         if (secondlen > 0) {
1158                 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1159                                            secondlen, DMA_TO_DEVICE);
1160                 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1161                         dma_unmap_single(bus(trans)->dev,
1162                                          dma_unmap_addr(out_meta, mapping),
1163                                          dma_unmap_len(out_meta, len),
1164                                          DMA_BIDIRECTIONAL);
1165                         return -1;
1166                 }
1167         }
1168
1169         /* Attach buffers to TFD */
1170         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1171         if (secondlen > 0)
1172                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1173                                              secondlen, 0);
1174
1175         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1176                                 offsetof(struct iwl_tx_cmd, scratch);
1177
1178         /* take back ownership of DMA buffer to enable update */
1179         dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1180                         DMA_BIDIRECTIONAL);
1181         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1182         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1183
1184         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1185                      le16_to_cpu(dev_cmd->hdr.sequence));
1186         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1187         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1188         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1189
1190         /* Set up entry for this TFD in Tx byte-count array */
1191         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1192
1193         dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1194                         DMA_BIDIRECTIONAL);
1195
1196         trace_iwlwifi_dev_tx(priv(trans),
1197                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1198                              sizeof(struct iwl_tfd),
1199                              &dev_cmd->hdr, firstlen,
1200                              skb->data + hdr_len, secondlen);
1201
1202         /* Tell device the write index *just past* this latest filled TFD */
1203         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1204         iwl_txq_update_write_ptr(trans, txq);
1205
1206         /*
1207          * At this point the frame is "transmitted" successfully
1208          * and we will get a TX status notification eventually,
1209          * regardless of the value of ret. "ret" only indicates
1210          * whether or not we should update the write pointer.
1211          */
1212         if (iwl_queue_space(q) < q->high_mark) {
1213                 if (wait_write_ptr) {
1214                         txq->need_update = 1;
1215                         iwl_txq_update_write_ptr(trans, txq);
1216                 } else {
1217                         iwl_stop_queue(trans, txq, "Queue is full");
1218                 }
1219         }
1220         return 0;
1221 }
1222
1223 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1224 {
1225         /* Remove all resets to allow NIC to operate */
1226         iwl_write32(bus(trans), CSR_RESET, 0);
1227 }
1228
1229 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1230 {
1231         struct iwl_trans_pcie *trans_pcie =
1232                 IWL_TRANS_GET_PCIE_TRANS(trans);
1233         int err;
1234
1235         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1236
1237         tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1238                 iwl_irq_tasklet, (unsigned long)trans);
1239
1240         iwl_alloc_isr_ict(trans);
1241
1242         err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1243                 DRV_NAME, trans);
1244         if (err) {
1245                 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1246                 iwl_free_isr_ict(trans);
1247                 return err;
1248         }
1249
1250         INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1251         return 0;
1252 }
1253
1254 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1255                       int txq_id, int ssn, u32 status,
1256                       struct sk_buff_head *skbs)
1257 {
1258         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1259         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1260         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1261         int tfd_num = ssn & (txq->q.n_bd - 1);
1262         int freed = 0;
1263
1264         txq->time_stamp = jiffies;
1265
1266         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1267                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1268                 /*
1269                  * FIXME: this is a uCode bug which need to be addressed,
1270                  * log the information and return for now.
1271                  * Since it is can possibly happen very often and in order
1272                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1273                  */
1274                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1275                         "agg_txq[sta_id[tid] %d", txq_id,
1276                         trans_pcie->agg_txq[sta_id][tid]);
1277                 return 1;
1278         }
1279
1280         if (txq->q.read_ptr != tfd_num) {
1281                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1282                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1283                                 tfd_num, ssn);
1284                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1285                 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1286                    (!txq->sched_retry ||
1287                    status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1288                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1289         }
1290         return 0;
1291 }
1292
1293 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1294 {
1295         iwl_calib_free_results(trans);
1296         iwl_trans_pcie_tx_free(trans);
1297         iwl_trans_pcie_rx_free(trans);
1298         free_irq(bus(trans)->irq, trans);
1299         iwl_free_isr_ict(trans);
1300         trans->shrd->trans = NULL;
1301         kfree(trans);
1302 }
1303
1304 #ifdef CONFIG_PM_SLEEP
1305 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1306 {
1307         /*
1308          * This function is called when system goes into suspend state
1309          * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1310          * function first but since iwlagn_mac_stop() has no knowledge of
1311          * who the caller is,
1312          * it will not call apm_ops.stop() to stop the DMA operation.
1313          * Calling apm_ops.stop here to make sure we stop the DMA.
1314          *
1315          * But of course ... if we have configured WoWLAN then we did other
1316          * things already :-)
1317          */
1318         if (!trans->shrd->wowlan) {
1319                 iwl_apm_stop(priv(trans));
1320         } else {
1321                 iwl_disable_interrupts(trans);
1322                 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1323                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1324         }
1325
1326         return 0;
1327 }
1328
1329 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1330 {
1331         bool hw_rfkill = false;
1332
1333         iwl_enable_interrupts(trans);
1334
1335         if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1336                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1337                 hw_rfkill = true;
1338
1339         if (hw_rfkill)
1340                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1341         else
1342                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1343
1344         iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1345
1346         return 0;
1347 }
1348 #endif /* CONFIG_PM_SLEEP */
1349
1350 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1351                                           enum iwl_rxon_context_id ctx,
1352                                           const char *msg)
1353 {
1354         u8 ac, txq_id;
1355         struct iwl_trans_pcie *trans_pcie =
1356                 IWL_TRANS_GET_PCIE_TRANS(trans);
1357
1358         for (ac = 0; ac < AC_NUM; ac++) {
1359                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1360                 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1361                         ac,
1362                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1363                               ? "stopped" : "awake");
1364                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1365         }
1366 }
1367
1368 const struct iwl_trans_ops trans_ops_pcie;
1369
1370 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1371 {
1372         struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1373                                               sizeof(struct iwl_trans_pcie),
1374                                               GFP_KERNEL);
1375         if (iwl_trans) {
1376                 struct iwl_trans_pcie *trans_pcie =
1377                         IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1378                 iwl_trans->ops = &trans_ops_pcie;
1379                 iwl_trans->shrd = shrd;
1380                 trans_pcie->trans = iwl_trans;
1381                 spin_lock_init(&iwl_trans->hcmd_lock);
1382         }
1383
1384         return iwl_trans;
1385 }
1386
1387 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1388                                       const char *msg)
1389 {
1390         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1391
1392         iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1393 }
1394
1395 #define IWL_FLUSH_WAIT_MS       2000
1396
1397 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1398 {
1399         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1400         struct iwl_tx_queue *txq;
1401         struct iwl_queue *q;
1402         int cnt;
1403         unsigned long now = jiffies;
1404         int ret = 0;
1405
1406         /* waiting for all the tx frames complete might take a while */
1407         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1408                 if (cnt == trans->shrd->cmd_queue)
1409                         continue;
1410                 txq = &trans_pcie->txq[cnt];
1411                 q = &txq->q;
1412                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1413                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1414                         msleep(1);
1415
1416                 if (q->read_ptr != q->write_ptr) {
1417                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1418                         ret = -ETIMEDOUT;
1419                         break;
1420                 }
1421         }
1422         return ret;
1423 }
1424
1425 /*
1426  * On every watchdog tick we check (latest) time stamp. If it does not
1427  * change during timeout period and queue is not empty we reset firmware.
1428  */
1429 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1430 {
1431         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1432         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1433         struct iwl_queue *q = &txq->q;
1434         unsigned long timeout;
1435
1436         if (q->read_ptr == q->write_ptr) {
1437                 txq->time_stamp = jiffies;
1438                 return 0;
1439         }
1440
1441         timeout = txq->time_stamp +
1442                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1443
1444         if (time_after(jiffies, timeout)) {
1445                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1446                         hw_params(trans).wd_timeout);
1447                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1448                         q->read_ptr, q->write_ptr);
1449                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1450                         iwl_read_prph(bus(trans), SCD_QUEUE_RDPTR(cnt))
1451                                 & (TFD_QUEUE_SIZE_MAX - 1),
1452                         iwl_read_prph(bus(trans), SCD_QUEUE_WRPTR(cnt)));
1453                 return 1;
1454         }
1455
1456         return 0;
1457 }
1458
1459 static const char *get_fh_string(int cmd)
1460 {
1461         switch (cmd) {
1462         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1463         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1464         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1465         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1466         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1467         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1468         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1469         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1470         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1471         default:
1472                 return "UNKNOWN";
1473         }
1474 }
1475
1476 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1477 {
1478         int i;
1479 #ifdef CONFIG_IWLWIFI_DEBUG
1480         int pos = 0;
1481         size_t bufsz = 0;
1482 #endif
1483         static const u32 fh_tbl[] = {
1484                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1485                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1486                 FH_RSCSR_CHNL0_WPTR,
1487                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1488                 FH_MEM_RSSR_SHARED_CTRL_REG,
1489                 FH_MEM_RSSR_RX_STATUS_REG,
1490                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1491                 FH_TSSR_TX_STATUS_REG,
1492                 FH_TSSR_TX_ERROR_REG
1493         };
1494 #ifdef CONFIG_IWLWIFI_DEBUG
1495         if (display) {
1496                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1497                 *buf = kmalloc(bufsz, GFP_KERNEL);
1498                 if (!*buf)
1499                         return -ENOMEM;
1500                 pos += scnprintf(*buf + pos, bufsz - pos,
1501                                 "FH register values:\n");
1502                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1503                         pos += scnprintf(*buf + pos, bufsz - pos,
1504                                 "  %34s: 0X%08x\n",
1505                                 get_fh_string(fh_tbl[i]),
1506                                 iwl_read_direct32(bus(trans), fh_tbl[i]));
1507                 }
1508                 return pos;
1509         }
1510 #endif
1511         IWL_ERR(trans, "FH register values:\n");
1512         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1513                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1514                         get_fh_string(fh_tbl[i]),
1515                         iwl_read_direct32(bus(trans), fh_tbl[i]));
1516         }
1517         return 0;
1518 }
1519
1520 static const char *get_csr_string(int cmd)
1521 {
1522         switch (cmd) {
1523         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1524         IWL_CMD(CSR_INT_COALESCING);
1525         IWL_CMD(CSR_INT);
1526         IWL_CMD(CSR_INT_MASK);
1527         IWL_CMD(CSR_FH_INT_STATUS);
1528         IWL_CMD(CSR_GPIO_IN);
1529         IWL_CMD(CSR_RESET);
1530         IWL_CMD(CSR_GP_CNTRL);
1531         IWL_CMD(CSR_HW_REV);
1532         IWL_CMD(CSR_EEPROM_REG);
1533         IWL_CMD(CSR_EEPROM_GP);
1534         IWL_CMD(CSR_OTP_GP_REG);
1535         IWL_CMD(CSR_GIO_REG);
1536         IWL_CMD(CSR_GP_UCODE_REG);
1537         IWL_CMD(CSR_GP_DRIVER_REG);
1538         IWL_CMD(CSR_UCODE_DRV_GP1);
1539         IWL_CMD(CSR_UCODE_DRV_GP2);
1540         IWL_CMD(CSR_LED_REG);
1541         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1542         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1543         IWL_CMD(CSR_ANA_PLL_CFG);
1544         IWL_CMD(CSR_HW_REV_WA_REG);
1545         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1546         default:
1547                 return "UNKNOWN";
1548         }
1549 }
1550
1551 void iwl_dump_csr(struct iwl_trans *trans)
1552 {
1553         int i;
1554         static const u32 csr_tbl[] = {
1555                 CSR_HW_IF_CONFIG_REG,
1556                 CSR_INT_COALESCING,
1557                 CSR_INT,
1558                 CSR_INT_MASK,
1559                 CSR_FH_INT_STATUS,
1560                 CSR_GPIO_IN,
1561                 CSR_RESET,
1562                 CSR_GP_CNTRL,
1563                 CSR_HW_REV,
1564                 CSR_EEPROM_REG,
1565                 CSR_EEPROM_GP,
1566                 CSR_OTP_GP_REG,
1567                 CSR_GIO_REG,
1568                 CSR_GP_UCODE_REG,
1569                 CSR_GP_DRIVER_REG,
1570                 CSR_UCODE_DRV_GP1,
1571                 CSR_UCODE_DRV_GP2,
1572                 CSR_LED_REG,
1573                 CSR_DRAM_INT_TBL_REG,
1574                 CSR_GIO_CHICKEN_BITS,
1575                 CSR_ANA_PLL_CFG,
1576                 CSR_HW_REV_WA_REG,
1577                 CSR_DBG_HPET_MEM_REG
1578         };
1579         IWL_ERR(trans, "CSR values:\n");
1580         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1581                 "CSR_INT_PERIODIC_REG)\n");
1582         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1583                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1584                         get_csr_string(csr_tbl[i]),
1585                         iwl_read32(bus(trans), csr_tbl[i]));
1586         }
1587 }
1588
1589 #ifdef CONFIG_IWLWIFI_DEBUGFS
1590 /* create and remove of files */
1591 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1592         if (!debugfs_create_file(#name, mode, parent, trans,            \
1593                                  &iwl_dbgfs_##name##_ops))              \
1594                 return -ENOMEM;                                         \
1595 } while (0)
1596
1597 /* file operation */
1598 #define DEBUGFS_READ_FUNC(name)                                         \
1599 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1600                                         char __user *user_buf,          \
1601                                         size_t count, loff_t *ppos);
1602
1603 #define DEBUGFS_WRITE_FUNC(name)                                        \
1604 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1605                                         const char __user *user_buf,    \
1606                                         size_t count, loff_t *ppos);
1607
1608
1609 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1610 {
1611         file->private_data = inode->i_private;
1612         return 0;
1613 }
1614
1615 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1616         DEBUGFS_READ_FUNC(name);                                        \
1617 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1618         .read = iwl_dbgfs_##name##_read,                                \
1619         .open = iwl_dbgfs_open_file_generic,                            \
1620         .llseek = generic_file_llseek,                                  \
1621 };
1622
1623 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1624         DEBUGFS_WRITE_FUNC(name);                                       \
1625 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1626         .write = iwl_dbgfs_##name##_write,                              \
1627         .open = iwl_dbgfs_open_file_generic,                            \
1628         .llseek = generic_file_llseek,                                  \
1629 };
1630
1631 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1632         DEBUGFS_READ_FUNC(name);                                        \
1633         DEBUGFS_WRITE_FUNC(name);                                       \
1634 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1635         .write = iwl_dbgfs_##name##_write,                              \
1636         .read = iwl_dbgfs_##name##_read,                                \
1637         .open = iwl_dbgfs_open_file_generic,                            \
1638         .llseek = generic_file_llseek,                                  \
1639 };
1640
1641 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1642                                                 char __user *user_buf,
1643                                                 size_t count, loff_t *ppos)
1644 {
1645         struct iwl_trans *trans = file->private_data;
1646         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1647         struct iwl_tx_queue *txq;
1648         struct iwl_queue *q;
1649         char *buf;
1650         int pos = 0;
1651         int cnt;
1652         int ret;
1653         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1654
1655         if (!trans_pcie->txq) {
1656                 IWL_ERR(trans, "txq not ready\n");
1657                 return -EAGAIN;
1658         }
1659         buf = kzalloc(bufsz, GFP_KERNEL);
1660         if (!buf)
1661                 return -ENOMEM;
1662
1663         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1664                 txq = &trans_pcie->txq[cnt];
1665                 q = &txq->q;
1666                 pos += scnprintf(buf + pos, bufsz - pos,
1667                                 "hwq %.2d: read=%u write=%u stop=%d"
1668                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1669                                 cnt, q->read_ptr, q->write_ptr,
1670                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1671                                 txq->swq_id, txq->swq_id & 3,
1672                                 (txq->swq_id >> 2) & 0x1f);
1673                 if (cnt >= 4)
1674                         continue;
1675                 /* for the ACs, display the stop count too */
1676                 pos += scnprintf(buf + pos, bufsz - pos,
1677                         "        stop-count: %d\n",
1678                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1679         }
1680         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1681         kfree(buf);
1682         return ret;
1683 }
1684
1685 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1686                                                 char __user *user_buf,
1687                                                 size_t count, loff_t *ppos) {
1688         struct iwl_trans *trans = file->private_data;
1689         struct iwl_trans_pcie *trans_pcie =
1690                 IWL_TRANS_GET_PCIE_TRANS(trans);
1691         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1692         char buf[256];
1693         int pos = 0;
1694         const size_t bufsz = sizeof(buf);
1695
1696         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1697                                                 rxq->read);
1698         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1699                                                 rxq->write);
1700         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1701                                                 rxq->free_count);
1702         if (rxq->rb_stts) {
1703                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1704                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1705         } else {
1706                 pos += scnprintf(buf + pos, bufsz - pos,
1707                                         "closed_rb_num: Not Allocated\n");
1708         }
1709         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1710 }
1711
1712 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1713                                          char __user *user_buf,
1714                                          size_t count, loff_t *ppos)
1715 {
1716         struct iwl_trans *trans = file->private_data;
1717         char *buf;
1718         int pos = 0;
1719         ssize_t ret = -ENOMEM;
1720
1721         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1722         if (buf) {
1723                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1724                 kfree(buf);
1725         }
1726         return ret;
1727 }
1728
1729 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1730                                         const char __user *user_buf,
1731                                         size_t count, loff_t *ppos)
1732 {
1733         struct iwl_trans *trans = file->private_data;
1734         u32 event_log_flag;
1735         char buf[8];
1736         int buf_size;
1737
1738         memset(buf, 0, sizeof(buf));
1739         buf_size = min(count, sizeof(buf) -  1);
1740         if (copy_from_user(buf, user_buf, buf_size))
1741                 return -EFAULT;
1742         if (sscanf(buf, "%d", &event_log_flag) != 1)
1743                 return -EFAULT;
1744         if (event_log_flag == 1)
1745                 iwl_dump_nic_event_log(trans, true, NULL, false);
1746
1747         return count;
1748 }
1749
1750 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1751                                         char __user *user_buf,
1752                                         size_t count, loff_t *ppos) {
1753
1754         struct iwl_trans *trans = file->private_data;
1755         struct iwl_trans_pcie *trans_pcie =
1756                 IWL_TRANS_GET_PCIE_TRANS(trans);
1757         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1758
1759         int pos = 0;
1760         char *buf;
1761         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1762         ssize_t ret;
1763
1764         buf = kzalloc(bufsz, GFP_KERNEL);
1765         if (!buf) {
1766                 IWL_ERR(trans, "Can not allocate Buffer\n");
1767                 return -ENOMEM;
1768         }
1769
1770         pos += scnprintf(buf + pos, bufsz - pos,
1771                         "Interrupt Statistics Report:\n");
1772
1773         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1774                 isr_stats->hw);
1775         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1776                 isr_stats->sw);
1777         if (isr_stats->sw || isr_stats->hw) {
1778                 pos += scnprintf(buf + pos, bufsz - pos,
1779                         "\tLast Restarting Code:  0x%X\n",
1780                         isr_stats->err_code);
1781         }
1782 #ifdef CONFIG_IWLWIFI_DEBUG
1783         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1784                 isr_stats->sch);
1785         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1786                 isr_stats->alive);
1787 #endif
1788         pos += scnprintf(buf + pos, bufsz - pos,
1789                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1790
1791         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1792                 isr_stats->ctkill);
1793
1794         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1795                 isr_stats->wakeup);
1796
1797         pos += scnprintf(buf + pos, bufsz - pos,
1798                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1799
1800         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1801                 isr_stats->tx);
1802
1803         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1804                 isr_stats->unhandled);
1805
1806         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1807         kfree(buf);
1808         return ret;
1809 }
1810
1811 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1812                                          const char __user *user_buf,
1813                                          size_t count, loff_t *ppos)
1814 {
1815         struct iwl_trans *trans = file->private_data;
1816         struct iwl_trans_pcie *trans_pcie =
1817                 IWL_TRANS_GET_PCIE_TRANS(trans);
1818         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1819
1820         char buf[8];
1821         int buf_size;
1822         u32 reset_flag;
1823
1824         memset(buf, 0, sizeof(buf));
1825         buf_size = min(count, sizeof(buf) -  1);
1826         if (copy_from_user(buf, user_buf, buf_size))
1827                 return -EFAULT;
1828         if (sscanf(buf, "%x", &reset_flag) != 1)
1829                 return -EFAULT;
1830         if (reset_flag == 0)
1831                 memset(isr_stats, 0, sizeof(*isr_stats));
1832
1833         return count;
1834 }
1835
1836 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1837                                          const char __user *user_buf,
1838                                          size_t count, loff_t *ppos)
1839 {
1840         struct iwl_trans *trans = file->private_data;
1841         char buf[8];
1842         int buf_size;
1843         int csr;
1844
1845         memset(buf, 0, sizeof(buf));
1846         buf_size = min(count, sizeof(buf) -  1);
1847         if (copy_from_user(buf, user_buf, buf_size))
1848                 return -EFAULT;
1849         if (sscanf(buf, "%d", &csr) != 1)
1850                 return -EFAULT;
1851
1852         iwl_dump_csr(trans);
1853
1854         return count;
1855 }
1856
1857 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1858                                          char __user *user_buf,
1859                                          size_t count, loff_t *ppos)
1860 {
1861         struct iwl_trans *trans = file->private_data;
1862         char *buf;
1863         int pos = 0;
1864         ssize_t ret = -EFAULT;
1865
1866         ret = pos = iwl_dump_fh(trans, &buf, true);
1867         if (buf) {
1868                 ret = simple_read_from_buffer(user_buf,
1869                                               count, ppos, buf, pos);
1870                 kfree(buf);
1871         }
1872
1873         return ret;
1874 }
1875
1876 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1877 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1878 DEBUGFS_READ_FILE_OPS(fh_reg);
1879 DEBUGFS_READ_FILE_OPS(rx_queue);
1880 DEBUGFS_READ_FILE_OPS(tx_queue);
1881 DEBUGFS_WRITE_FILE_OPS(csr);
1882
1883 /*
1884  * Create the debugfs files and directories
1885  *
1886  */
1887 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1888                                         struct dentry *dir)
1889 {
1890         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1891         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1892         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1893         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1894         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1895         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1896         return 0;
1897 }
1898 #else
1899 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1900                                         struct dentry *dir)
1901 { return 0; }
1902
1903 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1904
1905 const struct iwl_trans_ops trans_ops_pcie = {
1906         .alloc = iwl_trans_pcie_alloc,
1907         .request_irq = iwl_trans_pcie_request_irq,
1908         .start_device = iwl_trans_pcie_start_device,
1909         .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1910         .stop_device = iwl_trans_pcie_stop_device,
1911
1912         .tx_start = iwl_trans_pcie_tx_start,
1913         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1914
1915         .send_cmd = iwl_trans_pcie_send_cmd,
1916
1917         .tx = iwl_trans_pcie_tx,
1918         .reclaim = iwl_trans_pcie_reclaim,
1919
1920         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1921         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1922         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1923
1924         .kick_nic = iwl_trans_pcie_kick_nic,
1925
1926         .free = iwl_trans_pcie_free,
1927         .stop_queue = iwl_trans_pcie_stop_queue,
1928
1929         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1930
1931         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1932         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1933
1934 #ifdef CONFIG_PM_SLEEP
1935         .suspend = iwl_trans_pcie_suspend,
1936         .resume = iwl_trans_pcie_resume,
1937 #endif
1938 };