drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
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  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
  79                                                   u32 reg, u32 mask, u32 value)
  80 {
  81         u32 v;
  82
  83 #ifdef CONFIG_IWLWIFI_DEBUG
  84         WARN_ON_ONCE(value & ~mask);
  85 #endif
  86
  87         v = iwl_read32(trans, reg);
  88         v &= ~mask;
  89         v |= value;
  90         iwl_write32(trans, reg, v);
  91 }
  92
  93 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
  94                                               u32 reg, u32 mask)
  95 {
  96         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
  97 }
  98
  99 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
 100                                             u32 reg, u32 mask)
 101 {
 102         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
 103 }
 104
 105 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 106 {
 107         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 108                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 109                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 110                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 111         else
 112                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 113                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 114                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 115 }
 116
 117 /* PCI registers */
 118 #define PCI_CFG_RETRY_TIMEOUT   0x041
 119
 120 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 123         u16 lctl;
 124
 125         /*
 126          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 127          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 128          * If so (likely), disable L0S, so device moves directly L0->L1;
 129          *    costs negligible amount of power savings.
 130          * If not (unlikely), enable L0S, so there is at least some
 131          *    power savings, even without L1.
 132          */
 133         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 134         if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 135                 /* L1-ASPM enabled; disable(!) L0S */
 136                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 137                 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
 138         } else {
 139                 /* L1-ASPM disabled; enable(!) L0S */
 140                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 141                 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
 142         }
 143         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 144 }
 145
 146 /*
 147  * Start up NIC's basic functionality after it has been reset
 148  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 149  * NOTE:  This does not load uCode nor start the embedded processor
 150  */
 151 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 152 {
 153         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 154         int ret = 0;
 155         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 156
 157         /*
 158          * Use "set_bit" below rather than "write", to preserve any hardware
 159          * bits already set by default after reset.
 160          */
 161
 162         /* Disable L0S exit timer (platform NMI Work/Around) */
 163         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 164                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 165
 166         /*
 167          * Disable L0s without affecting L1;
 168          *  don't wait for ICH L0s (ICH bug W/A)
 169          */
 170         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 171                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 172
 173         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 174         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 175
 176         /*
 177          * Enable HAP INTA (interrupt from management bus) to
 178          * wake device's PCI Express link L1a -> L0s
 179          */
 180         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 181                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 182
 183         iwl_pcie_apm_config(trans);
 184
 185         /* Configure analog phase-lock-loop before activating to D0A */
 186         if (trans->cfg->base_params->pll_cfg_val)
 187                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 188                             trans->cfg->base_params->pll_cfg_val);
 189
 190         /*
 191          * Set "initialization complete" bit to move adapter from
 192          * D0U* --> D0A* (powered-up active) state.
 193          */
 194         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 195
 196         /*
 197          * Wait for clock stabilization; once stabilized, access to
 198          * device-internal resources is supported, e.g. iwl_write_prph()
 199          * and accesses to uCode SRAM.
 200          */
 201         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 202                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 203                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 204         if (ret < 0) {
 205                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 206                 goto out;
 207         }
 208
 209         /*
 210          * Enable DMA clock and wait for it to stabilize.
 211          *
 212          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 213          * do not disable clocks.  This preserves any hardware bits already
 214          * set by default in "CLK_CTRL_REG" after reset.
 215          */
 216         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 217         udelay(20);
 218
 219         /* Disable L1-Active */
 220         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 221                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 222
 223         /* Clear the interrupt in APMG if the NIC is in RFKILL */
 224         iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL);
 225
 226         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 227
 228 out:
 229         return ret;
 230 }
 231
 232 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 233 {
 234         int ret = 0;
 235
 236         /* stop device's busmaster DMA activity */
 237         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 238
 239         ret = iwl_poll_bit(trans, CSR_RESET,
 240                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 241                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 242         if (ret)
 243                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 244
 245         IWL_DEBUG_INFO(trans, "stop master\n");
 246
 247         return ret;
 248 }
 249
 250 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 251 {
 252         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 253         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 254
 255         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 256
 257         /* Stop device's DMA activity */
 258         iwl_pcie_apm_stop_master(trans);
 259
 260         /* Reset the entire device */
 261         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 262
 263         udelay(10);
 264
 265         /*
 266          * Clear "initialization complete" bit to move adapter from
 267          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 268          */
 269         iwl_clear_bit(trans, CSR_GP_CNTRL,
 270                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 271 }
 272
 273 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 274 {
 275         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 276         unsigned long flags;
 277
 278         /* nic_init */
 279         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 280         iwl_pcie_apm_init(trans);
 281
 282         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 283         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 284
 285         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 286
 287         iwl_pcie_set_pwr(trans, false);
 288
 289         iwl_op_mode_nic_config(trans->op_mode);
 290
 291         /* Allocate the RX queue, or reset if it is already allocated */
 292         iwl_pcie_rx_init(trans);
 293
 294         /* Allocate or reset and init all Tx and Command queues */
 295         if (iwl_pcie_tx_init(trans))
 296                 return -ENOMEM;
 297
 298         if (trans->cfg->base_params->shadow_reg_enable) {
 299                 /* enable shadow regs in HW */
 300                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 301                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 302         }
 303
 304         return 0;
 305 }
 306
 307 #define HW_READY_TIMEOUT (50)
 308
 309 /* Note: returns poll_bit return value, which is >= 0 if success */
 310 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 311 {
 312         int ret;
 313
 314         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 315                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 316
 317         /* See if we got it */
 318         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 319                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 320                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 321                            HW_READY_TIMEOUT);
 322
 323         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 324         return ret;
 325 }
 326
 327 /* Note: returns standard 0/-ERROR code */
 328 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 329 {
 330         int ret;
 331         int t = 0;
 332
 333         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 334
 335         ret = iwl_pcie_set_hw_ready(trans);
 336         /* If the card is ready, exit 0 */
 337         if (ret >= 0)
 338                 return 0;
 339
 340         /* If HW is not ready, prepare the conditions to check again */
 341         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 342                     CSR_HW_IF_CONFIG_REG_PREPARE);
 343
 344         do {
 345                 ret = iwl_pcie_set_hw_ready(trans);
 346                 if (ret >= 0)
 347                         return 0;
 348
 349                 usleep_range(200, 1000);
 350                 t += 200;
 351         } while (t < 150000);
 352
 353         return ret;
 354 }
 355
 356 /*
 357  * ucode
 358  */
 359 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 360                                    dma_addr_t phy_addr, u32 byte_cnt)
 361 {
 362         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 363         int ret;
 364
 365         trans_pcie->ucode_write_complete = false;
 366
 367         iwl_write_direct32(trans,
 368                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 369                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 370
 371         iwl_write_direct32(trans,
 372                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 373                            dst_addr);
 374
 375         iwl_write_direct32(trans,
 376                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 377                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 378
 379         iwl_write_direct32(trans,
 380                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 381                            (iwl_get_dma_hi_addr(phy_addr)
 382                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 383
 384         iwl_write_direct32(trans,
 385                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 386                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 387                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 388                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 389
 390         iwl_write_direct32(trans,
 391                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 392                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 393                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 394                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 395
 396         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 397                                  trans_pcie->ucode_write_complete, 5 * HZ);
 398         if (!ret) {
 399                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 400                 return -ETIMEDOUT;
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 407                             const struct fw_desc *section)
 408 {
 409         u8 *v_addr;
 410         dma_addr_t p_addr;
 411         u32 offset, chunk_sz = section->len;
 412         int ret = 0;
 413
 414         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 415                      section_num);
 416
 417         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 418                                     GFP_KERNEL | __GFP_NOWARN);
 419         if (!v_addr) {
 420                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 421                 chunk_sz = PAGE_SIZE;
 422                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 423                                             &p_addr, GFP_KERNEL);
 424                 if (!v_addr)
 425                         return -ENOMEM;
 426         }
 427
 428         for (offset = 0; offset < section->len; offset += chunk_sz) {
 429                 u32 copy_size;
 430
 431                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 432
 433                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 434                 ret = iwl_pcie_load_firmware_chunk(trans,
 435                                                    section->offset + offset,
 436                                                    p_addr, copy_size);
 437                 if (ret) {
 438                         IWL_ERR(trans,
 439                                 "Could not load the [%d] uCode section\n",
 440                                 section_num);
 441                         break;
 442                 }
 443         }
 444
 445         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 446         return ret;
 447 }
 448
 449 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 450                                 const struct fw_img *image)
 451 {
 452         int i, ret = 0;
 453
 454         for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
 455                 if (!image->sec[i].data)
 456                         break;
 457
 458                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 459                 if (ret)
 460                         return ret;
 461         }
 462
 463         /* Remove all resets to allow NIC to operate */
 464         iwl_write32(trans, CSR_RESET, 0);
 465
 466         return 0;
 467 }
 468
 469 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 470                                    const struct fw_img *fw, bool run_in_rfkill)
 471 {
 472         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 473         int ret;
 474         bool hw_rfkill;
 475
 476         /* This may fail if AMT took ownership of the device */
 477         if (iwl_pcie_prepare_card_hw(trans)) {
 478                 IWL_WARN(trans, "Exit HW not ready\n");
 479                 return -EIO;
 480         }
 481
 482         clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
 483
 484         iwl_enable_rfkill_int(trans);
 485
 486         /* If platform's RF_KILL switch is NOT set to KILL */
 487         hw_rfkill = iwl_is_rfkill_set(trans);
 488         if (hw_rfkill)
 489                 set_bit(STATUS_RFKILL, &trans_pcie->status);
 490         else
 491                 clear_bit(STATUS_RFKILL, &trans_pcie->status);
 492         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 493         if (hw_rfkill && !run_in_rfkill)
 494                 return -ERFKILL;
 495
 496         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 497
 498         ret = iwl_pcie_nic_init(trans);
 499         if (ret) {
 500                 IWL_ERR(trans, "Unable to init nic\n");
 501                 return ret;
 502         }
 503
 504         /* make sure rfkill handshake bits are cleared */
 505         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 506         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 507                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 508
 509         /* clear (again), then enable host interrupts */
 510         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 511         iwl_enable_interrupts(trans);
 512
 513         /* really make sure rfkill handshake bits are cleared */
 514         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 515         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 516
 517         /* Load the given image to the HW */
 518         return iwl_pcie_load_given_ucode(trans, fw);
 519 }
 520
 521 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 522 {
 523         iwl_pcie_reset_ict(trans);
 524         iwl_pcie_tx_start(trans, scd_addr);
 525 }
 526
 527 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 528 {
 529         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 530         unsigned long flags;
 531
 532         /* tell the device to stop sending interrupts */
 533         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 534         iwl_disable_interrupts(trans);
 535         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 536
 537         /* device going down, Stop using ICT table */
 538         iwl_pcie_disable_ict(trans);
 539
 540         /*
 541          * If a HW restart happens during firmware loading,
 542          * then the firmware loading might call this function
 543          * and later it might be called again due to the
 544          * restart. So don't process again if the device is
 545          * already dead.
 546          */
 547         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
 548                 iwl_pcie_tx_stop(trans);
 549                 iwl_pcie_rx_stop(trans);
 550
 551                 /* Power-down device's busmaster DMA clocks */
 552                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 553                                APMG_CLK_VAL_DMA_CLK_RQT);
 554                 udelay(5);
 555         }
 556
 557         /* Make sure (redundant) we've released our request to stay awake */
 558         iwl_clear_bit(trans, CSR_GP_CNTRL,
 559                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 560
 561         /* Stop the device, and put it in low power state */
 562         iwl_pcie_apm_stop(trans);
 563
 564         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 565          * Clean again the interrupt here
 566          */
 567         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 568         iwl_disable_interrupts(trans);
 569         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 570
 571         iwl_enable_rfkill_int(trans);
 572
 573         /* stop and reset the on-board processor */
 574         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 575
 576         /* clear all status bits */
 577         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 578         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
 579         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 580         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 581         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 582 }
 583
 584 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
 585 {
 586         iwl_disable_interrupts(trans);
 587
 588         /*
 589          * in testing mode, the host stays awake and the
 590          * hardware won't be reset (not even partially)
 591          */
 592         if (test)
 593                 return;
 594
 595         iwl_pcie_disable_ict(trans);
 596
 597         iwl_clear_bit(trans, CSR_GP_CNTRL,
 598                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 599         iwl_clear_bit(trans, CSR_GP_CNTRL,
 600                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 601
 602         /*
 603          * reset TX queues -- some of their registers reset during S3
 604          * so if we don't reset everything here the D3 image would try
 605          * to execute some invalid memory upon resume
 606          */
 607         iwl_trans_pcie_tx_reset(trans);
 608
 609         iwl_pcie_set_pwr(trans, true);
 610 }
 611
 612 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 613                                     enum iwl_d3_status *status,
 614                                     bool test)
 615 {
 616         u32 val;
 617         int ret;
 618
 619         if (test) {
 620                 iwl_enable_interrupts(trans);
 621                 *status = IWL_D3_STATUS_ALIVE;
 622                 return 0;
 623         }
 624
 625         iwl_pcie_set_pwr(trans, false);
 626
 627         val = iwl_read32(trans, CSR_RESET);
 628         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 629                 *status = IWL_D3_STATUS_RESET;
 630                 return 0;
 631         }
 632
 633         /*
 634          * Also enables interrupts - none will happen as the device doesn't
 635          * know we're waking it up, only when the opmode actually tells it
 636          * after this call.
 637          */
 638         iwl_pcie_reset_ict(trans);
 639
 640         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 641         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 642
 643         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 644                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 645                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 646                            25000);
 647         if (ret) {
 648                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
 649                 return ret;
 650         }
 651
 652         iwl_trans_pcie_tx_reset(trans);
 653
 654         ret = iwl_pcie_rx_init(trans);
 655         if (ret) {
 656                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
 657                 return ret;
 658         }
 659
 660         *status = IWL_D3_STATUS_ALIVE;
 661         return 0;
 662 }
 663
 664 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 665 {
 666         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 667         bool hw_rfkill;
 668         int err;
 669
 670         err = iwl_pcie_prepare_card_hw(trans);
 671         if (err) {
 672                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 673                 return err;
 674         }
 675
 676         /* Reset the entire device */
 677         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 678
 679         usleep_range(10, 15);
 680
 681         iwl_pcie_apm_init(trans);
 682
 683         /* From now on, the op_mode will be kept updated about RF kill state */
 684         iwl_enable_rfkill_int(trans);
 685
 686         hw_rfkill = iwl_is_rfkill_set(trans);
 687         if (hw_rfkill)
 688                 set_bit(STATUS_RFKILL, &trans_pcie->status);
 689         else
 690                 clear_bit(STATUS_RFKILL, &trans_pcie->status);
 691         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 692
 693         return 0;
 694 }
 695
 696 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
 697                                    bool op_mode_leaving)
 698 {
 699         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 700         bool hw_rfkill;
 701         unsigned long flags;
 702
 703         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 704         iwl_disable_interrupts(trans);
 705         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 706
 707         iwl_pcie_apm_stop(trans);
 708
 709         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 710         iwl_disable_interrupts(trans);
 711         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 712
 713         iwl_pcie_disable_ict(trans);
 714
 715         if (!op_mode_leaving) {
 716                 /*
 717                  * Even if we stop the HW, we still want the RF kill
 718                  * interrupt
 719                  */
 720                 iwl_enable_rfkill_int(trans);
 721
 722                 /*
 723                  * Check again since the RF kill state may have changed while
 724                  * all the interrupts were disabled, in this case we couldn't
 725                  * receive the RF kill interrupt and update the state in the
 726                  * op_mode.
 727                  */
 728                 hw_rfkill = iwl_is_rfkill_set(trans);
 729                 if (hw_rfkill)
 730                         set_bit(STATUS_RFKILL, &trans_pcie->status);
 731                 else
 732                         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 733                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 734         }
 735 }
 736
 737 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 738 {
 739         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 740 }
 741
 742 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 743 {
 744         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 745 }
 746
 747 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 748 {
 749         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 750 }
 751
 752 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 753 {
 754         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
 755                                ((reg & 0x000FFFFF) | (3 << 24)));
 756         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 757 }
 758
 759 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 760                                       u32 val)
 761 {
 762         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 763                                ((addr & 0x000FFFFF) | (3 << 24)));
 764         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 765 }
 766
 767 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 768                                      const struct iwl_trans_config *trans_cfg)
 769 {
 770         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 771
 772         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 773         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 774         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 775                 trans_pcie->n_no_reclaim_cmds = 0;
 776         else
 777                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 778         if (trans_pcie->n_no_reclaim_cmds)
 779                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 780                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 781
 782         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 783         if (trans_pcie->rx_buf_size_8k)
 784                 trans_pcie->rx_page_order = get_order(8 * 1024);
 785         else
 786                 trans_pcie->rx_page_order = get_order(4 * 1024);
 787
 788         trans_pcie->wd_timeout =
 789                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 790
 791         trans_pcie->command_names = trans_cfg->command_names;
 792         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
 793 }
 794
 795 void iwl_trans_pcie_free(struct iwl_trans *trans)
 796 {
 797         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 798
 799         synchronize_irq(trans_pcie->pci_dev->irq);
 800
 801         iwl_pcie_tx_free(trans);
 802         iwl_pcie_rx_free(trans);
 803
 804         free_irq(trans_pcie->pci_dev->irq, trans);
 805         iwl_pcie_free_ict(trans);
 806
 807         pci_disable_msi(trans_pcie->pci_dev);
 808         iounmap(trans_pcie->hw_base);
 809         pci_release_regions(trans_pcie->pci_dev);
 810         pci_disable_device(trans_pcie->pci_dev);
 811         kmem_cache_destroy(trans->dev_cmd_pool);
 812
 813         kfree(trans);
 814 }
 815
 816 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 817 {
 818         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 819
 820         if (state)
 821                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 822         else
 823                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 824 }
 825
 826 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
 827                                                 unsigned long *flags)
 828 {
 829         int ret;
 830         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 831
 832         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
 833
 834         /* this bit wakes up the NIC */
 835         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 836                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 837
 838         /*
 839          * These bits say the device is running, and should keep running for
 840          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 841          * but they do not indicate that embedded SRAM is restored yet;
 842          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 843          * to/from host DRAM when sleeping/waking for power-saving.
 844          * Each direction takes approximately 1/4 millisecond; with this
 845          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 846          * series of register accesses are expected (e.g. reading Event Log),
 847          * to keep device from sleeping.
 848          *
 849          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 850          * SRAM is okay/restored.  We don't check that here because this call
 851          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 852          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 853          *
 854          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 855          * and do not save/restore SRAM when power cycling.
 856          */
 857         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 858                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 859                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 860                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 861         if (unlikely(ret < 0)) {
 862                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 863                 if (!silent) {
 864                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
 865                         WARN_ONCE(1,
 866                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
 867                                   val);
 868                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
 869                         return false;
 870                 }
 871         }
 872
 873         /*
 874          * Fool sparse by faking we release the lock - sparse will
 875          * track nic_access anyway.
 876          */
 877         __release(&trans_pcie->reg_lock);
 878         return true;
 879 }
 880
 881 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
 882                                               unsigned long *flags)
 883 {
 884         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 885
 886         lockdep_assert_held(&trans_pcie->reg_lock);
 887
 888         /*
 889          * Fool sparse by faking we acquiring the lock - sparse will
 890          * track nic_access anyway.
 891          */
 892         __acquire(&trans_pcie->reg_lock);
 893
 894         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 895                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 896         /*
 897          * Above we read the CSR_GP_CNTRL register, which will flush
 898          * any previous writes, but we need the write that clears the
 899          * MAC_ACCESS_REQ bit to be performed before any other writes
 900          * scheduled on different CPUs (after we drop reg_lock).
 901          */
 902         mmiowb();
 903         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
 904 }
 905
 906 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
 907                                    void *buf, int dwords)
 908 {
 909         unsigned long flags;
 910         int offs, ret = 0;
 911         u32 *vals = buf;
 912
 913         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
 914                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
 915                 for (offs = 0; offs < dwords; offs++)
 916                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 917                 iwl_trans_release_nic_access(trans, &flags);
 918         } else {
 919                 ret = -EBUSY;
 920         }
 921         return ret;
 922 }
 923
 924 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
 925                                     const void *buf, int dwords)
 926 {
 927         unsigned long flags;
 928         int offs, ret = 0;
 929         const u32 *vals = buf;
 930
 931         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
 932                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
 933                 for (offs = 0; offs < dwords; offs++)
 934                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
 935                                     vals ? vals[offs] : 0);
 936                 iwl_trans_release_nic_access(trans, &flags);
 937         } else {
 938                 ret = -EBUSY;
 939         }
 940         return ret;
 941 }
 942
 943 #define IWL_FLUSH_WAIT_MS       2000
 944
 945 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
 946 {
 947         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 948         struct iwl_txq *txq;
 949         struct iwl_queue *q;
 950         int cnt;
 951         unsigned long now = jiffies;
 952         u32 scd_sram_addr;
 953         u8 buf[16];
 954         int ret = 0;
 955
 956         /* waiting for all the tx frames complete might take a while */
 957         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
 958                 if (cnt == trans_pcie->cmd_queue)
 959                         continue;
 960                 txq = &trans_pcie->txq[cnt];
 961                 q = &txq->q;
 962                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
 963                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
 964                         msleep(1);
 965
 966                 if (q->read_ptr != q->write_ptr) {
 967                         IWL_ERR(trans,
 968                                 "fail to flush all tx fifo queues Q %d\n", cnt);
 969                         ret = -ETIMEDOUT;
 970                         break;
 971                 }
 972         }
 973
 974         if (!ret)
 975                 return 0;
 976
 977         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 978                 txq->q.read_ptr, txq->q.write_ptr);
 979
 980         scd_sram_addr = trans_pcie->scd_base_addr +
 981                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
 982         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 983
 984         iwl_print_hex_error(trans, buf, sizeof(buf));
 985
 986         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
 987                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
 988                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
 989
 990         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
 991                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
 992                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 993                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 994                 u32 tbl_dw =
 995                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
 996                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
 997
 998                 if (cnt & 0x1)
 999                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1000                 else
1001                         tbl_dw = tbl_dw & 0x0000FFFF;
1002
1003                 IWL_ERR(trans,
1004                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1005                         cnt, active ? "" : "in", fifo, tbl_dw,
1006                         iwl_read_prph(trans,
1007                                       SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1008                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1009         }
1010
1011         return ret;
1012 }
1013
1014 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1015                                          u32 mask, u32 value)
1016 {
1017         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1018         unsigned long flags;
1019
1020         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1021         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1022         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1023 }
1024
1025 static const char *get_csr_string(int cmd)
1026 {
1027 #define IWL_CMD(x) case x: return #x
1028         switch (cmd) {
1029         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1030         IWL_CMD(CSR_INT_COALESCING);
1031         IWL_CMD(CSR_INT);
1032         IWL_CMD(CSR_INT_MASK);
1033         IWL_CMD(CSR_FH_INT_STATUS);
1034         IWL_CMD(CSR_GPIO_IN);
1035         IWL_CMD(CSR_RESET);
1036         IWL_CMD(CSR_GP_CNTRL);
1037         IWL_CMD(CSR_HW_REV);
1038         IWL_CMD(CSR_EEPROM_REG);
1039         IWL_CMD(CSR_EEPROM_GP);
1040         IWL_CMD(CSR_OTP_GP_REG);
1041         IWL_CMD(CSR_GIO_REG);
1042         IWL_CMD(CSR_GP_UCODE_REG);
1043         IWL_CMD(CSR_GP_DRIVER_REG);
1044         IWL_CMD(CSR_UCODE_DRV_GP1);
1045         IWL_CMD(CSR_UCODE_DRV_GP2);
1046         IWL_CMD(CSR_LED_REG);
1047         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1048         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1049         IWL_CMD(CSR_ANA_PLL_CFG);
1050         IWL_CMD(CSR_HW_REV_WA_REG);
1051         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1052         default:
1053                 return "UNKNOWN";
1054         }
1055 #undef IWL_CMD
1056 }
1057
1058 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1059 {
1060         int i;
1061         static const u32 csr_tbl[] = {
1062                 CSR_HW_IF_CONFIG_REG,
1063                 CSR_INT_COALESCING,
1064                 CSR_INT,
1065                 CSR_INT_MASK,
1066                 CSR_FH_INT_STATUS,
1067                 CSR_GPIO_IN,
1068                 CSR_RESET,
1069                 CSR_GP_CNTRL,
1070                 CSR_HW_REV,
1071                 CSR_EEPROM_REG,
1072                 CSR_EEPROM_GP,
1073                 CSR_OTP_GP_REG,
1074                 CSR_GIO_REG,
1075                 CSR_GP_UCODE_REG,
1076                 CSR_GP_DRIVER_REG,
1077                 CSR_UCODE_DRV_GP1,
1078                 CSR_UCODE_DRV_GP2,
1079                 CSR_LED_REG,
1080                 CSR_DRAM_INT_TBL_REG,
1081                 CSR_GIO_CHICKEN_BITS,
1082                 CSR_ANA_PLL_CFG,
1083                 CSR_HW_REV_WA_REG,
1084                 CSR_DBG_HPET_MEM_REG
1085         };
1086         IWL_ERR(trans, "CSR values:\n");
1087         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1088                 "CSR_INT_PERIODIC_REG)\n");
1089         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1090                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1091                         get_csr_string(csr_tbl[i]),
1092                         iwl_read32(trans, csr_tbl[i]));
1093         }
1094 }
1095
1096 #ifdef CONFIG_IWLWIFI_DEBUGFS
1097 /* create and remove of files */
1098 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1099         if (!debugfs_create_file(#name, mode, parent, trans,            \
1100                                  &iwl_dbgfs_##name##_ops))              \
1101                 goto err;                                               \
1102 } while (0)
1103
1104 /* file operation */
1105 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1106 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1107         .read = iwl_dbgfs_##name##_read,                                \
1108         .open = simple_open,                                            \
1109         .llseek = generic_file_llseek,                                  \
1110 };
1111
1112 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1113 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1114         .write = iwl_dbgfs_##name##_write,                              \
1115         .open = simple_open,                                            \
1116         .llseek = generic_file_llseek,                                  \
1117 };
1118
1119 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1120 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1121         .write = iwl_dbgfs_##name##_write,                              \
1122         .read = iwl_dbgfs_##name##_read,                                \
1123         .open = simple_open,                                            \
1124         .llseek = generic_file_llseek,                                  \
1125 };
1126
1127 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1128                                        char __user *user_buf,
1129                                        size_t count, loff_t *ppos)
1130 {
1131         struct iwl_trans *trans = file->private_data;
1132         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1133         struct iwl_txq *txq;
1134         struct iwl_queue *q;
1135         char *buf;
1136         int pos = 0;
1137         int cnt;
1138         int ret;
1139         size_t bufsz;
1140
1141         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1142
1143         if (!trans_pcie->txq)
1144                 return -EAGAIN;
1145
1146         buf = kzalloc(bufsz, GFP_KERNEL);
1147         if (!buf)
1148                 return -ENOMEM;
1149
1150         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1151                 txq = &trans_pcie->txq[cnt];
1152                 q = &txq->q;
1153                 pos += scnprintf(buf + pos, bufsz - pos,
1154                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1155                                 cnt, q->read_ptr, q->write_ptr,
1156                                 !!test_bit(cnt, trans_pcie->queue_used),
1157                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1158         }
1159         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1160         kfree(buf);
1161         return ret;
1162 }
1163
1164 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1165                                        char __user *user_buf,
1166                                        size_t count, loff_t *ppos)
1167 {
1168         struct iwl_trans *trans = file->private_data;
1169         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1170         struct iwl_rxq *rxq = &trans_pcie->rxq;
1171         char buf[256];
1172         int pos = 0;
1173         const size_t bufsz = sizeof(buf);
1174
1175         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1176                                                 rxq->read);
1177         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1178                                                 rxq->write);
1179         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1180                                                 rxq->free_count);
1181         if (rxq->rb_stts) {
1182                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1183                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1184         } else {
1185                 pos += scnprintf(buf + pos, bufsz - pos,
1186                                         "closed_rb_num: Not Allocated\n");
1187         }
1188         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1189 }
1190
1191 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1192                                         char __user *user_buf,
1193                                         size_t count, loff_t *ppos)
1194 {
1195         struct iwl_trans *trans = file->private_data;
1196         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1197         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1198
1199         int pos = 0;
1200         char *buf;
1201         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1202         ssize_t ret;
1203
1204         buf = kzalloc(bufsz, GFP_KERNEL);
1205         if (!buf)
1206                 return -ENOMEM;
1207
1208         pos += scnprintf(buf + pos, bufsz - pos,
1209                         "Interrupt Statistics Report:\n");
1210
1211         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1212                 isr_stats->hw);
1213         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1214                 isr_stats->sw);
1215         if (isr_stats->sw || isr_stats->hw) {
1216                 pos += scnprintf(buf + pos, bufsz - pos,
1217                         "\tLast Restarting Code:  0x%X\n",
1218                         isr_stats->err_code);
1219         }
1220 #ifdef CONFIG_IWLWIFI_DEBUG
1221         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1222                 isr_stats->sch);
1223         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1224                 isr_stats->alive);
1225 #endif
1226         pos += scnprintf(buf + pos, bufsz - pos,
1227                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1228
1229         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1230                 isr_stats->ctkill);
1231
1232         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1233                 isr_stats->wakeup);
1234
1235         pos += scnprintf(buf + pos, bufsz - pos,
1236                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1237
1238         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1239                 isr_stats->tx);
1240
1241         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1242                 isr_stats->unhandled);
1243
1244         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1245         kfree(buf);
1246         return ret;
1247 }
1248
1249 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1250                                          const char __user *user_buf,
1251                                          size_t count, loff_t *ppos)
1252 {
1253         struct iwl_trans *trans = file->private_data;
1254         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1255         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1256
1257         char buf[8];
1258         int buf_size;
1259         u32 reset_flag;
1260
1261         memset(buf, 0, sizeof(buf));
1262         buf_size = min(count, sizeof(buf) -  1);
1263         if (copy_from_user(buf, user_buf, buf_size))
1264                 return -EFAULT;
1265         if (sscanf(buf, "%x", &reset_flag) != 1)
1266                 return -EFAULT;
1267         if (reset_flag == 0)
1268                 memset(isr_stats, 0, sizeof(*isr_stats));
1269
1270         return count;
1271 }
1272
1273 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1274                                    const char __user *user_buf,
1275                                    size_t count, loff_t *ppos)
1276 {
1277         struct iwl_trans *trans = file->private_data;
1278         char buf[8];
1279         int buf_size;
1280         int csr;
1281
1282         memset(buf, 0, sizeof(buf));
1283         buf_size = min(count, sizeof(buf) -  1);
1284         if (copy_from_user(buf, user_buf, buf_size))
1285                 return -EFAULT;
1286         if (sscanf(buf, "%d", &csr) != 1)
1287                 return -EFAULT;
1288
1289         iwl_pcie_dump_csr(trans);
1290
1291         return count;
1292 }
1293
1294 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1295                                      char __user *user_buf,
1296                                      size_t count, loff_t *ppos)
1297 {
1298         struct iwl_trans *trans = file->private_data;
1299         char *buf = NULL;
1300         int pos = 0;
1301         ssize_t ret = -EFAULT;
1302
1303         ret = pos = iwl_dump_fh(trans, &buf);
1304         if (buf) {
1305                 ret = simple_read_from_buffer(user_buf,
1306                                               count, ppos, buf, pos);
1307                 kfree(buf);
1308         }
1309
1310         return ret;
1311 }
1312
1313 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1314 DEBUGFS_READ_FILE_OPS(fh_reg);
1315 DEBUGFS_READ_FILE_OPS(rx_queue);
1316 DEBUGFS_READ_FILE_OPS(tx_queue);
1317 DEBUGFS_WRITE_FILE_OPS(csr);
1318
1319 /*
1320  * Create the debugfs files and directories
1321  *
1322  */
1323 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1324                                          struct dentry *dir)
1325 {
1326         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1327         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1328         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1329         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1330         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1331         return 0;
1332
1333 err:
1334         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1335         return -ENOMEM;
1336 }
1337 #else
1338 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1339                                          struct dentry *dir)
1340 {
1341         return 0;
1342 }
1343 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1344
1345 static const struct iwl_trans_ops trans_ops_pcie = {
1346         .start_hw = iwl_trans_pcie_start_hw,
1347         .stop_hw = iwl_trans_pcie_stop_hw,
1348         .fw_alive = iwl_trans_pcie_fw_alive,
1349         .start_fw = iwl_trans_pcie_start_fw,
1350         .stop_device = iwl_trans_pcie_stop_device,
1351
1352         .d3_suspend = iwl_trans_pcie_d3_suspend,
1353         .d3_resume = iwl_trans_pcie_d3_resume,
1354
1355         .send_cmd = iwl_trans_pcie_send_hcmd,
1356
1357         .tx = iwl_trans_pcie_tx,
1358         .reclaim = iwl_trans_pcie_reclaim,
1359
1360         .txq_disable = iwl_trans_pcie_txq_disable,
1361         .txq_enable = iwl_trans_pcie_txq_enable,
1362
1363         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1364
1365         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1366
1367         .write8 = iwl_trans_pcie_write8,
1368         .write32 = iwl_trans_pcie_write32,
1369         .read32 = iwl_trans_pcie_read32,
1370         .read_prph = iwl_trans_pcie_read_prph,
1371         .write_prph = iwl_trans_pcie_write_prph,
1372         .read_mem = iwl_trans_pcie_read_mem,
1373         .write_mem = iwl_trans_pcie_write_mem,
1374         .configure = iwl_trans_pcie_configure,
1375         .set_pmi = iwl_trans_pcie_set_pmi,
1376         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1377         .release_nic_access = iwl_trans_pcie_release_nic_access,
1378         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1379 };
1380
1381 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1382                                        const struct pci_device_id *ent,
1383                                        const struct iwl_cfg *cfg)
1384 {
1385         struct iwl_trans_pcie *trans_pcie;
1386         struct iwl_trans *trans;
1387         u16 pci_cmd;
1388         int err;
1389
1390         trans = kzalloc(sizeof(struct iwl_trans) +
1391                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1392         if (!trans) {
1393                 err = -ENOMEM;
1394                 goto out;
1395         }
1396
1397         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1398
1399         trans->ops = &trans_ops_pcie;
1400         trans->cfg = cfg;
1401         trans_lockdep_init(trans);
1402         trans_pcie->trans = trans;
1403         spin_lock_init(&trans_pcie->irq_lock);
1404         spin_lock_init(&trans_pcie->reg_lock);
1405         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1406
1407         if (!cfg->base_params->pcie_l1_allowed) {
1408                 /*
1409                  * W/A - seems to solve weird behavior. We need to remove this
1410                  * if we don't want to stay in L1 all the time. This wastes a
1411                  * lot of power.
1412                  */
1413                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1414                                        PCIE_LINK_STATE_L1 |
1415                                        PCIE_LINK_STATE_CLKPM);
1416         }
1417
1418         err = pci_enable_device(pdev);
1419         if (err)
1420                 goto out_no_pci;
1421
1422         pci_set_master(pdev);
1423
1424         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1425         if (!err)
1426                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1427         if (err) {
1428                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1429                 if (!err)
1430                         err = pci_set_consistent_dma_mask(pdev,
1431                                                           DMA_BIT_MASK(32));
1432                 /* both attempts failed: */
1433                 if (err) {
1434                         dev_err(&pdev->dev, "No suitable DMA available\n");
1435                         goto out_pci_disable_device;
1436                 }
1437         }
1438
1439         err = pci_request_regions(pdev, DRV_NAME);
1440         if (err) {
1441                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1442                 goto out_pci_disable_device;
1443         }
1444
1445         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1446         if (!trans_pcie->hw_base) {
1447                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1448                 err = -ENODEV;
1449                 goto out_pci_release_regions;
1450         }
1451
1452         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1453          * PCI Tx retries from interfering with C3 CPU state */
1454         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1455
1456         err = pci_enable_msi(pdev);
1457         if (err) {
1458                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1459                 /* enable rfkill interrupt: hw bug w/a */
1460                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1461                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1462                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1463                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1464                 }
1465         }
1466
1467         trans->dev = &pdev->dev;
1468         trans_pcie->pci_dev = pdev;
1469         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1470         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1471         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1472                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1473
1474         /* Initialize the wait queue for commands */
1475         init_waitqueue_head(&trans_pcie->wait_command_queue);
1476
1477         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1478                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1479
1480         trans->dev_cmd_headroom = 0;
1481         trans->dev_cmd_pool =
1482                 kmem_cache_create(trans->dev_cmd_pool_name,
1483                                   sizeof(struct iwl_device_cmd)
1484                                   + trans->dev_cmd_headroom,
1485                                   sizeof(void *),
1486                                   SLAB_HWCACHE_ALIGN,
1487                                   NULL);
1488
1489         if (!trans->dev_cmd_pool) {
1490                 err = -ENOMEM;
1491                 goto out_pci_disable_msi;
1492         }
1493
1494         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1495
1496         if (iwl_pcie_alloc_ict(trans))
1497                 goto out_free_cmd_pool;
1498
1499         err = request_threaded_irq(pdev->irq, iwl_pcie_isr_ict,
1500                                    iwl_pcie_irq_handler,
1501                                    IRQF_SHARED, DRV_NAME, trans);
1502         if (err) {
1503                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1504                 goto out_free_ict;
1505         }
1506
1507         return trans;
1508
1509 out_free_ict:
1510         iwl_pcie_free_ict(trans);
1511 out_free_cmd_pool:
1512         kmem_cache_destroy(trans->dev_cmd_pool);
1513 out_pci_disable_msi:
1514         pci_disable_msi(pdev);
1515 out_pci_release_regions:
1516         pci_release_regions(pdev);
1517 out_pci_disable_device:
1518         pci_disable_device(pdev);
1519 out_no_pci:
1520         kfree(trans);
1521 out:
1522         return ERR_PTR(err);
1523 }