drivers/net/wireless/iwlwifi/pcie/tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
   5  *
   6  * Portions of this file are derived from the ipw3945 project, as well
   7  * as portions of the ieee80211 subsystem header files.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc.,
  20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  21  *
  22  * The full GNU General Public License is included in this distribution in the
  23  * file called LICENSE.
  24  *
  25  * Contact Information:
  26  *  Intel Linux Wireless <ilw@linux.intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
  29  *****************************************************************************/
  30 #include <linux/etherdevice.h>
  31 #include <linux/slab.h>
  32 #include <linux/sched.h>
  33
  34 #include "iwl-debug.h"
  35 #include "iwl-csr.h"
  36 #include "iwl-prph.h"
  37 #include "iwl-io.h"
  38 #include "iwl-scd.h"
  39 #include "iwl-op-mode.h"
  40 #include "internal.h"
  41 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  42 #include "dvm/commands.h"
  43
  44 #define IWL_TX_CRC_SIZE 4
  45 #define IWL_TX_DELIMITER_SIZE 4
  46
  47 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
  48  * DMA services
  49  *
  50  * Theory of operation
  51  *
  52  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  53  * of buffer descriptors, each of which points to one or more data buffers for
  54  * the device to read from or fill.  Driver and device exchange status of each
  55  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
  56  * entries in each circular buffer, to protect against confusing empty and full
  57  * queue states.
  58  *
  59  * The device reads or writes the data in the queues via the device's several
  60  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
  61  *
  62  * For Tx queue, there are low mark and high mark limits. If, after queuing
  63  * the packet for Tx, free space become < low mark, Tx queue stopped. When
  64  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  65  * Tx queue resumed.
  66  *
  67  ***************************************************/
  68 static int iwl_queue_space(const struct iwl_queue *q)
  69 {
  70         unsigned int max;
  71         unsigned int used;
  72
  73         /*
  74          * To avoid ambiguity between empty and completely full queues, there
  75          * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
  76          * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
  77          * to reserve any queue entries for this purpose.
  78          */
  79         if (q->n_window < TFD_QUEUE_SIZE_MAX)
  80                 max = q->n_window;
  81         else
  82                 max = TFD_QUEUE_SIZE_MAX - 1;
  83
  84         /*
  85          * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
  86          * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
  87          */
  88         used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
  89
  90         if (WARN_ON(used > max))
  91                 return 0;
  92
  93         return max - used;
  94 }
  95
  96 /*
  97  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
  98  */
  99 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
 100 {
 101         q->n_window = slots_num;
 102         q->id = id;
 103
 104         /* slots_num must be power-of-two size, otherwise
 105          * get_cmd_index is broken. */
 106         if (WARN_ON(!is_power_of_2(slots_num)))
 107                 return -EINVAL;
 108
 109         q->low_mark = q->n_window / 4;
 110         if (q->low_mark < 4)
 111                 q->low_mark = 4;
 112
 113         q->high_mark = q->n_window / 8;
 114         if (q->high_mark < 2)
 115                 q->high_mark = 2;
 116
 117         q->write_ptr = 0;
 118         q->read_ptr = 0;
 119
 120         return 0;
 121 }
 122
 123 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
 124                                   struct iwl_dma_ptr *ptr, size_t size)
 125 {
 126         if (WARN_ON(ptr->addr))
 127                 return -EINVAL;
 128
 129         ptr->addr = dma_alloc_coherent(trans->dev, size,
 130                                        &ptr->dma, GFP_KERNEL);
 131         if (!ptr->addr)
 132                 return -ENOMEM;
 133         ptr->size = size;
 134         return 0;
 135 }
 136
 137 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
 138                                   struct iwl_dma_ptr *ptr)
 139 {
 140         if (unlikely(!ptr->addr))
 141                 return;
 142
 143         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 144         memset(ptr, 0, sizeof(*ptr));
 145 }
 146
 147 static void iwl_pcie_txq_stuck_timer(unsigned long data)
 148 {
 149         struct iwl_txq *txq = (void *)data;
 150         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 151         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 152         u32 scd_sram_addr = trans_pcie->scd_base_addr +
 153                                 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
 154         u8 buf[16];
 155         int i;
 156
 157         spin_lock(&txq->lock);
 158         /* check if triggered erroneously */
 159         if (txq->q.read_ptr == txq->q.write_ptr) {
 160                 spin_unlock(&txq->lock);
 161                 return;
 162         }
 163         spin_unlock(&txq->lock);
 164
 165         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 166                 jiffies_to_msecs(txq->wd_timeout));
 167         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 168                 txq->q.read_ptr, txq->q.write_ptr);
 169
 170         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 171
 172         iwl_print_hex_error(trans, buf, sizeof(buf));
 173
 174         for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
 175                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
 176                         iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
 177
 178         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 179                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
 180                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 181                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 182                 u32 tbl_dw =
 183                         iwl_trans_read_mem32(trans,
 184                                              trans_pcie->scd_base_addr +
 185                                              SCD_TRANS_TBL_OFFSET_QUEUE(i));
 186
 187                 if (i & 0x1)
 188                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
 189                 else
 190                         tbl_dw = tbl_dw & 0x0000FFFF;
 191
 192                 IWL_ERR(trans,
 193                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
 194                         i, active ? "" : "in", fifo, tbl_dw,
 195                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
 196                                 (TFD_QUEUE_SIZE_MAX - 1),
 197                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
 198         }
 199
 200         iwl_force_nmi(trans);
 201 }
 202
 203 /*
 204  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 205  */
 206 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 207                                              struct iwl_txq *txq, u16 byte_cnt)
 208 {
 209         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
 210         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 211         int write_ptr = txq->q.write_ptr;
 212         int txq_id = txq->q.id;
 213         u8 sec_ctl = 0;
 214         u8 sta_id = 0;
 215         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 216         __le16 bc_ent;
 217         struct iwl_tx_cmd *tx_cmd =
 218                 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
 219
 220         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 221
 222         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 223
 224         sta_id = tx_cmd->sta_id;
 225         sec_ctl = tx_cmd->sec_ctl;
 226
 227         switch (sec_ctl & TX_CMD_SEC_MSK) {
 228         case TX_CMD_SEC_CCM:
 229                 len += IEEE80211_CCMP_MIC_LEN;
 230                 break;
 231         case TX_CMD_SEC_TKIP:
 232                 len += IEEE80211_TKIP_ICV_LEN;
 233                 break;
 234         case TX_CMD_SEC_WEP:
 235                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
 236                 break;
 237         }
 238
 239         if (trans_pcie->bc_table_dword)
 240                 len = DIV_ROUND_UP(len, 4);
 241
 242         bc_ent = cpu_to_le16(len | (sta_id << 12));
 243
 244         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 245
 246         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 247                 scd_bc_tbl[txq_id].
 248                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 249 }
 250
 251 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 252                                             struct iwl_txq *txq)
 253 {
 254         struct iwl_trans_pcie *trans_pcie =
 255                 IWL_TRANS_GET_PCIE_TRANS(trans);
 256         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 257         int txq_id = txq->q.id;
 258         int read_ptr = txq->q.read_ptr;
 259         u8 sta_id = 0;
 260         __le16 bc_ent;
 261         struct iwl_tx_cmd *tx_cmd =
 262                 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
 263
 264         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 265
 266         if (txq_id != trans_pcie->cmd_queue)
 267                 sta_id = tx_cmd->sta_id;
 268
 269         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 270         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 271
 272         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 273                 scd_bc_tbl[txq_id].
 274                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 275 }
 276
 277 /*
 278  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
 279  */
 280 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 281                                     struct iwl_txq *txq)
 282 {
 283         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 284         u32 reg = 0;
 285         int txq_id = txq->q.id;
 286
 287         lockdep_assert_held(&txq->lock);
 288
 289         /*
 290          * explicitly wake up the NIC if:
 291          * 1. shadow registers aren't enabled
 292          * 2. NIC is woken up for CMD regardless of shadow outside this function
 293          * 3. there is a chance that the NIC is asleep
 294          */
 295         if (!trans->cfg->base_params->shadow_reg_enable &&
 296             txq_id != trans_pcie->cmd_queue &&
 297             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 298                 /*
 299                  * wake up nic if it's powered down ...
 300                  * uCode will wake up, and interrupt us again, so next
 301                  * time we'll skip this part.
 302                  */
 303                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 304
 305                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 306                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 307                                        txq_id, reg);
 308                         iwl_set_bit(trans, CSR_GP_CNTRL,
 309                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 310                         txq->need_update = true;
 311                         return;
 312                 }
 313         }
 314
 315         /*
 316          * if not in power-save mode, uCode will never sleep when we're
 317          * trying to tx (during RFKILL, we're not trying to tx).
 318          */
 319         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
 320         iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
 321 }
 322
 323 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
 324 {
 325         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 326         int i;
 327
 328         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 329                 struct iwl_txq *txq = &trans_pcie->txq[i];
 330
 331                 spin_lock_bh(&txq->lock);
 332                 if (trans_pcie->txq[i].need_update) {
 333                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
 334                         trans_pcie->txq[i].need_update = false;
 335                 }
 336                 spin_unlock_bh(&txq->lock);
 337         }
 338 }
 339
 340 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 341 {
 342         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 343
 344         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 345         if (sizeof(dma_addr_t) > sizeof(u32))
 346                 addr |=
 347                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 348
 349         return addr;
 350 }
 351
 352 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 353                                        dma_addr_t addr, u16 len)
 354 {
 355         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 356         u16 hi_n_len = len << 4;
 357
 358         put_unaligned_le32(addr, &tb->lo);
 359         if (sizeof(dma_addr_t) > sizeof(u32))
 360                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 361
 362         tb->hi_n_len = cpu_to_le16(hi_n_len);
 363
 364         tfd->num_tbs = idx + 1;
 365 }
 366
 367 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
 368 {
 369         return tfd->num_tbs & 0x1f;
 370 }
 371
 372 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
 373                                struct iwl_cmd_meta *meta,
 374                                struct iwl_tfd *tfd)
 375 {
 376         int i;
 377         int num_tbs;
 378
 379         /* Sanity check on number of chunks */
 380         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
 381
 382         if (num_tbs >= IWL_NUM_OF_TBS) {
 383                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 384                 /* @todo issue fatal error, it is quite serious situation */
 385                 return;
 386         }
 387
 388         /* first TB is never freed - it's the scratchbuf data */
 389
 390         for (i = 1; i < num_tbs; i++)
 391                 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
 392                                  iwl_pcie_tfd_tb_get_len(tfd, i),
 393                                  DMA_TO_DEVICE);
 394
 395         tfd->num_tbs = 0;
 396 }
 397
 398 /*
 399  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 400  * @trans - transport private data
 401  * @txq - tx queue
 402  * @dma_dir - the direction of the DMA mapping
 403  *
 404  * Does NOT advance any TFD circular buffer read/write indexes
 405  * Does NOT free the TFD itself (which is within circular buffer)
 406  */
 407 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
 408 {
 409         struct iwl_tfd *tfd_tmp = txq->tfds;
 410
 411         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
 412          * idx is bounded by n_window
 413          */
 414         int rd_ptr = txq->q.read_ptr;
 415         int idx = get_cmd_index(&txq->q, rd_ptr);
 416
 417         lockdep_assert_held(&txq->lock);
 418
 419         /* We have only q->n_window txq->entries, but we use
 420          * TFD_QUEUE_SIZE_MAX tfds
 421          */
 422         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
 423
 424         /* free SKB */
 425         if (txq->entries) {
 426                 struct sk_buff *skb;
 427
 428                 skb = txq->entries[idx].skb;
 429
 430                 /* Can be called from irqs-disabled context
 431                  * If skb is not NULL, it means that the whole queue is being
 432                  * freed and that the queue is not empty - free the skb
 433                  */
 434                 if (skb) {
 435                         iwl_op_mode_free_skb(trans->op_mode, skb);
 436                         txq->entries[idx].skb = NULL;
 437                 }
 438         }
 439 }
 440
 441 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
 442                                   dma_addr_t addr, u16 len, bool reset)
 443 {
 444         struct iwl_queue *q;
 445         struct iwl_tfd *tfd, *tfd_tmp;
 446         u32 num_tbs;
 447
 448         q = &txq->q;
 449         tfd_tmp = txq->tfds;
 450         tfd = &tfd_tmp[q->write_ptr];
 451
 452         if (reset)
 453                 memset(tfd, 0, sizeof(*tfd));
 454
 455         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
 456
 457         /* Each TFD can point to a maximum 20 Tx buffers */
 458         if (num_tbs >= IWL_NUM_OF_TBS) {
 459                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 460                         IWL_NUM_OF_TBS);
 461                 return -EINVAL;
 462         }
 463
 464         if (WARN(addr & ~IWL_TX_DMA_MASK,
 465                  "Unaligned address = %llx\n", (unsigned long long)addr))
 466                 return -EINVAL;
 467
 468         iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
 469
 470         return 0;
 471 }
 472
 473 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
 474                                struct iwl_txq *txq, int slots_num,
 475                                u32 txq_id)
 476 {
 477         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 478         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 479         size_t scratchbuf_sz;
 480         int i;
 481
 482         if (WARN_ON(txq->entries || txq->tfds))
 483                 return -EINVAL;
 484
 485         setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
 486                     (unsigned long)txq);
 487         txq->trans_pcie = trans_pcie;
 488
 489         txq->q.n_window = slots_num;
 490
 491         txq->entries = kcalloc(slots_num,
 492                                sizeof(struct iwl_pcie_txq_entry),
 493                                GFP_KERNEL);
 494
 495         if (!txq->entries)
 496                 goto error;
 497
 498         if (txq_id == trans_pcie->cmd_queue)
 499                 for (i = 0; i < slots_num; i++) {
 500                         txq->entries[i].cmd =
 501                                 kmalloc(sizeof(struct iwl_device_cmd),
 502                                         GFP_KERNEL);
 503                         if (!txq->entries[i].cmd)
 504                                 goto error;
 505                 }
 506
 507         /* Circular buffer of transmit frame descriptors (TFDs),
 508          * shared with device */
 509         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 510                                        &txq->q.dma_addr, GFP_KERNEL);
 511         if (!txq->tfds)
 512                 goto error;
 513
 514         BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
 515         BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
 516                         sizeof(struct iwl_cmd_header) +
 517                         offsetof(struct iwl_tx_cmd, scratch));
 518
 519         scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
 520
 521         txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
 522                                               &txq->scratchbufs_dma,
 523                                               GFP_KERNEL);
 524         if (!txq->scratchbufs)
 525                 goto err_free_tfds;
 526
 527         txq->q.id = txq_id;
 528
 529         return 0;
 530 err_free_tfds:
 531         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
 532 error:
 533         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 534                 for (i = 0; i < slots_num; i++)
 535                         kfree(txq->entries[i].cmd);
 536         kfree(txq->entries);
 537         txq->entries = NULL;
 538
 539         return -ENOMEM;
 540
 541 }
 542
 543 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
 544                               int slots_num, u32 txq_id)
 545 {
 546         int ret;
 547
 548         txq->need_update = false;
 549
 550         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 551          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 552         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 553
 554         /* Initialize queue's high/low-water marks, and head/tail indexes */
 555         ret = iwl_queue_init(&txq->q, slots_num, txq_id);
 556         if (ret)
 557                 return ret;
 558
 559         spin_lock_init(&txq->lock);
 560
 561         /*
 562          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 563          * given Tx queue, and enable the DMA channel used for that queue.
 564          * Circular buffer (TFD queue in DRAM) physical base address */
 565         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 566                            txq->q.dma_addr >> 8);
 567
 568         return 0;
 569 }
 570
 571 /*
 572  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
 573  */
 574 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
 575 {
 576         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 577         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 578         struct iwl_queue *q = &txq->q;
 579
 580         spin_lock_bh(&txq->lock);
 581         while (q->write_ptr != q->read_ptr) {
 582                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
 583                                    txq_id, q->read_ptr);
 584                 iwl_pcie_txq_free_tfd(trans, txq);
 585                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
 586         }
 587         txq->active = false;
 588         spin_unlock_bh(&txq->lock);
 589
 590         /* just in case - this queue may have been stopped */
 591         iwl_wake_queue(trans, txq);
 592 }
 593
 594 /*
 595  * iwl_pcie_txq_free - Deallocate DMA queue.
 596  * @txq: Transmit queue to deallocate.
 597  *
 598  * Empty queue by removing and destroying all BD's.
 599  * Free all buffers.
 600  * 0-fill, but do not free "txq" descriptor structure.
 601  */
 602 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
 603 {
 604         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 605         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 606         struct device *dev = trans->dev;
 607         int i;
 608
 609         if (WARN_ON(!txq))
 610                 return;
 611
 612         iwl_pcie_txq_unmap(trans, txq_id);
 613
 614         /* De-alloc array of command/tx buffers */
 615         if (txq_id == trans_pcie->cmd_queue)
 616                 for (i = 0; i < txq->q.n_window; i++) {
 617                         kzfree(txq->entries[i].cmd);
 618                         kzfree(txq->entries[i].free_buf);
 619                 }
 620
 621         /* De-alloc circular buffer of TFDs */
 622         if (txq->tfds) {
 623                 dma_free_coherent(dev,
 624                                   sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
 625                                   txq->tfds, txq->q.dma_addr);
 626                 txq->q.dma_addr = 0;
 627                 txq->tfds = NULL;
 628
 629                 dma_free_coherent(dev,
 630                                   sizeof(*txq->scratchbufs) * txq->q.n_window,
 631                                   txq->scratchbufs, txq->scratchbufs_dma);
 632         }
 633
 634         kfree(txq->entries);
 635         txq->entries = NULL;
 636
 637         del_timer_sync(&txq->stuck_timer);
 638
 639         /* 0-fill queue descriptor structure */
 640         memset(txq, 0, sizeof(*txq));
 641 }
 642
 643 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
 644 {
 645         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 646         int nq = trans->cfg->base_params->num_of_queues;
 647         int chan;
 648         u32 reg_val;
 649         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
 650                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
 651
 652         /* make sure all queue are not stopped/used */
 653         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 654         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 655
 656         trans_pcie->scd_base_addr =
 657                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 658
 659         WARN_ON(scd_base_addr != 0 &&
 660                 scd_base_addr != trans_pcie->scd_base_addr);
 661
 662         /* reset context data, TX status and translation data */
 663         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 664                                    SCD_CONTEXT_MEM_LOWER_BOUND,
 665                             NULL, clear_dwords);
 666
 667         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 668                        trans_pcie->scd_bc_tbls.dma >> 10);
 669
 670         /* The chain extension of the SCD doesn't work well. This feature is
 671          * enabled by default by the HW, so we need to disable it manually.
 672          */
 673         if (trans->cfg->base_params->scd_chain_ext_wa)
 674                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
 675
 676         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
 677                                 trans_pcie->cmd_fifo,
 678                                 trans_pcie->cmd_q_wdg_timeout);
 679
 680         /* Activate all Tx DMA/FIFO channels */
 681         iwl_scd_activate_fifos(trans);
 682
 683         /* Enable DMA channel */
 684         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
 685                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 686                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 687                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 688
 689         /* Update FH chicken bits */
 690         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
 691         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
 692                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 693
 694         /* Enable L1-Active */
 695         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 696                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 697                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 698 }
 699
 700 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 701 {
 702         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 703         int txq_id;
 704
 705         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 706              txq_id++) {
 707                 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 708
 709                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 710                                    txq->q.dma_addr >> 8);
 711                 iwl_pcie_txq_unmap(trans, txq_id);
 712                 txq->q.read_ptr = 0;
 713                 txq->q.write_ptr = 0;
 714         }
 715
 716         /* Tell NIC where to find the "keep warm" buffer */
 717         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 718                            trans_pcie->kw.dma >> 4);
 719
 720         /*
 721          * Send 0 as the scd_base_addr since the device may have be reset
 722          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
 723          * contain garbage.
 724          */
 725         iwl_pcie_tx_start(trans, 0);
 726 }
 727
 728 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 729 {
 730         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 731         unsigned long flags;
 732         int ch, ret;
 733         u32 mask = 0;
 734
 735         spin_lock(&trans_pcie->irq_lock);
 736
 737         if (!iwl_trans_grab_nic_access(trans, false, &flags))
 738                 goto out;
 739
 740         /* Stop each Tx DMA channel */
 741         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 742                 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 743                 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 744         }
 745
 746         /* Wait for DMA channels to be idle */
 747         ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
 748         if (ret < 0)
 749                 IWL_ERR(trans,
 750                         "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
 751                         ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
 752
 753         iwl_trans_release_nic_access(trans, &flags);
 754
 755 out:
 756         spin_unlock(&trans_pcie->irq_lock);
 757 }
 758
 759 /*
 760  * iwl_pcie_tx_stop - Stop all Tx DMA channels
 761  */
 762 int iwl_pcie_tx_stop(struct iwl_trans *trans)
 763 {
 764         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 765         int txq_id;
 766
 767         /* Turn off all Tx DMA fifos */
 768         iwl_scd_deactivate_fifos(trans);
 769
 770         /* Turn off all Tx DMA channels */
 771         iwl_pcie_tx_stop_fh(trans);
 772
 773         /*
 774          * This function can be called before the op_mode disabled the
 775          * queues. This happens when we have an rfkill interrupt.
 776          * Since we stop Tx altogether - mark the queues as stopped.
 777          */
 778         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 779         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 780
 781         /* This can happen: start_hw, stop_device */
 782         if (!trans_pcie->txq)
 783                 return 0;
 784
 785         /* Unmap DMA from host system and free skb's */
 786         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 787              txq_id++)
 788                 iwl_pcie_txq_unmap(trans, txq_id);
 789
 790         return 0;
 791 }
 792
 793 /*
 794  * iwl_trans_tx_free - Free TXQ Context
 795  *
 796  * Destroy all TX DMA queues and structures
 797  */
 798 void iwl_pcie_tx_free(struct iwl_trans *trans)
 799 {
 800         int txq_id;
 801         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 802
 803         /* Tx queues */
 804         if (trans_pcie->txq) {
 805                 for (txq_id = 0;
 806                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 807                         iwl_pcie_txq_free(trans, txq_id);
 808         }
 809
 810         kfree(trans_pcie->txq);
 811         trans_pcie->txq = NULL;
 812
 813         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
 814
 815         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 816 }
 817
 818 /*
 819  * iwl_pcie_tx_alloc - allocate TX context
 820  * Allocate all Tx DMA structures and initialize them
 821  */
 822 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
 823 {
 824         int ret;
 825         int txq_id, slots_num;
 826         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 827
 828         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 829                         sizeof(struct iwlagn_scd_bc_tbl);
 830
 831         /*It is not allowed to alloc twice, so warn when this happens.
 832          * We cannot rely on the previous allocation, so free and fail */
 833         if (WARN_ON(trans_pcie->txq)) {
 834                 ret = -EINVAL;
 835                 goto error;
 836         }
 837
 838         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 839                                    scd_bc_tbls_size);
 840         if (ret) {
 841                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 842                 goto error;
 843         }
 844
 845         /* Alloc keep-warm buffer */
 846         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 847         if (ret) {
 848                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 849                 goto error;
 850         }
 851
 852         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 853                                   sizeof(struct iwl_txq), GFP_KERNEL);
 854         if (!trans_pcie->txq) {
 855                 IWL_ERR(trans, "Not enough memory for txq\n");
 856                 ret = -ENOMEM;
 857                 goto error;
 858         }
 859
 860         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 861         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 862              txq_id++) {
 863                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 864                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 865                 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
 866                                           slots_num, txq_id);
 867                 if (ret) {
 868                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 869                         goto error;
 870                 }
 871         }
 872
 873         return 0;
 874
 875 error:
 876         iwl_pcie_tx_free(trans);
 877
 878         return ret;
 879 }
 880 int iwl_pcie_tx_init(struct iwl_trans *trans)
 881 {
 882         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 883         int ret;
 884         int txq_id, slots_num;
 885         bool alloc = false;
 886
 887         if (!trans_pcie->txq) {
 888                 ret = iwl_pcie_tx_alloc(trans);
 889                 if (ret)
 890                         goto error;
 891                 alloc = true;
 892         }
 893
 894         spin_lock(&trans_pcie->irq_lock);
 895
 896         /* Turn off all Tx DMA fifos */
 897         iwl_scd_deactivate_fifos(trans);
 898
 899         /* Tell NIC where to find the "keep warm" buffer */
 900         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 901                            trans_pcie->kw.dma >> 4);
 902
 903         spin_unlock(&trans_pcie->irq_lock);
 904
 905         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 906         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 907              txq_id++) {
 908                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 909                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 910                 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
 911                                          slots_num, txq_id);
 912                 if (ret) {
 913                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 914                         goto error;
 915                 }
 916         }
 917
 918         if (trans->cfg->base_params->num_of_queues > 20)
 919                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
 920                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
 921
 922         return 0;
 923 error:
 924         /*Upon error, free only if we allocated something */
 925         if (alloc)
 926                 iwl_pcie_tx_free(trans);
 927         return ret;
 928 }
 929
 930 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
 931 {
 932         if (!txq->wd_timeout)
 933                 return;
 934
 935         /*
 936          * if empty delete timer, otherwise move timer forward
 937          * since we're making progress on this queue
 938          */
 939         if (txq->q.read_ptr == txq->q.write_ptr)
 940                 del_timer(&txq->stuck_timer);
 941         else
 942                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
 943 }
 944
 945 /* Frees buffers until index _not_ inclusive */
 946 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
 947                             struct sk_buff_head *skbs)
 948 {
 949         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 950         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 951         int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
 952         struct iwl_queue *q = &txq->q;
 953         int last_to_free;
 954
 955         /* This function is not meant to release cmd queue*/
 956         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
 957                 return;
 958
 959         spin_lock_bh(&txq->lock);
 960
 961         if (!txq->active) {
 962                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
 963                                     txq_id, ssn);
 964                 goto out;
 965         }
 966
 967         if (txq->q.read_ptr == tfd_num)
 968                 goto out;
 969
 970         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
 971                            txq_id, txq->q.read_ptr, tfd_num, ssn);
 972
 973         /*Since we free until index _not_ inclusive, the one before index is
 974          * the last we will free. This one must be used */
 975         last_to_free = iwl_queue_dec_wrap(tfd_num);
 976
 977         if (!iwl_queue_used(q, last_to_free)) {
 978                 IWL_ERR(trans,
 979                         "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
 980                         __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
 981                         q->write_ptr, q->read_ptr);
 982                 goto out;
 983         }
 984
 985         if (WARN_ON(!skb_queue_empty(skbs)))
 986                 goto out;
 987
 988         for (;
 989              q->read_ptr != tfd_num;
 990              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
 991
 992                 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
 993                         continue;
 994
 995                 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
 996
 997                 txq->entries[txq->q.read_ptr].skb = NULL;
 998
 999                 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1000
1001                 iwl_pcie_txq_free_tfd(trans, txq);
1002         }
1003
1004         iwl_pcie_txq_progress(txq);
1005
1006         if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1007                 iwl_wake_queue(trans, txq);
1008
1009         if (q->read_ptr == q->write_ptr) {
1010                 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
1011                 iwl_trans_pcie_unref(trans);
1012         }
1013
1014 out:
1015         spin_unlock_bh(&txq->lock);
1016 }
1017
1018 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1019                                       const struct iwl_host_cmd *cmd)
1020 {
1021         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1022         int ret;
1023
1024         lockdep_assert_held(&trans_pcie->reg_lock);
1025
1026         if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1027             !trans_pcie->ref_cmd_in_flight) {
1028                 trans_pcie->ref_cmd_in_flight = true;
1029                 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1030                 iwl_trans_pcie_ref(trans);
1031         }
1032
1033         if (trans_pcie->cmd_in_flight)
1034                 return 0;
1035
1036         trans_pcie->cmd_in_flight = true;
1037
1038         /*
1039          * wake up the NIC to make sure that the firmware will see the host
1040          * command - we will let the NIC sleep once all the host commands
1041          * returned. This needs to be done only on NICs that have
1042          * apmg_wake_up_wa set.
1043          */
1044         if (trans->cfg->base_params->apmg_wake_up_wa) {
1045                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1046                                          CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1047                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1048                         udelay(2);
1049
1050                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1051                                    CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1052                                    (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1053                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1054                                    15000);
1055                 if (ret < 0) {
1056                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1057                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1058                         trans_pcie->cmd_in_flight = false;
1059                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1060                         return -EIO;
1061                 }
1062         }
1063
1064         return 0;
1065 }
1066
1067 static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
1068 {
1069         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1070
1071         lockdep_assert_held(&trans_pcie->reg_lock);
1072
1073         if (trans_pcie->ref_cmd_in_flight) {
1074                 trans_pcie->ref_cmd_in_flight = false;
1075                 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
1076                 iwl_trans_pcie_unref(trans);
1077         }
1078
1079         if (WARN_ON(!trans_pcie->cmd_in_flight))
1080                 return 0;
1081
1082         trans_pcie->cmd_in_flight = false;
1083
1084         if (trans->cfg->base_params->apmg_wake_up_wa)
1085                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1086                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1087
1088         return 0;
1089 }
1090
1091 /*
1092  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1093  *
1094  * When FW advances 'R' index, all entries between old and new 'R' index
1095  * need to be reclaimed. As result, some free space forms.  If there is
1096  * enough free space (> low mark), wake the stack that feeds us.
1097  */
1098 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1099 {
1100         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1101         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1102         struct iwl_queue *q = &txq->q;
1103         unsigned long flags;
1104         int nfreed = 0;
1105
1106         lockdep_assert_held(&txq->lock);
1107
1108         if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1109                 IWL_ERR(trans,
1110                         "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1111                         __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1112                         q->write_ptr, q->read_ptr);
1113                 return;
1114         }
1115
1116         for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1117              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1118
1119                 if (nfreed++ > 0) {
1120                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1121                                 idx, q->write_ptr, q->read_ptr);
1122                         iwl_force_nmi(trans);
1123                 }
1124         }
1125
1126         if (q->read_ptr == q->write_ptr) {
1127                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1128                 iwl_pcie_clear_cmd_in_flight(trans);
1129                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1130         }
1131
1132         iwl_pcie_txq_progress(txq);
1133 }
1134
1135 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1136                                  u16 txq_id)
1137 {
1138         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1139         u32 tbl_dw_addr;
1140         u32 tbl_dw;
1141         u16 scd_q2ratid;
1142
1143         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1144
1145         tbl_dw_addr = trans_pcie->scd_base_addr +
1146                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1147
1148         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1149
1150         if (txq_id & 0x1)
1151                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1152         else
1153                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1154
1155         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1156
1157         return 0;
1158 }
1159
1160 /* Receiver address (actually, Rx station's index into station table),
1161  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1162 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1163
1164 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1165                                const struct iwl_trans_txq_scd_cfg *cfg,
1166                                unsigned int wdg_timeout)
1167 {
1168         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1169         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1170         int fifo = -1;
1171
1172         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1173                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1174
1175         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1176
1177         if (cfg) {
1178                 fifo = cfg->fifo;
1179
1180                 /* Disable the scheduler prior configuring the cmd queue */
1181                 if (txq_id == trans_pcie->cmd_queue &&
1182                     trans_pcie->scd_set_active)
1183                         iwl_scd_enable_set_active(trans, 0);
1184
1185                 /* Stop this Tx queue before configuring it */
1186                 iwl_scd_txq_set_inactive(trans, txq_id);
1187
1188                 /* Set this queue as a chain-building queue unless it is CMD */
1189                 if (txq_id != trans_pcie->cmd_queue)
1190                         iwl_scd_txq_set_chain(trans, txq_id);
1191
1192                 if (cfg->aggregate) {
1193                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1194
1195                         /* Map receiver-address / traffic-ID to this queue */
1196                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1197
1198                         /* enable aggregations for the queue */
1199                         iwl_scd_txq_enable_agg(trans, txq_id);
1200                         txq->ampdu = true;
1201                 } else {
1202                         /*
1203                          * disable aggregations for the queue, this will also
1204                          * make the ra_tid mapping configuration irrelevant
1205                          * since it is now a non-AGG queue.
1206                          */
1207                         iwl_scd_txq_disable_agg(trans, txq_id);
1208
1209                         ssn = txq->q.read_ptr;
1210                 }
1211         }
1212
1213         /* Place first TFD at index corresponding to start sequence number.
1214          * Assumes that ssn_idx is valid (!= 0xFFF) */
1215         txq->q.read_ptr = (ssn & 0xff);
1216         txq->q.write_ptr = (ssn & 0xff);
1217         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1218                            (ssn & 0xff) | (txq_id << 8));
1219
1220         if (cfg) {
1221                 u8 frame_limit = cfg->frame_limit;
1222
1223                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1224
1225                 /* Set up Tx window size and frame limit for this queue */
1226                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1227                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1228                 iwl_trans_write_mem32(trans,
1229                         trans_pcie->scd_base_addr +
1230                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1231                         ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1232                                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1233                         ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1234                                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1235
1236                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1237                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1238                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1239                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1240                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1241                                SCD_QUEUE_STTS_REG_MSK);
1242
1243                 /* enable the scheduler for this queue (only) */
1244                 if (txq_id == trans_pcie->cmd_queue &&
1245                     trans_pcie->scd_set_active)
1246                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1247
1248                 IWL_DEBUG_TX_QUEUES(trans,
1249                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1250                                     txq_id, fifo, ssn & 0xff);
1251         } else {
1252                 IWL_DEBUG_TX_QUEUES(trans,
1253                                     "Activate queue %d WrPtr: %d\n",
1254                                     txq_id, ssn & 0xff);
1255         }
1256
1257         txq->active = true;
1258 }
1259
1260 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1261                                 bool configure_scd)
1262 {
1263         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1264         u32 stts_addr = trans_pcie->scd_base_addr +
1265                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1266         static const u32 zero_val[4] = {};
1267
1268         /*
1269          * Upon HW Rfkill - we stop the device, and then stop the queues
1270          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1271          * allow the op_mode to call txq_disable after it already called
1272          * stop_device.
1273          */
1274         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1275                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1276                           "queue %d not used", txq_id);
1277                 return;
1278         }
1279
1280         if (configure_scd) {
1281                 iwl_scd_txq_set_inactive(trans, txq_id);
1282
1283                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1284                                     ARRAY_SIZE(zero_val));
1285         }
1286
1287         iwl_pcie_txq_unmap(trans, txq_id);
1288         trans_pcie->txq[txq_id].ampdu = false;
1289
1290         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1291 }
1292
1293 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1294
1295 /*
1296  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1297  * @priv: device private data point
1298  * @cmd: a pointer to the ucode command structure
1299  *
1300  * The function returns < 0 values to indicate the operation
1301  * failed. On success, it returns the index (>= 0) of command in the
1302  * command queue.
1303  */
1304 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1305                                  struct iwl_host_cmd *cmd)
1306 {
1307         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1308         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1309         struct iwl_queue *q = &txq->q;
1310         struct iwl_device_cmd *out_cmd;
1311         struct iwl_cmd_meta *out_meta;
1312         unsigned long flags;
1313         void *dup_buf = NULL;
1314         dma_addr_t phys_addr;
1315         int idx;
1316         u16 copy_size, cmd_size, scratch_size;
1317         bool had_nocopy = false;
1318         int i, ret;
1319         u32 cmd_pos;
1320         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1321         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1322
1323         copy_size = sizeof(out_cmd->hdr);
1324         cmd_size = sizeof(out_cmd->hdr);
1325
1326         /* need one for the header if the first is NOCOPY */
1327         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1328
1329         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1330                 cmddata[i] = cmd->data[i];
1331                 cmdlen[i] = cmd->len[i];
1332
1333                 if (!cmd->len[i])
1334                         continue;
1335
1336                 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1337                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1338                         int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1339
1340                         if (copy > cmdlen[i])
1341                                 copy = cmdlen[i];
1342                         cmdlen[i] -= copy;
1343                         cmddata[i] += copy;
1344                         copy_size += copy;
1345                 }
1346
1347                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1348                         had_nocopy = true;
1349                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1350                                 idx = -EINVAL;
1351                                 goto free_dup_buf;
1352                         }
1353                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1354                         /*
1355                          * This is also a chunk that isn't copied
1356                          * to the static buffer so set had_nocopy.
1357                          */
1358                         had_nocopy = true;
1359
1360                         /* only allowed once */
1361                         if (WARN_ON(dup_buf)) {
1362                                 idx = -EINVAL;
1363                                 goto free_dup_buf;
1364                         }
1365
1366                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1367                                           GFP_ATOMIC);
1368                         if (!dup_buf)
1369                                 return -ENOMEM;
1370                 } else {
1371                         /* NOCOPY must not be followed by normal! */
1372                         if (WARN_ON(had_nocopy)) {
1373                                 idx = -EINVAL;
1374                                 goto free_dup_buf;
1375                         }
1376                         copy_size += cmdlen[i];
1377                 }
1378                 cmd_size += cmd->len[i];
1379         }
1380
1381         /*
1382          * If any of the command structures end up being larger than
1383          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1384          * allocated into separate TFDs, then we will need to
1385          * increase the size of the buffers.
1386          */
1387         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1388                  "Command %s (%#x) is too large (%d bytes)\n",
1389                  get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1390                 idx = -EINVAL;
1391                 goto free_dup_buf;
1392         }
1393
1394         spin_lock_bh(&txq->lock);
1395
1396         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1397                 spin_unlock_bh(&txq->lock);
1398
1399                 IWL_ERR(trans, "No space in command queue\n");
1400                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1401                 idx = -ENOSPC;
1402                 goto free_dup_buf;
1403         }
1404
1405         idx = get_cmd_index(q, q->write_ptr);
1406         out_cmd = txq->entries[idx].cmd;
1407         out_meta = &txq->entries[idx].meta;
1408
1409         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1410         if (cmd->flags & CMD_WANT_SKB)
1411                 out_meta->source = cmd;
1412
1413         /* set up the header */
1414
1415         out_cmd->hdr.cmd = cmd->id;
1416         out_cmd->hdr.flags = 0;
1417         out_cmd->hdr.sequence =
1418                 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1419                                          INDEX_TO_SEQ(q->write_ptr));
1420
1421         /* and copy the data that needs to be copied */
1422         cmd_pos = offsetof(struct iwl_device_cmd, payload);
1423         copy_size = sizeof(out_cmd->hdr);
1424         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1425                 int copy;
1426
1427                 if (!cmd->len[i])
1428                         continue;
1429
1430                 /* copy everything if not nocopy/dup */
1431                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1432                                            IWL_HCMD_DFL_DUP))) {
1433                         copy = cmd->len[i];
1434
1435                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1436                         cmd_pos += copy;
1437                         copy_size += copy;
1438                         continue;
1439                 }
1440
1441                 /*
1442                  * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1443                  * in total (for the scratchbuf handling), but copy up to what
1444                  * we can fit into the payload for debug dump purposes.
1445                  */
1446                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1447
1448                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1449                 cmd_pos += copy;
1450
1451                 /* However, treat copy_size the proper way, we need it below */
1452                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1453                         copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1454
1455                         if (copy > cmd->len[i])
1456                                 copy = cmd->len[i];
1457                         copy_size += copy;
1458                 }
1459         }
1460
1461         IWL_DEBUG_HC(trans,
1462                      "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1463                      get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1464                      out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1465                      cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1466
1467         /* start the TFD with the scratchbuf */
1468         scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1469         memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1470         iwl_pcie_txq_build_tfd(trans, txq,
1471                                iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1472                                scratch_size, true);
1473
1474         /* map first command fragment, if any remains */
1475         if (copy_size > scratch_size) {
1476                 phys_addr = dma_map_single(trans->dev,
1477                                            ((u8 *)&out_cmd->hdr) + scratch_size,
1478                                            copy_size - scratch_size,
1479                                            DMA_TO_DEVICE);
1480                 if (dma_mapping_error(trans->dev, phys_addr)) {
1481                         iwl_pcie_tfd_unmap(trans, out_meta,
1482                                            &txq->tfds[q->write_ptr]);
1483                         idx = -ENOMEM;
1484                         goto out;
1485                 }
1486
1487                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1488                                        copy_size - scratch_size, false);
1489         }
1490
1491         /* map the remaining (adjusted) nocopy/dup fragments */
1492         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1493                 const void *data = cmddata[i];
1494
1495                 if (!cmdlen[i])
1496                         continue;
1497                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1498                                            IWL_HCMD_DFL_DUP)))
1499                         continue;
1500                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1501                         data = dup_buf;
1502                 phys_addr = dma_map_single(trans->dev, (void *)data,
1503                                            cmdlen[i], DMA_TO_DEVICE);
1504                 if (dma_mapping_error(trans->dev, phys_addr)) {
1505                         iwl_pcie_tfd_unmap(trans, out_meta,
1506                                            &txq->tfds[q->write_ptr]);
1507                         idx = -ENOMEM;
1508                         goto out;
1509                 }
1510
1511                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1512         }
1513
1514         out_meta->flags = cmd->flags;
1515         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1516                 kzfree(txq->entries[idx].free_buf);
1517         txq->entries[idx].free_buf = dup_buf;
1518
1519         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1520
1521         /* start timer if queue currently empty */
1522         if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1523                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1524
1525         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1526         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1527         if (ret < 0) {
1528                 idx = ret;
1529                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1530                 goto out;
1531         }
1532
1533         /* Increment and update queue's write index */
1534         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1535         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1536
1537         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1538
1539  out:
1540         spin_unlock_bh(&txq->lock);
1541  free_dup_buf:
1542         if (idx < 0)
1543                 kfree(dup_buf);
1544         return idx;
1545 }
1546
1547 /*
1548  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1549  * @rxb: Rx buffer to reclaim
1550  * @handler_status: return value of the handler of the command
1551  *      (put in setup_rx_handlers)
1552  *
1553  * If an Rx buffer has an async callback associated with it the callback
1554  * will be executed.  The attached skb (if present) will only be freed
1555  * if the callback returns 1
1556  */
1557 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1558                             struct iwl_rx_cmd_buffer *rxb, int handler_status)
1559 {
1560         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1561         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1562         int txq_id = SEQ_TO_QUEUE(sequence);
1563         int index = SEQ_TO_INDEX(sequence);
1564         int cmd_index;
1565         struct iwl_device_cmd *cmd;
1566         struct iwl_cmd_meta *meta;
1567         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1568         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1569
1570         /* If a Tx command is being handled and it isn't in the actual
1571          * command queue then there a command routing bug has been introduced
1572          * in the queue management code. */
1573         if (WARN(txq_id != trans_pcie->cmd_queue,
1574                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1575                  txq_id, trans_pcie->cmd_queue, sequence,
1576                  trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1577                  trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1578                 iwl_print_hex_error(trans, pkt, 32);
1579                 return;
1580         }
1581
1582         spin_lock_bh(&txq->lock);
1583
1584         cmd_index = get_cmd_index(&txq->q, index);
1585         cmd = txq->entries[cmd_index].cmd;
1586         meta = &txq->entries[cmd_index].meta;
1587
1588         iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1589
1590         /* Input error checking is done when commands are added to queue. */
1591         if (meta->flags & CMD_WANT_SKB) {
1592                 struct page *p = rxb_steal_page(rxb);
1593
1594                 meta->source->resp_pkt = pkt;
1595                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1596                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1597                 meta->source->handler_status = handler_status;
1598         }
1599
1600         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1601
1602         if (!(meta->flags & CMD_ASYNC)) {
1603                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1604                         IWL_WARN(trans,
1605                                  "HCMD_ACTIVE already clear for command %s\n",
1606                                  get_cmd_string(trans_pcie, cmd->hdr.cmd));
1607                 }
1608                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1609                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1610                                get_cmd_string(trans_pcie, cmd->hdr.cmd));
1611                 wake_up(&trans_pcie->wait_command_queue);
1612         }
1613
1614         meta->flags = 0;
1615
1616         spin_unlock_bh(&txq->lock);
1617 }
1618
1619 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1620
1621 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1622                                     struct iwl_host_cmd *cmd)
1623 {
1624         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1625         int ret;
1626
1627         /* An asynchronous command can not expect an SKB to be set. */
1628         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1629                 return -EINVAL;
1630
1631         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1632         if (ret < 0) {
1633                 IWL_ERR(trans,
1634                         "Error sending %s: enqueue_hcmd failed: %d\n",
1635                         get_cmd_string(trans_pcie, cmd->id), ret);
1636                 return ret;
1637         }
1638         return 0;
1639 }
1640
1641 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1642                                    struct iwl_host_cmd *cmd)
1643 {
1644         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1645         int cmd_idx;
1646         int ret;
1647
1648         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1649                        get_cmd_string(trans_pcie, cmd->id));
1650
1651         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1652                                   &trans->status),
1653                  "Command %s: a command is already active!\n",
1654                  get_cmd_string(trans_pcie, cmd->id)))
1655                 return -EIO;
1656
1657         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1658                        get_cmd_string(trans_pcie, cmd->id));
1659
1660         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1661         if (cmd_idx < 0) {
1662                 ret = cmd_idx;
1663                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1664                 IWL_ERR(trans,
1665                         "Error sending %s: enqueue_hcmd failed: %d\n",
1666                         get_cmd_string(trans_pcie, cmd->id), ret);
1667                 return ret;
1668         }
1669
1670         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1671                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1672                                            &trans->status),
1673                                  HOST_COMPLETE_TIMEOUT);
1674         if (!ret) {
1675                 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1676                 struct iwl_queue *q = &txq->q;
1677
1678                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1679                         get_cmd_string(trans_pcie, cmd->id),
1680                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1681
1682                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1683                         q->read_ptr, q->write_ptr);
1684
1685                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1686                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1687                                get_cmd_string(trans_pcie, cmd->id));
1688                 ret = -ETIMEDOUT;
1689
1690                 iwl_force_nmi(trans);
1691                 iwl_trans_fw_error(trans);
1692
1693                 goto cancel;
1694         }
1695
1696         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1697                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1698                         get_cmd_string(trans_pcie, cmd->id));
1699                 dump_stack();
1700                 ret = -EIO;
1701                 goto cancel;
1702         }
1703
1704         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1705             test_bit(STATUS_RFKILL, &trans->status)) {
1706                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1707                 ret = -ERFKILL;
1708                 goto cancel;
1709         }
1710
1711         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1712                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1713                         get_cmd_string(trans_pcie, cmd->id));
1714                 ret = -EIO;
1715                 goto cancel;
1716         }
1717
1718         return 0;
1719
1720 cancel:
1721         if (cmd->flags & CMD_WANT_SKB) {
1722                 /*
1723                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1724                  * TX cmd queue. Otherwise in case the cmd comes
1725                  * in later, it will possibly set an invalid
1726                  * address (cmd->meta.source).
1727                  */
1728                 trans_pcie->txq[trans_pcie->cmd_queue].
1729                         entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1730         }
1731
1732         if (cmd->resp_pkt) {
1733                 iwl_free_resp(cmd);
1734                 cmd->resp_pkt = NULL;
1735         }
1736
1737         return ret;
1738 }
1739
1740 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1741 {
1742         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1743             test_bit(STATUS_RFKILL, &trans->status)) {
1744                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1745                                   cmd->id);
1746                 return -ERFKILL;
1747         }
1748
1749         if (cmd->flags & CMD_ASYNC)
1750                 return iwl_pcie_send_hcmd_async(trans, cmd);
1751
1752         /* We still can fail on RFKILL that can be asserted while we wait */
1753         return iwl_pcie_send_hcmd_sync(trans, cmd);
1754 }
1755
1756 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1757                       struct iwl_device_cmd *dev_cmd, int txq_id)
1758 {
1759         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1760         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1761         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1762         struct iwl_cmd_meta *out_meta;
1763         struct iwl_txq *txq;
1764         struct iwl_queue *q;
1765         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1766         void *tb1_addr;
1767         u16 len, tb1_len, tb2_len;
1768         bool wait_write_ptr;
1769         __le16 fc = hdr->frame_control;
1770         u8 hdr_len = ieee80211_hdrlen(fc);
1771         u16 wifi_seq;
1772
1773         txq = &trans_pcie->txq[txq_id];
1774         q = &txq->q;
1775
1776         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1777                       "TX on unused queue %d\n", txq_id))
1778                 return -EINVAL;
1779
1780         spin_lock(&txq->lock);
1781
1782         /* In AGG mode, the index in the ring must correspond to the WiFi
1783          * sequence number. This is a HW requirements to help the SCD to parse
1784          * the BA.
1785          * Check here that the packets are in the right place on the ring.
1786          */
1787         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1788         WARN_ONCE(txq->ampdu &&
1789                   (wifi_seq & 0xff) != q->write_ptr,
1790                   "Q: %d WiFi Seq %d tfdNum %d",
1791                   txq_id, wifi_seq, q->write_ptr);
1792
1793         /* Set up driver data for this TFD */
1794         txq->entries[q->write_ptr].skb = skb;
1795         txq->entries[q->write_ptr].cmd = dev_cmd;
1796
1797         dev_cmd->hdr.sequence =
1798                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1799                             INDEX_TO_SEQ(q->write_ptr)));
1800
1801         tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1802         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1803                        offsetof(struct iwl_tx_cmd, scratch);
1804
1805         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1806         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1807
1808         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1809         out_meta = &txq->entries[q->write_ptr].meta;
1810
1811         /*
1812          * The second TB (tb1) points to the remainder of the TX command
1813          * and the 802.11 header - dword aligned size
1814          * (This calculation modifies the TX command, so do it before the
1815          * setup of the first TB)
1816          */
1817         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1818               hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1819         tb1_len = ALIGN(len, 4);
1820
1821         /* Tell NIC about any 2-byte padding after MAC header */
1822         if (tb1_len != len)
1823                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1824
1825         /* The first TB points to the scratchbuf data - min_copy bytes */
1826         memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1827                IWL_HCMD_SCRATCHBUF_SIZE);
1828         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1829                                IWL_HCMD_SCRATCHBUF_SIZE, true);
1830
1831         /* there must be data left over for TB1 or this code must be changed */
1832         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1833
1834         /* map the data for TB1 */
1835         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1836         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1837         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1838                 goto out_err;
1839         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
1840
1841         /*
1842          * Set up TFD's third entry to point directly to remainder
1843          * of skb, if any (802.11 null frames have no payload).
1844          */
1845         tb2_len = skb->len - hdr_len;
1846         if (tb2_len > 0) {
1847                 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1848                                                      skb->data + hdr_len,
1849                                                      tb2_len, DMA_TO_DEVICE);
1850                 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1851                         iwl_pcie_tfd_unmap(trans, out_meta,
1852                                            &txq->tfds[q->write_ptr]);
1853                         goto out_err;
1854                 }
1855                 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1856         }
1857
1858         /* Set up entry for this TFD in Tx byte-count array */
1859         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1860
1861         trace_iwlwifi_dev_tx(trans->dev, skb,
1862                              &txq->tfds[txq->q.write_ptr],
1863                              sizeof(struct iwl_tfd),
1864                              &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1865                              skb->data + hdr_len, tb2_len);
1866         trace_iwlwifi_dev_tx_data(trans->dev, skb,
1867                                   skb->data + hdr_len, tb2_len);
1868
1869         wait_write_ptr = ieee80211_has_morefrags(fc);
1870
1871         /* start timer if queue currently empty */
1872         if (q->read_ptr == q->write_ptr) {
1873                 if (txq->wd_timeout)
1874                         mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1875                 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
1876                 iwl_trans_pcie_ref(trans);
1877         }
1878
1879         /* Tell device the write index *just past* this latest filled TFD */
1880         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1881         if (!wait_write_ptr)
1882                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1883
1884         /*
1885          * At this point the frame is "transmitted" successfully
1886          * and we will get a TX status notification eventually.
1887          */
1888         if (iwl_queue_space(q) < q->high_mark) {
1889                 if (wait_write_ptr)
1890                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1891                 else
1892                         iwl_stop_queue(trans, txq);
1893         }
1894         spin_unlock(&txq->lock);
1895         return 0;
1896 out_err:
1897         spin_unlock(&txq->lock);
1898         return -1;
1899 }