drivers/net/wireless/p54/p54pci.c

   1
   2 /*
   3  * Linux device driver for PCI based Prism54
   4  *
   5  * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
   6  * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
   7  *
   8  * Based on the islsm (softmac prism54) driver, which is:
   9  * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/pci.h>
  18 #include <linux/slab.h>
  19 #include <linux/firmware.h>
  20 #include <linux/etherdevice.h>
  21 #include <linux/delay.h>
  22 #include <linux/completion.h>
  23 #include <linux/module.h>
  24 #include <net/mac80211.h>
  25
  26 #include "p54.h"
  27 #include "lmac.h"
  28 #include "p54pci.h"
  29
  30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  31 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  32 MODULE_LICENSE("GPL");
  33 MODULE_ALIAS("prism54pci");
  34 MODULE_FIRMWARE("isl3886pci");
  35
  36 static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
  37         /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  38         { PCI_DEVICE(0x1260, 0x3890) },
  39         /* 3COM 3CRWE154G72 Wireless LAN adapter */
  40         { PCI_DEVICE(0x10b7, 0x6001) },
  41         /* Intersil PRISM Indigo Wireless LAN adapter */
  42         { PCI_DEVICE(0x1260, 0x3877) },
  43         /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  44         { PCI_DEVICE(0x1260, 0x3886) },
  45         /* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
  46         { PCI_DEVICE(0x1260, 0xffff) },
  47         { },
  48 };
  49
  50 MODULE_DEVICE_TABLE(pci, p54p_table);
  51
  52 static int p54p_upload_firmware(struct ieee80211_hw *dev)
  53 {
  54         struct p54p_priv *priv = dev->priv;
  55         __le32 reg;
  56         int err;
  57         __le32 *data;
  58         u32 remains, left, device_addr;
  59
  60         P54P_WRITE(int_enable, cpu_to_le32(0));
  61         P54P_READ(int_enable);
  62         udelay(10);
  63
  64         reg = P54P_READ(ctrl_stat);
  65         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  66         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  67         P54P_WRITE(ctrl_stat, reg);
  68         P54P_READ(ctrl_stat);
  69         udelay(10);
  70
  71         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  72         P54P_WRITE(ctrl_stat, reg);
  73         wmb();
  74         udelay(10);
  75
  76         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  77         P54P_WRITE(ctrl_stat, reg);
  78         wmb();
  79
  80         /* wait for the firmware to reset properly */
  81         mdelay(10);
  82
  83         err = p54_parse_firmware(dev, priv->firmware);
  84         if (err)
  85                 return err;
  86
  87         if (priv->common.fw_interface != FW_LM86) {
  88                 dev_err(&priv->pdev->dev, "wrong firmware, "
  89                         "please get a LM86(PCI) firmware a try again.\n");
  90                 return -EINVAL;
  91         }
  92
  93         data = (__le32 *) priv->firmware->data;
  94         remains = priv->firmware->size;
  95         device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  96         while (remains) {
  97                 u32 i = 0;
  98                 left = min((u32)0x1000, remains);
  99                 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
 100                 P54P_READ(int_enable);
 101
 102                 device_addr += 0x1000;
 103                 while (i < left) {
 104                         P54P_WRITE(direct_mem_win[i], *data++);
 105                         i += sizeof(u32);
 106                 }
 107
 108                 remains -= left;
 109                 P54P_READ(int_enable);
 110         }
 111
 112         reg = P54P_READ(ctrl_stat);
 113         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
 114         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 115         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
 116         P54P_WRITE(ctrl_stat, reg);
 117         P54P_READ(ctrl_stat);
 118         udelay(10);
 119
 120         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
 121         P54P_WRITE(ctrl_stat, reg);
 122         wmb();
 123         udelay(10);
 124
 125         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 126         P54P_WRITE(ctrl_stat, reg);
 127         wmb();
 128         udelay(10);
 129
 130         /* wait for the firmware to boot properly */
 131         mdelay(100);
 132
 133         return 0;
 134 }
 135
 136 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
 137         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 138         struct sk_buff **rx_buf, u32 index)
 139 {
 140         struct p54p_priv *priv = dev->priv;
 141         struct p54p_ring_control *ring_control = priv->ring_control;
 142         u32 limit, idx, i;
 143
 144         idx = le32_to_cpu(ring_control->host_idx[ring_index]);
 145         limit = idx;
 146         limit -= index;
 147         limit = ring_limit - limit;
 148
 149         i = idx % ring_limit;
 150         while (limit-- > 1) {
 151                 struct p54p_desc *desc = &ring[i];
 152
 153                 if (!desc->host_addr) {
 154                         struct sk_buff *skb;
 155                         dma_addr_t mapping;
 156                         skb = dev_alloc_skb(priv->common.rx_mtu + 32);
 157                         if (!skb)
 158                                 break;
 159
 160                         mapping = pci_map_single(priv->pdev,
 161                                                  skb_tail_pointer(skb),
 162                                                  priv->common.rx_mtu + 32,
 163                                                  PCI_DMA_FROMDEVICE);
 164
 165                         if (pci_dma_mapping_error(priv->pdev, mapping)) {
 166                                 dev_kfree_skb_any(skb);
 167                                 dev_err(&priv->pdev->dev,
 168                                         "RX DMA Mapping error\n");
 169                                 break;
 170                         }
 171
 172                         desc->host_addr = cpu_to_le32(mapping);
 173                         desc->device_addr = 0;  // FIXME: necessary?
 174                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 175                         desc->flags = 0;
 176                         rx_buf[i] = skb;
 177                 }
 178
 179                 i++;
 180                 idx++;
 181                 i %= ring_limit;
 182         }
 183
 184         wmb();
 185         ring_control->host_idx[ring_index] = cpu_to_le32(idx);
 186 }
 187
 188 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
 189         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 190         struct sk_buff **rx_buf)
 191 {
 192         struct p54p_priv *priv = dev->priv;
 193         struct p54p_ring_control *ring_control = priv->ring_control;
 194         struct p54p_desc *desc;
 195         u32 idx, i;
 196
 197         i = (*index) % ring_limit;
 198         (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
 199         idx %= ring_limit;
 200         while (i != idx) {
 201                 u16 len;
 202                 struct sk_buff *skb;
 203                 dma_addr_t dma_addr;
 204                 desc = &ring[i];
 205                 len = le16_to_cpu(desc->len);
 206                 skb = rx_buf[i];
 207
 208                 if (!skb) {
 209                         i++;
 210                         i %= ring_limit;
 211                         continue;
 212                 }
 213
 214                 if (unlikely(len > priv->common.rx_mtu)) {
 215                         if (net_ratelimit())
 216                                 dev_err(&priv->pdev->dev, "rx'd frame size "
 217                                         "exceeds length threshold.\n");
 218
 219                         len = priv->common.rx_mtu;
 220                 }
 221                 dma_addr = le32_to_cpu(desc->host_addr);
 222                 pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
 223                         priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
 224                 skb_put(skb, len);
 225
 226                 if (p54_rx(dev, skb)) {
 227                         pci_unmap_single(priv->pdev, dma_addr,
 228                                 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
 229                         rx_buf[i] = NULL;
 230                         desc->host_addr = cpu_to_le32(0);
 231                 } else {
 232                         skb_trim(skb, 0);
 233                         pci_dma_sync_single_for_device(priv->pdev, dma_addr,
 234                                 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
 235                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 236                 }
 237
 238                 i++;
 239                 i %= ring_limit;
 240         }
 241
 242         p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
 243 }
 244
 245 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
 246         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 247         struct sk_buff **tx_buf)
 248 {
 249         struct p54p_priv *priv = dev->priv;
 250         struct p54p_ring_control *ring_control = priv->ring_control;
 251         struct p54p_desc *desc;
 252         struct sk_buff *skb;
 253         u32 idx, i;
 254
 255         i = (*index) % ring_limit;
 256         (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
 257         idx %= ring_limit;
 258
 259         while (i != idx) {
 260                 desc = &ring[i];
 261
 262                 skb = tx_buf[i];
 263                 tx_buf[i] = NULL;
 264
 265                 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
 266                                  le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
 267
 268                 desc->host_addr = 0;
 269                 desc->device_addr = 0;
 270                 desc->len = 0;
 271                 desc->flags = 0;
 272
 273                 if (skb && FREE_AFTER_TX(skb))
 274                         p54_free_skb(dev, skb);
 275
 276                 i++;
 277                 i %= ring_limit;
 278         }
 279 }
 280
 281 static void p54p_tasklet(unsigned long dev_id)
 282 {
 283         struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
 284         struct p54p_priv *priv = dev->priv;
 285         struct p54p_ring_control *ring_control = priv->ring_control;
 286
 287         p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
 288                            ARRAY_SIZE(ring_control->tx_mgmt),
 289                            priv->tx_buf_mgmt);
 290
 291         p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
 292                            ARRAY_SIZE(ring_control->tx_data),
 293                            priv->tx_buf_data);
 294
 295         p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
 296                 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
 297
 298         p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
 299                 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
 300
 301         wmb();
 302         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 303 }
 304
 305 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
 306 {
 307         struct ieee80211_hw *dev = dev_id;
 308         struct p54p_priv *priv = dev->priv;
 309         __le32 reg;
 310
 311         reg = P54P_READ(int_ident);
 312         if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
 313                 goto out;
 314         }
 315         P54P_WRITE(int_ack, reg);
 316
 317         reg &= P54P_READ(int_enable);
 318
 319         if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
 320                 tasklet_schedule(&priv->tasklet);
 321         else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
 322                 complete(&priv->boot_comp);
 323
 324 out:
 325         return reg ? IRQ_HANDLED : IRQ_NONE;
 326 }
 327
 328 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
 329 {
 330         unsigned long flags;
 331         struct p54p_priv *priv = dev->priv;
 332         struct p54p_ring_control *ring_control = priv->ring_control;
 333         struct p54p_desc *desc;
 334         dma_addr_t mapping;
 335         u32 idx, i;
 336
 337         spin_lock_irqsave(&priv->lock, flags);
 338         idx = le32_to_cpu(ring_control->host_idx[1]);
 339         i = idx % ARRAY_SIZE(ring_control->tx_data);
 340
 341         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
 342                                  PCI_DMA_TODEVICE);
 343         if (pci_dma_mapping_error(priv->pdev, mapping)) {
 344                 spin_unlock_irqrestore(&priv->lock, flags);
 345                 p54_free_skb(dev, skb);
 346                 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
 347                 return ;
 348         }
 349         priv->tx_buf_data[i] = skb;
 350
 351         desc = &ring_control->tx_data[i];
 352         desc->host_addr = cpu_to_le32(mapping);
 353         desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
 354         desc->len = cpu_to_le16(skb->len);
 355         desc->flags = 0;
 356
 357         wmb();
 358         ring_control->host_idx[1] = cpu_to_le32(idx + 1);
 359         spin_unlock_irqrestore(&priv->lock, flags);
 360
 361         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 362         P54P_READ(dev_int);
 363 }
 364
 365 static void p54p_stop(struct ieee80211_hw *dev)
 366 {
 367         struct p54p_priv *priv = dev->priv;
 368         struct p54p_ring_control *ring_control = priv->ring_control;
 369         unsigned int i;
 370         struct p54p_desc *desc;
 371
 372         P54P_WRITE(int_enable, cpu_to_le32(0));
 373         P54P_READ(int_enable);
 374         udelay(10);
 375
 376         free_irq(priv->pdev->irq, dev);
 377
 378         tasklet_kill(&priv->tasklet);
 379
 380         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 381
 382         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
 383                 desc = &ring_control->rx_data[i];
 384                 if (desc->host_addr)
 385                         pci_unmap_single(priv->pdev,
 386                                          le32_to_cpu(desc->host_addr),
 387                                          priv->common.rx_mtu + 32,
 388                                          PCI_DMA_FROMDEVICE);
 389                 kfree_skb(priv->rx_buf_data[i]);
 390                 priv->rx_buf_data[i] = NULL;
 391         }
 392
 393         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
 394                 desc = &ring_control->rx_mgmt[i];
 395                 if (desc->host_addr)
 396                         pci_unmap_single(priv->pdev,
 397                                          le32_to_cpu(desc->host_addr),
 398                                          priv->common.rx_mtu + 32,
 399                                          PCI_DMA_FROMDEVICE);
 400                 kfree_skb(priv->rx_buf_mgmt[i]);
 401                 priv->rx_buf_mgmt[i] = NULL;
 402         }
 403
 404         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
 405                 desc = &ring_control->tx_data[i];
 406                 if (desc->host_addr)
 407                         pci_unmap_single(priv->pdev,
 408                                          le32_to_cpu(desc->host_addr),
 409                                          le16_to_cpu(desc->len),
 410                                          PCI_DMA_TODEVICE);
 411
 412                 p54_free_skb(dev, priv->tx_buf_data[i]);
 413                 priv->tx_buf_data[i] = NULL;
 414         }
 415
 416         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
 417                 desc = &ring_control->tx_mgmt[i];
 418                 if (desc->host_addr)
 419                         pci_unmap_single(priv->pdev,
 420                                          le32_to_cpu(desc->host_addr),
 421                                          le16_to_cpu(desc->len),
 422                                          PCI_DMA_TODEVICE);
 423
 424                 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
 425                 priv->tx_buf_mgmt[i] = NULL;
 426         }
 427
 428         memset(ring_control, 0, sizeof(*ring_control));
 429 }
 430
 431 static int p54p_open(struct ieee80211_hw *dev)
 432 {
 433         struct p54p_priv *priv = dev->priv;
 434         int err;
 435
 436         init_completion(&priv->boot_comp);
 437         err = request_irq(priv->pdev->irq, p54p_interrupt,
 438                           IRQF_SHARED, "p54pci", dev);
 439         if (err) {
 440                 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
 441                 return err;
 442         }
 443
 444         memset(priv->ring_control, 0, sizeof(*priv->ring_control));
 445         err = p54p_upload_firmware(dev);
 446         if (err) {
 447                 free_irq(priv->pdev->irq, dev);
 448                 return err;
 449         }
 450         priv->rx_idx_data = priv->tx_idx_data = 0;
 451         priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
 452
 453         p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
 454                 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
 455
 456         p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
 457                 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
 458
 459         P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
 460         P54P_READ(ring_control_base);
 461         wmb();
 462         udelay(10);
 463
 464         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
 465         P54P_READ(int_enable);
 466         wmb();
 467         udelay(10);
 468
 469         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 470         P54P_READ(dev_int);
 471
 472         if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
 473                 wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
 474                 p54p_stop(dev);
 475                 return -ETIMEDOUT;
 476         }
 477
 478         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
 479         P54P_READ(int_enable);
 480         wmb();
 481         udelay(10);
 482
 483         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 484         P54P_READ(dev_int);
 485         wmb();
 486         udelay(10);
 487
 488         return 0;
 489 }
 490
 491 static void p54p_firmware_step2(const struct firmware *fw,
 492                                 void *context)
 493 {
 494         struct p54p_priv *priv = context;
 495         struct ieee80211_hw *dev = priv->common.hw;
 496         struct pci_dev *pdev = priv->pdev;
 497         int err;
 498
 499         if (!fw) {
 500                 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
 501                 err = -ENOENT;
 502                 goto out;
 503         }
 504
 505         priv->firmware = fw;
 506
 507         err = p54p_open(dev);
 508         if (err)
 509                 goto out;
 510         err = p54_read_eeprom(dev);
 511         p54p_stop(dev);
 512         if (err)
 513                 goto out;
 514
 515         err = p54_register_common(dev, &pdev->dev);
 516         if (err)
 517                 goto out;
 518
 519 out:
 520
 521         complete(&priv->fw_loaded);
 522
 523         if (err) {
 524                 struct device *parent = pdev->dev.parent;
 525
 526                 if (parent)
 527                         device_lock(parent);
 528
 529                 /*
 530                  * This will indirectly result in a call to p54p_remove.
 531                  * Hence, we don't need to bother with freeing any
 532                  * allocated ressources at all.
 533                  */
 534                 device_release_driver(&pdev->dev);
 535
 536                 if (parent)
 537                         device_unlock(parent);
 538         }
 539
 540         pci_dev_put(pdev);
 541 }
 542
 543 static int p54p_probe(struct pci_dev *pdev,
 544                                 const struct pci_device_id *id)
 545 {
 546         struct p54p_priv *priv;
 547         struct ieee80211_hw *dev;
 548         unsigned long mem_addr, mem_len;
 549         int err;
 550
 551         pci_dev_get(pdev);
 552         err = pci_enable_device(pdev);
 553         if (err) {
 554                 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
 555                 return err;
 556         }
 557
 558         mem_addr = pci_resource_start(pdev, 0);
 559         mem_len = pci_resource_len(pdev, 0);
 560         if (mem_len < sizeof(struct p54p_csr)) {
 561                 dev_err(&pdev->dev, "Too short PCI resources\n");
 562                 err = -ENODEV;
 563                 goto err_disable_dev;
 564         }
 565
 566         err = pci_request_regions(pdev, "p54pci");
 567         if (err) {
 568                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
 569                 goto err_disable_dev;
 570         }
 571
 572         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 573         if (!err)
 574                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 575         if (err) {
 576                 dev_err(&pdev->dev, "No suitable DMA available\n");
 577                 goto err_free_reg;
 578         }
 579
 580         pci_set_master(pdev);
 581         pci_try_set_mwi(pdev);
 582
 583         pci_write_config_byte(pdev, 0x40, 0);
 584         pci_write_config_byte(pdev, 0x41, 0);
 585
 586         dev = p54_init_common(sizeof(*priv));
 587         if (!dev) {
 588                 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
 589                 err = -ENOMEM;
 590                 goto err_free_reg;
 591         }
 592
 593         priv = dev->priv;
 594         priv->pdev = pdev;
 595
 596         init_completion(&priv->fw_loaded);
 597         SET_IEEE80211_DEV(dev, &pdev->dev);
 598         pci_set_drvdata(pdev, dev);
 599
 600         priv->map = ioremap(mem_addr, mem_len);
 601         if (!priv->map) {
 602                 dev_err(&pdev->dev, "Cannot map device memory\n");
 603                 err = -ENOMEM;
 604                 goto err_free_dev;
 605         }
 606
 607         priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
 608                                                   &priv->ring_control_dma);
 609         if (!priv->ring_control) {
 610                 dev_err(&pdev->dev, "Cannot allocate rings\n");
 611                 err = -ENOMEM;
 612                 goto err_iounmap;
 613         }
 614         priv->common.open = p54p_open;
 615         priv->common.stop = p54p_stop;
 616         priv->common.tx = p54p_tx;
 617
 618         spin_lock_init(&priv->lock);
 619         tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
 620
 621         err = request_firmware_nowait(THIS_MODULE, 1, "isl3886pci",
 622                                       &priv->pdev->dev, GFP_KERNEL,
 623                                       priv, p54p_firmware_step2);
 624         if (!err)
 625                 return 0;
 626
 627         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 628                             priv->ring_control, priv->ring_control_dma);
 629
 630  err_iounmap:
 631         iounmap(priv->map);
 632
 633  err_free_dev:
 634         pci_set_drvdata(pdev, NULL);
 635         p54_free_common(dev);
 636
 637  err_free_reg:
 638         pci_release_regions(pdev);
 639  err_disable_dev:
 640         pci_disable_device(pdev);
 641         pci_dev_put(pdev);
 642         return err;
 643 }
 644
 645 static void p54p_remove(struct pci_dev *pdev)
 646 {
 647         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 648         struct p54p_priv *priv;
 649
 650         if (!dev)
 651                 return;
 652
 653         priv = dev->priv;
 654         wait_for_completion(&priv->fw_loaded);
 655         p54_unregister_common(dev);
 656         release_firmware(priv->firmware);
 657         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 658                             priv->ring_control, priv->ring_control_dma);
 659         iounmap(priv->map);
 660         pci_release_regions(pdev);
 661         pci_disable_device(pdev);
 662         p54_free_common(dev);
 663 }
 664
 665 #ifdef CONFIG_PM_SLEEP
 666 static int p54p_suspend(struct device *device)
 667 {
 668         struct pci_dev *pdev = to_pci_dev(device);
 669
 670         pci_save_state(pdev);
 671         pci_set_power_state(pdev, PCI_D3hot);
 672         pci_disable_device(pdev);
 673         return 0;
 674 }
 675
 676 static int p54p_resume(struct device *device)
 677 {
 678         struct pci_dev *pdev = to_pci_dev(device);
 679         int err;
 680
 681         err = pci_reenable_device(pdev);
 682         if (err)
 683                 return err;
 684         return pci_set_power_state(pdev, PCI_D0);
 685 }
 686
 687 static SIMPLE_DEV_PM_OPS(p54pci_pm_ops, p54p_suspend, p54p_resume);
 688
 689 #define P54P_PM_OPS (&p54pci_pm_ops)
 690 #else
 691 #define P54P_PM_OPS (NULL)
 692 #endif /* CONFIG_PM_SLEEP */
 693
 694 static struct pci_driver p54p_driver = {
 695         .name           = "p54pci",
 696         .id_table       = p54p_table,
 697         .probe          = p54p_probe,
 698         .remove         = p54p_remove,
 699         .driver.pm      = P54P_PM_OPS,
 700 };
 701
 702 module_pci_driver(p54p_driver);